Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.
Marsden, G C; Krishnamoorthy, A V; Esener, S C; Lee, S H
The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.
Sturesson, Fredrik; Habinc, Sandi; Gaisler, Jiri
The GR712RC System-on-Chip (SoC) is a dual core LEON3FT system suitable for advanced high reliability space avionics. Fault tolerance features from Aeroflex Gaisler’s GRLIB IP library and an implementation using Ramon Chips RadSafe cell library enables superior radiation hardness.The GR712RC device has been designed to provide high processing power by including two LEON3FT 32- bit SPARC V8 processors, each with its own high- performance IEEE754 compliant floating-point-unit and SPARC reference memory management unit.This high processing power is combined with a large number of serial interfaces, ranging from high-speed links for data transfers to low-speed control buses for commanding and status acquisition.
Jia Min; Chen Huimin; Yuan Yuhua
This paper proposes a new multi-channel Medium Access Control (MAC) protocol named as Dual Reservation Code Division Multiple Access (CDMA) based MAC protocol with Power Control (DRCPC). The code channel is divided into common channel, broadcast channel and several data channels. And dynamic power control mechanism is implemented to reduce near-far interference. Compared with IEEE 802.11 Distributed Coordination Function (DCF) protocol, the results show that the proposed mechanism improves the average throughput and limits the transmission delay efficiently.
Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.
The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.
Shin, Hyun Kook; Nam, Sang Ku; Sohn, Se Do; Chang, Hoon Seon
The advanced digital reactor protection system (ADRPS) with diverse dual processors has been developed to prevent common-mode failure (CMF). The principle of diversity is applied to both hardware design and software design. For hardware diversity, two different types of CPUs are used for the bistable processor and local coincidence logic (LCL) processor. The Versa Module Eurocard-based single board computers are used for the CPU hardware platforms. The QNX operating system and the VxWorks operating system were selected for software diversity. Functional diversity is also applied to the input and output modules, and to the algorithm in the bistable processors and LCL processors. The characteristics of the newly developed digital protection system are described together with the preventive capability against CMF. Also, system reliability analysis is discussed. The evaluation results show that the ADRPS has a good preventive capability against the CMF and is a highly reliable reactor protection system
Balazs, G; Nowak, A; CERN. Geneva. IT Department
In this paper we compare a system based on an Intel Atom N330 low-power processor to a modern Intel Xeon® dual-socket server using CERN IT’s standard criteria for comparing price-performance and performance per watt. The Xeon server corresponds to what is typically acquired as servers in the LHC Computing Grid. The comparisons used public pricing information from November 2008. After the introduction in section 1, section 2 describes the hardware and software setup. In section 3 we describe the power measurements we did and in section 4 we discuss the throughput performance results. In section 5 we summarize our initial conclusions. We then go on to describe our long term vision and possible future scenarios for using such low-power processors, and finally we list interesting development directions.
Son, Ki Chang; Shin, Hyun Kook; Lee, Nam Hoon; Baek, Seung Min; Kim, Hang Bae
The Advanced Digital Reactor Protection System (ADRPS) with diverse dual processors is being developed by the National Research Lab of KOPEC for ADRPS development. One of the ADRPS goals is to develop digital Plant Protection System (PPS) free of Common Mode Failure (CMF). To prevent CMF, the principle of diversity is applied to both hardware design and software design. For the hardware diversity, two different types of CPUs are used for Bistable Processor and Local Coincidence Logic Processor. The VME based Single Board Computers (SBC) are used for the CPU hardware platforms. The QNX Operating System (OS) and the VxWorks OS are used for software diversity. Rigorous Software Verification and Validation (V and V) is also required to prevent CMF. In this paper, software V and V methodology for the ADRPS is described to enhance the ADRPS software reliability and to assure high quality of the ADRPS software
H. Dong; R. Flood; C. Hovater; J. Musson
A Dual Digital Signal Processing VME Board is being developed for the CEBAF Beam Current Monitor system at Jefferson Lab. It is a versatile general-purpose digital signal processing board using an open architecture, which allows for adaptation to various applications. The base design uses two independent Texas Instrument (TI) TMS320C6711, which are 900 MFLOPS floating-point digital signal processors (DSP). Applications that require a fixed point DSP can be implemented by replacing the baseline DSP with the pin-for-pin compatible TMS320C6211. Both parallel and serial protocols have been implemented for communicating with off board devices. The initial implementation makes use of TI Multi-channel Serial protocol and VME bus protocol. Other communication protocols can be implemented by reprogramming the FPGA. Each DSP is equipped with FLASH PROM and SDRAM for program and data storage. Additionally, each DSP has 16 bits of digital I/O, two digital analog converters, and two analog to digital converters. Dual 160 pins mezzanine connectors provide expansion capability without design modifications. The mezzanine interface conforms to the TI Expansion Daughter Card Interface standard. The design can be manufactured with a reduced chip set without redesigning the printed circuit board. For example, it can be implemented as a single-channel DSP with no analog I/O. The board supports JTAG 1149 boundary scan to facilitate testing, debugging, and programming. It is fully programmable using software development tools such as TI Code Composer Studio and a JTAG emulator such as Spectrum Digital DS510PP-PLUS. Using these tools allows one program the flash memory and FPGA through the JTAG ports, thus eliminating the need for a separate ROM/FPGA programmer. This work supported by U.S. DOE Contract No. DE-AC05-84ER40150
A new generation with a reworked motherboard is launched on 2001 with however the same Graphite box. It also included a processor speed-bump, and brought the DVD-R "SuperDrive" to the mid-level model. The Quicksilver PowerMac was available in three configurations: The 733 MHz model, with 128 MB of RAM, a 40 GB hard drive, and a CD-RW drive, was 1,699 dollars, the 867 MHz configuration, with 128 MB of RAM, a 60 GB hard drive and a DVD-R drive, was 2,499 dollars, and the high-end dual-800 MHz model, with 256 MB of RAM, an 80 GB hard drive and a DVD-R drive, was 3,499 dollars. The 733 MHz model is the first personal computer to have a DVD burner, named SuperDrive at Apple. The design was updated on 2002 with 800 MHz, 933 MHz and dual 1 GHz configurations, becoming the first Mac to reach 1 GHz.
This essential guide answers all your questions on using a Macintosh computer, whether you?re unpacking your very first Mac after switching from a PC or upgrading from an older Mac. You?ll walk through all pre-installed Mac applications, including using Mac OS X, browsing the Web using Safari, downloading music from the iTunes store, troubleshooting Mac-specific problems, organizing photos in iPhoto, organizing calendars in iCal, editing digital video in iMovie, and more.
This essay investigates the ways dance narratives are constructed and aims to reconfirm the significance of dance narratives in the creation of meanings within dance practices. It draws on key concepts in narratology and psychoanalysis. These two critical perspectives are applied to the analysis of the narrative in Kenneth MacMillan's 1991 one-act…
Even the most devoted Mac OS X user may need to use Windows XP, or may just be curious about XP and its applications. This Short Cut is a concise guide for OS X users who need to quickly get comfortable and become productive with Windows XP basics on their Macs. It covers: Security Networking ApplicationsMac users can easily install and use Windows thanks to Boot Camp and Parallels Desktop for Mac. Boot Camp lets an Intel-based Mac install and boot Windows XP on its own hard drive partition. Parallels Desktop for Mac uses virtualization technology to run Windows XP (or other operating systems
Baig, Edward C
Get the most out of your Mac with this comprehensive guide Macs For Dummies, 13th Edition is the ultimate guide to your Mac, fully updated to include information about the latest updates. The book walks you through troubleshooting, syncing mobile devices, integrating Windows, and more, so you can take advantage of everything Macs have to offer. Whether you're a new user, a recent convert, or you just want to get the most out of your Mac, this book puts all the information you need in one place. Discover what makes Macs superior computing machines. Learn the basics, from mastering the Dock and
... sweat, and saliva red-orange (may stain contact lenses); can interfere with birth control pills. Many drug interactions. CAN MAC BE PREVENTED? The bacteria that cause MAC are very common. It is ...
Craiger, Philip; Burke, Paul
This paper describes procedures for conducting forensic examinations of Apple Macs running Mac OS X. The target disk mode is used to create a forensic duplicate of a Mac hard drive and preview it. Procedures are discussed for recovering evidence from allocated space, unallocated space, slack space and virtual memory. Furthermore, procedures are described for recovering trace evidence from Mac OS X default email, web browser and instant messaging applications, as well as evidence pertaining to commands executed from a terminal.
IT departments everywhere will be integrating Macs and Mac OS X into their IT infrastructure and this book will tell them how to do it. It will serve as an authoritative, useful and frequently referenced book on Mac OS X administration.
Edge, Charles; Hunter, Beau
Charles Edge, Zack Smith, and Beau Hunter provide detailed explanations of the technology required for large-scale Mac OS X deployments and show you how to integrate it with other operating systems and applications. Enterprise Mac Administrator's Guide addresses the growing size and spread of Mac OS X deployments in corporations and institutions worldwide. In some cases, this is due to the growth of traditional Mac environments, but for the most part it has to do with "switcher" campaigns, where Windows and/or Linux environments are migrating to Mac OS X. However, there is a steep cu
Your essential, no-holds-barred guide to Mac security threats and solutions. Myth number one: Macs are safer than PCs. Not really, says author Joe Kissell, named one of MacTech's "25 Most Influential People" in the Mac community for 2008. In this timely guide, he not only takes you beyond the myths, he also delves into the nitty-gritty of each potential threat, helping you weigh the pros and cons of the solutions you might choose. Learn to measure risk versus inconvenience, make informed decisions, and protect your Mac computers, your privacy, and your data with this essential guide.
Tips and techniques for forward-thinking MacBook Pro users Now that you have a MacBook Pro, you need just one more accessory, your very own copy of MacBook Pro Portable Genius, Third Edition. This handy, compact book lets you in on a wealth of tips and tricks, so you get the very most out of Apple's very popular notebook. Discover the latest on the most recent release of iLife, get the skinny on the new Intel Core i7 and i5 processors in the Pro, see how to go wireless in a smart way, and much more. The book is easy to navigate, doesn't skimp on the essentials, and helps you save time and avoi
Bridge the gap between using a Mac at home and at the office. Now that you love your Mac at home, you want to use one at the office without missing a beat of productivity or professionalism. This unique guide shows you how. You'll find best Mac business practices for handling word processing, spreadsheet and presentation creation, task and project management, and graphics. The book also explores topics such as hardware maintenance, how to synchronize with multiple computers, data backup, and communication with Windows networks.: Covers the nuts and bolts of using a Mac at work, including sync
Edge, Stephen Charles; Hunter, Beau; Sullivan, Gene; LeBlanc, Dee-Ann
A common misconception in the Mac community is that Mac's operating system is more secure than others. While this might be true in certain cases, security on the Mac is still a crucial issue. When sharing is enabled or remote control applications are installed, Mac OS X faces a variety of security threats. Enterprise Mac Security: Mac OS X Snow Leopard is a definitive, expert-driven update of the popular, slash-dotted first edition and was written in part as a companion to the SANS Institute course for Mac OS X. It contains detailed Mac OS X security information, and walkthroughs on securing s
Many systems administrators on the Mac need a way to manage machine configuration after initial setup and deployment. Apple's Managed Preferences system (also known as MCX) is under-documented, often misunderstood, and sometimes outright unknown by sys admins. MCX is usually deployed in conjunction with an OS X server, but it can also be used in Windows environments or where no dedicated server exists at all. Enterprise Mac Managed Preferences is the definitive guide to Apple's Managed Client technology. With this book, you'll get the following: * An example-driven guide to Mac OS X Managed Pr
MacInnes, W J; Taylor, T L
A real-time, object-oriented solution for displaying stimuli on Windows 95/98, MacOS and Linux platforms is presented. The program, written in C++, utilizes a special-purpose window class (GLWindow), OpenGL, and 32-bit graphics acceleration; it avoids display timing uncertainty by substituting the new window class for the default window code for each system. We report the outcome of tests for real-time capability across PC and Mac platforms running a variety of operating systems. The test program, which can be used as a shell for programming real-time experiments and testing specific processors, is available at http://www.cs.dal.ca/~macinnwj. We propose to provide researchers with a sense of the usefulness of our program, highlight the ability of many multitasking environments to achieve real time, as well as caution users about systems that may not achieve real time, even under optimal conditions.
The MAC detector at PEP features a large solid-angle electromagnetic/hadronic calorimeter system, augmented by magnetic charged-particle tracking, muon analysis and scintillator triggering. Its implementation in the context of electron-positron annihilation physics is described, with emphasis on the utilization of calorimetry
CPMGIKAlBGE-340/2003-05. Resonance - January 2005. Licenced to post WPP No.6 RT Nagar Postoffice. Florence Jessie Mac Williams. (1917 - 1990). Registered with Registrar of Newspapers in India vide Regn. No. 66273/96. ISSN 0971-8044. Price per copy: Rs 40.
The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)
If you want to get the very most out of your iMac, put this savvy Portable Genius guide to work. Want to make the most of the new Magic Mouse and the latest iLife apps? Set up a wireless network using your iMac's AirPort card? Watch television on your iMac, or show iMac videos and movies on your television? You'll find cool and useful Genius tips, full-color screenshots, and pages of easy-to-access shortcuts and tools that will save you time and let you enjoy your iMac to the max.
Chambers , Mark L
Make friends with your MacBook the fun and easy way! Ultra-light, ultra-fast, and ultra-powerful, the MacBook is the coolest laptop in town, and longtime Mac guru Mark L. Chambers is just the guy to help you get to know your MacBook in no time. Take a closer look at the latest features, get the lowdown on OS X, unleash your creative forces with iLife, take care of business with the iWork applications, and sync it all with iCloud with the expert advice in this bestselling MacBook guide. Whether this is your first MacBook or your first laptop, period, you''ll learn to navigate the Mac desktop, c
Baig, Edward C
The fun and easy way to make the most of your wonderful Mac. Simply Mac-nificent — all the cool things your Mac can do! This handy guide helps you figure out the nuts and bolts of your Mac. Navigate the Mac desktop, use the Safari Web browser to surf the Internet, e-mail photos to friends and family, create and print documents, rip audio CDs, and more. The fun begins right here!. Open the book and find: How to set up and configure your Mac; Tips for getting around on the Mac desktop; Steps for setting up an e-mail account and browsing the Internet; Details about the free programs that come wit
The most up-to-date coverage on the latest iMac advice, tools, and shortcuts Cool and useful tips, full-color screenshots, and savvy advice show you how to get the most out of your iMac. Fully updated to cover the iMac's latest features and capabilities, this guide is packed with indispensible information on iLife '09 and Mac OS X Snow Leopard, and shows you how to customize your iMac in a way that it will work best for you.Explores all the bells and whistles of the iMac, including the new Magic Mouse, iLife apps such as iPhoto and iMovie, and Mac OS X Snow LeopardShows yo
Simon, Tyler; McGalliard, James
Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.
Gluesing-Luerssen, Heide; Schneider, Gert
A MacWilliams Identity for convolutional codes will be established. It makes use of the weight adjacency matrices of the code and its dual, based on state space realizations (the controller canonical form) of the codes in question. The MacWilliams Identity applies to various notions of duality appearing in the literature on convolutional coding theory.
Gluesing-Luerssen, Heide; Schneider, Gert
A MacWilliams Identity for convolutional codes will be established. It makes use of the weight adjacency matrices of the code and its dual, based on state space realizations (the controller canonical form) of the codes in question. The MacWilliams Identity applies to various notions of duality
Chambers, Mark L
Do it all with your iMac and this bestselling For Dummies guide! You're still a little giddy from finally scoring your new iMac, and you can't wait to get started. Even if you're already in love with your iMac, it helps to have a little guidance to really get the most out of this ultimate all-in-one computer. This updated edition of iMac For Dummies is the ideal way to learn the iMac fundamentals from setting up and personalizing your machine to importing files, making FaceTime video calls, surfing the web, using your favorite programs and apps, and everything in between. Trusted Mac guru Mark
Zhu, Zengxi; Lin, Rujian; Chen, Jian; Ye, Jiajun; Chen, Xinqiao
Ethernet passive optical network (EPON), which represents the convergence of low-cost, high-bandwidth and supporting multiple services, appears to be one of the best candidates for the next-generation access network. The work of standardizing EPON as a solution for access network is still underway in the IEEE802.3ah Ethernet in the first mile (EFM) task force. The final release is expected in 2004. Up to now, there has been no standard application specific integrated circuit (ASIC) chip available which fulfills the functions of media access control (MAC) layer of EPON. The MAC layer in EPON system has many functions, such as point-to-point emulation (P2PE), Ethernet MAC functionality, multi-point control protocol (MPCP), network operation, administration and maintenance (OAM) and link security. To implement those functions mentioned above, an embedded real-time operating system (RTOS) and a flexible programmable logic device (PLD) with an embedded processor are used. The software and hardware functions in MAC layer are realized through programming embedded microprocessor and field programmable gate array(FPGA). Finally, some experimental results are given in this paper. The method stated here can provide a valuable reference for developing EPON MAC layer ASIC.
Microsoft Excel 2011 for Mac OS X is a powerful application, but many of its most impressive features can be difficult to find. Learn Excel 2011 for Mac by Guy Hart-Davis is a practical, hands-on approach to learning all of the details of Excel 2011 in order to get work done efficiently on Mac OS X. From using formulas and functions to creating databases, from analyzing data to automating tasks, you'll learn everything you need to know to put this powerful application to use for a variety of tasks. What you'll learn * The secrets of the Excel for Mac interface! * How to create effective workbo
Schad, M.; Danesi, C.; Ricci, R.; Galluzzi, S.; Coviello, G.
Mac Leod's syndrome is a rarely diagnosed disease; that is why an accurate differential diagnosis is needed by means of radiological imaging. This paper is aimed at discussing the differential diagnosis, with a special emphasis on the pathogenesis of the syndrome. The phenomenon of air trapping in absence of central bronchial lesions is a typical radiographic finding. Chest X-ray is performed in both inspiration and expiration. Posterior oblique tomography at 55 grade centigrade of the effected side is also performed. Diffuse bronchiolitis obliterans in infancy or early childhood ia widely accepted pathogenetic pattern. Pulmonary hypoventilation causes vasoconstriction and underdevelopment of pulmonary vessels, that are reduced in caliber. Differential diagnosis includes all the diseases resulting in pulmonary hyperlucency, i.e. pulmonary and pleural alterations, and skeletal anomalies
Nykyään yhä useampi harkitsee erilaisista syistä käyttöjärjestelmän vaihtamista tutusta Windowsista johonkin muuhun käyttöjärjestelmään. Applen Macintosh-tietokoneiden mukana tuleva Mac OS X -käyttöjärjestelmä on hyvä vaihtoehto Windowsille. Ihmiset siirtyvät siihen mm. tietoturvaseikkojen, luotettavuuden, ohjelmiston sekä Applen koneiden ja käyttöjärjestelmän ulkomuodon takia. Microsoftin tuotteista ei myöskään tarvitse luopua kokonaan, sillä monista tutuista Microsoftin ohjelmista (esim. Mi...
Buzek, V.; Ziman, M.; Hillery, M.
We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright , Wiley Periodicals, Inc.)
Chambers, Mark L
The bestselling guide to the ultimate all-in-one computer—now updated and revised throughout! If you're looking for speed, performance, and power, the iMac is the ultimate all-in-one computer. From its superior performance, powerful operating system, and amazing applications, the iMac is one awesome machine, and the fun, friendly, and approachable style of iMac For Dummies is an ideal way to get started with the basics. You'll learn the fundamentals of the iMac including setting up and customizing your iMac and the software that comes with it, importing files from your old computer, send
Computer Security Team
Still believe your Mac is secure because Microsoft PCs fall prey to viruses and worms but Macs don’t? Time to wake up! This year has seen the first major compromise of Macs worldwide*. How is yours doing? The “Flashback” Trojan is affecting Apple’s own variant of Java and compromises Macs via so-called drive-by infections, i.e. when you visit an appropriately prepared (infected!) website - and this might not necessarily be a site with questionable contents, but could well be a popular, reputable one. Security Companies worldwide have been monitoring this particular Trojan for a while and have estimated that more than half a million Macs were compromised. Connected to a few central command and control servers, the compromised Macs were then supporting the malicious activity of the bad guys! Fortunately, the security companies have now been able to take over those command and control servers and stop their destructive drive. So, Mac users, face the f...
Davis, T Gene
Learn the guidelines of integrating Java with native Mac OS X applications with this Devloper Reference book. Java is used to create nearly every type of application that exists and is one of the most required skills of employers seeking computer programmers. Java code and its libraries can be integrated with Mac OS X features, and this book shows you how to do just that. You'll learn to write Java programs on OS X and you'll even discover how to integrate them with the Cocoa APIs.: Shows how Java programs can be integrated with any Mac OS X feature, such as NSView widgets or screen savers; Re
Want to learn how to program on your Mac? Not sure where to begin? Best-selling author Wallace Wang will explain how to get started with Cocoa, Objective-C, and Xcode. Whether you are an experienced Windows coder moving to the Mac, or you are completely new to programming, you'll see how the basic design of a Mac OS X program works, how Objective-C differs from other languages you may have used, and how to use the Xcode development environment. Most importantly, you'll learn how to use elements of the Cocoa framework to create windows, store data, and respond to users in your own Mac programs.
A devoted family man and churchgoer, Alistair MacDonald was a meticulous vet with a great sense of humour. Having served in the RAF during the Second World War, he had plenty of stories to tell. British Veterinary Association.
Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...
Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi
In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.
Hut, Rolf; van de Giesen, Nick; Larson, Martha
Crowdsourcing has become popular over the past years, also for scientific endeavors. There are many Citizen Science projects and crowdfunding platforms, such as Kickstarter, that are make helpful contributions to moving environmental science forward. An interesting underused source of useful crowd-derived contributions to research is the website Fiverr.com. On this platform, thousands of people, acting as small-scale freelance contractors, offer their skills in the form of services. The platform offers a chance for people to take a hobby, skill, or pastime and make it something more by reaching out to a wider audience and by receiving a payment in return for services. As is typical of other crowdsourcing platforms, the tasks are small and usually self contained. As the name Fiverr suggests, offers start at US5 to provide a particular service. Services offered range from graphic design, to messages sung or spoken with various styles or accents, to complete apps for Android or iPhone. Skill providers on the platform can accept a range of variation of definition in the tasks, some can be described in general terms, for others it is more appropriate to provide examples. Fiverr provides a central location for those offering skills and those needing services to find each other, it makes it possible to communicate and exchange files, to make payments, and it provides support for resolving disputes. In all cases, it is important to keep expectations aligned with the nature of the platform: quality can and will vary. Ultimately, the critical contribution of Fiverr is not to replace professional services or otherwise save money, but rather to provide access to a large group of people with specialized skills who are able to make a contribution on short notice. In the context of this session, it can be considered a pool of people with MacGyver skills lying in wait of a MacGyyer task to attack. There are many ways in which Fiverr tasks, which are called 'gigs', can be useful in
Like the MacBook itself, Teach Yourself VISUALLY MacBook, Second Edition is designed to be visually appealing, while providing excellent functionality at the same time. By using this book, MacBook users will be empowered to do everyday tasks quickly and easily. From such basic steps as powering on or shutting down the MacBook, working on the Mac desktop with the Dashboard and its widgets to running Windows applications, Teach Yourself VISUALLY MacBook, Second Edition covers all the vital information and provides the help and support a reader needs—in many ways it's like having a Mac Genius at
Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.
The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed
Tämän opinnäytetyön tavoitteena on luoda kattava kokonaiskuva Mac OS X -käyttöjärjestelmän sisäänrakennetuista tietoturvaratkaisuista ja selvittää miten tietoturvaratkaisut toteuttavat tietoturvan kolmea perustavoitetta eli luottamuksellisuutta, eheyttä ja saatavuutta. Työn kohderyhmäksi on valittu edistyneemmät tietokoneenkäyttäjät, joilla ei ole aikaisempaa Mac-kokemusta. Teoriaosuudessa syvennytään aluksi Apple-yhtiöön sekä Mac OS X -järjestelmän teknisiin ominaisuuksiin. Osuuden pääta...
Zhao, Jumin; Li, Yikun; Li, Dengao; Lin, Xiaojie
This paper proposes an innovative MAC protocol called I-MAC. Protocol for wireless sensor networks, which combines the advantages of collision tolerance and collision cancellation. The protocol increases the number of antenna in wireless sensor nodes. The purpose is to monitor the occurrence of packet collisions by increasing the number of antenna in real time. The built-in identity structure is used in the frame structure in order to help the sending node to identify the location of the receiving node after a data packet collision is detected. Packets can be recovered from where the conflict occurred. In this way, we can monitor the conflict for a fixed period of time. It can improve the channel utilisation through changing the transmission probability of collision nodes and solve the problem of hidden terminal through collision feedback mechanism. We have evaluated our protocol. Our results show that the throughput of I-MAC is 5 percentage points higher than that of carrier sense multiple access/collision notification. The network utilisation of I-MAC is more than 92%.
... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...
Kunz, P.F.; Gravina, M.; Oxoby, G.
The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future
The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...
An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.
An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed
Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)
A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.
Undervisningsforløbet Mr. MacDonald’s suitcase beskriver læringsmålstyret undervisning i faget engelsk i 1. klasse, hvor der arbejdes med kompetenceområdet mundtlig kommunikation. Undervisningsforløbet er bygget op omkring en engelsk tøjdukke, der besøger klassen og fortæller små historier...
Rohani, A.; Kerkhoff, Hans G.
The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of
Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department
In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...
Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.
Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/
The perfect guide to help administrators set up Apple's Mac OS X Lion Server With the overwhelming popularity of the iPhone and iPad, more Macs are appearing in corporate settings. The newest version of Mac Server is the ideal way to administer a Mac network. This friendly guide explains to both Windows and Mac administrators how to set up and configure the server, including services such as iCal Server, Podcast Producer, Wiki Server, Spotlight Server, iChat Server, File Sharing, Mail Services, and support for iPhone and iPad. It explains how to secure, administer, and troubleshoot the networ
Is Windows giving you pause? Ready to make the leap to the Mac instead? There has never been a better time to switch from Windows to Mac, and this incomparable guide will help you make a smooth transition. New York Times columnist and Missing Manuals creator David Pogue gets you past three challenges: transferring your stuff, assembling Mac programs so you can do what you did with Windows, and learning your way around Mac OS X. Learning to use a Mac is not a piece of cake, but once you do, the rewards are oh-so-much better. No viruses, worms, or spyware. No questionable firewalls, inefficien
Thinking of making the switch from your PC to a Mac? Congratulations! You're in for a great, virus-free ride. And Switching to Mac For Dummies makes it smoother than you ever imagined. From buying the Mac that's right for you to transferring your files to breaking your old Windows habits and learning to do things the (much easier) Mac way, it makes the whole process practically effortless. Whether you've been using Windows XP, Vista, or even Linux, you'll find simple, straightforward ways to make your transition go smoothly. That will leave you plenty of time to get familiar with Mac'
This SpringerBrief presents recent advances in the cognitive MAC designs for opportunistic spectrum access (OSA) networks. It covers the basic MAC functionalities and MAC enhancements of IEEE 802.11. Later chapters discuss the existing MAC protocols for OSA and classify them based on characteristic features. The authors provide new research in adaptive carrier sensing-based MAC designs tailored for OSA, which optimize spectrum utilization and ensure a peaceful coexistence of licensed and unlicensed systems. Analytically devised via optimization and game-theoretic approaches, these adaptive M
Pierfederici, F.; Pirzkal, N.; Hook, R. N.
Mac OS X is the new Unix based version of the Macintosh operating system. It combines a high performance DisplayPDF user interface with a standard BSD UNIX subsystem and provides users with simultaneous access to a broad range of applications which were not previously available on a single system such as Microsoft Office and Adobe Photoshop, as well as legacy X11-based scientific tools and packages like IRAF, SuperMongo, MIDAS, etc. The combination of a modern GUI layered on top of a familiar UNIX environment paves the way for new, more flexible and powerful astronomical tools to be developed while assuring compatibility with already existing, older programs. In this paper, we outline the strengths of the Mac OS X platform in a scientific environment, astronomy in particular, and point to the numerous astronomical software packages available for this platform; most notably the Scisoft collection which we have compiled.
Full Text Available Dual codes are defined with respect to non-degenerate sesquilinear or bilinear forms over a finite Frobenius ring. These dual codes have the properties one expects from a dual code: they satisfy a double-dual property, they have cardinality complementary to that of the primal code, and they satisfy the MacWilliams identities for the Hamming weight.
The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.
Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...
Michel, Mathieu; Quoitin, Bruno
This paper try to better understand the performance of ContikiMAC compared to X-MAC. ContikiMAC achieves a transmission by repeatedly transmitting a data packet until the reception of an ACK from the destination. While X-MAC uses a stream of small size strobes to advertise the destination of the incoming transmission. A priori, X-MAC is then less bandwidth consumptive. To better understand the efficiency of ContikiMAC, despite an intuitively more consumptive transmitting procedure, we have co...
In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The
The perfect how-to guide for visual learners Apple?s Mac Mini packs a powerful punch is in a small package, including both HDMI and Thunderbolt ports plus the acclaimed OS X. But if you want to get the very most from all this power and versatility, be sure to get this practical visual guide. With full-color, step-by-step instructions as well as screenshots and illustrations on every page, it clearly shows you how to accomplish tasks rather than burying you in pages of text. Discover helpful visuals and how-tos on the OS, hardware specs, Launchpad, the App Store, multimedia capabilities (such
If you're one of the many Unix developers drawn to Mac OS X for its Unix core, you'll find yourself in surprisingly unfamiliar territory. Unix and Mac OS X are kissing cousins, but there are enough pitfalls and minefields in going from one to another that even a Unix guru can stumble, and most guides to Mac OS X are written for Mac aficionados. For a Unix developer, approaching Tiger from the Mac side is a bit like learning Russian by reading the Russian side of a Russian-English dictionary. Fortunately, O'Reilly has been the Unix authority for over 25 years, and in Mac OS X Tiger for Unix Gee
Suzuki, Kazuyoshi; Fujiwara, Eiji
M-spotty byte error control codes are very effective for correcting/detecting errors in semiconductor memory systems that employ recent high-density RAM chips with wide I/O data (e.g., 8, 16, or 32bits). In this case, the width of the I/O data is one byte. A spotty byte error is defined as random t-bit errors within a byte of length b bits, where 1 le t ≤ b. Then, an error is called an m-spotty byte error if at least one spotty byte error is present in a byte. M-spotty byte error control codes are characterized by the m-spotty distance, which includes the Hamming distance as a special case for t =1 or t = b. The MacWilliams identity provides the relationship between the weight distribution of a code and that of its dual code. The present paper presents the MacWilliams identity for the m-spotty weight enumerator of m-spotty byte error control codes. In addition, the present paper clarifies that the indicated identity includes the MacWilliams identity for the Hamming weight enumerator as a special case.
This ebook explains a little bit of everything; in fact, it's The Mac OS X (and then some) Lexicon because it's never just you and your Mac. It's you and your Mac and the Web, and your email, and that article you just read that threw 17 new acronyms at you or assumed that you knew all sorts of networking terms. Or it's you and your Mac and Finder features you've never touched, such as burn folders, smart folders, or proxy icons, and that mysterious Services submenu. This book is a great guide for Macintosh users everywhere who have trouble keeping up with the latest jargon, fo
This book provides a literature review of various wireless MAC protocols and techniques for achieving real-time and reliable communications in the context of cyber-physical systems (CPS). The evaluation analysis of IEEE 802.15.4 for CPS therein will give insights into configuration and optimization of critical design parameters of MAC protocols. In addition, this book also presents the design and evaluation of an adaptive MAC protocol for medical CPS, which exemplifies how to facilitate real-time and reliable communications in CPS by exploiting IEEE 802.15.4 based MAC protocols. This book wil
Your all-in-one guide to unleashing your Mac's full potential It's a Mac world out there. But if you haven't read the instruction manual, you may be neglecting some of your computer's coolest features. Turn to Macs All-in-One For Dummies' jam-packed guide to access the incredible tools within your computer. With this fully updated reference, you will learn how to use Launchpad and Mission Control; protect your Mac; back up and restore data with Time Machine; sync across devices in iCloud; import, organize, and share photos; direct in iMovie; compose in GarageBand; and so much more. The possi
.... This research recounts MacArthur's personality development from childhood, investigates his last military campaign, and, finally, applies the diagnosis of narcissistic personality disorder to the assembled data...
O'Sullivan, George A.; O'Sullivan, Joseph A.
In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.
Knudsen, Lars Ramkilde; Mitchell, C.J.
Forgery and key-recovery attacks are described on the 3gpp-MAC scheme, proposed for inclusion in the 3gpp specification. Three main classes of attack are given, all of which operate whether or not truncation is applied to the MAC value. Attacks in the first class use a large number of 'chosen MAC...
Norris, Michael; Fetler, Bayard; Marchant, Jan; Johnson, Bruce A.
NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.
Norris, Michael; Fetler, Bayard [One Moon Scientific, Inc. (United States); Marchant, Jan [University of Maryland Baltimore County, Howard Hughes Medical Institute (United States); Johnson, Bruce A., E-mail: firstname.lastname@example.org [One Moon Scientific, Inc. (United States)
NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.
The nineteenth-century fantasy writer George MacDonald believed that "it is better to be a child in a green field than a knight of many orders." In this paper, I shall explore the bearing of this high estimate of childhood on spiritual education. MacDonald explores the spirituality of the child in his essay "A Sketch of Individual Development" and…
Joshi, V.M.; Agashe, Alok; Bairi, B.R.
This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs
In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)
Casasent, David; Taylor, Bradley K.
A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.
Larwill, M.; Lagerlund, T.D.; Barsotti, E.; Taff, L.M.; Franzen, J.
Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS ''event builder'' (i.e., data acquisition processor). Primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. Some possible FASTBUS data acquisition system architectures employing the UPI are discussed along with some detailed specifications of the UPI itself
Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining
The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.
Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah
In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.
This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...
Rothman, Ernest E; Rosen, Rich
If you've been lured to Mac OS X because of its Unix roots, this invaluable book serves as a bridge between Apple's Darwin OS and the more traditional Unix systems. The new edition offers a complete tour of Mac OS X's Unix shell for Leopard and Tiger, and helps you find the facilities that replace or correspond to standard Unix utilities. Learn how to compile code, link to libraries, and port Unix software to Mac OS X and much more with this concise guide.
Office 2008 for Mac is here, with great new enhancements to all your favorite office productivity tools. Who better than "Dr. Mac, "Bob LeVitus, to show you how to load and use them all? From choosing the best version for your needs to managing your life with your online calendar, Office 2008 For Mac For Dummies covers what you need to know. It compares the Student/Teacher Edition, Standard Edition, and Professional Edition, then walks you through installing your preferred version and keeping it up to date. You'll find out all the things you can do with Word, Excel, PowerPoint, and Entourage,
Office for Mac remains the leading productivity suite for Mac, with Apple's iWork and the free OpenOffice.org trailing far behind. And now it's being updated with a cleaner interface and more compatibility with Exchange and SharePoint. Learn Office 2011 for Mac OS X offers a practical, hands-on approach to using Office 2011 applications to create and edit documents and get work done efficiently. You'll learn how to customize Office, design, create, and share documents, manipulate data in a spreadsheet, and create lively presentations. You'll also discover how to organize your email, contacts,
Curtiss, J.A.; Indusi, J.P.
The MACS/ACRS (Managed Access by Controlled Sensing/Access by Controlled Remote Sensing) system is a collection of communication devices, video capability, and distance-measuring equipment which can effectively substitute for the physical presence of a challenge inspector within a facility. The MACS design allows growth of the prototype, developed in response to the Chemical Weapons Convention (CWC), into a versatile device for inspection of sensitive nuclear facilities under other international arrangements, for example the proposed Fissile Material Cutoff Convention. A MACS/ACRS-type system in a standard, international-recognized configuration could resolve sensitive information and safety concerns through providing a means of achieving the goals of an inspection while excluding the inspector. We believe the technology used to develop MACS for the Defense Nuclear Agency, followed by ACRS for the Department of Energy, is universally adaptable for minimally-intrusive managed-access international inspections of sensitive sites
Curtiss, J.A.; Indusi, J.P.
The MACS/ACRS (Managed Access by Controlled Sensing/Access by Controlled Remote Sensing) system is a collection of communication devices, video capability, and distance-measuring equipment which can effectively substitute for the physical presence of a challenge inspector within a facility. The MACS design allows growth of the prototype, developed in response to the Chemical Weapons Convention (CWC), into a versatile device for inspection of sensitive nuclear facilities under other international arrangements, for example the proposed Fissile Material Cutoff Convention. A MACS/ACRS-type system in a standard, international-recognized configuration could resolve sensitive information and safety concerns through providing a means of achieving the goals of an inspection while excluding the inspector. We believe the technology used to develop MACS for the Defense Nuclear Agency, followed by ACRS for the Department of Energy, is universally adaptable for minimally-intrusive managed-access international inspections of sensitive sites.
You're smart and savvy, but also busy. This comprehensive guide to Apple's Mac OS X 10.6, Snow Leopard, gives you everything you need to know to live a happy, productive Mac life. Learn Mac OS X Snow Leopard will have you up and connected lickity split. With a minimum of overhead and a maximum of useful information, you'll cover a lot of ground in the time it takes other books to get you plugged in. If this isn't your first experience with Mac OS X, skip right to the "What's New in Snow Leopard" sections. You may also find yourself using this book as a quick refresher course or a way
Brunner, M D; Braithwaite, P; Jhaveri, R; McEwan, A I; Goodman, D K; Smith, L R; Glass, P S
We have shown previously that a plasma fentanyl concentration of 1.67 ng ml-1 reduced the MAC of isoflurane by 50%. By comparing equal degrees of MAC reduction by sufentanil, we may determine the potency ratio of these opioids. Seventy-six patients were allocated randomly to receive predetermined infusions of sufentanil, and end-tidal concentrations of isoflurane in oxygen. Blood samples were obtained 10 min after the start of the infusion, and just before and after skin incision. Any purposeful movement by the patient was recorded. The MAC reduction of isoflurane produced by sufentanil was obtained using a logistic regression model. A sufentanil plasma concentration of 0.145 ng ml-1 (95% confidence limits 0.04, 0.26 ng ml-1) resulted in a 50% reduction in the MAC of isoflurane. At a plasma concentration greater than 0.5 ng ml-1, sufentanil exhibited a ceiling effect.
Lerner, David; Corporation, Tekserve
The Macintosh Troubleshooting Pocket Guide covers the most common user hardware and software trouble. It's not just a book for Mac OS X (although it includes tips for OS X and Jaguar), it's for anyone who owns a Mac of any type-- there are software tips going back as far as OS 6. This slim guide distills the answers to the urgent questions that Tekserve's employee's answer every week into a handy guide that fits in your back pocket or alongside your keyboard.
Yan, Ying; Dittmann, Lars
This paper introduces sleep mode operations for EPON. New MAC control functions are proposed to schedule sleep periods. Traffic profiles are considered to optimize energy efficiency and network performances. Simulation results are analyzed in OPNET modeler.......This paper introduces sleep mode operations for EPON. New MAC control functions are proposed to schedule sleep periods. Traffic profiles are considered to optimize energy efficiency and network performances. Simulation results are analyzed in OPNET modeler....
Dentistry, University of Illinois at Chicago, Chicago, IL, USA. 2 Department of Defense Biotechnology High Performance Computing Software...study, we used a commercially available Mac-1 deficient strain to examine whether this deficit 5 extends to slightly smaller wounds and incisional...levels of Collagen I and Collagen III in wounds from the two strains of mice at any time point. Unwounded skin from both WT and Mac-1 -/- mice contained
Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.
Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization
Kerczewski, R. J.; Apaza, R. D.; Dimond, R. P.
This The Aeronautical Mobile Airport Communications System (AeroMACS) is being developed to provide a new broadband wireless communications capability for safety critical communications in the airport surface domain, providing connectivity to aircraft and other ground vehicles as well as connections between other critical airport fixed assets. AeroMACS development has progressed from requirements definition through technology definition, prototype deployment and testing, and now into national and international standards development. The first prototype AeroMACS system has been deployed at the Cleveland Hopkins International Airport (CLE) and the adjacent NASA Glenn Research Center (GRC). During the past three years, extensive technical testing has taken place to characterize the performance of the AeroMACS prototype and provide technical support for the standards development process. The testing has characterized AeroMACS link and network performance over a variety of conditions for both fixed and mobile data transmission and has included basic system performance testing and fixed and mobile applications testing. This paper provides a summary of the AeroMACS performance testing and the status of standardization activities that the testing supports.
In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)
Chhabra, Siddhartha; Solihin, Yan
With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.
Arshad, J.; Akram, Q.; Saleem, Y.
Data communication between nodes is carried out under Medium Access Control (MAC) protocol which is defined at data link layer. The MAC protocols are responsible to communicate and coordinate between nodes according to the defined standards in WSN (Wireless Sensor Networks). The design of a MAC protocol should also address the issues of energy efficiency and transmission efficiency. There are number of MAC protocols that exist in the literature proposed for WSN. In this paper, nine MAC protocols which includes S-MAC, T-MAC, Wise-MAC, Mu-MAC, Z-MAC, A-MAC, D-MAC, B-MAC and B-MAC+ for WSN have been explored, studied and analyzed. These nine protocols are classified in contention based and hybrid (combination of contention and schedule based) MAC protocols. The goal of this comparative study is to provide a basis for MAC protocols and to highlight different mechanisms used with respect to parameters for the evaluation of energy and transmission efficiency in WSN. This study also aims to give reader a better understanding of the concepts, processes and flow of information used in these MAC protocols for WSN. A comparison with respect to energy reservation scheme, idle listening avoidance, latency, fairness, data synchronization, and throughput maximization has been presented. It was analyzed that contention based MAC protocols are less energy efficient as compared to hybrid MAC protocols. From the analysis of contention based MAC protocols in term of energy consumption, it was being observed that protocols based on preamble sampling consume lesser energy than protocols based on static or dynamic sleep schedule. (author)
Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.
Key, F.A.; Lea, T.G.; Douglas, A.
A description is given of the design, construction and initial testing of two types of Seismometer Array Station Processor (SASP), one to work with data stored on magnetic tape in analogue form, the other with data in digital form. The purpose of a SASP is to detect the short period P waves recorded by a UK-type array of 20 seismometers and to edit these on to a a digital library tape or disc. The edited data are then processed to obtain a rough location for the source and to produce seismograms (after optimum processing) for analysis by a seismologist. SASPs are an important component in the scheme for monitoring underground explosions advocated by the UK in the Conference of the Committee on Disarmament. With digital input a SASP can operate at 30 times real time using a linear detection process and at 20 times real time using the log detector of Weichert. Although the log detector is slower, it has the advantage over the linear detector that signals with lower signal-to-noise ratio can be detected and spurious large amplitudes are less likely to produce a detection. It is recommended, therefore, that where possible array data should be recorded in digital form for input to a SASP and that the log detector of Weichert be used. Trial runs show that a SASP is capable of detecting signals down to signal-to-noise ratios of about two with very few false detections, and at mid-continental array sites it should be capable of detecting most, if not all, the signals with magnitude above msub(b) 4.5; the UK argues that, given a suitable network, it is realistic to hope that sources of this magnitude and above can be detected and identified by seismological means alone. (author)
Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian
In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.
Mac Self-Service is a functionality within the Mac Desktop Service built and maintained to empower CERN users by giving them easy access to applications and configurations through the Self-Service application. This tutorial (text attached to the event page) explains how to install Mac Self-Service and how to use it to install applications and printers. Content owner: Vincent Nicolas Bippus Presenter: Pedro Augusto de Freitas Batista Tell us what you think via e-learning.support at cern.ch More tutorials in the e-learning collection of the CERN Document Server (CDS) https://cds.cern.ch/collection/E-learning%20modules?ln=en All info about the CERN rapid e-learning project is linked from http://twiki.cern.ch/ELearning
Luykx, Atul; Preneel, Bart; Tischhauser, Elmar Wolfgang
Lightweight cryptography strives to protect communication in constrained environments without sacrificing security. However, security often conflicts with efficiency, shown by the fact that many new lightweight block cipher designs have block sizes as low as 64 or 32 bits. Such low block sizes lead...... no effect on the security bound, allowing an order of magnitude more data to be processed per key. Furthermore, LightMAC is incredibly simple, has almost no overhead over the block cipher, and is parallelizable. As a result, LightMAC not only offers compact authentication for resource-constrained platforms...
Tehan III, William J.
For more than a half century Douglas MacArthur was a servant of the United States. He is best remembered as a general and a soldier, especially for his leadership during World War II and the Korean War. MacArthur was also the Superintendent of West Point, Chief of Staff of the U.S. Army, Generalissimo ( Commander) of the Armed Forces and Military Advisor (Minister of Defense) to the President of the Commonwealth of the Philippines, and the Supreme Commander Allied Powers and the Military Gove...
Discover loads of tips and techniques for the newest MacBook Pro You're already ahead of the game with a MacBook Pro. Now you can get even more out the popular Apple notebook with the new edition of this handy, compact book. Crammed with savvy insights and tips on key tools and shortcuts, this book will help you increase your productivity and keep your Apple digital lifestyle on track. From desktop sharing and wireless networking to running Windows applications, this book avoids fluff, doesn't skimp on the essentials, saves you time and hassle, and shows you what you most want to know. Include
Whether you're new to the Mac or a longtime user, this handy book is the quickest way to get up to speed on Snow Leopard. Packed with concise information in an easy-to-read format, Mac OS X Snow Leopard Pocket Guide covers what you need to know and is an ideal resource for problem-solving on the fly. This book goes right to the heart of Snow Leopard, with details on system preferences, built-in applications, and utilities. You'll also find configuration tips, keyboard shortcuts, guides for troubleshooting, lots of step-by-step instructions, and more. Learn about new features and changes s
The design, construction, and performance characteristics of a high precision gaseous drift chamber made of thin walled proportional tubes are described. The device achieved an average spatial resolution of 45 μm in use for physics analysis with the MAC detector. The B-lifetime result obtained with this chamber is discussed
Yukinobu Kitamura; Hiroshi Fujiki
We demonstrate a statistical procedure for selecting the most suitable empirical model to test an economic theory, using the example of the test for purchasing power parity based on the Big Mac Index. Our results show that supporting evidence for purchasing power parity, conditional on the Balassa-Samuelson effect, depends crucially on the selection of models, sample periods and economies used for estimations.
Stolz, Steven A.
MacIntyre's earlier work and concern with social science enquiry not only exposes its limits, but also provides an insight into how its knowledge claims have been put to ideological use. He maintains that the institutional embodiment of these ideological ideas is the bureaucratic manager who has had a negative role to play in social structures…
Home; Journals; Resonance – Journal of Science Education; Volume 10; Issue 1. Florence Jessie Mac Williams (1917-1990). Featured Scientist Volume 10 Issue 1 January 2005 pp 98-98. Fulltext. Click here to view fulltext PDF. Permanent link: https://www.ias.ac.in/article/fulltext/reso/010/01/0098-0098. Resonance ...
American Indian Journal, 1979
Peter MacDonald, Chairman of the Navajo Nation, the largest tribe in the United States speaks to such issues as energy development/management, oil companies, Navajo-Hopi relocation legislation, traditionalism, and the role of the Council of Energy Resource Tribes. (RTS)
A vertex chamber for MAC was proposed to increase precision in the measurement of the B hadron and tau lepton lifetimes. Thin-walled aluminized mylar drift tubes were used for detector elements. A study of radiation hardness was conducted under the conditions of the proposed design using different gases and different operating conditions
Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.
The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module
Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe
of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....
Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.
Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department
In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...
Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department
In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...
Curtiss, J.A.; Indusi, J.P.
General acceptance of the challenge provision in the Chemical Weapons Convention has the potential for influence in other arms control areas. While most applications of the challenge inspection may be straightforward, there may be instances where access to the site by inspectors may be problematic. The MACS system described in this paper was developed to respond to these situations. Inspection and verification may be difficult when a host is unwilling,for valid reasons, to permit physical access to a site. We proposed a system of remote sensors which may be used to demonstrate compliance with Chemical Weapons Convention (CWC) challenge inspections even ff the inspector is physically excluded from a sensitive site. The system is based upon alternative-means-of-access provisions of the CWC. The Defense Nuclear Agency (DNA) funded design and construction of a system prototype, designated as MACS for Managed Access by Controlled Sensing. Features of the MACS design allow growth of the prototype into a versatile device for international monitoring of production facilities and other sites. MACS consists of instrumentation and communication equipment allowing site personnel to conduct a facility tour and perform acceptable measurements, while physically excluding the inspector from the facility. MACS consists of a base station used by the inspector, and a mobile unit used within the facility and manipulated by the facility staff. The base station and the mobile unit are at sign ed by a communication system, currently realized as a fiber optic cable. The mobile unit is equipped with television cameras and remote-reading distance-measuring equipment (DME) for use in verifying locations and dimensions. Global Positioning System receivers on the mobile unit provide both precise location and dead reckoning, suitable for tracking the mobile unit's position while within a building when satellite signals are not available
Martella, Andrea; Pollard, Steven M; Dai, Junbiao; Cai, Yizhi
The enabling technologies of synthetic biology are opening up new opportunities for engineering and enhancement of mammalian cells. This will stimulate diverse applications in many life science sectors such as regenerative medicine, development of biosensing cell lines, therapeutic protein production, and generation of new synthetic genetic regulatory circuits. Harnessing the full potential of these new engineering-based approaches requires the design and assembly of large DNA constructs-potentially up to chromosome scale-and the effective delivery of these large DNA payloads to the host cell. Random integration of large transgenes, encoding therapeutic proteins or genetic circuits into host chromosomes, has several drawbacks such as risks of insertional mutagenesis, lack of control over transgene copy-number and position-specific effects; these can compromise the intended functioning of genetic circuits. The development of a system orthogonal to the endogenous genome is therefore beneficial. Mammalian artificial chromosomes (MACs) are functional, add-on chromosomal elements, which behave as normal chromosomes-being replicating and portioned to daughter cells at each cell division. They are deployed as useful gene expression vectors as they remain independent from the host genome. MACs are maintained as a single-copy and can accommodate multiple gene expression cassettes of, in theory, unlimited DNA size (MACs up to 10 megabases have been constructed). MACs therefore enabled control over ectopic gene expression and represent an excellent platform to rapidly prototype and characterize novel synthetic gene circuits without recourse to engineering the host genome. This review describes the obstacles synthetic biologists face when working with mammalian systems and how the development of improved MACs can overcome these-particularly given the spectacular advances in DNA synthesis and assembly that are fuelling this research area.
Casasent, David; Jackson, James; Vaerewyck, Gerard
A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.
Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.
We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate
Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...
Modali, Sita D; Zgurskaya, Helen I
Escherichia coli MacAB-TolC is a tripartite macrolide efflux transporter driven by hydrolysis of ATP. In this complex, MacA is the periplasmic membrane fusion protein that stimulates the activity of MacB transporter and establishes the link with the outer membrane channel TolC. The molecular mechanism by which MacA stimulates MacB remains unknown. Here, we report that the periplasmic membrane proximal domain of MacA plays a critical role in functional MacA-MacB interactions and stimulation of MacB ATPase activity. Binding of MacA to MacB stabilizes the ATP-bound conformation of MacB, whereas interactions with both MacB and TolC affect the conformation of MacA. A single G353A substitution in the C-terminus of MacA inactivates MacAB-TolC function by changing the conformation of the membrane proximal domain of MacA and disrupting the proper assembly of the MacA-MacB complex. We propose that MacA acts in transport by promoting MacB transition into the closed ATP-bound conformation and in this respect, is similar to the periplasmic solute-binding proteins. © 2011 Blackwell Publishing Ltd.
...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...
Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven
As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...
Chambers, Mark L
Get comfortable and confident with your MacBook! Combining the fun-but-straightforward content of nine minibooks, this new edition of MacBook All-in-One For Dummies delivers helpful coverage of the rich features and essential tools you need to know to use the MacBook to its fullest potential. You'll learn an array of MacBook basics while veteran author Mark Chambers walks you through setting up your MacBook, running programs, finding files with Finder, searching with Spotlight, keeping track with Address Book, enjoying music with iTunes, creating cool multimedia projects with iLife, and more.
Learn the skills, tools and shortcuts you need in order to make the most of your MacBook Pro This easy-to-use, compact guide skips the fluff and gets right to the essentials so that you can maximize all the latest features of the MacBook Pro. Packed with savvy insights and tips on key tools and shortcuts, this handy book aims to help you increase your productivity and save you time and hassle. From desktop sharing and wireless networking to running Windows applications and more, this book shows you what you want to know. Includes the latest version of OS X, iCloud, FaceTime, and moreCovers al
Hrasnica, Halid; Haidine, Abdelfatteh
The usage of electrical power distribution networks for voice and data transmission, called Powerline Communications, becomes nowadays more and more attractive, particularly in the telecommunication access area. The most important reasons for that are the deregulation of the telecommunication market and a fact that the access networks are still property of former monopolistic companies. In this work, first we analyze a PLC network and system structure as well as a disturbance scenario in powerline networks. After that, we define a logical structure of the powerline MAC layer and propose the reservation MAC protocols for the usage in the PLC network which provides collision free data transmission. This makes possible better network utilization and realization of QoS guarantees which can make PLC networks competitive to other access technologies.
Two recent publications, from the MAC and Mark II collaborations, have reported the somewhat surprising result that the lifetime of particles made up of b quarks is in the 1 to 2 picosecond range, or somewhat longer than the lifetimes of charm particles. Although the charm decays are favored transitions while those of b particles depend upon off-diagonal elements of the weak flavor mixing matrix, the smallness of the b decay rates in face of the large available phase space indicates that the off-diagonal elements are indeed very small. The possibility for complete determination of the mixing matrix was brought significantly nearer by the availability of the lifetime information; what is needed now is to reduce the uncertainty of the measurements, which was about 33% for both experiments. We describe here an extension of the b lifetime study with the MAC detector, incorporating some new data and improvements in the analysis. 12 references
Halbiniak, Zbigniew; Jozwiak, Ireneusz J.
In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case
Step by step guide to installing the version control software Git under the Macintosh Operating System MacOS X (and later). Includes a seqeunce of screenshots with hand drawn arrows ;-) These slides are part of the materials for an Introductory course on the R language and environment for statistial computing. Free and Open Source materials for this course hosted on GitHub: https://github.com/brfitzpatrick/Intro_to_R
Lim, Kihong; Hyun, Young-Min; Lambert-Emo, Kris; Topham, David J; Kim, Minsoo
β2 integrins play critical roles in migration of immune cells and in the interaction with other cells, pathogens, and the extracellular matrix. Among the β2 integrins, Mac-1 (Macrophage antigen-1), composed of CD11b and CD18, is mainly expressed in innate immune cells and plays a major role in cell migration and trafficking. In order to image Mac-1-expressing cells both in live cells and mouse, we generated a knock-in (KI) mouse strain expressing CD11b conjugated with monomeric yellow fluorescent protein (mYFP). Expression of CD11b-mYFP protein was confirmed by Western blot and silver staining of CD11b-immunoprecipitates and total cell lysates from the mouse splenocytes. Mac-1-mediated functions of the KI neutrophils were comparable with those in WT cells. The fluorescence intensity of CD11b-mYFP was sufficient to image CD11b expressing cells in live mice using intravital two-photon microscopy. In vitro, dynamic changes in the intracellular localization of CD11b molecules could be measured by epifluorescent microscopy. Finally, CD11b-expressing immune cells from tissue were easily detected by flow cytometry without anti-CD11b antibody staining. Copyright © 2015 Elsevier B.V. All rights reserved.
Kiniry, Joseph R.; Cheong, Elaine
The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.
Full Text Available Low power MAC protocols have received a lot of consideration in the last few years because of their influence on the lifetime of wireless sensor networks. Since, sensors typically operate on batteries, replacement of which is often difficult. A lot of work has been done to minimize the energy expenditure and prolong the sensor lifetime through energy efficient designs, across layers. Meanwhile, the sensor network should be able to maintain a certain throughput in order to fulfill the QoS requirements of the end user, and to ensure the constancy of the network. This paper introduces different types of MAC protocols used for WSNs and proposes S‐MAC, a Medium‐Access Control protocol designed for Wireless Sensor Networks. S‐MAC uses a few innovative techniques to reduce energy consumption and support selfconfiguration. A new protocol is suggested to improve the energy efficiency, latency and throughput of existing MAC protocol for WSNs. A modification of the protocol is then proposed to eliminate the need for some nodes to stay awake longer than the other nodes which improves the energy efficiency, latency and throughput and hence increases the life span of a wireless sensor network.
The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)
This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...
Raut, V.M.; Taware, S.P.; Halvankar, G.B.; Varghese, Philips
A mutant variety -MACS 111 developed by treating seeds of indigenous black seeded 'Kalitur' variety with gamma irradiation + Ethyleneimine was used in development of high yielding varieties. MACS 450 a promising high yielding variety was selected from Bragg x MACS 111 cross by pedigree selection method. This variety gave the highest average seed yield in station trials (3422 kg/ha), coordinated breeding trials (2361 kg/ha) and varieties cum plant population trial (2215 kg/ha). On the basis of its performance in these trials it was released for commercial cultivation in Southern India. On all India basis, it also recorded the highest seed yield of 4076 kg/ha and 3582 kg/ha in Front line Demonstrations conducted on the farmers' field during 1998 and 1999 respectively. (author)
Hung, Jen-Sheng; Lin, Chia-Hsing; Jen, Chein-Wei
An on-chip memory architecture for video signal processor (VSP) is proposed. This memory structure is a two-level design for the different data locality in video applications. The upper level--Memory A provides enough storage capacity to reduce the impact on the limitation of chip I/O bandwidth, and the lower level--Memory B provides enough data parallelism and flexibility to meet the requirements of multiple reconfigurable pipeline function units in a single VSP chip. The needed memory size is decided by the memory usage analysis for video algorithms and the number of function units. Both levels of memory adopted a dual-port memory scheme to sustain the simultaneous read and write operations. Especially, Memory B uses multiple one-read-one-write memory banks to emulate the real multiport memory. Therefore, one can change the configuration of Memory B to several sets of memories with variable read/write ports by adjusting the bus switches. Then the numbers of read ports and write ports in proposed memory can meet requirement of data flow patterns in different video coding algorithms. We have finished the design of a prototype memory design using 1.2- micrometers SPDM SRAM technology and will fabricated it through TSMC, in Taiwan.
Now that multicore processors are coming to mobile devices, wouldn't it be great to take advantage of all those cores without having to manage threads? This concise book shows you how to use Apple's Grand Central Dispatch (GCD) to simplify programming on multicore iOS devices and Mac OS X. Managing your application's resources on more than one core isn't easy, but it's vital. Apps that use only one core in a multicore environment will slow to a crawl. If you know how to program with Cocoa or Cocoa Touch, this guide will get you started with GCD right away, with many examples to help you writ
Pezzarossa, Luca; Kenn Toft, Jakob; Lønbæk, Jesper
The Patmos processor, which is used as the intellectual property of the T-CREST platform, is only equipped with a RS-232 serial port for communication with the outside world. The serial port is a minimal input/output device with a limited speed and without native networking features. An Ethernet 10....../100BASE-T IEEE 802.3 based communication channel is a reliable and high speed communication interface (10/100 Mbits/s) that also supports networking. This technical report presents an implementation of an Ethernet-based communication channel for the Patmos processor, targeting the Terasic DE2......-115 development board. We have designed the hardware to interface the EthMac Ethernet controller from OpenCores to Patmos and to the physical chip of the development board, and we have implemented a software library to drive the controller and to support some essential protocols. The design was implemented...
Wang, Haixin; Bai, Guoqiang; Chen, Hongyi
The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.
It was one of the first portable macs released. The Portable had many new advances in mobile computing : The display was crispy clear, and looked beautiful when used in daylight ; The Portable came with a Lead-acid gel/cell battery that could run a anywhere from 6 -12 hours ; It supported to internal hard drives, and an external one. The reaction to the laptop was weak because it was slow, it had no capacity for expansion, it weighed heavily, its price was expensive. It has been stayed 1 year and half on the market.
Modali, Sita D.; Zgurskaya, Helen I.
Escherichia coli MacAB-TolC is a tri-partite macrolide efflux transporter driven by hydrolysis of ATP. In this complex, MacA is the periplasmic membrane fusion protein that stimulates the activity of MacB transporter and establishes the link with the outer membrane channel TolC. The molecular mechanism by which MacA stimulates MacB remains unknown. Here, we report that the periplasmic membrane proximal domain of MacA plays a critical role in functional MacA-MacB interactions and stimulation o...
Objective: The purpose of this study was to create a global medical earnings index, called the Medical MAC Index, to enable a comparison of what medical specialists earn in the countries included in the study. Design: The study gathered data on the earnings of specialist anaesthetists employed in state hospitals with five ...
Galzarano, S.; Liotta, A.; Fortino, G.; Aversa, R.; Kolodziej, J.; Zhang, J.; Amato, F.; Fortino, G.
WSNs are becoming an increasingly attractive technology thanks to the significant benefits they can offer to a wide range of application domains. Extending the system lifetime while preserving good network performance is one of the main challenges in WSNs. In this paper, a novel MAC protocol
If you've ever wondered how to safely manipulate Mac OS X Panther Server's many underlying configuration files or needed to explain AFP permission mapping--this book's for you. From the command line to Apple's graphical tools, the book provides insight into this powerful server software. Topics covered include installation, deployment, server management, web application services, data gathering, and more
Making Everything Easier!. Mac OS® X Snow Leopard Server for Dummies. Learn to::;. Set up and configure a Mac network with Snow Leopard Server;. Administer, secure, and troubleshoot the network;. Incorporate a Mac subnet into a Windows Active Directory® domain;. Take advantage of Unix® power and security. John Rizzo. Want to set up and administer a network even if you don't have an IT department? Read on!. Like everything Mac, Snow Leopard Server was designed to be easy to set up and use. Still, there are so many options and features that this book will save you heaps of time and effort. It wa
Richardson, B.S.; Haley, D.C.; Dudar, A.M.; Ward, C.R.
The Savannah River Technology Center (SRTC) and Oak Ridge National Laboratory are developing an advanced Mobile Automated Characterization System (MACS) to characterize indoor contaminated floors. MACS is based upon Semi-Intelligent Mobile Observing Navigator (SIMON), an earlier floor characterization system developed at SRTC. MACS will feature enhanced navigation systems, operator interface, and an interface to simplify integration of additional sensors. The enhanced navigation system will provide the capability to survey large open areas much more accurately than is now possible with SIMON, which is better suited for hallways and corridors that provide the means for recalibrating position and heading. MACS operator interface is designed to facilitate MACS's use as a tool for health physicists, thus eliminating the need for additional training in the robot's control language. Initial implementation of MACS will use radiation detectors. Additional sensors, such as PCB sensors currently being developed, will be integrated on MACS in the future. Initial use of MACS will be focused toward obtaining comparative results with manual methods. Surveys will be conducted both manually and with MACS to compare relative costs and data quality. While clear cost benefits anticipated, data quality benefits should be even more significant
Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan
This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The
Sriram, Kotikalapudi; Li, Chia-Chang; Magill, Peter; Whitaker, Norman A.; Dail, James E.; Dajer, Miguel A.; Siller, Curtis A.
Described here is an adaptive MAC-layer protocol that supports multiservice (STM and ATM) applications in the context of subscriber access to tree and branch (e.g., fiber-coaxial cable) networks. The protocol adapts to changing demands for a mix of circuit and cell mode applications, and efficiently allocates upstream and downstream bandwidth to a variety of bursty and isochronous traffic sources. In the case of a hybrid fiber-coaxial (HFC) network the protocol resides in customer premises equipment and a common head-end controller. A medium-access control (MAC) processor provides for dividing the time domain for a given digital bitstream into successive frames, each with multiple STM and ATM time slots. Within the STM region of a frame, variable length time slots are allocated to calls (e.g., telephony, video telephony) requiring different amounts of bandwidth. A contention access signaling channel is also provided in this region for call control and set-up requests. Within the ATM region fixed-length time slots accommodate one individual ATM cell. These ATM time slots may be reserved for a user for the duration of a call or burst of successive ATM cells, or shared via a contention process. At least one contention time slot is available for signaling messages related to ATM call control and set-up requests. Further, the fixed-length ATM time slots may be reserved by a user for the duration of a call, or shared through a contention process. This paper describes the MAC-layer protocol, its relation to circuit- and ATM- amenable applications, and its performance with respect to signaling throughput and latency, and bandwidth efficiency for several service scenarios.
Downie, John D.; Goodman, Joseph W.
Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.
SHANKER NILANGI; SOWMYA L
This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...
Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew
The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.
Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)
A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16
Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate
Forsberg, H.; Karolinska Sjukhuset, Stockholm
Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)
Kaerhae, K.; Jouhiaho, A.
The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)
Berry, John N., III
This article profiles Steven L. MacCall, winner of "Library Journal's" 2010 Teaching Award. An associate professor at the School of Library and Information Studies (SLIS) at the University of Alabama, Tuscaloosa, MacCall was nominated by Kathie Popadin, known as "Kpop" to the members of her cohort in the online MLIS program at SLIS. Sixteen of…
Russell, V.K.; Mullaney, J.E.
The K Basins Materials Accounting (MAC) and Material Balance (MBA) database system were set up to run under one common applications program. This Acceptance Test Plan (ATP) describes how the code was to be tested to verify its correctness. The scope of the tests is minimal, since both MAC and MBA have already been tested in detail as stand-alone programs
A vertex chamber for MAC was proposed in fall 1983 to increase precision in the measurement of the B hadron and tau lepton lifetimes. The chamber had to be placed within the existing central drift chamber, making access for repairs difficult and costly. Therefore for detector elements thin-walled aluminized mylar drift tubes (straws) were used because of their simplicity and robustness. The diameter of the drift tubes was 6.9 mm. The radial extent of the proposed chamber was from 3 cm to 10 cm, the inner wall of the central drift. It was clear that radiation levels, from synchrotron x-rays and overfocussed electrons, were potentially high. Since the drift distance is short in the straws, it was desirable to operate them at the highest possible gas gain, to achieve the best spatial resolution. There was a likelihood of drawing large currents in the chamber and thus causing radiation damage. Therefore a study of radiation hardness under the conditions of their proposed design was undertaken. In tests, argon-hydrocarbon mixtures consistently became unusable at ∼0.05 C/cm collected charge, due to anode buildup. Argon-CO 2 mixtures, while underquenched, were operational to 0.25 C/cm, at which point loss of cathode material became intolerable. Argon-xenon-CO 2 proved to be quenched as well as argon-hydrocarbons, but was limited by cathode damage. The MAC vertex chamber has operated at a distance of 4.6 cm from the e + e - interaction point at PEP for two years and has shown no aging effects
Micro computers can be used satisfactorily in general protection duties with economic advantages over hardwired systems. The reliability of such protection functions can be enhanced by keeping the task performed by each protection micro processor simple and by avoiding such a task being dependent on others in any substantial way. This implies that vital work done for any task is kept within it and that any communications from it to outside or to it from outside are restricted to those for controlling data transfer. Also that the amount of this data should be the minimum consistent with satisfactory task execution. Technology is changing rapidly and devices may become obsolete and be supplanted by new ones before their theoretical reliability can be confirmed or otherwise by field service. This emphasises the need for users to pool device performance data so that effective reliability judgements can be made within the lifetime of the devices. (orig.) [de
Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik
We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...
Duff, I.S.; Reid, J.K.
These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)
Smit, Gerardus Johannes Maria; Jansen, P.G.
Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,
Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.
A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors
Song, W.-Z.; Huang, R.; Shirazi, B.; Husent, R.L.
Earlier sensor network MAC protocols focus on energy conservation in low-duty cycle applications, while some recent applications involve real-time high-data-rate signals. This motivates us to design an innovative localized TDMA MAC protocol to achieve high throughput and low congestion in data collection sensor networks, besides energy conservation. TreeMAC divides a time cycle into frames and frame into slots. Parent determines children's frame assigmnent based on their relative bandwidth demand, and each node calculates its own slot assignment based on its hop-count to the sink. This innovative 2-dimensional frame-slot assignment algorithm has the following nice theory properties. Firstly, given any node, at any time slot, there is at most one active sender in its neighborhood (includ ing itself). Secondly, the packet scheduling with TreelMAC is bufferless, which therefore minimizes the probability of network congestion. Thirdly, the data throughput to gateway is at least 1/3 of the optimum assuming reliable links. Our experiments on a 24 node test bed demonstrate that TreeMAC protocol significantly improves network throughput and energy efficiency, by comparing to the TinyOS's default CSMA MAC protocol and a recent TDMA MAC protocol Funneling-MAC. ?? 2009 IEEE.
A particularly pathogenic group of mycobacteria belong to the Mycobacterium avium complex (MAC), which includes M. avium and M. intracellulare. MAC organisms cause disease in children, the elderly, and immuno-compromised individuals. A critical step in preventing MAC infections...
Abdul Kareem PARCHUR; Ram Asaray SINGH
High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...
The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5\\,us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.
Khomich, A; The ATLAS collaboration
The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serializers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.
Gupta, Madan M.; Knopf, George K.
A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.
Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya
Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)
Thomson, E. J.
A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented
J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly
Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999
Ramakrishna, STGS; Jamadagni, HS
Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP)   is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...
Brosnan Robert J
Full Text Available Abstract Background Sevoflurane potently enhances glycine receptor currents and more modestly decreases NMDA receptor currents, each of which may contribute to immobility. This modest NMDA receptor antagonism by sevoflurane at a minimum alveolar concentration (MAC could be reciprocally related to large potentiation of other inhibitory ion channels. If so, then reduced glycine receptor potency should increase NMDA receptor antagonism by sevoflurane at MAC. Methods Indwelling lumbar subarachnoid catheters were surgically placed in 14 anesthetized rats. Rats were anesthetized with sevoflurane the next day, and a pre-infusion sevoflurane MAC was measured in duplicate using a tail clamp method. Artificial CSF (aCSF containing either 0 or 4 mg/mL strychnine was then infused intrathecally at 4 μL/min, and the post-infusion baseline sevoflurane MAC was measured. Finally, aCSF containing strychnine (either 0 or 4 mg/mL plus 0.4 mg/mL dizocilpine (MK-801 was administered intrathecally at 4 μL/min, and the post-dizocilpine sevoflurane MAC was measured. Results Pre-infusion sevoflurane MAC was 2.26%. Intrathecal aCSF alone did not affect MAC, but intrathecal strychnine significantly increased sevoflurane requirement. Addition of dizocilpine significantly decreased MAC in all rats, but this decrease was two times larger in rats without intrathecal strychnine compared to rats with intrathecal strychnine, a statistically significant (P Conclusions Glycine receptor antagonism increases NMDA receptor antagonism by sevoflurane at MAC. The magnitude of anesthetic effects on a given ion channel may therefore depend on the magnitude of its effects on other receptors that modulate neuronal excitability.
Srivastava, Shiv P.; Das, Indra J.
Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.
Casasent, David; Telfer, Brian
We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.
Want to build native Mac OS X applications with a sleek, developer-friendly alternative to Objective-C? MacRuby is an ideal choice. This in-depth guide shows you how Apple's implementation of Ruby gives you access to all the features available to Objective-C programmers. You'll get clear, detailed explanations of MacRuby, including quick programming techniques such as prototyping. Perfect for programmers at any level, this book is packed with code samples and complete project examples. If you use Ruby, you can tap your skills to take advantage of Interface Builder, Cocoa libraries, the Objec
The iMac G3 is an all-in-one personal computer, encompassing both the monitor and the computer in one package. It allowed to revitalize the Apple brand that was in decline and close to financial ruin. Originally released in striking bondi blue and later a range of other translucent plastic envelopes in bright colors. The iMac comes with a keyboard and mouse matching the color of the case. The iMac G3 was sold from 1998 to 2003 and has been updated many times.
Logesh, K.; Rao, Samba Siva
This paper we presented the design objectives and technical challenges in Multichannel MAC protocols in Mobile Ad-hoc Network. In IEEE 802.11 a/b/g standards allow use of multiple channels, only a single channel is popularly used, due to the lack of efficient protocols that enable use of Multiple Channels. Even though complex environments in ad hoc networks require a combined control of physical (PHY) and medium access control (MAC) layers resources in order to optimize performance. And also we discuss the characteristics of cross-layer frame and give a multichannel MAC approach.
Advance in technology have produced intriguing tools that can be applied to problems in nuclear science. Information management in nuclear science is an example of how technology is not quickly exploited. The U.S. Department of Energy supports an extensive program to evaluate published nuclear properties and store them in an electronic data base. Much of the evaluation effort has focused on producing the journal Nuclear Data Sheets and the publication Table of Isotopes. Although the electronic data base can itself be a valuable source of information, the software used to access is was designed using decades-old technologies. The authors of this paper have developed a novel data-base management system for nuclear properties. The application is known as MacNuclide. It is a nuclear data-base environment that uses the highly interactive and intuitive windowing environmentsof desk-top computers. The environment is designed around that image of the chart of nuclides. Questions are posed to the data base by placing constraints on properties and defining collections of nuclides to be used in data-base seraches. Results are displayed either as a simple list of nuclides that meet the imposed constraints or as a color chart of nuclides
Computer Security Team
Still love bashing on Windows as you believe it is an insecure operating system? Hold on a second! Just recently, a vulnerability has been published for Java 7. It affects Windows/Linux PCs and Macs, Internet Explorer, Safari and Firefox. In fact, it affects all computers that have enabled the Java 7 plug-in in their browser (Java 6 and earlier is not affected). Once you visit a malicious website (and there are plenty already out in the wild), your computer is infected… That's "Game Over" for you. And this is not the first time. For a while now, attackers have not been targeting the operating system itself, but rather aiming at vulnerabilities inherent in e.g. your Acrobat Reader, Adobe Flash or Java programmes. All these are standard plug-ins added into your favourite web browser which make your web-surfing comfortable (or impossible when you un-install them). A single compromised web-site, however, is sufficient to prob...
Park, Y.S.; Park, C.O.
The nuclear design analysis requires time-consuming and erroneous model-input preparation, code run, output analysis and quality assurance process. To reduce human effort and improve design quality and productivity, Innovative Design Processor (IDP) is being developed. Two basic principles of IDP are the document-oriented design and the web-based design. The document-oriented design is that, if the designer writes a design document called active document and feeds it to a special program, the final document with complete analysis, table and plots is made automatically. The active documents can be written with ordinary HTML editors or created automatically on the web, which is another framework of IDP. Using the proper mix-up of server side and client side programming under the LAMP (Linux/Apache/MySQL/PHP) environment, the design process on the web is modeled as a design wizard style so that even a novice designer makes the design document easily. This automation using the IDP is now being implemented for all the reload design of Korea Standard Nuclear Power Plant (KSNP) type PWRs. The introduction of this process will allow large reduction in all reload design efforts of KSNP and provide a platform for design and R and D tasks of KNFC. (authors)
Otten, Leonard J.; Meigs, Andrew D.; Franklin, Abraham J.; Sears, Robert D.; Robison, Mark W.; Rafert, J. Bruce; Fronterhouse, Donald C.; Grotbeck, Ronald L.
Previous papers have described the concept behind the MightySat II.1 program, the satellite's Fourier Transform imaging spectrometer's optical design, the design for the spectral imaging payload, and its initial qualification testing. This paper discusses the on board data processing designed to reduce the amount of downloaded data by an order of magnitude and provide a demonstration of a smart spaceborne spectral imaging sensor. Two custom components, a spectral imager interface 6U VME card that moves data at over 30 MByte/sec, and four TI C-40 processors mounted to a second 6U VME and daughter card, are used to adapt the sensor to the spacecraft and provide the necessary high speed processing. A system architecture that offers both on board real time image processing and high-speed post data collection analysis of the spectral data has been developed. In addition to the on board processing of the raw data into a usable spectral data volume, one feature extraction technique has been incorporated. This algorithm operates on the basic interferometric data. The algorithm is integrated within the data compression process to search for uploadable feature descriptions.
Fishwick, P. A.
A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.
AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki
We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.
Zacharias, Sven; Newe, Thomas
Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.
Zacharias, Sven; Newe, Thomas, E-mail: Sven.Zacharias@ul.ie [University of Limerick (Ireland)
Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.
Zacharias, Sven; Newe, Thomas
Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.
The K Basins Materials Accounting (MAC) programs had some major improvements made to it to organize the main-tables by Location, Canister, and Material. This ATP describes how the code was to be tested to verify its correctness
This article deals with the principles of synergy effect of mechatronical aided concept (MAC) to the design of intelligent transport vehicles products applying CA technologies and virtual reality design methods. Also includes presentation of intelligent railway vehicle development.
You can set your watch to it: As soon as Apple comes out with another version of Mac OS X, David Pogue hits the streets with another meticulous Missing Manual to cover it with a wealth of detail. The new Mac OS X 10.4, better known as Tiger, is faster than its predecessors, but nothing's too fast for Pogue and Mac OS X: The Missing Manual. There are many reasons why this is the most popular computer book of all time. With its hallmark objectivity, the Tiger Edition thoroughly explores the latest features to grace the Mac OS. Which ones work well and which do not? What should you look for? Th
Reddy, K. Ganesh; Thilagam, P. Santhi
Wireless Mesh Networks (WMNs) have emerged as a promising technology for a broad range of applications due to their self-organizing, self-configuring and self-healing capability, in addition to their low cost and easy maintenance. Securing WMNs is more challenging and complex issue due to their inherent characteristics such as shared wireless medium, multi-hop and inter-network communication, highly dynamic network topology and decentralized architecture. These vulnerable features expose the WMNs to several types of attacks in MAC layer. The existing MAC layer standards and implementations are inadequate to secure these features and fail to provide comprehensive security solutions to protect both backbone and client mesh. Hence, there is a need for developing efficient, scalable and integrated security solutions for WMNs. In this paper, we classify the MAC layer attacks and analyze the existing countermeasures. Based on attacks classification and countermeasures analysis, we derive the research directions to enhance the MAC layer security for WMNs.
Recounts the life and times of a pioneer children's theater playwright and fiction author, Nora Tully MacAlvay (1900-86). Points out that her interest in children's theater and children's literature was lifelong and intense. (PA)
The MacMillan Pier Transportation Center Feasibility Study examines two potential sites (landside and waterside) for a transportation center that provides a range of tourist and traveler information. It would serve as a gateway for Provincetown and t...
Alasdair MacIntyre panus 20. sajandi eetikasse. Tema käsitlus vooruseetikast ja vooruseetilisest perspektiivist, mida on võimalik näha komplekselt, vaadeldes voorust, praktikat, narratiivi ja traditsiooni mõisteid
The Economist võrdleb maailma valuutade suhestamiseks Big Mac'i burgeri hindu 120 riigis, kuna see meetod võimaldab saada ülevaate riikide elanikkonna tegelikust ostujõust. Tabel: Hamburgeri standard
Budinger, James M.; Hall, Edward
To help increase the capacity and efficiency of the nation s airports, a secure wideband wireless communications system is proposed for use on the airport surface. This paper provides an overview of the research and development process for the Aeronautical Mobile Airport Communications System (AeroMACS). AeroMACS is based on a specific commercial profile of the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard known as Wireless Worldwide Interoperability for Microwave Access or WiMAX (WiMax Forum). The paper includes background on the need for global interoperability in air/ground data communications, describes potential AeroMACS applications, addresses allocated frequency spectrum constraints, summarizes the international standardization process, and provides findings and recommendations from the world s first AeroMACS prototype implemented in Cleveland, Ohio, USA.
Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...
Arthur Low; Steven Muegge
Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...
Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.
A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)
Full Text Available IEEE 802.15.4 is an important standard for Low Rate Wireless Personal Area Network (LRWPAN. The IEEE 802.15.4 presents a flexible MAC protocol that provides good efficiency for data transmission by adapting its parameters according to characteristics of different applications. In this research work, some restrictions of this standard are explained and an improvement of traffic efficiency by optimizing MAC layer is proposed. Implementation details for several blocks of communication system are carefully modeled. The protocol implementation is done using VHDL language. The analysis gives a full understanding of the behavior of the MAC protocol with regard to backoff delay, data loss probability, congestion probability, slot effectiveness, and traffic distribution for terminals. Two ideas are proposed and tested to improve efficiency of CSMA/CA mechanism for IEEE 802.15.4 MAC Layer. Primarily, we dynamically adjust the backoff exponent (BE according to queue level of each node. Secondly, we vary the number of consecutive clear channel assessment (CCA for packet transmission. We demonstrate also that slot compensation provided by the enhanced MAC protocol can greatly avoid unused slots. The results show the significant improvements expected by our approach among the IEEE 802.15.4 MAC standards. Synthesis results show also hardware performances of our proposed architecture.
Zhang, Qi; Fitzek, Frank H.P.; Iversen, Villy Bæk
hole; moreover, it designs dual inband sensing scheme to detect primary user appearance. Additionally, C-CSMA/CA has the advantage to effectively solve the cognitive radio self-coexistence issues in the overlapping CR BSSs scenario. It also realizes station-based dynamic resource selection......To solve the performance degradation issue in current WLAN caused by the crowded unlicensed spectrum, we propose a cognitive radio (CR) media access protocol, C-CSMA/CA. The basic idea is that with cognitive radio techniques the WLAN devices can not only access the legacy WLAN unlicensed spectrum...
Batsell, Stephen Gordon
One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.
Philip de Jersey
Full Text Available Following on from the impressive development of the new HSBC Money Gallery in 1997, the British Museum has launched into the world of electronic publishing with the World of Money, an "interactive exploration of money worldwide from ancient times to the present day". Intended for ages ten to adult, the CD promises "a mine of information about the use, form, history and importance of money around the globe", and "fun and information for all the family". Reviewing in a Mac-unfriendly environment, I have been able to run the CD only on a PC. On a 166Mhz MMX with 32Mb RAM and a 12x CD it runs impressively quickly, with no more than two or three seconds of the "loading new page" display when switching between different parts of the program. Minimum requirements are listed as a 486 with 8Mb RAM, 40Mb free hard disk space, Windows 3.11 or Windows 95, 4x CD drive, 1Mb 256 colours graphics card, 16-bit Sound Blaster compatible sound card, and a VGA monitor. Minimum requirements for the Mac are listed as System 7, 603e processor, 16Mb RAM, 40MB free hard disk space, 6x CD drive, 1Mb video card and Apple monitor or Multisync with adaptor. The CD opens with an image of the British Museum portico, through which we are taken into the foyer, complete with the sound effects of massed ranks of tourists. We have four options available on a lectern, or by turning left, right or going upstairs: History of Money, Information Centre, Activities, and Options. Clicking on a large question mark brings up the Help screens (Figure 1.
Full Text Available We propose the efficient reliable multicast MAC protocol based on the connectivity information among the recipients. Enhancing the BMMM (Batch Mode Multicast MAC protocol, the reliable multicast MAC protocol significantly reduces the RAK (Request for ACK frame transmissions in a reasonable computational time and enhances the MAC performance. By the analytical performance analysis, the throughputs of the BMMM protocol and our proposed MAC protocol are derived. Numerical examples show that our proposed MAC protocol increases the reliable multicast MAC performance for IEEE 802.11 wireless LANs.
An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....
Thoroughly revised and updated for Mac OS X Tiger, this new edition introduces Mac users to the Terminal application and shows you how to navigate the command interface, explore hundreds of Unix applications that come with the Mac, and, most importantly, how to take advantage of both the Mac and Unix interfaces. If you want to master the command-line, this gentle guide to using Unix on Mac OS X Tiger is well worth its cover price
Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.
In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)
Full Text Available Un helléniste convaincu, Victor Bérard, en vient, au début du XXe siècle à soutenir l’existence de « Macédoniens » et le slogan « la Macédoine aux Macédoniens”.Le Congrès de Berlin en 1878 avait laissé la Macédoine aux mains des Ottomans. La Grèce, la Serbie et la Bulgarie, parvenues à ses limites et prévoyant le retrait futur des Ottomans peaufinent les arguments linguistiques et historiques qui justifieront leurs revendications territoriales. Victor Bérard, un helléniste respecté et bon connaisseur de la région sud balkanique, effectue des enquêtes en Macédoine en 1896 et 1903 qu’il publie à Paris.Cette étude montre comment, dans le contexte de la propagande nationaliste des prétendants à la possession de la Macédoine, Victor Bérard en vient progressivement à affirmer qu’il existe une population autochtone, les Macédoniens. Il soutient leur programme pour la constitution d’une fédération ou confédération avec le slogan « la Macédoine aux Macédoniens » ce qui fait toute l’actualité de ses ouvrages.In 1878, the Congress of Berlin had left Macedonia in the hands of the Ottomans. Greece, Serbia and Bulgaria had reached its limits. Anticipating the Ottoman retreat, they polish language and historical arguments that will justify their territorial claims. Victor Bérard, a respected Hellenist and a good expert of the southern Balkans, is doing researches in Macedonia in 1896 and 1903. These will be later published in Paris.This study shows how, in the context of the nationalist propaganda build-up made by the candidates for the possession of Macedonia, Victor Bérard comes progressively to assert the existence of a native population: the Macedonians. He supports their program for the forming of a federation or confederation which slogan would be “Macedonia to Macedonians”. This makes his works very topical.
Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.
A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.
Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos
The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.
Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.
The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)
Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy
The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.
Bains, N.; Baird, S.A.; Biddulph, P.
The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)
Horninger, K.; Sandweg, G.
The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de
Glackin, Shane Nicholas
Can biological facts explain human morality? Aristotelian 'virtue' ethics has traditionally assumed so. In recent years Alasdair MacIntyre has reintroduced a form of Aristotle's 'metaphysical biology' into his ethics. He argues that the ethological study of dependence and rationality in other species--dolphins in particular--sheds light on how those same traits in the typical lives of humans give rise to the moral virtues. However, some goal-oriented dolphin behaviour appears both dependent and rational in the precise manner which impresses MacIntyre, yet anything but ethically 'virtuous'. More damningly, dolphin ethologists consistently refuse to evaluate such behaviour in the manner MacIntyre claims is appropriate to moral judgement. In light of this, I argue that virtues--insofar as they name a biological or ethological category--do not name a morally significant one.
The easy way to work with Office on your iPad or Mac Are you a Mac user who isn't accustomed to working with Microsoft Office? Consider this friendly guide your go-to reference! Written in plain English and packed with easy-to-follow, step-by-step instructions, Office for iPad and Mac For Dummies walks you through every facet of Office, from installing the software and opening files to working with Word, Excel, PowerPoint, and Outlook-and beyond. Plus, you'll discover how to manage files, share content and collaborate online through social media, and find help when you need it. Two things a
Mehta, Saurabh; Kwak, Kyung Sup
The wireless personal area network (WPAN) is an emerging wireless technology for future short range indoor and outdoor communication applications. The IEEE 802.15.3 medium access control (MAC) is proposed to coordinate the access to the wireless medium among the competing devices, especially for short range and high data rate applications in home networks. In this paper we use analytical modeling to study the performance analysis of WPAN (IEEE 802.15.3) MAC in terms of throughput, efficient bandwidth utilization, and delay with various ACK policies under error channel condition. This allows us to introduce a K-Dly-ACK-AGG policy, payload size adjustment mechanism, and Improved Backoff algorithm to improve the performance of the WPAN MAC. Performance evaluation results demonstrate the impact of our improvements on network capacity. Moreover, these results can be very useful to WPAN application designers and protocol architects to easily and correctly implement WPAN for home networking.
Full Text Available The wireless personal area network (WPAN is an emerging wireless technology for future short range indoor and outdoor communication applications. The IEEE 802.15.3 medium access control (MAC is proposed to coordinate the access to the wireless medium among the competing devices, especially for short range and high data rate applications in home networks. In this paper we use analytical modeling to study the performance analysis of WPAN (IEEE 802.15.3 MAC in terms of throughput, efficient bandwidth utilization, and delay with various ACK policies under error channel condition. This allows us to introduce a K-Dly-ACK-AGG policy, payload size adjustment mechanism, and Improved Backoff algorithm to improve the performance of the WPAN MAC. Performance evaluation results demonstrate the impact of our improvements on network capacity. Moreover, these results can be very useful to WPAN application designers and protocol architects to easily and correctly implement WPAN for home networking.
Pawar, Pranav M.; Nielsen, Rasmus Hjorth; Prasad, Neeli R.
and initiate security attacks that disturb the normal functioning of the network in a severe manner. Such attacks affect the performance of the network by increasing the energy consumption, by reducing throughput and by inducing long delays. Of all existing WSN attacks, MAC layer attacks are considered...... the most harmful as they directly affect the available resources and thus the nodes’ energy consumption. The first endeavour of this paper is to model the activities of MAC layer security attacks to understand the flow of activities taking place when mounting the attack and when actually executing it....... The second aim of the paper is to simulate these attacks on hybrid MAC mechanisms, which shows the performance degradation of aWSN under the considered attacks. The modelling and implementation of the security attacks give an actual view of the network which can be useful in further investigating secure...
Pérez, Daniel; Gasulla, Ivana; Capmany, José
We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.
Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system
Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.
Yang, Zhutian; Shi, Zhenguo; Jin, Chunlin
The Cognitive Radio Sensor Network (CRSN) is considered as a viable solution to enhance various aspects of the electric power grid and to realize a smart grid. However, several challenges for CRSNs are generated due to the harsh wireless environment in a smart grid. As a result, throughput and reliability become critical issues. On the other hand, the spectrum aggregation technique is expected to play an important role in CRSNs in a smart grid. By using spectrum aggregation, the throughput of CRSNs can be improved efficiently, so as to address the unique challenges of CRSNs in a smart grid. In this regard, we proposed Spectrum Aggregation Cognitive Receiver-Based MAC (SACRB-MAC), which employs the spectrum aggregation technique to improve the throughput performance of CRSNs in a smart grid. Moreover, SACRB-MAC is a receiver-based MAC protocol, which can provide a good reliability performance. Analytical and simulation results demonstrate that SACRB-MAC is a promising solution for CRSNs in a smart grid.
Kerczewski, Robert J.; Clements, Donna J.; Apaza, Rafael D.
As the development of standards for the aeronautical mobile airport communications system (AeroMACS) progresses, the process of identifying and quantifying appropriate uses for the system is progressing. In addition to defining important elements of AeroMACS standards, indentifying the systems uses impacts AeroMACS bandwidth requirements. Although an initial 59 MHz spectrum allocation for AeroMACS was established in 2007, the allocation may be inadequate; studies have indicated that 100 MHz or more of spectrum may be required to support airport surface communications. Hence additional spectrum allocations have been proposed. Vehicle health management (VHM) systems, which can produce large volumes of vehicle health data, were not considered in the original bandwidth requirements analyses, and are therefore of interest in supporting proposals for additional AeroMACS spectrum. VHM systems are an emerging development in air vehicle safety, and preliminary estimates of the amount of data that will be produced and transmitted off an aircraft, both in flight and on the ground, have been prepared based on estimates of data produced by on-board vehicle health sensors and initial concepts of data processing approaches. This allowed an initial estimate of VHM data transmission requirements for the airport surface. More recently, vehicle-level systems designed to process and analyze VHM data and draw conclusions on the current state of vehicle health have been undergoing testing and evaluation. These systems make use of vehicle system data that is mostly different from VHM data considered previously for airport surface transmission, and produce processed system outputs that will be also need to be archived, thus generating additional data load for AeroMACS. This paper provides an analysis of airport surface data transmission requirements resulting from the vehicle level reasoning systems, within the context of overall VHM data requirements.
Abdul Kareem PARCHUR
Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.
Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de
Full Text Available Recently, Wifi is one of the most useful technologies that can be used for detecting and counting MAC Address. This paper described using of WiFi scanner which carried out seven times circulated the bus. The method used WiFi and GPS are to counting MAC address as raw data from the pedestrian smartphone, bus passenger or WiFi devices near from the bus as long as the bus going around the route. There are seven processes to make map WiFi data.
The marriage of a mass-produced personal computer with the versatile VMEbus and CAMAC systems creates a cost-effective solution to many laboratory small system requirements. This paper describes MacVEE (Microcomputer Applied to the Control of VME Electronic Equipment), a novel system in which an Apple Macintosh computer is equipped with a special interface which allows it direct memory-mapped access to single or multiple VME and CAMAC crates interconnected by a ribbon cable bus. The bus is driven by an electronics plinth called MacPlinth, which attaches to the computer and becomes an integral part of it. (Auth.)
Ali Abedi Renani
In this paper, I seek to explain the similarity and disparity between MacIntyre’s moral theory and moral relativism. I will argue that MacIntyre’s moral theory can escape the charge of moral relativism because both his earlier social and his later metaphysical approaches appeal to some criteria, the human telos or universal human qualities respectively. The notion of telos is wider than the notion of function which is defined in social contexts. If there is a context-transcending notion of te...
The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review
Ferguson, Roscoe C.; Olivas, Zulema
The purpose of the Space Shuttle Cockpit Avionics Upgrade project (1999 2004) was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. An early version of this system was tested at the Johnson Space Center for one month by teams of astronauts. The results were positive, but NASA eventually cancelled the project towards the end of the development cycle. The goal to reduce crew workload and improve situational awareness resulted in the need for high performance Central Processing Units (CPUs). The choice of CPU selected was the PowerPC family, which is a reduced instruction set computer (RISC) known for its high performance. However, the requirement for radiation tolerance resulted in the re-evaluation of the selected family member of the PowerPC line. Radiation testing revealed that the original selected processor (PowerPC 7400) was too soft to meet mission objectives and an effort was established to perform trade studies and performance testing to determine a feasible candidate. At that time, the PowerPC RAD750s were radiation tolerant, but did not meet the required performance needs of the project. Thus, the final solution was to select the PowerPC 7455. This processor did not have a radiation tolerant version, but had some ability to detect failures. However, its cache tags did not provide parity and thus the project incorporated a software strategy to detect radiation failures. The strategy was to incorporate dual paths for software generating commands to the legacy Space Shuttle avionics to prevent failures due to the softness of the upgraded avionics.
Spady, Richard; Stouli, Sami
We propose dual regression as an alternative to the quantile regression process for the global estimation of conditional distribution functions under minimal assumptions. Dual regression provides all the interpretational power of the quantile regression process while avoiding the need for repairing the intersecting conditional quantile surfaces that quantile regression often produces in practice. Our approach introduces a mathematical programming characterization of conditional distribution f...
Batsell, S G; Jong, T L; Walkup, J F; Krile, T F
A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.
A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages
Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans
Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight
Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.
... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...
Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while
Duff, I.S.; Reid, J.K.
This book presents the papers given at a conference which reviewed the new developments in parallel and vector processing. Topics considered at the conference included hardware (array processors, supercomputers), programming languages, software aids, numerical methods (e.g., Monte Carlo algorithms, iterative methods, finite elements, optimization), and applications (e.g., neutron transport theory, meteorology, image processing)
This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.
The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are
This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes
Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...
Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.
This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable
David Tung Chong Wong
Full Text Available This survey paper presents the state-of-the-art directional medium access control (MAC protocols in wireless ad hoc and sensor networks (WAHSNs. The key benefits of directional antennas over omni-directional antennas are longer communication range, less multipath interference, more spatial reuse, more secure communications, higher throughput and reduced latency. However, directional antennas lead to single-/multi-channel directional hidden/exposed terminals, deafness and neighborhood, head-of-line blocking, and MAC-layer capture which need to be overcome. Addressing these problems and benefits for directional antennas to MAC protocols leads to many classes of directional MAC protocols in WAHSNs. These classes of directional MAC protocols presented in this survey paper include single-channel, multi-channel, cooperative and cognitive directional MACs. Single-channel directional MAC protocols can be classified as contention-based or non-contention-based or hybrid-based, while multi-channel directional MAC protocols commonly use a common control channel for control packets/tones and one or more data channels for directional data transmissions. Cooperative directional MAC protocols improve throughput in WAHSNs via directional multi-rate/single-relay/multiple-relay/two frequency channels/polarization, while cognitive directional MAC protocols leverage on conventional directional MAC protocols with new twists to address dynamic spectrum access. All of these directional MAC protocols are the pillars for the design of future directional MAC protocols in WAHSNs.
Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.
Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.
Law, Y.W.; Hartel, Pieter H.; den Hartog, Jeremy; Havinga, Paul J.M.
We argue that among denial-of-service (DoS) attacks, link-layer jamming is a more attractive option to attackers than radio jamming is. By exploiting the semantics of the link-layer protocol (aka MAC protocol), an attacker can achieve better efficiency than blindly jamming the radio signals alone.
Law, Y.W.; Hartel, Pieter H.; den Hartog, Jeremy; Havinga, Paul J.M.
We argue that among denial-of-service (DoS) attacks, link-layer jamming is a more attractive option to attackers than radio jamming is. By exploiting the semantics of the link-layer protocol (aka MAC protocol), an attacker can achieve better efficiency than blindly jamming the radio signals alone.
Full Text Available In Wireless Body Area Networks (WBANs, every healthcare application that is based on physical sensors is responsible for monitoring the vital signs data of patient. WBANs applications consist of heterogeneous and dynamic traffic loads. Routine patient’s observation is described as low-load traffic while an alarming situation that is unpredictable by nature is referred to as high-load traffic. This paper offers a thematic review of traffic adaptive Medium Access Control (MAC protocols in WBANs. First, we have categorized them based on their goals, methods, and metrics of evaluation. The Zigbee standard IEEE 802.15.4 and the baseline MAC IEEE 802.15.6 are also reviewed in terms of traffic adaptive approaches. Furthermore, a comparative analysis of the protocols is made and their performances are analyzed in terms of delay, packet delivery ratio (PDR, and energy consumption. The literature shows that no review work has been done on traffic adaptive MAC protocols in WBANs. This review work, therefore, could add enhancement to traffic adaptive MAC protocols and will stimulate a better way of solving the traffic adaptivity problem.
Sport philosophy is in crisis. This subdiscipline of kinesiology garners little to no respect and few tenure track lines in kinesiology departments. Why is this the case? Why isn't philosophy held in greater esteem? Is it possible that philosopher Alasdair MacIntyre's (2009) diagnosis found in "God, Philosophy, Universities" could…
famous mathematician Oscar Zariski, well known for his work in algebraic geometry, at. Johns Hopkins University, following him to Harvard University to study with him for a year. There was a break in her studies for many years following her marriage in 1941 to. W al ter Mac Williams, an engineer, and the birth and raising of ...
The MacDonald Scabbler is a small, hand held machine suitable for use in cleaning and roughening concrete surfaces, It weighs 308 pounds (140 kg), has 11 cutting heads, and, as a power source, requires a compressor capable of delivering 365 cubic foo...
Hotz, Henry B.
Context for this information. MacOS X login process and available hooks. Authorization Services configuration. Authorization Services plug-in s. Kerberos plug-in s. Other bugs and recommendations. Authorization Services Called by loginwindow, screen saver and fast user switching. It calls Directory Services, Login Hook, and Login Items (System Preferences).
Muheim, Claudio; Götzke, Hansjörg; Eriksson, Anna U.
molecules that make the outer membrane of Escherichia coli more permeable. We identified MAC13243, an inhibitor of the periplasmic chaperone LolA that traffics lipoproteins from the inner to the outer membrane. We observed that cells were (1) more permeable to the fluorescent probe 1-N...
Full Text Available This article deals with the principles of synergy effect of mechatronical aided concept (MAC to the design of intelligent transport vehicles products applying CA technologies and virtual reality design methods. Also includes presentation of intelligent railway vehicle development.
The K Basins Materials Accounting (MAC) programs had some improvements made to it to to change slightly the access authorized users had to the modification of critical data. This ATP describes how the code was to be tested to verify its correctness
Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.
This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor
Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I
The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)
While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....
Morshed, S.; Dimitrova, D.C.; Brogle, M.; Braun, T.; Heijenk, Gerhard J.
Energy-constrained behavior of sensor nodes is one of the most important criteria for successful deployment of wireless sensor net- works. The medium access control (MAC) protocol determines the time a sensor node transceiver spends listening or transmitting, and hence the energy consumption of the
Baehler, P.; Bosco, N.; Lingjaerde, T.; Ljuslin, C.; Van Praag, A.; Werner, P.
The XOP processor has been designed for trigger calculation and data compression in high energy physics experiments. Therefore, emphasis has been placed upon fast execution and high input/output rate. The fast execution is achieved by a wide instruction word holding operations which are executed concurrently. Thus, the arithmetic operations, data address calculations, data accessing, condition checking, loop count checking and next instruction evaluation all overlap in time. In conventional micro-processors these operations are performed sequentially. In addition, the instruction set comprises not only the classical computer instructions, but also specialized instructions suitable for trigger calculations, such as bit search, population count, loose compare and vector instructions. In order to achieve a high input/output rate, each XOP ECLine interface board is equipped with an input and an output port which fulfil the LeCroy ECLine specifications. The autonomous input port allows a data rate of 40 Mbytes/sec, while the program controlled output port allows 20 Mbytes/sec. For Fastbus based systems a dual Fastbus master interface is under design which allows to build up a Fastbus multi-processor system. This design is being done in collaboration with LAPP Annecy for the CERN Lep L3 experiment. Their scheme comprises 4-5 XOP processors, each of them with a master interface on a data input segment and a master interface on a data output segment. This paper describes the structure of the XOP processor, the interface capabilities and the software development and debugging tools. (Auth.)
Diskin, Jill A.; FitzGerald, Patricia
Describes specific applications of the Macintosh computer at Carnegie-Mellon University Libraries, where MacPaint was used as a flexible, easy to use, and powerful tool to produce informational, instructional, and promotional signage. Profiles of system hardware and software, an evaluation of the computer program MacPaint, and MacPaint signage…
van Hoesel, L.F.W.; Dal Pont, L.; Havinga, Paul J.M.
In this document the design of a MAC protocol for wireless sensor networks is discussed. The autonomous decentralized TDMA based MAC protocol minimizes power consumtion by efficiency implementing unicast/omnicast, scheduled rendezvous times and wakeup calls. The MAC protocol is an ongoing research
Sadler, Glenn Edward
Discusses the life and writings of George MacDonald (1824-1905). Suggests that the most striking feature of MacDonald's children's books is his sensitivity toward spiritual values and the power of change within the lives of his characters. Appends a list of questions to stimulate student response to MacDonald's writings. (RS)
Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.
To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user
Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.
Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.
With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods
Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.
In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.
Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)
This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.
Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.
VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)
algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system
Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.
AFRL-OSR-VA-TR-2014-0132 SILICON PROCESSORS USING ORGANICALLY RECONFIGURABLE TECHNIQUES ( SPORT ) Dennis Prather UNIVERSITY OF DELAWARE Final Report 05...5a. CONTRACT NUMBER Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) 5b. GRANT NUMBER FA9550-10-1-0363 5c...Contract: Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) Contract #: FA9550-10-1-0363 Reporting Period: 1 July 2010 – 31 December
Kaicher, Michael P.; Wilhelm, Frank K. [Theoretical Physics, Saarland University, 66123 Saarbruecken (Germany); Love, Peter J. [Department of Physics and Astronomy, Tufts University, Medford, MA 02155 (United States)
Quantum chemistry is the most promising civilian application for quantum processors to date. We study its adaptation to superconducting (sc) quantum systems, computing the ground state energy of LiH through a variational hybrid quantum classical algorithm. We demonstrate how interactions native to sc qubits further reduce the amount of quantum resources needed, pushing sc architectures as a near-term candidate for simulations of more complex atoms/molecules.
The Supervisory Control and Diagnostic System (SCDS) for the Mirror Fusion Test Facility (MFTF) consists of nine 32-bit minicomputers arranged in a tightly coupled distributed computer system utilizing a share memory as the data exchange medium. Debugging of more than one program in the multi-processor environment is a difficult process. This paper describes what new tools were developed and how the testing of software is performed in the SCDS for the MFTF project
Monowar, Muhammad; Hassan, Mohammad; Bajaber, Fuad; Al-Hussein, Musaed; Alamri, Atif
The emergence of heterogeneous applications with diverse requirements for resource-constrained Wireless Body Area Networks (WBANs) poses significant challenges for provisioning Quality of Service (QoS) with multi-constraints (delay and reliability) while preserving energy efficiency. To address such challenges, this paper proposes McMAC, a MAC protocol with multi-constrained QoS provisioning for diverse traffic classes in WBANs. McMAC classifies traffic based on their multi-constrained QoS de...
Lee, Kwang-Il; Hwang, SungJae; Yoon, DongHwa
Dual Modular Redundancy (DMR) is mainly used to implement these safety control systems. DMR is conveyed when components of a system are duplicated, providing another component in case one should fault or fail. This feature has a high availability and large fault tolerant. It provides zero downtime that is required for nuclear power plants. So nuclear power plant has been commercialized by multiple redundant systems. The following paper, we propose a Virtual Modular Redundancy (VMR) rather than physical triple of the Programmable Logic Controller (PLC) processor module to ensure the reliability of the nuclear power plant control system. VMR implementation minimizes design changes to continue to use the commercially available redundant system. Also, the purpose of the VMR is to improve the efficiency and reliability in many ways, such as fault tolerant and fail-safe and cost. VMR guarantees a wide range of reliable fault recovery, fault tolerance, etc. It is prevented before it causes great damages due to the continuous failure of the two modules. The reliable communication speed is slow and also it has a small bandwidth. It is a great loss in the safety control system. However, VMR aims to avoid nuclear power plants that were suspended due to fail-safe. It is not for the purpose of commonly used. Application of VMR is actually expected to require a lot of research and trial and error until they adapt to the nuclear regulatory and standards
Lee, Kwang-Il; Hwang, SungJae; Yoon, DongHwa [SOOSAN ENS Co., Seoul (Korea, Republic of)
Dual Modular Redundancy (DMR) is mainly used to implement these safety control systems. DMR is conveyed when components of a system are duplicated, providing another component in case one should fault or fail. This feature has a high availability and large fault tolerant. It provides zero downtime that is required for nuclear power plants. So nuclear power plant has been commercialized by multiple redundant systems. The following paper, we propose a Virtual Modular Redundancy (VMR) rather than physical triple of the Programmable Logic Controller (PLC) processor module to ensure the reliability of the nuclear power plant control system. VMR implementation minimizes design changes to continue to use the commercially available redundant system. Also, the purpose of the VMR is to improve the efficiency and reliability in many ways, such as fault tolerant and fail-safe and cost. VMR guarantees a wide range of reliable fault recovery, fault tolerance, etc. It is prevented before it causes great damages due to the continuous failure of the two modules. The reliable communication speed is slow and also it has a small bandwidth. It is a great loss in the safety control system. However, VMR aims to avoid nuclear power plants that were suspended due to fail-safe. It is not for the purpose of commonly used. Application of VMR is actually expected to require a lot of research and trial and error until they adapt to the nuclear regulatory and standards.
Sanders, G.H.; Butler, H.S.; Cooper, M.D.
A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering
Ogrady, E. P.; Wang, C.-H.
A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.
Piccinelli, Emiliano; Sannino, Roberto
The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.
Rangwalla, I.J.; Korn, D.J.; Nablo, S.V.
The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NO x which can be transported from the process zone by the product into the work area. Since the tolerable levels for O 3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O 2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O 2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O 2 ). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O 2 ) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O 2 ) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)
We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.
ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)
Full Text Available This article centers on the thought of Alasdair MacIntyre, whose most prominente work, After Virtue, is considered a classic of political science. In contrast with other reviews, this article will examine After Virtue within the broader context of MacIntyre’s thinking and publications. An overview of MacIntyre’s literary corpus and the evolution of his thinking will shed light on the volume examined and trace certain ideas that are characteristic of this Scottish political philosopher. Matters that remained unsettled in After Virtue have become over time more defined in MacIntyre’s thinking, such as the influence exerted upon him by Thomas Aquinas.
Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus
The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv
Mac OS X Snow Leopard for Power Users: Advanced Capabilities and Techniques is for Mac OS X users who want to go beyond the obvious, the standard, and the easy. If want to dig deeper into Mac OS X and maximize your skills and productivity using the world's slickest and most elegant operating system, then this is the book for you. Written by Scott Granneman, an experienced teacher, developer, and consultant, Mac OS X for Power Users helps you push Mac OS X to the max, unveiling advanced techniques and options that you may have not known even existed. Create custom workflows and apps with Automa
Van C. Lansingh; Marissa J. Carter; Kristen A. Eckert; Kevin L. Winthrop; João M. Furtado; Serge Resnikoff
Purpose: One barrier to cataract surgery is its high price in some countries. This study aims to understand to what extent the price of cataract surgery is over- or undervalued and whether it varies in relation to GDP using The Economist newspaper Big Mac Index (BMcI) methodology, which measures the purchasing power parity between different currencies. Methods: Peer-reviewed articles containing information on cataract surgery prices were searched from 1993 to June 2012 in databases. Ophtha...
The ITER Management Advisory Committee (MAC) Meeting was held on 28 June 2000 in Moskow, Russia. The main topics were the consideration of the report by the director on the ITER EDA status, the review of the work program, the review of the joint fund, the review of a schedule of ITER meetings and initial discussion and consideration on the disposition of R and D hardware and facilities and other dispositions relating to the termination of the EDA
Steffey, Eugene P; Pascoe, Peter J
To quantitate the dose- and time-related magnitude of the anesthetic sparing effect of, and selected physiological responses to detomidine during isoflurane anesthesia in horses. Randomized cross-over study. Three, healthy, young adult horses weighing 485 ± 14 kg. Horses were anesthetized on two occasions to determine the minimum alveolar concentration (MAC) of isoflurane in O 2 and then to measure the anesthetic sparing effect (time-related MAC reduction) following IV detomidine (0.03 and 0.06 mg kg -1 ). Selected common measures of cardiopulmonary function, blood glucose and urinary output were also recorded. Isoflurane MAC was 1.44 ± 0.07% (mean ± SEM). This was reduced by 42.8 ± 5.4% and 44.8 ± 3.0% at 83 ± 23 and 125 ± 36 minutes, respectively, following 0.03 and 0.06 mg kg -1 , detomidine. The MAC reduction was detomidine dose- and time-dependent. There was a tendency for mild cardiovascular and respiratory depression, especially following the higher detomidine dose. Detomidine increased both blood glucose and urine flow; the magnitude of these changes was time- and dose-dependent CONCLUSIONS: Detomidine reduces anesthetic requirement for isoflurane and increases blood glucose concentration and urine flow in horses. These changes were dose- and time-related. The results imply potent anesthetic sparing actions by detomidine. The detomidine-related increased urine flow should be considered in designing anesthetic protocols for individual horses. Copyright © 2002 Association of Veterinary Anaesthetists and American College of Veterinary Anesthesia and Analgesia. Published by Elsevier Ltd. All rights reserved.
Rico García, Cristina; Lehner, Andreas; Robertson, Patrick; Strang, Thomas
The investigation of infrastructureless safety applications in dierent transportation systems is a hot research topic. The nodes in thevnetwork are designed to advertise to the rest of the nodes informationabout the current traffic situation by means of short beacon messages containing speed, direction, positions and other relevant safety information. The scheduling should be organized by the MAC layer so that the transmitted messages arrive successfully as soon as possible at the recei...
A step-by-step online tutorial about LHC@home for Mac users by Alexandre Racine. It contains detailed instructions on how-to-join this volunteer computing project. There are 3 screen capture videos with the real installation process accelerated attached to the event page. This 5' video is linked from http://lhcathome.web.cern.ch/join-us Also from the CDS e-learning category.
Lee Jae Won; Choi Jin Ho; Jin Dae Ho
In this paper, we give the explicit determinations of dual plane curves, general dual helices and dual slant helices in terms of its dual curvature and dual torsion as a fundamental theory of dual curves in a dual 3-space
Blume, H.; Alexandru, R.; Applegate, R.; Giordano, T.; Kamiya, K.; Kresina, R.
In a digital diagnostic imaging department, the majority of operations for handling and processing of images can be grouped into a small set of basic operations, such as image data buffering and storage, image processing and analysis, image display, image data transmission and image data compression. These operations occur in almost all nodes of the diagnostic imaging communications network of the department. An image processor architecture was developed in which each of these functions has been mapped into hardware and software modules. The modular approach has advantages in terms of economics, service, expandability and upgradeability. The architectural design is based on the principles of hierarchical functionality, distributed and parallel processing and aims at real time response. Parallel processing and real time response is facilitated in part by a dual bus system: a VME control bus and a high speed image data bus, consisting of 8 independent parallel 16-bit busses, capable of handling combined up to 144 MBytes/sec. The presented image processor is versatile enough to meet the video rate processing needs of digital subtraction angiography, the large pixel matrix processing requirements of static projection radiography, or the broad range of manipulation and display needs of a multi-modality diagnostic work station. Several hardware modules are described in detail. For illustrating the capabilities of the image processor, processed 2000 x 2000 pixel computed radiographs are shown and estimated computation times for executing the processing opera-tions are presented.
Full Text Available Mobile and wireless networks are the integrant infrastructure of mobile and pervasive computing that aims at providing transparent and preferred information and services for people anytime anywhere. In such environments, end-to-end network bandwidth is crucial to improve user's transparent experience when providing on-demand services such as mobile video playing. As a result, powerful computing power is required for networked nodes, especially for routers. General-purpose processors cannot meet such requirements due to their limited processing ability, and poor programmability and scalability. Intel's network processor IXP is specially designed for fast packet processing to achieve a broad bandwidth. IXP provides a large number of registers to reduce the number of memory accesses. Registers in an IXP are physically partitioned as two banks so that two source operands in an instruction have to come from the two banks respectively, which makes the IXP register allocation tricky and different from conventional ones. In this paper, we investigate an approach for efficiently generating balanced bipartite graph and register allocation algorithms for the dual-bank register allocation in IXPs. The paper presents a graph uniform 2-way partition algorithm (FPT, which provides an optimal solution to the graph partition, and a heuristic algorithm for generating balanced bipartite graph. Finally, we design a framework for IXP register allocation. Experimental results demonstrate the framework and the algorithms are efficient in register allocation for IXP network processors.
Wang Tao; Sang Xin-Zhu; Yan Bin-Bin; Li Yan; Song Fei-Jun; Zhang Xia; Wang Kui-Ru; Yuan Jin-Hui; Yu Chong-Xiu; Ai Qi; Chen Xiao; Zhang Ying; Chen Gen-Xiang; Xiao Feng; Kamal Alameh
Frequency-tunable microwave signal generation is proposed and experimentally demonstrated with a dual-wavelength single-longitudinal-mode (SLM) erbium-doped fiber ring laser based on a digital Opto-DMD processor and four-wave mixing (FWM) in a high-nonlinear photonic crystal fiber (PCF). The high-nonlinear PCF is employed for the generation of the FWM to obtain stable and uniform dual-wavelength oscillation. Two different short passive sub-ring cavities in the main ring cavity serve as mode filters to make SLM lasing. The two lasing wavelengths are electronically selected by loading different gratings on the Opto-DMD processor controlled with a computer. The wavelength spacing can be smartly adjusted from 0.165 nm to 1.08 nm within a tuning accuracy of 0.055 nm. Two microwave signals at 17.23 GHz and 27.47 GHz are achieved. The stability of the microwave signal is discussed. The system has the ability to generate a 137.36-GHz photonic millimeter signal at room temperature
A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.
Lu, Shuo; Zgurskaya, Helen I
The Escherichia coli MacAB-TolC transporter has been implicated in efflux of macrolide antibiotics and secretion of enterotoxin STII. In this study, we found that purified MacA, a periplasmic membrane fusion protein, contains one tightly bound rough core lipopolysaccharide (R-LPS) molecule per MacA molecule. R-LPS was bound specifically to MacA protein with affinity exceeding that of polymyxin B. Sequence analyses showed that MacA contains two high-density clusters of positively charged amino acid residues located in the cytoplasmic N-terminal domain and the periplasmic C-terminal domain. Substitutions in the C-terminal cluster reducing the positive-charge density completely abolished binding of R-LPS. At the same time, these substitutions significantly reduced the functionality of MacA in the protection of E. coli against macrolides in vivo and in the in vitro MacB ATPase stimulation assays. Taken together, our results suggest that R-LPS or a similar glycolipid is a physiological substrate of MacAB-TolC.
Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.
Holmes, M.; Thorne, A.R.
The design of a graphics processor is described which takes into account known and anticipated user requirements, the availability of cheap minicomputers, the state of integrated circuit technology, and the overall need to minimise cost for a given performance. The main user needs are the ability to display large high resolution pictures, and to dynamically change the user's view in real time by means of fast coordinate processing hardware. The transformations that can be applied to 2D or 3D coordinates either singly or in combination are: translation, scaling, mirror imaging, rotation, and the ability to map the transformation origin on to any point on the screen. (author)
Dix, G.E.; Congdon, S.P.
BWR [boiling water reactor] nuclear design is a complicated process, involving trade-offs among a variety of conflicting objectives. Complex computer calculations and usually required for each design iteration. GE Nuclear Energy has implemented a system where the evaluations are performed interactively on a large number of small microcomputers. This approach minimizes the time it takes to carry out design iterations even through the processor speeds are low compared with modern super computers. All of the desktop microcomputers are linked to a common data base via an ethernet communications system so that design data can be shared and data quality can be maintained
This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves
Lee, T.D.; Chou, K.C.; Zichichi, A.
The book's contents include: Lattice Gauge Theory Lectures: Introduction and Current Fermion Simulations; Monte Carlo Algorithms for Lattice Gauge Theory; Specialized Computers for Lattice Gauge Theory; Lattice Gauge Theory at Finite Temperature: A Monte Carlo Study; Computational Method - An Elementary Introduction to the Langevin Equation, Present Status of Numerical Quantum Chromodynamics; Random Lattice Field Theory; The GF11 Processor and Compiler; and The APE Computer and First Physics Results; Columbia Supercomputer Project: Parallel Supercomputer for Lattice QCD; Statistical and Systematic Errors in Numerical Simulations; Monte Carlo Simulation for LGT and Programming Techniques on the Columbia Supercomputer; Food for Thought: Five Lectures on Lattice Gauge Theory
Hicks, H.R.; Lynch, V.E.
FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult
We uncover a novel solution of the 't Hooft anomaly matching conditions for QCD. Interestingly in the perturbative regime the new gauge theory, if interpreted as a possible QCD dual, predicts the critical number of flavors above which QCD in the nonperturbative regime, develops an infrared stable...
Bonamigo, M.; Grillo, C. [Dark Cosmology Centre, Niels Bohr Institute, University of Copenhagen, Juliane Maries Vej 30, DK-2100 Copenhagen (Denmark); Ettori, S. [INAF, Osservatorio Astronomico di Bologna, Via Piero Gobetti, 93/3, 40129 Bologna (Italy); Caminha, G. B.; Rosati, P. [Dipartimento di Fisica e Scienze della Terra, Università degli Studi di Ferrara, Via Saragat 1, I-44122 Ferrara (Italy); Mercurio, A. [INAF—Osservatorio Astronomico di Capodimonte, Via Moiariello 16, I-80131 Napoli (Italy); Annunziatella, M. [INAF—Osservatorio Astronomico di Trieste, Via G.B. Tiepolo, 11 I-34143 Trieste (Italy); Balestra, I. [University Observatory Munich, Scheinerstrasse 1, D-81679 Munich (Germany); Lombardi, M., E-mail: email@example.com [Dipartimento di Fisica, Università degli Studi di Milano, via Celoria 16, I-20133 Milano (Italy)
We present a novel approach for a combined analysis of X-ray and gravitational lensing data and apply this technique to the merging galaxy cluster MACS J0416.1–2403. The method exploits the information on the intracluster gas distribution that comes from a fit of the X-ray surface brightness and then includes the hot gas as a fixed mass component in the strong-lensing analysis. With our new technique, we can separate the collisional from the collision-less diffuse mass components, thus obtaining a more accurate reconstruction of the dark matter distribution in the core of a cluster. We introduce an analytical description of the X-ray emission coming from a set of dual pseudo-isothermal elliptical mass distributions, which can be directly used in most lensing softwares. By combining Chandra observations with Hubble Frontier Fields imaging and Multi Unit Spectroscopic Explorer spectroscopy in MACS J0416.1–2403, we measure a projected gas-to-total mass fraction of approximately 10% at 350 kpc from the cluster center. Compared to the results of a more traditional cluster mass model (diffuse halos plus member galaxies), we find a significant difference in the cumulative projected mass profile of the dark matter component and that the dark matter over total mass fraction is almost constant, out to more than 350 kpc. In the coming era of large surveys, these results show the need of multiprobe analyses for detailed dark matter studies in galaxy clusters.
Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)
Cederman, Daniel; Hellstrom, Daniel; Sherrill, Joel; Bloom, Gedare; Patte, Mathieu; Zulianello, Marco
This paper presents the final result of an European Space Agency (ESA) activity aimed at improving the software support for LEON processors used in SMP configurations. One of the benefits of using a multicore system in a SMP configuration is that in many instances it is possible to better utilize the available processing resources by load balancing between cores. This however comes with the cost of having to synchronize operations between cores, leading to increased complexity. While in an AMP system one can use multiple instances of operating systems that are only uni-processor capable, a SMP system requires the operating system to be written to support multicore systems. In this activity we have improved and extended the SMP support of the RTEMS real-time operating system and ensured that it fully supports the multicore capable LEON processors. The targeted hardware in the activity has been the GR712RC, a dual-core core LEON3FT processor, and the functional prototype of ESA's Next Generation Multiprocessor (NGMP), a quad core LEON4 processor. The final version of the NGMP is now available as a product under the name GR740. An implementation of the Multicore Task Management API (MTAPI) has been developed as part of this activity to aid in the parallelization of applications for RTEMS SMP. It allows for simplified development of parallel applications using the task-based programming model. An existing space application, the Gaia Video Processing Unit, has been ported to RTEMS SMP using the MTAPI implementation to demonstrate the feasibility and usefulness of multicore processors for space payload software. The activity is funded by ESA under contract 4000108560/13/NL/JK. Gedare Bloom is supported in part by NSF CNS-0934725.
Moyer, Ruth A.
Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…
Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto
International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...
Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.
Wicks, Michael C
An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...
Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A
A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.
Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.
The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time
Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.
We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)
Wireless Mesh Networks (WMNs) have emerged to meet a need for a self-organized and self-configured multi-hop wireless network infrastructure. Low cost infrastructure and ease of deployment have made WMNs an attractive technology for last mile access. However, 802.11 based WMNs are subject to serious fairness issues. With backlogged TCP traffic, nodes which are two or more hops away from the gateway are subject to starvation, while the one-hop away node saturates the channel with its own local traffic. We study the interactions of TCP and IEEE 802.11 MAC in WMNs to aid us in understanding and overcoming the unfairness problem. We propose a Markov chain to capture the behavior of TCP sessions, particularly the impact on network throughput performance due to the effect of queue utilization and packet relaying. A closed form solution is derived to numerically derive the throughput. Based on the developed model, we propose a distributed MAC protocol called Timestamp-ordered MAC (TMAC), aiming to alleviate the unfairness problem in WMNs via a manipulative per-node scheduling mechanism which takes advantage of the age of each packet as a priority metric. Simulation is conducted to validate our model and to illustrate the fairness characteristics of TMAC. Our results show that TMAC achieves excellent resource allocation fairness while maintaining above 90% of maximum link capacity in parking lot and large grid topologies. Our work illuminates the factors affecting TCP fairness in WMNs. Our theoretical and empirical findings can be used in future research to develop more fairness-aware protocols for WMNs.
Wu, S.; Liu, K.; Huang, B.; Liu, F.
To extend the lifetime of wireless sensor networks, we proposed an intelligent balanced energy consumption cooperative MAC protocol (IBEC-CMAC) based on the multi-node cooperative transmission model. The protocol has priority to access high-quality channels for reducing energy consumption of each transmission. It can also balance the energy consumption among cooperative nodes by using high residual energy nodes instead of excessively consuming some node's energy. Simulation results show that IBEC-CMAC can obtain longer network lifetime and higher energy utilization than direct transmission.
Marcus, Allan B [Los Alamos National Laboratory
The Los Alamos National Laboratory (LANL) had a need for central configuration management of non-Windows computers. LANL has three to five thousand Macs and an equal number of Linux based systems. The primary goal was to be able to inventory all non-windows systems and patch Mc OS X systems. LANL examined a number of commercial and open source solutions and ultimately selected Puppet. This paper will discuss why we chose Puppet, how we implemented it, and some lessons we learned along the way.
M. Sivakumar; S. Saravanan
The main function of Medium Access Control (MAC) is to share the channel efficiently between all nodes. In the real-time scenario, there will be certain amount of wastage in bandwidth due to back-off periods. More bandwidth will be wasted in idle state if the back-off period is very high and collision may occur if the back-off period is small. So, an optimization is needed for this problem. The main objective of the work is to reduce delay due to back-off period thereby reducing collision and...
Grapes (0.28) 327 Sour Grapes, analog The Taming of the Shrew (0.22), Merry Wives 251 (0.18), S[11 stories], Sour Grapes (-0.19) Sour Grapes, literal... The Institute for the 0 1 Learning Sciences Northwestern University CD• 00 MAC/FAC: A MODEL OF SIMILARITY-BASED RETRIEVAL Kenneth D. Forbus Dedre...Gentner Keith Law Technical Report #59 • October 1994 94-35188 wit Establisthed in 1989 with the support of Andersen Consulting Form Approved REPORT
Younas Khan; Sheeraz Ahmed; Fakhri Alam Khan; Imran Ahmad; Saqib Shahid Rahim; M. Irfan Khattak
Idle listening issue arises when a sensor node listens to medium despite the absence of data which results in consumption of energy. ETEEM is a variant of Traffic Aware Energy Efficient MAC protocol (TEEM) which focuses on energy optimization due to reduced idle listening time and much lesser overhead on energy sources. It uses a novel scheme for using idle listening time of sensor nodes. The nodes are only active for small amount of time and most of the time, will be in sleep mode when no da...
Alvitez Muñoz, Julio César; Esquivel Porras, César Augusto; Slocovich Salcedo, Erick Rodolfo
El presente trabajo desarrolla una propuesta de valor en el ámbito del mercado de seguros de vida para ser implementada en Rímac Seguros, permitiendo asegurar a la empresa la sostenibilidad de su liderazgo a través del incremento de su participación en el mercado y la fidelización de sus clientes. Las condiciones en las que se desarrolla la industria de seguros en el mundo y en el Perú en particular, como la séptima en volumen de primas a nivel latinoamericano ofrece un mercado reducido ba...
Abuhlail, Jawad Y.
In this note we introduce and investigate the concepts of dual entwining structures and dual entwined modules. This generalizes the concepts of dual Doi-Koppinen structures and dual Doi-Koppinen modules introduced (in the infinite case over rings) by the author is his dissertation.
Dual pathology is defined as the association of two potentially epileptogenic lesions, hippocampal (sclerosis, neuronal loss) and extrahippocampal (temporal or extratemporal). Epileptic activity may be generated by either lesion and the relative importance of every lesion's epileptogenicity conditions the surgical strategy adopted. Most frequently associated with hippocampal sclerosis are cortical dysplasias. The common physiopathology of the two lesions is not clearly established. Extrahippocampal lesions may be undetectable on MRI (microdysgenesis, for example) and ictal discharge patterns may vary among dual pathology patients. The surgical strategy depends on the location of the extrahippocampal lesion and its relative role in seizure generation; however, reported surgical results suggest that simultaneous resection of mesial temporal structures along with the extrahippocampal lesion should be performed.
LI Meng; ZHANG Lin; XIAO Yong-kang; SHAN Xiu-ming
Energy and bandwidth are the scarce resources in ad hoc networks because most of the mobile nodes are battery-supplied and share the exclusive wireless medium. Integrating the power control into MAC protocol is a promising technique to fully exploit these precious resources of ad hoc wireless networks. In this paper, a new intelligent power-controlled Medium Access Control (MAC) (iMAC) protocol with dynamic neighbor prediction is proposed. Through the elaborate design of the distributed transmit-receive strategy of mobile nodes, iMAC greatly outperforms the prevailing IEEE 802.11 MAC protocols in not only energy conservation but also network throughput. Using the Dynamic Neighbor Prediction (DNP), iMAC performs well in mobile scenes. To the best of our knowledge, iMAC is the first protocol that considers the performance deterioration of power-controlled MAC protocols in mobile scenes and then proposes a solution. Simulation results indicate that DNP is important and necessary for power-controlled MAC protocols in mobile ad hoc networks.
Seyed Davoud Mousavi
Full Text Available Cooperative communication techniques have recently enabled wireless technologies to overcome their challenges. The main objective of these techniques is to improve resource allocation. In this paper, we propose a new protocol in medium access control (MAC of the IEEE 802.11 standard. In our new protocol, which is called Fair Cooperative MAC (FC-MAC, every relay node participates in cooperation proportionally to its provided cooperation gain. This technique improves network resource allocation by exploiting the potential capacity of all relay candidates. Simulation results demonstrate that the FC-MAC protocol presents better performance in terms of throughput, fairness, and network lifetime.
In this video tutorial for Microsoft Excel 2011 For Mac, expert author Guy Vaccaro teaches you to effectively utilize the features and functions of Excel through project based learning. You will complete various projects, and along they way learn to leverage the power of the most important features Excel 2011 has to offer the Mac user. Starting your training course with the creation of a spreadsheet to record and monitor sales data, you will learn the basics of what you can do with a spreadsheet. You will then move on to creating a Profit and Loss report, learning formulas along the way. Moving to score sheets for a sports day, you will discover conditional based formatting, lookups, and more. You then create a functional expense claim form, advancing your Excel expertise. Moving on to a sales contact management sheet, you will discover how you can manipulate text, and even create mail merges from Excel. Finally, you will utilize all your knowledge thus far to create a sales report, including charts, pivot ta...
Full Text Available Battery energy limitation has become a performance bottleneck for mobile ad hoc networks. IEEE 802.11 has been adopted as the current standard MAC protocol for ad hoc networks. However, it was developed without considering energy efficiency. To solve this problem, many modifications on IEEE 802.11 to incorporate power control have been proposed in the literature. The main idea of these power control schemes is to use a maximum possible power level for transmitting RTS/CTS and the lowest acceptable power for sending DATA/ACK. However, these schemes may degrade network throughput and reduce the overall energy efficiency of the network. This paper proposes autonomous power control MAC protocol (APCMP, which allows mobile nodes dynamically adjusting power level for transmitting DATA/ACK according to the distances between the transmitter and its neighbors. In addition, the power level for transmitting RTS/CTS is also adjustable according to the power level for DATA/ACK packets. In this paper, the performance of APCMP protocol is evaluated by simulation and is compared with that of other protocols.
Eyckmans, J.; Van Regemorter, D.; Van Steenberghe, V.
In this paper we present some numerical simulations with the MacGEM model to evaluate the consequences of the recent Marrakesh agreements and the defection of the USA for the Kyoto Protocol. MacGEM is a global marginal abatement cost model for carbon emissions from fossil fuel use based on the GEM-E3-World general equilibrium. Nonparticipation of the USA causes the equilibrium carbon price in Annex B countries to fall by approximately 50% since an important share of permit demand falls out. Carbon sinks enhancement activities enable Parties to fulfil their reduction commitment at lower compliance costs and cause the equilibrium permit price to decrease by 40%. Finally, it is shown that the former Soviet Union and central European countries have substantial monopoly power in the Kyoto carbon permit market. We conclude that the recent accords have eroded completely the Kyoto Protocol's emission targets but that they have the merit to have saved the international climate change negotiation framework
The increasing availability of asynchronous parallel processors has provided opportunities for original and useful work in scientific computing. However, the field of parallel computing is still in a highly volatile state, and researchers display a wide range of opinion about many fundamental questions such as models of parallelism, approaches for detecting and analyzing parallelism of algorithms, and tools that allow software developers and users to make effective use of diverse forms of complex hardware. This volume collects the work of researchers specializing in different aspects of parallel computing, who met to discuss the framework and the mechanics of numerical computing. The far-reaching impact of high-performance asynchronous systems is reflected in the wide variety of topics, which include scientific applications (e.g. linear algebra, lattice gauge simulation, ordinary and partial differential equations), models of parallelism, parallel language features, task scheduling, automatic parallelization techniques, tools for algorithm development in parallel environments, and system design issues
Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.
The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471
Krivda, M.; Alexandre, D.; Barnby, L.S.; Evans, D.; Jones, P.G.; Jusko, A.; Lietava, R.; Baillie, O. Villalobos; Pospíšil, J.
The ALICE Central Trigger Processor (CTP) at the CERN LHC has been upgraded for LHC Run 2, to improve the Transition Radiation Detector (TRD) data-taking efficiency and to improve the physics performance of ALICE. There is a new additional CTP interaction record sent using a new second Detector Data Link (DDL), a 2 GB DDR3 memory and an extension of functionality for classes. The CTP switch has been incorporated directly onto the new LM0 board. A design proposal for an ALICE CTP upgrade for LHC Run 3 is also presented. Part of the development is a low latency high bandwidth interface whose purpose is to minimize an overall trigger latency
A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.
An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint
The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of
Deppe, J.; Areti, H.; Atac, R.
We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs
Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are
Barron, M.; Downward, J.
A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation
Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.
A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table
Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria
In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.
Beer, G.; Sobinkovic, B.
In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors
Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.
Casasent, David P.; Baranoski, Edward J.
A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.
Smereka, Jacek; Ladny, Jerzy R; Naylor, Amanda; Ruetzler, Kurt; Szarpak, Lukasz
The aim of this study was to compare C-MAC videolaryngoscopy with direct laryngoscopy for intubation in simulated cervical spine immobilization conditions. The study was designed as a prospective randomized crossover manikin trial. 70 paramedics with immobilization (Scenario A); manual inline cervical immobilization (Scenario B); cervical immobilization using cervical extraction collar (Scenario C). Scenario A: Nearly all participants performed successful intubations with both MAC and C-MAC on the first attempt (95.7% MAC vs. 100% C-MAC), with similar intubation times (16.5s MAC vs. 18s C-MAC). Scenario B: The results with C-MAC were significantly better than those with MAC (pimmobilization. Copyright © 2017 Elsevier Inc. All rights reserved.
Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.
Barr, David R. W.; Dudek, Piotr
We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.
Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy
A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.
Collins, Michael D; Baer, Ralph N; Simpson, Harry J
Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America
The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de
Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi
Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)
Frison, Gianluca; Jørgensen, John Bagterp
In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...
David R. W. Barr
Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.
8 Figure 6: (a) Proposed on-demand single photon source based on dynamic cavity storage . (b) Example of a gate implementation...electronic architectures tuned to implement artificial neural networks that improve upon both computational speed and energy efficiency. 3.6 All...states are in the dual- rail logic representation. Approved for Public Release; Distribution Unlimited. 6 Figure 3: Schematic of two-photon
Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM
A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.
Hein, Irma M; Troost, Pieter W; Lindeboom, Robert; Benninga, Marc A; Zwaan, C Michel; van Goudoever, Johannes B; Lindauer, Ramón J L
An objective assessment of children's competence to consent to research participation is currently not possible. Age limits for asking children's consent vary considerably between countries, and, to our knowledge, the correlation between competence and children's age has never been systematically investigated. To test a standardized competence assessment instrument for children by modifying the MacArthur Competence Assessment Tool for Clinical Research (MacCAT-CR), to investigate its reliability and validity, and to examine the correlation of its assessment with age and estimate cutoff ages. This prospective study included children and adolescents aged 6 to 18 years in the inpatient and outpatient departments of allergology, gastroenterology, oncology, ophthalmology, and pulmonology from January 1, 2012, through January 1, 2014. Participants were eligible for clinical research studies, including observational studies and randomized clinical trials. Competence judgments by experts aware of the 4 relevant criteria-understanding, appreciation, reasoning, and choice-were used to establish the reference standard. The index test was the MacCAT-CR, which used a semistructured interview format. Interrater reliability, validity, and dimensionality of the MacCAT-CR and estimated cutoff ages for competence. Of 209 eligible patients, we included 161 (mean age, 10.6 years; 47.2% male). Good reproducibility of MacCAT-CR total and subscale scores was observed (intraclass correlation coefficient range, 0.68-0.92). We confirmed unidimensionality of the MacCAT-CR. By the reference standard, we judged 54 children (33.5%) to be incompetent; by the MacCAT-CR, 61 children (37.9%). Criterion-related validity of MacCAT-CR scores was supported by high overall accuracy in correctly classifying children as competent against the reference standard (area under the receiver operating characteristics curve, 0.78). Age was a good predictor of competence on the MacCAT-CR (area under the receiver
Buerger, L.; Gossanyi, A.; Parkanyi, T.; Szabo, G.; Vegh, E.
A multiprocessor process control system is described. During its development the reliability was the most important aspect because it is used in the computerized control of a 5 MW research reactor. DUAL-PROCESS is fully compatible with the earlier single processor control system PROCESS-24K. The paper deals in detail with the communication, synchronization, error detection and error recovery problems of the operating system. (author)
... National Library of Medicine Comorbidity or dual diagnosis - Opioid addiction, part 9 - English PDF Comorbidity or dual diagnosis - Opioid addiction, part 9 - español (Spanish) PDF Comorbidity or dual ...
Resumo. Os extratos e metabólitos secundários de plantas podem agir como agentes tóxicos e inibidores do da alimentação e do desenvolvimento em insetos. Neste estudo foi utilizado Oncopeltus fasciatus (Dallas (Hemiptera como modelo experimental a fim de avaliar as atividades do extrato etanólico bruto e frações obtidos das flores ou caules de Eremanthus erythropappus (DC. MacLeisch (Asteraceae, na mortalidade e sobre o desenvolvimento do inseto. A fração butanólica obtida do extrato etanólico mostrou toxidade sobre as ninfas de O. fasciatus, bem como atividade de inibição do crescimento. Os resultados sugerem que a fração butanólica de E. erythropappus possui substâncias ativas sobre a fisiologia, crescimento e desenvolvimento de insetos.
Hicks, Daniel J; Stapleford, Thomas A
“Practice” has become a ubiquitous term in the history of science, and yet historians have not always reflected on its philosophical import and in particular on its potential connections with ethics. This essay draws on the work of the virtue ethicist Alasdair MacIntyre to develop a theory of “communal practices” and explore how such an approach can inform the history of science, including allegations about the corruption of science by wealth or power, consideration of scientific ethics or “moral economies,” the role of values in science, the ethical distinctiveness (or not) of scientific vocations, and the relationship between history of science and the practice of science itself.
Ulwick, J. C.
Four Super Arcas rockets were launched at the Andoya Rocket Range, Norway, as part of the MAC/SINE campaign to measure electron density irregularities with high spatial resolution in the cold summer polar mesosphere. They were launched as part of two salvos: the turbulent/gravity wave salvo (3 rockets) and the EISCAT/SOUSY radar salvo (one rocket). In both salvos meteorological rockets, measuring temperature and winds, were also launched and the SOUSY radar, located near the launch site, measured mesospheric turbulence. Electron density irregularities and strong gradients were measured by the rocket probes in the region of most intense backscatter observed by the radar. The electron density profiles (8 to 4 on ascent and 4 on descent) show very different characteristics in the peak scattering region and show marked spatial and temporal variability. These data are intercompared and discussed.
Smee, S A; Scharfstein, G A; Qiu, Y; Brand, P C; Anand, D K; Broholm, C L
A novel doubly focusing neutron monochromator has been developed as part of the Multi-Analyzer Crystal Spectrometer (MACS) at the NIST Center for Neutron Research. The instrument utilizes a unique vertical focusing element that enables active vertical and horizontal focusing with a large, 357-crystal (1428 cm sup 2), array. The design significantly reduces the amount of structural material in the beam path as compared to similar instruments. Optical measurements verify the excellent focal performance of the device. Analytical and Monte Carlo simulations predict that, when mounted at the NIST cold-neutron source, the device should produce a monochromatic beam (DELTA E=0.2 meV) with flux phi>10 sup 8 n/cm sup 2 s. (orig.)
Full Text Available Abstract This paper presents an empirical investigation on the performance of body implant communication using radio frequency (RF technology. In body implant communication, the electrical properties of the body influence the signal propagation in several ways. We use a Perspex body model (30 cm diameter, 80 cm height and 0.5 cm thickness filled with a liquid that mimics the electrical properties of the basic body tissues. This model is used to observe the effects of body tissue on the RF communication. We observe best performance at 3cm depth inside the liquid. We further present a simulation study of several low-power MAC protocols for an on-body sensor network and discuss the derived results. Also, the traditional preamble-based TMDA protocol is extended towards a beacon-based TDMA protocol in order to avoid preamble collision and to ensure low-power communication.
Full Text Available This paper presents an empirical investigation on the performance of body implant communication using radio frequency (RF technology. In body implant communication, the electrical properties of the body influence the signal propagation in several ways. We use a Perspex body model (30 cm diameter, 80 cm height and 0.5 cm thickness filled with a liquid that mimics the electrical properties of the basic body tissues. This model is used to observe the effects of body tissue on the RF communication. We observe best performance at 3cm depth inside the liquid. We further present a simulation study of several low-power MAC protocols for an on-body sensor network and discuss the derived results. Also, the traditional preamble-based TMDA protocol is extended towards a beacon-based TDMA protocol in order to avoid preamble collision and to ensure low-power communication.
... diligence procedures that are required for investments, but we do not intend to change the fundamental... Federal Agricultural Mortgage Corporation Funding and Fiscal Affairs; Farmer Mac Investments and Liquidity... Mortgage Corporation Funding and Fiscal Affairs; Farmer Mac Investments and Liquidity Management AGENCY...
Amjad, Hussain; Syed Tauseef, Mohyud-Din; Ahmet, Yildirim
MacMillan's equations are extended to Poincaré's formalism, and MacMillan's equations for nonlinear nonholonomic systems are obtained in terms of Poincaré parameters. The equivalence of the results obtained here with other forms of equations of motion is demonstrated. An illustrative example of the theory is provided as well.
Leeper, Roy V.; Leeper, Kathie A.
Considers how public relation's search for a unifying theory may be fulfilled through application of Alasdair MacIntyre's concept of a "practice," a very specific and value-laden concept. Explores what it would mean to be a public relations practice in MacIntyre's concept of the term and argues that such an approach to public relations…
... the business planning period a required discussion of how factors might impact Farmer Mac's current... discussion of any expected changes to Farmer Mac's business plan that are likely to have a material impact on... conditions that cause increases in delinquency rates caused by any variety of factors (e.g., widespread...
Lindstrom, Marilyn M.; Mckay, David S.; Wentworth, Susan J.; Martinez, Rene R.; Mittlefehldt, David W.; Wang, Ming-Sheng; Lipschutz, Michael E.
MacAlpine Hills 88104 and 88105, anorthositic lunar meteorites recovered form the same area in Antartica, are characterized. Petrographic studies show that MAC88104/5 is a polymict breccia dominated by impact melt clasts. It is better classified as a fragmental breccia than a regolith breccia. The bulk composition is ferroan and highly aluminous (Al2O3-28 percent).
Morshed, S.; Heijenk, Geert
Energy-efficiency is an important requirement in the design of communication protocols for wireless sensor networks (WSN). TR-MAC is an energy-efficient medium access control (MAC) layer protocol for low power WSN that exploits transmitted-reference (TR) modulation in the physical layer. The
MAC organisms are able to grow, persist, and colonize in water distribution systems and may amplify in hospital hot water systems. This study examined the response of MAC organisms (M. avium, M. intracellulare, and MX) to a range of temperatures commonly associated with drinking...
van Kleunen, W.A.P.; Meratnia, Nirvana; Havinga, Paul J.M.
In this article we introduce a MAC protocol designed for underwater localization and time-synchronisation. The MAC protocol assumes a network of static reference nodes and allows blind nodes to be localized by listening-only to the beacon messages. Such a system is known to be very scalable. We show
Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.
This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs
Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.
A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made
Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.
The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor
Tongam Sihol Nababan
Full Text Available The aim of this study is to identify : (1 profile of exchange rate and purchasing power parity of IDR against US $ based on Big Mac Index compared to the exchange rate of other countries, and (2 the position of the Big Mac Affordability of Indonesia compared to other ASEAN countries. The results showed that based on Big Mac index during the period April 1998 up to January 2015, IDR exchange rate tends to be undervalued against the USA dollar. The cause of the currency tends to be in a position of undervalued due to the components of non-tradable have not been included in Big Mac index. The index of Big Mac Affordability indicates that there is a great disparity of income between Singapore and five other ASEAN countries. The purchasing power of the real income of the people in Singapore is nearly five times the real income of the people in Indonesia.
Kim, Sungryul; Yoo, Younghwan
Medium Access Control (MAC) delay which occurs between the anchor node's transmissions is one of the error sources in underwater localization. In particular, in AUV localization, the MAC delay significantly degrades the ranging accuracy. The Cramer-Rao Low Bound (CRLB) definition theoretically proves that the MAC delay significantly degrades the localization performance. This paper proposes underwater localization combined with multiple access technology to decouple the localization performance from the MAC delay. Towards this goal, we adopt hyperbolic frequency modulation (HFM) signal that provides multiplexing based on its good property, high-temporal correlation. Owing to the multiplexing ability of the HFM signal, the anchor nodes can transmit packets without MAC delay, i.e., simultaneous transmission is possible. In addition, the simulation results show that the simultaneous transmission is not an optional communication scheme, but essential for the localization of mobile object in underwater.
Kerczewski, Robert J.; Wilson, Jeffrey D.
Interference issues related to the operation of an aeronautical mobile airport communications system (AeroMACS) in the C-Band (specifically 5091-5150 MHz) is being investigated. The issue of primary interest is co-channel interference from AeroMACS into mobile-satellite system (MSS) feeder uplinks. The effort is focusing on establishing practical limits on AeroMACS transmissions from airports so that the threshold of interference into MSS is not exceeded. The analyses are being performed with the software package Visualyse Professional, developed by Transfinite Systems Limited. Results with omni-directional antennas and plans to extend the models to represent AeroMACS more accurately will be presented. These models should enable realistic analyses of emerging AeroMACS designs to be developed from NASA Test Bed, RTCA 223, and European results.
In this paper, we propose the efficient reliable multicast MAC protocol by which the AP (Access Point) can transmit reliably its multicast data frames to the recipients in the AP's one-hop or two-hop transmission range. The AP uses the STAs (Stations) that are directly associated with itself as the relays for the data delivery to the remote recipients that cannot be reached directly from itself. Based on the connectivity information among the recipients, the reliable multicast MAC protocol optimizes the number of the RAK (Request for ACK) frame transmissions in a reasonable computational time. Numerical examples show that our proposed MAC protocol significantly enhances the MAC performance compared with the BMMM (Batch Mode Multicast MAC) protocol that is extended to support the recipients that are in the AP's one-hop or two-hop transmission range in IEEE 802.11 wireless LANs.
Arefijamaal, Ali Akbar; Neyshaburi, Fahimeh Arabyani
In this paper we extend the notion of approximate dual to fusion frames and present some approaches to obtain dual and approximate alternate dual fusion frames. Also, we study the stability of dual and approximate alternate dual fusion frames.
Biri, S.; Buttsev, V.S.; Molnar, J.; Samojlov, V.N.
The functional and operational descriptions on PCA/INCREMENT MEMORY interface are discussed. The following is solved with this unit: connection between the analogue signal processor and PC, nuclear spectrum acquisition up to 2 24 -1 counts/channel using increment or decrement method, data read/write from or to memory via data bus PC during the spectrum acquisition. Dual ported memory organization is 4096x24 bit, increment cycle time at 4.77 MHz system clock frequency is 1.05 μs. 6 refs.; 2 figs
Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.
Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico
The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...
Muirhead, Dean; Carter, Layne; Williamson, Jill; Chambers, Antja
The ISS Urine Processor Assembly (UPA) was initially designed to achieve 85% recovery of water from pretreated urine on ISS. Pretreated urine is comprised of crew urine treated with flush water, an oxidant (chromium trioxide), and an inorganic acid (sulfuric acid) to control microbial growth and inhibit precipitation. Unfortunately, initial operation of the UPA on ISS resulted in the precipitation of calcium sulfate at 85% recovery. This occurred because the calcium concentration in the crew urine was elevated in microgravity due to bone loss. The higher calcium concentration precipitated with sulfate from the pretreatment acid, resulting in a failure of the UPA due to the accumulation of solids in the Distillation Assembly. Since this failure, the UPA has been limited to a reduced recovery of water from urine to prevent calcium sulfate from reaching the solubility limit. NASA personnel have worked to identify a solution that would allow the UPA to return to a nominal recovery rate of 85%. This effort has culminated with the development of a pretreatment based on phosphoric acid instead of sulfuric acid. By eliminating the sulfate associated with the pretreatment, the brine can be concentrated to a much higher concentration before calcium sulfate reach the solubility limit. This paper summarizes the development of this pretreatment and the testing performed to verify its implementation on ISS.
Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José
Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.
Ramsey, John K., Jr.; Ramsey, John K., Sr.
Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.
Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine
The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.
Hristov, Ivan; Goranov, Goran; Hristova, Radoslava
We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.
Full Text Available We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP” in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL. The results show 2 times better performance on KNL processor.
Park, Yong-Sung; Kim, Tae-Hyoung; Yun, Cheol-Won
Although copper functions as a cofactor in many physiological processes, copper overload leads to harmful effects in living cells. Thus, copper homeostasis is tightly regulated. However, detailed copper metabolic pathways have not yet been identified in filamentous fungi. In this report, we investigated the copper transcription factor AfMac1 ( A spergillus f umigatus Mac1 homolog) and identified its regulatory mechanism in A. fumigatus AfMac1 has domains homologous to the DNA-binding and copper-binding domains of Mac1 from Saccharomyces cerevisiae , and AfMac1 efficiently complemented Mac1 in S. cerevisiae Expression of Afmac1 resulted in CTR1 up-regulation, and mutation of the DNA-binding domain of Afmac1 failed to activate CTR1 expression in S. cerevisiae The Afmac1 deletion strain of A. fumigatus failed to grow in copper-limited media, and its growth was restored by introducing ctrC We found that AfMac1 specifically bound to the promoter region of ctrC based on EMSA. The AfMac1-binding motif 5'-TGTGCTCA-3' was identified from the promoter region of ctrC , and the addition of mutant ctrC lacking the AfMac1-binding motif failed to up-regulate ctrC in A. fumigatus Furthermore, deletion of Afmac1 significantly reduced strain virulence and activated conidial killing activity by neutrophils and macrophages. Taken together, these results suggest that AfMac1 is a copper transcription factor that regulates cellular copper homeostasis in A. fumigatus . © 2017 The Author(s); published by Portland Press Limited on behalf of the Biochemical Society.
Pourshaghaghi, H.R.; Fatemi, S.H.; Pineda de Gyvez, J.
In this paper, we present a novel robust sliding-mode controller for stabilizing supply voltage and clock frequency of dual core processors determined by dynamic voltage and frequency scaling (DVFS) methods in the presence of systematic and random variations. We show that maximum rejection for
Schoeberl, Martin; Schleuniger, Pascal; Puffitsch, Wolfgang
for low WCET bounds rather than high average case performance. Patmos is a dualissue, statically scheduled RISC processor. The instruction cache is organized as a method cache and the data cache is organized as a split cache in order to simplify the cache WCET analysis. To fill the dual-issue pipeline...
Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the authorÃ¢Â€Â²s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.
National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...
International Journal of Natural and Applied Sciences ... a simple developed compiler could generate the code of a simple programming language. ... It should be noted that such code generation must be done on a particular processor- for ...
.... Systems could be constructed for which serious security threats would be eliminated. This thesis explores the Intel IA-64 processor's hardware support and its relationship to software for building a secure system...
Valiant, Leslie; Skyum, Sven
It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....
Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.
An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.
Hummel, Richard J.; Fulp, Errin W.
Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.
National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...
Bonny, Mohamed Talal; Henkel, Jö rg
% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.
With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...
Sato, Hiroyuki; Ikesaka, Morio
This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)
National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....
Pelto, E. V.
Assembly processor program converts symbolic programming language to machine language. This program translates symbolic codes into computer understandable instructions, assigns locations in storage for successive instructions, and computer locations from symbolic addresses.
Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van
Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.
Prisagjanec, Milcho; Mitrevski, Pece
The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This tec...
Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.
A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)
Calzas, A.; Danon, G.; Bouquet, B.
GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)
Anand Nandakumar Shardul
In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...
Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico
The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...
Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A
The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...
Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico
The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...
Puetter, R. C.; Hier, R. G.
PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.
The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table
Fahy, J.B.; Kim, Y.
The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge
Mertoguno, S; Bourbakis, N G
This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.
Siryj, B. W.
Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.
Nicholas P. Greene
Full Text Available The MacB ABC transporter forms a tripartite efflux pump with the MacA adaptor protein and TolC outer membrane exit duct to expel antibiotics and export virulence factors from Gram-negative bacteria. Here, we review recent structural and functional data on MacB and its homologs. MacB has a fold that is distinct from other structurally characterized ABC transporters and uses a unique molecular mechanism termed mechanotransmission. Unlike other bacterial ABC transporters, MacB does not transport substrates across the inner membrane in which it is based, but instead couples cytoplasmic ATP hydrolysis with transmembrane conformational changes that are used to perform work in the extra-cytoplasmic space. In the MacAB-TolC tripartite pump, mechanotransmission drives efflux of antibiotics and export of a protein toxin from the periplasmic space via the TolC exit duct. Homologous tripartite systems from pathogenic bacteria similarly export protein-like signaling molecules, virulence factors and siderophores. In addition, many MacB-like ABC transporters do not form tripartite pumps, but instead operate in diverse cellular processes including antibiotic sensing, cell division and lipoprotein trafficking.
Greene, Nicholas P.; Kaplan, Elise; Crow, Allister; Koronakis, Vassilis
The MacB ABC transporter forms a tripartite efflux pump with the MacA adaptor protein and TolC outer membrane exit duct to expel antibiotics and export virulence factors from Gram-negative bacteria. Here, we review recent structural and functional data on MacB and its homologs. MacB has a fold that is distinct from other structurally characterized ABC transporters and uses a unique molecular mechanism termed mechanotransmission. Unlike other bacterial ABC transporters, MacB does not transport substrates across the inner membrane in which it is based, but instead couples cytoplasmic ATP hydrolysis with transmembrane conformational changes that are used to perform work in the extra-cytoplasmic space. In the MacAB-TolC tripartite pump, mechanotransmission drives efflux of antibiotics and export of a protein toxin from the periplasmic space via the TolC exit duct. Homologous tripartite systems from pathogenic bacteria similarly export protein-like signaling molecules, virulence factors and siderophores. In addition, many MacB-like ABC transporters do not form tripartite pumps, but instead operate in diverse cellular processes including antibiotic sensing, cell division and lipoprotein trafficking. PMID:29892271
Full Text Available Although the conventional duty cycle MAC protocols for Wireless Sensor Networks (WSNs such as RMAC perform well in terms of saving energy and reducing end-to-end delivery latency, they were designed independently and require an extra routing protocol in the network layer to provide path information for the MAC layer. In this paper, we propose a new cross-layer duty cycle MAC protocol with data forwarding supporting a pipeline feature (P-MAC for WSNs. P-MAC first divides the whole network into many grades around the sink. Each node identifies its grade according to its logical hop distance to the sink and simultaneously establishes a sleep/wakeup schedule using the grade information. Those nodes in the same grade keep the same schedule, which is staggered with the schedule of the nodes in the adjacent grade. Then a variation of the RTS/CTS handshake mechanism is used to forward data continuously in a pipeline fashion from the higher grade to the lower grade nodes and finally to the sink. No extra routing overhead is needed, thus increasing the network scalability while maintaining the superiority of duty-cycling. The simulation results in OPNET show that P-MAC has better performance than S-MAC and RMAC in terms of packet delivery latency and energy efficiency.
Full Text Available In wireless body area networks (WBANs, various sensors and actuators are placed on/inside the human body and connected wirelessly. WBANs have specific requirements for healthcare and medical applications, hence, standard protocols like the IEEE 802.15.4 cannot fulfill all the requirements. Consequently, many medium access control (MAC protocols, mostly derived from the IEEE 802.15.4 superframe structure, have been studied. Nevertheless, they do not support a differentiated quality of service (QoS for the various forms of traffic coexisting in a WBAN. In particular, a QoS-aware MAC protocol is essential for WBANs operating in the unlicensed Industrial, Scientific, and Medical (ISM bands, because different wireless services like Bluetooth, WiFi, and Zigbee may coexist there and cause severe interference. In this paper, we propose a priority-based adaptive MAC (PA-MAC protocol for WBANs in unlicensed bands, which allocates time slots dynamically, based on the traffic priority. Further, multiple channels are effectively utilized to reduce access delays in a WBAN, in the presence of coexisting systems. Our performance evaluation results show that the proposed PA-MAC outperforms the IEEE 802.15.4 MAC and the conventional priority-based MAC in terms of the average transmission time, throughput, energy consumption, and data collision ratio.
Bhandari, Sabin; Moh, Sangman
In wireless body area networks (WBANs), various sensors and actuators are placed on/inside the human body and connected wirelessly. WBANs have specific requirements for healthcare and medical applications, hence, standard protocols like the IEEE 802.15.4 cannot fulfill all the requirements. Consequently, many medium access control (MAC) protocols, mostly derived from the IEEE 802.15.4 superframe structure, have been studied. Nevertheless, they do not support a differentiated quality of service (QoS) for the various forms of traffic coexisting in a WBAN. In particular, a QoS-aware MAC protocol is essential for WBANs operating in the unlicensed Industrial, Scientific, and Medical (ISM) bands, because different wireless services like Bluetooth, WiFi, and Zigbee may coexist there and cause severe interference. In this paper, we propose a priority-based adaptive MAC (PA-MAC) protocol for WBANs in unlicensed bands, which allocates time slots dynamically, based on the traffic priority. Further, multiple channels are effectively utilized to reduce access delays in a WBAN, in the presence of coexisting systems. Our performance evaluation results show that the proposed PA-MAC outperforms the IEEE 802.15.4 MAC and the conventional priority-based MAC in terms of the average transmission time, throughput, energy consumption, and data collision ratio.
Monowar, Muhammad Mostafa; Hassan, Mohammad Mehedi; Bajaber, Fuad; Al-Hussein, Musaed; Alamri, Atif
The emergence of heterogeneous applications with diverse requirements for resource-constrained Wireless Body Area Networks (WBANs) poses significant challenges for provisioning Quality of Service (QoS) with multi-constraints (delay and reliability) while preserving energy efficiency. To address such challenges, this paper proposes McMAC,a MAC protocol with multi-constrained QoS provisioning for diverse traffic classes in WBANs. McMAC classifies traffic based on their multi-constrained QoS demands and introduces a novel superframe structure based on the "transmit-whenever-appropriate"principle, which allows diverse periods for diverse traffic classes according to their respective QoS requirements. Furthermore, a novel emergency packet handling mechanism is proposedto ensure packet delivery with the least possible delay and the highest reliability. McMAC is also modeled analytically, and extensive simulations were performed to evaluate its performance. The results reveal that McMAC achieves the desired delay and reliability guarantee according to the requirements of a particular traffic class while achieving energy efficiency.
Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.
A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits
The K Basins Materials Accounting (MAC) and Materials Balance (MBA) programs had the Paradox Conversion to 4.0 ATP run to check out the systems. This report describes the results of the test and provides the signoff sheets associated with the testing. The test primarily concentrated on verifying that MAC and MBA software would run properly in the Paradox 4.0 environment. Changes in the MAC and MBA programs were basically limited to superficial items needed to accommodate the enhanced method of execution
AppleScript is an English-like, easy-to-understand scripting language built into every Mac. AppleScript can automate hundreds of AppleScriptable applications, performing tasks both large and small, complex and simple. Learn AppleScript: The Comprehensive Guide to Scripting and Automation on Mac OS X, Third Edition has been completely updated for Mac OS X Snow Leopard. It's all here, with an emphasis on practical information that will help you solve any automation problem-from the most mundane repetitive tasks to highly integrated workflows of complex systems. * Friendly enough for beginners, d
Soo, Kwok Tong
We make use of The Economist’s Big Mac Index (BMI) to investigate the Law of One Price (LOP) and whether the BMI can be used to predict future exchange rate and price changes. Deviations from Big Mac parity decay quickly, in approximately 1 year. The BMI is a better predictor of relative price changes than of exchange rate changes, and performs best when predicting a depreciation of a currency relative to the US dollar. Convergence to Big Mac parity occurs more rapidly for currencies with som...
Tongam Sihol Nababan
The aim of this study is to identify : (1) profile of exchange rate and purchasing power parity of IDR against US $ based on Big Mac Index compared to the exchange rate of other countries, and (2) the position of the Big Mac Affordability of Indonesia compared to other ASEAN countries. The results showed that based on Big Mac index during the period April 1998 up to January 2015, IDR exchange rate tends to be undervalued against the USA dollar. The cause of the currency tends to be in a posi...
Elizarraras, Omar; Panduro, Marco; Méndez, Aldo L.
The problem of obtaining the transmission rate in an ad hoc network consists in adjusting the power of each node to ensure the signal to interference ratio (SIR) and the energy required to transmit from one node to another is obtained at the same time. Therefore, an optimal transmission rate for each node in a medium access control (MAC) protocol based on CSMA-CDMA (carrier sense multiple access-code division multiple access) for ad hoc networks can be obtained using evolutionary optimization. This work proposes a genetic algorithm for the transmission rate election considering a perfect power control, and our proposition achieves improvement of 10% compared with the scheme that handles the handshaking phase to adjust the transmission rate. Furthermore, this paper proposes a genetic algorithm that solves the problem of power combining, interference, data rate, and energy ensuring the signal to interference ratio in an ad hoc network. The result of the proposed genetic algorithm has a better performance (15%) compared to the CSMA-CDMA protocol without optimizing. Therefore, we show by simulation the effectiveness of the proposed protocol in terms of the throughput. PMID:25140339
Full Text Available The problem of obtaining the transmission rate in an ad hoc network consists in adjusting the power of each node to ensure the signal to interference ratio (SIR and the energy required to transmit from one node to another is obtained at the same time. Therefore, an optimal transmission rate for each node in a medium access control (MAC protocol based on CSMA-CDMA (carrier sense multiple access-code division multiple access for ad hoc networks can be obtained using evolutionary optimization. This work proposes a genetic algorithm for the transmission rate election considering a perfect power control, and our proposition achieves improvement of 10% compared with the scheme that handles the handshaking phase to adjust the transmission rate. Furthermore, this paper proposes a genetic algorithm that solves the problem of power combining, interference, data rate, and energy ensuring the signal to interference ratio in an ad hoc network. The result of the proposed genetic algorithm has a better performance (15% compared to the CSMA-CDMA protocol without optimizing. Therefore, we show by simulation the effectiveness of the proposed protocol in terms of the throughput.
Full Text Available The human body communication (HBC is a technology that enables short range data communication using the human body as a medium, like an electrical wire. Thus it removes the need for a traditional antenna. HBC may be used as a type of data communication in body area network (BAN, while the devices are being in contact with body. One of important issues in BAN is an emergency alarm because it may be closely related to human life. For emergency data communication, the most critical factor is the time constraint. IEEE 802.15.6 specifies that the emergency alarm for the BAN must be notified in less than 1 sec and must provide prioritization mechanisms for emergency traffic and notification. As one type of BAN, the HBC must follow this recommendation, too. Existing emergency handling methods in BAN are based on the carrier sensing capability on radio frequencies to detect the status of channels. However, PHY protocol in HBC does not provide the carrier sensing. So the previous methods are not well suitable for HBC directly. Additionally, in the environment that the emergency rate is very low, the allocation of dedicated slot(s for emergency in each superframe is very wasteful. In this work, we proposed specific emergency handling operation for human body communication's medium access control (HBC-MAC protocol to meet the emergency requirements for BAN. We also showed the optimal number of emergency slots for the various combinations of beacon intervals and emergency rates.
Full Text Available The operation of multiple RFID readers in close proximity results in interference between the readers. This issue is termed the reader collision problem and cannot always be solved by assigning them to different frequency channels due to technical and regulatory limitations. The typical solution is to separate the operation of such readers across time. This sequential operation, however, results in a long delay to identify all tags. We present a bit level synchronized (BLSync MAC protocol for multi-reader RFID networks that allows multiple readers to operate simultaneously on the same frequency channel. The BLSync protocol solves the reader collision problem by allowing all readers to transmit the same query at the same time. We analyze the performance of using the BLSync protocol and demonstrate benefits of 40%–50% in terms of tag reading delay for most settings. The benefits of BLSync, first demonstrated through analysis, are then validated and quantified through simulations on realistic reader-tag layouts.
Full Text Available In mobile ad hoc radio networks, mechanisms on how to access the radio channel are extremely important in order to improve network efficiency. In this paper, the load adaptable medium access control for ad hoc networks (LAMAN protocol is described. LAMAN is a novel decentralized multipacket MAC protocol designed following a cross-layer approach. Basically, this protocol is a hybrid CDMA-TDMA-based protocol that aims at throughput maximization in multipacket communication environments by efficiently combining contention and conflict-free protocol components. Such combination of components is used to adapt the nodes' access priority to changes on the traffic load while, at the same time, accounting for the multipacket reception (MPR capability of the receivers. A theoretical analysis of the system is developed presenting closed expressions of network throughput and packet delay. By simulations the validity of our analysis is shown and the performances of a LAMAN-based system and an Aloha-CDMA-based one are compared.
Soucek, Jan; Rothkaehl, Hanna; Ahlen, Lennart; Balikhin, Michael; Carr, Christopher; Dekkali, Moustapha; Khotyaintsev, Yuri; Lan, Radek; Magnes, Werner; Morawski, Marek; Nakamura, Rumi; Uhlir, Ludek; Yearby, Keith; Winkler, Marek; Zaslavsky, Arnaud
If selected, Turbulence Heating ObserveR (THOR) will become the first spacecraft mission dedicated to the study of plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all THOR fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer, and search-coil magnetometer (SCM), and perform signal digitization and on-board data processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The scientific value of highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation will further improve on this heritage. Large dynamic range of the instruments will be complemented by a thorough electromagnetic cleanliness program, which will prevent perturbation of field measurements by interference from payload and platform subsystems. Taking advantage of the capabilities of modern electronics and the large telemetry bandwidth of THOR, FWP will provide multi-component electromagnetic field waveforms and spectral data products at a high time resolution. Fully synchronized sampling of many signals will allow to resolve wave phase information and estimate wavelength via interferometric correlations between EFI probes. FWP will also implement a plasma resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will rapidly transmit information about magnetic field vector and spacecraft potential to the
Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH
As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...
preliminary validity of the Walking and Remembering Test. Journal of geriatric physical therapy . 2009;32(1):2-9. 23. Mancini M, Salarian A, Carlson-Kuhta P...MacMillan), American Physical Therapy Association (APTA) 2014 Annual conference, Charlotte, NC 88 August 18-21, 2014 (paper) A novel dual...Multitasking Performance for Mild TBI. Federal Section, American Physical Therapy Association’s Combined Section Meeting, (Weightman, Scherer, McCulloch
The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)
Pawar, Pranav M.; Nielsen, Rasmus Hjorth; Prasad, Neeli R.
is the vulnerability to security attacks/threats. The performance and behavior of a WSN are vastly affected by such attacks. In order to be able to better address the vulnerabilities of WSNs in terms of security, it is important to understand the behavior of the attacks. This paper addresses the behavioral modeling...... of medium access control (MAC) security attacks in WSNs. The MAC layer is responsible for energy consumption, delay and channel utilization of the network and attacks on this layer can introduce significant degradation of the individual sensor nodes due to energy drain and in performance due to delays....... The behavioral modeling of attacks will be beneficial for designing efficient and secure MAC layer protocols. The security attacks are modeled using a sequential diagram approach of Unified Modeling Language (UML). Further, a new attack definition, specific to hybrid MAC mechanisms, is proposed....
G. P. Halkes
Full Text Available The evaluation of MAC protocols for Wireless Sensor Networks (WSNs is often performed through simulation. These simulations necessarily abstract away from reality in many ways. However, the impact of these abstractions on the results of the simulations has received only limited attention. Moreover, many studies on the accuracy of simulation have studied either the physical layer and per link effects or routing protocol effects. To the best of our knowledge, no other work has focused on the study of the simulation abstractions with respect to MAC protocol performance. In this paper, we present the results of an experimental study of two often used abstractions in the simulation of WSN MAC protocols. We show that a simple SNR-based reception model can provide quite accurate results for metrics commonly used to evaluate MAC protocols. Furthermore, we provide an analysis of what the main sources of deviation are and thereby how the simulations can be improved to provide even better results.
Das, G.; Lannoo, B.; Jung, H.D.; Koonen, A.M.J.; Colle, D.; Pickavet, M.; Demeester, P.
In this paper we propose a novel architecture and MAC protocol for a scalable, cost effective WDM / TDM PON providing fully flexible dynamic bandwidth allocation for upstream and downstream data transmission.
Maulidin, Mahmuddin, M.; Kamaruddin, L. M.; Elsaikh, Mohamed
Wireless Sensor Network (WSN) is a wireless network which consists of sensor nodes scattered in a particular area which are used to monitor physical or environment condition. Each node in WSN is also scattered in sensor field, so an appropriate scheme of MAC protocol should have to develop communication link for data transferring. Video transmission is one of the important applications for the future that can be transmitted with low aspect in side of cost and also power consumption. In this paper, comparison of five different MAC WSN protocol for video transmission namely IEEE 802.11 standard, IEEE 802.15.4 standard, CSMA/CA, Berkeley-MAC, and Lightweight-MAC protocol are studied. Simulation experiment has been conducted in OMNeT++ with INET network simulator software to evaluate the performance. Obtained results indicate that IEEE 802.11 works better than other protocol in term of packet delivery, throughput, and latency.
Full Text Available We have found the errors in the throughput formulae presented in our paper "Connectivity-based reliable multicast MAC protocol for IEEE 802.11 wireless LANs". We provide the corrected formulae and numerical results.
Yen, Chih-Ming; Chang, Chung-Ju; Chen, Yih-Shen; Huang, Ching Yao
The paper proposes and analyzes an adaptive p-persistent-based (APP) medium access control (MAC) scheme for IEEE 802.11 WLAN. The APP MAC scheme intends to support delay fairness for every station in each access, denoting small delay variance. It differentiates permission probabilities of transmission for stations which are incurred with various packet delays. This permission probability is designed as a function of the numbers of retransmissions and re-backoffs so that stations with larger packet delay are endowed with higher permission probability. Also, the scheme is analyzed by a Markov-chain analysis, where the collision probability, the system throughput, and the average delay are successfully obtained. Numerical results show that the proposed APP MAC scheme can attain lower mean delay and higher mean throughput. In the mean time, simulation results are given to justify the validity of the analysis, and also show that the APP MAC scheme can achieve more delay fairness than conventional algorithms.
... Funding and Fiscal Affairs; Farmer Mac Liquidity Management ACTION: Proposed rule; reopening of comment... proposed rule that would amend its liquidity management regulations for the Federal Agricultural Mortgage... comment on the proposed liquidity regulations. [[Page 26712
Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A
The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg
Krishna Mani Pathak
This article is a critical examination of MacIntyre’s notion of morality in reference to Kant’s deontological moral theory. The examination shows that MacIntyre (a) criticizes Kant’s moral theory to defend virtue ethics or neo-Aristotelian ethics with a weak notion of morality; (b) favors the idea of local morality, which does not leave any room for moral assessment and reciprocity in an intercultural domain; and (c) f...
Guinea Campaign.11 It studies the campaign exclusively from the February 1944 through October 1944. The choice in dates argues that the campaign...the Pacific. King continued to maintain that MacArthur’s line of operation in SWPA, toward the Philippines to the exclusion of the central Pacific...with Nimitz allowed MacArthur the rare luxury of aircraft carriers providing a protective bubble over both the Morotai and Palaus operations. Escort
Scott Loveridge; Dusan Paredes
Rural leaders can point to low housing costs as a reason that their area should be competitive for business attraction. To what extent do rural housing costs offset transportation and other locational disadvantages in costs structures? The US lacks information to systematically answer the question. We adapt a strategy employed by The Economist in exploring purchasing power parity: the Big Mac Index. We gather information on Big Mac prices with a random sample of restaurants across the contigu...
Gautreau, G; Winans, P
This paper profiles Alena Jean MacMaster, an extraordinary nurse leader, activist, visionary and humanitarian from New Brunswick. Her determination and drive were instrumental in fostering the development and progression of health care, nursing education and nursing services at the local, provincial, federal and international levels. "First, loyalty to the institution in which you serve. The patient is the most important person in the entire institution," was Miss MacMaster's guiding principle throughout her career.
The K Basins Materials Accounting (MAC) and Materials Balance (MBA) programs had the Paradox Code Cleanup ATP run to check out the systems. This report describes the results of the test and provides the signoff sheets associated with the testing. The Acceptance Test results indicate that the MAC and MBA systems are ready for operation using the cleaned up code. The final codes were removed to the production space on the customer server on April 15th
Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.
A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)
The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV
Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram
The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.
Lucas de Melo Guimarães
Full Text Available The increasing demands for high-data rate traffic stimulated the development of the fifth-generation (5G mobile networks. The envisioned 5G network is expected to meet its challenge by devising means to further improve spectrum usage. Many alternatives to enhance spectrum usage are being researched, such as massive MIMO, operation in mmWave frequency, cognitive radio, and the employment of full-duplex antennas. Efficient utilization of the potential of any of these technologies faces a set of challenges related to medium access control (MAC schemes. This work focuses on MAC schemes tailored for full-duplex antennas, since they are expected to play a major role in the foreseeable 5G networks. In this context, this paper presents a MAC layer technique to improve total transmission time when full-duplex antennas are employed. Several evaluations in different scenarios are conducted to assess the proposed MAC scheme. Numerical results show that the proposed scheme provides gains up to 156% when compared to a state-of-the-art full-duplex antenna MAC protocol. Compared to traditional half-duplex antenna MAC protocols, the proposed scheme yields gain up to 412%.
Xu, Yongbin; Song, Saemee; Moeller, Arne; Kim, Nahee; Piao, Shunfu; Sim, Se-Hoon; Kang, Mooseok; Yu, Wookyung; Cho, Hyun-Soo; Chang, Iksoo; Lee, Kangseok; Ha, Nam-Chul
Macrolide-specific efflux pump MacAB-TolC has been identified in diverse Gram-negative bacteria including Escherichia coli. The inner membrane transporter MacB requires the outer membrane factor TolC and the periplasmic adaptor protein MacA to form a functional tripartite complex. In this study, we used a chimeric protein containing the tip region of the TolC α-barrel to investigate the role of the TolC α-barrel tip region with regard to its interaction with MacA. The chimeric protein formed a stable complex with MacA, and the complex formation was abolished by substitution at the functionally essential residues located at the MacA α-helical tip region. Electron microscopic study delineated that this complex was made by tip-to-tip interaction between the tip regions of the α-barrels of TolC and MacA, which correlated well with the TolC and MacA complex calculated by molecular dynamics. Taken together, our results demonstrate that the MacA hexamer interacts with TolC in a tip-to-tip manner, and implies the manner by which MacA induces opening of the TolC channel. PMID:21325274
Xu, Yongbin; Song, Saemee; Moeller, Arne; Kim, Nahee; Piao, Shunfu; Sim, Se-Hoon; Kang, Mooseok; Yu, Wookyung; Cho, Hyun-Soo; Chang, Iksoo; Lee, Kangseok; Ha, Nam-Chul
Macrolide-specific efflux pump MacAB-TolC has been identified in diverse gram-negative bacteria including Escherichia coli. The inner membrane transporter MacB requires the outer membrane factor TolC and the periplasmic adaptor protein MacA to form a functional tripartite complex. In this study, we used a chimeric protein containing the tip region of the TolC α-barrel to investigate the role of the TolC α-barrel tip region with regard to its interaction with MacA. The chimeric protein formed a stable complex with MacA, and the complex formation was abolished by substitution at the functionally essential residues located at the MacA α-helical tip region. Electron microscopic study delineated that this complex was made by tip-to-tip interaction between the tip regions of the α-barrels of TolC and MacA, which correlated well with the TolC and MacA complex calculated by molecular dynamics. Taken together, our results demonstrate that the MacA hexamer interacts with TolC in a tip-to-tip manner, and implies the manner by which MacA induces opening of the TolC channel.
The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations
Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John
We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate
Kurt James Werner
Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.
Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang
For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....
Sudarshan K. Srinivasan
Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.
Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D
The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.
Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.
This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.
Hilsenrath, F.; Bakke, J.C.; Voss, H.D.
A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite
Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T
The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.
Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.
This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained
Narasimha Murthy Yayavaram
Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.
Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.
Szymanski, T. H.
A scheduling algorithm and MAC protocol which provides low-jitter guaranteed-rate (GR) communications between base-stations (BS) in a Wireless Mesh Network (WMN) is proposed. The protocol can provision long-term multimedia services such as VOIP, IPTV, or Video-on-Demand. The time-axis is partitioned into scheduling frames with F time-slots each. A directional antennae scheme is used to provide each directed link with a fixed transmission rate. A protocol such as IntServ is used to provision resources along an end-to-end path of BSs for GR sessions. The Guaranteed Rates between the BSs are then specified in a doubly stochastic traffic rate matrix, which is recursively decomposed to yield a low-jitter GR frame transmission schedule. In the resulting schedule, the end-to-end delay and jitter are small and bounded, and the cell loss rate due to primary scheduling conflicts is zero. For dual-channel WMNs, the MAC protocol can achieve 100% utilization, as well as near-minimal queueing delays and near minimal delay jitter. The scheduling time complexity is O(NFlogNF), where N is the number of BSs. Extensive simulation results are presented.
Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François
A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and
Michalakes, J.; Vachharajani, M.
Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.
Muhammad Mostafa Monowar
Full Text Available The emergence of heterogeneous applications with diverse requirements forresource-constrained Wireless Body Area Networks (WBANs poses significant challengesfor provisioning Quality of Service (QoS with multi-constraints (delay and reliability whilepreserving energy efficiency. To address such challenges, this paper proposes McMAC,a MAC protocol with multi-constrained QoS provisioning for diverse traffic classes inWBANs. McMAC classifies traffic based on their multi-constrained QoS demands andintroduces a novel superframe structure based on the "transmit-whenever-appropriate"principle, which allows diverse periods for diverse traffic classes according to their respectiveQoS requirements. Furthermore, a novel emergency packet handling mechanism is proposedto ensure packet delivery with the least possible delay and the highest reliability. McMACis also modeled analytically, and extensive simulations were performed to evaluate itsperformance. The results reveal that McMAC achieves the desired delay and reliabilityguarantee according to the requirements of a particular traffic class while achieving energyefficiency.
Niemann, Hans Henrik
A different aspect of using the parameterisation of all systems stabilised by a given controller, i.e. the dual Youla parameterisation, is considered. The relation between system change and the dual Youla parameter is derived in explicit form. A number of standard uncertain model descriptions...... are considered and the relation with the dual Youla parameter given. Some applications of the dual Youla parameterisation are considered in connection with the design of controllers and model/performance validation....
Hristov Ivan; Goranov Goran; Hristova Radoslava
We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP”) in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL). The results show 2 times better per...
Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders
A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...
Ghosh, A; Paparao, P
Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.
Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.
The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.
Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.
A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.
The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution
The main features of a VAX-FPS Loosely-Coupled Array of Processors (LCAP) set-up and the implementation of a High Energy Physics tracking program for off-line purposes will be described. This LCAP consists of a VAX 11/750 host and two FPS 64 bit attached processors. Before analyzing the performances of this LCAP, its characteristics will be outlined, especially from a user's point of vue, and will be briefly compared to those of the IBM-FPS LCAP
Jose Hugo Barron-Zambrano
Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.
Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III
In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network
Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M
In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.
Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.
Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions
Aljada, Muhsen; Alameh, Kamal
We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.
Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R
As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).
Raj Kumar Tiwari; Santosh Kumar Agrahari
The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...