WorldWideScience

Sample records for mac dual processor

  1. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  2. THE DESIGN AND IMPLEMENTATION OF THE IEEE 802.11 MAC BASED ON SOFT-CORE PROCESSOR AND RTOS

    Institute of Scientific and Technical Information of China (English)

    Xiao Wan'ang; Fang Zhi; Shi Yin

    2007-01-01

    The implementation method of the IEEE 802.11 Medium Access Control (MAC) protocol is mainly based on DSP (Digital Signal Processor)/ARM (Advanced Reduced instruction set computer Machine) processor or DSP/ARM IP (Intellectual Property) core. This paper presents a method based on Nios Ⅱ soft-core processor embedded in Altera's Cyclone FPGA (Field Programmable Gate Array)and MicroC/OS-Ⅱ RTOS (Real-Time Operation System). The benefits and drawbacks of above methods are compared, and then the method presented in this paper is described. The hardware and software partitioning are discussed; the hardware architecture is also illustrated and the MAC software programming is described in detail. The presented method has some advantages, such as low cost,easy-implementation and very suitable for the implementation of IEEE 802.11 MAC in research stage.

  3. Dual Description of Supergravity MacDowell-Mansouri Theory

    CERN Document Server

    García-Compéan, H; Obregón, O; Ramírez, C

    1999-01-01

    In the context of field theory two elements seem to be necessary to search for strong-weak coupling duality. First, one needs a gauge theory and second, it should be supersymmetric. For gravitation these two elements are present in MacDowell-Mansouri supergravity. The search for an "effective duality" in this theory presents technical and conceptual problems that we discuss. Nevertheless, by means of a field theoretical approach, which in the abelian case coincides with $S$-duality, we exhibit a dual theory for supergravity, with inverted couplings. This results in a supersymmetric non-linear sigma model of the Freedman-Townsend type.

  4. A DUAL RESERVATION CDMA-BASED MAC PROTOCOL WITH POWER CONTROL FOR AD HOC NETWORKS

    Institute of Scientific and Technical Information of China (English)

    Jia Min; Chen Huimin; Yuan Yuhua

    2007-01-01

    This paper proposes a new multi-channel Medium Access Control (MAC) protocol named as Dual Reservation Code Division Multiple Access (CDMA) based MAC protocol with Power Control (DRCPC). The code channel is divided into common channel, broadcast channel and several data channels. And dynamic power control mechanism is implemented to reduce near-far interference. Compared with IEEE 802.11 Distributed Coordination Function (DCF) protocol, the results show that the proposed mechanism improves the average throughput and limits the transmission delay efficiently.

  5. Dual shear plate power processor packaging design. [for Solar Electric Propulsion spacecraft

    Science.gov (United States)

    Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.

    1975-01-01

    The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.

  6. Tandem demodulation lock-in amplifier based on digital signal processor for dual-modulated spectroscopy.

    Science.gov (United States)

    Qin, Jianhuan; Huang, Zhiming; Ge, Yujian; Hou, Yun; Chu, Junhao

    2009-03-01

    Dual-modulated spectroscopy is one of the most powerful methods in the measurement of modulation spectroscopy. Here we develop a tandem lock-in amplifier (LIA) based on digital signal processor to implement a novel algorithm of tandem demodulation. The theoretical analysis of demodulation algorithm is presented, and the implementation of this tandem LIA is described in detail. Compared to the traditional demodulating way with two LIAs in cascade, this tandem LIA eliminates the extra quantization error of redundant analog-to-digital and digital-to-analog conversions and removes the limitation to the time constant in the commercial LIA, hence lowers the requirement of frequency ratio in dual-modulated spectroscopy. The applications are given as examples in the photoreflectance (PR) measurements of GaAs (100) thin film and GaSb bulk material, respectively, at the different optical energy regions. The experimental results indicate that this tandem is well capable of PR spectra measurement with good PR lineshapes and reasonable signal noise ratio. A brief comparison of GaAs PR results between tandem LIA and two LIAs is made to prove the efficiency and advantages of the tandem LIA.

  7. Evaluation of Dual-Launch Lunar Architectures Using the Mission Assessment Post Processor

    Science.gov (United States)

    Stewart, Shaun M.; Senent, Juan; Williams, Jacob; Condon, Gerald L.; Lee, David E.

    2010-01-01

    The National Aeronautics and Space Administrations (NASA) Constellation Program is currently designing a new transportation system to replace the Space Shuttle, support human missions to both the International Space Station (ISS) and the Moon, and enable the eventual establishment of an outpost on the lunar surface. The present Constellation architecture is designed to meet nominal capability requirements and provide flexibility sufficient for handling a host of contingency scenarios including (but not limited to) launch delays at the Earth. This report summarizes a body of work performed in support of the Review of U.S. Human Space Flight Committee. It analyzes three lunar orbit rendezvous dual-launch architecture options which incorporate differing methodologies for mitigating the effects of launch delays at the Earth. NASA employed the recently-developed Mission Assessment Post Processor (MAPP) tool to quickly evaluate vehicle performance requirements for several candidate approaches for conducting human missions to the Moon. The MAPP tool enabled analysis of Earth perturbation effects and Earth-Moon geometry effects on the integrated vehicle performance as it varies over the 18.6-year lunar nodal cycle. Results are provided summarizing best-case and worst-case vehicle propellant requirements for each architecture option. Additionally, the associated vehicle payload mass requirements at launch are compared between each architecture and against those of the Constellation Program. The current Constellation Program architecture assumes that the Altair lunar lander and Earth Departure Stage (EDS) vehicles are launched on a heavy lift launch vehicle. The Orion Crew Exploration Vehicle (CEV) is separately launched on a smaller man-rated vehicle. This strategy relaxes man-rating requirements for the heavy lift launch vehicle and has the potential to significantly reduce the cost of the overall architecture over the operational lifetime of the program. The crew launch

  8. Quicksilver Power Mac G4

    CERN Multimedia

    2001-01-01

    A new generation with a reworked motherboard is launched on 2001 with however the same Graphite box. It also included a processor speed-bump, and brought the DVD-R "SuperDrive" to the mid-level model. The Quicksilver PowerMac was available in three configurations: The 733 MHz model, with 128 MB of RAM, a 40 GB hard drive, and a CD-RW drive, was 1,699 dollars, the 867 MHz configuration, with 128 MB of RAM, a 60 GB hard drive and a DVD-R drive, was 2,499 dollars, and the high-end dual-800 MHz model, with 256 MB of RAM, an 80 GB hard drive and a DVD-R drive, was 3,499 dollars. The 733 MHz model is the first personal computer to have a DVD burner, named SuperDrive at Apple. The design was updated on 2002 with 800 MHz, 933 MHz and dual 1 GHz configurations, becoming the first Mac to reach 1 GHz.

  9. 基于硬件多线程网络处理器功耗可控无线局域网MAC协议实现%Power controllable WLAN MAC protocol implementation based on hardware multi-threaded network processor

    Institute of Scientific and Technical Information of China (English)

    王磊; 张晓彤; 张艳丽; 王沁

    2012-01-01

    针对在如何在提高网络吞吐率并满足实时性需求的同时消耗更少的功耗的问题,以硬件多线程网络处理为平台,以IEEE 802.11 MAC层协议为例,通过对MAC层数据流的模式、数据流上的操作行为以及时间约束进行建模并测试分析,提出一种多线程化网络协议的软件实现方法;配合动态功耗可控的多线程网络处理器能够根据流量和实时性自适应地调整系统的性能.实验结果证明,异构多线程结构程序在实时性任务时五个软件线程需四个硬件线程支持,而无实时性任务只需两个硬件线程支持.提出的多线程MAC层协议编程模型能够达到根据网络负载特征动态控制处理器性能的目的.%How to improve network throughput and meet the real-time while consuming less power process are key concerns during network processor designing. Hardware multi-threaded network processor as a platform, IEEE 802. 11MAC layer proto-col as an example, modeling based on MAC layer data stream model, data stream operation behavior and time constraints and test the model. This paper presented a multi-threaded network protocol software implementation method. This method could adjust system performance based on traffic and real-time with dynamic power controlled multi-threaded network processor, thereby reducing power consumption when the processor was running. The result shows that real-time tasks require 4 hard threads on multi-threaded processor while only 2 are required for non-realtime tasks. This programming model provided proces-sors the ability to dynamically adapt network workload characteristics.

  10. Parallel Performance of MPI Sorting Algorithms on Dual-Core Processor Windows-Based Systems

    CERN Document Server

    Elnashar, Alaa Ismail

    2011-01-01

    Message Passing Interface (MPI) is widely used to implement parallel programs. Although Windowsbased architectures provide the facilities of parallel execution and multi-threading, little attention has been focused on using MPI on these platforms. In this paper we use the dual core Window-based platform to study the effect of parallel processes number and also the number of cores on the performance of three MPI parallel implementations for some sorting algorithms.

  11. Mac Bible

    CERN Document Server

    Spivey, Dwight

    2009-01-01

    This essential guide answers all your questions on using a Macintosh computer, whether you?re unpacking your very first Mac after switching from a PC or upgrading from an older Mac. You?ll walk through all pre-installed Mac applications, including using Mac OS X, browsing the Web using Safari, downloading music from the iTunes store, troubleshooting Mac-specific problems, organizing photos in iPhoto, organizing calendars in iCal, editing digital video in iMovie, and more.

  12. 基于双DSP的信息处理机设计%Design of a signal processor based on dual DSP structure

    Institute of Scientific and Technical Information of China (English)

    王冬; 李登科

    2013-01-01

    介绍了一种基于双DSP的信息处理机设计,该信息处理机是某目标跟踪系统的重要组成部分,能够完成8路模拟信号的数模转换及预处理,并配合目标跟踪软件完成目标跟踪.处理机采用TMS320C6414作为主处理器,ADSP2187为预处理器.讲述了双DSP信息处理机的总体设计思路,预处理系统,主处理系统以及逻辑译码电路的开发设计.实验表明,该信息处理机完成了系统规定的功能,工作稳定可靠.%This paper introduces a design of signal processor based on dual DSP,the signal processor is a important part of the target tracking system,it can complete 8 analog signals digital-analog conversion and pretreatment,and with the target tracking software to complete target tracking.The processor uses TMS320C6414 as the main processor,ADSP2187 as a preprocessor.This paper describes the overall design ideas of dual DSP signal processor,pretreatment system,the main processing system as well as the design and development of a logic decoding circuit.Experiments show that,the signal processor can complete the function which required bt the system,it can stable and reliable work.

  13. Practical Dual WiFi NIC and Multi-channel MAC Protocol%双网卡多信道无线MAC协议

    Institute of Scientific and Technical Information of China (English)

    赵蕴龙; 康世龙; 高振国; 杨飞

    2012-01-01

    多收发器多信道技术能够有效提高无线多跳网络的带宽和吞吐量,成为学术界的研究热点.多收发器多信道MAC协议研究主要涉及信道资源的分配与管理问题.在现有多信道MAC协议的研究基础上,提出一种基于IEEE802.11标准WiFi网卡的双收发器多信道MAC协议-DIM( Dual-Interface Management).协议采用信道冲突模型来分配信道资源,以优化网络的信道分布;同时,DIM协议在较少的硬件配置下,充分利用IEEE802.11标准提供的信道资源,提高了信道利用率.仿真实验表明,DIM协议具有较大的网络吞吐量和较小的分组传输延迟.%Multi-radio multi-channel technology can efficiently improve the multi-hop wireless networks' bandwidth and throughput, so that it has been becoming the researching hot spot. Among the so many researching key issues about the multi-radio multi-channel technology, wireless channel assignment and management are more important and difficult. This paper proposed a new dual-radio multi-channel MAC protocol using the standard 802. 11 WiFi NIC, named as DIM (Dual-Interface Management MAC protocol). DIM can optimize the channel assignment by applying the channel conflict model,and take full use of the available IEEE802. 11 wireless channels with little command on hardwire configuration. The simulation rtsults show that DIM has more network throughput and less latency of packets delivery.

  14. A MacWilliams Relation of Linear Codes and Their Dual Codes over Zps%ZPs上的线性码及其对偶码的MacWilliams关系式

    Institute of Scientific and Technical Information of China (English)

    董学东; 董久祥; 张妍; 曹明

    2004-01-01

    Asch等人给出Zp2上的线性码及其对偶码的MacWilliams关系式,其中p为奇素数.进一步推广Asch等人的结果,得到了Zps上的线性码及其对偶码的MacWilliams关系式,其中s≥2并且P为奇素数.

  15. 认知无线电网络双天线多信道媒体接入控制协议%Dual-antenna multi-channel MAC protocol in cognitive radio networks

    Institute of Scientific and Technical Information of China (English)

    黄巍; 钱裕乐; 李云

    2011-01-01

    在认知无线电网络中,媒体接入控制(MAC)协议的主要功能包括信道感知、选择和接入控制,其中感知时间和传输时间的长度对网络的性能有着重要的影响.提出了一种双天线多信道分布式认知无线电MAC(TM-MAC)协议,不需要在传输之前对信道进行感知;节点可以在其他节点传输数据的同时对频谱资源进行检测,然后利用空闲的频谱资源通信;建立了数学模型分析在饱和网络状况下MAC协议的吞吐量.仿真分析表明TM-MAC协议能够有效提高网络的吞吐量.%In the cognitive radio networks, the main functions of MAC protocols include channel sensing, channel selection and access, and the detection time and transmission time have important influence on network performance. A dual- antenna multi-channel distributed MAC (TM-MAC) protocol was proposed, which was not necessary to detect channels before transmitting nodes data. The node could detect the spectrum resource while other nodes transmit data. Then, the node could transmit data by the idle spectrum resource. A model was built to analyze the throughput of TM-MAC under the saturation condition. The simulation results show that TM-MAC improves the throughput in cognitive ratio networks.

  16. Implementation of MAC by using Modified Vedic Multiplier

    OpenAIRE

    2013-01-01

    Multiplier Accumulator Unit (MAC) is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 32 X 32 bits....

  17. MacWilliams identity and self-dual codes of linear codes over Z2a +uZ2a%Z2a+uZ2a上线性码的MacWilliams恒等式及自对偶码

    Institute of Scientific and Technical Information of China (English)

    宋贤梅; 熊蕾

    2016-01-01

    考虑环 R =Z2a +uZ2a上的线性码,其中 u2=u。研究了环 R 上线性码的完全 Gray 权估计的 MacWilliams 恒等式。给出了环 R 上的自对偶码的生成矩阵及环 Z23+uZ23上长为偶数 n 的自对偶码的数量公式。讨论了环 R上的挠码,得到挠码的生成矩阵及挠码与剩余码的关系。%The linear codes over R =Z2a +uZ2a with u2 =u are discussed.MacWilliams identity for the complete Gray weight enumerator is investigated firstly.Then,the generator matrices of self-dual codes over R and the number of dis-tinct self-dual codes of even length n over Z23 +uZ23 are given.The torsion codes over R are discussed and the genera-tor matrices of torsion codes and the relationship between the torsion codes and the residue codes are also obtained.

  18. Frequency diversity wideband digital receiver and signal processor for solid-state dual-polarimetric weather radars

    Science.gov (United States)

    Mishra, Kumar Vijay

    -channel digital receiver has been successfully deployed as a key component in the recently developed National Aeronautical and Space Administration (NASA) Global Precipitation Measurement (GPM) Dual-Frequency Dual-Polarization Doppler Radar (D3R). The D3R is the principal ground validation instrument for the precipitation measurements of the Dual Precipitation Radar (DPR) onboard the GPM Core Observatory satellite scheduled for launch in 2014. The D3R system employs two broadly separated frequencies at Ku- and Ka-bands that together make measurements for precipitation types which need higher sensitivity such as light rain, drizzle and snow. This research describes unique design space to configure the digital receiver for D3R at several processing levels. At length, this research presents analysis and results obtained by employing the multi-carrier waveforms for D3R during the 2012 GPM Cold-Season Precipitation Experiment (GCPEx) campaign in Canada.

  19. Living in the Fragments of Dreams: Analysis of the Dual-Narrative Structure in Kenneth MacMillan's "Winter Dreams" from Narratological and Psychoanalytical Perspectives

    Science.gov (United States)

    Kodera, Ryota

    2012-01-01

    This essay investigates the ways dance narratives are constructed and aims to reconfirm the significance of dance narratives in the creation of meanings within dance practices. It draws on key concepts in narratology and psychoanalysis. These two critical perspectives are applied to the analysis of the narrative in Kenneth MacMillan's 1991 one-act…

  20. Macs for dummies

    CERN Document Server

    Baig, Edward C

    2014-01-01

    Get the most out of your Mac with this comprehensive guide Macs For Dummies, 13th Edition is the ultimate guide to your Mac, fully updated to include information about the latest updates. The book walks you through troubleshooting, syncing mobile devices, integrating Windows, and more, so you can take advantage of everything Macs have to offer. Whether you're a new user, a recent convert, or you just want to get the most out of your Mac, this book puts all the information you need in one place. Discover what makes Macs superior computing machines. Learn the basics, from mastering the Dock and

  1. Windows for Intel Macs

    CERN Document Server

    Ogasawara, Todd

    2008-01-01

    Even the most devoted Mac OS X user may need to use Windows XP, or may just be curious about XP and its applications. This Short Cut is a concise guide for OS X users who need to quickly get comfortable and become productive with Windows XP basics on their Macs. It covers: Security Networking ApplicationsMac users can easily install and use Windows thanks to Boot Camp and Parallels Desktop for Mac. Boot Camp lets an Intel-based Mac install and boot Windows XP on its own hard drive partition. Parallels Desktop for Mac uses virtualization technology to run Windows XP (or other operating systems

  2. Design and Implementation of an Efficient 64 bit MAC

    Directory of Open Access Journals (Sweden)

    Mohammad Shabber Hasan Khan

    2015-08-01

    Full Text Available The design of optimized 64 bit multiplier and accumulator (MAC unit is implemented in this paper. MAC unit plays major role in many of the digital signal processing (DSP applications. The MAC unit is designed with the combinations of multipliers and adders. In the proposed method MAC unit is implemented using Vedic multiplier and the adder is done with ripple carry adder .The components are reduced by implementing Vedic multiplier using the techniques of Vedic mathematics that have been modified to improve performance. a high speed processor depends significantly on the multiplier as it is one of the key hardware blocks in most digital signal processing systems as well as in general processors. The area is optimized effectively using Vedic multiplier .The total design implemented using Xilinx.

  3. Enterprise Mac administrators guide

    CERN Document Server

    Smith, William

    2015-01-01

    IT departments everywhere will be integrating Macs and Mac OS X into their IT infrastructure and this book will tell them how to do it. It will serve as an authoritative, useful and frequently referenced book on Mac OS X administration.

  4. MacBook Pro Portable Genius

    CERN Document Server

    Miser, Brad

    2011-01-01

    Tips and techniques for forward-thinking MacBook Pro users Now that you have a MacBook Pro, you need just one more accessory, your very own copy of MacBook Pro Portable Genius, Third Edition. This handy, compact book lets you in on a wealth of tips and tricks, so you get the very most out of Apple's very popular notebook. Discover the latest on the most recent release of iLife, get the skinny on the new Intel Core i7 and i5 processors in the Pro, see how to go wireless in a smart way, and much more. The book is easy to navigate, doesn't skimp on the essentials, and helps you save time and avoi

  5. Mac at Work

    CERN Document Server

    Sparks, David

    2011-01-01

    Bridge the gap between using a Mac at home and at the office. Now that you love your Mac at home, you want to use one at the office without missing a beat of productivity or professionalism. This unique guide shows you how.  You'll find best Mac business practices for handling word processing, spreadsheet and presentation creation, task and project management, and graphics. The book also explores topics such as hardware maintenance, how to synchronize with multiple computers, data backup, and communication with Windows networks.: Covers the nuts and bolts of using a Mac at work, including sync

  6. Enterprise Mac Security Mac OS X Snow Leopard Security

    CERN Document Server

    Edge, Stephen Charles; Hunter, Beau; Sullivan, Gene; LeBlanc, Dee-Ann

    2010-01-01

    A common misconception in the Mac community is that Mac's operating system is more secure than others. While this might be true in certain cases, security on the Mac is still a crucial issue. When sharing is enabled or remote control applications are installed, Mac OS X faces a variety of security threats. Enterprise Mac Security: Mac OS X Snow Leopard is a definitive, expert-driven update of the popular, slash-dotted first edition and was written in part as a companion to the SANS Institute course for Mac OS X. It contains detailed Mac OS X security information, and walkthroughs on securing s

  7. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  8. Design of High Speed Architecture of Parallel MAC Based On Radix-2 MBA

    Directory of Open Access Journals (Sweden)

    Syed Anwar Ahmed,

    2014-05-01

    Full Text Available The multiplier and multiplier-and-accumulator (MAC are the essential elements of the digital signal processing such as filtering, convolution, transformations and Inner products. Parallel MAC is frequently used in digital signal processing and video/graphics applications. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors today, especially since the media processing took off. The MAC provides high speed multiplication and multiplication with accumulative addition. This paper presents a combined process of multiplication and accumulation based on radix-4 & radix-8 booth encodings. In this Paper, we investigate the method of implementing the Parallel MAC with the smallest possible delay. Enhancing the speed of operation of the parallel MAC is a major design issue. This has been achieved by developing a CLA adder for parallel MAC.

  9. The MAC framework: redefining MAC protocols for wireless sensor networks

    NARCIS (Netherlands)

    Parker, T.; Halkes, G.; Bezemer, M.; Langendoen, K.

    2010-01-01

    Most current WSN MAC protocol implementations have multiple tasks to perform—deciding on correct timing, sending of packets, sending of acknowledgements, etc. However, as much of this is common to all MAC protocols, there is duplication of functionality, which leads to larger MAC protocol code size

  10. The MAC framework: redefining MAC protocols for wireless sensor networks

    NARCIS (Netherlands)

    Parker, T.; Halkes, G.; Bezemer, M.; Langendoen, K.

    2010-01-01

    Most current WSN MAC protocol implementations have multiple tasks to perform—deciding on correct timing, sending of packets, sending of acknowledgements, etc. However, as much of this is common to all MAC protocols, there is duplication of functionality, which leads to larger MAC protocol code size

  11. Recent results from MAC

    Energy Technology Data Exchange (ETDEWEB)

    MAC Collaboration

    1982-05-01

    Some preliminary results from the MAC detector at PEP are presented. These include measurements of the angular distribution of ..gamma gamma.., ..mu mu.. and tau tau final states, a determination of the tau lifetime, a measurement of R, and a presentation of the inclusive muon p/sub perpendicular/ distribution for hadronic events.

  12. Macs For Seniors For Dummies

    CERN Document Server

    Chambers, Mark L

    2012-01-01

    You're never too old to fall in love—with your Mac! You took a while, but you are now the proud owner of your first Mac computer. Macs For Seniors For Dummies is just for you. This friendly, accessible guide walks you through choosing a Mac and learning how to use it. You'll find yourself falling head over heels for your Mac in no time. Macs For Seniors For Dummies introduces you to all the basics that you need to know: turning the Mac on and getting connected; using the keyboard and mouse; working with files and folders; navigate around the Mac desktop and OS X Lion; setting up an Inter

  13. Processor-Dependent Malware... and codes

    CERN Document Server

    Desnos, Anthony; Filiol, Eric

    2010-01-01

    Malware usually target computers according to their operating system. Thus we have Windows malwares, Linux malwares and so on ... In this paper, we consider a different approach and show on a technical basis how easily malware can recognize and target systems selectively, according to the onboard processor chip. This technology is very easy to build since it does not rely on deep analysis of chip logical gates architecture. Floating Point Arithmetic (FPA) looks promising to define a set of tests to identify the processor or, more precisely, a subset of possible processors. We give results for different families of processors: AMD, Intel (Dual Core, Atom), Sparc, Digital Alpha, Cell, Atom ... As a conclusion, we propose two {\\it open problems} that are new, to the authors' knowledge.

  14. Implementation of MAC by using Modified Vedic Multiplier

    Directory of Open Access Journals (Sweden)

    Sreelekshmi M. S.

    2013-09-01

    Full Text Available Multiplier Accumulator Unit (MAC is a part of Digital Signal Processors. The speed of MAC depends on the speed of multiplier. So by using an efficient Vedic multiplier which excels in terms of speed, power and area, the performance of MAC can be increased. For this fast method of multiplication based on ancient Indian Vedic mathematics is proposed in this paper. Among various method of multiplication in Vedic mathematics, Urdhva Tiryagbhyam is used and the multiplication is for 32 X 32 bits. Urdhva Tiryagbhyam is a general multiplication formula applicable to all cases of multiplication. Adder used is Carry Look Ahead adder. The proposed design shows improvement over carry save adder.

  15. iMac pocket genius

    CERN Document Server

    Hart-Davis, Guy

    2010-01-01

    If you want to get the very most out of your iMac, put this savvy Portable Genius guide to work. Want to make the most of the new Magic Mouse and the latest iLife apps? Set up a wireless network using your iMac's AirPort card? Watch television on your iMac, or show iMac videos and movies on your television? You'll find cool and useful Genius tips, full-color screenshots, and pages of easy-to-access shortcuts and tools that will save you time and let you enjoy your iMac to the max.

  16. Monolithic MACS micro resonators

    Science.gov (United States)

    Lehmann-Horn, J. A.; Jacquinot, J.-F.; Ginefri, J. C.; Bonhomme, C.; Sakellariou, D.

    2016-10-01

    Magic Angle Coil Spinning (MACS) aids improving the intrinsically low NMR sensitivity of heterogeneous microscopic samples. We report on the design and testing of a new type of monolithic 2D MACS resonators to overcome known limitations of conventional micro coils. The resonators' conductors were printed on dielectric substrate and tuned without utilizing lumped element capacitors. Self-resonance conditions have been computed by a hybrid FEM-MoM technique. Preliminary results reported here indicate robust mechanical stability, reduced eddy currents heating and negligible susceptibility effects. The gain in B1 /√{ P } is in agreement with the NMR sensitivity enhancement according to the principle of reciprocity. A sensitivity enhancement larger than 3 has been achieved in a monolithic micro resonator inside a standard 4 mm rotor at 500 MHz. These 2D resonators could offer higher performance micro-detection and ease of use of heterogeneous microscopic substances such as biomedical samples, microscopic specimens and thin film materials.

  17. Blind Cognitive MAC Protocols

    CERN Document Server

    Mehanna, Omar; Gamal, Hesham El

    2008-01-01

    We consider the design of cognitive Medium Access Control (MAC) protocols enabling an unlicensed (secondary) transmitter-receiver pair to communicate over the idle periods of a set of licensed channels, i.e., the primary network. The objective is to maximize data throughput while maintaining the synchronization between secondary users and avoiding interference with licensed (primary) users. No statistical information about the primary traffic is assumed to be available a-priori to the secondary user. We investigate two distinct sensing scenarios. In the first, the secondary transmitter is capable of sensing all the primary channels, whereas it senses one channel only in the second scenario. In both cases, we propose MAC protocols that efficiently learn the statistics of the primary traffic online. Our simulation results demonstrate that the proposed blind protocols asymptotically achieve the throughput obtained when prior knowledge of primary traffic statistics is available.

  18. Gravitational Duality in MacDowell-Mansouri Gauge Theory

    CERN Document Server

    García-Compéan, H; Ramírez, C

    1998-01-01

    Strong-weak duality invariance can only be defined for particular sectors of supersymmetric Yang-Mills theories. Nevertheless, for full non-Abelian non-supersymmetric theories, dual theories with inverted couplings, have been found. We show that an analogous procedure allows to find the dual action to the gauge theory of gravity constructed by the MacDowell-Mansouri model plus the superposition of a $\\Theta$ term.

  19. MacBook for dummies

    CERN Document Server

    Chambers , Mark L

    2014-01-01

    Make friends with your MacBook the fun and easy way! Ultra-light, ultra-fast, and ultra-powerful, the MacBook is the coolest laptop in town, and longtime Mac guru Mark L. Chambers is just the guy to help you get to know your MacBook in no time. Take a closer look at the latest features, get the lowdown on OS X, unleash your creative forces with iLife, take care of business with the iWork applications, and sync it all with iCloud with the expert advice in this bestselling MacBook guide. Whether this is your first MacBook or your first laptop, period, you''ll learn to navigate the Mac desktop, c

  20. Macs For Dummies, Pocket Edition

    CERN Document Server

    Baig, Edward C

    2011-01-01

    The fun and easy way to make the most of your wonderful Mac. Simply Mac-nificent — all the cool things your Mac can do! This handy guide helps you figure out the nuts and bolts of your Mac. Navigate the Mac desktop, use the Safari Web browser to surf the Internet, e-mail photos to friends and family, create and print documents, rip audio CDs, and more. The fun begins right here!. Open the book and find: How to set up and configure your Mac; Tips for getting around on the Mac desktop; Steps for setting up an e-mail account and browsing the Internet; Details about the free programs that come wit

  1. iMac portable genius

    CERN Document Server

    Hart-Davis, Guy

    2010-01-01

    The most up-to-date coverage on the latest iMac advice, tools, and shortcuts Cool and useful tips, full-color screenshots, and savvy advice show you how to get the most out of your iMac. Fully updated to cover the iMac's latest features and capabilities, this guide is packed with indispensible information on iLife '09 and Mac OS X Snow Leopard, and shows you how to customize your iMac in a way that it will work best for you.Explores all the bells and whistles of the iMac, including the new Magic Mouse, iLife apps such as iPhoto and iMovie, and Mac OS X Snow LeopardShows yo

  2. iMac for dummies

    CERN Document Server

    Chambers, Mark L

    2014-01-01

    Do it all with your iMac and this bestselling For Dummies guide! You're still a little giddy from finally scoring your new iMac, and you can't wait to get started. Even if you're already in love with your iMac, it helps to have a little guidance to really get the most out of this ultimate all-in-one computer. This updated edition of iMac For Dummies is the ideal way to learn the iMac fundamentals from setting up and personalizing your machine to importing files, making FaceTime video calls, surfing the web, using your favorite programs and apps, and everything in between. Trusted Mac guru Mark

  3. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  4. Learn Excel 2011 for Mac

    CERN Document Server

    Hart-Davis, Guy

    2011-01-01

    Microsoft Excel 2011 for Mac OS X is a powerful application, but many of its most impressive features can be difficult to find. Learn Excel 2011 for Mac by Guy Hart-Davis is a practical, hands-on approach to learning all of the details of Excel 2011 in order to get work done efficiently on Mac OS X. From using formulas and functions to creating databases, from analyzing data to automating tasks, you'll learn everything you need to know to put this powerful application to use for a variety of tasks. What you'll learn * The secrets of the Excel for Mac interface! * How to create effective workbo

  5. Array processors in chemistry

    Energy Technology Data Exchange (ETDEWEB)

    Ostlund, N.S.

    1980-01-01

    The field of attached scientific processors (''array processors'') is surveyed, and an attempt is made to indicate their present and possible future use in computational chemistry. The current commercial products from Floating Point Systems, Inc., Datawest Corporation, and CSP, Inc. are discussed.

  6. Ellen MacArthur

    Institute of Scientific and Technical Information of China (English)

    Teodora; Lazarova

    2006-01-01

    Just over a year since breaking the round theworld solo record on board her 75 foot trimaranB&O,Ellen MacArthur embarked on a newventure:the Asian Record Circuit 2006,incorpo-rating the ‘Tour Of China’,and bringing a differ-ent set of challenges into new territories.Wespoke to Ellen and her team during their recent(April)stopover in Oingdao.When did you start sailing and what inspiredyou(you grew up in Derbyshire,in the UK,quite far away from the water)?I was introduced to sailing by my Aunt Thea ona small sailing boat called Cabaret.We wentsailing along the east coast of EngLand andbefore I knew it,I was hooked on sailing.I wasso inspired that when I was at school,I saved

  7. Macs for seniors for dummies

    CERN Document Server

    Chambers, Mark L

    2009-01-01

    Over 50 and thinking about getting your first computer? A user-friendly Mac is a great choice, and Macs For Seniors For Dummies walks you through choosing one and learning to use it. You won't even need your grandchildren to help! Macs For Seniors For Dummies introduces you to all the basic things you may not have encountered before-how to use the keyboard and mouse, work with files and folders, navigate around the Mac OS X desktop, set up an Internet connection, and much more. You'll learn to:Choose the Mac that's right for you, set it up, run programs and manage files, and hook up a printerU

  8. iMac for dummies

    CERN Document Server

    Chambers, Mark L

    2012-01-01

    The bestselling guide to the ultimate all-in-one computer—now updated and revised throughout! If you're looking for speed, performance, and power, the iMac is the ultimate all-in-one computer. From its superior performance, powerful operating system, and amazing applications, the iMac is one awesome machine, and the fun, friendly, and approachable style of iMac For Dummies is an ideal way to get started with the basics. You'll learn the fundamentals of the iMac including setting up and customizing your iMac and the software that comes with it, importing files from your old computer, send

  9. Gotcha! Macs lose their innocence

    CERN Multimedia

    Computer Security Team

    2012-01-01

    Still believe your Mac is secure because Microsoft PCs fall prey to viruses and worms but Macs don’t? Time to wake up! This year has seen the first major compromise of Macs worldwide*. How is yours doing?   The “Flashback” Trojan is affecting Apple’s own variant of Java and compromises Macs via so-called drive-by infections, i.e. when you visit an appropriately prepared (infected!) website - and this might not necessarily be a site with questionable contents, but could well be a popular, reputable one. Security Companies worldwide have been monitoring this particular Trojan for a while and have estimated that more than half a million Macs were compromised. Connected to a few central command and control servers, the compromised Macs were then supporting the malicious activity of the bad guys! Fortunately, the security companies have now been able to take over those command and control servers and stop their destructive drive. So, Mac users, face the f...

  10. Java and Mac OS X

    CERN Document Server

    Davis, T Gene

    2010-01-01

    Learn the guidelines of integrating Java with native Mac OS X applications with this Devloper Reference book. Java is used to create nearly every type of application that exists and is one of the most required skills of employers seeking computer programmers. Java code and its libraries can be integrated with Mac OS X features, and this book shows you how to do just that. You'll learn to write Java programs on OS X and you'll even discover how to integrate them with the Cocoa APIs.: Shows how Java programs can be integrated with any Mac OS X feature, such as NSView widgets or screen savers; Re

  11. Benchmarking a DSP processor

    OpenAIRE

    Lennartsson, Per; Nordlander, Lars

    2002-01-01

    This Master thesis describes the benchmarking of a DSP processor. Benchmarking means measuring the performance in some way. In this report, we have focused on the number of instruction cycles needed to execute certain algorithms. The algorithms we have used in the benchmark are all very common in signal processing today. The results we have reached in this thesis have been compared to benchmarks for other processors, performed by Berkeley Design Technology, Inc. The algorithms were programm...

  12. Mac Programming for Absolute Beginners

    CERN Document Server

    Wang, Wallace

    2011-01-01

    Want to learn how to program on your Mac? Not sure where to begin? Best-selling author Wallace Wang will explain how to get started with Cocoa, Objective-C, and Xcode. Whether you are an experienced Windows coder moving to the Mac, or you are completely new to programming, you'll see how the basic design of a Mac OS X program works, how Objective-C differs from other languages you may have used, and how to use the Xcode development environment. Most importantly, you'll learn how to use elements of the Cocoa framework to create windows, store data, and respond to users in your own Mac programs.

  13. MacBook portable genius

    CERN Document Server

    Miser, Brad

    2008-01-01

    The Genius is in. You don't have to be a genius to use a MacBook. But if you want to get the very most out of yours, put this savvy Portable Genius guide to work. Want to connect your MacBook to other Macs? Use Expose to its fullest potential? Troubleshoot? You'll find cool and useful Genius tips, insider secrets, full-color screenshots, and pages of easy-to-access shortcuts and tools that will save you loads of time and make your MacBook IQ soar. Portable GENIUS Fun, hip, and straightforward, the new Portable Genius series gives forward-thinking Apple users useful informat

  14. Mac mini真体验

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    2005年,Mac mini首次登场,众所周知,苹果的模具更换的并不频繁,在外貌没有大幅改变的情况下,迄今为止,Mac mini实际上已经更新了7代。最新的Mac mini的工业设计实际上延续了2008年开始的Unibody一体成型铝合金机身设计与其他Mac在外观上保持了一致的元素。更小的Mac mini看起来更加性感诱人,那么,你需要它么?

  15. Fiverr MacGyver

    Science.gov (United States)

    Hut, Rolf; van de Giesen, Nick; Larson, Martha

    2014-05-01

    Crowdsourcing has become popular over the past years, also for scientific endeavors. There are many Citizen Science projects and crowdfunding platforms, such as Kickstarter, that are make helpful contributions to moving environmental science forward. An interesting underused source of useful crowd-derived contributions to research is the website Fiverr.com. On this platform, thousands of people, acting as small-scale freelance contractors, offer their skills in the form of services. The platform offers a chance for people to take a hobby, skill, or pastime and make it something more by reaching out to a wider audience and by receiving a payment in return for services. As is typical of other crowdsourcing platforms, the tasks are small and usually self contained. As the name Fiverr suggests, offers start at US5 to provide a particular service. Services offered range from graphic design, to messages sung or spoken with various styles or accents, to complete apps for Android or iPhone. Skill providers on the platform can accept a range of variation of definition in the tasks, some can be described in general terms, for others it is more appropriate to provide examples. Fiverr provides a central location for those offering skills and those needing services to find each other, it makes it possible to communicate and exchange files, to make payments, and it provides support for resolving disputes. In all cases, it is important to keep expectations aligned with the nature of the platform: quality can and will vary. Ultimately, the critical contribution of Fiverr is not to replace professional services or otherwise save money, but rather to provide access to a large group of people with specialized skills who are able to make a contribution on short notice. In the context of this session, it can be considered a pool of people with MacGyver skills lying in wait of a MacGyyer task to attack. There are many ways in which Fiverr tasks, which are called 'gigs', can be useful in

  16. MacBook Teach Yourself VISUALLY

    CERN Document Server

    Miser, Brad

    2010-01-01

    Like the MacBook itself, Teach Yourself VISUALLY MacBook, Second Edition is designed to be visually appealing, while providing excellent functionality at the same time. By using this book, MacBook users will be empowered to do everyday tasks quickly and easily. From such basic steps as powering on or shutting down the MacBook, working on the Mac desktop with the Dashboard and its widgets to running Windows applications, Teach Yourself VISUALLY MacBook, Second Edition covers all the vital information and provides the help and support a reader needs—in many ways it's like having a Mac Genius at

  17. Switching to a Mac portable genius

    CERN Document Server

    McFedries, Paul

    2011-01-01

    Switching from a PC to a Mac is a breeze with this book Anyone considering making the move to Mac from the Windows world will find this book smoothes the way. While Macs are famous for ease of use, there are fundamental differences in Mac and PC ways of thinking, plus there?s the hassle of moving files, calendars, and other essential data from one platform to another. This guide lays out all the information, explains basic Mac procedures for the newcomer, offers great tips on data-sharing (including running Windows applications on a Mac), and provides everything the new Mac user needs to move

  18. Switching to a Mac For Dummies

    CERN Document Server

    Reinhold, Arnold

    2011-01-01

    Learn how to make the switch from PC to Mac a completely smooth transition The number of Mac users continues to increase significantly each year. If you are one of those people and are eager but also anxious about making the switch, then fear not! This friendly guide skips the jargon to deliver you an easy-to-read, understandable introduction to the Macintosh computer. Computer guru Arnold Reinhold walks you through the Mac OS, user interface, and icons. You'll learn how to set up your Mac, move your files from your PC to your Mac, switch applications, get your Mac online, network your Mac, se

  19. EARLY EXPERIENCE WITH A HYBRID PROCESSOR: K-MEANS CLUSTERING

    Energy Technology Data Exchange (ETDEWEB)

    M. GOKHALE; ET AL

    2001-02-01

    We discuss hardware/software coprocessing on a hybrid processor for a compute- and data-intensive hyper-spectral imaging algorithm, K-Means Clustering. The experiments are performed on the Altera Excalibur board using the soft IP core 32-bit NIOS RISC processor. In our experiments, we compare performance of the sequential algorithm with two different accelerated versions. We consider granularity and synchronization issues when mapping an algorithm to a hybrid processor. Our results show that on the Excalibur NIOS, a 15% speedup can be achieved over the sequential algorithm on images with 8 spectral bands where the pixels are divided into 8 categories. Speedup is limited by the communication cost of transferring data from external memory through the NIOS processor to the customized circuits. Our results indicate that future hybrid processors must either (1) have a clock rate 10X the speed of the configurable logic circuits or (2) include dual port memories that both the processor and configurable logic can access. If either of these conditions is met, the hybrid processor will show a factor of 10 speedup over the sequential algorithm. Such systems will combine the convenience of conventional processors with the speed of configurable logic.

  20. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  1. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  2. Signal processor packaging design

    Science.gov (United States)

    McCarley, Paul L.; Phipps, Mickie A.

    1993-10-01

    The Signal Processor Packaging Design (SPPD) program was a technology development effort to demonstrate that a miniaturized, high throughput programmable processor could be fabricated to meet the stringent environment imposed by high speed kinetic energy guided interceptor and missile applications. This successful program culminated with the delivery of two very small processors, each about the size of a large pin grid array package. Rockwell International's Tactical Systems Division in Anaheim, California developed one of the processors, and the other was developed by Texas Instruments' (TI) Defense Systems and Electronics Group (DSEG) of Dallas, Texas. The SPPD program was sponsored by the Guided Interceptor Technology Branch of the Air Force Wright Laboratory's Armament Directorate (WL/MNSI) at Eglin AFB, Florida and funded by SDIO's Interceptor Technology Directorate (SDIO/TNC). These prototype processors were subjected to rigorous tests of their image processing capabilities, and both successfully demonstrated the ability to process 128 X 128 infrared images at a frame rate of over 100 Hz.

  3. The Milstar Advanced Processor

    Science.gov (United States)

    Tjia, Khiem-Hian; Heely, Stephen D.; Morphet, John P.; Wirick, Kevin S.

    The Milstar Advanced Processor (MAP) is a 'drop-in' replacement for its predecessor which preserves existing interfaces with other Milstar satellite processors and minimizes the impact of such upgrading to already-developed application software. In addition to flight software development, and hardware development that involves the application of VHSIC technology to the electrical design, the MAP project is developing two sophisticated and similar test environments. High density RAM and ROM are employed by the MAP memory array. Attention is given to the fine-pitch VHSIC design techniques and lead designs used, as well as the tole of TQM and concurrent engineering in the development of the MAP manufacturing process.

  4. Mac OS X Lion在Mac App Store上线

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    2011年7月20日,Apple宣布具有超过250种新功能的世界最先进操作系统的第八个重要版本Mac OS X Lion今天在Mac App StoreTM推出并可进行下载,价格为29.99美元。Lion的诸多超强功能包括:全新Multi-Touch手势;全系统支持全屏应用程序;

  5. Interactive Digital Signal Processor

    Science.gov (United States)

    Mish, W. H.

    1985-01-01

    Interactive Digital Signal Processor, IDSP, consists of set of time series analysis "operators" based on various algorithms commonly used for digital signal analysis. Processing of digital signal time series to extract information usually achieved by applications of number of fairly standard operations. IDSP excellent teaching tool for demonstrating application for time series operators to artificially generated signals.

  6. Beyond processor sharing

    NARCIS (Netherlands)

    Aalto, S.; Ayesta, U.; Borst, S.C.; Misra, V.; Núñez Queija, R.

    2007-01-01

    While the (Egalitarian) Processor-Sharing (PS) discipline offers crucial insights in the performance of fair resource allocation mechanisms, it is inherently limited in analyzing and designing differentiated scheduling algorithms such as Weighted Fair Queueing and Weighted Round-Robin. The Discrimin

  7. Properties of dual codes defined by nondegenerate forms

    Directory of Open Access Journals (Sweden)

    Steve Szabo

    2017-01-01

    Full Text Available Dual codes are defined with respect to non-degenerate sesquilinear or bilinear forms over a finite Frobenius ring. These dual codes have the properties one expects from a dual code: they satisfy a double-dual property, they have cardinality complementary to that of the primal code, and they satisfy the MacWilliams identities for the Hamming weight.

  8. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  9. Office 2011 for Mac For Dummies

    CERN Document Server

    LeVitus, Bob

    2011-01-01

    Get started with Office 2011 for Mac and discover the creative possibilitiesThe leading suite of productivity software for the Mac, Microsoft Office helps users complete common business tasks, including word processing, e-mail, presentations, financial analysis, and much more. Office 2011 for Mac For Dummies is the perfect companion for Microsoft Office for Mac users upgrading to the newest version, new computer users, and those who may have switched from the Windows version of Office. Written by one of the most popular gurus in the Mac community, Bob "Dr. Mac" LeVitus, the book explains every

  10. A Domain Specific DSP Processor

    OpenAIRE

    Tell, Eric

    2001-01-01

    This thesis describes the design of a domain specific DSP processor. The thesis is divided into two parts. The first part gives some theoretical background, describes the different steps of the design process (both for DSP processors in general and for this project) and motivates the design decisions made for this processor. The second part is a nearly complete design specification. The intended use of the processor is as a platform for hardware acceleration units. Support for this has howe...

  11. Processor register error correction management

    Science.gov (United States)

    Bose, Pradip; Cher, Chen-Yong; Gupta, Meeta S.

    2016-12-27

    Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.

  12. CoR-MAC: Contention over Reservation MAC Protocol for Time-Critical Services in Wireless Body Area Sensor Networks.

    Science.gov (United States)

    Yu, Jeongseok; Park, Laihyuk; Park, Junho; Cho, Sungrae; Keum, Changsup

    2016-05-09

    Reserving time slots for urgent data, such as life-critical information, seems to be very attractive to guarantee their deadline requirements in wireless body area sensor networks (WBASNs). On the other hand, this reservation imposes a negative impact on performance for the utilization of a channel. This paper proposes a new channel access scheme referred to as the contention over reservation MAC (CoR-MAC) protocol for time-critical services in wireless body area sensor networks. CoR-MAC uses the dual reservation; if the reserved time slots are known to be vacant, other nodes can access the time slots by contention-based reservation to maximize the utilization of a channel and decrease the delay of the data. To measure the effectiveness of the proposed scheme against IEEE 802.15.4 and IEEE 802.15.6, we evaluated their performances with various performance indexes. The CoR-MAC showed 50% to 850% performance improvement in terms of the delay of urgent and time-critical data according to the number of nodes.

  13. New Generation Processor Architecture Research

    Institute of Scientific and Technical Information of China (English)

    Chen Hongsong(陈红松); Hu Mingzeng; Ji Zhenzhou

    2003-01-01

    With the rapid development of microelectronics and hardware,the use of ever faster micro-processors and new architecture must be continued to meet tomorrow′s computing needs. New processor microarchitectures are needed to push performance further and to use higher transistor counts effectively.At the same time,aiming at different usages,the processor has been optimized in different aspects,such as high performace,low power consumption,small chip area and high security. SOC (System on chip)and SCMP (Single Chip Multi Processor) constitute the main processor system architecture.

  14. Stereoscopic Optical Signal Processor

    Science.gov (United States)

    Graig, Glenn D.

    1988-01-01

    Optical signal processor produces two-dimensional cross correlation of images from steroscopic video camera in real time. Cross correlation used to identify object, determines distance, or measures movement. Left and right cameras modulate beams from light source for correlation in video detector. Switch in position 1 produces information about range of object viewed by cameras. Position 2 gives information about movement. Position 3 helps to identify object.

  15. Tiled Multicore Processors

    Science.gov (United States)

    Taylor, Michael B.; Lee, Walter; Miller, Jason E.; Wentzlaff, David; Bratt, Ian; Greenwald, Ben; Hoffmann, Henry; Johnson, Paul R.; Kim, Jason S.; Psota, James; Saraf, Arvind; Shnidman, Nathan; Strumpen, Volker; Frank, Matthew I.; Amarasinghe, Saman; Agarwal, Anant

    For the last few decades Moore’s Law has continually provided exponential growth in the number of transistors on a single chip. This chapter describes a class of architectures, called tiled multicore architectures, that are designed to exploit massive quantities of on-chip resources in an efficient, scalable manner. Tiled multicore architectures combine each processor core with a switch to create a modular element called a tile. Tiles are replicated on a chip as needed to create multicores with any number of tiles. The Raw processor, a pioneering example of a tiled multicore processor, is examined in detail to explain the philosophy, design, and strengths of such architectures. Raw addresses the challenge of building a general-purpose architecture that performs well on a larger class of stream and embedded computing applications than existing microprocessors, while still running existing ILP-based sequential programs with reasonable performance. Central to achieving this goal is Raw’s ability to exploit all forms of parallelism, including ILP, DLP, TLP, and Stream parallelism. Raw approaches this challenge by implementing plenty of on-chip resources - including logic, wires, and pins - in a tiled arrangement, and exposing them through a new ISA, so that the software can take advantage of these resources for parallel applications. Compared to a traditional superscalar processor, Raw performs within a factor of 2x for sequential applications with a very low degree of ILP, about 2x-9x better for higher levels of ILP, and 10x-100x better when highly parallel applications are coded in a stream language or optimized by hand.

  16. NMRFx Processor: a cross-platform NMR data processing program.

    Science.gov (United States)

    Norris, Michael; Fetler, Bayard; Marchant, Jan; Johnson, Bruce A

    2016-08-01

    NMRFx Processor is a new program for the processing of NMR data. Written in the Java programming language, NMRFx Processor is a cross-platform application and runs on Linux, Mac OS X and Windows operating systems. The application can be run in both a graphical user interface (GUI) mode and from the command line. Processing scripts are written in the Python programming language and executed so that the low-level Java commands are automatically run in parallel on computers with multiple cores or CPUs. Processing scripts can be generated automatically from the parameters of NMR experiments or interactively constructed in the GUI. A wide variety of processing operations are provided, including methods for processing of non-uniformly sampled datasets using iterative soft thresholding. The interactive GUI also enables the use of the program as an educational tool for teaching basic and advanced techniques in NMR data analysis.

  17. Mac OS X Lion Server For Dummies

    CERN Document Server

    Rizzo, John

    2011-01-01

    The perfect guide to help administrators set up Apple's Mac OS X Lion Server With the overwhelming popularity of the iPhone and iPad, more Macs are appearing in corporate settings. The newest version of Mac Server is the ideal way to administer a Mac network. This friendly guide explains to both Windows and Mac administrators how to set up and configure the server, including services such as iCal Server, Podcast Producer, Wiki Server, Spotlight Server, iChat Server, File Sharing, Mail Services, and support for iPhone and iPad. It explains how to secure, administer, and troubleshoot the networ

  18. Take Control of Maintaining Your Mac

    CERN Document Server

    Kissell, Joe

    2009-01-01

    Keep your Mac running smoothly with our easy maintenance program! Regular maintenance is necessary to avoid problems and to ensure your Mac runs at peak performance, but it's hard to know what to do and when to do it. Best-selling author Joe Kissell has now applied his commonsense approach to the task of maintaining your Mac, whether you use Tiger or Leopard! Learn how to start on the right foot; what you should do daily, weekly, monthly, and yearly; and how to prepare for Mac OS X updates. Joe even explains how to monitor your Mac's health and debunks common panaceas. Read this book to lea

  19. Switching to a Mac For Dummies

    CERN Document Server

    Reinhold, Arnold

    2007-01-01

    Thinking of making the switch from your PC to a Mac? Congratulations! You're in for a great, virus-free ride. And Switching to Mac For Dummies makes it smoother than you ever imagined. From buying the Mac that's right for you to transferring your files to breaking your old Windows habits and learning to do things the (much easier) Mac way, it makes the whole process practically effortless. Whether you've been using Windows XP, Vista, or even Linux, you'll find simple, straightforward ways to make your transition go smoothly. That will leave you plenty of time to get familiar with Mac'

  20. Switching to the Mac The Missing Manual

    CERN Document Server

    Pogue, David

    2010-01-01

    Is Windows giving you pause? Ready to make the leap to the Mac instead? There has never been a better time to switch from Windows to Mac, and this incomparable guide will help you make a smooth transition. New York Times columnist and Missing Manuals creator David Pogue gets you past three challenges: transferring your stuff, assembling Mac programs so you can do what you did with Windows, and learning your way around Mac OS X. Learning to use a Mac is not a piece of cake, but once you do, the rewards are oh-so-much better. No viruses, worms, or spyware. No questionable firewalls, inefficien

  1. Cognitive MAC designs for OSA networks

    CERN Document Server

    Derakhshani, Mahsa

    2014-01-01

    This SpringerBrief presents recent advances in the cognitive MAC designs for opportunistic spectrum access (OSA) networks. It covers the basic MAC functionalities and MAC enhancements of IEEE 802.11. Later chapters discuss the existing MAC protocols for OSA and classify them based on characteristic features. The authors provide new research in adaptive carrier sensing-based MAC designs tailored for OSA, which optimize spectrum utilization and ensure a peaceful coexistence of licensed and unlicensed systems. Analytically devised via optimization and game-theoretic approaches, these adaptive M

  2. Distributed processor allocation for launching applications in a massively connected processors complex

    Science.gov (United States)

    Pedretti, Kevin

    2008-11-18

    A compute processor allocator architecture for allocating compute processors to run applications in a multiple processor computing apparatus is distributed among a subset of processors within the computing apparatus. Each processor of the subset includes a compute processor allocator. The compute processor allocators can share a common database of information pertinent to compute processor allocation. A communication path permits retrieval of information from the database independently of the compute processor allocators.

  3. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  4. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  5. A Systolic Array RLS Processor

    OpenAIRE

    Asai, T.; Matsumoto, T.

    2000-01-01

    This paper presents the outline of the systolic array recursive least-squares (RLS) processor prototyped primarily with the aim of broadband mobile communication applications. To execute the RLS algorithm effectively, this processor uses an orthogonal triangularization technique known in matrix algebra as QR decomposition for parallel pipelined processing. The processor board comprises 19 application-specific integrated circuit chips, each with approximately one million gates. Thirty-two bit ...

  6. AMD's 64-bit Opteron processor

    CERN Document Server

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  7. Emerging Trends in Embedded Processors

    Directory of Open Access Journals (Sweden)

    Gurvinder Singh

    2014-05-01

    Full Text Available An Embedded Processors is simply a µProcessors that has been “Embedded” into a device. Embedded systems are important part of human life. For illustration, one cannot visualize life without mobile phones for personal communication. Embedded systems are used in many places like healthcare, automotive, daily life, and in different offices and industries.Embedded Processors develop new research area in the field of hardware designing.

  8. Spaceborne Processor Array

    Science.gov (United States)

    Chow, Edward T.; Schatzel, Donald V.; Whitaker, William D.; Sterling, Thomas

    2008-01-01

    A Spaceborne Processor Array in Multifunctional Structure (SPAMS) can lower the total mass of the electronic and structural overhead of spacecraft, resulting in reduced launch costs, while increasing the science return through dynamic onboard computing. SPAMS integrates the multifunctional structure (MFS) and the Gilgamesh Memory, Intelligence, and Network Device (MIND) multi-core in-memory computer architecture into a single-system super-architecture. This transforms every inch of a spacecraft into a sharable, interconnected, smart computing element to increase computing performance while simultaneously reducing mass. The MIND in-memory architecture provides a foundation for high-performance, low-power, and fault-tolerant computing. The MIND chip has an internal structure that includes memory, processing, and communication functionality. The Gilgamesh is a scalable system comprising multiple MIND chips interconnected to operate as a single, tightly coupled, parallel computer. The array of MIND components shares a global, virtual name space for program variables and tasks that are allocated at run time to the distributed physical memory and processing resources. Individual processor- memory nodes can be activated or powered down at run time to provide active power management and to configure around faults. A SPAMS system is comprised of a distributed Gilgamesh array built into MFS, interfaces into instrument and communication subsystems, a mass storage interface, and a radiation-hardened flight computer.

  9. Mac OS X Tiger for Unix Geeks

    CERN Document Server

    Jepson, Brian

    2005-01-01

    If you're one of the many Unix developers drawn to Mac OS X for its Unix core, you'll find yourself in surprisingly unfamiliar territory. Unix and Mac OS X are kissing cousins, but there are enough pitfalls and minefields in going from one to another that even a Unix guru can stumble, and most guides to Mac OS X are written for Mac aficionados. For a Unix developer, approaching Tiger from the Mac side is a bit like learning Russian by reading the Russian side of a Russian-English dictionary. Fortunately, O'Reilly has been the Unix authority for over 25 years, and in Mac OS X Tiger for Unix Gee

  10. Teach yourself visually Mac Mini

    CERN Document Server

    Hart-Davis, Guy

    2012-01-01

    The perfect how-to guide for visual learners Apple?s Mac Mini packs a powerful punch is in a small package, including both HDMI and Thunderbolt ports plus the acclaimed OS X. But if you want to get the very most from all this power and versatility, be sure to get this practical visual guide. With full-color, step-by-step instructions as well as screenshots and illustrations on every page, it clearly shows you how to accomplish tasks rather than burying you in pages of text. Discover helpful visuals and how-tos on the OS, hardware specs, Launchpad, the App Store, multimedia capabilities (such

  11. Web Development with the Mac

    CERN Document Server

    Vegh, Aaron

    2010-01-01

    Learn Web development the Apple way and build a business. With a focus on both coding and creative development, this in-depth guide thoroughly covers what you need to know to build winning websites for clients — from what it takes to bring a business online to how to make your site interactive to how to run a freelance web business. In between, you'll master the technical tools of the trade — such as HTML, CSS, JavaScript, PHP, and Ruby on Rails — and learn how to create beautiful interfaces using Photoshop . This book covers everything a fledgling web developer working on a Mac needs to launc

  12. Embedded Processor Oriented Compiler Infrastructure

    Directory of Open Access Journals (Sweden)

    DJUKIC, M.

    2014-08-01

    Full Text Available In the recent years, research of special compiler techniques and algorithms for embedded processors broaden the knowledge of how to achieve better compiler performance in irregular processor architectures. However, industrial strength compilers, besides ability to generate efficient code, must also be robust, understandable, maintainable, and extensible. This raises the need for compiler infrastructure that provides means for convenient implementation of embedded processor oriented compiler techniques. Cirrus Logic Coyote 32 DSP is an example that shows how traditional compiler infrastructure is not able to cope with the problem. That is why the new compiler infrastructure was developed for this processor, based on research. in the field of embedded system software tools and experience in development of industrial strength compilers. The new infrastructure is described in this paper. Compiler generated code quality is compared with code generated by the previous compiler for the same processor architecture.

  13. Analysis of 3gpp-MAC and two-key 3gpp-MAC

    DEFF Research Database (Denmark)

    Knudsen, Lars Ramkilde; Mitchell, C.J.

    2003-01-01

    Forgery and key-recovery attacks are described on the 3gpp-MAC scheme, proposed for inclusion in the 3gpp specification. Three main classes of attack are given, all of which operate whether or not truncation is applied to the MAC value. Attacks in the first class use a large number of 'chosen MACs......', those in the second class use a large number of 'known MACs', and those in the third class require a large number of MAC verifications, but very few known MACS and no chosen MACS. The first class yields both forgery and key-recovery attacks, whereas the second and third classes are key-recovery attacks...... only. Both single-key and two-key variants of 3gpp-MAC are considered; the forgery attacks are relevant to both variants, whereas the key-recovery attacks are only relevant to the two-key variant....

  14. Analysis of 3gpp-MAC and two-key 3gpp-MAC

    DEFF Research Database (Denmark)

    Knudsen, Lars Ramkilde; Mitchell, C.J.

    2003-01-01

    Forgery and key-recovery attacks are described on the 3gpp-MAC scheme, proposed for inclusion in the 3gpp specification. Three main classes of attack are given, all of which operate whether or not truncation is applied to the MAC value. Attacks in the first class use a large number of 'chosen MACs......', those in the second class use a large number of 'known MACs', and those in the third class require a large number of MAC verifications, but very few known MACS and no chosen MACS. The first class yields both forgery and key-recovery attacks, whereas the second and third classes are key-recovery attacks...... only. Both single-key and two-key variants of 3gpp-MAC are considered; the forgery attacks are relevant to both variants, whereas the key-recovery attacks are only relevant to the two-key variant....

  15. Mac protocols for cyber-physical systems

    CERN Document Server

    Xia, Feng

    2015-01-01

    This book provides a literature review of various wireless MAC protocols and techniques for achieving real-time and reliable communications in the context of cyber-physical systems (CPS). The evaluation analysis of IEEE 802.15.4 for CPS therein will give insights into configuration and optimization of critical design parameters of MAC protocols. In addition, this book also presents the design and evaluation of an adaptive MAC protocol for medical CPS, which exemplifies how to facilitate real-time and reliable communications in CPS by exploiting IEEE 802.15.4 based MAC protocols. This book wil

  16. Take control of troubleshooting your Mac

    CERN Document Server

    Kissell, Joe

    2009-01-01

    Learn how to solve any Mac problem with Joe Kissell's expert advice! We may love our Macs, but they can still suffer significant problems. In this essential guide from best-selling author Joe Kissell, you'll learn 17 basic troubleshooting procedures and how to solve 9 common problems, along with an easy-to-follow way to troubleshoot novel problems. Whether your Mac won't turn on, experiences kernel panics repeatedly, or is glacially slow, this book has the calm, friendly advice you need to find a solution. Following in the footsteps of his critically acclaimed books Take Control of Mac OS X

  17. Teach yourself visually MacBook Pro

    CERN Document Server

    Hart-Davis, Guy

    2014-01-01

    Clear instructions to help visual learners get started with their MacBook Pro Covering all the essential information you need to get up to speed with your MacBook Pro, this new edition provides you with the most up-to-date information on performing everyday tasks quickly and easily. From basics such as powering on or shutting down the MacBook Pro to more advanced tasks such as running Windows applications, this visual guide provides the help and support you need to confidently use your MacBook Pro to its full potential.Empowers you to perform everyday tasks quickly and easilyCovers new hardwa

  18. Take control the Mac OS X lexicon

    CERN Document Server

    Zardetto, Sharon

    2009-01-01

    This ebook explains a little bit of everything; in fact, it's The Mac OS X (and then some) Lexicon because it's never just you and your Mac. It's you and your Mac and the Web, and your email, and that article you just read that threw 17 new acronyms at you or assumed that you knew all sorts of networking terms. Or it's you and your Mac and Finder features you've never touched, such as burn folders, smart folders, or proxy icons, and that mysterious Services submenu. This book is a great guide for Macintosh users everywhere who have trouble keeping up with the latest jargon, fo

  19. Macs all-in-one for dummies

    CERN Document Server

    Hutsko, Joe

    2014-01-01

    Your all-in-one guide to unleashing your Mac's full potential It's a Mac world out there. But if you haven't read the instruction manual, you may be neglecting some of your computer's coolest features. Turn to Macs All-in-One For Dummies' jam-packed guide to access the incredible tools within your computer. With this fully updated reference, you will learn how to use Launchpad and Mission Control; protect your Mac; back up and restore data with Time Machine; sync across devices in iCloud; import, organize, and share photos; direct in iMovie; compose in GarageBand; and so much more. The possi

  20. Wound healing in Mac-1 deficient mice.

    Science.gov (United States)

    Chen, Lin; Nagaraja, Sridevi; Zhou, Jian; Zhao, Yan; Fine, David; Mitrophanov, Alexander Y; Reifman, Jaques; DiPietro, Luisa A

    2017-05-01

    Mac-1 (CD11b/CD18) is a macrophage receptor that plays several critical roles in macrophage recruitment and activation. Because macrophages are essential for proper wound healing, the impact of Mac-1 deficiency on wound healing is of significant interest. Prior studies have shown that Mac-1(-/-) mice exhibit deficits in healing, including delayed wound closure in scalp and ear wounds. This study examined whether Mac-1 deficiency influences wound healing in small excisional and incisional skin wounds. Three millimeter diameter full thickness excisional wounds and incisional wounds were prepared on the dorsal skin of Mac-1 deficient (Mac-1(-/-) ) and wild type (WT) mice, and wound healing outcomes were examined. Mac-1 deficient mice exhibited a normal rate of wound closure, generally normal levels of total collagen, and nearly normal synthesis and distribution of collagens I and III. In incisional wounds, wound breaking strength was similar for Mac-1(-/-) and WT mice. Wounds of Mac-1 deficient mice displayed normal total macrophage content, although macrophage phenotype markers were skewed as compared to WT. Interestingly, amounts of TGF-β1 and its downstream signaling molecules, SMAD2 and SMAD3, were significantly decreased in the wounds of Mac-1 deficient mice compared to WT. The results suggest that Mac-1 deficiency has little impact on the healing of small excisional and incisional wounds. Moreover, the findings demonstrate that the effect of single genetic deficiencies on wound healing may markedly differ among wound models. These conclusions have implications for the interpretation of the many prior studies that utilize a single model system to examine wound healing outcomes in genetically deficient mice. © 2017 by the Wound Healing Society.

  1. A MAC Mode for Lightweight Block Ciphers

    DEFF Research Database (Denmark)

    Luykx, Atul; Preneel, Bart; Tischhauser, Elmar Wolfgang;

    2016-01-01

    , but also allows high-performance parallel implementations. We highlight this in a comprehensive implementation study, instantiating LightMAC with PRESENT and the AES. Moreover, LightMAC allows flexible trade-offs between rate and maximum message length. Unlike PMAC and its many derivatives, Light...

  2. MAC-awake of sevoflurane in children.

    Science.gov (United States)

    Davidson, Andrew J; Wong, Aaron; Knottenbelt, Graham; Sheppard, Suzette; Donath, Susan; Frawley, Geoff

    2008-08-01

    Age influences the potency of anesthetic agents, but there is little information on how age influences MAC-awake. MAC-awake may be an important aspect of anesthesia potency for the prevention of awareness during anesthesia. The aim of this study was to measure MAC-awake in a range of ages in children. After institutional ethics approval and informed parental consent 60 children were enrolled; 20 in each of three age groups (2 to awake. The Dixon up-down method was used to determine progression of subsequent concentrations and MAC-awake (ED50) for the three age groups were obtained using the probit model. This study found evidence for a difference in ED50 between age groups (P = 0.008). The MAC-awake was highest in the youngest group (0.66%) and similar in the older groups (0.45% and 0.43%). Although MAC-awake changes with age, in the ages where awareness has been reported, MAC-awake was found to be relatively low, and therefore it seems unlikely that age-specific changes to MAC-awake are a cause for awareness in children aged 5-12 years.

  3. Nomogram to estimate age-related MAC.

    NARCIS (Netherlands)

    Lerou, J.G.C.

    2004-01-01

    BACKGROUND: In clinical practice it is difficult to estimate rapidly two important values: (i) the total age-corrected MAC multiple from measured end-expired concentrations of volatile agent and nitrous oxide; (ii) the end-expired concentration of volatile agent needed to obtain a given total MAC

  4. VLA-MAC: A Variable Load Adaptive MAC Protocol for Wireless Sensor Networks

    Science.gov (United States)

    Yao, Guoliang; Liu, Hao; Chen, Hao; Shi, Longxin

    This letter presents VLA-MAC, a novel adaptive MAC protocol for wireless sensor networks that can achieve high energy efficiency and low latency in variable load conditions. In VLA-MAC, traffic load is measured online and utilized for adaptive adjustment. VLA-MAC transmits packets via a burst style to alleviate packets accumulation problem and achieve low latency in high load condition. Furthermore, it also saves obvious energy by removing unnecessary listen period in low load condition. Unlike current approach, VLA-MAC does not need to adjust duty-cycle according to load online. Simulation results based on ns-2 show the performance improvements of our protocol.

  5. Efficiency of Cache Mechanism for Network Processors

    Institute of Scientific and Technical Information of China (English)

    XU Bo; CHANG Jian; HUANG Shimeng; XUE Yibo; LI Jun

    2009-01-01

    With the explosion of network bandwidth and the ever-changing requirements for diverse net-work-based applications, the traditional processing architectures, i.e., general purpose processor (GPP) and application specific integrated circuits (ASIC) cannot provide sufficient flexibility and high performance at the same time. Thus, the network processor (NP) has emerged as an altemative to meet these dual demands for today's network processing. The NP combines embedded multi-threaded cores with a dch memory hierarchy that can adapt to different networking circumstances when customized by the application developers. In to-day's NP architectures, muitithreading prevails over cache mechanism, which has achieved great success in GPP to hide memory access latencies. This paper focuses on the efficiency of the cache mechanism in an NP. Theoretical timing models of packet processing are established for evaluating cache efficiency and experi-ments are performed based on real-life network backbone traces. Testing results show that an improvement of neady 70% can be gained in throughput with assistance from the cache mechanism. Accordingly, the cache mechanism is still efficient and irreplaceable in network processing, despite the existing of multithreading.

  6. Pipelining and bypassing in a RISC/DSP processor

    Science.gov (United States)

    Yu, Guojun; Yao, Qingdong; Liu, Peng; Jiang, Zhidi; Li, Fuping

    2005-03-01

    This paper proposes pipelining and bypassing unit (BPU) design method in our 32-bit RISC/DSP processor: MediaDsp3201 (briefly, MD32). MD32 is realized in 0.18μm technology, 1.8v, 200MHz working clock and can achieve 200 million/s Multiply-Accumulate (MAC) operations. It merges RISC architecture and DSP computation capability thoroughly, achieves fundamental RISC, extended DSP and single instruction multiple data (SIMD) instruction set with various addressing modes in a unified and customized DSP pipeline stage architecture. We will first describe the pipeline structure of MD32, comparing it to typical RISC-style pipeline structure. And then we will study the validity of two bypassing schemes in terms of their effectiveness in resolving pipeline data hazards: Centralized and Distributed BPU design strategy (CBPU and DBPU). A bypassing circuit chain model is given for DBPU, which register read is only placed at ID pipe stage. Considering the processor"s working clock which is decided by the pipeline time delay, the optimization of circuit that serial select with priority is also analyzed in detail since the BPU consists of a long serial path for combination logic. Finally, the performance improvement is analyzed.

  7. Mac OS X Snow Leopard for dummies

    CERN Document Server

    LeVitus, Bob

    2010-01-01

    Get to know Snow Leopard and make the most of your Mac Snow Leopard has a few new tricks up its sleeve, so whether you're new to Mac or a longtime Mac-thusiast, Mac expert Bob LeVitus has tips you'll appreciate. Learn how to start up your Mac, get to know the Dock and Finder, work your way through windows and dialogs, and organize and manage files and folders. Open the book and find: How to navigate around the Finder, Dock, and desktop Tips for opening, closing, resizing, and moving windows Steps for keeping Snow Leopard organized How to back up your system with Time Machine® Troubleshooting a

  8. Parallel optimization of multi-view deblurring algorithm in dual-core digital signal processor%多视点去模糊算法在双核DSP上的并行优化

    Institute of Scientific and Technical Information of China (English)

    付航; 章秀华; 贺武

    2015-01-01

    To rea1ize fast running of the mu1ti-view deb1urring a1gorithm in sma11 devices, apara11e1 optimiza-tion a1gorithm was proposed.TMS320C6657 dua1-core digita1 signa1 processor (DSP) was used as the primary computing chip, and the CCSv5.2 was used as the software deve1opment environment. To so1ve the prob1em of time consume of the sing1e core, the time of each sub-function in the a1gorithm was ana1yzed by using the time stamp counter. Then the a1gorithm of matrix mu1tip1ication that consumes the 1ongest time in the sub-function was optimized by dividing into two parts using a dividing point, and the amount of ca1cu1ation was assigned to the two cores of DSP equa11y to ensure the a1gorithm run in para11e1. The resu1ts show that the so1ving method of the dividing point is correct and effective; the running time of the DSP is reduced signifi-cantly by the optimized a1gorithm of mu1ti-view deb1urring and the operation efficiency is improved.%为了实现多视点去模糊算法在小型设备上快速运行,提出了一种并行优化的方法.采用TMS320C6657双核数字信号处理器(DSP,Digita1 signa1 processor)作为主要运算芯片,使用CCSv5.2作为软件开发环境.为了解决算法在单核上运行时间长的问题,首先使用时间戳计数器对算法中各部分功能函数的运行时间进行了详细的统计和分析;然后将运行时间最长的子函数中矩阵相乘部分的算法进行了优化,采用一个分界点将矩阵相乘部分算法划分为两块,将计算量均等的分配到DSP的两个核心上,使这部分算法能够同时在两个核心上并行运算.结果表明对分界点的求解是正确有效的;优化后的图像去模糊算法极大的缩短了DSP上的运算时间,提高了运算效率.

  9. High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

    Science.gov (United States)

    Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

    2016-04-01

    In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

  10. Fast Forwarding with Network Processors

    OpenAIRE

    Lefèvre, Laurent; Lemoine, E.; Pham, C; Tourancheau, B.

    2003-01-01

    Forwarding is a mechanism found in many network operations. Although a regular workstation is able to perform forwarding operations it still suffers from poor performances when compared to dedicated hardware machines. In this paper we study the possibility of using Network Processors (NPs) to improve the capability of regular workstations to forward data. We present a simple model and an experimental study demonstrating that even though NPs are less powerful than Host Processors (HPs) they ca...

  11. Comparison of CSMA based MAC protocols of wireless sensor networks

    CERN Document Server

    singh, Himanshu

    2012-01-01

    Energy conservation has been an important area of interest in Wireless Sensor networks (WSNs). Medium Access Control (MAC) protocols play an important role in energy conservation. In this paper, we describe CSMA based MAC protocols for WSN and analyze the simulation results of these protocols. We implemented S-MAC, T-MAC, B-MAC, B-MAC+, X-MAC, DMAC and Wise-MAC in TOSSIM, a simulator which unlike other simulators simulates the same code running on real hardware. Previous surveys mainly focused on the classification of MAC protocols according to the techniques being used or problem dealt with and presented a theoretical evaluation of protocols. This paper presents the comparative study of CSMA based protocols for WSNs, showing which MAC protocol is suitable in a particular environment and supports the arguments with the simulation results. The comparative study can be used to find the best suited MAC protocol for wireless sensor networks in different environments.

  12. Mac OS X for Unix Geeks (Leopard)

    CERN Document Server

    Rothman, Ernest E; Rosen, Rich

    2009-01-01

    If you've been lured to Mac OS X because of its Unix roots, this invaluable book serves as a bridge between Apple's Darwin OS and the more traditional Unix systems. The new edition offers a complete tour of Mac OS X's Unix shell for Leopard and Tiger, and helps you find the facilities that replace or correspond to standard Unix utilities. Learn how to compile code, link to libraries, and port Unix software to Mac OS X and much more with this concise guide.

  13. Mac OS X Lion portable genius

    CERN Document Server

    Spivey, Dwight

    2012-01-01

    Two e-books, Mac OS X Lion Portable Genius and MacBook Pro Portable Genius, Third Edition, bundled in one package Books in the Portable Genius series provide readers with the most accessible, useful information possible, including plenty of tips and techniques for the most-used features in a product or software. These e-books will show you what you may not find out by just working with your MacBook Pro and OS X Lion. Genius icons present smart or innovative ways to do something, saving time and hassle. Easy-to-find information gives you the essentials plus insightful tips on how to navigate

  14. Office 2008 for Mac for dummies

    CERN Document Server

    LeVitus, Bob

    2013-01-01

    Office 2008 for Mac is here, with great new enhancements to all your favorite office productivity tools. Who better than "Dr. Mac, "Bob LeVitus, to show you how to load and use them all? From choosing the best version for your needs to managing your life with your online calendar, Office 2008 For Mac For Dummies covers what you need to know. It compares the Student/Teacher Edition, Standard Edition, and Professional Edition, then walks you through installing your preferred version and keeping it up to date. You'll find out all the things you can do with Word, Excel, PowerPoint, and Entourage,

  15. Wireless sensors networks MAC protocols analysis

    CERN Document Server

    Chaari, Lamia

    2010-01-01

    Wireless sensors networks performance are strictly related to the medium access mechanism. An effective one, require non-conventional paradigms for protocol design due to several constraints. An adequate equilibrium between communication improvement and data processing capabilities must be accomplished. To achieve low power operation, several MAC protocols already proposed for WSN. The aim of this paper is to survey and to analyze the most energy efficient MAC protocol in order to categorize them and to compare their performances. Furthermore we have implemented some of WSN MAC protocol under OMNET++ with the purpose to evaluate their performances.

  16. Beginning Mac OS X Snow Leopard programming

    CERN Document Server

    Trent, Michael

    2010-01-01

    Michael Trent is a technical reviewer for numerous books and magazine articles and the coauthor of Beginning Mac OS X Programming with Drew McCormack. Drew McCormack is an experienced computational scientist, founder of the ""The Mental Faculty""-an independent company developing software for the Mac and iPhone-and the coauthor of Beginning Mac OS X Programming with Michael Trent. Wrox Beginning guides are crafted to make learning programming languages and technologies easier than you think, providing a structured, tutorial format that will guide you through all the techniques involved.

  17. Learn Office 2011 for Mac OS X

    CERN Document Server

    Hart-Davis, Guy

    2011-01-01

    Office for Mac remains the leading productivity suite for Mac, with Apple's iWork and the free OpenOffice.org trailing far behind. And now it's being updated with a cleaner interface and more compatibility with Exchange and SharePoint. Learn Office 2011 for Mac OS X offers a practical, hands-on approach to using Office 2011 applications to create and edit documents and get work done efficiently. You'll learn how to customize Office, design, create, and share documents, manipulate data in a spreadsheet, and create lively presentations. You'll also discover how to organize your email, contacts,

  18. MAC Layer Hurdles in BSNs

    CERN Document Server

    Ullah, Sana; Choi, Young-Woo; Lee, Hyung-Soo; Kwak, Kyung Sup

    2009-01-01

    The last few decades have seen considerable research progress in microelectronics and integrated circuits, system-on-chip design, wireless communication, and sensor technology. This progress has enabled the seamless integration of autonomous wireless sensor nodes around a human body to create a Body Sensor Network (BSN). The development of a proactive and ambulatory BSN induces a number of enormous issues and challenges. This paper presents the technical hurdles during the design and implementation of a low-power Medium Access Control (MAC) protocol for in-body and on-body sensor networks. We analyze the performance of IEEE 802.15.4 protocol for the on-body sensor network. We also provide a comprehensive insight into the heterogeneous characteristics of the in-body sensor network. A low-power technique called Pattern-Based Wake-up Table is proposed to handle the normal traffic in a BSN. The proposed technique provides a reliable solution towards low-power communication in the in-body sensor network.

  19. CR-MAC: A multichannel MAC protocol for cognitive radio ad hoc networks

    CERN Document Server

    Kamruzzaman, S M

    2010-01-01

    This paper proposes a cross-layer based cognitive radio multichannel medium access control (MAC) protocol with TDMA, which integrate the spectrum sensing at physical (PHY) layer and the packet scheduling at MAC layer, for the ad hoc wireless networks. The IEEE 802.11 standard allows for the use of multiple channels available at the PHY layer, but its MAC protocol is designed only for a single channel. A single channel MAC protocol does not work well in a multichannel environment, because of the multichannel hidden terminal problem. Our proposed protocol enables secondary users (SUs) to utilize multiple channels by switching channels dynamically, thus increasing network throughput. In our proposed protocol, each SU is equipped with only one spectrum agile transceiver, but solves the multichannel hidden terminal problem using temporal synchronization. The proposed cognitive radio MAC (CR-MAC) protocol allows SUs to identify and use the unused frequency spectrum in a way that constrains the level of interference...

  20. H-MAC: A Hybrid MAC Protocol for Wireless Sensor Networks

    CERN Document Server

    Mehta, S; 10.5121/ijcnc.2010.2208

    2010-01-01

    In this paper, we propose a hybrid medium access control protocol (H-MAC) for wireless sensor networks. It is based on the IEEE 802.11's power saving mechanism (PSM) and slotted aloha, and utilizes multiple slots dynamically to improve performance. Existing MAC protocols for sensor networks reduce energy consumptions by introducing variation in an active/sleep mechanism. But they may not provide energy efficiency in varying traffic conditions as well as they did not address Quality of Service (QoS) issues. H-MAC, the propose MAC protocol maintains energy efficiency as well as QoS issues like latency, throughput, and channel utilization. Our numerical results show that H-MAC has significant improvements in QoS parameters than the existing MAC protocols for sensor networks while consuming comparable amount of energy.

  1. Learn Mac OS X Snow Leopard

    CERN Document Server

    Meyers, Scott

    2009-01-01

    You're smart and savvy, but also busy. This comprehensive guide to Apple's Mac OS X 10.6, Snow Leopard, gives you everything you need to know to live a happy, productive Mac life. Learn Mac OS X Snow Leopard will have you up and connected lickity split. With a minimum of overhead and a maximum of useful information, you'll cover a lot of ground in the time it takes other books to get you plugged in. If this isn't your first experience with Mac OS X, skip right to the "What's New in Snow Leopard" sections. You may also find yourself using this book as a quick refresher course or a way

  2. Macintosh Troubleshooting Pocket Guide for Mac OS

    CERN Document Server

    Lerner, David; Corporation, Tekserve

    2009-01-01

    The Macintosh Troubleshooting Pocket Guide covers the most common user hardware and software trouble. It's not just a book for Mac OS X (although it includes tips for OS X and Jaguar), it's for anyone who owns a Mac of any type-- there are software tips going back as far as OS 6. This slim guide distills the answers to the urgent questions that Tekserve's employee's answer every week into a handy guide that fits in your back pocket or alongside your keyboard.

  3. Enhanced Sleep Mode MAC Control for EPON

    DEFF Research Database (Denmark)

    Yan, Ying; Dittmann, Lars

    2011-01-01

    This paper introduces sleep mode operations for EPON. New MAC control functions are proposed to schedule sleep periods. Traffic profiles are considered to optimize energy efficiency and network performances. Simulation results are analyzed in OPNET modeler.......This paper introduces sleep mode operations for EPON. New MAC control functions are proposed to schedule sleep periods. Traffic profiles are considered to optimize energy efficiency and network performances. Simulation results are analyzed in OPNET modeler....

  4. Evaluation of the Intel Westmere-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

  5. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  6. Libera Electron Beam Position Processor

    CERN Document Server

    Ursic, Rok

    2005-01-01

    Libera is a product family delivering unprecedented possibilities for either building powerful single station solutions or architecting complex feedback systems in the field of accelerator instrumentation and controls. This paper presents functionality and field performance of its first member, the electron beam position processor. It offers superior performance with multiple measurement channels delivering simultaneously position measurements in digital format with MHz kHz and Hz bandwidths. This all-in-one product, facilitating pulsed and CW measurements, is much more than simply a high performance beam position measuring device delivering micrometer level reproducibility with sub-micrometer resolution. Rich connectivity options and innate processing power make it a powerful feedback building block. By interconnecting multiple Libera electron beam position processors one can build a low-latency high throughput orbit feedback system without adding additional hardware. Libera electron beam position processor ...

  7. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  8. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  9. 42 CFR 405.1120 - Filing briefs with the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Filing briefs with the MAC. 405.1120 Section 405....1120 Filing briefs with the MAC. Upon request, the MAC will give the party requesting review, as well... ending with the date the brief is received by the MAC will not be counted toward the adjudication...

  10. 42 CFR 423.1974 - Medicare Appeals Council (MAC) review.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Medicare Appeals Council (MAC) review. 423.1974..., MAC review, and Judicial Review § 423.1974 Medicare Appeals Council (MAC) review. An enrollee who is dissatisfied with an ALJ hearing decision may request that the MAC review the ALJ's decision or dismissal as...

  11. 42 CFR 423.2130 - Effect of the MAC's decision.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Effect of the MAC's decision. 423.2130 Section 423... (CONTINUED) MEDICARE PROGRAM VOLUNTARY MEDICARE PRESCRIPTION DRUG BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2130 Effect of the MAC's decision. The MAC's decision is final and binding...

  12. 42 CFR 405.1130 - Effect of the MAC's decision.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Effect of the MAC's decision. 405.1130 Section 405....1130 Effect of the MAC's decision. The MAC's decision is final and binding on all parties unless a Federal district court issues a decision modifying the MAC's decision or the decision is revised as the...

  13. 42 CFR 423.2118 - Obtaining evidence from the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Obtaining evidence from the MAC. 423.2118 Section..., MAC review, and Judicial Review § 423.2118 Obtaining evidence from the MAC. An enrollee may request... the costs of providing these items. If an enrollee requests evidence from the MAC and an opportunity...

  14. 42 CFR 423.2126 - Case remanded by the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Case remanded by the MAC. 423.2126 Section 423.2126... (CONTINUED) MEDICARE PROGRAM VOLUNTARY MEDICARE PRESCRIPTION DRUG BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2126 Case remanded by the MAC. (a) When the MAC may remand a case to the ALJ...

  15. 42 CFR 423.2120 - Filing briefs with the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Filing briefs with the MAC. 423.2120 Section 423... (CONTINUED) MEDICARE PROGRAM VOLUNTARY MEDICARE PRESCRIPTION DRUG BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2120 Filing briefs with the MAC. Upon request, the MAC will give the...

  16. Cluster Algorithm Special Purpose Processor

    Science.gov (United States)

    Talapov, A. L.; Shchur, L. N.; Andreichenko, V. B.; Dotsenko, Vl. S.

    We describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.

  17. Cluster algorithm special purpose processor

    Energy Technology Data Exchange (ETDEWEB)

    Talapov, A.L.; Shchur, L.N.; Andreichenko, V.B.; Dotsenko, V.S. (Landau Inst. for Theoretical Physics, GSP-1 117940 Moscow V-334 (USSR))

    1992-08-10

    In this paper, the authors describe a Special Purpose Processor, realizing the Wolff algorithm in hardware, which is fast enough to study the critical behaviour of 2D Ising-like systems containing more than one million spins. The processor has been checked to produce correct results for a pure Ising model and for Ising model with random bonds. Its data also agree with the Nishimori exact results for spin glass. Only minor changes of the SPP design are necessary to increase the dimensionality and to take into account more complex systems such as Potts models.

  18. Reconfigurable Communication Processor:A New Approach for Network Processor

    Institute of Scientific and Technical Information of China (English)

    孙华; 陈青山; 张文渊

    2003-01-01

    As the traditional RISC +ASIC/ASSP approach for network processor design can not meet the today'srequirements, this paper described an alternate approach, Reconfigurable Processing Architecture, to boost theperformance to ASIC level while reserve the programmability of the traditional RISC based system. This papercovers both the hardware architecture and the software development environment architecture.

  19. Fast, Massively Parallel Data Processors

    Science.gov (United States)

    Heaton, Robert A.; Blevins, Donald W.; Davis, ED

    1994-01-01

    Proposed fast, massively parallel data processor contains 8x16 array of processing elements with efficient interconnection scheme and options for flexible local control. Processing elements communicate with each other on "X" interconnection grid with external memory via high-capacity input/output bus. This approach to conditional operation nearly doubles speed of various arithmetic operations.

  20. ASSP Advanced Sensor Signal Processor.

    Science.gov (United States)

    1984-06-01

    transfer data sad cimeds . When a Processor receives the required data (Image) md/or oamand, that data will be operated on B-3 I I I autonomouly. The...BAN is provided by two separately controled DMA address generator chips (Am29o40). Each of these DMA chips create an 8 bit address. One DMA chip gene

  1. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    Cassava processors' awareness of occupational and environmental hazards ... Majority of the respondents also complained of lack of water (78.4%), lack of ... so as to reduce the problems faced by cassava processors during processing.

  2. SA-MAC:Self-Stabilizing Adaptive MAC Protocol for Wireless Sensor Networks

    Institute of Scientific and Technical Information of China (English)

    波澄; 韩君泽; 李向阳; 王昱; 肖波

    2014-01-01

    A common method of prolonging the lifetime of wireless sensor networks is to use low power duty cycling protocol. Existing protocols consist of two categories: sender-initiated and receiver-initiated. In this paper, we present SA-MAC, a self-stabilizing adaptive MAC protocol for wireless sensor networks. SA-MAC dynamically adjusts the transmission time-slot, waking up time-slot, and packet detection pattern according to current network working condition, such as packet length and wake-up patterns of neighboring nodes. In the long run, every sensor node will find its own transmission phase so that the network will enter a stable stage when the network load and qualities are static. We conduct extensive experiments to evaluate the energy consumption, packet reception rate of SA-MAC in real sensor networking systems. Our results indicate that SA-MAC outperforms other existing protocols.

  3. A wearable real-time image processor for a vision prosthesis.

    Science.gov (United States)

    Tsai, D; Morley, J W; Suaning, G J; Lovell, N H

    2009-09-01

    Rapid progress in recent years has made implantable retinal prostheses a promising therapeutic option in the near future for patients with macular degeneration or retinitis pigmentosa. Yet little work on devices that encode visual images into electrical stimuli have been reported to date. This paper presents a wearable image processor for use as the external module of a vision prosthesis. It is based on a dual-core microprocessor architecture and runs the Linux operating system. A set of image-processing algorithms executes on the digital signal processor of the device, which may be controlled remotely via a standard desktop computer. The results indicate that a highly flexible and configurable image processor can be built with the dual-core architecture. Depending on the image-processing requirements, general-purpose embedded microprocessors alone may be inadequate for implementing image-processing strategies required by retinal prostheses.

  4. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... on FPGA-based processor cores: first, superpipelining enables higher-frequency system clocks, and second, predicated instructions circumvent costly pipeline stalls due to branches. To evaluate their effects, we develop Tinuso, a processor architecture optimized for FPGA implementation. We demonstrate...

  5. Evaluation and Choice of Various Branch Predictors for Low-Power Embedded Processor

    Institute of Scientific and Technical Information of China (English)

    FAN DongRui (范东睿); YANG HongBo (杨洪波); GAO GuangRong (高光荣); ZHAO RongCai (赵荣彩)

    2003-01-01

    Power is an important design constraint in embedded computing systems. To meet the power constraint, microarchitecture and hardware designed to achieve high performance need to be revisited, from both performance and power angles. This paper studies one of them:branch predictor. As well known, branch prediction is critical to exploit instruction level parallelism effectively, but may incur additional power consumption due to the hardware resource dedicated for branch prediction and the extra power consumed on mispredicted branches. This paper explores the design space of branch prediction mechanisms and tries to find the most beneficial one to realize low-power embedded processor. The sample processor studied is Godson-like processor, which is a dual-issue, out-of-order processor with deep pipeline, supporting MIPS instruction set.

  6. 40 CFR 791.45 - Processors.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 31 2010-07-01 2010-07-01 true Processors. 791.45 Section 791.45 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) TOXIC SUBSTANCES CONTROL ACT (CONTINUED) DATA REIMBURSEMENT Basis for Proposed Order § 791.45 Processors. (a) Generally, processors will be...

  7. Mac OS X Snow Leopard试用

    Institute of Scientific and Technical Information of China (English)

    大大

    2009-01-01

    苹果新一代操作系统Mac OS X 10.6 Snow Leopard(雪豹)于8月底上市。根据NPD集团的统计数据,该系统在美国市场前两周的销售非常喜人,是2007年Mac OS X 10.5 Leopard上市销量的2倍以上,是2005年的Mac OS X 10.4 Tiger操作系统的售量的4倍。假如你也对升级价格仅需88元雪豹系统感兴趣,就让我们从一起升级安装开始,体验它独特的魅力。

  8. MacSelfService online tutorial

    CERN Document Server

    CERN. Geneva

    2016-01-01

    Mac Self-Service is a functionality within the Mac Desktop Service built and maintained to empower CERN users by giving them easy access to applications and configurations through the Self-Service application. This tutorial (text attached to the event page) explains how to install Mac Self-Service and how to use it to install applications and printers. Content owner: Vincent Nicolas Bippus Presenter: Pedro Augusto de Freitas Batista Tell us what you think via e-learning.support at cern.ch More tutorials in the e-learning collection of the CERN Document Server (CDS) https://cds.cern.ch/collection/E-learning%20modules?ln=en All info about the CERN rapid e-learning project is linked from http://twiki.cern.ch/ELearning  

  9. Mac OS X Snow Leopard pocket guide

    CERN Document Server

    Seiblod, Chris

    2009-01-01

    Whether you're new to the Mac or a longtime user, this handy book is the quickest way to get up to speed on Snow Leopard. Packed with concise information in an easy-to-read format, Mac OS X Snow Leopard Pocket Guide covers what you need to know and is an ideal resource for problem-solving on the fly. This book goes right to the heart of Snow Leopard, with details on system preferences, built-in applications, and utilities. You'll also find configuration tips, keyboard shortcuts, guides for troubleshooting, lots of step-by-step instructions, and more. Learn about new features and changes s

  10. MacBook Pro Portable Genius

    CERN Document Server

    Miser, Brad

    2012-01-01

    Discover loads of tips and techniques for the newest MacBook Pro You're already ahead of the game with a MacBook Pro. Now you can get even more out the popular Apple notebook with the new edition of this handy, compact book. Crammed with savvy insights and tips on key tools and shortcuts, this book will help you increase your productivity and keep your Apple digital lifestyle on track. From desktop sharing and wireless networking to running Windows applications, this book avoids fluff, doesn't skimp on the essentials, saves you time and hassle, and shows you what you most want to know. Include

  11. Communications systems and methods for subsea processors

    Science.gov (United States)

    Gutierrez, Jose; Pereira, Luis

    2016-04-26

    A subsea processor may be located near the seabed of a drilling site and used to coordinate operations of underwater drilling components. The subsea processor may be enclosed in a single interchangeable unit that fits a receptor on an underwater drilling component, such as a blow-out preventer (BOP). The subsea processor may issue commands to control the BOP and receive measurements from sensors located throughout the BOP. A shared communications bus may interconnect the subsea processor and underwater components and the subsea processor and a surface or onshore network. The shared communications bus may be operated according to a time division multiple access (TDMA) scheme.

  12. MAC2: A Multi-Hop Adaptive MAC Protocol with Packet Concatenation for Wireless Sensor Networks

    Science.gov (United States)

    Nguyen, Kien; Meis, Ulrich; Ji, Yusheng

    Wireless sensor network MAC protocols switch radios off periodically, employing the so-called duty cycle mechanism, in order to conserve battery power that would otherwise be wasted by energy-costly idle listening. In order to minimize the various negative side-effects of the original scheme, especially on latency and throughput, various improvements have been proposed. In this paper, we introduce a new MAC protocol called MAC2(Multi-hop Adaptive with packet Concatenation-MAC) which combines three promising techniques into one protocol. Firstly, the idea to forward packets over multiple hops within one operational cycle as initially introduced in RMAC. Secondly, an adaptive method that adjusts the listening period according to traffic load minimizing idle listening. Thirdly, a packet concatenation scheme that not only increases throughput but also reduces power consumption that would otherwise be incurred by additional control packets. Furthermore, MAC2 incorporates the idea of scheduling data transmissions with minimum latency, thereby performing packet concatenation together with the multi-hop transmission mechanism in a most efficient way. We evaluated MAC2 using the prominent network simulator ns-2 and the results show that our protocol can outperform DW-MAC — a state of the art protocol both in terms of energy efficiency and throughput.

  13. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  14. An Experimental Digital Image Processor

    Science.gov (United States)

    Cok, Ronald S.

    1986-12-01

    A prototype digital image processor for enhancing photographic images has been built in the Research Laboratories at Kodak. This image processor implements a particular version of each of the following algorithms: photographic grain and noise removal, edge sharpening, multidimensional image-segmentation, image-tone reproduction adjustment, and image-color saturation adjustment. All processing, except for segmentation and analysis, is performed by massively parallel and pipelined special-purpose hardware. This hardware runs at 10 MHz and can be adjusted to handle any size digital image. The segmentation circuits run at 30 MHz. The segmentation data are used by three single-board computers for calculating the tonescale adjustment curves. The system, as a whole, has the capability of completely processing 10 million three-color pixels per second. The grain removal and edge enhancement algorithms represent the largest part of the pipelined hardware, operating at over 8 billion integer operations per second. The edge enhancement is performed by unsharp masking, and the grain removal is done using a collapsed Walsh-hadamard transform filtering technique (U.S. Patent No. 4549212). These two algo-rithms can be realized using four basic processing elements, some of which have been imple-mented as VLSI semicustom integrated circuits. These circuits implement the algorithms with a high degree of efficiency, modularity, and testability. The digital processor is controlled by a Digital Equipment Corporation (DEC) PDP 11 minicomputer and can be interfaced to electronic printing and/or electronic scanning de-vices. The processor has been used to process over a thousand diagnostic images.

  15. A simulation study of TaMAC protocol using network simulator 2.

    Science.gov (United States)

    Ullah, Sana; Kwak, Kyung Sup

    2012-10-01

    A Wireless Body Area Network (WBAN) is expected to play a significant role in future healthcare system. It interconnects low-cost and intelligent sensor nodes in, on, or around a human body to serve a variety of medical applications. It can be used to diagnose and treat patients with chronic diseases such as hypertensions, diabetes, and cardiovascular diseases. The lightweight sensor nodes integrated in WBAN require low-power operation, which can be achieved using different optimization techniques. We introduce a Traffic-adaptive MAC protocol (TaMAC) for WBAN that supports dual wakeup mechanisms for normal, emergency, and on-demand traffic. In this letter, the TaMAC protocol is simulated using a well-known Network Simulator 2 (NS-2). The problem of multiple emergency nodes is solved using both wakeup radio and CSMA/CA protocol. The power consumption, delay, and throughput performance are closely compared with beacon-enabled IEEE 802.15.4 MAC protocol using extensive simulations.

  16. The UA1 trigger processor

    CERN Document Server

    Grayer, G H

    1981-01-01

    Experiment UA1 is a large multipurpose spectrometer at the CERN proton-antiproton collider. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead-time losses due to the bunched nature of the beam. To achieve this fast 8-bit charge to digital converters have been built followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, and to transverse energy in the other. Each processor forms four sums from a chosen combination of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in...

  17. Taxonomy of Data Prefetching for Multicore Processors

    Institute of Scientific and Technical Information of China (English)

    Surendra Byna; Yong Chen; Xian-He Sun

    2009-01-01

    Data prefetching is an effective data access latency hiding technique to mask the CPU stall caused by cache misses and to bridge the performance gap between processor and memory. With hardware and/or software support, data prefetching brings data closer to a processor before it is actually needed. Many prefetching techniques have been developed for single-core processors. Recent developments in processor technology have brought multicore processors into mainstream.While some of the single-core prefetching techniques are directly applicable to multicore processors, numerous novel strategies have been proposed in the past few years to take advantage of multiple cores. This paper aims to provide a comprehensive review of the state-of-the-art prefetching techniques, and proposes a taxonomy that classifies various design concerns in developing a prefetching strategy, especially for multicore processors. We compare various existing methods through analysis as well.

  18. Results from the MAC Vertex chamber

    Energy Technology Data Exchange (ETDEWEB)

    Nelson, H.N.

    1987-05-01

    The design, construction, and performance characteristics of a high precision gaseous drift chamber made of thin walled proportional tubes are described. The device achieved an average spatial resolution of 45 ..mu..m in use for physics analysis with the MAC detector. The B-lifetime result obtained with this chamber is discussed.

  19. MacIntyre, Managerialism and Universities

    Science.gov (United States)

    Stolz, Steven A.

    2017-01-01

    MacIntyre's earlier work and concern with social science enquiry not only exposes its limits, but also provides an insight into how its knowledge claims have been put to ideological use. He maintains that the institutional embodiment of these ideological ideas is the bureaucratic manager who has had a negative role to play in social structures…

  20. Design and implementation of a high performance network security processor

    Science.gov (United States)

    Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

    2010-03-01

    The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

  1. AH-MAC: Adaptive Hierarchical MAC Protocol for Low-Rate Wireless Sensor Network Applications

    Directory of Open Access Journals (Sweden)

    Adnan Ismail Al-Sulaifanie

    2017-01-01

    Full Text Available This paper proposes an adaptive hierarchical MAC protocol (AH-MAC with cross-layer optimization for low-rate and large-scale wireless sensor networks. The main goal of the proposed protocol is to combine the strengths of LEACH and IEEE 802.15.4 while offsetting their weaknesses. The predetermined cluster heads are supported with an energy harvesting circuit, while the normal nodes are battery-operated. To prolong the network’s operational lifetime, the proposed protocol transfers most of the network’s activities to the cluster heads while minimizing the node’s activity. Some of the main features of this protocol include energy efficiency, self-configurability, scalability, and self-healing. The simulation results showed great improvement of the AH-MAC over LEACH protocol in terms of energy consumption and throughput. AH-MAC consumes eight times less energy while improving throughput via acknowledgment support.

  2. CA-MAC: A Novel MAC Protocol to Alleviate Congestion in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    WU, J.

    2013-11-01

    Full Text Available Even if the traffic pattern is known and the network topology is simple, a strong congestion can take place in wireless sensor networks (WSNs due to the data gathering effect and the duty-cycle operation. In this paper, we propose a novel medium access control (MAC protocol to alleviate the congestion, which is referred to as the congestion alleviation-MAC (CA-MAC. It adopts an adaptive contention window (ACW, which allows the nodes with more buffered packets to transmit with a higher probability, as well as an intelligent burst packet transmission when the congested nodes seize the channel. Simulations are performed in NS-2, and results show that the proposed CA-MAC protocol achieves a good performance in terms of the packet delivery ratio (PDR, power consumption, throughput, and average latency.

  3. Exposure histories of lunar meteorites: ALHA81005, MAC88104, MAC88105, and Y791197

    Energy Technology Data Exchange (ETDEWEB)

    Nishiizumi, K.; Arnold, J.R. (Univ. of California, San Diego, (United States)); Klein, J.; Fink, D.; Middleton, R. (Univ. of Pennsylvania, Philadelphia (United States)); Kubik, P.W.; Sharma, P.; Elmore, D. (Univ. of Rochester, NY (United States)); Reedy, R.C. (Los Alamos National Lab., NM (United States))

    1991-11-01

    The cosmogenic radionuclides {sup 41}Ca, {sup 36}Cl, {sup 26}Al, and {sup 10}Be in the Allan Hills 81005, MacAlpine Hills 88104, MacAlpine Hills 88105,and Yamato 791197 meteorites were measured by accelerator mass spectrometry (AMS). {sup 53}Mn in Allan Hills 81005 and Yamato 791197 was measured by activation. These four lunar meteorites experienced similar histories. They were ejected from near the surface of the Moon ranging in depth down to 400 g/cm{sup 2} and had very short transition times (less than 0.1 Ma) from the Moon to the Earth. A comparison of the cosmogenic nuclide concentrations in MacAlpine Hills 88104 and MacAlpine Hills 88105 clearly indicates that they are a pair from the same fall.

  4. 42 CFR 405.1126 - Case remanded by the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Case remanded by the MAC. 405.1126 Section 405.1126....1126 Case remanded by the MAC. (a) When the MAC may remand a case. Except as specified in § 405.1122(c), the MAC may remand a case in which additional evidence is needed or additional action by the ALJ is...

  5. Reduction in standard MAC and MAC for intubation after clonidine premedication in children.

    Science.gov (United States)

    Inomata, S; Kihara, S; Yaguchi, Y; Baba, Y; Kohda, Y; Toyooka, H

    2000-11-01

    We examined the relative effects of different doses of oral clonidine on the MAC for endotracheal intubation (MACEI) and the MAC for skin incision (MAC) in children. We studied 90 children (15 in each group) (age range 2-8 yr, weight 10-27 kg, height 89-124 cm) who received one of three preanaesthetic medications: placebo (control), oral clonidine 2 micrograms kg-1, or oral clonidine 4 micrograms kg-1 100 min before anaesthesia. Anaesthesia was induced and maintained with sevoflurane in oxygen and air without i.v. anesthetics and neuromuscular relaxants. The end-tidal sevoflurane concentration was kept constant for > or = 15 min before tracheal intubation or skin incision. MACs were determined using Dixon's 'up-and-down method'. Mean (SD) MACEIs of sevoflurane were 2.9 (0.1)%, 2.5 (0.1)% and 1.9 (0.1)% (P clonidine 2 micrograms kg-1 and clonidine 4 micrograms kg-1 groups. The MACEIs and MACs decreased dose-dependently. The MACEI/MAC ratio (1.4) was not affected by clonidine.

  6. CR-MAC: A Multichannel MAC Protocol for Cognitive Radio AD HOC Networks

    Directory of Open Access Journals (Sweden)

    S. M. Kamruzzaman

    2010-09-01

    Full Text Available This paper proposes a cross-layer based cognitive radio multichannel medium access control (MACprotocol with TDMA, which integrate the spectrum sensing at physical (PHY layer and the packetscheduling at MAC layer, for the ad hoc wireless networks. The IEEE 802.11 standard allows for the useof multiple channels available at the PHY layer, but its MAC protocol is designed only for a singlechannel. A single channel MAC protocol does not work well in a multichannel environment, because ofthe multichannel hidden terminal problem. Our proposed protocol enables secondary users (SUs toutilize multiple channels by switching channels dynamically, thus increasing network throughput. In ourproposed protocol, each SU is equipped with only one spectrum agile transceiver, but solves themultichannel hidden terminal problem using temporal synchronization. The proposed cognitive radioMAC (CR-MAC protocol allows SUs to identify and use the unused frequency spectrum in a way thatconstrains the level of interference to the primary users (PUs. Our scheme improves network throughputsignificantly, especially when the network is highly congested. The simulation results show that ourproposed CR-MAC protocol successfully exploits multiple channels and significantly improves networkperformance by using the licensed spectrum band opportunistically and protects PUs from interference,even in hidden terminal situations.

  7. 42 CFR 423.2128 - Action of the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Action of the MAC. 423.2128 Section 423.2128 Public...) MEDICARE PROGRAM VOLUNTARY MEDICARE PRESCRIPTION DRUG BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2128 Action of the MAC. (a) After it has reviewed all the evidence in the...

  8. 42 CFR 405.1118 - Obtaining evidence from the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Obtaining evidence from the MAC. 405.1118 Section... Council Review § 405.1118 Obtaining evidence from the MAC. A party may request and receive a copy of all... these items. If a party requests evidence from the MAC and an opportunity to comment on that evidence...

  9. 42 CFR 405.1128 - Action of the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Action of the MAC. 405.1128 Section 405.1128 Public... the MAC. (a) After it has reviewed all the evidence in the administrative record and any additional evidence received, subject to the limitations on MAC consideration of additional evidence in § 405.1122...

  10. 42 CFR 422.608 - Medicare Appeals Council (MAC) review.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Medicare Appeals Council (MAC) review. 422.608... and Appeals § 422.608 Medicare Appeals Council (MAC) review. Any party to the hearing, including the MA organization, who is dissatisfied with the ALJ hearing decision, may request that the MAC review...

  11. MAC 700 Wash高亮度灯具

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    马田最新推出的MAC 700 Wash高亮度灯具继承了MAC系列的传统优点.具有与MAC 700 Profile相同的强大功能、模组桔构和出色设计,是MAC 700 Profile的“最佳搭档”。

  12. A light hydrocarbon fuel processor producing high-purity hydrogen

    Science.gov (United States)

    Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

    This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with thermal efficiency is

  13. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  14. Digital Signal Processor For GPS Receivers

    Science.gov (United States)

    Thomas, J. B.; Meehan, T. K.; Srinivasan, J. M.

    1989-01-01

    Three innovative components combined to produce all-digital signal processor with superior characteristics: outstanding accuracy, high-dynamics tracking, versatile integration times, lower loss-of-lock signal strengths, and infrequent cycle slips. Three components are digital chip advancer, digital carrier downconverter and code correlator, and digital tracking processor. All-digital signal processor intended for use in receivers of Global Positioning System (GPS) for geodesy, geodynamics, high-dynamics tracking, and ionospheric calibration.

  15. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...... through the use of micro-benchmarks that our principles guide the design of a processor core that improves performance by an average of 38% over a similar Xilinx MicroBlaze configuration....

  16. Isolation and characterisation of human gingival margin-derived STRO-1/MACS1 and MACS2 cell populations

    Institute of Scientific and Technical Information of China (English)

    Karim M Fawzy El-Sayed; Sebastian Paris; Christian Graetz; Neemat Kassem; Mohamed Mekhemar; Hendrick Ungefroren; Fred Fandrich; Christof Dorfer

    2015-01-01

    Recently, gingival margin-derived stem/progenitor cells isolated via STRO-1/magnetic activated cell sorting (MACS) showed remarkable periodontal regenerative potential in vivo. As a second-stage investigation, the present study’s aim was to perform in vitro characterisation and comparison of the stem/progenitor cell characteristics of sorted STRO-1-positive (MACS1) and STRO-1-negative (MACS2) cell populations from the human free gingival margin. Cells were isolated from the free gingiva using a minimally invasive technique and were magnetically sorted using anti-STRO-1 antibodies. Subsequently, the MACS1 and MACS2 cell fractions were characterized by flow cytometry for expression of CD14, CD34, CD45, CD73, CD90, CD105, CD146/MUC18 and STRO-1. Colony-forming unit (CFU) and multilineage differentiation potential were assayed for both cell fractions. Mineralisation marker expression was examined using real-time polymerase chain reaction (PCR). MACS1 and MACS2 cell fractions showed plastic adherence. MACS1 cells, in contrast to MACS2 cells, showed all of the predefined mesenchymal stem/progenitor cell characteristics and a significantly higher number of CFUs (P,0.01). More than 95%of MACS1 cells expressed CD105, CD90 and CD73;lacked the haematopoietic markers CD45, CD34 and CD14, and expressed STRO-1 and CD146/MUC18. MACS2 cells showed a different surface marker expression profile, with almost no expression of CD14 or STRO-1, and more than 95%of these cells expressed CD73, CD90 and CD146/MUC18, as well as the haematopoietic markers CD34 and CD45 and CD105. MACS1 cells could be differentiated along osteoblastic, adipocytic and chondroblastic lineages. In contrast, MACS2 cells demonstrated slight osteogenic potential. Unstimulated MACS1 cells showed significantly higher expression of collagen I (P,0.05) and collagen III (P,0.01), whereas MACS2 cells demonstrated higher expression of osteonectin (P,0.05;Mann–Whitney). The present study is the first to compare gingival

  17. MacBook All-in-One For Dummies

    CERN Document Server

    Chambers, Mark L

    2011-01-01

    Get comfortable and confident with your MacBook! Combining the fun-but-straightforward content of nine minibooks, this new edition of MacBook All-in-One For Dummies delivers helpful coverage of the rich features and essential tools you need to know to use the MacBook to its fullest potential. You'll learn an array of MacBook basics while veteran author Mark Chambers walks you through setting up your MacBook, running programs, finding files with Finder, searching with Spotlight, keeping track with Address Book, enjoying music with iTunes, creating cool multimedia projects with iLife, and more.

  18. Concurrent Programming in Mac OS X and iOS Unleash Multicore Performance with Grand Central Dispatch

    CERN Document Server

    Nahavandipoor, Vandad

    2011-01-01

    Now that multicore processors are coming to mobile devices, wouldn't it be great to take advantage of all those cores without having to manage threads? This concise book shows you how to use Apple's Grand Central Dispatch (GCD) to simplify programming on multicore iOS devices and Mac OS X. Managing your application's resources on more than one core isn't easy, but it's vital. Apps that use only one core in a multicore environment will slow to a crawl. If you know how to program with Cocoa or Cocoa Touch, this guide will get you started with GCD right away, with many examples to help you writ

  19. The case for a generic implant processor.

    Science.gov (United States)

    Strydis, Christos; Gaydadjiev, Georgi N

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably selected processor simulator, various operational aspects of the application are being monitored. Findings on performance, cache behavior, branch prediction, power consumption, energy expenditure and instruction mixes are presented and analyzed. The suitability of such an implant processor and directions for future work are given.

  20. A Novel Approach of Pattern Detection Processor for Multipurpose Devices

    Directory of Open Access Journals (Sweden)

    R. Indu Praveena,

    2014-06-01

    Full Text Available In this day and age, itinerant handsets coalesce the functionality of preset phones and PDAs. Unfortunately, mobile handsets development system has been determined by souk demand, focusing on new features and neglecting security. So, it is imperative to study the lying on hand face with the aim of facing the transportable handsets threat suppression development along by way of the different techniques as well seeing that methodologies with the intention of used to facade folks challenges and contain the mobile handsets malwares. A TCAM-based virus-detection entry provides towering throughput, but also challenges for small power and low cost. In this paper, an adaptively dividable equal-port BiTCAM (unifying dual and ternary CAMs is projected to achieve a high-throughput, low-power, and low-cost virus-detection workspace for mobile devices. The proposed dual-port BiTCAM is realized with the dual-port AND-type match-line scheme which is composed of dual -port active AND gates. The dual-port designs diminish power expenditure through supplement storage efficiency owing to shared storage spaces. In totaling, the dividable BiTCAM provides high flexibility for regularly update the virus-database. In this paper, am presenting a multi blueprint matching algorithm with low area and less complexity. Prior to going to store patterns within database; patterns decoding is done with an efficient approach like TCAM. together ternary and twofold combines to form TCAM patterns. This paper is developed with an adaptively dividable dual-port BiTCAM to achieve a high-throughput, low-power, and low-cost pattern-detection processor for multipurpose devices.

  1. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  2. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie L.; Adam, Niklas M.; Barta, Daniel; Meyer, Caitlin E.; Pensinger, Stuart; Vega, Leticia M.; Callahan, Michael R.; Flynn, Michael; Wheeler, Ray; hide

    2013-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrification and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  3. Modeling MAC layer for powerline communications networks

    Science.gov (United States)

    Hrasnica, Halid; Haidine, Abdelfatteh

    2001-02-01

    The usage of electrical power distribution networks for voice and data transmission, called Powerline Communications, becomes nowadays more and more attractive, particularly in the telecommunication access area. The most important reasons for that are the deregulation of the telecommunication market and a fact that the access networks are still property of former monopolistic companies. In this work, first we analyze a PLC network and system structure as well as a disturbance scenario in powerline networks. After that, we define a logical structure of the powerline MAC layer and propose the reservation MAC protocols for the usage in the PLC network which provides collision free data transmission. This makes possible better network utilization and realization of QoS guarantees which can make PLC networks competitive to other access technologies.

  4. Seán MacDiarmada

    Directory of Open Access Journals (Sweden)

    Madden

    2016-12-01

    Full Text Available Seán MacDiarmada: Signatory to Proclamation – Executed after the Rising of 1916 - Leitrim to Kilmainham was written by Tom Madden to coincide with the 1916/2016 centenary commemorations. The play was first performed at the Mullagh Arts Festival in Cavan during September 2016 and provides a lively account of the background and activism of one the seven leaders of the Easter Rising of 1916. The action plays out over twelve scenes taking in MacDiarmada's journey from teacher to revolutionary activist culminating in a deeply flawed court-martial and his subsequent execution by a British Army firing squad on May 12th, 1916.

  5. Earth tides in MacDonald's model

    CERN Document Server

    Ferraz-Mello, S

    2013-01-01

    We expand the equations used in MacDonald's 1964 theory and Fourier analyze the tidal variations of the height at one point on the Earth surface, and also the tidal potential at such point. It is shown that no intrinsic law is relating the lag of the tide components to their frequencies. In other words, no simple rheology is being intrinsically fixed by MacDonald's equations. The same is true of the modification proposed by Singer(1968). At variance with these two cases, the modification proposed by Williams and Efroimsky (2012) fix the standard Darwin rheology in which the lags are proportional to the frequencies and their model is, in this sense, equivalent to Mignard's 1979 formulation of Darwin's theory.

  6. MacBook Pro portable genius

    CERN Document Server

    Gruman, Galen

    2013-01-01

    Learn the skills, tools and shortcuts you need in order to make the most of your MacBook Pro This easy-to-use, compact guide skips the fluff and gets right to the essentials so that you can maximize all the latest features of the MacBook Pro. Packed with savvy insights and tips on key tools and shortcuts, this handy book aims to help you increase your productivity and save you time and hassle. From desktop sharing and wireless networking to running Windows applications and more, this book shows you what you want to know. Includes the latest version of OS X, iCloud, FaceTime, and moreCovers al

  7. Performance Analysis of MAC Layer Protocols in Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    Hameeza Ahmed

    2014-10-01

    Full Text Available Media Access Control (MAC layer protocols have a critical role in making a typical Wireless Sensor Network (WSN more reliable and efficient. Choice of MAC layer protocol and other factors including number of nodes, mobility, traffic rate and playground size dictates the performance of a particular WSN. In this paper, the performance of an experimental WSN is evaluated using different MAC layer protocols. In this experiment, a WSN is created using OMNeT++ MiXiM network simulator and its performance in terms of packet delivery ratio and mean latency is evaluated. The simulation results show that IEEE 802.11 MAC layer protocol performs better than CSMA, B-MAC and IEEE 802.15.4 MAC layer protocols. In the considered scenario, IEEE 802.15.4 is ranked second in performance, followed by CSMA and B-MAC.

  8. 关于Mac OS X Lion

    Institute of Scientific and Technical Information of China (English)

    饭桶

    2011-01-01

    Lion是Mac OS X操作系统的第七个版本,第一个版本是2001年发布的Cheetah(猎豹).或许很多Windows用户会认为,Lion不过是一次升级,主版本仍然是Mac OSX.那么我不介意稍微解释一下:Mac OS X对应的层次是Windows,Cheetah或者Lion相当于XP,或者7.因此即使从软件工程的角度看,Lion也是一个全新的操作系统.由于重新编译了核心,Lion的安装文件只有3.6GB大小,比上一代(Snow Leopard)减少了近一半的体积,这种比旧版本体积更小的新操作系统在历史上可不多见.

  9. Power Saving MAC Protocols for WSNs and Optimization of S-MAC Protocol

    Directory of Open Access Journals (Sweden)

    Simarpreet Kaur

    2012-11-01

    Full Text Available Low power MAC protocols have received a lot of consideration in the last few years because of their influence on the lifetime of wireless sensor networks. Since, sensors typically operate on batteries, replacement of which is often difficult. A lot of work has been done to minimize the energy expenditure and prolong the sensor lifetime through energy efficient designs, across layers. Meanwhile, the sensor network should be able to maintain a certain throughput in order to fulfill the QoS requirements of the end user, and to ensure the constancy of the network. This paper introduces different types of MAC protocols used for WSNs and proposes S‐MAC, a Medium‐Access Control protocol designed for Wireless Sensor Networks. S‐MAC uses a few innovative techniques to reduce energy consumption and support selfconfiguration. A new protocol is suggested to improve the energy efficiency, latency and throughput of existing MAC protocol for WSNs. A modification of the protocol is then proposed to eliminate the need for some nodes to stay awake longer than the other nodes which improves the energy efficiency, latency and throughput and hence increases the life span of a wireless sensor network.

  10. SR-MAC: A Low Latency MAC Protocol for Multi-Packet Transmissions in Wireless Sensor Networks

    Institute of Scientific and Technical Information of China (English)

    Hong-Wei Tang; Jian-Nong Cao; Xue-Feng Liu; Cai-Xia Sun

    2013-01-01

    Event detection is one of the major applications of wireless sensor networks (WSNs).Most of existing medium access control (MAC) protocols are mainly optimized for the situation under which an event only generates one packet on a single sensor node.When an event generates multiple packets on a single node,the performance of these MAC protocols degrades rapidly.In this paper,we present a new synchronous duty-cycle MAC protocol called SR-MAC for the event detection applications in which multiple packets are generated on a single node.SR-MAC introduces a new scheduling mechanism that reserves few time slots during the SLEEP period for the nodes to transmit multiple packets.By this approach,SR-MAC can schedule multiple packets generated by an event on a single node to be forwarded over multiple hops in one operational cycle without collision.We use event delivery latency (EDL) and event delivery ratio (EDR) to measure the event detection capability of the SR-MAC protocol.Through detailed ns-2 simulation,the results show that SR-MAC can achieve lower EDL,higher EDR and higher network throughput with guaranteed energy efficiency compared with R-MAC,DW-MAC and PR-MAC.

  11. Ultrafast Fourier-transform parallel processor

    Energy Technology Data Exchange (ETDEWEB)

    Greenberg, W.L.

    1980-04-01

    A new, flexible, parallel-processing architecture is developed for a high-speed, high-precision Fourier transform processor. The processor is intended for use in 2-D signal processing including spatial filtering, matched filtering and image reconstruction from projections.

  12. Adapting implicit methods to parallel processors

    Energy Technology Data Exchange (ETDEWEB)

    Reeves, L.; McMillin, B.; Okunbor, D.; Riggins, D. [Univ. of Missouri, Rolla, MO (United States)

    1994-12-31

    When numerically solving many types of partial differential equations, it is advantageous to use implicit methods because of their better stability and more flexible parameter choice, (e.g. larger time steps). However, since implicit methods usually require simultaneous knowledge of the entire computational domain, these methods axe difficult to implement directly on distributed memory parallel processors. This leads to infrequent use of implicit methods on parallel/distributed systems. The usual implementation of implicit methods is inefficient due to the nature of parallel systems where it is common to take the computational domain and distribute the grid points over the processors so as to maintain a relatively even workload per processor. This creates a problem at the locations in the domain where adjacent points are not on the same processor. In order for the values at these points to be calculated, messages have to be exchanged between the corresponding processors. Without special adaptation, this will result in idle processors during part of the computation, and as the number of idle processors increases, the lower the effective speed improvement by using a parallel processor.

  13. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural

  14. Multi-output programmable quantum processor

    OpenAIRE

    Yu, Yafei; Feng, Jian; Zhan, Mingsheng

    2002-01-01

    By combining telecloning and programmable quantum gate array presented by Nielsen and Chuang [Phys.Rev.Lett. 79 :321(1997)], we propose a programmable quantum processor which can be programmed to implement restricted set of operations with several identical data outputs. The outputs are approximately-transformed versions of input data. The processor successes with certain probability.

  15. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... AND ORDERS; MISCELLANEOUS COMMODITIES), DEPARTMENT OF AGRICULTURE POPCORN PROMOTION, RESEARCH, AND CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14 Processor. Processor means a person engaged in the preparation of unpopped popcorn for the market who...

  16. The TM3270 Media-processor

    NARCIS (Netherlands)

    van de Waerdt, J.W.

    2006-01-01

    I n this thesis, we present the TM3270 VLIW media-processor, the latest of TriMedia processors, and describe the innovations with respect to its prede- cessor: the TM3260. We describe enhancements to the load/store unit design, such as a new data prefetching technique, and architectural enhancements

  17. Advanced Multiple Processor Configuration Study. Final Report.

    Science.gov (United States)

    Clymer, S. J.

    This summary of a study on multiple processor configurations includes the objectives, background, approach, and results of research undertaken to provide the Air Force with a generalized model of computer processor combinations for use in the evaluation of proposed flight training simulator computational designs. An analysis of a real-time flight…

  18. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably se

  19. An Empirical Evaluation of XQuery Processors

    NARCIS (Netherlands)

    Manegold, S.

    2008-01-01

    This paper presents an extensive and detailed experimental evaluation of XQuery processors. The study consists of running five publicly available XQuery benchmarks --- the Michigan benchmark (MBench), XBench, XMach-1, XMark and X007 --- on six XQuery processors, three stand-alone (file-based) XQuery

  20. The Case for a Generic Implant Processor

    NARCIS (Netherlands)

    Strydis, C.; Gaydadjiev, G.N.

    2008-01-01

    A more structured and streamlined design of implants is nowadays possible. In this paper we focus on implant processors located in the heart of implantable systems. We present a real and representative biomedical-application scenario where such a new processor can be employed. Based on a suitably

  1. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  2. Verilog Implementation of 32-Bit CISC Processor

    Directory of Open Access Journals (Sweden)

    P.Kanaka Sirisha

    2016-04-01

    Full Text Available The Project deals with the design of the 32-Bit CISC Processor and modeling of its components using Verilog language. The Entire Processor uses 32-Bit bus to deal with all the registers and the memories. This Processor implements various arithmetic, logical, Data Transfer operations etc., using variable length instructions, which is the core property of the CISC Architecture. The Processor also supports various addressing modes to perform a 32-Bit instruction. Our Processor uses Harvard Architecture (i.e., to have a separate program and data memory and hence has different buses to negotiate with the Program Memory and Data Memory individually. This feature enhances the speed of our processor. Hence it has two different Program Counters to point to the memory locations of the Program Memory and Data Memory.Our processor has ‘Instruction Queuing’ which enables it to save the time needed to fetch the instruction and hence increases the speed of operation. ‘Interrupt Service Routine’ is provided in our Processor to make it address the Interrupts.

  3. Upgrade of the PreProcessor system for the ATLAS level-1 calorimeter trigger

    Energy Technology Data Exchange (ETDEWEB)

    Khomich, A, E-mail: khomich@kip.uni-heidelberg.de [Kirchhoff-Institut fuer Physik, Universitaet Heidelberg, Im Neuenheimer Feld 227, 69120 Heidelberg (Germany)

    2010-12-15

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-P{sub T} objects in the ATLAS calorimeters within a fixed latency of 2.5 us. It consists of three subsystems: the PreProcessor which conditions and digitises analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten year old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to enhance the flexibility of the digital processing and to profit from state-of-the-art electronics. The development and first test results are presented.

  4. W-MAC: a workload-aware MAC protocol for heterogeneous convergecast in wireless sensor networks.

    Science.gov (United States)

    Xia, Ming; Dong, Yabo; Lu, Dongming

    2011-01-01

    The power consumption and latency of existing MAC protocols for wireless sensor networks (WSNs) are high in heterogeneous convergecast, where each sensor node generates different amounts of data in one convergecast operation. To solve this problem, we present W-MAC, a workload-aware MAC protocol for heterogeneous convergecast in WSNs. A subtree-based iterative cascading scheduling mechanism and a workload-aware time slice allocation mechanism are proposed to minimize the power consumption of nodes, while offering a low data latency. In addition, an efficient schedule adjustment mechanism is provided for adapting to data traffic variation and network topology change. Analytical and simulation results show that the proposed protocol provides a significant energy saving and latency reduction in heterogeneous convergecast, and can effectively support data aggregation to further improve the performance.

  5. Notas sobre dois livros de MacIntyre Notes on two books by MacIntyre

    Directory of Open Access Journals (Sweden)

    Isabel Ribeiro de Oliveira

    2005-04-01

    Full Text Available Os conceitos centrais da teoria da justiça desenvolvida por Alasdair MacIntyre - prática, narrativa e tradição - ocupam o núcleo da análise feita acerca de dois de seus livros: Depois da Virtude e Justiça de Quem? Qual racionalidade?. O artigo considera a relação, em MacIntyre, entre ética e história, virtude e relativismo, bem como apresenta seu conceito do Eu, como corretivos à anomia contemporânea.The central concepts of MacIntyre's approach to justice - practice, narrative and tradition - constitute the main trust of the analysis of two of his books: After Virtue and Whose justice? Which rationality? The article elaborates on the relationship of ethics to history, of virtues to relativism as well as his conception of the self as correctives to the pervasive anomie in contemporary societies.

  6. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  7. Monitored Anaesthesia Care (MAC in antalgic surgery

    Directory of Open Access Journals (Sweden)

    Giovanni Maria Pisanu

    2011-09-01

    Full Text Available The use of surgical techniques for pain relief in the treatment of chronic-persistent pain unresponsive to drug therapy is experiencing a growing spread application in algology. These techniques have set themselves the goal of removing the pain after treatment. Therefore, not always, percutaneous or open procedures are carried out with due precaution necessary to alleviate the patient discomfort and suffering during the surgical intervention. We present our personal experience in the use of this technique Monitored Anaesthesia Care (MAC for patients undergoing surgical treatment of pain management at our Regional Center of Pain Management.

  8. One of the First Portable Macs

    CERN Multimedia

    1989-01-01

    It was one of the first portable macs released. The Portable had many new advances in mobile computing : The display was crispy clear, and looked beautiful when used in daylight ; The Portable came with a Lead-acid gel/cell battery that could run a anywhere from 6 -12 hours ; It supported to internal hard drives, and an external one. The reaction to the laptop was weak because it was slow, it had no capacity for expansion, it weighed heavily, its price was expensive. It has been stayed 1 year and half on the market.

  9. Energy Efficient MAC for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Pekka KOSKELA

    2010-10-01

    Full Text Available This paper considers an overlay solution for asynchronous Medium Access Control (MAC protocols in a duty-cycled wireless sensor network (WSN. The solution extends sleeping times and corrects time drift when the sampling rate is low. The sleeping time is adjusted according to the requisite data sampling rate and the delay requirements of the prevailing application. This and the time drift correction considerably reduced idle listening and thus also decreased power consumption. When the power consumption is reduced, the life of wireless sensor nodes extends.

  10. Enabling Future Robotic Missions with Multicore Processors

    Science.gov (United States)

    Powell, Wesley A.; Johnson, Michael A.; Wilmot, Jonathan; Some, Raphael; Gostelow, Kim P.; Reeves, Glenn; Doyle, Richard J.

    2011-01-01

    Recent commercial developments in multicore processors (e.g. Tilera, Clearspeed, HyperX) have provided an option for high performance embedded computing that rivals the performance attainable with FPGA-based reconfigurable computing architectures. Furthermore, these processors offer more straightforward and streamlined application development by allowing the use of conventional programming languages and software tools in lieu of hardware design languages such as VHDL and Verilog. With these advantages, multicore processors can significantly enhance the capabilities of future robotic space missions. This paper will discuss these benefits, along with onboard processing applications where multicore processing can offer advantages over existing or competing approaches. This paper will also discuss the key artchitecural features of current commercial multicore processors. In comparison to the current art, the features and advancements necessary for spaceflight multicore processors will be identified. These include power reduction, radiation hardening, inherent fault tolerance, and support for common spacecraft bus interfaces. Lastly, this paper will explore how multicore processors might evolve with advances in electronics technology and how avionics architectures might evolve once multicore processors are inserted into NASA robotic spacecraft.

  11. Essential Mac OS X panther server administration integrating Mac OS X server into heterogeneous networks

    CERN Document Server

    Bartosh, Michael

    2004-01-01

    If you've ever wondered how to safely manipulate Mac OS X Panther Server's many underlying configuration files or needed to explain AFP permission mapping--this book's for you. From the command line to Apple's graphical tools, the book provides insight into this powerful server software. Topics covered include installation, deployment, server management, web application services, data gathering, and more

  12. APC-MAC/TA: Adaptive Power Controlled MAC Protocol with Traffic Awareness for Wireless Sensor Networks

    Science.gov (United States)

    Woo, Seok; Kim, Kiseon

    In this paper, we propose an adaptive power controlled MAC protocol with a traffic-aware scheme specifically designed to reduce both energy and latency in wireless sensor networks. Typically, existing MAC protocols for sensor networks sacrifice latency performance for node energy efficiency. However, some sensor applications for emergencies require rather fast transmissions of sensed data, where we need to consider both energy and latency together. The proposed MAC protocol includes two novel ideas: one is a transmission power control scheme for improving latency in high traffic loads, and the other is a traffic-aware scheme to save more energy in low traffic loads. The transmission power control scheme increases channel utilization by mitigating interference between nodes, and the traffic-aware scheme allows nodes to sleep to reduce idle energy consumption when there are no traffic loads in a network. Simulation results show that the proposed protocol significantly reduces the latency as well as the energy consumption compared to the S-MAC protocol specifically for a large transmission power of nodes and low network traffic.

  13. Mac OS X Snow Leopard Server For Dummies

    CERN Document Server

    Rizzo, John

    2009-01-01

    Making Everything Easier!. Mac OS® X Snow Leopard Server for Dummies. Learn to::;. Set up and configure a Mac network with Snow Leopard Server;. Administer, secure, and troubleshoot the network;. Incorporate a Mac subnet into a Windows Active Directory® domain;. Take advantage of Unix® power and security. John Rizzo. Want to set up and administer a network even if you don't have an IT department? Read on!. Like everything Mac, Snow Leopard Server was designed to be easy to set up and use. Still, there are so many options and features that this book will save you heaps of time and effort. It wa

  14. Energy-efficient MAC protocols for Wireless Sensor Networks

    Institute of Scientific and Technical Information of China (English)

    Li De-liang; Peng Fei

    2009-01-01

    Designing energy-efficient Medium Access Control (MAC) protocols has a significant influence on the energy performance of wireless sensor network (WSN). In this paper we present a survey of the recent typical MAC protocols regarding energy efficiency for WSN. According to channel access policies, we classify these protocols into four categories: contention-based, TDMA-based, hybrid, and cross layer protocols, in which the advantages and disadvantages in each class of MAC protocols are discussed. Finally, we point out open research issues that need to carry on to achieve high energy efficiency for the design of MAC protocols in WSN.

  15. Study on intracellular trafficking of Mac-1 by direct visualization

    Institute of Scientific and Technical Information of China (English)

    YAN Ming; MAO Jifang; WEI Yi; ZHONG Jigen; YANG Shengsheng; XU Renbao

    2004-01-01

    Previously, we constructed DNA vectors containing cDNA of Mac-1 subunits (CD11b or CD18b) fused with fluorescence protein (FP). cDNA fragments and the DNA constructs were then transfected into CHO cells (as CHO-Mac-1-FP). The structure and function of Mac-1-FP obtained from the CHO-Mac-1-FP cells are nearly identical to that expressed in wild type leukocytes. In the present study, the intracellular trafficking of Mac-1 was visualized directly by monitoring the fluorescent intensities of YFP-CD18 and PE-conjugated monoclonal antibody against CD11b under a confocal microscope in CHO-Mac-1-FP cells. The results indicate that: (ⅰ) although Mac-1 was not detected in the cell membrane at resting state, it had been translocated and clustered into the cell membrane by 1 h and internalized 2 h after PMA stimulation, at which point the fluorescence intensity began to diminish gradually, probably due to partial degradation of Mac-1. The fluorescence of CD18 and CD11b reappeared on the cell membrane 1 h after re-treatment with PMA, suggesting the recycling of non-degraded Mac-1. (ⅱ) The adhesion rate of CHO-Mac-1-FP to magnetic beads coupled ICAM-1 increased within 4 h after their initial interaction, accompanied by the clustering of Mac-1-FP. After 8 h,the adhesion rate declined and fluorescence also decreased simultaneously. The pattern of change in fluorescence in CHO-Mac-1-FP cells elicited by ICAM-1 beads was similar to that elicited by PMA, suggesting that endocytosis and degradation of Mac-1 occurred after the interaction with ICAM-1. Thus, we conclude that the intracellular trafficking of Mac-1 after activation is associated with membrane translocation, endocytosis, degradation and recycling. These changes are in parallel with the adhesion of CHO-Mac-1-FP cells with ICAM-1, and may be involved in the adhesion and detachment of leukocytes. The detachment of leukocytes may be caused by endocytosis of Mac-1.

  16. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...

  17. Processor arrays with asynchronous TDM optical buses

    Science.gov (United States)

    Li, Y.; Zheng, S. Q.

    1997-04-01

    We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardwared priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performances of our proposed buses are significantly better than the performances of known pipelined synchronous time division multiplexing optical buses. We also propose a class of processor arrays connected by pipelined asynchronous time division multiplexing optical buses. We claim that our proposed processor array not only have better performance, but also have better scalabilities than the existing processor arrays connected by pipelined synchronous time division multiplexing optical buses.

  18. An Energy Efficient Analysis of S-MAC And H-MAC Protocols for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    P.T.Kalaivaani

    2013-04-01

    Full Text Available Wireless Sensor Networks (WSNs is an interesting topic to the researchers because of its variousapplications. The applications are health monitoring and environmental monitoring, Industrial ProcessMonitoring, Target detection, Target tracking, Energy Efficiency, Disaster Management and MilitarySecurity Systems. The wireless medium requires highly optimized medium Access Protocols to avoidinterferences. Limited resources have driven the research towards energy consumption of MACfunctionalities. Two Medium Access Control (MAC protocol performances are analyzed by using the MAClayer frame work for wireless sensor networks. In this paper an energy efficient analysis of S-MAC and HMACprotocols for wireless sensor networks is proposed with spatial correlation concept. Two MACprotocols such as Sensor MAC (S-MAC and Hybrid MAC (H-MAC protocols are proposed to analyze theperformance of Wireless Sensor Network using four different Parameters such as End to End delay, PacketDelivery Ratio, Packet Drop Rate and Energy Consumption. Performance analysis is carried out by usingthe simulation tool NS2.

  19. TreeMAC: Localized TDMA MAC protocol for real-time high-data-rate sensor networks

    Science.gov (United States)

    Song, W.-Z.; Huang, R.; Shirazi, B.; LaHusen, R.

    2009-01-01

    Earlier sensor network MAC protocols focus on energy conservation in low-duty cycle applications, while some recent applications involve real-time high-data-rate signals. This motivates us to design an innovative localized TDMA MAC protocol to achieve high throughput and low congestion in data collection sensor networks, besides energy conservation. TreeMAC divides a time cycle into frames and each frame into slots. A parent node determines the children's frame assignment based on their relative bandwidth demand, and each node calculates its own slot assignment based on its hop-count to the sink. This innovative 2-dimensional frame-slot assignment algorithm has the following nice theory properties. First, given any node, at any time slot, there is at most one active sender in its neighborhood (including itself). Second, the packet scheduling with TreeMAC is bufferless, which therefore minimizes the probability of network congestion. Third, the data throughput to the gateway is at least 1/3 of the optimum assuming reliable links. Our experiments on a 24-node testbed show that TreeMAC protocol significantly improves network throughput, fairness, and energy efficiency compared to TinyOS's default CSMA MAC protocol and a recent TDMA MAC protocol Funneling-MAC. Partial results of this paper were published in Song, Huang, Shirazi and Lahusen [W.-Z. Song, R. Huang, B. Shirazi, and R. Lahusen, TreeMAC: Localized TDMA MAC protocol for high-throughput and fairness in sensor networks, in: The 7th Annual IEEE International Conference on Pervasive Computing and Communications, PerCom, March 2009]. Our new contributions include analyses of the performance of TreeMAC from various aspects. We also present more implementation detail and evaluate TreeMAC from other aspects. ?? 2009 Elsevier B.V.

  20. 42 CFR 405.1122 - What evidence may be submitted to the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false What evidence may be submitted to the MAC. 405.1122... Council Review § 405.1122 What evidence may be submitted to the MAC. (a) Appeal before the MAC on request for review of ALJ's decision. (1) If the MAC is reviewing an ALJ's decision, the MAC limits its review...

  1. 42 CFR 423.2122 - What evidence may be submitted to the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false What evidence may be submitted to the MAC. 423.2122..., MAC review, and Judicial Review § 423.2122 What evidence may be submitted to the MAC. (a) Appeal before the MAC on request for review of ALJ's decision. (1) If the MAC is reviewing an ALJ's decision...

  2. Concept of a Supervector Processor: A Vector Approach to Superscalar Processor, Design and Performance Analysis

    Directory of Open Access Journals (Sweden)

    Deepak Kumar, Ranjan Kumar Behera, K. S. Pandey

    2013-07-01

    Full Text Available To maximize the available performance is always a goal in microprocessor design. In this paper a new technique has been implemented which exploits the advantage of both superscalar and vector processing technique in a proposed processor called Supervector processor. Vector processor operates on array of data called vector and can greatly improve certain task such as numerical simulation and tasks which requires huge number crunching. On other handsuperscalar processor issues multiple instructions per cyclewhich can enhance the throughput. To implement parallelism multiple vector instructions were issued and executed per cycle in superscalar fashion. Case study has been done on various benchmarks to compare the performance of proposedsupervector processor architecture with superscalar and vectorprocessor architecture. Trimaran Framework has been used in order to evaluate the performance of the proposed supervector processor scheme.

  3. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  4. Radiation Tolerant Software Defined Video Processor Project

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  5. Critical review of programmable media processor architectures

    Science.gov (United States)

    Berg, Stefan G.; Sun, Weiyun; Kim, Donglok; Kim, Yongmin

    1998-12-01

    In the past several years, there has been a surge of new programmable mediaprocessors introduced to provide an alternative solution to ASICs and dedicated hardware circuitries in the multimedia PC and embedded consumer electronics markets. These processors attempt to combine the programmability of multimedia-enhanced general purpose processors with the performance and low cost of dedicated hardware. We have reviewed five current multimedia architectures and evaluated their strengths and weaknesses.

  6. First Cluster Algorithm Special Purpose Processor

    Science.gov (United States)

    Talapov, A. L.; Andreichenko, V. B.; Dotsenko S., Vi.; Shchur, L. N.

    We describe the architecture of the special purpose processor built to realize in hardware cluster Wolff algorithm, which is not hampered by a critical slowing down. The processor simulates two-dimensional Ising-like spin systems. With minor changes the same very effective architecture, which can be defined as a Memory Machine, can be used to study phase transitions in a wide range of models in two or three dimensions.

  7. A New Echeloned Poisson Series Processor (EPSP)

    Science.gov (United States)

    Ivanova, Tamara

    2001-07-01

    A specialized Echeloned Poisson Series Processor (EPSP) is proposed. It is a typical software for the implementation of analytical algorithms of Celestial Mechanics. EPSP is designed for manipulating long polynomial-trigonometric series with literal divisors. The coefficients of these echeloned series are the rational or floating-point numbers. The Keplerian processor and analytical generator of special celestial mechanics functions based on the EPSP are also developed.

  8. Evaluating current processors performance and machines stability

    CERN Document Server

    Esposito, R; Tortone, G; Taurino, F M

    2003-01-01

    Accurately estimate performance of currently available processors is becoming a key activity, particularly in HENP environment, where high computing power is crucial. This document describes the methods and programs, opensource or freeware, used to benchmark processors, memory and disk subsystems and network connection architectures. These tools are also useful to stress test new machines, before their acquisition or before their introduction in a production environment, where high uptimes are requested.

  9. SMART AS A CRYPTOGRAPHIC PROCESSOR

    Directory of Open Access Journals (Sweden)

    Saroja Kanchi

    2016-05-01

    Full Text Available SMaRT is a 16-bit 2.5-address RISC-type single-cycle processor, which was recently designed and successfully mapped into a FPGA chip in our ECE department. In this paper, we use SMaRT to run the well-known encryption algorithm, Data Encryption Standard. For information security purposes, encryption is a must in today’s sophisticated and ever-increasing computer communications such as ATM machines and SIM cards. For comparison and evaluation purposes, we also map the same algorithm on the HC12, a same-size but CISC-type off-the-shelf microcontroller, Our results show that compared to HC12, SMaRT code is only 14% longer in terms of the static number of instructions but about 10 times faster in terms of the number of clock cycles, and 7% smaller in terms of code size. Our results also show that 2.5- address instructions, a SMaRT selling point, amount to 45% of the whole R-type instructions resulting in significant improvement in static number of instructions hence code size as well as performance. Additionally, we see that the SMaRT short-branch range is sufficiently wide in 90% of cases in the SMaRT code. Our results also reveal that the SMaRT novel concept of locality of reference in using the MSBs of the registers in non-subroutine branch instructions stays valid with a remarkable hit rate of 95%!

  10. Influence of prior determination of baseline minimum alveolar concentration (MAC) of isoflurane on the effect of ketamine on MAC in dogs.

    Science.gov (United States)

    Gianotti, Giacomo; Valverde, Alexander; Johnson, Ron; Sinclair, Melissa; Gibson, Thomas; Dyson, Doris H

    2014-07-01

    The objective of this study was to determine if prior measurement of the minimum alveolar concentration (MAC) of isoflurane influences the effect of ketamine on the MAC of isoflurane in dogs. Eight mixed-breed dogs were studied on 2 occasions. Anesthesia was induced and maintained using isoflurane. In group 1 the effect of ketamine on isoflurane MAC was determined after initially finding the baseline isoflurane MAC. In group 2, the effect of ketamine on isoflurane MAC was determined without previous measure of the baseline isoflurane MAC. In both groups, MAC was determined again 30 min after stopping the CRI of ketamine. Plasma ketamine concentrations were measured during MAC determinations. In group 1, baseline MAC (mean ± SD: 1.18 ± 0.14%) was decreased by ketamine (0.88 ± 0.14%; P MAC after stopping ketamine was similar (1.09 ± 0.16%) to baseline MAC and higher than with ketamine (P MAC with ketamine (0.79 ± 0.11%) was also increased after stopping ketamine (1.10 ± 0.17%; P MAC values with ketamine were different between groups (P MAC determination. The MAC of isoflurane during the CRI of ketamine yielded different results when methods of same day (group-1) versus separate days (group-2) are used, despite similar plasma ketamine concentrations with both methods. However, because the magnitude of this difference was less than 10%, either method of determining MAC is deemed acceptable for research purposes.

  11. On the orthogonality of the MacDonald s functions

    Energy Technology Data Exchange (ETDEWEB)

    Passian, Ali [ORNL; Simpson, Henry [University of Tennessee, Knoxville (UTK); Koucheckian, Sherwin [University of South Florida, Tampa; Yakubovich, Semyon [University of Porto, Portugal

    2009-01-01

    A proof of an orthogonality relation for the MacDonald's functions with identical arguments but unequal complex lower indices is presented. The orthogonality is derived first via a heuristic approach based on the Mehler-Fock integral transform of the MacDonald's functions, and then proved rigorously using a polynomial approximation procedure.

  12. SuperMacLang: Development of an Authoring System.

    Science.gov (United States)

    Frommer, Judith; Foelsche, Otmar K. E.

    1999-01-01

    Describes the development of "SuperMacLang, the 1990s version of the MacLang authoring system. An analysis of various features of the program explains the ways in which certain aspects of collaboration and funding affected developer and programming decisions. (Author/VWL)

  13. Steven MacCall: Winner of LJ's 2010 Teaching Award

    Science.gov (United States)

    Berry, John N., III

    2010-01-01

    This article profiles Steven L. MacCall, winner of "Library Journal's" 2010 Teaching Award. An associate professor at the School of Library and Information Studies (SLIS) at the University of Alabama, Tuscaloosa, MacCall was nominated by Kathie Popadin, known as "Kpop" to the members of her cohort in the online MLIS program at SLIS. Sixteen of…

  14. MAC of xenon and halothane in rhesus monkeys.

    Science.gov (United States)

    Whitehurst, S L; Nemoto, E M; Yao, L; Yonas, H

    1994-10-01

    Local cerebral blood flow (LCBF) maps produced by 33% xenon-enhanced computed tomographic scanning (Xe/CT LCBF) are useful in the clinical diagnosis and management of patients with cerebrovascular disorders. However, observations in humans that 25-35% xenon (Xe) inhalation increases cerebral blood flow (CBF) have raised concerns that Xe/CT LCBF measurements may be inaccurate and that Xe inhalation may be hazardous in patients with decreased intracranial compliance. In contrast, 33% Xe does not increase CBF in rhesus monkeys. To determine whether this interspecies difference in the effect of Xe on CBF correlates with an interspecies difference in the anesthetic potency of Xe, we measured the minimum alveolar concentration (MAC) of Xe preventing movement to a tail-clamp stimulus in rhesus monkeys. Using a standard protocol for the determination of MAC in animals, we first measured the MAC of halothane (n = 5), and then used a combination of halothane and Xe to measure the MAC of Xe (n = 7). The halothane MAC was 0.99 +/- 0.12% (M +/- SD), and the Xe MAC was 98 +/- 15%. These results suggest that the MAC of Xe in rhesus monkeys is higher than the reported human Xe MAC value of 71%. Thus the absence of an effect of 33% Xe on CBF in the rhesus monkey may be related to its lower anesthetic potency.

  15. Intel-Based Mac Computers Improve Teaching and Learning

    Science.gov (United States)

    Technology & Learning, 2007

    2007-01-01

    Today, Mac computers offer schools an easy and powerful way to engage students in learning, foster 21st century skills and leverage existing software assets. Innovative software and hardware built into the Mac allows students to demonstrate their individual strengths--empowering them to be creators of content, rather than just consumers. Judging…

  16. Intel-Based Mac Computers Improve Teaching and Learning

    Science.gov (United States)

    Technology & Learning, 2007

    2007-01-01

    Today, Mac computers offer schools an easy and powerful way to engage students in learning, foster 21st century skills and leverage existing software assets. Innovative software and hardware built into the Mac allows students to demonstrate their individual strengths--empowering them to be creators of content, rather than just consumers. Judging…

  17. Multi-channel MAC Protocol in Cognitive Radio Networks

    Directory of Open Access Journals (Sweden)

    Yongli Sun

    2013-11-01

    Full Text Available Since cognitive wireless network (CRN has the characteristic of secondary use, it can enable the device to dynamically access available spectrum without interference to primary users (PUs, which can effectively alleviate contradiction between the lack of spectrum resources and the growing demand for wireless access. However, Medium Access Control (MAC protocol as CRN core components, can achieve competition access of the licensed spectrum and coordination control, which will maximize spectrum utilization efficiency and network throughput. The contribution of this survey is threefold. First, we analyze the characteristics of the existed multi- channel MAC protocol in CRN; Second, according to the different ways of spectrum access in CRNs, the multi-channel MAC protocols are classified into time-slotted based MAC protocol, control channel based MAC protocol and hybrid MAC protocol, and the paper emphatically analyzed the advantages and disadvantages of these multi-channel MAC protocols; Finally, the paper explores the difficulties and the challenges of multi-channel MAC protocols design in cognitive wireless network.

  18. Steven MacCall: Winner of LJ's 2010 Teaching Award

    Science.gov (United States)

    Berry, John N., III

    2010-01-01

    This article profiles Steven L. MacCall, winner of "Library Journal's" 2010 Teaching Award. An associate professor at the School of Library and Information Studies (SLIS) at the University of Alabama, Tuscaloosa, MacCall was nominated by Kathie Popadin, known as "Kpop" to the members of her cohort in the online MLIS program at SLIS. Sixteen of…

  19. A Sensing Error Aware MAC Protocol for Cognitive Radio Networks

    CERN Document Server

    Hu, Donglin

    2011-01-01

    Cognitive radios (CR) are intelligent radio devices that can sense the radio environment and adapt to changes in the radio environment. Spectrum sensing and spectrum access are the two key CR functions. In this paper, we present a spectrum sensing error aware MAC protocol for a CR network collocated with multiple primary networks. We explicitly consider both types of sensing errors in the CR MAC design, since such errors are inevitable for practical spectrum sensors and more important, such errors could have significant impact on the performance of the CR MAC protocol. Two spectrum sensing polices are presented, with which secondary users collaboratively sense the licensed channels. The sensing policies are then incorporated into p-Persistent CSMA to coordinate opportunistic spectrum access for CR network users. We present an analysis of the interference and throughput performance of the proposed CR MAC, and find the analysis highly accurate in our simulation studies. The proposed sensing error aware CR MAC p...

  20. McCay ("Mac") Vernon (1928-2013).

    Science.gov (United States)

    Sherman, William A

    2014-09-01

    McCay ("Mac") Vernon, the founding and preeminent psychologist in the field of deafness. Mac was born at Walter Reed Hospital in Washington, DC, into a military family on October 14, 1928 and died on August 28, 2013, at the age of 84. Prior to Mac, research and clinical direction in the field were sparse. Mac became the icon for psychological services for deaf people, and his work extended into the education of deaf children, forensic and ethical practices with the deaf, and public understanding of deafness as a disability and of deaf persons as a psychosocial minority group. Mac will also be remembered for his sharp intellect, good humor, compassion, and advocacy for those who are misunderstood.

  1. Alasdair MacIntyre, joven lector de Freud

    Directory of Open Access Journals (Sweden)

    Ramis Barceló, Rafael

    2010-06-01

    Full Text Available This article tries to show the reading of Freud that MacIntyre made from 1955 to 1970. For this purpose, it summarizes the ideas of MacIntyre in the intellectual context, mainly the use of philosophical ideas of Freud against the Enlightenment project. MacIntyre criticises Marxist interpreters and the mixing between Marx and Freud. MacIntyre uses the philosophical ideas of Freud for answering two problems on determinism: the links between determinism and reasons for action and determinism and Marxism. The main conclusion is that MacIntyre used Freud in his own advantage: as an ally in the criticism of the Enlightenment.

    Este artículo trata de mostrar la lectura que MacIntyre hizo de Freud desde 1955 hasta 1970. Con este fin, se resumen las ideas de MacIntyre en el contexto intelectual, principalmente el uso de las ideas filosóficas de Freud contra el proyecto de la Ilustración. MacIntyre critica a los intérpretes de Marx y a la mezcla entre Marx y Freud. MacIntyre usa las ideas filosóficas de Freud para contestar dos problemas sobre el determinismo: los vínculos entre el determinismo y las razones para la acción y el determinismo y el marxismo. La conclusión principal es que MacIntyre usó a Freud en su propio beneficio: como un aliado en la crítica de la Ilustración.

  2. TreeMAC: Localized TDMA MAC protocol for real-time high-data-rate sensor networks

    Science.gov (United States)

    Song, W.-Z.; Huang, R.; Shirazi, B.; Husent, R.L.

    2009-01-01

    Earlier sensor network MAC protocols focus on energy conservation in low-duty cycle applications, while some recent applications involve real-time high-data-rate signals. This motivates us to design an innovative localized TDMA MAC protocol to achieve high throughput and low congestion in data collection sensor networks, besides energy conservation. TreeMAC divides a time cycle into frames and frame into slots. Parent determines children's frame assigmnent based on their relative bandwidth demand, and each node calculates its own slot assignment based on its hop-count to the sink. This innovative 2-dimensional frame-slot assignment algorithm has the following nice theory properties. Firstly, given any node, at any time slot, there is at most one active sender in its neighborhood (includ ing itself). Secondly, the packet scheduling with TreelMAC is bufferless, which therefore minimizes the probability of network congestion. Thirdly, the data throughput to gateway is at least 1/3 of the optimum assuming reliable links. Our experiments on a 24 node test bed demonstrate that TreeMAC protocol significantly improves network throughput and energy efficiency, by comparing to the TinyOS's default CSMA MAC protocol and a recent TDMA MAC protocol Funneling-MAC[8]. ?? 2009 IEEE.

  3. TR-MAC: an energy-efficient MAC protocol exploiting transmitted reference modulation for wireless sensor networks

    NARCIS (Netherlands)

    Morshed, S.; Heijenk, Geert

    2014-01-01

    The medium access control (MAC) protocol determines the energy consumption of a wireless sensor node by specifying the listening, transmitting or sleeping time. Therefore MAC protocols play an important role in minimizing the overall energy consumption in a typical wireless sensor network (WSN).

  4. TR-MAC: an energy-efficient MAC protocol exploiting transmitted reference modulation for wireless sensor networks

    NARCIS (Netherlands)

    Morshed, Sarwar; Heijenk, Geert

    2014-01-01

    The medium access control (MAC) protocol determines the energy consumption of a wireless sensor node by specifying the listening, transmitting or sleeping time. Therefore MAC protocols play an important role in minimizing the overall energy consumption in a typical wireless sensor network (WSN). Usi

  5. IDSP- INTERACTIVE DIGITAL SIGNAL PROCESSOR

    Science.gov (United States)

    Mish, W. H.

    1994-01-01

    The Interactive Digital Signal Processor, IDSP, consists of a set of time series analysis "operators" based on the various algorithms commonly used for digital signal analysis work. The processing of a digital time series to extract information is usually achieved by the application of a number of fairly standard operations. However, it is often desirable to "experiment" with various operations and combinations of operations to explore their effect on the results. IDSP is designed to provide an interactive and easy-to-use system for this type of digital time series analysis. The IDSP operators can be applied in any sensible order (even recursively), and can be applied to single time series or to simultaneous time series. IDSP is being used extensively to process data obtained from scientific instruments onboard spacecraft. It is also an excellent teaching tool for demonstrating the application of time series operators to artificially-generated signals. IDSP currently includes over 43 standard operators. Processing operators provide for Fourier transformation operations, design and application of digital filters, and Eigenvalue analysis. Additional support operators provide for data editing, display of information, graphical output, and batch operation. User-developed operators can be easily interfaced with the system to provide for expansion and experimentation. Each operator application generates one or more output files from an input file. The processing of a file can involve many operators in a complex application. IDSP maintains historical information as an integral part of each file so that the user can display the operator history of the file at any time during an interactive analysis. IDSP is written in VAX FORTRAN 77 for interactive or batch execution and has been implemented on a DEC VAX-11/780 operating under VMS. The IDSP system generates graphics output for a variety of graphics systems. The program requires the use of Versaplot and Template plotting

  6. The minimum alveolar concentration (MAC) of isoflurane in preterm neonates.

    Science.gov (United States)

    LeDez, K M; Lerman, J

    1987-09-01

    Studies in fetal lambs suggested that the minimum alveolar concentration (MAC) in preterm neonates may be less than that in full-term neonates and older infants. To determine the MAC of isoflurane in preterm neonates, 20 patients less than 32 weeks gestation at birth and 16 patients 32-37 weeks gestation at birth, all less than 1 month post-natal age, were studied. Following tracheal intubation, the neonates were anesthetized with a predetermined end-tidal concentration of isoflurane in oxygen and air. The move-no move responses to skin incision were recorded, and MAC was determined using the "up-and-down" technique. Heart rate and systolic arterial pressure were recorded awake, before skin incision, and after skin incision. MAC (mean +/- SD) of isoflurane in preterm neonates less than 32 weeks gestation was 1.28 +/- 0.17%, and MAC in neonates 32-37 weeks gestation was 1.41 +/- 0.18% (P less than 0.05). Although heart rate did not decrease significantly in either group during the study, systolic arterial pressure decreased between 20 and 30% below awake values both before and after skin incision in both age groups (P less than 0.01). We conclude that the MAC of isoflurane in preterm neonates less than 32 weeks gestation is significantly less than that in preterm neonates 32-37 weeks gestation, and that systolic arterial pressure decreases to a similar extent at approximately 1 MAC isoflurane in both age groups.

  7. Increased NMDA receptor inhibition at an increased Sevoflurane MAC

    Directory of Open Access Journals (Sweden)

    Brosnan Robert J

    2012-06-01

    Full Text Available Abstract Background Sevoflurane potently enhances glycine receptor currents and more modestly decreases NMDA receptor currents, each of which may contribute to immobility. This modest NMDA receptor antagonism by sevoflurane at a minimum alveolar concentration (MAC could be reciprocally related to large potentiation of other inhibitory ion channels. If so, then reduced glycine receptor potency should increase NMDA receptor antagonism by sevoflurane at MAC. Methods Indwelling lumbar subarachnoid catheters were surgically placed in 14 anesthetized rats. Rats were anesthetized with sevoflurane the next day, and a pre-infusion sevoflurane MAC was measured in duplicate using a tail clamp method. Artificial CSF (aCSF containing either 0 or 4 mg/mL strychnine was then infused intrathecally at 4 μL/min, and the post-infusion baseline sevoflurane MAC was measured. Finally, aCSF containing strychnine (either 0 or 4 mg/mL plus 0.4 mg/mL dizocilpine (MK-801 was administered intrathecally at 4 μL/min, and the post-dizocilpine sevoflurane MAC was measured. Results Pre-infusion sevoflurane MAC was 2.26%. Intrathecal aCSF alone did not affect MAC, but intrathecal strychnine significantly increased sevoflurane requirement. Addition of dizocilpine significantly decreased MAC in all rats, but this decrease was two times larger in rats without intrathecal strychnine compared to rats with intrathecal strychnine, a statistically significant (P  Conclusions Glycine receptor antagonism increases NMDA receptor antagonism by sevoflurane at MAC. The magnitude of anesthetic effects on a given ion channel may therefore depend on the magnitude of its effects on other receptors that modulate neuronal excitability.

  8. Increased NMDA receptor inhibition at an increased Sevoflurane MAC.

    Science.gov (United States)

    Brosnan, Robert J; Thiesen, Roberto

    2012-06-06

    Sevoflurane potently enhances glycine receptor currents and more modestly decreases NMDA receptor currents, each of which may contribute to immobility. This modest NMDA receptor antagonism by sevoflurane at a minimum alveolar concentration (MAC) could be reciprocally related to large potentiation of other inhibitory ion channels. If so, then reduced glycine receptor potency should increase NMDA receptor antagonism by sevoflurane at MAC. Indwelling lumbar subarachnoid catheters were surgically placed in 14 anesthetized rats. Rats were anesthetized with sevoflurane the next day, and a pre-infusion sevoflurane MAC was measured in duplicate using a tail clamp method. Artificial CSF (aCSF) containing either 0 or 4 mg/mL strychnine was then infused intrathecally at 4 μL/min, and the post-infusion baseline sevoflurane MAC was measured. Finally, aCSF containing strychnine (either 0 or 4 mg/mL) plus 0.4 mg/mL dizocilpine (MK-801) was administered intrathecally at 4 μL/min, and the post-dizocilpine sevoflurane MAC was measured. Pre-infusion sevoflurane MAC was 2.26%. Intrathecal aCSF alone did not affect MAC, but intrathecal strychnine significantly increased sevoflurane requirement. Addition of dizocilpine significantly decreased MAC in all rats, but this decrease was two times larger in rats without intrathecal strychnine compared to rats with intrathecal strychnine, a statistically significant (P MAC. The magnitude of anesthetic effects on a given ion channel may therefore depend on the magnitude of its effects on other receptors that modulate neuronal excitability.

  9. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-01-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  10. Making CSB+-Tree Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  11. Dynamic Load Balancing using Graphics Processors

    Directory of Open Access Journals (Sweden)

    R Mohan

    2014-04-01

    Full Text Available To get maximum performance on the many-core graphics processors, it is important to have an even balance of the workload so that all processing units contribute equally to the task at hand. This can be hard to achieve when the cost of a task is not known beforehand and when new sub-tasks are created dynamically during execution. Both the dynamic load balancing methods using Static task assignment and work stealing using deques are compared to see which one is more suited to the highly parallel world of graphics processors. They have been evaluated on the task of simulating a computer move against the human move, in the famous four in a row game. The experiments showed that synchronization can be very expensive, and those new methods which use graphics processor features wisely might be required.

  12. Intrusion Detection Architecture Utilizing Graphics Processors

    Directory of Open Access Journals (Sweden)

    Branislav Madoš

    2012-12-01

    Full Text Available With the thriving technology and the great increase in the usage of computer networks, the risk of having these network to be under attacks have been increased. Number of techniques have been created and designed to help in detecting and/or preventing such attacks. One common technique is the use of Intrusion Detection Systems (IDS. Today, number of open sources and commercial IDS are available to match enterprises requirements. However, the performance of these systems is still the main concern. This paper examines perceptions of intrusion detection architecture implementation, resulting from the use of graphics processor. It discusses recent research activities, developments and problems of operating systems security. Some exploratory evidence is presented that shows capabilities of using graphical processors and intrusion detection systems. The focus is on how knowledge experienced throughout the graphics processor inclusion has played out in the design of intrusion detection architecture that is seen as an opportunity to strengthen research expertise.

  13. ETHERNET PACKET PROCESSOR FOR SOC APPLICATION

    Directory of Open Access Journals (Sweden)

    Raja Jitendra Nayaka

    2012-07-01

    Full Text Available As the demand for Internet expands significantly in numbers of users, servers, IP addresses, switches and routers, the IP based network architecture must evolve and change. The design of domain specific processors that require high performance, low power and high degree of programmability is the bottleneck in many processor based applications. This paper describes the design of ethernet packet processor for system-on-chip (SoC which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance. Our design has been configured for use with multiple projects ttargeted to a commercial configurable logic device the system is designed to support 10/100/1000 links with a speed advantage. VHDL has been used to implement and simulated the required functions in FPGA.

  14. Programmable DNA-mediated multitasking processor

    CERN Document Server

    Shu, Jian-Jun; Yong, Kian-Yan; Shao, Fangwei; Lee, Kee Jin

    2015-01-01

    Because of DNA appealing features as perfect material, including minuscule size, defined structural repeat and rigidity, programmable DNA-mediated processing is a promising computing paradigm, which employs DNAs as information storing and processing substrates to tackle the computational problems. The massive parallelism of DNA hybridization exhibits transcendent potential to improve multitasking capabilities and yield a tremendous speed-up over the conventional electronic processors with stepwise signal cascade. As an example of multitasking capability, we present an in vitro programmable DNA-mediated optimal route planning processor as a functional unit embedded in contemporary navigation systems. The novel programmable DNA-mediated processor has several advantages over the existing silicon-mediated methods, such as conducting massive data storage and simultaneous processing via much fewer materials than conventional silicon devices.

  15. SWIFT Privacy: Data Processor Becomes Data Controller

    Directory of Open Access Journals (Sweden)

    Edwin Jacobs

    2007-04-01

    Full Text Available Last month, SWIFT emphasised the urgent need for a solution to compliance with US Treasury subpoenas that provides legal certainty for the financial industry as well as for SWIFT. SWIFT will continue its activities to adhere to the Safe Harbor framework of the European data privacy legislation. Safe Harbor is a framework negotiated by the EU and US in 2000 to provide a way for companies in Europe, with operations in the US, to conform to EU data privacy regulations. This seems to conclude a complex privacy case, widely covered by the US and European media. A fundamental question in this case was who is a data controller and who is a mere data processor. Both the Belgian and the European privacy authorities considered SWIFT, jointly with the banks, as a data controller whereas SWIFT had considered itself as a mere data processor that processed financial data for banks. The difference between controller and processor has far reaching consequences.

  16. Multichannel MAC Layer In Mobile Ad—Hoc Network

    Science.gov (United States)

    Logesh, K.; Rao, Samba Siva

    2010-11-01

    This paper we presented the design objectives and technical challenges in Multichannel MAC protocols in Mobile Ad-hoc Network. In IEEE 802.11 a/b/g standards allow use of multiple channels, only a single channel is popularly used, due to the lack of efficient protocols that enable use of Multiple Channels. Even though complex environments in ad hoc networks require a combined control of physical (PHY) and medium access control (MAC) layers resources in order to optimize performance. And also we discuss the characteristics of cross-layer frame and give a multichannel MAC approach.

  17. MacRuby Ruby and Cocoa on OS X

    CERN Document Server

    Aimonetti, Matt

    2011-01-01

    Want to build native Mac OS X applications with a sleek, developer-friendly alternative to Objective-C? MacRuby is an ideal choice. This in-depth guide shows you how Apple's implementation of Ruby gives you access to all the features available to Objective-C programmers. You'll get clear, detailed explanations of MacRuby, including quick programming techniques such as prototyping. Perfect for programmers at any level, this book is packed with code samples and complete project examples. If you use Ruby, you can tap your skills to take advantage of Interface Builder, Cocoa libraries, the Objec

  18. Handling Deafness Problem of Scheduled Multi-Channel Polling MACs

    Science.gov (United States)

    Jiang, Fulong; Liu, Hao; Shi, Longxing

    Combining scheduled channel polling with channel diversity is a promising way for a MAC protocol to achieve high energy efficiency and performance under both light and heavy traffic conditions. However, the deafness problem may cancel out the benefit of channel diversity. In this paper, we first investigate the deafness problem of scheduled multi-channel polling MACs with experiments. Then we propose and evaluate two schemes to handle the deafness problem. Our experiment shows that deafness is a significant reason for performance degradation in scheduled multi-channel polling MACs. A proper scheme should be chosen depending on the traffic pattern and the design objective.

  19. Cooperative energy harvesting-adaptive MAC protocol for WBANs.

    Science.gov (United States)

    Esteves, Volker; Antonopoulos, Angelos; Kartsakli, Elli; Puig-Vidal, Manel; Miribel-Català, Pere; Verikoukis, Christos

    2015-05-28

    In this paper, we introduce a cooperative medium access control (MAC) protocol, named cooperative energy harvesting (CEH)-MAC, that adapts its operation to the energy harvesting (EH) conditions in wireless body area networks (WBANs). In particular, the proposed protocol exploits the EH information in order to set an idle time that allows the relay nodes to charge their batteries and complete the cooperation phase successfully. Extensive simulations have shown that CEH-MAC significantly improves the network performance in terms of throughput, delay and energy efficiency compared to the cooperative operation of the baseline IEEE 802.15.6 standard.

  20. A Hybrid MacCormack-type Scheme for Computational Aeroacoustics

    Science.gov (United States)

    Yazdani, Soroush

    A new type of MacCormack scheme, using a modified Low Dissipation and Dispersion Runge-Kutta time marching method, is presented. This scheme is using two stages in every step which implements biased spatial differencing stencils and for the remaining stages uses non-dissipative central differencing stencils. Because of using the MacCormack-type scheme in this method, the new scheme carries an inherent artificial dissipation which uses the ease of implementing boundary condition specifications of a two-stage MacCormack scheme.

  1. iMac G3 Blueberry 350MHz

    CERN Multimedia

    2000-01-01

    The iMac G3 is an all-in-one personal computer, encompassing both the monitor and the computer in one package. It allowed to revitalize the Apple brand that was in decline and close to financial ruin. Originally released in striking bondi blue and later a range of other translucent plastic envelopes in bright colors. The iMac comes with a keyboard and mouse matching the color of the case. The iMac G3 was sold from 1998 to 2003 and has been updated many times.

  2. MacWillia ms Identities of Linear Codes Over Ring R+vR+v2R%环R+vR+v2 R上线性码的Mac Wi lli ams恒等式

    Institute of Scientific and Technical Information of China (English)

    朱士信; 黄磊

    2016-01-01

    By constructing gray map,linear codes over ring R+vR+v2 R are studied.The Lee weight and several clas-ses of weight enumerators about linear codes over ring R+vR+v2 R are defined,the MacWilliams identities of weight distri-butions between the linear codes and their dual codes over ring R+vR+v2 R are given.According to these identities,we can get the weight distributions of dual codes directly without obtaining the dual codes of linear codes over ring R+vR+v2 R.%通过构造Gray映射,对环R+vR+v2 R上线性码进行了研究。定义了环R+vR+v2 R上线性码的Lee重量及其几类重量计数器,给出了环R+vR+v2 R上线性码及其对偶码之间的各种重量分布的MacWilliams恒等式。利用这些恒等式,不用求出环R+vR+v2 R上线性码的对偶码便可得到对偶码的各种重量分布。

  3. Efficient SIMD optimization for media processors

    Institute of Scientific and Technical Information of China (English)

    Jian-peng ZHOU; Ce SHI

    2008-01-01

    Single instruction multiple data (SIMD) instructions are often implemented in modem media processors. Although SIMD instructions are useful in multimedia applications, most compilers do not have good support for SIMD instructions. This paper focuses on SIMD instructions generation for media processors. We present an efficient code optimization approach that is integrated into a retargetable C compiler. SIMD instructions are generated by finding and combining the same operations in programs. Experimental results for the UltraSPARC VIS instruction set show that a speedup factor up to 2.639 is obtained.

  4. 8 Bit RISC Processor Using Verilog HDL

    Directory of Open Access Journals (Sweden)

    Ramandeep Kaur

    2014-03-01

    Full Text Available RISC is a design philosophy to reduce the complexity of instruction set that in turn reduces the amount of space, cycle time, cost and other parameters taken into account during the implementation of the design. The advent of FPGA has enabled the complex logical systems to be implemented on FPGA. The intent of this paper is to design and implement 8 bit RISC processor using FPGA Spartan 3E tool. This processor design depends upon design specification, analysis and simulation. It takes into consideration very simple instruction set. The momentous components include Control unit, ALU, shift registers and accumulator register.

  5. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.......g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability...... of the different models of communication for real-time systems....

  6. SPROC: A multiple-processor DSP IC

    Science.gov (United States)

    Davis, R.

    1991-01-01

    A large, single-chip, multiple-processor, digital signal processing (DSP) integrated circuit (IC) fabricated in HP-Cmos34 is presented. The innovative architecture is best suited for analog and real-time systems characterized by both parallel signal data flows and concurrent logic processing. The IC is supported by a powerful development system that transforms graphical signal flow graphs into production-ready systems in minutes. Automatic compiler partitioning of tasks among four on-chip processors gives the IC the signal processing power of several conventional DSP chips.

  7. Models of Communication for Multicore Processors

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Sørensen, Rasmus Bo; Sparsø, Jens

    2015-01-01

    To efficiently use multicore processors we need to ensure that almost all data communication stays on chip, i.e., the bits moved between tasks executing on different processor cores do not leave the chip. Different forms of on-chip communication are supported by different hardware mechanism, e.......g., shared caches with cache coherency protocols, core-to-core networks-on-chip, and shared scratchpad memories. In this paper we explore the different hardware mechanism for on-chip communication and how they support or favor different models of communication. Furthermore, we discuss the usability...... of the different models of communication for real-time systems....

  8. Multi-core processors - An overview

    CERN Document Server

    Venu, Balaji

    2011-01-01

    Microprocessors have revolutionized the world we live in and continuous efforts are being made to manufacture not only faster chips but also smarter ones. A number of techniques such as data level parallelism, instruction level parallelism and hyper threading (Intel's HT) already exists which have dramatically improved the performance of microprocessor cores. This paper briefs on evolution of multi-core processors followed by introducing the technology and its advantages in today's world. The paper concludes by detailing on the challenges currently faced by multi-core processors and how the industry is trying to address these issues.

  9. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  10. PAD-MAC: primary user activity-aware distributed MAC for multi-channel cognitive radio networks.

    Science.gov (United States)

    Ali, Amjad; Piran, Md Jalil; Kim, Hansoo; Yun, Jihyeok; Suh, Doug Young

    2015-03-30

    Cognitive radio (CR) has emerged as a promising technology to solve problems related to spectrum scarcity and provides a ubiquitous wireless access environment. CR-enabled secondary users (SUs) exploit spectrum white spaces opportunistically and immediately vacate the acquired licensed channels as primary users (PUs) arrive. Accessing the licensed channels without the prior knowledge of PU traffic patterns causes severe throughput degradation due to excessive channel switching and PU-to-SU collisions. Therefore, it is significantly important to design a PU activity-aware medium access control (MAC) protocol for cognitive radio networks (CRNs). In this paper, we first propose a licensed channel usage pattern identification scheme, based on a two-state Markov model, and then estimate the future idle slots using previous observations of the channels. Furthermore, based on these past observations, we compute the rank of each available licensed channel that gives SU transmission success assessment during the estimated idle slot. Secondly, we propose a PU activity-aware distributed MAC (PAD-MAC) protocol for heterogeneous multi-channel CRNs that selects the best channel for each SU to enhance its throughput. PAD-MAC controls SU activities by allowing them to exploit the licensed channels only for the duration of estimated idle slots and enables predictive and fast channel switching. To evaluate the performance of the proposed PAD-MAC, we compare it with the distributed QoS-aware MAC (QC-MAC) and listen-before-talk MAC schemes. Extensive numerical results show the significant improvements of the PAD-MAC in terms of the SU throughput, SU channel switching rate and PU-to-SU collision rate.

  11. Infecting Windows, Linux & Mac in one go

    CERN Multimedia

    Computer Security Team

    2012-01-01

    Still love bashing on Windows as you believe it is an insecure operating system? Hold on a second! Just recently, a vulnerability has been published for Java 7.   It affects Windows/Linux PCs and Macs, Internet Explorer, Safari and Firefox. In fact, it affects all computers that have enabled the Java 7 plug-in in their browser (Java 6 and earlier is not affected). Once you visit a malicious website (and there are plenty already out in the wild), your computer is infected… That's "Game Over" for you.      And this is not the first time. For a while now, attackers have not been targeting the operating system itself, but rather aiming at vulnerabilities inherent in e.g. your Acrobat Reader, Adobe Flash or Java programmes. All these are standard plug-ins added into your favourite web browser which make your web-surfing comfortable (or impossible when you un-install them). A single compromised web-site, however, is sufficient to prob...

  12. Inter Processor Communication for Fault Diagnosis in Multiprocessor Systems

    Directory of Open Access Journals (Sweden)

    C. D. Malleswar

    1994-04-01

    Full Text Available In the preseJlt paper a simple technique is proposed for fault diagnosis for multiprocessor and multiple system environments, wherein all microprocessors in the system are used in part to check the health of their neighbouring processors. It involves building simple fail-safe serial communication links between processors. Processors communicate with each other over these links and each processor is made to go through certain sequences of actions intended for diagnosis, under the observation of another processor .With limited overheads, fault detection can be done by this method. Also outlined are some of the popular techniques used for health check of processor-based systems.

  13. Prior determination of baseline minimum alveolar concentration (MAC) of isoflurane does not influence the effect of ketamine on MAC in rabbits.

    Science.gov (United States)

    Gianotti, Giacomo; Valverde, Alexander; Sinclair, Melissa; Dyson, Doris H; Gibson, Thomas; Johnson, Ron

    2012-10-01

    The objective of this study was to compare the effect on the minimum alveolar concentration (MAC) of isoflurane when ketamine was administered either after or without prior determination of the baseline MAC of isoflurane in rabbits. Using a prospective randomized crossover study, 8 adult, female New Zealand rabbits were allocated to 2 treatment groups. Anesthesia was induced and maintained with isoflurane. Group 1 (same-day determination) had the MAC-sparing effect of ketamine [1 mg/kg bodyweight (BW) bolus followed by a constant rate infusion (CRI) of 40 μg/kg BW per min, given by intravenous (IV)], which was determined after the baseline MAC of isoflurane was determined beforehand. A third MAC determination was started 30 min after stopping the CRI. Group 2 (separate-day determination) had the MAC-sparing effect of ketamine determined without previous determination of the baseline MAC of isoflurane. A second MAC determination was started 30 min after stopping the CRI. In group 1, the MAC of isoflurane (2.15 ± 0.09%) was significantly decreased by ketamine (1.63 ± 0.07%). After stopping the CRI, the MAC was significantly less (2.04 ± 0.11%) than the baseline MAC of isoflurane and significantly greater than the MAC during the CRI. In group 2, ketamine decreased isoflurane MAC (1.53 ± 0.22%) and the MAC increased significantly (1.94 ± 0.25%) after stopping the CRI. Minimum alveolar concentration (MAC) values did not differ significantly between the groups either during ketamine administration or after stopping ketamine. Under the study conditions, prior determination of the baseline isoflurane MAC did not alter the effect of ketamine on MAC. Both methods of determining MAC seemed to be valid for research purposes.

  14. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    Science.gov (United States)

    Zacharias, Sven; Newe, Thomas

    2011-08-01

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  15. After MacIntyre : Kaasaegsest vooruseetikast / Meego Remmel

    Index Scriptorium Estoniae

    Remmel, Meego

    2006-01-01

    Alasdair MacIntyre panus 20. sajandi eetikasse. Tema käsitlus vooruseetikast ja vooruseetilisest perspektiivist, mida on võimalik näha komplekselt, vaadeldes voorust, praktikat, narratiivi ja traditsiooni mõisteid

  16. After MacIntyre : Kaasaegsest vooruseetikast / Meego Remmel

    Index Scriptorium Estoniae

    Remmel, Meego

    2006-01-01

    Alasdair MacIntyre panus 20. sajandi eetikasse. Tema käsitlus vooruseetikast ja vooruseetilisest perspektiivist, mida on võimalik näha komplekselt, vaadeldes voorust, praktikat, narratiivi ja traditsiooni mõisteid

  17. Beamforming in Ad Hoc Networks: MAC Design and Performance Modeling

    National Research Council Canada - National Science Library

    Fakih, Khalil; Diouris, Jean-Francois; Andrieux, Guillaume

    2009-01-01

    .... Our proposition performs jointly channel estimation and radio resource sharing. We validate the fruitfulness of the proposed MAC and we evaluate the effects of the channel estimation on the network performance...

  18. Aeronautical Mobile Airport Communications System (AeroMACS)

    Science.gov (United States)

    Budinger, James M.; Hall, Edward

    2011-01-01

    To help increase the capacity and efficiency of the nation s airports, a secure wideband wireless communications system is proposed for use on the airport surface. This paper provides an overview of the research and development process for the Aeronautical Mobile Airport Communications System (AeroMACS). AeroMACS is based on a specific commercial profile of the Institute of Electrical and Electronics Engineers (IEEE) 802.16 standard known as Wireless Worldwide Interoperability for Microwave Access or WiMAX (WiMax Forum). The paper includes background on the need for global interoperability in air/ground data communications, describes potential AeroMACS applications, addresses allocated frequency spectrum constraints, summarizes the international standardization process, and provides findings and recommendations from the world s first AeroMACS prototype implemented in Cleveland, Ohio, USA.

  19. Rating of new outlet structures for MacFarlane Reservoir

    Data.gov (United States)

    US Fish and Wildlife Service, Department of the Interior — Memorandum explaining the new work on the outlet structure at MacFarlane Reservoir. Flow measurements were taken at different staff gage elevations and this data is...

  20. Big Mac arvestab raha ostujõudu / Harli Uljas

    Index Scriptorium Estoniae

    Uljas, Harli

    2005-01-01

    The Economist võrdleb maailma valuutade suhestamiseks Big Mac'i burgeri hindu 120 riigis, kuna see meetod võimaldab saada ülevaate riikide elanikkonna tegelikust ostujõust. Tabel: Hamburgeri standard

  1. Big Mac arvestab raha ostujõudu / Harli Uljas

    Index Scriptorium Estoniae

    Uljas, Harli

    2005-01-01

    The Economist võrdleb maailma valuutade suhestamiseks Big Mac'i burgeri hindu 120 riigis, kuna see meetod võimaldab saada ülevaate riikide elanikkonna tegelikust ostujõust. Tabel: Hamburgeri standard

  2. MAC layer security issues in wireless mesh networks

    Science.gov (United States)

    Reddy, K. Ganesh; Thilagam, P. Santhi

    2016-03-01

    Wireless Mesh Networks (WMNs) have emerged as a promising technology for a broad range of applications due to their self-organizing, self-configuring and self-healing capability, in addition to their low cost and easy maintenance. Securing WMNs is more challenging and complex issue due to their inherent characteristics such as shared wireless medium, multi-hop and inter-network communication, highly dynamic network topology and decentralized architecture. These vulnerable features expose the WMNs to several types of attacks in MAC layer. The existing MAC layer standards and implementations are inadequate to secure these features and fail to provide comprehensive security solutions to protect both backbone and client mesh. Hence, there is a need for developing efficient, scalable and integrated security solutions for WMNs. In this paper, we classify the MAC layer attacks and analyze the existing countermeasures. Based on attacks classification and countermeasures analysis, we derive the research directions to enhance the MAC layer security for WMNs.

  3. Mac OS X : Tiger edition the missing manual

    CERN Document Server

    Pogue, David

    2005-01-01

    You can set your watch to it: As soon as Apple comes out with another version of Mac OS X, David Pogue hits the streets with another meticulous Missing Manual to cover it with a wealth of detail. The new Mac OS X 10.4, better known as Tiger, is faster than its predecessors, but nothing's too fast for Pogue and Mac OS X: The Missing Manual. There are many reasons why this is the most popular computer book of all time. With its hallmark objectivity, the Tiger Edition thoroughly explores the latest features to grace the Mac OS. Which ones work well and which do not? What should you look for? Th

  4. Review of World of Money CD-ROM for PC/Mac [CD-ROM

    Directory of Open Access Journals (Sweden)

    Philip de Jersey

    1998-12-01

    Full Text Available Following on from the impressive development of the new HSBC Money Gallery in 1997, the British Museum has launched into the world of electronic publishing with the World of Money, an "interactive exploration of money worldwide from ancient times to the present day". Intended for ages ten to adult, the CD promises "a mine of information about the use, form, history and importance of money around the globe", and "fun and information for all the family". Reviewing in a Mac-unfriendly environment, I have been able to run the CD only on a PC. On a 166Mhz MMX with 32Mb RAM and a 12x CD it runs impressively quickly, with no more than two or three seconds of the "loading new page" display when switching between different parts of the program. Minimum requirements are listed as a 486 with 8Mb RAM, 40Mb free hard disk space, Windows 3.11 or Windows 95, 4x CD drive, 1Mb 256 colours graphics card, 16-bit Sound Blaster compatible sound card, and a VGA monitor. Minimum requirements for the Mac are listed as System 7, 603e processor, 16Mb RAM, 40MB free hard disk space, 6x CD drive, 1Mb video card and Apple monitor or Multisync with adaptor. The CD opens with an image of the British Museum portico, through which we are taken into the foyer, complete with the sound effects of massed ranks of tourists. We have four options available on a lectern, or by turning left, right or going upstairs: History of Money, Information Centre, Activities, and Options. Clicking on a large question mark brings up the Help screens (Figure 1.

  5. A tribute to Lloyd D. MacLean.

    Science.gov (United States)

    Keith, Roger G

    2015-08-01

    Dr. Lloyd D. MacLean, long-time co-editor of the Canadian Journal of Surgery passed away earlier this year at the age of 90. In order to appreciate the contributions of Dr. MacLean to the journal, this commentary recognizes him as a humble surgeon–scientist who was one of — if not the — most outstanding Canadian ambassadors to academic surgery in North America.

  6. Conformal holonomy in MacDowell-Mansouri gravity

    Energy Technology Data Exchange (ETDEWEB)

    Reid, James A., E-mail: j.a.reid@abdn.ac.uk [SUPA Department of Physics, University of Aberdeen, Aberdeen, AB24 3UE (United Kingdom); Wang, Charles H.-T., E-mail: c.wang@abdn.ac.uk [SUPA Department of Physics, University of Aberdeen, Aberdeen, AB24 3UE (United Kingdom); STFC Rutherford Appleton Laboratory, Chilton, Didcot, Oxon, OX11 0QX (United Kingdom)

    2014-03-15

    The MacDowell-Mansouri formulation of general relativity is based on a gauge theory whose gauge algebra depends on the sign of the cosmological constant. In this article, we show that the gauge algebra is uniquely determined by the conformal structure of spacetime itself. Specifically, we show that in vacuum: the spacetime conformal holonomy algebra coincides with the MacDowell-Mansouri gauge algebra for both signs of the cosmological constant, in both Lorentzian and Euclidean metric signatures.

  7. Some Problems of Alasdair MacIntyre’s "Emotivism Thesis"

    OpenAIRE

    2016-01-01

    In this article Alasdair MacIntyre’s thesis concerning emotivist use of moral utterances in contemporary liberal societies is analysed. One tries to show that it needs further clarification since at least three elements of MacIntyre’s argument seem to pose certain problems; these are: ‘discussion halt’ as the source of emotivism, comprehensive doctrines as premises of respective arguments in liberal debates and the problem of incommensurability. These three problematic eleme...

  8. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  9. Fuel processors for fuel cell APU applications

    Science.gov (United States)

    Aicher, T.; Lenz, B.; Gschnell, F.; Groos, U.; Federici, F.; Caprile, L.; Parodi, L.

    The conversion of liquid hydrocarbons to a hydrogen rich product gas is a central process step in fuel processors for auxiliary power units (APUs) for vehicles of all kinds. The selection of the reforming process depends on the fuel and the type of the fuel cell. For vehicle power trains, liquid hydrocarbons like gasoline, kerosene, and diesel are utilized and, therefore, they will also be the fuel for the respective APU systems. The fuel cells commonly envisioned for mobile APU applications are molten carbonate fuel cells (MCFC), solid oxide fuel cells (SOFC), and proton exchange membrane fuel cells (PEMFC). Since high-temperature fuel cells, e.g. MCFCs or SOFCs, can be supplied with a feed gas that contains carbon monoxide (CO) their fuel processor does not require reactors for CO reduction and removal. For PEMFCs on the other hand, CO concentrations in the feed gas must not exceed 50 ppm, better 20 ppm, which requires additional reactors downstream of the reforming reactor. This paper gives an overview of the current state of the fuel processor development for APU applications and APU system developments. Furthermore, it will present the latest developments at Fraunhofer ISE regarding fuel processors for high-temperature fuel cell APU systems on board of ships and aircrafts.

  10. A Demo Processor as an Educational Tool

    NARCIS (Netherlands)

    van Moergestel, L.; van Nieuwland, K.; Vermond, L.; Meyer, John-Jules Charles

    2014-01-01

    Explaining the workings of a processor can be done in several ways. Just a written explanation, some pictures, a simulator program or a real hardware demo. The research presented here is based on the idea that a slowly working hardware demo could be a nice tool to explain to IT students the inner

  11. Quantum Algorithm Processor For Finding Exact Divisors

    OpenAIRE

    Burger, John Robert

    2005-01-01

    Wiring diagrams are given for a quantum algorithm processor in CMOS to compute, in parallel, all divisors of an n-bit integer. Lines required in a wiring diagram are proportional to n. Execution time is proportional to the square of n.

  12. Continuous history variable for programmable quantum processors

    CERN Document Server

    Vlasov, Alexander Yu

    2010-01-01

    In this brief note is discussed application of continuous quantum history ("trash") variable for simplification of scheme of programmable quantum processor. Similar scheme may be tested also in other models of the theory of quantum algorithms and complexity, because provides modification of a standard operation: quantum function evaluation.

  13. Focal-plane sensor-processor chips

    CERN Document Server

    Zarándy, Ákos

    2011-01-01

    Focal-Plane Sensor-Processor Chips explores both the implementation and application of state-of-the-art vision chips. Presenting an overview of focal plane chip technology, the text discusses smart imagers and cellular wave computers, along with numerous examples of current vision chips.

  14. Microarchitecture of the Godson-2 Processor

    Institute of Scientific and Technical Information of China (English)

    Wei-Wu Hu; Fu-Xin Zhang; Zu-Song Li

    2005-01-01

    The Godson project is the first attempt to design high performance general-purpose microprocessors in China.This paper introduces the microarchitecture of the Godson-2 processor which is a 64-bit, 4-issue, out-of-order execution RISC processor that implements the 64-bit MIPS-like instruction set. The adoption of the aggressive out-of-order execution techniques (such as register mapping, branch prediction, and dynamic scheduling) and cache techniques (such as non-blocking cache, load speculation, dynamic memory disambiguation) helps the Godson-2 processor to achieve high performance even at not so high frequency. The Godson-2 processor has been physically implemented on a 6-metal 0.18μm CMOS technology based on the automatic placing and routing flow with the help of some crafted library cells and macros. The area of the chip is 6,700 micrometers by 6,200 micrometers and the clock cycle at typical corner is 2.3ns.

  15. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  16. Practical guide to energy management for processors

    CERN Document Server

    Consortium, Energywise

    2012-01-01

    Do you know how best to manage and reduce your energy consumption? This book gives comprehensive guidance on effective energy management for organisations in the polymer processing industry. This book is one of three which support the ENERGYWISE Plastics Project eLearning platform for European plastics processors to increase their knowledge and understanding of energy management. Topics covered include: Understanding Energy,

  17. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  18. Analysis of Reconfigurable Processors Using Petri Net

    Directory of Open Access Journals (Sweden)

    Hadis Heidari

    2013-07-01

    Full Text Available In this paper, we propose Petri net models for processing elements. The processing elements include: a general-purpose processor (GPP, a reconfigurable element (RE, and a hybrid element (combining a GPP with an RE. The models consist of many transitions and places. The model and associated analysis methods provide a promising tool for modeling and performance evaluation of reconfigurable processors. The model is demonstrated by considering a simple example. This paper describes the development of a reconfigurable processor; the developed system is based on the Petri net concept. Petri nets are becoming suitable as a formal model for hardware system design. Designers can use Petri net as a modeling language to perform high level analysis of complex processors designs processing chips. The simulation does with PIPEv4.1 simulator. The simulation results show that Petri net state spaces are bounded and safe and have not deadlock and the average of number tokens in first token is 0.9901 seconds. In these models, there are only 5% errors; also the analysis time in these models is 0.016 seconds.

  19. 42 CFR 423.2102 - Request for MAC review when ALJ issues decision or dismissal.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Request for MAC review when ALJ issues decision or... Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2102 Request for MAC review when ALJ issues decision or dismissal. (a)(1) An enrollee to the ALJ hearing may request a MAC review if the enrollee files...

  20. 42 CFR 423.2062 - Applicability of policies not binding on the ALJ and MAC.

    Science.gov (United States)

    2010-10-01

    ... and MAC. 423.2062 Section 423.2062 Public Health CENTERS FOR MEDICARE & MEDICAID SERVICES, DEPARTMENT... BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2062 Applicability of policies not binding on the ALJ and MAC. (a) ALJs and the MAC are not bound by CMS program guidance, such as program...

  1. 42 CFR 423.2110 - MAC reviews on its own motion.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false MAC reviews on its own motion. 423.2110 Section 423... (CONTINUED) MEDICARE PROGRAM VOLUNTARY MEDICARE PRESCRIPTION DRUG BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2110 MAC reviews on its own motion. (a) General rule. The MAC may decide on...

  2. 42 CFR 423.2050 - Removal of a hearing request from an ALJ to the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false Removal of a hearing request from an ALJ to the MAC..., ALJ Hearings, MAC review, and Judicial Review § 423.2050 Removal of a hearing request from an ALJ to the MAC. If a request for hearing is pending before an ALJ, the MAC may assume responsibility for...

  3. 42 CFR 423.2108 - MAC Actions when request for review is filed.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false MAC Actions when request for review is filed. 423... Hearings, MAC review, and Judicial Review § 423.2108 MAC Actions when request for review is filed. (a) General. Except as specified in paragraph (c) of this section, when an enrollee requests that the MAC...

  4. A Mac Protocol Implementation for Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    Jamila Bhar

    2015-01-01

    Full Text Available IEEE 802.15.4 is an important standard for Low Rate Wireless Personal Area Network (LRWPAN. The IEEE 802.15.4 presents a flexible MAC protocol that provides good efficiency for data transmission by adapting its parameters according to characteristics of different applications. In this research work, some restrictions of this standard are explained and an improvement of traffic efficiency by optimizing MAC layer is proposed. Implementation details for several blocks of communication system are carefully modeled. The protocol implementation is done using VHDL language. The analysis gives a full understanding of the behavior of the MAC protocol with regard to backoff delay, data loss probability, congestion probability, slot effectiveness, and traffic distribution for terminals. Two ideas are proposed and tested to improve efficiency of CSMA/CA mechanism for IEEE 802.15.4 MAC Layer. Primarily, we dynamically adjust the backoff exponent (BE according to queue level of each node. Secondly, we vary the number of consecutive clear channel assessment (CCA for packet transmission. We demonstrate also that slot compensation provided by the enhanced MAC protocol can greatly avoid unused slots. The results show the significant improvements expected by our approach among the IEEE 802.15.4 MAC standards. Synthesis results show also hardware performances of our proposed architecture.

  5. Connectivity-Based Reliable Multicast MAC Protocol for IEEE 802.11 Wireless LANs

    Directory of Open Access Journals (Sweden)

    Woo-Yong Choi

    2009-01-01

    Full Text Available We propose the efficient reliable multicast MAC protocol based on the connectivity information among the recipients. Enhancing the BMMM (Batch Mode Multicast MAC protocol, the reliable multicast MAC protocol significantly reduces the RAK (Request for ACK frame transmissions in a reasonable computational time and enhances the MAC performance. By the analytical performance analysis, the throughputs of the BMMM protocol and our proposed MAC protocol are derived. Numerical examples show that our proposed MAC protocol increases the reliable multicast MAC performance for IEEE 802.11 wireless LANs.

  6. Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

    National Research Council Canada - National Science Library

    Abdul Rehman Buzdar; Liguo Sun; Rao Kashif; Muhammad Waqar Azhar; Muhammad Imran Khan

    2017-01-01

    We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency...

  7. Area and Energy Efficient Viterbi Accelerator for Embedded Processor Datapaths

    National Research Council Canada - National Science Library

    Abdul Rehman Buzdar; Liguo Sun; Muhammad Waqar Azhar; Muhammad Imran Khan; Rao Kashif

    2017-01-01

    .... We present the integration of a mixed hardware/software viterbi accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency...

  8. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S.; Sedukhin, S. [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I.

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  9. Anaesthesia with sevoflurane in pigeons: minimal anaesthetic concentration (MAC) determination and investigation of cardiorespiratory variables at 1 MAC.

    Science.gov (United States)

    Botman, J; Gabriel, F; Dugdale, A H A; Vandeweerd, J-M

    2016-05-28

    The objective of the study was to determine the minimal anaesthetic concentration (MAC) of sevoflurane (SEVO) in pigeons and investigate the effects of 1 MAC SEVO anaesthesia on cardiovascular and respiratory variables compared with the awake state. This is a prospective, experimental study. Animals were seven healthy adult pigeons. After acclimatisation to handling, heart rate (HR), heart rhythm, respiratory rate (fR), end-expired carbon dioxide tension (PE'CO2), inspired CO2 tension, indirect systolic arterial blood pressure (SAP) and cloacal temperature were measured to determine baseline, 'awake' values. Pigeons were then anaesthetised with SEVO and MAC was determined by the 'bracketing' method. The same variables were monitored during a 40 minute period at 1.0 MAC SEVO for each bird. Mean MAC was 3.0±0.6 per cent for SEVO. During maintenance of anaesthesia at 1.0 MAC, SAP decreased significantly (Pawake PE'CO2 values were unexpectedly low. Sinus arrhythmias were detected in two birds under SEVO anaesthesia. The times to tracheal intubation and to recovery were 2.5±0.7 and 6.4±1.7 minutes, respectively. Recovery was rapid and uneventful in all birds. In conclusion, SEVO is suitable for anaesthesia in pigeons. British Veterinary Association.

  10. Learning Unix for Mac OS X Tiger Unlock the Power of Unix

    CERN Document Server

    Taylor, Dave

    2005-01-01

    Thoroughly revised and updated for Mac OS X Tiger, this new edition introduces Mac users to the Terminal application and shows you how to navigate the command interface, explore hundreds of Unix applications that come with the Mac, and, most importantly, how to take advantage of both the Mac and Unix interfaces. If you want to master the command-line, this gentle guide to using Unix on Mac OS X Tiger is well worth its cover price

  11. 49 CFR 234.275 - Processor-based systems.

    Science.gov (United States)

    2010-10-01

    ..., DEPARTMENT OF TRANSPORTATION GRADE CROSSING SIGNAL SYSTEM SAFETY AND STATE ACTION PLANS Maintenance, Inspection, and Testing Requirements for Processor-Based Systems § 234.275 Processor-based systems. (a... 49 Transportation 4 2010-10-01 2010-10-01 false Processor-based systems. 234.275 Section...

  12. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores that...

  13. Evaluating New Architectural Features Of The Intel(R) Xeon(R) 7500 Processor For Hpc Workloads

    OpenAIRE

    2011-01-01

    In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies an...

  14. Finite difference programs and array processors. [High-speed floating point processing by coupling host computer to programable array processor

    Energy Technology Data Exchange (ETDEWEB)

    Rudy, T.E.

    1977-08-01

    An alternative to maxi computers for high-speed floating-point processing capabilities is the coupling of a host computer to a programable array processor. This paper compares the performance of two finite difference programs on various computers and their expected performance on commercially available array processors. The significance of balancing array processor computation, host-array processor control traffic, and data transfer operations is emphasized. 3 figures, 1 table.

  15. A MacWilliams type identity for m-spotty generalized Lee weight enumerators over $\\mathbb{Z}_q$ q

    CERN Document Server

    Ozen, Mehmet

    2012-01-01

    Burst errors are very common in practice. There have been many designs in order to control and correct such errors. Recently, a new class of byte error control codes called spotty byte error control codes has been specifically designed to fit the large capacity memory systems that use high-density random access memory (RAM) chips with input/output data of 8, 16, and 32 bits. The MacWilliams identity describes how the weight enumerator of a linear code and the weight enumerator of its dual code are related. Also, Lee metric which has attracted many researchers due to its applications. In this paper, we combine these two interesting topics and introduce the m-spotty generalized Lee weights and the m-spotty generalized Lee weight enumerators of a code over Z q and prove a MacWilliams type identity. This generalization includes both the case of the identity given in the paper [I. Siap, MacWilliams identity for m-spotty Lee weight enumerators, Appl. Math. Lett. 23 (1) (2010) 13-16] and the identity given in the pa...

  16. Cache Energy Optimization Techniques For Modern Processors

    Energy Technology Data Exchange (ETDEWEB)

    Mittal, Sparsh [ORNL

    2013-01-01

    Modern multicore processors are employing large last-level caches, for example Intel's E7-8800 processor uses 24MB L3 cache. Further, with each CMOS technology generation, leakage energy has been dramatically increasing and hence, leakage energy is expected to become a major source of energy dissipation, especially in last-level caches (LLCs). The conventional schemes of cache energy saving either aim at saving dynamic energy or are based on properties specific to first-level caches, and thus these schemes have limited utility for last-level caches. Further, several other techniques require offline profiling or per-application tuning and hence are not suitable for product systems. In this book, we present novel cache leakage energy saving schemes for single-core and multicore systems; desktop, QoS, real-time and server systems. Also, we present cache energy saving techniques for caches designed with both conventional SRAM devices and emerging non-volatile devices such as STT-RAM (spin-torque transfer RAM). We present software-controlled, hardware-assisted techniques which use dynamic cache reconfiguration to configure the cache to the most energy efficient configuration while keeping the performance loss bounded. To profile and test a large number of potential configurations, we utilize low-overhead, micro-architecture components, which can be easily integrated into modern processor chips. We adopt a system-wide approach to save energy to ensure that cache reconfiguration does not increase energy consumption of other components of the processor. We have compared our techniques with state-of-the-art techniques and have found that our techniques outperform them in terms of energy efficiency and other relevant metrics. The techniques presented in this book have important applications in improving energy-efficiency of higher-end embedded, desktop, QoS, real-time, server processors and multitasking systems. This book is intended to be a valuable guide for both

  17. Cognitive Radio MAC Protocol for WLAN

    DEFF Research Database (Denmark)

    Zhang, Qi; Fitzek, Frank H.P.; Iversen, Villy Bæk

    2008-01-01

    To solve the performance degradation issue in current WLAN caused by the crowded unlicensed spectrum, we propose a cognitive radio (CR) media access protocol, C-CSMA/CA. The basic idea is that with cognitive radio techniques the WLAN devices can not only access the legacy WLAN unlicensed spectrum...... hole; moreover, it designs dual inband sensing scheme to detect primary user appearance. Additionally, C-CSMA/CA has the advantage to effectively solve the cognitive radio self-coexistence issues in the overlapping CR BSSs scenario. It also realizes station-based dynamic resource selection...... and utilization. It is compatible with any legacy WLAN (BSS) system. We develop and implement the simulation of C-CSMA/CA by OPNET. The simulation results show that C-CSMA/CA highly enhances throughput and reduces the queuing delay and media access delay....

  18. C-MAC compared with direct laryngoscopy for intubation in patients with cervical spine immobilization: A manikin trial.

    Science.gov (United States)

    Smereka, Jacek; Ladny, Jerzy R; Naylor, Amanda; Ruetzler, Kurt; Szarpak, Lukasz

    2017-08-01

    The aim of this study was to compare C-MAC videolaryngoscopy with direct laryngoscopy for intubation in simulated cervical spine immobilization conditions. The study was designed as a prospective randomized crossover manikin trial. 70 paramedics with MAC and C-MAC on the first attempt (95.7% MAC vs. 100% C-MAC), with similar intubation times (16.5s MAC vs. 18s C-MAC). Scenario B: The results with C-MAC were significantly better than those with MAC (pMAC vs. 19 s C-MAC), success of the first intubation attempt (88.6% MAC vs. 100% C-MAC), Cormack-Lehane grade, POGO score, severity of dental compression, device difficulty score, and preferred airway device. Scenario C: The results with C-MAC were significantly better than those with MAC (pMAC vs. 100% C-MAC), overall success rate, intubation time (27 s MAC vs. 20.5 s C-MAC), Cormack-Lehane grade, POGO score, dental compression, device difficulty score and the preferred airway device. The C-MAC videolaryngoscope is an excellent alternative to the MAC laryngoscope for intubating manikins with cervical spine immobilization. Copyright © 2017 Elsevier Inc. All rights reserved.

  19. Multiple core computer processor with globally-accessible local memories

    Energy Technology Data Exchange (ETDEWEB)

    Shalf, John; Donofrio, David; Oliker, Leonid

    2016-09-20

    A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores.

  20. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  1. Multifunction nonlinear signal processor - Deconvolution and correlation

    Science.gov (United States)

    Javidi, Bahram; Horner, Joseph L.

    1989-08-01

    A multifuncional nonlinear optical signal processor is described that allows different types of operations, such as image deconvolution and nonlinear correlation. In this technique, the joint power spectrum of the input signal is thresholded with varying nonlinearity to produce different specific operations. In image deconvolution, the joint power spectrum is modified and hard-clip thresholded to remove the amplitude distortion effects and to restore the correct phase of the original image. In optical correlation, the Fourier transform interference intensity is thresholded to provide higher correlation peak intensity and a better-defined correlation spot. Various types of correlation signals can be produced simply by varying the severity of the nonlinearity, without the need for synthesis of specific matched filter. An analysis of the nonlinear processor for image deconvolution is presented.

  2. Model of computation for Fourier optical processors

    Science.gov (United States)

    Naughton, Thomas J.

    2000-05-01

    We present a novel and simple theoretical model of computation that captures what we believe are the most important characteristics of an optical Fourier transform processor. We use this abstract model to reason about the computational properties of the physical systems it describes. We define a grammar for our model's instruction language, and use it to write algorithms for well-known filtering and correlation techniques. We also suggest suitable computational complexity measures that could be used to analyze any coherent optical information processing technique, described with the language, for efficiency. Our choice of instruction language allows us to argue that algorithms describable with this model should have optical implementations that do not require a digital electronic computer to act as a master unit. Through simulation of a well known model of computation from computer theory we investigate the general-purpose capabilities of analog optical processors.

  3. Victor Bérard et la Macédoine

    Directory of Open Access Journals (Sweden)

    Ivan Savev

    2011-01-01

    Full Text Available Un helléniste convaincu, Victor Bérard, en vient, au début du XXe siècle à soutenir l’existence de « Macédoniens » et le slogan « la Macédoine aux Macédoniens”.Le Congrès de Berlin en 1878 avait laissé la Macédoine aux mains des Ottomans. La Grèce, la Serbie et la Bulgarie, parvenues à ses limites et prévoyant le retrait futur des Ottomans peaufinent les arguments linguistiques et historiques qui justifieront leurs revendications territoriales. Victor Bérard, un helléniste respecté et bon connaisseur de la région sud balkanique, effectue des enquêtes en Macédoine en 1896 et 1903 qu’il publie à Paris.Cette étude montre comment, dans le contexte de la propagande nationaliste des prétendants à la possession de la Macédoine, Victor Bérard en vient progressivement à affirmer qu’il existe une population autochtone, les Macédoniens. Il soutient leur programme pour la constitution d’une fédération ou confédération avec le slogan « la Macédoine aux Macédoniens » ce qui fait toute l’actualité de ses ouvrages.In 1878, the Congress of Berlin had left Macedonia in the hands of the Ottomans. Greece, Serbia and Bulgaria had reached its limits. Anticipating the Ottoman retreat, they polish language and historical arguments that will justify their territorial claims. Victor Bérard, a respected Hellenist and a good expert of the southern Balkans, is doing researches in Macedonia in 1896 and 1903. These will be later published in Paris.This study shows how, in the context of the nationalist propaganda build-up made by the candidates for the possession of Macedonia, Victor Bérard comes progressively to assert the existence of a native population: the Macedonians. He supports their program for the forming of a federation or confederation which slogan would be “Macedonia to Macedonians”. This makes his works very topical.

  4. The many faces of Mac-1 in autoimmune disease.

    Science.gov (United States)

    Rosetti, Florencia; Mayadas, Tanya N

    2016-01-01

    Mac-1 (CD11b/CD18) is a β2 integrin classically regarded as a pro-inflammatory molecule because of its ability to promote phagocyte cytotoxic functions and enhance the function of several effector molecules such as FcγR, uPAR, and CD14. Nevertheless, recent reports have revealed that Mac-1 also plays significant immunoregulatory roles, and genetic variants in ITGAM, the gene that encodes CD11b, confer risk for the autoimmune disease systemic lupus erythematosus (SLE). This has renewed interest in the physiological roles of this integrin and raised new questions on how its seemingly opposing biological functions may be regulated. Here, we provide an overview of the CD18 integrins and how their activation may be regulated as this may shed light on how the opposing roles of Mac-1 may be elicited. We then discuss studies that exemplify Mac-1's pro-inflammatory versus regulatory roles particularly in the context of IgG immune complex-mediated inflammation. This includes a detailed examination of molecular mechanisms that could explain the risk-conferring effect of rs1143679, a single nucleotide non-synonymous Mac-1 polymorphism associated with SLE.

  5. Communication Efficient Multi-processor FFT

    Science.gov (United States)

    Lennart Johnsson, S.; Jacquemin, Michel; Krawitz, Robert L.

    1992-10-01

    Computing the fast Fourier transform on a distributed memory architecture by a direct pipelined radix-2, a bi-section, or a multisection algorithm, all yield the same communications requirement, if communication for all FFT stages can be performed concurrently, the input data is in normal order, and the data allocation is consecutive. With a cyclic data allocation, or bit-reversed input data and a consecutive allocation, multi-sectioning offers a reduced communications requirement by approximately a factor of two. For a consecutive data allocation, normal input order, a decimation-in-time FFT requires that P/ N + d-2 twiddle factors be stored for P elements distributed evenly over N processors, and the axis that is subject to transformation be distributed over 2 d processors. No communication of twiddle factors is required. The same storage requirements hold for a decimation-in-frequency FFT, bit-reversed input order, and consecutive data allocation. The opposite combination of FFT type and data ordering requires a factor of log 2N more storage for N processors. The peak performance for a Connection Machine system CM-200 implementation is 12.9 Gflops/s in 32-bit precision, and 10.7 Gflops/s in 64-bit precision for unordered transforms local to each processor. The corresponding execution rates for ordered transforms are 11.1 Gflops/s and 8.5 Gflops/s, respectively. For distributed one- and two-dimensional transforms the peak performance for unordered transforms exceeds 5 Gflops/s in 32-bit precision and 3 Gflops/s in 64-bit precision. Three-dimensional transforms execute at a slightly lower rate. Distributed ordered transforms execute at a rate of about {1}/{2}to {2}/{3} of the unordered transforms.

  6. Breadboard Signal Processor for Arraying DSN Antennas

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Chandra, Kumar; Trinh, Joseph; Soriano, Melissa; Navarro, Robert; Rogstad, Stephen; Goodhart, Charles; Proctor, Robert; Jourdan, Michael; hide

    2008-01-01

    A recently developed breadboard version of an advanced signal processor for arraying many antennas in NASA s Deep Space Network (DSN) can accept inputs in a 500-MHz-wide frequency band from six antennas. The next breadboard version is expected to accept inputs from 16 antennas, and a following developed version is expected to be designed according to an architecture that will be scalable to accept inputs from as many as 400 antennas. These and similar signal processors could also be used for combining multiple wide-band signals in non-DSN applications, including very-long-baseline interferometry and telecommunications. This signal processor performs functions of a wide-band FX correlator and a beam-forming signal combiner. [The term "FX" signifies that the digital samples of two given signals are fast Fourier transformed (F), then the fast Fourier transforms of the two signals are multiplied (X) prior to accumulation.] In this processor, the signals from the various antennas are broken up into channels in the frequency domain (see figure). In each frequency channel, the data from each antenna are correlated against the data from each other antenna; this is done for all antenna baselines (that is, for all antenna pairs). The results of the correlations are used to obtain calibration data to align the antenna signals in both phase and delay. Data from the various antenna frequency channels are also combined and calibration corrections are applied. The frequency-domain data thus combined are then synthesized back to the time domain for passing on to a telemetry receiver

  7. A post-processor for Gurmukhi OCR

    Indian Academy of Sciences (India)

    G S Lehal; Chandan Singh

    2002-02-01

    A post-processing system for OCR of Gurmukhi script has been developed. Statistical information of Punjabi language syllable combinations, corpora look-up and certain heuristics based on Punjabi grammar rules have been combined to design the post-processor. An improvement of 3% in recognition rate, from 94.35% to 97.34%, has been reported on clean images using the post-processing techniques.

  8. Modules for Pipelined Mixed Radix FFT Processors

    Directory of Open Access Journals (Sweden)

    Anatolij Sergiyenko

    2016-01-01

    Full Text Available A set of soft IP cores for the Winograd r-point fast Fourier transform (FFT is considered. The cores are designed by the method of spatial SDF mapping into the hardware, which provides the minimized hardware volume at the cost of slowdown of the algorithm by r times. Their clock frequency is equal to the data sampling frequency. The cores are intended for the high-speed pipelined FFT processors, which are implemented in FPGA.

  9. High-pressure coal fuel processor development

    Energy Technology Data Exchange (ETDEWEB)

    Greenhalgh, M.L.

    1992-11-01

    The objective of Subtask 1.1 Engine Feasibility was to conduct research needed to establish the technical feasibility of ignition and stable combustion of directly injected, 3,000 psi, low-Btu gas with glow plug ignition assist at diesel engine compression ratios. This objective was accomplished by designing, fabricating, testing and analyzing the combustion performance of synthesized low-Btu coal gas in a single-cylinder test engine combustion rig located at the Caterpillar Technical Center engine lab in Mossville, Illinois. The objective of Subtask 1.2 Fuel Processor Feasibility was to conduct research needed to establish the technical feasibility of air-blown, fixed-bed, high-pressure coal fuel processing at up to 3,000 psi operating pressure, incorporating in-bed sulfur and particulate capture. This objective was accomplished by designing, fabricating, testing and analyzing the performance of bench-scale processors located at Coal Technology Corporation (subcontractor) facilities in Bristol, Virginia. These two subtasks were carried out at widely separated locations and will be discussed in separate sections of this report. They were, however, independent in that the composition of the synthetic coal gas used to fuel the combustion rig was adjusted to reflect the range of exit gas compositions being produced on the fuel processor rig. Two major conclusions resulted from this task. First, direct injected, ignition assisted Diesel cycle engine combustion systems can be suitably modified to efficiently utilize these low-Btu gas fuels. Second, high pressure gasification of selected run-of-the-mine coals in batch-loaded fuel processors is feasible. These two findings, taken together, significantly reduce the perceived technical risks associated with the further development of the proposed coal gas fueled Diesel cycle power plant concept.

  10. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  11. Virtual Modular Redundancy of Processor Module in the PLC

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Kwang-Il; Hwang, SungJae; Yoon, DongHwa [SOOSAN ENS Co., Seoul (Korea, Republic of)

    2016-10-15

    Dual Modular Redundancy (DMR) is mainly used to implement these safety control systems. DMR is conveyed when components of a system are duplicated, providing another component in case one should fault or fail. This feature has a high availability and large fault tolerant. It provides zero downtime that is required for nuclear power plants. So nuclear power plant has been commercialized by multiple redundant systems. The following paper, we propose a Virtual Modular Redundancy (VMR) rather than physical triple of the Programmable Logic Controller (PLC) processor module to ensure the reliability of the nuclear power plant control system. VMR implementation minimizes design changes to continue to use the commercially available redundant system. Also, the purpose of the VMR is to improve the efficiency and reliability in many ways, such as fault tolerant and fail-safe and cost. VMR guarantees a wide range of reliable fault recovery, fault tolerance, etc. It is prevented before it causes great damages due to the continuous failure of the two modules. The reliable communication speed is slow and also it has a small bandwidth. It is a great loss in the safety control system. However, VMR aims to avoid nuclear power plants that were suspended due to fail-safe. It is not for the purpose of commonly used. Application of VMR is actually expected to require a lot of research and trial and error until they adapt to the nuclear regulatory and standards.

  12. Intelligent trigger processor for the crystal box

    CERN Document Server

    Sanders, G H; Cooper, M D; Hart, G W; Hoffman, C M; Hogan, G E; Hughes, E B; Matis, H S; Rolfe, J; Sandberg, V D; Williams, R A; Wilson, S; Zeman, H

    1981-01-01

    A large solid angle angular modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor-changing decays of the muon. A beam of up to 10/sup 6/ muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor. Further reduction to <1 Hz is achieved by a microprocessor-based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic logic. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex ...

  13. Software-Reconfigurable Processors for Spacecraft

    Science.gov (United States)

    Farrington, Allen; Gray, Andrew; Bell, Bryan; Stanton, Valerie; Chong, Yong; Peters, Kenneth; Lee, Clement; Srinivasan, Jeffrey

    2005-01-01

    A report presents an overview of an architecture for a software-reconfigurable network data processor for a spacecraft engaged in scientific exploration. When executed on suitable electronic hardware, the software performs the functions of a physical layer (in effect, acts as a software radio in that it performs modulation, demodulation, pulse-shaping, error correction, coding, and decoding), a data-link layer, a network layer, a transport layer, and application-layer processing of scientific data. The software-reconfigurable network processor is undergoing development to enable rapid prototyping and rapid implementation of communication, navigation, and scientific signal-processing functions; to provide a long-lived communication infrastructure; and to provide greatly improved scientific-instrumentation and scientific-data-processing functions by enabling science-driven in-flight reconfiguration of computing resources devoted to these functions. This development is an extension of terrestrial radio and network developments (e.g., in the cellular-telephone industry) implemented in software running on such hardware as field-programmable gate arrays, digital signal processors, traditional digital circuits, and mixed-signal application-specific integrated circuits (ASICs).

  14. Issue Mechanism for Embedded Simultaneous Multithreading Processor

    Science.gov (United States)

    Zang, Chengjie; Imai, Shigeki; Frank, Steven; Kimura, Shinji

    Simultaneous Multithreading (SMT) technology enhances instruction throughput by issuing multiple instructions from multiple threads within one clock cycle. For in-order pipeline to each thread, SMT processors can provide large number of issued instructions close to or surpass than using out-of-order pipeline. In this work, we show an efficient issue logic for predicated instruction sequence with the parallel flag in each instruction, where the predicate register based issue control is adopted and the continuous instructions with the parallel flag of ‘0’ are executed in parallel. The flag is pre-defined by a compiler. Instructions from different threads are issued based on the round-robin order. We also introduce an Instruction Queue skip mechanism for thread if the queue is empty. Using this kind of issue logic, we designed a 6 threads, 7-stage, in-order pipeline processor. Based on this processor, we compare round-robin issue policy (RR(T1-Tn)) with other policies: thread one always has the highest priority (PR(T1)) and thread one or thread n has the highest priority in turn (PR(T1-Tn)). The results show that RR(T1-Tn) policy outperforms others and PR(T1-Tn) is almost the same to RR(T1-Tn) from the point of view of the issued instructions per cycle.

  15. Efficient searching and sorting applications using an associative array processor

    Science.gov (United States)

    Pace, W.; Quinn, M. J.

    1978-01-01

    The purpose of this paper is to describe a method of searching and sorting data by using some of the unique capabilities of an associative array processor. To understand the application, the associative array processor is described in detail. In particular, the content addressable memory and flip network are discussed because these two unique elements give the associative array processor the power to rapidly sort and search. A simple alphanumeric sorting example is explained in hardware and software terms. The hardware used to explain the application is the STARAN (Goodyear Aerospace Corporation) associative array processor. The software used is the APPLE (Array Processor Programming Language) programming language. Some applications of the array processor are discussed. This summary tries to differentiate between the techniques of the sequential machine and the associative array processor.

  16. Testing and operating a multiprocessor chip with processor redundancy

    Energy Technology Data Exchange (ETDEWEB)

    Bellofatto, Ralph E; Douskey, Steven M; Haring, Rudolf A; McManus, Moyra K; Ohmacht, Martin; Schmunkamp, Dietmar; Sugavanam, Krishnan; Weatherford, Bryan J

    2014-10-21

    A system and method for improving the yield rate of a multiprocessor semiconductor chip that includes primary processor cores and one or more redundant processor cores. A first tester conducts a first test on one or more processor cores, and encodes results of the first test in an on-chip non-volatile memory. A second tester conducts a second test on the processor cores, and encodes results of the second test in an external non-volatile storage device. An override bit of a multiplexer is set if a processor core fails the second test. In response to the override bit, the multiplexer selects a physical-to-logical mapping of processor IDs according to one of: the encoded results in the memory device or the encoded results in the external storage device. On-chip logic configures the processor cores according to the selected physical-to-logical mapping.

  17. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  18. Dolphin natures, human virtues: MacIntyre and ethical naturalism.

    Science.gov (United States)

    Glackin, Shane Nicholas

    2008-09-01

    Can biological facts explain human morality? Aristotelian 'virtue' ethics has traditionally assumed so. In recent years Alasdair MacIntyre has reintroduced a form of Aristotle's 'metaphysical biology' into his ethics. He argues that the ethological study of dependence and rationality in other species--dolphins in particular--sheds light on how those same traits in the typical lives of humans give rise to the moral virtues. However, some goal-oriented dolphin behaviour appears both dependent and rational in the precise manner which impresses MacIntyre, yet anything but ethically 'virtuous'. More damningly, dolphin ethologists consistently refuse to evaluate such behaviour in the manner MacIntyre claims is appropriate to moral judgement. In light of this, I argue that virtues--insofar as they name a biological or ethological category--do not name a morally significant one.

  19. An Energy Efficient MAC Proto col for Linear WSNs

    Institute of Scientific and Technical Information of China (English)

    DAI Guoyong; MIAO Chunyu; YING Kezhen; WANG Kai; CHEN Qingzhang

    2015-01-01

    Wireless sensor networks (WSNs) have been employed as an ideal solution in many applications for data gathering in harsh environment. Energy consumption is a key issue in wireless sensor networks since nodes are often battery operated. Medium access control (MAC) pro-tocol plays an important role in energy efficiency in wire-less sensor networks because nodes’ access to the shared medium is coordinated by the MAC layer. An energy ef-ficient MAC protocol is designed for data gathering in linear wireless sensor networks. In order to enhance the performance, when a source node transmits data to the sink, proper relay nodes are selected for forwarding data according to the energy consumption factor and residual energy balance factor. Some simulation experiments are conducted and the results show that, the proposed proto-col provides better energy efficiency and long lifetime than the existing DMAC protocol.

  20. A Fair-Priority MAC design in Networked Control System

    Directory of Open Access Journals (Sweden)

    Hongjun Li

    2009-10-01

    Full Text Available Media Access Control (MAC protocols in Wireless Networked Control System (WNCS must minimize the radio energy costs in sensor nodes. Latency and throughput are also important design features for MAC protocols in the applications. But most of them cannot guarantee quality for real-time traffic. This paper studies the state of the art of current real-time MAC protocols, and then introduces a medium access control protocol and a improved protocol that provide multiple priority levels and hard real-time transmission. The channel is accessed by sensors according to their priorities. Sensors send frames in a round manner with same priority. The fairness between different priorities is provided. The channel access procedure is divided into two stages: broadcast period and transmission period. Simulation and experiment results indicate that our protocol provides high channel utilization and bounded delays for real-time communication and can be well applied in the many fields especially the dynamic wireless sensor networks.

  1. Cognitive MAC Protocols for General Primary Network Models

    CERN Document Server

    Mehanna, Omar; Gamal, Hesham El

    2009-01-01

    We consider the design of cognitive Medium Access Control (MAC) protocols enabling a secondary (unlicensed) transmitter-receiver pair to communicate over the idle periods of a set of primary (licensed) channels. More specifically, we propose cognitive MAC protocols optimized for both slotted and un-slotted primary networks. For the slotted structure, the objective is to maximize the secondary throughput while maintaining synchronization between the secondary pair and not causing interference to the primary network. Our investigations differentiate between two sensing scenarios. In the first, the secondary transmitter is capable of sensing all the primary channels, whereas it senses only a subset of the primary channels in the second scenario. In both cases, we propose blind MAC protocols that efficiently learn the statistics of the primary traffic on-line and asymptotically achieve the throughput obtained when prior knowledge of primary traffic statistics is available. For the un-slotted structure, the object...

  2. Synthesizing Existing CSMA and TDMA Based MAC Protocols for VANETs.

    Science.gov (United States)

    Huang, Jiawei; Li, Qi; Zhong, Shaohua; Liu, Lianhai; Zhong, Ping; Wang, Jianxin; Ye, Jin

    2017-02-10

    Many Carrier Sense Multiple Access (CSMA) and Time Division Multiple Access (TDMA) based medium access control (MAC) protocols for vehicular ad hoc networks (VANETs) have been proposed recently. Contrary to the common perception that they are competitors, we argue that the underlying strategies used in these MAC protocols are complementary. Based on this insight, we design CTMAC, a MAC protocol that synthesizes existing strategies; namely, random accessing channel (used in CSMA-style protocols) and arbitral reserving channel (used in TDMA-based protocols). CTMAC swiftly changes its strategy according to the vehicle density, and its performance is better than the state-of-the-art protocols. We evaluate CTMAC using at-scale simulations. Our results show that CTMAC reduces the channel completion time and increases the network goodput by 45% for a wide range of application workloads and network settings.

  3. ETEEM- Extended Traffic Aware Energy Efficient MAC Scheme for WSNs

    Directory of Open Access Journals (Sweden)

    Younas Khan

    2016-11-01

    Full Text Available Idle listening issue arises when a sensor node listens to medium despite the absence of data which results in consumption of energy. ETEEM is a variant of Traffic Aware Energy Efficient MAC protocol (TEEM which focuses on energy optimization due to reduced idle listening time and much lesser overhead on energy sources. It uses a novel scheme for using idle listening time of sensor nodes. The nodes are only active for small amount of time and most of the time, will be in sleep mode when no data is available. ETEEM reduces energy at byte level and uses a smaller byte packet called FLAG replacing longer byte SYNC packets of S-MAC and SYNCrts of TEEM respectively. It also uses a single acknowledgement packet per data set hence reducing energy while reducing frequency of the acknowledgment frames sent. The performance of ETEEM is 70% better comparative to other under-consideration MAC protocols.

  4. Office for iPad and Mac for dummies

    CERN Document Server

    Weverka, Peter

    2015-01-01

    The easy way to work with Office on your iPad or Mac Are you a Mac user who isn't accustomed to working with Microsoft Office? Consider this friendly guide your go-to reference! Written in plain English and packed with easy-to-follow, step-by-step instructions, Office for iPad and Mac For Dummies walks you through every facet of Office, from installing the software and opening files to working with Word, Excel, PowerPoint, and Outlook-and beyond. Plus, you'll discover how to manage files, share content and collaborate online through social media, and find help when you need it. Two things a

  5. SACRB-MAC: A High-Capacity MAC Protocol for Cognitive Radio Sensor Networks in Smart Grid.

    Science.gov (United States)

    Yang, Zhutian; Shi, Zhenguo; Jin, Chunlin

    2016-03-31

    The Cognitive Radio Sensor Network (CRSN) is considered as a viable solution to enhance various aspects of the electric power grid and to realize a smart grid. However, several challenges for CRSNs are generated due to the harsh wireless environment in a smart grid. As a result, throughput and reliability become critical issues. On the other hand, the spectrum aggregation technique is expected to play an important role in CRSNs in a smart grid. By using spectrum aggregation, the throughput of CRSNs can be improved efficiently, so as to address the unique challenges of CRSNs in a smart grid. In this regard, we proposed Spectrum Aggregation Cognitive Receiver-Based MAC (SACRB-MAC), which employs the spectrum aggregation technique to improve the throughput performance of CRSNs in a smart grid. Moreover, SACRB-MAC is a receiver-based MAC protocol, which can provide a good reliability performance. Analytical and simulation results demonstrate that SACRB-MAC is a promising solution for CRSNs in a smart grid.

  6. SACRB-MAC: A High-Capacity MAC Protocol for Cognitive Radio Sensor Networks in Smart Grid

    Directory of Open Access Journals (Sweden)

    Zhutian Yang

    2016-03-01

    Full Text Available The Cognitive Radio Sensor Network (CRSN is considered as a viable solution to enhance various aspects of the electric power grid and to realize a smart grid. However, several challenges for CRSNs are generated due to the harsh wireless environment in a smart grid. As a result, throughput and reliability become critical issues. On the other hand, the spectrum aggregation technique is expected to play an important role in CRSNs in a smart grid. By using spectrum aggregation, the throughput of CRSNs can be improved efficiently, so as to address the unique challenges of CRSNs in a smart grid. In this regard, we proposed Spectrum Aggregation Cognitive Receiver-Based MAC (SACRB-MAC, which employs the spectrum aggregation technique to improve the throughput performance of CRSNs in a smart grid. Moreover, SACRB-MAC is a receiver-based MAC protocol, which can provide a good reliability performance. Analytical and simulation results demonstrate that SACRB-MAC is a promising solution for CRSNs in a smart grid.

  7. AMPA receptor competitive antagonism reduces halothane MAC in rats.

    Science.gov (United States)

    McFarlane, C; Warner, D S; Todd, M M; Nordholm, L

    1992-12-01

    Various subtypes of receptors have been identified for glutamate, an excitatory neurotransmitter. Previous studies have shown that antagonism of glutamate at the NMDA receptors reduces minimum alveolar concentration (MAC) for volatile anesthetics. NBQX (2,3-dihydroxy-6-nitro-7-sulfamoyl-benzo(f)quinoxaline) is a selective antagonist at the glutamatergic AMPA receptor. The purpose of this experiment was to determine whether AMPA receptor antagonism influences halothane MAC in the rat. Sprague-Dawley rats were anesthetized with halothane in 50% O2/balance N2, tracheally intubated and the lungs were mechanically ventilated. Increasing doses of NBQX were intravenously infused in three groups while the control group was infused with vehicle (D5W). Halothane MAC was then determined by the tail-clamp method. Halothane MAC was log-linearly related to plasma NBQX concentrations (MAC = 0.125 (In plasma concentration NBQX) + 1.035, r2 = 0.77). A maximal 58% reduction of halothane MAC was achieved with an NBQX loading dose of 42 mg/kg followed by a continuous infusion rate of 36 mg x kg-1 x h-1 (control = 1.02 +/- 0.07%; NBQX = 0.43 +/- 0.12%; P awake rats were randomly assigned to groups based on the dose of NBQX infused. Pa(CO2) and mean arterial pressure were measured at time 0 and at 5 and 30 min after start of NBQX infusion. The infusion was then stopped. Time until recovery of the righting reflex was recorded.(ABSTRACT TRUNCATED AT 250 WORDS)

  8. Vehicle Health Management Communications Requirements for AeroMACS

    Science.gov (United States)

    Kerczewski, Robert J.; Clements, Donna J.; Apaza, Rafael D.

    2012-01-01

    As the development of standards for the aeronautical mobile airport communications system (AeroMACS) progresses, the process of identifying and quantifying appropriate uses for the system is progressing. In addition to defining important elements of AeroMACS standards, indentifying the systems uses impacts AeroMACS bandwidth requirements. Although an initial 59 MHz spectrum allocation for AeroMACS was established in 2007, the allocation may be inadequate; studies have indicated that 100 MHz or more of spectrum may be required to support airport surface communications. Hence additional spectrum allocations have been proposed. Vehicle health management (VHM) systems, which can produce large volumes of vehicle health data, were not considered in the original bandwidth requirements analyses, and are therefore of interest in supporting proposals for additional AeroMACS spectrum. VHM systems are an emerging development in air vehicle safety, and preliminary estimates of the amount of data that will be produced and transmitted off an aircraft, both in flight and on the ground, have been prepared based on estimates of data produced by on-board vehicle health sensors and initial concepts of data processing approaches. This allowed an initial estimate of VHM data transmission requirements for the airport surface. More recently, vehicle-level systems designed to process and analyze VHM data and draw conclusions on the current state of vehicle health have been undergoing testing and evaluation. These systems make use of vehicle system data that is mostly different from VHM data considered previously for airport surface transmission, and produce processed system outputs that will be also need to be archived, thus generating additional data load for AeroMACS. This paper provides an analysis of airport surface data transmission requirements resulting from the vehicle level reasoning systems, within the context of overall VHM data requirements.

  9. Balanced Bipartite Graph Based Register Allocation for Network Processors in Mobile and Wireless Networks

    Directory of Open Access Journals (Sweden)

    Feilong Tang

    2010-01-01

    Full Text Available Mobile and wireless networks are the integrant infrastructure of mobile and pervasive computing that aims at providing transparent and preferred information and services for people anytime anywhere. In such environments, end-to-end network bandwidth is crucial to improve user's transparent experience when providing on-demand services such as mobile video playing. As a result, powerful computing power is required for networked nodes, especially for routers. General-purpose processors cannot meet such requirements due to their limited processing ability, and poor programmability and scalability. Intel's network processor IXP is specially designed for fast packet processing to achieve a broad bandwidth. IXP provides a large number of registers to reduce the number of memory accesses. Registers in an IXP are physically partitioned as two banks so that two source operands in an instruction have to come from the two banks respectively, which makes the IXP register allocation tricky and different from conventional ones. In this paper, we investigate an approach for efficiently generating balanced bipartite graph and register allocation algorithms for the dual-bank register allocation in IXPs. The paper presents a graph uniform 2-way partition algorithm (FPT, which provides an optimal solution to the graph partition, and a heuristic algorithm for generating balanced bipartite graph. Finally, we design a framework for IXP register allocation. Experimental results demonstrate the framework and the algorithms are efficient in register allocation for IXP network processors.

  10. Resource efficiency of hardware extensions of a 4-issue VLIW processor for elliptic curve cryptography

    Science.gov (United States)

    Jungeblut, T.; Puttmann, C.; Dreesen, R.; Porrmann, M.; Thies, M.; Rückert, U.; Kastens, U.

    2010-12-01

    The secure transmission of data plays a significant role in today's information era. Especially in the area of public-key-cryptography methods, which are based on elliptic curves (ECC), gain more and more importance. Compared to asymmetric algorithms, like RSA, ECC can be used with shorter key lengths, while achieving an equal level of security. The performance of ECC-algorithms can be increased significantly by adding application specific hardware extensions. Due to their fine grained parallelism, VLIW-processors are well suited for the execution of ECC algorithms. In this work, we extended the fourfold parallel CoreVA-VLIW-architecture by several hardware accelerators to increase the resource efficiency of the overall system. For the design-space exploration we use a dual design flow, which is based on the automatic generation of a complete C-compiler based tool chain from a central processor specification. Using the hardware accelerators the performance of the scalar multiplication on binary fields can be increased by the factor of 29. The energy consumption can be reduced by up to 90%. The extended processor hardware was mapped on a current 65 nm low-power standard-cell-technology. The chip area of the CoreVA-VLIW-architecture is 0.24 mm2 at a power consumption of 29 mW/MHz. The performance gain is analyzed in respect to the increased hardware costs, as chip area or power consumption.

  11. Link-layer jamming attacks on S-MAC

    OpenAIRE

    Law, Yee Wei; Hartel, Pieter; Hartog, den, D.N.; Havinga, Paul

    2005-01-01

    We argue that among denial-of-service (DoS) attacks, link-layer jamming is a more attractive option to attackers than radio jamming is. By exploiting the semantics of the link-layer protocol (aka MAC protocol), an attacker can achieve better efficiency than blindly jamming the radio signals alone. In this paper, we investigate some jamming attacks on S-MAC, the level of effectiveness and efficiency the attacks can potentially achieve, and a countermeasure that can be implemented against one o...

  12. Rand and MacIntyre on moral agency

    OpenAIRE

    Beadle, Ron

    2008-01-01

    This paper contrasts the work of Ayn Rand and Alasdair MacIntyre on moral agency. Both argue that moral agency requires the application of a consistent moral code across relationships with others and that such consistency is rarely evident in the modern social order. However, while MacIntyre holds this failure to be a defining feature of the modern social order, Rand holds this to be a failure of individuals and a marker of a wider cultural confusion. While Rand sees selfishness and capitalis...

  13. Alasdair MacIntyre: relatividad conceptual, tomismo y liberalismo

    Directory of Open Access Journals (Sweden)

    Carlos Isler S.

    2011-01-01

    Full Text Available Influenciado por Thomas Kuhn, Alasdair MacIntyre presenta una teoría conceptualmente relativista sobre las tradiciones de investigación, la cual pretende no sólo describir la estructura de las distintas tradiciones, sino también encontrar un principioque permita resolver las disputas entre ellas. Se expone esta teoría y se analiza su compatibilidad con el tomismo, tradición a la que MacIntyre dice pertenecer, y con el liberalismo, tradición a la que critica con vigor.

  14. Mac Lane method in the investigation of magnetic translation groups

    OpenAIRE

    Florek, Wojciech

    1998-01-01

    Central extensions of the three-dimensional translation group T=Z^3 by the unitary group U(1) (a group of factors) are considered within the frame of the Mac~Lane method. All nonzero vectors t in T are considered to be generators of T. This choice leads to very illustrative relations between the Mac~Lane method and Zak's approach to magnetic translation groups. It is shown that factor systems introduced by Zak and Brown can be realized only for the unitary group U(1) and for some of its finit...

  15. Directional Medium Access Control (MAC Protocols in Wireless Ad Hoc and Sensor Networks: A Survey

    Directory of Open Access Journals (Sweden)

    David Tung Chong Wong

    2015-06-01

    Full Text Available This survey paper presents the state-of-the-art directional medium access control (MAC protocols in wireless ad hoc and sensor networks (WAHSNs. The key benefits of directional antennas over omni-directional antennas are longer communication range, less multipath interference, more spatial reuse, more secure communications, higher throughput and reduced latency. However, directional antennas lead to single-/multi-channel directional hidden/exposed terminals, deafness and neighborhood, head-of-line blocking, and MAC-layer capture which need to be overcome. Addressing these problems and benefits for directional antennas to MAC protocols leads to many classes of directional MAC protocols in WAHSNs. These classes of directional MAC protocols presented in this survey paper include single-channel, multi-channel, cooperative and cognitive directional MACs. Single-channel directional MAC protocols can be classified as contention-based or non-contention-based or hybrid-based, while multi-channel directional MAC protocols commonly use a common control channel for control packets/tones and one or more data channels for directional data transmissions. Cooperative directional MAC protocols improve throughput in WAHSNs via directional multi-rate/single-relay/multiple-relay/two frequency channels/polarization, while cognitive directional MAC protocols leverage on conventional directional MAC protocols with new twists to address dynamic spectrum access. All of these directional MAC protocols are the pillars for the design of future directional MAC protocols in WAHSNs.

  16. Properties of Dual Language Exposure that Influence 2-Year-Olds' Bilingual Proficiency

    Science.gov (United States)

    Place, Silvia; Hoff, Erika

    2011-01-01

    The mothers of 29 Spanish English bilingual 25-month-olds kept diary records of their children's dual language exposure and provided information on their children's English and Spanish language development using the MacArthur-Bates inventories. Relative amount of exposure predicted language outcomes in English and Spanish. In addition, the number…

  17. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  18. Message-Driven Processor Architecture Version 11

    Science.gov (United States)

    1988-08-18

    UNCLASSIFIED . $CUUIT. v A$SIf9CAYON Or IMIS SAGE ’Whlken Dese E,...’lld) __ REPO_Or T CU NT PAGE ateREAD INSTRUCTIONS REPORT DOCUmtNTATION PAGE...fields instead of 2. This reflects the change in machine topology from 2D to 3D . Also, the NNR is no longer set to zero on a reset; it is left to...an X field, a Y field and a Z field indicating the position of the node in the 3D network grid. Its value identifies the processor on the network and

  19. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  20. Link-layer jamming attacks on S-MAC

    NARCIS (Netherlands)

    Law, Yee Wei; Hartel, Pieter; Hartog, den Jerry; Havinga, Paul

    2005-01-01

    We argue that among denial-of-service (DoS) attacks, link-layer jamming is a more attractive option to attackers than radio jamming is. By exploiting the semantics of the link-layer protocol (aka MAC protocol), an attacker can achieve better efficiency than blindly jamming the radio signals alone. W

  1. Listening, Looking, and Learning with MacLang.

    Science.gov (United States)

    Frommer, Judith

    1989-01-01

    Describes how the capabilities of the MacLang authoring system allow foreign language teachers to develop computer-assisted instruction that meets the listening skill objectives of foreign language courses. Examples are given of the use of audio and video interfaces that facilitate listening comprehension. (Author/CB)

  2. Beamforming in Ad Hoc Networks: MAC Design and Performance Modeling

    Directory of Open Access Journals (Sweden)

    Khalil Fakih

    2009-01-01

    Full Text Available We examine in this paper the benefits of beamforming techniques in ad hoc networks. We first devise a novel MAC paradigm for ad hoc networks when using these techniques in multipath fading environment. In such networks, the use of conventional directional antennas does not necessarily improve the system performance. On the other hand, the exploitation of the potential benefits of smart antenna systems and especially beamforming techniques needs a prior knowledge of the physical channel. Our proposition performs jointly channel estimation and radio resource sharing. We validate the fruitfulness of the proposed MAC and we evaluate the effects of the channel estimation on the network performance. We then present an accurate analytical model for the performance of IEEE 802.11 MAC protocol. We extend the latter model, by introducing the fading probability, to derive the saturation throughput for our proposed MAC when the simplest beamforming strategy is used in real multipath fading ad hoc networks. Finally, numerical results validate our proposition.

  3. God, Sport Philosophy, Kinesiology: A MacIntyrean Examination

    Science.gov (United States)

    Twietmeyer, Gregg

    2015-01-01

    Sport philosophy is in crisis. This subdiscipline of kinesiology garners little to no respect and few tenure track lines in kinesiology departments. Why is this the case? Why isn't philosophy held in greater esteem? Is it possible that philosopher Alasdair MacIntyre's (2009) diagnosis found in "God, Philosophy, Universities" could…

  4. MAC Support for High Density Wireless Sensor Networks

    NARCIS (Netherlands)

    Taddia, C.; Meratnia, Nirvana; van Hoesel, L.F.W.; Mazzini, G.; Havinga, Paul J.M.

    Large scale and high density networks of tiny sensor nodes offer promising solutions for event detection and actuating applications. In this paper we address the effect of high density of wireless sensor network performance with a specific MAC protocol, the Lightweight Medium Access Control (LMAC).

  5. God, Sport Philosophy, Kinesiology: A MacIntyrean Examination

    Science.gov (United States)

    Twietmeyer, Gregg

    2015-01-01

    Sport philosophy is in crisis. This subdiscipline of kinesiology garners little to no respect and few tenure track lines in kinesiology departments. Why is this the case? Why isn't philosophy held in greater esteem? Is it possible that philosopher Alasdair MacIntyre's (2009) diagnosis found in "God, Philosophy, Universities" could…

  6. Dual diagnosis

    OpenAIRE

    2013-01-01

    Dual diagnosis denotes intertwining of intellectual disabilities with mental disorders. With the help of systematic examination of literature, intellectual disabilities are determined (they are characterized by subaverage intellectual activity and difficulties in adaptive skills), along side mental disorders. Their influence is seen in changes of thinking, perception, emotionality, behaviour and cognition. Mental disorders often occur with people with intellectual disabilities (data differs f...

  7. Roles of Mac-1 and glycoprotein IIb/IIIa integrins in leukocyte-platelet aggregate formation: stabilization by Mac-1 and inhibition by GpIIb/IIIa blockers.

    Science.gov (United States)

    Patko, Zsofia; Csaszar, Albert; Acsady, Gyorgy; Peter, Karlheinz; Schwarz, Meike

    2012-01-01

    Circulating platelet-leukocyte hetero-aggregates play an important role in acute cardiovascular events and hypersensitivity reactions. The association involves the receptor families of selectins and integrin. The objective of this study was to investigate the role of CD11b/CD18 integrin (Mac-1) in hetero-aggregate formation and search for a counter-receptor on platelets ready to interact with Mac-1. As a model of leukocytes, Mac-1 presenting Chinese hamster ovary (CHO) cells were used to evaluate the role of Mac-1 in hetero-aggregate formation. The amount of CHO cell-bound active and inactive platelets was measured by flow cytometry, while the counter-receptors on platelets were identified via using blocking antibodies. We observed significant platelet adhesion on Mac-1-bearing cells when platelet-rich plasma or activated platelets were present. Inactive platelets did not adhere to Mac-1-bearing cells. Addition of fibrinogen, a ligand of Mac-1 significantly increased platelet binding. CD40L was demonstrated to act similarly on Mac-1. Inhibition of platelet GpIIb/IIIa completely abolished CHO cell-platelet aggregation. In our study, we have shown for the first time that Mac-1 mediates the formation of hetero-aggregates without selectin tethering when Mac-1 ligands such as fibrinogen or CD40L are present and blockers of platelet GpIIb/IIIa are able to diminish this interaction.

  8. Pyrogen testing of lipid-based TPN using Mono Mac 6 monocyte cell line and DELFIA

    DEFF Research Database (Denmark)

    Moesby, Lise; Hansen, E W; Christensen, J D

    1997-01-01

    Measurement of lipopolysaccharide (LPS) induced interleukin-6 (IL-6) secretion in Mono Mac 6 cells.......Measurement of lipopolysaccharide (LPS) induced interleukin-6 (IL-6) secretion in Mono Mac 6 cells....

  9. The ISS Water Processor Catalytic Reactor as a Post Processor for Advanced Water Reclamation Systems

    Science.gov (United States)

    Nalette, Tim; Snowdon, Doug; Pickering, Karen D.; Callahan, Michael

    2007-01-01

    Advanced water processors being developed for NASA s Exploration Initiative rely on phase change technologies and/or biological processes as the primary means of water reclamation. As a result of the phase change, volatile compounds will also be transported into the distillate product stream. The catalytic reactor assembly used in the International Space Station (ISS) water processor assembly, referred to as Volatile Removal Assembly (VRA), has demonstrated high efficiency oxidation of many of these volatile contaminants, such as low molecular weight alcohols and acetic acid, and is considered a viable post treatment system for all advanced water processors. To support this investigation, two ersatz solutions were defined to be used for further evaluation of the VRA. The first solution was developed as part of an internal research and development project at Hamilton Sundstrand (HS) and is based primarily on ISS experience related to the development of the VRA. The second ersatz solution was defined by NASA in support of a study contract to Hamilton Sundstrand to evaluate the VRA as a potential post processor for the Cascade Distillation system being developed by Honeywell. This second ersatz solution contains several low molecular weight alcohols, organic acids, and several inorganic species. A range of residence times, oxygen concentrations and operating temperatures have been studied with both ersatz solutions to provide addition performance capability of the VRA catalyst.

  10. Retargetable Code Generation based on Structural Processor Descriptions

    OpenAIRE

    Leupers, Rainer; Marwedel, Peter

    1998-01-01

    Design automation for embedded systems comprising both hardware and software components demands for code generators integrated into electronic CAD systems. These code generators provide the necessary link between software synthesis tools in HW/SW codesign systems and embedded processors. General-purpose compilers for standard processors are often insufficient, because they do not provide flexibility with respect to different target processors and also suffer from inferior code quality....

  11. User microprogrammable processors for high data rate telemetry preprocessing

    Science.gov (United States)

    Pugsley, J. H.; Ogrady, E. P.

    1973-01-01

    The use of microprogrammable processors for the preprocessing of high data rate satellite telemetry is investigated. The following topics are discussed along with supporting studies: (1) evaluation of commercial microprogrammable minicomputers for telemetry preprocessing tasks; (2) microinstruction sets for telemetry preprocessing; and (3) the use of multiple minicomputers to achieve high data processing. The simulation of small microprogrammed processors is discussed along with examples of microprogrammed processors.

  12. Latency-information theory and applications: Part I. On the discovery of the time dual for information theory

    Science.gov (United States)

    Feria, Erlan H.

    2008-04-01

    As part of research conducted on the design of an efficient clutter covariance processor for DARPA's knowledge aided sensor signal processing expert reasoning (KASSPER) program a time-dual for information theory was discovered and named latency theory, this theory is discussed in this first of a multi-paper series. While information theory addresses the design of communication systems, latency theory does the same for recognition systems. Recognition system is the name given to the time dual of a communication system. A recognition system uses prior-knowledge about a signal-processor's input to enable the sensing of its output by a processing-time limited sensor when the fastest possible signal-processor replacement cannot achieve this task. A processor-coder is the time dual of a source coder. While a source coder replaces a signal-source to yield a smaller sourced-space in binary digits (bits) units a processor coder replaces a signal-processor to yield a smaller processing-time in binary operators (bors) units. A sensor coder is the time dual of a channel coder. While a channel coder identifies the necessary overhead-knowledge for accurate communications a sensor coder identifies the necessary prior-knowledge for accurate recognitions. In the second of this multipaper series latency theory is successfully illustrated with real-world knowledge aided radar.

  13. MAC: identifying and correcting annotation for multi-nucleotide variations.

    Science.gov (United States)

    Wei, Lei; Liu, Lu T; Conroy, Jacob R; Hu, Qiang; Conroy, Jeffrey M; Morrison, Carl D; Johnson, Candace S; Wang, Jianmin; Liu, Song

    2015-08-01

    Next-Generation Sequencing (NGS) technologies have rapidly advanced our understanding of human variation in cancer. To accurately translate the raw sequencing data into practical knowledge, annotation tools, algorithms and pipelines must be developed that keep pace with the rapidly evolving technology. Currently, a challenge exists in accurately annotating multi-nucleotide variants (MNVs). These tandem substitutions, when affecting multiple nucleotides within a single protein codon of a gene, result in a translated amino acid involving all nucleotides in that codon. Most existing variant callers report a MNV as individual single-nucleotide variants (SNVs), often resulting in multiple triplet codon sequences and incorrect amino acid predictions. To correct potentially misannotated MNVs among reported SNVs, a primary challenge resides in haplotype phasing which is to determine whether the neighboring SNVs are co-located on the same chromosome. Here we describe MAC (Multi-Nucleotide Variant Annotation Corrector), an integrative pipeline developed to correct potentially mis-annotated MNVs. MAC was designed as an application that only requires a SNV file and the matching BAM file as data inputs. Using an example data set containing 3024 SNVs and the corresponding whole-genome sequencing BAM files, we show that MAC identified eight potentially mis-annotated SNVs, and accurately updated the amino acid predictions for seven of the variant calls. MAC can identify and correct amino acid predictions that result from MNVs affecting multiple nucleotides within a single protein codon, which cannot be handled by most existing SNV-based variant pipelines. The MAC software is freely available and represents a useful tool for the accurate translation of genomic sequence to protein function.

  14. Generation of MAC waves by convection in Earth's core

    Science.gov (United States)

    Jaupart, Etienne; Buffett, Bruce

    2017-05-01

    Convection in Earth's core is a viable mechanism for generating MAC waves when the top of the core is stably stratified. We quantify the generation mechanism by extending the physical description of MAC waves to include a source term due to buoyancy forces in the convecting part of the core. Solutions for the forced motion are obtained using a Green's function, which is constructed from the eigenfunctions for the unforced motion. When the source term is evaluated using the output of a numerical geodynamo model, the largest excitation occurs at even spherical harmonic degrees, corresponding to waves with symmetric azimuthal flow about the equator. We also find that the magnitude of the source term decreases at periods shorter than about 60 yr. As a result most of the wave generation is confined to waves with periods of 60 yr or longer. Quantitative predictions for the wave amplitudes depend on the projection of the source term into the eigenfunction of the waves. Strong stratification limits the penetration of density anomalies into the stratified layer, which means that the source term is confined to the lowermost part of the layer. Overtones of MAC waves with large amplitudes in the lower part of the stratified layer are more effectively generated by convection, even though these waves are heavily damped by magnetic diffusion. Generation of MAC waves by convection establishes a physical link between observable wave motion and deeper convective processes. Detection of changes in the amplitude and phase of MAC waves would constrain the generation processes and offer insights into the nature of the convection.

  15. 42 CFR 405.1110 - MAC reviews on its own motion.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false MAC reviews on its own motion. 405.1110 Section 405....1110 MAC reviews on its own motion. (a) General rule. The MAC may decide on its own motion to review a decision or dismissal issued by an ALJ. CMS or any of its contractors may refer a case to the MAC for it to...

  16. Minimum Alveolar Concentration for Blunting Adrenergic Responses (MAC-BAR) of Sevoflurane in Dogs

    OpenAIRE

    YAMASHITA, Kazuto; FURUKAWA, Erika; ITAMI, Takaharu; ISHIZUKA, Tomohito; TAMURA, Jun; MIYOSHI, Kenjirou

    2012-01-01

    It is well known that heart rate or arterial blood pressure may increase in response to surgical stimulation despite the absence of a purposeful movement. However, there is limited information regarding anesthetic requirement for blunting adrenergic response in dogs. This study was designed to compare the minimum alveolar concentrations of sevoflurane required to prevent autonomic response (MAC-BAR) and purposeful movement (MAC) in dogs. Sevoflurane MAC-BAR and MAC were determined in 5 beagle...

  17. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...

  18. Dynamically Reconfigurable Processor for Floating Point Arithmetic

    Directory of Open Access Journals (Sweden)

    S. Anbumani,

    2014-01-01

    Full Text Available Recently, development of embedded processors is toward miniaturization and energy saving for ecology. On the other hand, high performance arithmetic circuits are required in a lot of application in science and technology. Dynamically reconfigurable processors have been developed to meet these requests. They can change circuit configuration according to instructions in program instantly during operations.This paper describes, a dynamically reconfigurable circuit for floating-point arithmetic is proposed. The arithmetic circuit consists of two single precision floating-point arithmetic circuits. It performs double precision floating-point arithmetic by reconfiguration. Dynamic reconfiguration changes circuit construction at one clock cycle during operation without stopping circuits. It enables reconfiguration of circuits in a few nano seconds. The proposed circuit is reconfigured in two modes. In first mode it performs one double precision floating-point arithmetic or else the circuit will perform two parallel operations of single precision floating-point arithmetic. The new system design reduces implementation area by reconfiguring common parts of each operation. It also increases the processing speed with a very little number of clocks.

  19. Bilinear Interpolation Image Scaling Processor for VLSI

    Directory of Open Access Journals (Sweden)

    Ms. Pawar Ashwini Dilip

    2014-05-01

    Full Text Available We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCUis invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 μm2 synthesized by a 0.13-μm CMOS process

  20. Speed Scaling on Parallel Processors with Migration

    CERN Document Server

    Angel, Eric; Kacem, Fadi; Letsios, Dimitrios

    2011-01-01

    We study the problem of scheduling a set of jobs with release dates, deadlines and processing requirements (or works), on parallel speed-scaled processors so as to minimize the total energy consumption. We consider that both preemption and migration of jobs are allowed. An exact polynomial-time algorithm has been proposed for this problem, which is based on the Ellipsoid algorithm. Here, we formulate the problem as a convex program and we propose a simpler polynomial-time combinatorial algorithm which is based on a reduction to the maximum flow problem. Our algorithm runs in $O(nf(n)logP)$ time, where $n$ is the number of jobs, $P$ is the range of all possible values of processors' speeds divided by the desired accuracy and $f(n)$ is the complexity of computing a maximum flow in a layered graph with O(n) vertices. Independently, Albers et al. \\cite{AAG11} proposed an $O(n^2f(n))$-time algorithm exploiting the same relation with the maximum flow problem. We extend our algorithm to the multiprocessor speed scal...

  1. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  2. Broadband monitoring simulation with massively parallel processors

    Science.gov (United States)

    Trubetskov, Mikhail; Amotchkina, Tatiana; Tikhonravov, Alexander

    2011-09-01

    Modern efficient optimization techniques, namely needle optimization and gradual evolution, enable one to design optical coatings of any type. Even more, these techniques allow obtaining multiple solutions with close spectral characteristics. It is important, therefore, to develop software tools that can allow one to choose a practically optimal solution from a wide variety of possible theoretical designs. A practically optimal solution provides the highest production yield when optical coating is manufactured. Computational manufacturing is a low-cost tool for choosing a practically optimal solution. The theory of probability predicts that reliable production yield estimations require many hundreds or even thousands of computational manufacturing experiments. As a result reliable estimation of the production yield may require too much computational time. The most time-consuming operation is calculation of the discrepancy function used by a broadband monitoring algorithm. This function is formed by a sum of terms over wavelength grid. These terms can be computed simultaneously in different threads of computations which opens great opportunities for parallelization of computations. Multi-core and multi-processor systems can provide accelerations up to several times. Additional potential for further acceleration of computations is connected with using Graphics Processing Units (GPU). A modern GPU consists of hundreds of massively parallel processors and is capable to perform floating-point operations efficiently.

  3. The ATLAS Level-1 Central Trigger Processor

    CERN Document Server

    Pauly, T; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Spiwoks, R; Torga-Teixeira, R; Wengler, T; 14th IEEE-NPSS Real Time Conference 2005

    2005-01-01

    ATLAS is a multi-purpose particle physics detector at CERN’s Large Hadron Collider where two pulsed beams of protons are brought to collision at very high energy. There are collisions every 25 ns, corresponding to a rate of 40 MHz. A three-level trigger system reduces this rate to about 200 Hz while keeping bunch crossings which potentially contain interesting processes. The Level-1 trigger, implemented in electronics and firmware, makes an initial selection in under 2.5 us with an output rate of less than 100 kHz. A key element of this is the Central Trigger Processor (CTP) which combines trigger information from the calorimeter and muon trigger processors to make the final Level-1 accept decision in under 100 ns on the basis of lists of selection criteria, implemented as a trigger menu. Timing and trigger signals are fanned out to all sub-detectors, while busy signals from all sub-detector read-out systems are collected and fed into the CTP in order to throttle the generation of Level-1 triggers.

  4. MDS-Mac: a scheduled MAC for localization, time-synchronisation and communication in underwater acoustic networks

    NARCIS (Netherlands)

    Kleunen, van Wouter; Meratnia, Nirvana; Havinga, Paul J.M.

    2012-01-01

    In this paper we describe a design for an underwater MAC protocol which combines localization, time-synchronisation and communication. This protocol is designed for small-scale clustered networks in which all nodes are able to ommunicate with each other. We consider an integrated design of localizat

  5. TR-MAC: an energy-efficient MAC protocol for wireless sensor networks exploiting noise-based transmitted reference modulation

    NARCIS (Netherlands)

    Morshed, S.; Dimitrova, D.C.; Brogle, M.; Braun, T.; Heijenk, Gerhard J.

    Energy-constrained behavior of sensor nodes is one of the most important criteria for successful deployment of wireless sensor net- works. The medium access control (MAC) protocol determines the time a sensor node transceiver spends listening or transmitting, and hence the energy consumption of the

  6. Library Signage: Applications for the Apple Macintosh and MacPaint.

    Science.gov (United States)

    Diskin, Jill A.; FitzGerald, Patricia

    1984-01-01

    Describes specific applications of the Macintosh computer at Carnegie-Mellon University Libraries, where MacPaint was used as a flexible, easy to use, and powerful tool to produce informational, instructional, and promotional signage. Profiles of system hardware and software, an evaluation of the computer program MacPaint, and MacPaint signage…

  7. 42 CFR 405.1050 - Removal of a hearing request from an ALJ to the MAC.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Removal of a hearing request from an ALJ to the MAC... Removal of a hearing request from an ALJ to the MAC. If a request for hearing is pending before an ALJ, the MAC may assume responsibility for holding a hearing by requesting that the ALJ send the hearing...

  8. 42 CFR 405.1108 - MAC actions when request for review or escalation is filed.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false MAC actions when request for review or escalation...) Medicare Appeals Council Review § 405.1108 MAC actions when request for review or escalation is filed. (a) Except as specified in paragraphs (c) and (d) of this section, when a party requests that the MAC review...

  9. Traffic-adaptive duty cycle adaptation in TR-MAC protocol for wireless sensor networks

    NARCIS (Netherlands)

    Morshed, Sarwar; Baratchi, Mitra; Heijenk, Geert

    2016-01-01

    The Medium Access Control (MAC) layer can influence the energy consumption of a wireless sensor network (WSN) to a significant level. TR-MAC is an energy-efficient preamble sampling based MAC protocol for low power WSNs suitable for low data rate and low duty cycle scenario. However, low data rate i

  10. 42 CFR 405.1102 - Request for MAC review when ALJ issues decision or dismissal.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 2 2010-10-01 2010-10-01 false Request for MAC review when ALJ issues decision or...) Medicare Appeals Council Review § 405.1102 Request for MAC review when ALJ issues decision or dismissal. (a)(1) A party to the ALJ hearing may request a MAC review if the party files a written request for...

  11. The use of digital signal processors (DSPs) in real-time processing of multi-parametric bioelectronic signals.

    Science.gov (United States)

    Ressler, Johann; Dirscherl, Andreas; Grothe, Helmut; Wolf, Bernhard

    2007-02-01

    In many cases of bioanalytical measurement, calculation of large amounts of data, analysis of complex signal waveforms or signal speed can overwhelm the performance of microcontrollers, analog electronic circuits or even PCs. One method to obtain results in real time is to apply a digital signal processor (DSP) for the analysis or processing of measurement data. In this paper we show how DSP-supported multiplying and accumulating (MAC) operations, such as time/frequency transformation, pattern recognition by correlation, convolution or filter algorithms, can optimize the processing of bioanalytical data. Discrete integral calculations are applied to the acquisition of impedance values as part of multi-parametric sensor chips, to pH monitoring using light-addressable potentiometric sensors (LAPS) and to the analysis of rapidly changing signal shapes, such as action potentials of cultured neuronal networks, as examples of DSP capability.

  12. QCD Dual

    DEFF Research Database (Denmark)

    Sannino, Francesco

    2009-01-01

    We uncover a novel solution of the 't Hooft anomaly matching conditions for QCD. Interestingly in the perturbative regime the new gauge theory, if interpreted as a possible QCD dual, predicts the critical number of flavors above which QCD in the nonperturbative regime, develops an infrared stable...... fixed point. Remarkably this value is identical to the maximum bound predicted in the nonpertubative regime via the all-orders conjectured beta function for nonsupersymmetric gauge theories.......We uncover a novel solution of the 't Hooft anomaly matching conditions for QCD. Interestingly in the perturbative regime the new gauge theory, if interpreted as a possible QCD dual, predicts the critical number of flavors above which QCD in the nonperturbative regime, develops an infrared stable...

  13. The minimum alveolar concentration (MAC) and hemodynamic effects of halothane, isoflurane, and sevoflurane in newborn swine.

    Science.gov (United States)

    Lerman, J; Oyston, J P; Gallagher, T M; Miyasaka, K; Volgyesi, G A; Burrows, F A

    1990-10-01

    To determine the minimum alveolar concentration (MAC) and hemodynamic responses to halothane, isoflurane, and sevoflurane in newborn swine, 36 fasting swine 4-10 days of age were anesthetized with one of the three volatile anesthetics in 100% oxygen. MAC was determined for each swine. Carotid artery and internal jugular catheters were inserted and each swine was allowed to recover for 48 h. After recovery, heart rate (HR), systemic systolic arterial pressure (SAP), and cardiac index (CI) were measured awake and then at 0.5, 1.0, and 1.5 MAC of the designated anesthetic in random sequence. The (mean +/- SD) MAC for halothane was 0.90 +/- 0.12%; the MAC for isoflurane was 1.48 +/- 0.21%; and the MAC for sevoflurane was 2.12 +/- 0.39%. Awake (mean +/- SD) measurements of HR, SAP, and CI did not differ significantly among the three groups. Compared to the awake HR, the mean HR decreased 35% at 1.5 MAC halothane (P less than 0.001), 19% at 1.5 MAC isoflurane (P less than 0.005), and 31% at 1.5 MAC sevoflurane (P less than 0.005). Compared to awake SAP, mean SAP measurements decreased 46% at 1.5 MAC halothane (P less than 0.001), 43% at 1.5 MAC isoflurane (P less than 0.001), and 36% at 1.5 MAC sevoflurane (P less than 0.005). Mean SAP at 1.0 and 1.5 MAC halothane and isoflurane were significantly less than those measured at equipotent concentrations of sevoflurane (P less than 0.005). Compared to awake CI, mean CI measurements decreased 53% at 1.5 MAC halothane (P less than 0.001) and 43% at 1.5 MAC isoflurane (P less than 0.005).(ABSTRACT TRUNCATED AT 250 WORDS)

  14. MAC-awake of isoflurane, enflurane and halothane evaluated by slow and fast alveolar washout.

    Science.gov (United States)

    Gaumann, D M; Mustaki, J P; Tassonyi, E

    1992-01-01

    End-tidal anaesthetic concentrations at first eye opening in response to a verbal command during recovery from anaesthesia (MAC-awake), were measured for isoflurane (n = 16), enflurane (n = 16) and halothane (n = 14). MAC-awake was measured during either slow or fast alveolar washout. Slow washout was obtained by decreasing anaesthetic concentrations in predetermined steps of 15 min, assuming equilibration between brain and alveolar partial pressures. Fast alveolar washout was obtained by discontinuation of the inhalation anaesthetic, which had been maintained at 1 MAC for at least 15 min. Mean MAC-awake obtained with slow alveolar washout was similar for isoflurane (0.25 (SD 0.03) MAC), and enflurane (0.27 (0.04) MAC) and significantly greater than values obtained by fast alveolar washout (isoflurane: 0.19 (0.03) MAC; enflurane: 0.20 (0.03) MAC). The MAC-awake of isoflurane and enflurane was significantly less than that of halothane, which was 0.59 (0.10) MAC as evaluated by the slow and 0.50 (0.05) MAC as evaluated by the fast alveolar washout method. Recovery time from anaesthesia with fast alveolar washout was 8.8 (4.0) min for halothane, which was not different from isoflurane (15 (2.5) min), but significantly shorter than for enflurane (22 (10) min), reflecting differences in the anaesthetic concentration gradient between MAC and MAC-awake values. These data do not support the hypothesis of a uniform ratio between MAC and MAC-awake values.

  15. Una lectura interpretativa de Tras la virtud, de Alasdair MacIntyre - An Interpretive Reading of After Virtue, by Alasdair MacIntyre

    Directory of Open Access Journals (Sweden)

    Fernando Fernández-Llebrez

    2010-12-01

    Full Text Available This article centers on the thought of Alasdair MacIntyre, whose most prominente work, After Virtue, is considered a classic of political science. In contrast with other reviews, this article will examine After Virtue within the broader context of MacIntyre’s thinking and publications. An overview of MacIntyre’s literary corpus and the evolution of his thinking will shed light on the volume examined and trace certain ideas that are characteristic of this Scottish political philosopher. Matters that remained unsettled in After Virtue have become over time more defined in MacIntyre’s thinking, such as the influence exerted upon him by Thomas Aquinas.

  16. Distinguishing and Second-Preimage Attacks on CBC-Like MACs

    Science.gov (United States)

    Jia, Keting; Wang, Xiaoyun; Yuan, Zheng; Xu, Guangwu

    This paper first presents a new distinguishing attack on the CBC-MAC structure based on block ciphers in cipher block chaining (CBC) mode. This attack detects a CBC-like MAC from random functions. The second result of this paper is a second-preimage attack on the CBC-MAC, which is an extension of the attack of Brincat and Mitchell. The attack also covers MT-MAC, PMAC and MACs with three-key enciphered CBC mode. Instead of exhaustive search, both types of attacks are of birthday attack complexity.

  17. GA103 a microprogrammable processor for online filtering

    CERN Document Server

    Calzas, A; Danon, G

    1981-01-01

    GA103 is a 16 bit microprogrammable processor, which emulates the PDP 11 instruction set. It is based on the Am2900 slices. It allows user- implemented microinstructions and addition of hardwired processors. It will perform online filtering tasks in the NA14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (3 refs).

  18. Expert System Constant False Alarm Rate (CFAR) Processor

    Science.gov (United States)

    2006-09-01

    Processor has been developed on a Sun Sparc Station 4/470 using a commercial-off-the-shelf software development package called G2 by Gensym Corporation...size of the training data set. A prototype expert system CFAR Processor has been presented which applies artificial intelligence to CFAR detection

  19. Digital Signal Processor System for AC Power Drivers

    OpenAIRE

    Ovidiu Neamtu

    2009-01-01

    DSP (Digital Signal Processor) is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulation)circuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  20. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  1. High speed matrix processors using floating point representation

    Energy Technology Data Exchange (ETDEWEB)

    Birkner, D.A.

    1980-01-01

    The author describes the architecture of a high-speed matrix processor which uses a floating-point format for data representation. It is shown how multipliers and other LSI devices are used in the design to obtain the high speed of the processor.

  2. Temporal Partitioning and Multi-Processor Scheduling for Reconfigurable Architectures

    DEFF Research Database (Denmark)

    Popp, Andreas; Le Moullec, Yannick; Koch, Peter

    This poster presentation outlines a proposed framework for handling mapping of signal processing applications to heterogeneous reconfigurable architectures. The methodology consists of an extension to traditional multi-processor scheduling by creating a separate HW track for generation of groups...... of tasks that are handled similarly to SW processes in a traditional multi-processor scheduling context....

  3. Message Passing on a Time-predictable Multicore Processor

    DEFF Research Database (Denmark)

    Sørensen, Rasmus Bo; Puffitsch, Wolfgang; Schoeberl, Martin

    2015-01-01

    Real-time systems need time-predictable computing platforms. For a multicore processor to be time-predictable, communication between processor cores needs to be time-predictable as well. This paper presents a time-predictable message-passing library for such a platform. We show how to build up...

  4. A Simple and Affordable TTL Processor for the Classroom

    Science.gov (United States)

    Feinberg, Dave

    2007-01-01

    This paper presents a simple 4 bit computer processor design that may be built using TTL chips for less than $65. In addition to describing the processor itself in detail, we discuss our experience using the laboratory kit and its associated machine instruction set to teach computer architecture to high school students. (Contains 3 figures and 5…

  5. Bibliographic Pattern Matching Using the ICL Distributed Array Processor.

    Science.gov (United States)

    Carroll, David M.; And Others

    1988-01-01

    Describes the use of a highly parallel array processor for pattern matching operations in a bibliographic retrieval system. The discussion covers the hardware and software features of the processor, the pattern matching algorithm used, and the results of experimental tests of the system. (37 references) (Author/CLB)

  6. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, Anja; Wester, Rinse; Rovers, Kenneth; Baaij, Christiaan; Kuper, Jan; Smit, Gerard

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  7. Signal Processor for Spring8 Linac BPM

    CERN Document Server

    Yanagida, K; Dewa, H; Hanaki, H; Hori, T; Kobayashi, T; Mizuno, A; Sasaki, S; Suzuki, S; Takashima, T; Taniushi, T; Tomizawa, H

    2001-01-01

    A signal processor of the single shot BPM system consists of a narrow-band BPF unit, a detector unit, a P/H circuit, an S/H IC and a 16-bit ADC. The BPF unit extracts a pure 2856MHz RF signal component from a BPM and makes the pulse width longer than 100ns. The detector unit that includes a demodulating logarithmic amplifier is used to detect an S-band RF amplitude. A wide dynamic range of beam current has been achieved; 0.01 ~ 3.5nC for below 100ns input pulse width, or 0.06 ~ 20mA for above 100ns input pulse width. The maximum acquisition rate with a VME system has been achieved up to 1kHz.

  8. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-05-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  9. Scaling the ion trap quantum processor.

    Science.gov (United States)

    Monroe, C; Kim, J

    2013-03-08

    Trapped atomic ions are standards for quantum information processing, serving as quantum memories, hosts of quantum gates in quantum computers and simulators, and nodes of quantum communication networks. Quantum bits based on trapped ions enjoy a rare combination of attributes: They have exquisite coherence properties, they can be prepared and measured with nearly 100% efficiency, and they are readily entangled with each other through the Coulomb interaction or remote photonic interconnects. The outstanding challenge is the scaling of trapped ions to hundreds or thousands of qubits and beyond, at which scale quantum processors can outperform their classical counterparts in certain applications. We review the latest progress and prospects in that effort, with the promise of advanced architectures and new technologies, such as microfabricated ion traps and integrated photonics.

  10. Efficient quantum walk on a quantum processor.

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L; Wang, Jingbo B; Matthews, Jonathan C F

    2016-05-05

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor.

  11. Water Processor and Oxygen Generation Assembly

    Science.gov (United States)

    Bedard, John

    1997-01-01

    This report documents the results of the tasks which initiated efforts on design issues relating to the Water Processor (WP) and the Oxygen Generation Assembly (OGA) Flight Hardware for the International Space Station. This report fulfills the Statement of Work deliverables requirement for contract H-29387D. The following lists the tasks required by contract H-29387D: (1) HSSSI shall coordinate a detailed review of WP/OGA Flight Hardware program requirements with personnel from MSFC to identify requirements that can be eliminated without affecting the technical integrity of the WP/OGA Hardware; (2) HSSSI shall conduct the technical interchanges with personnel from MSFC to resolve design issues related to WP/OGA Flight Hardware; (3) HSSSI will initiate discussions with Zellwegger Analytics, Inc. to address design issues related to WP and PCWQM interfaces.

  12. Face feature processor on mobile service robot

    Science.gov (United States)

    Ahn, Ho Seok; Park, Myoung Soo; Na, Jin Hee; Choi, Jin Young

    2005-12-01

    In recent years, many mobile service robots have been developed. These robots are different from industrial robots. Service robots were confronted to unexpected changes in the human environment. So many capabilities were needed to service mobile robot, for example, the capability to recognize people's face and voice, the capability to understand people's conversation, and the capability to express the robot's thinking etc. This research considered face detection, face tracking and face recognition from continuous camera image. For face detection module, it used CBCH algorithm using openCV library from Intel Corporation. For face tracking module, it used the fuzzy controller to control the pan-tilt camera movement smoothly with face detection result. A PCA-FX, which adds class information to PCA, was used for face recognition module. These three procedures were called face feature processor, which were implemented on mobile service robot OMR to verify.

  13. Building custom processors with Handel-C

    CERN Document Server

    Lokier, J

    1999-01-01

    Triggering and data acquisition for the ATLAS LHC experiment requires state of the art computer hardware. Amongst other things, specialised processors may be required. To build these economically we are looking at reconfigurable computing, and a high-level hardware description language: Handel-C. We had previously implemented a specialised network hardware application in AHDL-a hardware description at the level of gates, flip-flops and state machines. As a feasibility study, we have rewritten the application in Handel-C -a language similar to C, except that it can be translated into hardware. There were problems to solve: high data throughput with complex pipelines; timing constraints; I/O interfaces to external devices; difficulties with the Altera devices. We gained valuable experience, wrote useful support tools, and discovered clean new ways to make the most of the language in the high-speed domain. (0 refs).

  14. Conversion via software of a simd processor into a mimd processor

    Energy Technology Data Exchange (ETDEWEB)

    Guzman, A.; Gerzso, M.; Norkin, K.B.; Vilenkin, S.Y.

    1983-01-01

    A method is described which takes a pure LISP program and automatically decomposes it via automatic parallelization into several parts, one for each processor of an SIMD architecture. Each of these parts is a different execution flow, i.e., a different program. The execution of these different programs by an SIMD architecture is examined. The method has been developed in some detail for the PS-2000, an SIMD Soviet multiprocessor, making it behave like AHR, a Mexican MIMD multi-microprocessor. Both the PS-2000 and AHR execute a pure LISP program in parallel; its decomposition into >n> pieces, their synchronization, scheduling, etc., are performed by the system (hardware and software). In order to achieve simultaneous execution of different programs in an SIMD processor, the method uses a scheme of node scheduling and node exportation. 14 references.

  15. Magnetic activated cell sorting (MACS): utility in assisted reproduction.

    Science.gov (United States)

    Makker, Kartikeya; Agarwal, Ashok; Sharma, Rakesh K

    2008-07-01

    Assisted reproductive techniques (ART) have now been extensively incorporated in the management of infertile couples. But even after rapid methodological and technological advances the success rates of these procedures have been below expectations. This has led to development of many sperm preparation protocols to obtain an ideal semen sample for artificial reproduction. Sperm apoptosis has been heavily linked to failures in reproductive techniques. One of the earliest changes shown by apoptotic spermatozoa is externalization of phosphatidyl serine. Magnetic activated cell sorting (MACS) is a novel sperm preparation technique that separates apoptotic and non-apoptotic spermatozoa based on the expression of phosphatidylserine. This has led to the incorporation of MACS as a sperm preparation technique. The review highlights the principle and mechanism of this novel technique and enumerates its advantages as a sperm preparation technique. Its utility in ART as an efficient tool for sperm recovery and its application in cryopreservation of semen samples is also explained.

  16. Secure MAC for Wireless Sensor Networks through RBFNN

    Directory of Open Access Journals (Sweden)

    P.Sankara Rao

    2010-08-01

    Full Text Available This paper discusses an application of a neural network in wireless sensor network security. It presents a Radial Basic Function Neural Network based media access control protocol (MAC to secure a CSMA-based wireless sensor network against the denial-of-service attacks launched by adversaries. The Radial Basic Function Neural Network enhances the security of a WSN by constantly monitoring the parameters that exhibit unusual variations in case of an attack. The RBFN shuts down the MAC layer and the physical layer of the sensor node when the suspicion factor, the output of the MLP, exceeds a preset threshold level. The MLP-guarded secure WSN is implemented using the Prowler simulator. Simulation results show that the MLP helps in extending the lifetime of the WSN.

  17. On the Development of Low Power MAC Protocol for WBANs

    CERN Document Server

    Ullah, Sana; Kwak, Kyung Sup

    2009-01-01

    Current advances in wireless communication, microelectronics, semiconductor technologies, and intelligent sensors have contributed to the development of unobtrusive WBANs. These networks provide long term health monitoring of patients without any constraint in their normal activities. Traditional MAC protocols do not accommodate the assorted WBAN traffic requirements in a power efficient manner. In this paper, we present a brief discussion on the development process of a low power MAC protocol for WBANs. We observe the behavior of a beacon-enabled IEEE 802.15.4 for on-body sensor networks. We further propose a low power technique called traffic based wakeup mechanism for a WBAN that exploits the traffic patterns of the BAN Nodes to ensure power efficient and reliable communication.

  18. Activity Modelling and Comparative Evaluation of WSN MAC Security Attacks

    DEFF Research Database (Denmark)

    Pawar, Pranav M.; Nielsen, Rasmus Hjorth; Prasad, Neeli R.

    2012-01-01

    and initiate security attacks that disturb the normal functioning of the network in a severe manner. Such attacks affect the performance of the network by increasing the energy consumption, by reducing throughput and by inducing long delays. Of all existing WSN attacks, MAC layer attacks are considered....... The second aim of the paper is to simulate these attacks on hybrid MAC mechanisms, which shows the performance degradation of aWSN under the considered attacks. The modelling and implementation of the security attacks give an actual view of the network which can be useful in further investigating secure......Applications of wireless sensor networks (WSNs) are growing tremendously in the domains of habitat, tele-health, industry monitoring, vehicular networks, home automation and agriculture. This trend is a strong motivation for malicious users to increase their focus on WSNs and to develop...

  19. Floating-point processor for INTEL 8080A microprocessor systems

    Energy Technology Data Exchange (ETDEWEB)

    Bairstow, R.; Barlow, J.; Jires, M.; Waters, M.

    1982-03-01

    An A.M.D. 9511 Floating Point Processor has been interfaced to the Rutherford Laboratory Bubble Chamber Group's microcomputers. These computers are based on the INTEL 8080A microprocessor. The interface uses a memory mapped I/O technique to ensure rapid transfer of arguments between processors. The A.M.D. 9511 acts as a slave processor to the INTEL 8080A system. The 8080 processor is held in WAIT status until completion of the A.M.D. operation. A software Macro Processor has been written to effectively extend the basic INTEL 8080A instruction set to include the full range of A.M.D. 9511 instructions.

  20. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  1. An Efficient Graph-Coloring Algorithm for Processor Allocation

    Directory of Open Access Journals (Sweden)

    Mohammed Hasan Mahafzah

    2013-06-01

    Full Text Available This paper develops an efficient exact graph-coloring algorithm based on Maximum Independent Set (MIS for allocating processors in distributed systems. This technique represents the allocated processors in specific time in a fully connected graph and prevents each processor in multiprocessor system to be assigned to more than one process at a time. This research uses a sequential technique to distribute processes among processors. Moreover, the proposed method has been constructed by modifying the FMIS algorithm. The proposed algorithm has been programmed in Visual C++ and implemented on an Intel core i7. The experiments show that the proposed algorithm gets better performance in terms of CPU utilization, and minimum time for of graph coloring, comparing with the latest FMIS algorithm. The proposed algorithm can be developed to detect defected processor in the system.

  2. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  3. PERFORMANCE EVALUATION OF DIRECT PROCESSOR ACCESS FOR NON DEDICATED SERVER

    Directory of Open Access Journals (Sweden)

    P. S. BALAMURUGAN

    2010-10-01

    Full Text Available The objective of the paper is to design a co processor for a desktop machine which enables the machine to act as non dedicated server, such that the co processor will act as a server processor and the multi-core processor to act as desktop processor. By implementing this methodology a client machine can be made to act as a non dedicated server and a client machine. These type of machine can be used in autonomy networks. This design will lead to design of a cost effective server and machine which can parallel act as a non dedicated server and a client machine or it can be made to switch and act as client or server.

  4. Explore the Performance of the ARM Processor Using JPEG

    Directory of Open Access Journals (Sweden)

    A.D. Jadhav

    2010-01-01

    Full Text Available Recently, the evolution of embedded systems has shown a strong trend towards application- specific, single- chip solutions. The ARM processor core is a leading RISC processor architecture in the embedded domain. The ARM family of processors supports a unique feature of code size reduction. In this paper it is illustrated using an embedded platform trying to design an image encoder, more specifically a JPEG encoder using ARM7TDMI processor. Here gray scale image is used and it is coded by using keil software and same procedure is repeated by using MATLAB software for compare the results with standard one. Successfully putting a new application of JPEG on ARM7 processor.

  5. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  6. Mac OS X Server Snow Leopard 雪豹

    Institute of Scientific and Technical Information of China (English)

    王炳晨

    2010-01-01

    日前,苹果公司宣布推出Mac OSX Server Snow Leopard服务器系统。这是一个真正意义的全64位操作系统,为充分发挥多核心处理器和内存的性能而设计,且完全兼容32位应用程序。

  7. LHC@home online tutorial for Mac users - recording

    CERN Document Server

    CERN. Geneva

    2016-01-01

    A step-by-step online tutorial about LHC@home for Mac users by Alexandre Racine. It contains detailed instructions on how-to-join this volunteer computing project.  There are 3 screen capture videos with the real installation process accelerated attached to the event page. This 5' video is linked from http://lhcathome.web.cern.ch/join-us Also from the CDS e-learning category.

  8. Gauge theory of supergravity based only on a self-dual spin connection

    Energy Technology Data Exchange (ETDEWEB)

    Nieto, J.A.; Socorro, J.; Obregon, O. [Area of Superstrings, Escuela de Ciencias Fisico-Matematicas de la Universidad Michoacana de San Nicolas de Hidalgo, P.O. Box 749, 58000, Morelia, Michoacan (Mexico)]|[Instituto de Fisica de la Universidad de Guanajuato, P.O. Box E-143, 37150, Leon, Gto. (Mexico)]|[Depto. de Fisica, Universidad Autonoma Metropolitana-Iztapalapa, P.O. Box 55-534, 09340, D.F., Mexico (Mexico)

    1996-05-01

    A gauge theory of supergravity is constructed based only on the supersymmetric self-dual spin connection associated to the supergroup OSp(1{vert_bar}4). We show that Jacobson{close_quote}s supergravity action arises naturally from our proposed action. It is formulated by taking the self-dual part of the MacDowell-Mansouri gauge theory of supergravity. In this sense, our quadratic action in the supersymmetric self-dual curvature tensor provides a relation between these two important previous extensions of supergravity. {copyright} {ital 1996 The American Physical Society.}

  9. On the Selection of MAC Optimised Routing Protocol for VANET

    Directory of Open Access Journals (Sweden)

    Kanu Priya

    2017-02-01

    Full Text Available In today‘s era of modernization, the concept of smart vehicles, smart cities and automated vehicles is trending day by day. VANET (Vehicular Adhoc Network has also been emerging as a potential applicant to enable these smart applications. Though VANET is very much similar to MANET (Mobile Adhoc Network but VANET has more severe challenges as compared to MANET due to hostile channel conditions and high degree of mobility. So lot of work related to MAC and Network Layer need attention from the network designers. In this paper MAC Layer has been optimised in terms of Queue Size by using QoS Parameters namely Packet Collision Rate, Packet Drop Rate, Throughput Rate and Broadcast Rate. In doing so, simulative investigations have been done to find out optimum queue size. For this purpose various routing protocols namely DSDV, AODV, ADV and GOD have been considered and optimum queue length for each of these have been obtained. Further the most efficient routing protocol has also been identified. Moreover this paper also compares the performance of most efficient Routing Protocols selected in terms of QoS parameters for different MAC Interfaces.

  10. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L.; Camp, William J.

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  11. 42 CFR 423.2140 - MAC Review of ALJ decision in a case remanded by a Federal District Court.

    Science.gov (United States)

    2010-10-01

    ... 42 Public Health 3 2010-10-01 2010-10-01 false MAC Review of ALJ decision in a case remanded by a... BENEFIT Reopening, ALJ Hearings, MAC review, and Judicial Review § 423.2140 MAC Review of ALJ decision in..., when a case is remanded by a Federal District Court for further consideration and the MAC remands the...

  12. VLSI digital demodulator co-processor

    Science.gov (United States)

    Stephen, Karen J.; Buznitsky, Mitchell A.; Lindsey, Mark J.

    A demodulation coprocessor that incorporates into a single VLSI package a number of important arithmetic functions commonly encountered in demodulation processing is developed. The LD17 demodulator is designed for use in a digital modem as a companion to any of the commercially available digital signal processing (DSP) microprocessors. The LD17 includes an 8-b complex multiplier-accumulator (MAC), a programmable tone generator, a preintegrator, a dedicated noncoherent differential phase-shift keying (DPSK) calculator, and a program/data sequencer. By using a simple generic interface and small but powerful instruction set, the LD17 has the capability to operate in several architectural schemes with a minimum of glue logic. Speed, size, and power constraints will dictate which of these schemes is best for a particular application. The LD17 will be implemented in a 1.5-micron DLM CMOS gate array and packaged in an 84-pin JLCC. With the LD17 and its memory, the real-time processing compatibility of a typical DSP microprocessor can be extended to sampling rates from hundreds to thousands of kilosamples per second.

  13. A vector DSP for digital media processors

    Science.gov (United States)

    Bersack, Bret; Redford, John; Moniz, Matt; Goldman, Michael

    2003-05-01

    A new chip using a DSP with a novel vector architecture is described. It uses a Very Dense Instruction Word (rather than a VLIW) and exploits the parallelism and narrow data typical of image processing to gain high performance at low cost and power. It contains eight 32-bit datapaths all working off a single instruction, and can do sixteen 16-bit MACs per cycle or four 32-bit memory accesses per cycle to 128 KB of on-chip memory. It also contains a serial datapath for handling low-performance code and OS functions. The chip includes memory, video and IO interfaces on an industry-standard bus. It also includes camera-specific IO such as videos DACs for NTSC/PAL and analog LCDs, an I2S audio interface, and USB 1.1. It is built in 0.18 um CMOS, runs at 233 MHz, and draws 300 mW. It uses no fixed-function blocks, microcode, or coprocessors, but can capture and compress video at 30 fps at VGA resolution using JPEG, or at CIF resolution using MPEG-4.

  14. Interplay between MacDonald and Hall-Littlewood expansions of extended torus superpolynomials

    CERN Document Server

    Mironov, A; Shakirov, Sh; Sleptsov, A

    2012-01-01

    In arXiv:1106.4305 extended superpolynomials were introduced for the torus links T[m,mk+r], which are functions on the entire space of time variables and, at expense of reducing the topological invariance, possess additional algebraic properties, resembling those of the matrix model partition functions and the KP/Toda tau-functions. Not surprisingly, being a suitable extension it actually allows one to calculate the superpolynomials. These functions are defined as expansions into MacDonald polynomials, and their dependence on k is entirely captured by the action of the cut-and-join operator, like in the HOMFLY case. We suggest a simple description of the coefficients in these character expansions, by expanding the initial (at k=0) conditions for the k-evolution into the new auxiliary basis, this time provided by the Hall-Littlewood polynomials, which, hence, play a role in the description of the dual m-evolution. For illustration we list manifest expressions for a few first series, mk\\pm 1, mk\\pm 2, mk\\pm 3. ...

  15. Leukocyte integrin Mac-1 regulates thrombosis via interaction with platelet GPIbα.

    Science.gov (United States)

    Wang, Yunmei; Gao, Huiyun; Shi, Can; Erhardt, Paul W; Pavlovsky, Alexander; A Soloviev, Dmitry; Bledzka, Kamila; Ustinov, Valentin; Zhu, Liang; Qin, Jun; Munday, Adam D; Lopez, Jose; Plow, Edward; Simon, Daniel I

    2017-05-30

    Inflammation and thrombosis occur together in many diseases. The leukocyte integrin Mac-1 (also known as integrin αMβ2, or CD11b/CD18) is crucial for leukocyte recruitment to the endothelium, and Mac-1 engagement of platelet GPIbα is required for injury responses in diverse disease models. However, the role of Mac-1 in thrombosis is undefined. Here we report that mice with Mac-1 deficiency (Mac-1(-/-)) or mutation of the Mac-1-binding site for GPIbα have delayed thrombosis after carotid artery and cremaster microvascular injury without affecting parameters of haemostasis. Adoptive wild-type leukocyte transfer rescues the thrombosis defect in Mac-1(-/-) mice, and Mac-1-dependent regulation of the transcription factor Foxp1 contributes to thrombosis as evidenced by delayed thrombosis in mice with monocyte-/macrophage-specific overexpression of Foxp1. Antibody and small-molecule targeting of Mac-1:GPIbα inhibits thrombosis. Our data identify a new pathway of thrombosis involving leukocyte Mac-1 and platelet GPIbα, and suggest that targeting this interaction has anti-thrombotic therapeutic potential with reduced bleeding risk.

  16. Characteristics of Mycobacterium avium complex (MAC) pulmonary disease in previously treated lung cancer patients.

    Science.gov (United States)

    Meier, Erin; Pennington, Kelly; Gallo de Moraes, Alice; Escalante, Patricio

    2017-01-01

    Mycobacterium avium complex (MAC) is responsible for a large portion of non-tuberculous mycobacterial (NTM) infections worldwide. Host factors such as active malignancy, immunosuppression, chronic obstructive pulmonary disease (COPD) and bronchiectasis increase the risk of MAC infection. However, the relationship between previously treated lung cancer with subsequent development of MAC pulmonary disease and treatment outcomes have not been previously studied. We retrospectively identified all patients with lung cancer and MAC pulmonary disease documented in medical records at Mayo Clinic between January 2005 and October 2016. Patients who were diagnosed with MAC pulmonary disease before or at the time of lung cancer diagnosis were excluded. Patients meeting all inclusion criteria underwent chart review for prior oncologic treatments, clinical characteristics, and MAC treatment response. We identified 13 patients with MAC pulmonary disease and prior lung cancer, including 4 men and 9 women. Eight patients had structural lung disease that can predispose to MAC pulmonary disease, including bronchiectasis (23.0%) and COPD (46.2%). Four (30.8%) had no apparent immunosuppression or other risk factor(s) for MAC pulmonary disease. Primary pulmonary malignancies included pulmonary carcinoid, adenocarcinoma, and squamous cell carcinoma. Ten (76.9%) patients were started on antimicrobial treatment for MAC, and 8 (61.5%) patients completed MAC treatment with 6 (46.1%) patients achieving symptomatic improvement. MAC pulmonary disease in previously treated lung cancer can occur without apparent risk factors for this NTM infection. Symptomatic improvement with MAC antimicrobial therapy appears to be lower than expected but comorbidities might influence outcomes in this patient population.

  17. Evaluating New Architectural Features Of The Intel(R Xeon(R 7500 Processor For Hpc Workloads

    Directory of Open Access Journals (Sweden)

    Paweł Gepner

    2011-01-01

    Full Text Available In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600 and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies and features like Intels HyperThreading Technology (HT and Intel Turbo Boost Technology (Turbo Mode and theperformance implication of these technologies for HPC.

  18. First Results of an "Artificial Retina" Processor Prototype

    Science.gov (United States)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-11-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called "artificial retina algorithm", inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate.

  19. Digital optical cellular image processor (DOCIP) - Experimental implementation

    Science.gov (United States)

    Huang, K.-S.; Sawchuk, A. A.; Jenkins, B. K.; Chavel, P.; Wang, J.-M.; Weber, A. G.; Wang, C.-H.; Glaser, I.

    1993-01-01

    We demonstrate experimentally the concept of the digital optical cellular image processor architecture by implementing one processing element of a prototype optical computer that includes a 54-gate processor, an instruction decoder, and electronic input-output interfaces. The processor consists of a two-dimensional (2-D) array of 54 optical logic gates implemented by use of a liquid-crystal light valve and a 2-D array of 53 subholograms to provide interconnections between gates. The interconnection hologram is fabricated by a computer-controlled optical system.

  20. Ethernet-Enabled Power and Communication Module for Embedded Processors

    Science.gov (United States)

    Perotti, Jose; Oostdyk, Rebecca

    2010-01-01

    The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

  1. Scientific Computing Kernels on the Cell Processor

    Energy Technology Data Exchange (ETDEWEB)

    Williams, Samuel W.; Shalf, John; Oliker, Leonid; Kamil, Shoaib; Husbands, Parry; Yelick, Katherine

    2007-04-04

    The slowing pace of commodity microprocessor performance improvements combined with ever-increasing chip power demands has become of utmost concern to computational scientists. As a result, the high performance computing community is examining alternative architectures that address the limitations of modern cache-based designs. In this work, we examine the potential of using the recently-released STI Cell processor as a building block for future high-end computing systems. Our work contains several novel contributions. First, we introduce a performance model for Cell and apply it to several key scientific computing kernels: dense matrix multiply, sparse matrix vector multiply, stencil computations, and 1D/2D FFTs. The difficulty of programming Cell, which requires assembly level intrinsics for the best performance, makes this model useful as an initial step in algorithm design and evaluation. Next, we validate the accuracy of our model by comparing results against published hardware results, as well as our own implementations on a 3.2GHz Cell blade. Additionally, we compare Cell performance to benchmarks run on leading superscalar (AMD Opteron), VLIW (Intel Itanium2), and vector (Cray X1E) architectures. Our work also explores several different mappings of the kernels and demonstrates a simple and effective programming model for Cell's unique architecture. Finally, we propose modest microarchitectural modifications that could significantly increase the efficiency of double-precision calculations. Overall results demonstrate the tremendous potential of the Cell architecture for scientific computations in terms of both raw performance and power efficiency.

  2. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  3. Element Load Data Processor (ELDAP) Users Manual

    Science.gov (United States)

    Ramsey, John K., Jr.; Ramsey, John K., Sr.

    2015-01-01

    Often, the shear and tensile forces and moments are extracted from finite element analyses to be used in off-line calculations for evaluating the integrity of structural connections involving bolts, rivets, and welds. Usually the maximum forces and moments are desired for use in the calculations. In situations where there are numerous structural connections of interest for numerous load cases, the effort in finding the true maximum force and/or moment combinations among all fasteners and welds and load cases becomes difficult. The Element Load Data Processor (ELDAP) software described herein makes this effort manageable. This software eliminates the possibility of overlooking the worst-case forces and moments that could result in erroneous positive margins of safety and/or selecting inconsistent combinations of forces and moments resulting in false negative margins of safety. In addition to forces and moments, any scalar quantity output in a PATRAN report file may be evaluated with this software. This software was originally written to fill an urgent need during the structural analysis of the Ares I-X Interstage segment. As such, this software was coded in a straightforward manner with no effort made to optimize or minimize code or to develop a graphical user interface.

  4. Simultaneous multithreaded processor enhanced for multimedia applications

    Science.gov (United States)

    Mombers, Friederich; Thomas, Michel

    1999-12-01

    The paper proposes a new media processor architecture specifically designed to handle state-of-the-art multimedia encoding and decoding tasks. To achieve this, the architecture efficiently exploit Data-, Instruction- and Thread-Level parallelisms while continuously adapting its computational resources to reach the most appropriate parallelism level among all the concurrent encoding/decoding processes. Looking at the implementation constraints, several critical choices were adopted that solve the interconnection delay problem, lower the cache misses and pipeline stalls effects and reduce register files and memory size by adopting a clustered Simultaneous Multithreaded Architecture. We enhanced the classic model to exploit both Instruction and Data Level Parallelism through vector instructions. The vector extension is well justified for multimedia workload and improves code density, crossbars complexity, register file ports and decoding logic area while it still provides an efficient way to fully exploit a large set of functional units. An MPEG-2 encoding algorithms based on Hybrid Genetic search has been implemented that show the efficiency of the architecture to adapt its resources allocation to better fulfill the application requirements.

  5. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  6. Food processors requirements met by radiation processing

    Science.gov (United States)

    Durante, Raymond W.

    2002-03-01

    Processing food using irradiation provides significant advantages to food producers by destroying harmful pathogens and extending shelf life without any detectable physical or chemical changes. It is expected that through increased public education, food irradiation will emerge as a viable commercial industry. Food production in most countries involves state of the art manufacturing, packaging, labeling, and shipping techniques that provides maximum efficiency and profit. In the United States, food sales are extremely competitive and profit margins small. Most food producers have heavily invested in equipment and are hesitant to modify their equipment. Meat and poultry producers in particular utilize sophisticated production machinery that processes enormous volumes of product on a continuous basis. It is incumbent on the food irradiation equipment suppliers to develop equipment that can easily merge with existing processes without requiring major changes to either the final food product or the process utilized to produce that product. Before a food producer can include irradiation as part of their food production process, they must be certain the available equipment meets their needs. This paper will examine several major requirements of food processors that will most likely have to be provided by the supplier of the irradiation equipment.

  7. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  8. A CNN-Specific Integrated Processor

    Science.gov (United States)

    Malki, Suleyman; Spaanenburg, Lambert

    2009-12-01

    Integrated Processors (IP) are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN) to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  9. Optimal piecewise linear schedules for LSGP- and LPGS-decomposed array processors via quadratic programming

    Science.gov (United States)

    Zimmermann, Karl-Heinz; Achtziger, Wolfgang

    2001-09-01

    The size of a systolic array synthesized from a uniform recurrence equation, whose computations are mapped by a linear function to the processors, matches the problem size. In practice, however, there exist several limiting factors on the array size. There are two dual schemes available to derive arrays of smaller size from large-size systolic arrays based on the partitioning of the large-size arrays into subarrays. In LSGP, the subarrays are clustered one-to-one into the processors of a small-size array, while in LPGS, the subarrays are serially assigned to a reduced-size array. In this paper, we propose a common methodology for both LSGP and LPGS based on polyhedral partitionings of large-size k-dimensional systolic arrays which are synthesized from n-dimensional uniform recurrences by linear mappings for allocation and timing. In particular, we address the optimization problem of finding optimal piecewise linear timing functions for small-size arrays. These are mappings composed of linear timing functions for the computations of the subarrays. We study a continuous approximation of this problem by passing from piecewise linear to piecewise quasi-linear timing functions. The resultant problem formulation is then a quadratic programming problem which can be solved by standard algorithms for nonlinear optimization problems.

  10. Image data compression using a new floating-point digital signal processor.

    Science.gov (United States)

    Siegel, E L; Templeton, A W; Hensley, K L; McFadden, M A; Baxter, K G; Murphey, M D; Cronin, P E; Gesell, R G; Dwyer, S J

    1991-08-01

    A new dual-ported, floating-point, digital signal processor has been evaluated for compressing 512 and 1,024 digital radiographic images using a full-frame, two-dimensional, discrete cosine transform (2D-DCT). The floating point digital signal processor operates at 49.5 million floating point instructions per second (MFLOPS). The level of compression can be changed by varying four parameters in the lossy compression algorithm. Throughput times were measured for both 2D-DCT compression and decompression. For a 1,024 x 1,024 x 10-bit image with a compression ratio of 316:1, the throughput was 75.73 seconds (compression plus decompression throughput). For a digital fluorography 1,024 x 1,024 x 8-bit image and a compression ratio of 26:1, the total throughput time was 63.23 seconds. For a computed tomography image of 512 x 512 x 12 bits and a compression ratio of 10:1 the throughput time was 19.65 seconds.

  11. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Kazimierz Wiatr

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  12. TMAC: Timestamp-Ordered MAC Protocol for Wireless Mesh Networks

    KAUST Repository

    Nawab, Faisal

    2011-05-01

    Wireless Mesh Networks (WMNs) have emerged to meet a need for a self-organized and self-configured multi-hop wireless network infrastructure. Low cost infrastructure and ease of deployment have made WMNs an attractive technology for last mile access. However, 802.11 based WMNs are subject to serious fairness issues. With backlogged TCP traffic, nodes which are two or more hops away from the gateway are subject to starvation, while the one-hop away node saturates the channel with its own local traffic. We study the interactions of TCP and IEEE 802.11 MAC in WMNs to aid us in understanding and overcoming the unfairness problem. We propose a Markov chain to capture the behavior of TCP sessions, particularly the impact on network throughput performance due to the effect of queue utilization and packet relaying. A closed form solution is derived to numerically derive the throughput. Based on the developed model, we propose a distributed MAC protocol called Timestamp-ordered MAC (TMAC), aiming to alleviate the unfairness problem in WMNs via a manipulative per-node scheduling mechanism which takes advantage of the age of each packet as a priority metric. Simulation is conducted to validate our model and to illustrate the fairness characteristics of TMAC. Our results show that TMAC achieves excellent resource allocation fairness while maintaining above 90% of maximum link capacity in parking lot and large grid topologies. Our work illuminates the factors affecting TCP fairness in WMNs. Our theoretical and empirical findings can be used in future research to develop more fairness-aware protocols for WMNs.

  13. Architecture and Design of Medical Processor Units for Medical Networks

    CERN Document Server

    Ahamed, Syed V; 10.5121/ijcnc.2010.2602

    2011-01-01

    This paper introduces analogical and deductive methodologies for the design medical processor units (MPUs). From the study of evolution of numerous earlier processors, we derive the basis for the architecture of MPUs. These specialized processors perform unique medical functions encoded as medical operational codes (mopcs). From a pragmatic perspective, MPUs function very close to CPUs. Both processors have unique operation codes that command the hardware to perform a distinct chain of subprocesses upon operands and generate a specific result unique to the opcode and the operand(s). In medical environments, MPU decodes the mopcs and executes a series of medical sub-processes and sends out secondary commands to the medical machine. Whereas operands in a typical computer system are numerical and logical entities, the operands in medical machine are objects such as such as patients, blood samples, tissues, operating rooms, medical staff, medical bills, patient payments, etc. We follow the functional overlap betw...

  14. APEmille a parallel processor in the teraflop range

    CERN Document Server

    Panizzi, E

    1996-01-01

    APEmille is a SIMD parallel processor under development at the Italian National Institute for Nuclear Physics (INFN). APEmille is very well suited for Lattice QCD applications, both for its hardware characteristics and for its software and language features. APEmille is an array of custom arithmetic processors arranged on a tridimensional torus. The replicated processor is a pipelined VLIW device performing integer and single/double precision IEEE floating point operations. The processor is optimized for complex computations and has a peak performance of 528Mflop at 66MHz and of 800Mflop at 100MHz. In principle an array of 2048 nodes is able to break the Tflops barrier. A powerful programming language named TAO is provided and is highly optimized for QCD. A C++ compiler is foreseen. Specific data structures, operators and even statements can be defined by the user for each different application. Effort has been made to define the language constructs for QCD.

  15. Compiler for Fast, Accurate Mathematical Computing on Integer Processors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The proposers will develop a computer language compiler to enable inexpensive, low-power, integer-only processors to carry our mathematically-intensive comptutations...

  16. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Zhiyi Yu

    2007-05-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  17. 2009 Survey of Gulf of Mexico Dockside Seafood Processors

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This survey gathered and analyze economic data from seafood processors throughout the states in the Gulf region. The survey sought to collect financial variables...

  18. Baseband processor development for the Advanced Communications Satellite Program

    Science.gov (United States)

    Moat, D.; Sabourin, D.; Stilwell, J.; Mccallister, R.; Borota, M.

    1982-01-01

    An onboard-baseband-processor concept for a satellite-switched time-division-multiple-access (SS-TDMA) communication system was developed for NASA Lewis Research Center. The baseband processor routes and controls traffic on an individual message basis while providing significant advantages in improved link margins and system flexibility. Key technology developments required to prove the flight readiness of the baseband-processor design are being verified in a baseband-processor proof-of-concept model. These technology developments include serial MSK modems, Clos-type baseband routing switch, a single-chip CMOS maximum-likelihood convolutional decoder, and custom LSL implementation of high-speed, low-power ECL building blocks.

  19. A Shared Memory Module for Asynchronous Arrays of Processors

    Directory of Open Access Journals (Sweden)

    Meeuwsen MichaelJ

    2007-01-01

    Full Text Available A shared memory module connecting multiple independently clocked processors is presented. The memory module itself is independently clocked, supports hardware address generation, mutual exclusion, and multiple addressing modes. The architecture supports independent address generation and data generation/consumption by different processors which increases efficiency and simplifies programming for many embedded and DSP tasks. Simultaneous access by different processors is arbitrated using a least-recently-serviced priority scheme. Simulations show high throughputs over a variety of memory loads. A standard cell implementation shares an 8 K-word SRAM among four processors, and can support a 64 K-word SRAM with no additional changes. It cycles at 555 MHz and occupies 1.2 mm2 in 0.18 μm CMOS.

  20. Processors' training needs on modern shea butter processing ...

    African Journals Online (AJOL)

    Processors' training needs on modern shea butter processing technologies in North Central ... South African Journal of Agricultural Extension ... The need for continual production of high quality shea butter in Nigeria through the use of modern ...

  1. Reconfigurable VLIW Processor for Software Defined Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...

  2. Tournament MAC with Constant Size Congestion Window for WLAN

    CERN Document Server

    Galtier, Jerome

    2007-01-01

    In the context of radio distributed networks, we present a generalized approach for the Medium Access Control (MAC) with fixed congestion window. Our protocol is quite simple to analyze and can be used in a lot of different situations. We give mathematical evidence showing that our performance is tight, in the sense that no protocol with fixed congestion window can do better. We also place ourselves in the WiFi/WiMAX framework, and show experimental results enlightening collision reduction of 14% to 21% compared to the best known other methods. We show channel capacity improvement, and fairness considerations.

  3. Mac configuration management at the Los Alamos National Laboratory

    Energy Technology Data Exchange (ETDEWEB)

    Marcus, Allan B [Los Alamos National Laboratory

    2010-01-01

    The Los Alamos National Laboratory (LANL) had a need for central configuration management of non-Windows computers. LANL has three to five thousand Macs and an equal number of Linux based systems. The primary goal was to be able to inventory all non-windows systems and patch Mc OS X systems. LANL examined a number of commercial and open source solutions and ultimately selected Puppet. This paper will discuss why we chose Puppet, how we implemented it, and some lessons we learned along the way.

  4. Proximate analysis of coal by Leco MAC-400

    Energy Technology Data Exchange (ETDEWEB)

    Wilson, S.T. (British Steel Corporation, London (UK). Ravenscraig Works)

    1988-01-01

    Discussion is presented of the use of the Leco Mac-400 Proximate Analyser at the Ravenscraig Steel Works, UK. It is used for the analysis of in-plant coals and the determination of ash in coke. The instrument does not meet the British Standard requirement for repeatability, so is not used for 'value in use' coal analysis. It has recently been overhauled, however, and will be re-evaluated to see if the overhaul has brought an improvement in performance. 6 figs., 7 tabs.

  5. Intelligent Cooperative MAC Protocol for Balancing Energy Consumption

    Science.gov (United States)

    Wu, S.; Liu, K.; Huang, B.; Liu, F.

    To extend the lifetime of wireless sensor networks, we proposed an intelligent balanced energy consumption cooperative MAC protocol (IBEC-CMAC) based on the multi-node cooperative transmission model. The protocol has priority to access high-quality channels for reducing energy consumption of each transmission. It can also balance the energy consumption among cooperative nodes by using high residual energy nodes instead of excessively consuming some node's energy. Simulation results show that IBEC-CMAC can obtain longer network lifetime and higher energy utilization than direct transmission.

  6. Minimum alveolar concentration (MAC) for sevoflurane and xenon at normothermia and hypothermia in newborn pigs.

    Science.gov (United States)

    Liu, X; Dingley, J; Elstad, M; Scull-Brown, E; Steen, P A; Thoresen, M

    2013-05-01

    Neuroprotection from therapeutic hypothermia increases when combined with the anaesthetic gas xenon in animal studies. A clinical feasibility study of the combined treatment has been successfully undertaken in asphyxiated human term newborns. It is unknown whether xenon alone would be sufficient for sedation during hypothermia eliminating or reducing the need for other sedative or analgesic infusions in ventilated sick infants. Minimum alveolar concentration (MAC) of xenon is unknown in any neonatal species. Eight newborn pigs were anaesthetised with sevoflurane alone and then sevoflurane plus xenon at two temperatures. Pigs were randomised to start at either 38.5°C or 33.5°C. MAC for sevoflurane was determined using the claw clamp technique at the preset body temperature. For xenon MAC determination, a background of 0.5 MAC sevoflurane was used, and 60% xenon added to the gas mixture. The relationship between sevoflurane and xenon MAC is assumed to be additive. Xenon concentrations were changed in 5% steps until a positive clamp reaction was noted. Pigs' temperature was changed to the second target, and two MAC determinations for sevoflurane and 0.5 MAC sevoflurane plus xenon were repeated. MAC for sevoflurane was 4.1% [95% confidence interval (CI): 3.65-4.50] at 38.5°C and 3.05% (CI: 2.63-3.48) at 33.5°C, a significant reduction. MAC for xenon was 120% at 38.5°C and 116% at 33.5°C, not different. In newborn swine sevoflurane, MAC was temperature dependent, while xenon MAC was independent of temperature. There was large individual variability in xenon MAC, from 60% to 120%. © 2013 The Acta Anaesthesiologica Scandinavica Foundation.

  7. Floating-point multiple data stream digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Fortier, M.; Corinthios, M.J.

    1982-01-01

    A microprogrammed multiple data stream digital signal processor is introduced. This floating-point processor is capable of implementing optimum Wiener filtering of signals, in general, and images in particular. Generalised spectral analysis transforms such as Fourier, Walsh, Hadamard, and generalised Walsh are efficiently implemented in a bit-slice microprocessor-based architecture. In this architecture, a microprogrammed sequencing section directly controls a central floating-point signal processing unit. Throughout, computations are performed on pipelined multiple complex data streams. 12 references.

  8. Real time simulator with Ti floating point digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Razazian, K.; Bobis, J.P.; Dieckman, S.L.; Raptis, A.C.

    1994-08-01

    This paper describes the design and operation of a Real Time Simulator using Texas Instruments TMS320C30 digital signal processor. This system operates with two banks of memory which provide the input data to digital signal processor chip. This feature enables the TMS320C30 to be utilized in variety of applications for which external connections to acquire input data is not needed. In addition, some practical applications of this Real Time Simulator are discussed.

  9. Multi Microkernel Operating Systems for Multi-Core Processors

    Directory of Open Access Journals (Sweden)

    Rami Matarneh

    2009-01-01

    Full Text Available Problem statement: In the midst of the huge development in processors industry as a response to the increasing demand for high-speed processors manufacturers were able to achieve the goal of producing the required processors, but this industry disappointed hopes, because it faced problems not amenable to solution, such as complexity, hard management and large consumption of energy. These problems forced the manufacturers to stop the focus on increasing the speed of processors and go toward parallel processing to increase performance. This eventually produced multi-core processors with high-performance, if used properly. Unfortunately, until now, these processors did not use as it should be used; because of lack support of operating system and software applications. Approach: The approach based on the assumption that single-kernel operating system was not enough to manage multi-core processors to rethink the construction of multi-kernel operating system. One of these kernels serves as the master kernel and the others serve as slave kernels. Results: Theoretically, the proposed model showed that it can do much better than the existing models; because it supported single-threaded processing and multi-threaded processing at the same time, in addition, it can make better use of multi-core processors because it divided the load almost equally between the cores and the kernels which will lead to a significant improvement in the performance of the operating system. Conclusion: Software industry needed to get out of the classical framework to be able to keep pace with hardware development, this objective was achieved by re-thinking building operating systems and software in a new innovative methodologies and methods, where the current theories of operating systems were no longer capable of achieving the aspirations of future.

  10. Nanosensor Data Processor in Quantum-Dot Cellular Automata

    OpenAIRE

    Fenghui Yao; Mohamed Saleh Zein-Sabatto; Guifeng Shao; Mohammad Bodruzzaman; Mohan Malkani

    2014-01-01

    Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. This paper describes the design of a 4-bit multifunction nanosensor data processor (NSDP). The functions of NSDP contain (i) sending the preprocessed raw data to high-level processor, (ii) counting...

  11. An Imaging Infrared (IIR) seeker using a microprogrammed processor

    Science.gov (United States)

    Richmond, K. V.

    1980-01-01

    A recently developed Imaging Infrared Seeker uses a microprogrammed processor to perform gimbal servo control and system interface while performing the seeker functions of automatic target detection, acquisition, and tracking. The automatic detection mode requires up to 80% of the available capability of a high performance microprogrammed processor. Although system complexity was increased significantly, this approach can be cost effective when the basic computation capacity is already available.

  12. Fast Parallel Computation of Polynomials Using Few Processors

    DEFF Research Database (Denmark)

    Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.;

    1983-01-01

    It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors.......It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

  13. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors.......It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  14. MQ-MAC: A Multi-Constrained QoS-Aware Duty Cycle MAC for Heterogeneous Traffic in Wireless Sensor Networks

    Science.gov (United States)

    Monowar, Muhammad Mostafa; Rahman, Md. Obaidur; Hong, Choong Seon; Lee, Sungwon

    2010-01-01

    Energy conservation is one of the striking research issues now-a-days for power constrained wireless sensor networks (WSNs) and hence, several duty-cycle based MAC protocols have been devised for WSNs in the last few years. However, assimilation of diverse applications with different QoS requirements (i.e., delay and reliability) within the same network also necessitates in devising a generic duty-cycle based MAC protocol that can achieve both the delay and reliability guarantee, termed as multi-constrained QoS, while preserving the energy efficiency. To address this, in this paper, we propose a Multi-constrained QoS-aware duty-cycle MAC for heterogeneous traffic in WSNs (MQ-MAC). MQ-MAC classifies the traffic based on their multi-constrained QoS demands. Through extensive simulation using ns-2 we evaluate the performance of MQ-MAC. MQ-MAC provides the desired delay and reliability guarantee according to the nature of the traffic classes as well as achieves energy efficiency. PMID:22163439

  15. MQ-MAC: a multi-constrained QoS-aware duty cycle MAC for heterogeneous traffic in wireless sensor networks.

    Science.gov (United States)

    Monowar, Muhammad Mostafa; Rahman, Md Obaidur; Hong, Choong Seon; Lee, Sungwon

    2010-01-01

    Energy conservation is one of the striking research issues now-a-days for power constrained wireless sensor networks (WSNs) and hence, several duty-cycle based MAC protocols have been devised for WSNs in the last few years. However, assimilation of diverse applications with different QoS requirements (i.e., delay and reliability) within the same network also necessitates in devising a generic duty-cycle based MAC protocol that can achieve both the delay and reliability guarantee, termed as multi-constrained QoS, while preserving the energy efficiency. To address this, in this paper, we propose a Multi-constrained QoS-aware duty-cycle MAC for heterogeneous traffic in WSNs (MQ-MAC). MQ-MAC classifies the traffic based on their multi-constrained QoS demands. Through extensive simulation using ns-2 we evaluate the performance of MQ-MAC. MQ-MAC provides the desired delay and reliability guarantee according to the nature of the traffic classes as well as achieves energy efficiency.

  16. MQ-MAC: A Multi-Constrained QoS-Aware Duty Cycle MAC for Heterogeneous Traffic in Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Sungwon Lee

    2010-11-01

    Full Text Available Energy conservation is one of the striking research issues now-a-days for power constrained wireless sensor networks (WSNs and hence, several duty-cycle based MAC protocols have been devised for WSNs in the last few years. However, assimilation of diverse applications with different QoS requirements (i.e., delay and reliability within the same network also necessitates in devising a generic duty-cycle based MAC protocol that can achieve both the delay and reliability guarantee, termed as multi-constrained QoS, while preserving the energy efficiency. To address this, in this paper, we propose a Multi-constrained QoS-aware duty-cycle MAC for heterogeneous traffic in WSNs (MQ-MAC. MQ-MAC classifies the traffic based on their multi-constrained QoS demands. Through extensive simulation using ns-2 we evaluate the performance of MQ-MAC. MQ-MAC provides the desired delay and reliability guarantee according to the nature of the traffic classes as well as achieves energy efficiency.

  17. THOR Field and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Balikhin, Michael; Zaslavsky, Arnaud; Nakamura, Rumi; Khotyaintsev, Yuri; Uhlir, Ludek; Lan, Radek; Yearby, Keith; Morawski, Marek; Winkler, Marek

    2016-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first mission ever flown in space dedicated to plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer and search-coil magnetometer (SCM) and perform data digitization and on-board processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The feasibility of making highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation complemented by a thorough electromagnetic cleanliness program will further improve on this heritage. Taking advantage of the capabilities of modern electronics, FWP will provide simultaneous synchronized waveform and spectral data products at high time resolution from the numerous THOR sensors, taking advantage of the large telemetry bandwidth of THOR. FWP will also implement a plasma a resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will be interfaced with the particle instrument data processing unit (PPU) via a dedicated digital link which will enable performing on board correlation between waves and particles, quantifying the transfer of energy between waves and particles. The FWP instrument shall be designed and built by an international consortium of scientific institutes from Czech Republic, Poland, France, UK, Sweden

  18. Biomolecular simulation on thousands of processors

    Science.gov (United States)

    Phillips, James Christopher

    Classical molecular dynamics simulation is a generally applicable method for the study of biomolecular aggregates of proteins, lipids, and nucleic acids. As experimental techniques have revealed the structures of larger and more complex biomolecular machines, the time required to complete even a single meaningful simulation of such systems has become prohibitive. We have developed the program NAMD to simulate systems of 50,000--500,000 atoms efficiently with full electrostatics on parallel computers with 1000 and more processors. NAMD's scalability is achieved through latency tolerant adaptive message-driven execution and measurement-based load balancing. NAMD is implemented in C++ and uses object-oriented design and threads to shield the basic algorithms from the necessary complexity of high-performance parallel execution. Apolipoprotein A-I is the primary protein constituent of high density lipoprotein particles, which transport cholesterol in the bloodstream. In collaboration with A. Jonas, we have constructed and simulated models of the nascent discoidal form of these particles, providing theoretical insight to the debate regarding the lipid-bound structure of the protein. Recently, S. Sligar and coworkers have created 10 nm phospholipid bilayer nanoparticles comprising a small lipid bilayer disk solubilized by synthetic membrane scaffold proteins derived from apolipoprotein A-I. Membrane proteins may be embedded in the water-soluble disks, with various medical and technological applications. We are working to develop variant scaffold proteins that produce disks of greater size, stability, and homogeneity. Our simulations have demonstrated a significant deviation from idealized cylindrical structure, and are being used in the interpretation of small angle x-ray scattering data.

  19. High Throughput Bent-Pipe Processor Demonstrator

    Science.gov (United States)

    Tabacco, P.; Vernucci, A.; Russo, L.; Cangini, P.; Botticchio, T.; Angeletti, P.

    2008-08-01

    The work associated to this article is a study initiative sponsored by ESA/ESTEC that responds to the crucial need of developing new Satellite payload aimed at making rapid progresses in handling large amounts of data at a competitive price with respect to terrestrial one in the telecommunication field. Considering the quite limited band allowed to space communications at Ka band, reusing the same band in a large number of beams is mandatory: therefore beam-forming is the right technological answer. Technological progresses - mainly in the digital domain - also help greatly in increasing the satellite capacity. Next Satellite payload target are set in throughput range of 50Gbps. Despite the fact that the implementation of a wideband transparent processor for a high capacity communication payload is a very challenging task, Space Engineering team in the frame of this ESA study proposed an intermediate step of development for a scalable unit able to demonstrate both the capacity and flexibility objectives for different type of Wideband Beamforming antennas designs. To this aim the article describes the features of Wideband HW (analog and digital) platform purposely developed by Space Engineering in the frame of this ESA/ESTEC contract ("WDBFN" contract) with some preliminary system test results. The same platform and part of the associated SW will be used in the development and demonstration of the real payload digital front end Mux and Demux algorithms as well as the Beam Forming and on Board channel switching in frequency domain. At the time of this article writing, despite new FPGA and new ADC and DAC converters have become available as choices for wideband system implementation, the two HW platforms developed by Space Engineering, namely WDBFN ADC and DAC Boards, represent still the most performing units in terms of analog bandwidth, processing capability (in terms of FPGA module density), SERDES (SERiliazer DESerializers) external links density, integration form

  20. A novel VLSI processor architecture for supercomputing arrays

    Science.gov (United States)

    Venkateswaran, N.; Pattabiraman, S.; Devanathan, R.; Ahmed, Ashaf; Venkataraman, S.; Ganesh, N.

    1993-01-01

    Design of the processor element for general purpose massively parallel supercomputing arrays is highly complex and cost ineffective. To overcome this, the architecture and organization of the functional units of the processor element should be such as to suit the diverse computational structures and simplify mapping of complex communication structures of different classes of algorithms. This demands that the computation and communication structures of different class of algorithms be unified. While unifying the different communication structures is a difficult process, analysis of a wide class of algorithms reveals that their computation structures can be expressed in terms of basic IP,IP,OP,CM,R,SM, and MAA operations. The execution of these operations is unified on the PAcube macro-cell array. Based on this PAcube macro-cell array, we present a novel processor element called the GIPOP processor, which has dedicated functional units to perform the above operations. The architecture and organization of these functional units are such to satisfy the two important criteria mentioned above. The structure of the macro-cell and the unification process has led to a very regular and simpler design of the GIPOP processor. The production cost of the GIPOP processor is drastically reduced as it is designed on high performance mask programmable PAcube arrays.

  1. Review of trigger and on-line processors at SLAC

    Energy Technology Data Exchange (ETDEWEB)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e/sup +/e/sup -/ physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e/sup +/e/sup -/ annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e/sup +/e/sup -/ context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table.

  2. Design and Implementation of Quintuple Processor Architecture Using FPGA

    Directory of Open Access Journals (Sweden)

    P.Annapurna

    2014-09-01

    Full Text Available The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.

  3. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  4. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  5. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  6. Sevoflurane decreases bispectral index values more than does halothane at equal MAC multiples.

    Science.gov (United States)

    Schwab, Hildebrand S; Seeberger, Manfred D; Eger, Edmond I; Kindler, Christoph H; Filipovic, Miodrag

    2004-12-01

    At the minimum alveolar concentration (MAC) of inhaled anesthetics, 50% of subjects move in response to noxious stimulation. Similarly, at MAC-awake, 50% of subjects respond appropriately to command. The bispectral index (BIS) nominally measures the effect of anesthetics on wakefulness or consciousness. We postulated that the use of halothane with a larger MAC-awake/MAC ratio than sevoflurane would produce higher BIS values at comparable levels of MAC. We studied 33 unpremedicated patients anesthetized by inhalation, 18 with sevoflurane and 15 with halothane. We measured BIS before and during anesthesia at 1 MAC, both before and after tracheal intubation facilitated by fentanyl and rocuronium and then at 1.5 MAC. BIS measurements were made after meeting steady-state conditions. No surgery was performed during this study. BIS values in awake patients did not differ between the sevoflurane and halothane groups (96 +/- 2 and 96 +/- 2, mean +/- sd, respectively). At 1 MAC without and with neuromuscular blockade and at 1.5 MAC, BIS values for patients anesthetized with halothane (54 +/- 7, 56 +/- 7, and 49 +/- 7, respectively) exceeded those for patients anesthetized with sevoflurane (34 +/- 6, 34 +/- 6, and 29 +/- 5, respectively) (P < 0.0001). This finding adds to other evidence indicating that BIS is drug specific.

  7. Power-Controlled MAC Protocols with Dynamic Neighbor Prediction for Ad hoc Networks

    Institute of Scientific and Technical Information of China (English)

    LI Meng; ZHANG Lin; XIAO Yong-kang; SHAN Xiu-ming

    2004-01-01

    Energy and bandwidth are the scarce resources in ad hoc networks because most of the mobile nodes are battery-supplied and share the exclusive wireless medium. Integrating the power control into MAC protocol is a promising technique to fully exploit these precious resources of ad hoc wireless networks. In this paper, a new intelligent power-controlled Medium Access Control (MAC) (iMAC) protocol with dynamic neighbor prediction is proposed. Through the elaborate design of the distributed transmit-receive strategy of mobile nodes, iMAC greatly outperforms the prevailing IEEE 802.11 MAC protocols in not only energy conservation but also network throughput. Using the Dynamic Neighbor Prediction (DNP), iMAC performs well in mobile scenes. To the best of our knowledge, iMAC is the first protocol that considers the performance deterioration of power-controlled MAC protocols in mobile scenes and then proposes a solution. Simulation results indicate that DNP is important and necessary for power-controlled MAC protocols in mobile ad hoc networks.

  8. An Empirical Study and some Improvements of the MiniMac Protocol for Secure Computation

    DEFF Research Database (Denmark)

    Damgård, Ivan Bjerre; Lauritsen, Rasmus; Toft, Tomas

    2014-01-01

    (nicknamed MiniMac). While TinyOT has already been implemented, we present in this paper the first implementation of MiniMac, using the same platform as the existing TinyOT implementation. We also suggest several improvements of MiniMac, both on the protocol design and implementation level. In particular, we...... suggest a modification of MiniMac that achieves increased parallelism at no extra communication cost. This gives an asymptotic improvement of the original protocol as well as an 8-fold speed-up of our implementation. We compare the resulting protocol to TinyOT for the case of secure computation in parallel...

  9. PA-MAC:A Passive Asynchronous MAC Protocol for Low Duty-Cycled Wireless Sensor Networks%PA-MAC:一种被动的异步低占空比无线传感器网络MAC协议

    Institute of Scientific and Technical Information of China (English)

    唐震洲; 施晓秋; 金可仲

    2011-01-01

    空闲侦听是无线传感器网络能耗的主要原因之一,而占空比机制是减少空闲侦听能量损耗最主要的方法之一.提出了一种新的无线传感器网络异步MAC协议,称为PA-MAC(Passive Asynchronous MAC),即被动异步MAC.PA-MAC通过采用接收方发起数据传输机制、异步占空比机制以及节点唤醒时间估计机制,降低了节点的工作占空比,提高了网络的能量有效性.在NS2网络仿真平台上对PA-MAC的性能进行了评估.仿真结果表明,在保持网络性能的前提下,PA-MAC能够进一步降低节点工作的占空比,进而减少节点的能耗.%The problem of idle listening is one of the most concerned issues in wireless sensor networks, and the duty cycling mechanism is widely used to reduce energy consumption. We present a new asynchronous MAC protocol, called Passive-Asynchronous MAC (PA-MAC). PA-MAC uses receiver-initiated data transmission scheme, asynchronous duty cycling mechanism and awakening time estimation scheme to achieve low duty cycle and high energy efficiency. Simulations have been done to evaluate the performance of the proposed new protocol, by which we can find out that,on the premise of keeping the network performance,PA-MAC can further reduce the nodes' duty cycle ,thereby reduce the energy consumption.

  10. Realization of a single image haze removal system based on DaVinci DM6467T processor

    Science.gov (United States)

    Liu, Zhuang

    2014-10-01

    Video monitoring system (VMS) has been extensively applied in domains of target recognition, traffic management, remote sensing, auto navigation and national defence. However the VMS has a strong dependence on the weather, for instance, in foggy weather, the quality of images received by the VMS are distinct degraded and the effective range of VMS is also decreased. All in all, the VMS performs terribly in bad weather. Thus the research of fog degraded images enhancement has very high theoretical and practical application value. A design scheme of a fog degraded images enhancement system based on the TI DaVinci processor is presented in this paper. The main function of the referred system is to extract and digital cameras capture images and execute image enhancement processing to obtain a clear image. The processor used in this system is the dual core TI DaVinci DM6467T - ARM@500MHz+DSP@1GH. A MontaVista Linux operating system is running on the ARM subsystem which handles I/O and application processing. The DSP handles signal processing and the results are available to the ARM subsystem in shared memory.The system benefits from the DaVinci processor so that, with lower power cost and smaller volume, it provides the equivalent image processing capability of a X86 computer. The outcome shows that the system in this paper can process images at 25 frames per second on D1 resolution.

  11. Autonomous Power Control MAC Protocol for Mobile Ad Hoc Networks

    Directory of Open Access Journals (Sweden)

    2006-01-01

    Full Text Available Battery energy limitation has become a performance bottleneck for mobile ad hoc networks. IEEE 802.11 has been adopted as the current standard MAC protocol for ad hoc networks. However, it was developed without considering energy efficiency. To solve this problem, many modifications on IEEE 802.11 to incorporate power control have been proposed in the literature. The main idea of these power control schemes is to use a maximum possible power level for transmitting RTS/CTS and the lowest acceptable power for sending DATA/ACK. However, these schemes may degrade network throughput and reduce the overall energy efficiency of the network. This paper proposes autonomous power control MAC protocol (APCMP, which allows mobile nodes dynamically adjusting power level for transmitting DATA/ACK according to the distances between the transmitter and its neighbors. In addition, the power level for transmitting RTS/CTS is also adjustable according to the power level for DATA/ACK packets. In this paper, the performance of APCMP protocol is evaluated by simulation and is compared with that of other protocols.

  12. Learning Microsoft Excel 2011 for Mac video training DVD

    CERN Document Server

    Vaccaro, Guy

    2011-01-01

    In this video tutorial for Microsoft Excel 2011 For Mac, expert author Guy Vaccaro teaches you to effectively utilize the features and functions of Excel through project based learning. You will complete various projects, and along they way learn to leverage the power of the most important features Excel 2011 has to offer the Mac user. Starting your training course with the creation of a spreadsheet to record and monitor sales data, you will learn the basics of what you can do with a spreadsheet. You will then move on to creating a Profit and Loss report, learning formulas along the way. Moving to score sheets for a sports day, you will discover conditional based formatting, lookups, and more. You then create a functional expense claim form, advancing your Excel expertise. Moving on to a sales contact management sheet, you will discover how you can manipulate text, and even create mail merges from Excel. Finally, you will utilize all your knowledge thus far to create a sales report, including charts, pivot ta...

  13. MAC Layer Resource Allocation for Wireless Body Area Networks

    Institute of Scientific and Technical Information of China (English)

    Qinghua Shen; Xuemin Sherman Shen; Tom HLuan; Jing Liu

    2014-01-01

    Wireless body area networks (WBANs) can provide low-cost, timely healthcare services and are expected to be widely used for e-healthcare in hospitals. In a hospital, space is often limited and multiple WBANs have to coexist in an area and share the same channel in order to provide healthcare services to different patients. This causes severe interference between WBANs that could significantly reduce the network throughput and increase the amount of power consumed by sensors placed on the body. There-fore, an efficient channel-resource allocation scheme in the medium access control (MAC) layer is crucial. In this paper, we devel-op a centralized MAC layer resource allocation scheme for a WBAN. We focus on mitigating the interference between WBANs and reducing the power consumed by sensors. Channel and buffer state are reported by smartphones deployed in each WBAN, and channel access allocation is performed by a central controller to maximize network throughput. Sensors have strict limitations in terms of energy consumption and computing capability and cannot provide all the necessary information for channel allocation in a timely manner. This deteriorates network performance. We exploit the temporal correlation of the body area channel in order to minimize the number of channel state reports necessary. We view the network design as a partly observable optimization prob-lem and develop a myopic policy, which we then simulate in Matlab.

  14. A Review of MAC Scheduling Algorithms in LTE System

    Directory of Open Access Journals (Sweden)

    Satheesh Monikandan B

    2017-06-01

    Full Text Available The recent wireless communication networks rely on the new technology named Long Term Evolution (LTE to offer high data rate real-time (RT traffic with better Quality of Service (QoS for the increasing demand of customer requirement. LTE provide low latency for real-time services with high throughput, with the help of two-level packet retransmission. Hybrid Automatic Repeat Request (HARQ retransmission at the Medium Access Control (MAC layer of LTE networks achieves error-free data transmission. The performance of the LTE networks mainly depends on how effectively this HARQ adopted in the latest communication standard, Universal Mobile Telecommunication System (UMTS. The major challenge in LTE is to balance QoS and fairness among the users. Hence, it is very essential to design a down link scheduling scheme to get the expected service quality to the customers and to utilize the system resources efficiently. This paper provides a comprehensive literature review of LTE MAC layer and six types of QoS/Channel-aware downlink scheduling algorithms designed for this purpose. The contributions of this paper are to identify the gap of knowledge in the downlink scheduling procedure and to point out the future research direction. Based on the comparative study of algorithms taken for the review, this paper is concluded that the EXP Rule scheduler is most suited for LTE networks due to its characteristics of less Packet Loss Ratio (PLR, less Packet Delay (PD, high throughput, fairness and spectral efficiency.

  15. Mac-1 deficiency induces respiratory failure by affecting type I alveolar epithelial cells.

    Science.gov (United States)

    Wang, J; Ci, Y B; Liu, C L; Sun, H M

    2017-08-31

    As a β2 integrin family member, Mac-1 plays an important role in the inflammatory response. Inflammation and lung injury are closely associated, but the involvement of Mac-1 in the occurrence and development of such pathologies remains poorly understood. We aimed to investigate the relationship between Mac-1 deficiency and respiratory failure in Mac-1 knockout {Mac-1(-/-)} mice, using C57BL/6J mice as a control. The newborn survival rate of Mac-1(-/-) mice was calculated, and mouse lung tissue was treated with hematoxylin and eosin and subjected to immunofluorescent staining. Moreover, western blotting and immunohistochemistry were used to detect the expression of molecules specific to type I and type II alveolar epithelial cells, as well as alveolar surfactant proteins secreted by the latter. Survival of Mac-1(-/-) pups was significantly lower than that of newborn C57BL/6J mice. In a float test, lung tissues from C57BL/6J mice were buoyant, whereas those of Mac-1(-/-) mice were not. Compared with C57BL/6J mice, expression of proSP-C {specific to type II alveolar epithelial cells} and alveolar surfactant proteins in Mac-1(-/-) mice was not significantly different, implying that type II cell function was unaltered. However, western blotting revealed expression of T1α, Aqp5, and Snx5 {type I alveolar epithelial cell markers} in Mac-1(-/-) mice to be significantly decreased {P Mac-1 may play an important role in respiratory failure. Its absence leads to this condition not by influencing type II alveolar epithelial cells or their secreted surfactant proteins, but rather by reducing type I alveolar cell numbers.

  16. Evaluation of MERIS Case-II Water Processors in the Baltic Sea

    OpenAIRE

    Arroyo Pedrero, Jaume

    2009-01-01

    Projecte realitzat en col.laboració amb Helsinki University of Technology Four MERIS Case-II Water Processors are studied, compared and evaluated: Coastal Case 2 Regional Processor, Boreal Lakes Processor, Eutrophic Lakes Processor and FUB/Wew Water Processor. In situ data from the Baltic Sea have been used to evaluate the water constituent estimations. In addition, the effect of adjacency effect ICOL on the estimation has been analyzed. For this purpose, a set of tools has been d...

  17. THOR Fields and Wave Processor - FWP

    Science.gov (United States)

    Soucek, Jan; Rothkaehl, Hanna; Ahlen, Lennart; Balikhin, Michael; Carr, Christopher; Dekkali, Moustapha; Khotyaintsev, Yuri; Lan, Radek; Magnes, Werner; Morawski, Marek; Nakamura, Rumi; Uhlir, Ludek; Yearby, Keith; Winkler, Marek; Zaslavsky, Arnaud

    2017-04-01

    If selected, Turbulence Heating ObserveR (THOR) will become the first spacecraft mission dedicated to the study of plasma turbulence. The Fields and Waves Processor (FWP) is an integrated electronics unit for all electromagnetic field measurements performed by THOR. FWP will interface with all THOR fields sensors: electric field antennas of the EFI instrument, the MAG fluxgate magnetometer, and search-coil magnetometer (SCM), and perform signal digitization and on-board data processing. FWP box will house multiple data acquisition sub-units and signal analyzers all sharing a common power supply and data processing unit and thus a single data and power interface to the spacecraft. Integrating all the electromagnetic field measurements in a single unit will improve the consistency of field measurement and accuracy of time synchronization. The scientific value of highly sensitive electric and magnetic field measurements in space has been demonstrated by Cluster (among other spacecraft) and THOR instrumentation will further improve on this heritage. Large dynamic range of the instruments will be complemented by a thorough electromagnetic cleanliness program, which will prevent perturbation of field measurements by interference from payload and platform subsystems. Taking advantage of the capabilities of modern electronics and the large telemetry bandwidth of THOR, FWP will provide multi-component electromagnetic field waveforms and spectral data products at a high time resolution. Fully synchronized sampling of many signals will allow to resolve wave phase information and estimate wavelength via interferometric correlations between EFI probes. FWP will also implement a plasma resonance sounder and a digital plasma quasi-thermal noise analyzer designed to provide high cadence measurements of plasma density and temperature complementary to data from particle instruments. FWP will rapidly transmit information about magnetic field vector and spacecraft potential to the

  18. Digital signal processor for silicon audio playback devices; Silicon audio saisei kikiyo digital signal processor

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital audio signal processor (DSP) TC9446F series has been developed silicon audio playback devices with a memory medium of, e.g., flash memory, DVD players, and AV devices, e.g., TV sets. It corresponds to AAC (advanced audio coding) (2ch) and MP3 (MPEG1 Layer3), as the audio compressing techniques being used for transmitting music through an internet. It also corresponds to compressed types, e.g., Dolby Digital, DTS (digital theater system) and MPEG2 audio, being adopted for, e.g., DVDs. It can carry a built-in audio signal processing program, e.g., Dolby ProLogic, equalizer, sound field controlling, and 3D sound. TC9446XB has been lined up anew. It adopts an FBGA (fine pitch ball grid array) package for portable audio devices. (translated by NEDO)

  19. Alternative self-dual gravity in eight dimensions

    Science.gov (United States)

    Nieto, J. A.

    2016-07-01

    We develop an alternative Ashtekar formalism in eight dimensions. In fact, using a MacDowell-Mansouri physical framework and a self-dual curvature symmetry, we propose an action in eight dimensions in which the Levi-Civita tenor with eight indices plays a key role. We explicitly show that such an action contains number of linear, quadratic and cubic terms in the Riemann tensor, Ricci tensor and scalar curvature. In particular, the linear term is reduced to the Einstein-Hilbert action with cosmological constant in eight dimensions. We prove that such a reduced action is equivalent to the Lovelock action in eight dimensions.

  20. Alternative Self-dual Gravity in Eight Dimensions

    CERN Document Server

    Nieto, J A

    2016-01-01

    We develop an alternative Ashtekar formalism in eight dimensions. In fact, using a MacDowell-Mansouri physical framework and a self-dual curvature symmetry we propose an action in eight dimensions in which the Levi-Civita tenor with eight indices plays a key role. We explicitly show that such an action contains number of linear, quadratic and cubic terms in the Riemann tensor, Ricci tensor and scalar curvature. In particular, the linear term is reduced to the Einstein-Hilbert action with cosmological constant in eight dimensions. We prove that such a reduced action is equivalent to the Lovelock action in eight dimensions.