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Sample records for lsi-11 processor family

  1. Support and utilization of the LSI-11 processor family at SLAC

    International Nuclear Information System (INIS)

    Kieffer, J.; Logg, C.A.; Farwell, D.E.

    1981-01-01

    Microcomputer systems based on the DEC LSI-11 processor family have been in use at SLAC for five years. They are used for a wide variety of applications. The support of these systems is divided into three general areas: engineering, maintenance, and software. Engineering specifies the system to match user requirements. SLAC has been able to design one general purpose system which can be tailored to fit many specific requirements. Maintenance provides system and component diagnostic services and repair. Software support includes software consulting services, assistance in systems design, and the development and support of special purpose operating systems and programs. These support functions are handled as subtasks by three teams in the SLAC Electronics Instrumentation Group. Each of these teams utilizes several LSI-11 systems in the performance of its primary tasks. They work closely together to jointly provide overall support for the larger SLAC community

  2. The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

    International Nuclear Information System (INIS)

    Clark, D.L.

    1983-01-01

    The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

  3. CAMAC serial highway interface for the LSI-11

    International Nuclear Information System (INIS)

    Lau, N.H.

    1980-01-01

    A CAMAC Serial Highway Interface has been designed for the Local Control and Instrumentation System of the Mirror Fusion Test Facility. There are over 50 distinguishable systems in the facility, each of which consists of the LSI-11 computer, fiber optic communication links, and the CAMAC system. The LSI-11 computer includes a 32k memory, serial modem interface and the CAMAC Serial Highway Interface

  4. LSI-11 based multiparameter system

    International Nuclear Information System (INIS)

    Patwardhan, P.K.; Chatur, C.G.; Gupta, J.D.; Kumar, Sudhir

    1981-01-01

    This paper describes a LSI-11 based nuclear data processing system having four parameter capability. The system features simultaneous data acquisition and processing in independent memory zones. It also incorporates useful resident application programs and a built-in dual trace display. (author)

  5. Simplified extension of the LSI-11 Q-Bus for a high energy laser control application

    International Nuclear Information System (INIS)

    Burczyk, L.

    1981-01-01

    Antares, a large, experimental laser fusion facility under construction at Los Alamos National Laboratory in New Mexico, is controlled by a network of PDP-11 minicomputers and microprocessors. The remote nodes of the Antares control network are based on an LSI-11/2 microcomputer interfaced to an STD Bus. This machine interface or MI forms the intelligent process controller located directly adjacent to the many diverse laser subsystem devices. The STD Bus, linked to the LSI-11/2 microcomputer, offers a standardized, cost effective means for the development of the specialized interface functions required for the high energy laser environment

  6. LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

    Energy Technology Data Exchange (ETDEWEB)

    Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

    1984-01-01

    Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

  7. Atomic absorption spectrometer readout and data reduction using the LSI-11 microcomputer

    International Nuclear Information System (INIS)

    Allen, M.J.; Wikkerink, R.W.

    1978-01-01

    Some common instruments found in the chemistry laboratory have analog chart recorder output as their primary data readout media. Data reduction from this medium is slow and relatively inaccurate. This paper describes how to interface a single LSI-11 microcomputer to PERKIN-ELMER models 603 and 303 Atomic Absorption Spectrophotometers

  8. Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

    Science.gov (United States)

    Lindgren, R. W.; Tarbell, T. D.

    1981-01-01

    The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

  9. A discussion of tools and techniques for distributed processor based control systems using CAMAC

    International Nuclear Information System (INIS)

    Tippie, J.W.; Scandora, A.E.

    1985-01-01

    This paper describes and analyzes various distributed processor architectures using commercially available CAMAC components. The general orientation is toward distributed control systems using Digital Equipment Corporation LSI11 processors in a CAMAC environment. The paper describes in detail software tools available to simplify the development of applications software and to provide a high-level runtime environment both at the host and the remote processors. Discussion focuses on techniques for downloading of operating systems from a large host and applications tasks written in high-level languages. It also discusses software tools which enable tasks in the remote processors to exchange messages and data with tasks in the host in a simple and elegant way

  10. MIL-STD-1553B Marconi LSI chip set in a remote terminal application

    Science.gov (United States)

    Dimarino, A.

    1982-11-01

    Marconi Avionics is utilizing the MIL-STD-1553B LSI Chip Set in the SCADC Air Data Computer application to perform all of the required remote terminal MIL-STD-1553B protocol functions. Basic components of the RTU are the dual redundant chip set, CT3231 Transceivers, 256 x 16 RAM and a Z8002 microprocessor. Basic transfers are to/from the RAM command of the bus controller or Z8002 processor. During transfers from the processor to the RAM, the chip set busy bit is set for a period not exceeding 250 microseconds. When the transfer is complete, the busy bit is released and transfers to the data bus occur on command. The LSI Chip Set word count lines are used to locate each data word in the local memory and 4 mode codes are used in the application: reset remote terminal, transmit status word, transmitter shut-down, and override transmitter shutdown.

  11. VON WISPR Family Processors: Volume 1

    National Research Council Canada - National Science Library

    Wagstaff, Ronald

    1997-01-01

    ...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

  12. FY1995 four-terminal-device intelligent LSI system for real-time event recognition; 1995 nendo shunji ninshiki kino wo motta 4 tanshi device chino LSI no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    Development of an intelligent LSI system having real-time response capability for real-word events. This is accomplished by enhancing the functionality of an elemental device, employing ultra-fine-grain parallelism and merging software directly in the LSI hardware. Intelligent functions are created directly on the LSI hardware, thus enabling real-time recognition by electronic systems. The origin of human intelligence lies in the huge memory data base acquired through one's life and the very fast search mechanism to recall the 'most similar' event to the current input. Based on this principle components of intelligent LSI systems have been developed. An analog EEPROM technology capable of storing 256 levels of data per cell without time-consuming write/verify operations has been developed. In situ monitoring of memory content during writing has allowed us high-accuracy data writing. A high-speed parallel-search engine for the minimum distance vector (an associator) has been developed using neuron MOS technology. The associator has been applied to the motion vector detector as an example, which has shown a very fast detection with an extremely simple hardware configuration. The association architecture has been applied to a real-time motion picture compression system, demonstrating three orders of magnitude higher performance than typical CISC processors (Pentium 166MHz). (NEDO)

  13. Simulation of LSI-11/PDP-11 series minicomputers

    International Nuclear Information System (INIS)

    Myers, J.R.; Cottrell, R.L.A.; Bricaud, B.M.

    1979-04-01

    A functional simulation of te PDP-11 series minicomputers was implemented to run either interactively or as a batch job on an IBM 370 computer. The simulator operates in two modes, the supervisor mode and the run mode. In the supervisor mode, the simulator implements a command language, which allows users to examine and change the contents of memory or other addressable registers in the simulated machine. Optionally, an instruction trace may also be turned on or off. In the run mode, the simulation of the instruction set is tested by successfully running DEC's MAINDEC basic instruction test on the simulated machine. The interrupt structure is modeled. The simulation is open ended in the sense that users may define new peripheral devices, by including their own FORTRAN callable subroutines for each simulated device. Currently the following devices are supported: floppy disks, a console terminal, a card reader, a card punch, a line printer, and a communications multiplexer (DH11). With these devices DEC's RT-11 versions 2C and 3B have been successfully run on the simulator. At SLAC this simulator is proving useful in debugging software for one-of-a-kind hardware configurations, such as communications front end processors, that are not readily accessible for stand alone testing. 5 figures

  14. FY1995 four-terminal-device intelligent LSI system for real-time event recognition; 1995 nendo shunji ninshiki kino wo motta 4 tanshi device chino LSI no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    Development of an intelligent LSI system having real-time response capability for real-word events. This is accomplished by enhancing the functionality of an elemental device, employing ultra-fine-grain parallelism and merging software directly in the LSI hardware. Intelligent functions are created directly on the LSI hardware, thus enabling real-time recognition by electronic systems. The origin of human intelligence lies in the huge memory data base acquired through one's life and the very fast search mechanism to recall the 'most similar' event to the current input. Based on this principle components of intelligent LSI systems have been developed. An analog EEPROM technology capable of storing 256 levels of data per cell without time-consuming write/verify operations has been developed. In situ monitoring of memory content during writing has allowed us high-accuracy data writing. A high-speed parallel-search engine for the minimum distance vector (an associator) has been developed using neuron MOS technology. The associator has been applied to the motion vector detector as an example, which has shown a very fast detection with an extremely simple hardware configuration. The association architecture has been applied to a real-time motion picture compression system, demonstrating three orders of magnitude higher performance than typical CISC processors (Pentium 166MHz). (NEDO)

  15. Analysis list: lsy-2 [Chip-atlas[Archive

    Lifescience Database Archive (English)

    Full Text Available lsy-2 Embryo,Larvae + ce10 http://dbarchive.biosciencedbc.jp/kyushu-u/ce10/target/l...sy-2.1.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/ce10/target/lsy-2.5.tsv http://dbarchive.biosciencedbc....jp/kyushu-u/ce10/target/lsy-2.10.tsv http://dbarchive.biosciencedbc.jp/kyushu-u/ce10/colo/lsy-2.Embryo.tsv,http://dbarchive.bioscien...cedbc.jp/kyushu-u/ce10/colo/lsy-2.Larvae.tsv http://dbarchive.bioscience...dbc.jp/kyushu-u/ce10/colo/Embryo.gml,http://dbarchive.biosciencedbc.jp/kyushu-u/ce10/colo/Larvae.gml ...

  16. 3D-LSI technology for image sensor

    International Nuclear Information System (INIS)

    Motoyoshi, Makoto; Koyanagi, Mitsumasa

    2009-01-01

    Recently, the development of three-dimensional large-scale integration (3D-LSI) technologies has accelerated and has advanced from the research level or the limited production level to the investigation level, which might lead to mass production. By separating 3D-LSI technology into elementary technologies such as (1) through silicon via (TSV) formation, (2) bump formation, (3) wafer thinning, (4) chip/wafer alignment, and (5) chip/wafer stacking and reconstructing the entire process and structure, many methods to realize 3D-LSI devices can be developed. However, by considering a specific application, the supply chain of base wafers, and the purpose of 3D integration, a few suitable combinations can be identified. In this paper, we focus on the application of 3D-LSI technologies to image sensors. We describe the process and structure of the chip size package (CSP), developed on the basis of current and advanced 3D-LSI technologies, to be used in CMOS image sensors. Using the current LSI technologies, CSPs for 1.3 M, 2 M, and 5 M pixel CMOS image sensors were successfully fabricated without any performance degradation. 3D-LSI devices can be potentially employed in high-performance focal-plane-array image sensors. We propose a high-speed image sensor with an optical fill factor of 100% to be developed using next-generation 3D-LSI technology and fabricated using micro(μ)-bumps and micro(μ)-TSVs.

  17. Multi-valued LSI/VLSI logic design

    Science.gov (United States)

    Santrakul, K.

    A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

  18. Real-time interferometer phase detection using an LSI-11 microcomputer and high-speed digital techniques

    International Nuclear Information System (INIS)

    Mendell, D.S.

    1978-01-01

    This paper describes the basic design and philosophy of a real-time, interferometer phase-detection system used on the 2XIIB and TMX magnetic-fusion experiments at the Lawrence Livermore Laboratory. This diagnostics system is now a satellite to a host computer and uses high-speed, emitter-coupled logic techniques to derive data on real-time phase relationships. The system's input signals can be derived from interferometer outputs over a wide range of reference frequencies. An LSI-11 microcomputer is the interface between the high-speed phase-detection logic, buffer memory, human interaction, and host computer. Phase data on a storage CRT is immediately displayed after each experimental fusion shot. An operator can interrogate this phase data more closely from an interactive control panel, while the host computer is simultaneously examining the system's buffer memory or arming the system for the next shot

  19. Intelligent trigger processor for the crystal box

    International Nuclear Information System (INIS)

    Sanders, G.H.; Butler, H.S.; Cooper, M.D.

    1981-01-01

    A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering

  20. LSI/CAMAC system for heavy elements research

    International Nuclear Information System (INIS)

    Watkins, E.D.; Dougan, R.J.; McQuaid, J.H.

    1985-01-01

    We have developed a LSI-11/23 computer-driven CAMAC data acquisition system. The 64 silicon-detector system is being used to investigate the alpha and spontaneous fission activities of short-lived transfermium isotopes by the real-time monitoring of the mother-daughter alpha decay sequence. A unique modular pulse processing electronics system was designed to simplify set up and calibration. The computer adjusts the gain of the CAMAC shaping amplifiers enabling the calibration and alignment of all 64 of the 1 k alpha spectra to within 0.5 channel in less than 10 minutes

  1. Single event effects and performance predictions for space applications of RISC processors

    International Nuclear Information System (INIS)

    Kimbrough, J.R.; Colella, N.J.; Denton, S.M.; Shaeffer, D.L.; Shih, D.; Wilburn, J.W.; Coakley, P.G.; Casteneda, C.; Koga, R.; Clark, D.A.; Ullmann, J.L.

    1994-01-01

    Proton and ion Single Event Phenomena (SEP) tests were performed on 32-b processors including R3000A's from all commercial manufacturers along with the Performance PR3400 family, Integrated Device Technology Inc. 79R3081, LSI Logic Corporation LR33000HC, and Intel i80960MX parts. The microprocessors had acceptable upset rates for operation in a low earth orbit or a lunar mission such as CLEMENTINE with a wide range in proton total dose failure. Even though R3000A devices are 60% smaller in physical area than R3000 devices, there was a 340% increase in device Single Event Upset (SEU) cross section. Software tests of varying complexity demonstrate that registers and other functional blocks using register architecture dominate the cross section. The current approach of giving a single upset cross section can lead to erroneous upset rates depending on the application software

  2. Essential knowledge for transistor-level LSI circuit design

    CERN Document Server

    Nakura, Toru

    2016-01-01

    This book is a collection of the miscellaneous knowledge essential for transistor-level LSI circuit design, summarized as the issues that need to be considered in each design step. To design an LSI that actually functions and to be able to properly measure it, an extremely large amount of diverse, detailed knowledge is necessary. Even though one may read a textbook about an op-amp, for example, the op-amp circuit design may not actually be possible to complete in one’s CAD tools. The first half of this text explains important design issues such as the operating principles of CAD tools, including schematic entry, SPICE simulation, layout and verification, and RC extraction. Then, mistake-prone topics for many circuit design beginners, resulting from their lack of consideration of these subjects, are explained including IO buffers, noise, and problems due to the progress of miniaturization. Following these topics, basic but very specialized issues for LSI circuit measurement are explained including measuremen...

  3. A ferroelectric memory technology for embedded LSI

    CERN Document Server

    Kunio, T

    1999-01-01

    We have developed an FeRAM (Ferroelectric Random Access Memory) embedded smart card LSI by using double metal 0.8- mu m CMOS technology. The smart-card has a 256-byte FeRAM macro and an 8-bit microcontroller. The FeRAM macro has the $9 performance of 10/sup 8/ endurance cycles and is half the size of an EEPROM macro. We have also developed a new CMVP (Capacitor on Meta/Via Stacked Plug) cell for an advanced FeRAM embedded LSI by using 0.25- mu m CMOS technology. $9 The ferroelectric capacitors of this cell are fabricated after the multiple interconnect is formed, and a cell area of 3.2 mu m/sup 2/ is obtained. (8 refs).

  4. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  5. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  6. Custom LSI plus hybrid equals cost effectiveness

    Science.gov (United States)

    Friedman, S. N.

    The possibility to combine various technologies, such as Bi-Polar linear and CMOS/Digital makes it feasible to create systems with a tailored performance not available on a single monolithic circuit. The custom LSI 'BLOCK', especially if it is universal in nature, is proving to be a cost effective way for the developer to improve his product. The custom LSI represents a low price part in contrast to the discrete components it will replace. In addition, the hybrid assembly can realize a savings in labor as a result of the reduced parts handling and associated wire bonds. The possibility of the use of automated system manufacturing techniques leads to greater reliability as the human factor is partly eliminated. Attention is given to reliability predictions, cost considerations, and a product comparison study.

  7. Distance and total column density to the periodic radio star LSI + 61 deg 303

    International Nuclear Information System (INIS)

    Frail, D.A.; Hjellming, R.M.

    1991-01-01

    New observations toward the periodic radio star LSI + 61 deg 303 in the lines of H I at 21 cm and CO-18 at 2.7 mm are reported. Using the kinematic method, H I observations are interpreted in terms of the two-armed spiral shock model of Roberts (1972) to derive a distance to LSI + 61 deg 303 of 2.0 + or - 0.2 kpc. The results clearly show the presence of the Perseus arm shock and locate LSI + 61 deg 303 between this shock and the more distant postshock gas. In addition, by using the H I and CO-18 data, the total neutral and molecular gas column density is derived along the line of sight toward LSI + 61 deg 303. 32 refs

  8. CRI, 4-Processor VAX-11/780 Simulation of CRAY Multitasking System

    International Nuclear Information System (INIS)

    Werner, N.E.; Van Matre, S.W.

    1988-01-01

    1 - Description of program or function: CRI is a subroutine library and set of utilities which allow the use of a four-processor shared memory DEC VAX11/780-4 computer for parallel processing in a manner compatible with the present use of Cray Research, Inc.'s (CRI's) multitasking primitives on Cray computers. Included in the library are subroutines to perform resource initialization, task functions, lock operations, event signals, file sharing, and work queueing synchronization. 2 - Method of solution: A task consists of code and data that can be scheduled for execution on a CPU. Locks are the facility for monitoring critical regions of code. Events allow signaling between tasks; they have two states: cleared and posted. Posting an event allows all other tasks waiting on that event to resume execution. The CRI utilities consist of command procedures for creating the files needed to use the shared memory; for compiling and liking a multitasking program; for starting the logical processors on the physical processors after the time specified by submitting the job(s) to the selected generic batch queue and, optionally, interactively relinquishing control to the multiprocessor debugger; and for removing jobs from the batch queue and, optionally, un-mapping specified global sections from shared memory. CRIDEBUG utility does not work properly in this release

  9. Analyzing CMOS/SOS fabrication for LSI arrays

    Science.gov (United States)

    Ipri, A. C.

    1978-01-01

    Report discusses set of design rules that have been developed as result of work with test arrays. Set of optimum dimensions is given that would maximize process output and would correspondingly minimize costs in fabrication of large-scale integration (LSI) arrays.

  10. Investigation of transient thermal dissipation in thinned LSI for advanced packaging

    Science.gov (United States)

    Araga, Yuuki; Shimamoto, Haruo; Melamed, Samson; Kikuchi, Katsuya; Aoyagi, Masahiro

    2018-04-01

    Thinning of LSI is necessary for superior form factor and performance in dense cutting-edge packaging technologies. At the same time, degradation of thermal characteristics caused by the steep thermal gradient on LSIs with thinned base silicon is a concern. To manage a thermal environment in advanced packages, thermal characteristics of the thinned LSIs must be clarified. In this study, static and dynamic thermal dissipations were analyzed before and after thinning silicon to determine variations of thermal characteristics in thinned LSI. Measurement results revealed that silicon thinning affects dynamic thermal characteristics as well as static one. The transient variations of thermal characteristics of thinned LSI are precisely verified by analysis using an equivalent model based on the thermal network method. The results of analysis suggest that transient thermal characteristics can be easily estimated by employing the equivalent model.

  11. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  12. Multi-processor data acquisition and monitoring systems for particle physics

    International Nuclear Information System (INIS)

    White, V.; Burch, B.; Eng, K.; Heinicke, P.; Pyatetsky, M.; Ritchie, D.

    1983-01-01

    A high speed distributed processing system, using PDP-11 and VAX processors, is being developed at Fermilab. The acquisition of data is done using one or more PDP-11s. Additional processors are connected to provide either data logging or extra data analysis capabilities. Within this framework, functional interchangeability of PDP-11 and VAX processors and of the PDP-11 operating systems, RT-11 and RSX-11M, has been maintained. Inter-processor connections have been implemented in a general way using the 5 megabit DR11-W hardware currently selected for the purpose. Using this approach the authors have been able to make use of several existing data acquisition and analysis packages, such as RT/MULTI, in a multi-processor system

  13. Integrated electric circuit engineering system in LSI design center, Konami Kogyo Co. Ltd

    Energy Technology Data Exchange (ETDEWEB)

    Kamitsuki, Kagehiko; Tanaka, Tomiaki

    1988-08-26

    Development of the integrated engineering system is presented which designs and manufactures the hardwares, softwares and cases of electronic game products with LSI integratedly as an experiment. The system is intended to reduce the number of each development of the parts, to verify each other by comparing each parts with the product concept during the development, to reduce modifications, and to shorten development periods. The main subsystems are an electric circuit CAD for LSI designs and a mechanical CAD for case or printed circuit board designs. The LSI development period has been shortened up to one month by a larger capacity computer and higher speed simulator, and the electric circuit engineering system capable of keeping step with the software development has been approximately completed. In the future, the system will be intended to introduce an expert system or a visual system capable of predicting the final product during a logical design period. (10 figs, 1 photo)

  14. An Analytical Approach for Fast Recovery of the LSI Properties in Magnetic Particle Imaging

    Directory of Open Access Journals (Sweden)

    Hamed Jabbari Asl

    2016-01-01

    Full Text Available Linearity and shift invariance (LSI characteristics of magnetic particle imaging (MPI are important properties for quantitative medical diagnosis applications. The MPI image equations have been theoretically shown to exhibit LSI; however, in practice, the necessary filtering action removes the first harmonic information, which destroys the LSI characteristics. This lost information can be constant in the x-space reconstruction method. Available recovery algorithms, which are based on signal matching of multiple partial field of views (pFOVs, require much processing time and a priori information at the start of imaging. In this paper, a fast analytical recovery algorithm is proposed to restore the LSI properties of the x-space MPI images, representable as an image of discrete concentrations of magnetic material. The method utilizes the one-dimensional (1D x-space imaging kernel and properties of the image and lost image equations. The approach does not require overlapping of pFOVs, and its complexity depends only on a small-sized system of linear equations; therefore, it can reduce the processing time. Moreover, the algorithm only needs a priori information which can be obtained at one imaging process. Considering different particle distributions, several simulations are conducted, and results of 1D and 2D imaging demonstrate the effectiveness of the proposed approach.

  15. 3081/E processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.

    1984-04-01

    The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

  16. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

    1983-01-01

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  17. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  18. Quantitative assessment of graded burn wounds using a commercial and research grade laser speckle imaging (LSI) system

    Science.gov (United States)

    Ponticorvo, A.; Rowland, R.; Yang, B.; Lertsakdadet, B.; Crouzet, C.; Bernal, N.; Choi, B.; Durkin, A. J.

    2017-02-01

    Burn wounds are often characterized by injury depth, which then dictates wound management strategy. While most superficial burns and full thickness burns can be diagnosed through visual inspection, clinicians experience difficulty with accurate diagnosis of burns that fall between these extremes. Accurately diagnosing burn severity in a timely manner is critical for starting the appropriate treatment plan at the earliest time points to improve patient outcomes. To address this challenge, research groups have studied the use of commercial laser Doppler imaging (LDI) systems to provide objective characterization of burn-wound severity. Despite initial promising findings, LDI systems are not commonplace in part due to long acquisition times that can suffer from artifacts in moving patients. Commercial LDI systems are being phased out in favor of laser speckle imaging (LSI) systems that can provide similar information with faster acquisition speeds. To better understand the accuracy and usefulness of commercial LSI systems in burn-oriented research, we studied the performance of a commercial LSI system in three different sample systems and compared its results to a research-grade LSI system in the same environments. The first sample system involved laboratory measurements of intralipid (1%) flowing through a tissue simulating phantom, the second preclinical measurements in a controlled burn study in which wounds of graded severity were created on a Yorkshire pig, and the third clinical measurements involving a small sample of clinical patients. In addition to the commercial LSI system, a research grade LSI system that was designed and fabricated in our labs was used to quantitatively compare the performance of both systems and also to better understand the "Perfusion Unit" output of commercial systems.

  19. Limnological state index (LSI) to evaluate ecological conditions of the Canal del Dique wetlands, Colombia

    International Nuclear Information System (INIS)

    Pinilla A, Gabriel A; Duarte Coy, Juliana; Vega Mora, Leonel

    2010-01-01

    Determining the ecological state or health of an ecosystem offers useful tools for its management and conservation. In Colombia, indexes of aquatic systems that combine in a single parameter the physical, chemical and biological variables have not been published, and the evaluation of water bodies' ecological state has been fragmentary or incomplete. In this work a limnological state index (LSI) for wetlands of the Canal del Dique, ecosystems under constant pressure by the human communities, is presented. For the construction of this multi-metric index, graphs of quality of the selected variables were constructed and values of importance were assigned to them. The theory of the multi-attributes was used to construct the LSI, which considers 12 variables. A principal components analysis was realized with these chosen parameters. A simplified version was designed (partial LSI - PLSI) in which four of the biological variables were excluded. Finally, an interpretation scale of the values obtained with these indices was built. The LSI and the PLSI were applied to wetlands of the Canal del Dique to establish their current ecological condition. Data show that the limnological state of most wetlands is acceptable, which suggests that these lentic ecosystems are within tolerable limits of function, although they are not exempt from deterioration processes.

  20. VIRTUS: a multi-processor system in FASTBUS

    International Nuclear Information System (INIS)

    Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

    1986-01-01

    VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

  1. Bank switched memory interface for an image processor

    International Nuclear Information System (INIS)

    Barron, M.; Downward, J.

    1980-09-01

    A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

  2. Report on research achievements in fiscal 1999 on development of simulation technology related to behavior of LSI circuit (re-commissioned portion); 1999 nendo LSI kairo no kyodo ni kansuru simulation gijutsu kaihatsu seika hokokusho (saiitakubun)

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-03-01

    Development has been advanced on a new circuit design technology, in which the present digital circuit design performed according to the intensive circuit theory that regards reception and transmission of signals as migration of electrons is carried out by a new circuit theory centering on the intensive system (Quasi static closed circuit, QSCC) that regards reception and transmission of signals as propagation of wave motions. Studies required for structuring the QSCC theory were performed, such as verification of the reliability and effectiveness of the QSCC theory by means of the electro-magnetic field-circuit simulation and experiments and improvement of their completeness, development of the electro-magnetic field simulation technology required for the QSCC theory structuring, and development of a simple type design system based on the QSCC theory and a simple simulator for design verification. Specifically, the research and development on the eight items were carried out, including: 1) analysis of the generation and propagation mechanisms of electro-magnetic waves including those from LSI to circuit substrates, 2) analysis of electro-magnetic details of signals and power supply circuits including those from LSI to circuit substrates, 3) preparation of a library including the items from LSI to circuit substrates, and 4) development of a simulation technology including those from LSI to circuit substrates (QSCC designer). (NEDO)

  3. Screening and Expression of a Silicon Transporter Gene (Lsi1) in Wild-Type Indica Rice Cultivars

    Science.gov (United States)

    Abiri, Rambod; Kalhori, Nahid; Atabaki, Narges

    2017-01-01

    Silicon (Si) is one of the most prevalent elements in the soil. It is beneficial for plant growth and development, and it contributes to plant defense against different stresses. The Lsi1 gene encodes a Si transporter that was identified in a mutant Japonica rice variety. This gene was not identified in fourteen Malaysian rice varieties during screening. Then, a mutant version of Lsi1 was substituted for the native version in the three most common Malaysian rice varieties, MR219, MR220, and MR276, to evaluate the function of the transgene. Real-time PCR was used to explore the differential expression of Lsi1 in the three transgenic rice varieties. Silicon concentrations in the roots and leaves of transgenic plants were significantly higher than in wild-type plants. Transgenic varieties showed significant increases in the activities of the enzymes SOD, POD, APX, and CAT; photosynthesis; and chlorophyll content; however, the highest chlorophyll A and B levels were observed in transgenic MR276. Transgenic varieties have shown a stronger root and leaf structure, as well as hairier roots, compared to the wild-type plants. This suggests that Lsi1 plays a key role in rice, increasing the absorption and accumulation of Si, then alters antioxidant activities, and improves morphological properties. PMID:28191468

  4. Screening and Expression of a Silicon Transporter Gene (Lsi1 in Wild-Type Indica Rice Cultivars

    Directory of Open Access Journals (Sweden)

    Mahbod Sahebi

    2017-01-01

    Full Text Available Silicon (Si is one of the most prevalent elements in the soil. It is beneficial for plant growth and development, and it contributes to plant defense against different stresses. The Lsi1 gene encodes a Si transporter that was identified in a mutant Japonica rice variety. This gene was not identified in fourteen Malaysian rice varieties during screening. Then, a mutant version of Lsi1 was substituted for the native version in the three most common Malaysian rice varieties, MR219, MR220, and MR276, to evaluate the function of the transgene. Real-time PCR was used to explore the differential expression of Lsi1 in the three transgenic rice varieties. Silicon concentrations in the roots and leaves of transgenic plants were significantly higher than in wild-type plants. Transgenic varieties showed significant increases in the activities of the enzymes SOD, POD, APX, and CAT; photosynthesis; and chlorophyll content; however, the highest chlorophyll A and B levels were observed in transgenic MR276. Transgenic varieties have shown a stronger root and leaf structure, as well as hairier roots, compared to the wild-type plants. This suggests that Lsi1 plays a key role in rice, increasing the absorption and accumulation of Si, then alters antioxidant activities, and improves morphological properties.

  5. Screening and Expression of a Silicon Transporter Gene (Lsi1) in Wild-Type Indica Rice Cultivars.

    Science.gov (United States)

    Sahebi, Mahbod; Hanafi, Mohamed M; Rafii, M Y; Azizi, Parisa; Abiri, Rambod; Kalhori, Nahid; Atabaki, Narges

    2017-01-01

    Silicon (Si) is one of the most prevalent elements in the soil. It is beneficial for plant growth and development, and it contributes to plant defense against different stresses. The Lsi1 gene encodes a Si transporter that was identified in a mutant Japonica rice variety. This gene was not identified in fourteen Malaysian rice varieties during screening. Then, a mutant version of Lsi1 was substituted for the native version in the three most common Malaysian rice varieties, MR219, MR220, and MR276, to evaluate the function of the transgene. Real-time PCR was used to explore the differential expression of Lsi1 in the three transgenic rice varieties. Silicon concentrations in the roots and leaves of transgenic plants were significantly higher than in wild-type plants. Transgenic varieties showed significant increases in the activities of the enzymes SOD, POD, APX, and CAT; photosynthesis; and chlorophyll content; however, the highest chlorophyll A and B levels were observed in transgenic MR276. Transgenic varieties have shown a stronger root and leaf structure, as well as hairier roots, compared to the wild-type plants. This suggests that Lsi1 plays a key role in rice, increasing the absorption and accumulation of Si, then alters antioxidant activities, and improves morphological properties.

  6. Spacecube: A Family of Reconfigurable Hybrid On-Board Science Data Processors

    Science.gov (United States)

    Flatley, Thomas P.

    2015-01-01

    SpaceCube is a family of Field Programmable Gate Array (FPGA) based on-board science data processing systems developed at the NASA Goddard Space Flight Center (GSFC). The goal of the SpaceCube program is to provide 10x to 100x improvements in on-board computing power while lowering relative power consumption and cost. SpaceCube is based on the Xilinx Virtex family of FPGAs, which include processor, FPGA logic and digital signal processing (DSP) resources. These processing elements are leveraged to produce a hybrid science data processing platform that accelerates the execution of algorithms by distributing computational functions to the most suitable elements. This approach enables the implementation of complex on-board functions that were previously limited to ground based systems, such as on-board product generation, data reduction, calibration, classification, eventfeature detection, data mining and real-time autonomous operations. The system is fully reconfigurable in flight, including data parameters, software and FPGA logic, through either ground commanding or autonomously in response to detected eventsfeatures in the instrument data stream.

  7. LSI development for microcomputer application to weapon control

    International Nuclear Information System (INIS)

    Huen, T.

    1975-01-01

    The concept of the secure PAL (permissive-action link) system has been proposed for the control of nuclear weapons. Essential to the successful application of this system is the design of a miniature, all-LSI (large-scale-integration), secure PAL coded switch (SPCS). Two prototypes have been constructed to demonstrate the feasibility of a coded switch that occupies a volume of less than 0.5 cm 3 . Engineering development work on this system since 1972 is discussed, as is current activity. (auth)

  8. Particle simulation on a distributed memory highly parallel processor

    International Nuclear Information System (INIS)

    Sato, Hiroyuki; Ikesaka, Morio

    1990-01-01

    This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

  9. One-chip Integrated Module of MEMS Shock Sensor and Sensing Amplifier LSI using Pseudo-SOC Technology

    Science.gov (United States)

    Iida, Atsuko; Onozuka, Yutaka; Nishigaki, Michihiko; Yamada, Hiroshi; Funaki, Hideyuki; Itaya, Kazuhiko

    We have been developing the pseudo-SOC technology for one-chip module integration of heterogeneous devices that realizes high electrical performance and high density of devices embodying the advantages of both SOC technology and SIP technology. Especially, this technology is available for MEMS-LSI integration. We developed a 0.2mm-thickness one-chip module integrating a MEMS shock sensor and a sensing amplifier LSI by applying this technology. The MEMS shock sensor and the sensing amplifier LSI were connected by high-rigidity epoxy resin optimized the material constants to reduce the stress and the warpage resulting from resin shrinkage due to curing. Then the planar insulating layer and the redistributed conducting layer were formed on it for the global layer. The MEMS shock sensor was preformed to be modularized with a glass cap. Electrical contacts were achieved by bonding of Au bumps on the MEMS fixed electrodes and via holes filled with Ag paste of the glass cap. Functional performance was confirmed by obtaining signal corresponding to the reference signal of the pick-up sensor. Furthermore, stress analysis was performed using the FEM model simulation considering the resin shrinkage.

  10. Electrical Design and Evaluation of Asynchronous Serial Bus Communication Network of 48 Sensor Platform LSIs with Single-Ended I/O for Integrated MEMS-LSI Sensors

    Science.gov (United States)

    Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki

    2018-01-01

    For installing many sensors in a limited space with a limited computing resource, the digitization of the sensor output at the site of sensation has advantages such as a small amount of wiring, low signal interference and high scalability. For this purpose, we have developed a dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) (referred to as “sensor platform LSI”) for bus-networked Micro-Electro-Mechanical-Systems (MEMS)-LSI integrated sensors. In this LSI, collision avoidance, adaptation and event-driven functions are simply implemented to relieve data collision and congestion in asynchronous serial bus communication. In this study, we developed a network system with 48 sensor platform LSIs based on Printed Circuit Board (PCB) in a backbone bus topology with the bus length being 2.4 m. We evaluated the serial communication performance when 48 LSIs operated simultaneously with the adaptation function. The number of data packets received from each LSI was almost identical, and the average sampling frequency of 384 capacitance channels (eight for each LSI) was 73.66 Hz. PMID:29342923

  11. Electrical Design and Evaluation of Asynchronous Serial Bus Communication Network of 48 Sensor Platform LSIs with Single-Ended I/O for Integrated MEMS-LSI Sensors

    Directory of Open Access Journals (Sweden)

    Chenzhong Shao

    2018-01-01

    Full Text Available For installing many sensors in a limited space with a limited computing resource, the digitization of the sensor output at the site of sensation has advantages such as a small amount of wiring, low signal interference and high scalability. For this purpose, we have developed a dedicated Complementary Metal-Oxide-Semiconductor (CMOS Large-Scale Integration (LSI (referred to as “sensor platform LSI” for bus-networked Micro-Electro-Mechanical-Systems (MEMS-LSI integrated sensors. In this LSI, collision avoidance, adaptation and event-driven functions are simply implemented to relieve data collision and congestion in asynchronous serial bus communication. In this study, we developed a network system with 48 sensor platform LSIs based on Printed Circuit Board (PCB in a backbone bus topology with the bus length being 2.4 m. We evaluated the serial communication performance when 48 LSIs operated simultaneously with the adaptation function. The number of data packets received from each LSI was almost identical, and the average sampling frequency of 384 capacitance channels (eight for each LSI was 73.66 Hz.

  12. A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications.

    Science.gov (United States)

    Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Nonomura, Yutaka; Muroyama, Masanori

    2017-08-28

    Robot tactile sensation can enhance human-robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as "sensor platform LSI") as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated.

  13. Software for the Local Control and Instrumentation System for MFTF

    International Nuclear Information System (INIS)

    Labiak, W.G.

    1979-01-01

    There are nine different systems requiring over fifty computers in the Local Control and Instrumentation System for the Mirror Fusion Test Facility. Each computer system consists of an LSI-11/2 processor with 32,000 words of memory, a serial driver that implements the CAMAC serial highway protocol. With this large number of systems it is important that as much software as possible be common to all systems. A serial communications system has been developed for data transfers between the LSI-11/2's and the supervisory computers. This system is based on the RS 232 C interface with modem control lines. Six modem control lines are used for hardware handshaking, which allows totally independent full duplex communications to occur. Odd parity on each byte and a 16-bit checksum are used to detect errors in transmission

  14. The Starburst, a J-11 based front-end processor system

    International Nuclear Information System (INIS)

    Worm, F.H.; Klotz, D.V.

    1984-01-01

    This paper describes a coherent solution to the demand for ever-increasing performance in CAMAC-based data acquisition and pre-processing systems. It outlines the development of this modular high density system, covering the design decision and trade-offs from the hardware and software standpoints. Current applications are briefly described and the direction of future developments is indicated. The keystone of the system is a single-width module based on a DEC J-11 processor. It offers all the functions of an Auxiliary Crate Controller with programmable LAM-grader; at the same time functioning as an autonomous computer with a high-speed 64K word dual-port memory, console and Q22-bus peripheral interface. This structure supports extension on both, the CAMAC side and the Q-bus side; and the hardware design choices have been made with a view to allowing use of a large range of popular software. The principal module is supported on the CAMAC side by dedicated semi-autonomous memories, and on the computer side by portable winchester and floppy disk storage subsystems, while offering expansion capabilities through the Q22-bus port

  15. 76 FR 67184 - California State Nonroad Engine Pollution Control Standards; Large Spark-Ignition (LSI) Engines...

    Science.gov (United States)

    2011-10-31

    ... are applicable to fleets comprised of four or more pieces of equipment powered by LSI engines... comment. If you send an email comment directly to EPA without going through http://www.regulations.gov...

  16. ACP/R3000 processors in data acquisition systems

    International Nuclear Information System (INIS)

    Deppe, J.; Areti, H.; Atac, R.

    1989-02-01

    We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

  17. GA103: A microprogrammable processor for online filtering

    International Nuclear Information System (INIS)

    Calzas, A.; Danon, G.; Bouquet, B.

    1981-01-01

    GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)

  18. Report on achievements in fiscal 1998. Development on an immediately effective and innovative energy and environment technology (Research and development of an information terminal LSI requiring very low power consumption); 1998 nendo sokkoteki kakushinteki energy kankyo gijutsu kaihatsu seika hokokusho. Gokuteidenryoku joho tanmatsuyo LSI no kenkyu kaihatsu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1999-09-01

    It is intended that the technology for SOI expected of consuming very small power and operating at high speed be realized as an information terminal LSI for the coming 21st century. Therefore, research and development is made on the fundamental technology for LSI which operates in CMOS devices at high speed even with as very low voltage as about 0.5V by applying the optimized digital and analog circuit technology. Specifically, the aim is placed on enhancement of drive capability of transistors over that in the present devices, reduction of load capacity, and a very thin film complete depletion type SOI device that can be most expected of reduction of area as the main subjects. It is also intended to establish a method to realize very low power consuming LSI by using a CMOS circuit (a multi threshold value type CMOS circuit) that uses transistors with different threshold voltages and is optimized for the above SOI device. The achievements in this fiscal year include: a prototype 256kbSRAM was fabricated by using different design rules and wafer sizes, and the performance evaluation thereon was obtained; investigations were carried out on selection of SOI models for circuit simulation and on a high accuracy complete depletion type SOI models; and design criteria required for LSI design were put in order for comprehensive trial fabrication. (NEDO)

  19. High performance graphics processors for medical imaging applications

    International Nuclear Information System (INIS)

    Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

    1989-01-01

    This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

  20. The GF11 supercomputer

    International Nuclear Information System (INIS)

    Beetem, J.; Denneau, M.; Weingarten, D.

    1985-01-01

    GF11 is a parallel computer currently under construction at the Yorktown Research Center. The machine incorporates 576 floating-point processors arranged in a modified SIMD architecture. Each processor has space for 2 Mbytes of memory and is capable of 20 MFLOPS, giving the total machine a peak of 1.125 Gbytes of memory and 11.52 GFLOPS. The floating-point processors are interconnected by a dynamically reconfigurable non-blocking switching network. At each machine cycle any of 1024 pre-selected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chromodynamics, a proposed theory of the elementary particles which participate in nuclear interactions

  1. Utility of spatial frequency domain imaging (SFDI) and laser speckle imaging (LSI) to non-invasively diagnose burn depth in a porcine model☆

    Science.gov (United States)

    Burmeister, David M.; Ponticorvo, Adrien; Yang, Bruce; Becerra, Sandra C.; Choi, Bernard; Durkin, Anthony J.; Christy, Robert J.

    2015-01-01

    Surgical intervention of second degree burns is often delayed because of the difficulty in visual diagnosis, which increases the risk of scarring and infection. Non-invasive metrics have shown promise in accurately assessing burn depth. Here, we examine the use of spatial frequency domain imaging (SFDI) and laser speckle imaging (LSI) for predicting burn depth. Contact burn wounds of increasing severity were created on the dorsum of a Yorkshire pig, and wounds were imaged with SFDI/LSI starting immediately after-burn and then daily for the next 4 days. In addition, on each day the burn wounds were biopsied for histological analysis of burn depth, defined by collagen coagulation, apoptosis, and adnexal/vascular necrosis. Histological results show that collagen coagulation progressed from day 0 to day 1, and then stabilized. Results of burn wound imaging using non-invasive techniques were able to produce metrics that correlate to different predictors of burn depth. Collagen coagulation and apoptosis correlated with SFDI scattering coefficient parameter ( μs′) and adnexal/vascular necrosis on the day of burn correlated with blood flow determined by LSI. Therefore, incorporation of SFDI scattering coefficient and blood flow determined by LSI may provide an algorithm for accurate assessment of the severity of burn wounds in real time. PMID:26138371

  2. Custom high-reliability radiation-hard CMOS-LSI circuit design

    International Nuclear Information System (INIS)

    Barnard, W.J.

    1981-01-01

    Sandia has developed a custom CMOS-LSI design capability to provide high reliability radiation-hardened circuits. This capability relies on (1) proven design practices to enhance reliability, (2) use of well characterized cells and logic modules, (3) computer-aided design tools to reduce design time and errors and to standardize design definition, and (4) close working relationships with the system designer and technology fabrication personnel. Trade-offs are made during the design between circuit complexity/performance and technology/producibility for high reliability and radiation-hardened designs to result. Sandia has developed and is maintaining a radiation-hardened bulk CMOS technology fabrication line for production of prototype and small production volume parts

  3. Code compression for VLIW embedded processors

    Science.gov (United States)

    Piccinelli, Emiliano; Sannino, Roberto

    2004-04-01

    The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

  4. A VAX-FPS Loosely-Coupled Array of Processors

    International Nuclear Information System (INIS)

    Grosdidier, G.

    1987-03-01

    The main features of a VAX-FPS Loosely-Coupled Array of Processors (LCAP) set-up and the implementation of a High Energy Physics tracking program for off-line purposes will be described. This LCAP consists of a VAX 11/750 host and two FPS 64 bit attached processors. Before analyzing the performances of this LCAP, its characteristics will be outlined, especially from a user's point of vue, and will be briefly compared to those of the IBM-FPS LCAP

  5. Open-source implementation of an ad-hoc IEEE802.11a/g/p software-defined radio on low-power and low-cost general purpose processors

    Directory of Open Access Journals (Sweden)

    S. Ciccia

    2017-12-01

    Full Text Available This work proposes a low-cost and low-power software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. A state-of-the-art version of the IEEE 802.11 a/g/p software for GNU Radio (a free and open-source software development framework is available online, but we show here that its computational complexity prevents operations in low-power general purpose processors, even at throughputs below the standard. We therefore propose an evolution of this software that achieves a faster and lighter IEEE 802.11 a/g/p transmitter and receiver, suitable for low-power general purpose processors, for which GNU Radio provides very limited support; we discuss and describe the software radio processing structuring that is necessary to achieve the goal, providing a review of signal processing techniques. In particular, we emphasize the advanced reduced-instruction set (RISC machine (ARM study case, for which we also optimize some of the processing libraries. The presented software will remain open-source.

  6. GF11

    International Nuclear Information System (INIS)

    Beetem, J; Denneav, M.; Weingarten, D.

    1986-01-01

    GF11 is a parallel processor currently under construction at the IBM Yorktown Research Center. The machine incorporates 576 floating-point boards. Each board has space for 2 x 10 6 bytes of memory and is capable of 2 x 10 7 floating point operations per second; given the total machine a peak of 1.15 x 10 9 bytes of memory and 1.15 x 10 10 floating point operations per second. The floatingpoint processors are interconnected by a dynamically reconfigurable switching network. At each machine cycle any of 1024 preselected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chormodynamics

  7. The GF11 supercomputer

    International Nuclear Information System (INIS)

    Beetem, J.; Weingarten, D.

    1986-01-01

    GF11 is a parallel computer currently under construction at the IBM Yorktown Research Center. The machine incorporates 576 floating-point processors arrangedin a modified SIMD architecture. Each has space for 2 Mbytes of memory and is capable of 20 Mflops, giving the total machine a peak of 1.125 Gbytes of memory and 11.52 Gflops. The floating-point processors are interconnected by a dynamically reconfigurable non-blocking switching network. At each machine cycle any of 1024 pre-selected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chromodynamics

  8. The GF11 supercomputer

    International Nuclear Information System (INIS)

    Beetem, J.; Denneau, M.; Weingarten, D.

    1985-01-01

    GF11 is a parallel computer currently under construction at the IBM Yorktown Research Center. The machine incorporates 576 floating- point processors arranged in a modified SIMD architecture. Each has space for 2 Mbytes of memory and is capable of 20 Mflops, giving the total machine a peak of 1.125 Gbytes of memory and 11.52 Gflops. The floating-point processors are interconnected by a dynamically reconfigurable nonblocking switching network. At each machine cycle any of 1024 pre-selected permutations of data can be realized among the processors. The main intended application of GF11 is a class of calculations arising from quantum chromodynamics

  9. Microprocessor- and LSI-based CAMAC RAM controllers in a modular multiparameter instrumentation system

    International Nuclear Information System (INIS)

    Skarda, V.

    1982-01-01

    This contribution deals with the main features and with the hardware modifications of RAM controllers in the dual-port accessed CAMAC memory modules that have been applied in a modular multichannel analyzer instrumentation system. The modules described in this paper are fully compatible with the CAMAC standard EUR 4100 and with the COMPEX draft proposal of the ESONE Study Group, as well. Special attention is paid to the possible application of modern LSI bipolar circuits. (orig.)

  10. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  11. Green Secure Processors: Towards Power-Efficient Secure Processor Design

    Science.gov (United States)

    Chhabra, Siddhartha; Solihin, Yan

    With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

  12. Rapid Damage Assessment. Volume II. Development and Testing of Rapid Damage Assessment System.

    Science.gov (United States)

    1981-02-01

    pixels/s Camera Line Rate 732.4 lines/s Pixels per Line 1728 video 314 blank 4 line number (binary) 2 run number (BCD) 2048 total Pixel Resolution 8 bits...sists of an LSI-ll microprocessor, a VDI -200 video display processor, an FD-2 dual floppy diskette subsystem, an FT-I function key-trackball module...COMPONENT LIST FOR IMAGE PROCESSOR SYSTEM IMAGE PROCESSOR SYSTEM VIEWS I VDI -200 Display Processor Racks, Table FD-2 Dual Floppy Diskette Subsystem FT-l

  13. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  14. Effect of Lenient Steam Injection (LSI) heat treatment of bovine milk on the activities of some enzymes, the milk fat globule and pH

    DEFF Research Database (Denmark)

    Dickow, Jonatan A.; Nielsen, Martin Thorup; Hammershøj, Marianne

    2012-01-01

    This study investigated the effects of Lenient Steam Injection (LSI) treatment at temperatures 70–150 C on the enzymatic activities of the indigenous milk enzymes alkaline phosphatase, lactoperoxidase (LPO), xanthine oxidase (XO), lipoprotein lipase (LPL) and plasmin in comparison with two...... reference heat treatments of 63 C for 30 s and of 72 C for 15 s by indirect heating. Milk fat globule (MFG) size distributions and pH were also monitored. Alkaline phosphatase, LPO, XO and LPL activities decreased with increasing LSI temperature. Plasmin activity was increased at temperatures

  15. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  16. A Tactile Sensor Network System Using a Multiple Sensor Platform with a Dedicated CMOS-LSI for Robot Applications †

    Science.gov (United States)

    Shao, Chenzhong; Tanaka, Shuji; Nakayama, Takahiro; Hata, Yoshiyuki; Bartley, Travis; Muroyama, Masanori

    2017-01-01

    Robot tactile sensation can enhance human–robot communication in terms of safety, reliability and accuracy. The final goal of our project is to widely cover a robot body with a large number of tactile sensors, which has significant advantages such as accurate object recognition, high sensitivity and high redundancy. In this study, we developed a multi-sensor system with dedicated Complementary Metal-Oxide-Semiconductor (CMOS) Large-Scale Integration (LSI) circuit chips (referred to as “sensor platform LSI”) as a framework of a serial bus-based tactile sensor network system. The sensor platform LSI supports three types of sensors: an on-chip temperature sensor, off-chip capacitive and resistive tactile sensors, and communicates with a relay node via a bus line. The multi-sensor system was first constructed on a printed circuit board to evaluate basic functions of the sensor platform LSI, such as capacitance-to-digital and resistance-to-digital conversion. Then, two kinds of external sensors, nine sensors in total, were connected to two sensor platform LSIs, and temperature, capacitive and resistive sensing data were acquired simultaneously. Moreover, we fabricated flexible printed circuit cables to demonstrate the multi-sensor system with 15 sensor platform LSIs operating simultaneously, which showed a more realistic implementation in robots. In conclusion, the multi-sensor system with up to 15 sensor platform LSIs on a bus line supporting temperature, capacitive and resistive sensing was successfully demonstrated. PMID:29061954

  17. Evaluation of the Intel Westmere-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2011-01-01

    One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

  18. Genomic evolution of 11 type strains within family Planctomycetaceae.

    Directory of Open Access Journals (Sweden)

    Min Guo

    Full Text Available The species in family Planctomycetaceae are ideal groups for investigating the origin of eukaryotes. Their cells are divided by a lipidic intracytoplasmic membrane and they share a number of eukaryote-like molecular characteristics. However, their genomic structures, potential abilities, and evolutionary status are still unknown. In this study, we searched for common protein families and a core genome/pan genome based on 11 sequenced species in family Planctomycetaceae. Then, we constructed phylogenetic tree based on their 832 common protein families. We also annotated the 11 genomes using the Clusters of Orthologous Groups database. Moreover, we predicted and reconstructed their core/pan metabolic pathways using the KEGG (Kyoto Encyclopedia of Genes and Genomes orthology system. Subsequently, we identified genomic islands (GIs and structural variations (SVs among the five complete genomes and we specifically investigated the integration of two Planctomycetaceae plasmids in all 11 genomes. The results indicate that Planctomycetaceae species share diverse genomic variations and unique genomic characteristics, as well as have huge potential for human applications.

  19. Computer-based data acquisition system in the Large Coil Test Facility

    International Nuclear Information System (INIS)

    Gould, S.S.; Layman, L.R.; Million, D.L.

    1983-01-01

    The utilization of computers for data acquisition and control is of paramount importance on large-scale fusion experiments because they feature the ability to acquire data from a large number of sensors at various sample rates and provide for flexible data interpretation, presentation, reduction, and analysis. In the Large Coil Test Facility (LCTF) a Digital Equipment Corporation (DEC) PDP-11/60 host computer with the DEC RSX-11M operating system coordinates the activities of five DEC LSI-11/23 front-end processors (FEPs) via direct memory access (DMA) communication links. This provides host control of scheduled data acquisition and FEP event-triggered data collection tasks. Four of the five FEPs have no operating system

  20. Real-time simulation of MHD/steam power plants by digital parallel processors

    International Nuclear Information System (INIS)

    Johnson, R.M.; Rudberg, D.A.

    1981-01-01

    Attention is given to a large FORTRAN coded program which simulates the dynamic response of the MHD/steam plant on either a SEL 32/55 or VAX 11/780 computer. The code realizes a detailed first-principle model of the plant. Quite recently, in addition to the VAX 11/780, an AD-10 has been installed for usage as a real-time simulation facility. The parallel processor AD-10 is capable of simulating the MHD/steam plant at several times real-time rates. This is desirable in order to develop rapidly a large data base of varied plant operating conditions. The combined-cycle MHD/steam plant model is discussed, taking into account a number of disadvantages. The disadvantages can be overcome with the aid of an array processor used as an adjunct to the unit processor. The conversion of some computations for real-time simulation is considered

  1. Simulation of a parallel processor on a serial processor: The neutron diffusion equation

    International Nuclear Information System (INIS)

    Honeck, H.C.

    1981-01-01

    Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

  2. Translation and validation of the Life Satisfaction Index for Adolescents scale with neuromuscular disorders: LSI-A Brazil

    Directory of Open Access Journals (Sweden)

    Valdecir Antonio Simon

    Full Text Available ABSTRACT Objective To validate the Life Satisfaction Index for Adolescents (LSI-A scale, parent version and patient version, for Duchenne muscular dystrophy (DMD, spinal muscular atrophy (SMA and limb-girdle muscular dystrophy (LGMD. Methods The parent version of the instrument was divided into Groups A, B, C and D; and the patient version, divided into B, C and D. For the statistical calculation, the following tests were used: Cronbach’s α, ICC, Pearson and the ROC Curve. Results The parent and patient versions of the instrument are presented, with the following results in the overall score, respectively: Cronbach’s α, 0.87 and 0.89; reliability, r 0.98 and 0.97; reproducibility, ICC 0.69 and 0.80; sensitivity, 0.78 and 0.72; specificity, 0.5 and 0.69; and accuracy, 64% and 70.4%. Conclusion According to the validity and reproducibility values, the LSI-A Brazil parent and patient versions, are clinically useful to assess quality of life in DMD, SMA or LGMD and may also be useful for other neuromuscular disorders.

  3. Translation and validation of the Life Satisfaction Index for Adolescents scale with neuromuscular disorders: LSI-A Brazil.

    Science.gov (United States)

    Simon, Valdecir Antonio; Zanoteli, Edmar; Simon, Margarete Andreozzi Vaz Pereira; Resende, Maria Bernadete Dutra de; Reed, Umbertina Conti

    2017-08-01

    To validate the Life Satisfaction Index for Adolescents (LSI-A) scale, parent version and patient version, for Duchenne muscular dystrophy (DMD), spinal muscular atrophy (SMA) and limb-girdle muscular dystrophy (LGMD). The parent version of the instrument was divided into Groups A, B, C and D; and the patient version, divided into B, C and D. For the statistical calculation, the following tests were used: Cronbach's α, ICC, Pearson and the ROC Curve. The parent and patient versions of the instrument are presented, with the following results in the overall score, respectively: Cronbach's α, 0.87 and 0.89; reliability, r 0.98 and 0.97; reproducibility, ICC 0.69 and 0.80; sensitivity, 0.78 and 0.72; specificity, 0.5 and 0.69; and accuracy, 64% and 70.4%. According to the validity and reproducibility values, the LSI-A Brazil parent and patient versions, are clinically useful to assess quality of life in DMD, SMA or LGMD and may also be useful for other neuromuscular disorders.

  4. Induction of Barley Silicon Transporter HvLsi1 and HvLsi2, increased silicon concentration in the shoot and regulated Starch and ABA Homeostasis under Osmotic stress and Concomitant Potassium Deficiency

    Directory of Open Access Journals (Sweden)

    Seyed A. Hosseini

    2017-08-01

    Full Text Available Drought is one of the major stress factors reducing cereal production worldwide. There is ample evidence that the mineral nutrient status of plants plays a critical role in increasing plant tolerance to different biotic and abiotic stresses. In this regard, the important role of various nutrients e.g., potassium (K or silicon (Si in the mitigation of different stress factors, such as drought, heat or frost has been well documented. Si application has been reported to ameliorate plant nutrient deficiency. Here, we used K and Si either solely or in combination to investigate whether an additive positive effect on barley growth can be achieved under osmotic stress and which mechanisms contribute to a better tolerance to osmotic stress. To achieve this goal, barley plants were subjected to polyethylene glycol (PEG-induced osmotic stress under low or high K supply and two Si regimes. The results showed that barley silicon transporters HvLsi1 and HvLsi2 regulate the accumulation of Si in the shoot only when plant suffered from K deficiency. Si, in turn, increased the starch level under both osmotic stress and K deficiency and modulated the glycolytic and TCA pathways. Hormone profiling revealed that the beneficial effect of Si is most likely mediated also by ABA homeostasis and active cytokinin isopentenyl adenine (iP. We conclude that Si may effectively improve stress tolerance under K deficient condition in particular when additional stress like osmotic stress interferes.

  5. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  6. Adaptive signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

  7. Adaptive signal processor

    International Nuclear Information System (INIS)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  8. Multithreading in vector processors

    Science.gov (United States)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  9. The SAFT-UT (synthetic aperture focusing technique for ultrasonic testing) real-time inspection system: Operational principles and implementation

    Energy Technology Data Exchange (ETDEWEB)

    Hall, T. E.; Reid, L. D.; Doctor, S. R.

    1988-06-01

    This document provides a technical description of the real-time imaging system developed for rapid flaw detection and characterization utilizing the synthetic aperture focusing technique for ultrasonic testing (SAFT-UT). The complete fieldable system has been designed to perform inservice inspection of light-water reactor components. Software was written on a DEC LSI 11/23 computer system to control data collection. The unprocessed data is transferred to a VAX 11/730 host computer to perform data processing and image display tasks. A parallel architecture peripheral to the host computer, referred to as the Real-Time SAFT Processor, rapidly performs the SAFT processing function. From the host's point of view, this device operates on the SAFT data in such a way that one may consider it to be a specialized or SAFT array processor. A guide to SAFT-UT theory and conventions is included, along with a detailed description of the operation of the software, how to install the software, and a detailed hardware description.

  10. Integrated fuel processor development

    International Nuclear Information System (INIS)

    Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

    2001-01-01

    The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

  11. 3081/E processor and its on-line use

    International Nuclear Information System (INIS)

    Rankin, P.; Bricaud, B.; Gravina, M.

    1985-05-01

    The 3081/E is a second generation emulator of a mainframe IBM. One of it's applications will be to form part of the data acquisition system of the upgraded Mark II detector for data taking at the SLAC linear collider. Since the processor does not have direct connections to I/O devices a FASTBUS interface will be provided to allow communication with both SLAC Scanner Processors (which are responsible for the accumulation of data at a crate level) and the experiment's VAX 8600 mainframe. The 3081/E's will supply a significant amount of on-line computing power to the experiment (a single 3081/E is equivalent to 4 to 5 VAX 11/780's). A major advantage of the 3081/E is that program development can be done on an IBM mainframe (such as the one used for off-line analysis) which gives the programmer access to a full range of debugging tools. The processor's performance can be continually monitored by comparison of the results obtained using it to those given when the same program is run on an IBM computer. 9 refs

  12. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  13. The Molen Polymorphic Media Processor

    NARCIS (Netherlands)

    Kuzmanov, G.K.

    2004-01-01

    In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

  14. Fiscal 2000 achievement report. Development of prompt-effect technology for innovative energy environment (Research and development of extremely low power consuming LSI for information terminal); 2000 nendo sokkoteki kakushinteki energy kankyo gijutsu kaihatsu seika hokokusho. Gokuteidenryoku joho tanmatsuyo LSI no kenkyu kaihatsu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2001-03-01

    With the advancement of information technologies, multimedia information terminals such as handyphone systems and mobile computers are increasing in number and improving in quality, sharply increasing power consumption in this domain. So as to suppress the power consumption, efforts are exerted to develop technologies for information terminal LSI (large-scale integration) substrates consuming extremely low power and still capable of high-speed operation. Studied are a device technology of SOI (silicon on insulator) to realize a remarkable reduction in power consumption and enable high-speed operation and a circuit technology of the multi-threshold CMOS (complementary metal-oxide semiconductor) advantageous to the achievement of low-voltage high-speed operation. In concrete terms, the efforts center about an extremely thin film SOI device of the full depletion type higher in transistor driving capability, lower in load capacity, and smaller in surface area than those currently in use, and aim to put such an SOI device on an optimized multi-threshold CMOS circuit for the establishment of techniques toward the embodiment of an LSI substrate consuming extremely low electric power. (NEDO)

  15. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  16. MEMS-LSI Integrated Microchip using Pseudo-SoC Technology

    Science.gov (United States)

    Funaki, Hideyuki; Itaya, Kazuhiko; Yamada, Hiroshi; Onozuka, Yutaka; Iida, Atsuko

    The authors have developed pseudo-SoC technology to realize MEMS-LSI integrated micro-chip. The pseudo-SoC technology consists of three technologies which are wafer reconfiguration technology, inter-chip redistribution layer technology, and pseudo-SoC thinning technology. In the wafer reconfiguration technology, the filling of resin and surface step between heterogeneous chips were improved through the optimization of vacuum printing process and resin material. These improvements reduced the warpage of reconfiguration wafer, leading to achievement of the reconfiguration wafer with 5 inch in diameter. In the inter-chip redistribution layer technology, the interface adherence between planar layer and inter-chip redistribution layer was improved, leading to the inter-chip redistribution layer with 1μm/1μm in line/space on reconfiguration wafer. In the pseudo-SoC thinning technology, thin pseudo-SoC device with 100μm in thickness was achieved through developing mechanical backside grinding process technology. Furthermore, ultra-thin pseudo-SoC which integrated electrostatic MEMS light valve and PWM driver IC was prototyped through developing the ultra-thin MEMS encapsulation technology.

  17. Frequency of family meals and 6-11-year-old children's social behaviors.

    Science.gov (United States)

    Lora, Karina R; Sisson, Susan B; DeGrace, Beth W; Morris, Amanda S

    2014-08-01

    Family meals are regarded as an opportunity to promote healthy child development. In this brief report, we examined the relationship between frequency of family meals and children's social behaviors in 6-11-year-olds. The 2007 U.S. National Survey of Children's Health (NSCH) provided data on the frequency of family meals in a sample of 6-11-year-old children (N = 24,167). The following social behavior indicators were examined: child positive social skills, child problematic social behaviors, child engagement in school, and parental aggravation with the child. Individual logistic regression analyses were calculated in unadjusted and adjusted models. On average, families had 5.3 meals together per week. In adjusted models, more frequent family meals increased the odds of child positive social skills (OR = 1.08, 95% CI [1.02, 1.16]) and child engagement in school (OR = 1.11, 95% CI [1.06, 1.15]), and decreased the likelihood of child problematic social behaviors (OR = 0.92, 95% CI [0.87, 0.98]). There was no association between frequency of family meals and parental aggravation with the child (OR = 0.98, 95% CI [0.93, 1.04]). Findings support the promotion of family meals to benefit children's development of healthy social behaviors.

  18. 7 CFR 201.56-11 - Knotweed family, Polygonaceae.

    Science.gov (United States)

    2010-01-01

    ... SERVICE (Standards, Inspections, Marketing Practices), DEPARTMENT OF AGRICULTURE (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Germination Tests in the Administration of the Act § 201.56-11 Knotweed family, Polygonaceae. Kinds of seed: Buckwheat, rhubarb, and sorrel. (a) General description. (1...

  19. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    Kaerhae, K.; Jouhiaho, A.

    2009-01-01

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  20. Hardware synthesis from DDL. [Digital Design Language for computer aided design and test of LSI

    Science.gov (United States)

    Shah, A. M.; Shiva, S. G.

    1981-01-01

    The details of the digital systems can be conveniently input into the design automation system by means of Hardware Description Languages (HDL). The Computer Aided Design and Test (CADAT) system at NASA MSFC is used for the LSI design. The Digital Design Language (DDL) has been selected as HDL for the CADAT System. DDL translator output can be used for the hardware implementation of the digital design. This paper addresses problems of selecting the standard cells from the CADAT standard cell library to realize the logic implied by the DDL description of the system.

  1. Optical Associative Processors For Visual Perception"

    Science.gov (United States)

    Casasent, David; Telfer, Brian

    1988-05-01

    We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

  2. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  3. Composable processor virtualization for embedded systems

    NARCIS (Netherlands)

    Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

    2010-01-01

    Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

  4. Deterministic chaos in the processor load

    International Nuclear Information System (INIS)

    Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

    2007-01-01

    In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

  5. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    Science.gov (United States)

    Wang, Hui; Chen, Huansheng; Wu, Qizhong; Lin, Junmin; Chen, Xueshun; Xie, Xinwei; Wang, Rongrong; Tang, Xiao; Wang, Zifa

    2017-08-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC), KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1) updating the pure Message Passing Interface (MPI) parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2) fully employing the 512 bit wide vector processing units (VPUs) on the KNL platform; (3) reducing unnecessary memory access to improve cache efficiency; (4) reducing the thread local storage (TLS) in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5) changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined performance and energy

  6. Radiation-hardened CMOS/SOS LSI circuits

    International Nuclear Information System (INIS)

    Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.

    1976-01-01

    The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology

  7. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  8. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    Million, D.L.

    1983-05-01

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  9. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

  10. Design Approach and Implementation of Application Specific Instruction Set Processor for SHA-3 BLAKE Algorithm

    Science.gov (United States)

    Zhang, Yuli; Han, Jun; Weng, Xinqian; He, Zhongzhu; Zeng, Xiaoyang

    This paper presents an Application Specific Instruction-set Processor (ASIP) for the SHA-3 BLAKE algorithm family by instruction set extensions (ISE) from an RISC (reduced instruction set computer) processor. With a design space exploration for this ASIP to increase the performance and reduce the area cost, we accomplish an efficient hardware and software implementation of BLAKE algorithm. The special instructions and their well-matched hardware function unit improve the calculation of the key section of the algorithm, namely G-functions. Also, relaxing the time constraint of the special function unit can decrease its hardware cost, while keeping the high data throughput of the processor. Evaluation results reveal the ASIP achieves 335Mbps and 176Mbps for BLAKE-256 and BLAKE-512. The extra area cost is only 8.06k equivalent gates. The proposed ASIP outperforms several software approaches on various platforms in cycle per byte. In fact, both high throughput and low hardware cost achieved by this programmable processor are comparable to that of ASIC implementations.

  11. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS on Intel Xeon Phi processors

    Directory of Open Access Journals (Sweden)

    H. Wang

    2017-08-01

    Full Text Available The Global Nested Air Quality Prediction Modeling System (GNAQPMS is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS, which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL. Compared with the first-generation Xeon Phi coprocessor (codenamed Knights Corner, KNC, KNL has many new hardware features such as a bootable processor, high-performance in-package memory and ISA compatibility with Intel Xeon processors. In particular, we describe the five optimisations we applied to the key modules of GNAQPMS, including the CBM-Z gas-phase chemistry, advection, convection and wet deposition modules. These optimisations work well on both the KNL 7250 processor and the Intel Xeon E5-2697 V4 processor. They include (1 updating the pure Message Passing Interface (MPI parallel mode to the hybrid parallel mode with MPI and OpenMP in the emission, advection, convection and gas-phase chemistry modules; (2 fully employing the 512 bit wide vector processing units (VPUs on the KNL platform; (3 reducing unnecessary memory access to improve cache efficiency; (4 reducing the thread local storage (TLS in the CBM-Z gas-phase chemistry module to improve its OpenMP performance; and (5 changing the global communication from writing/reading interface files to MPI functions to improve the performance and the parallel scalability. These optimisations greatly improved the GNAQPMS performance. The same optimisations also work well for the Intel Xeon Broadwell processor, specifically E5-2697 v4. Compared with the baseline version of GNAQPMS, the optimised version was 3.51 × faster on KNL and 2.77 × faster on the CPU. Moreover, the optimised version ran at 26 % lower average power on KNL than on the CPU. With the combined

  12. Sensitometric control of roentgen film processors

    International Nuclear Information System (INIS)

    Forsberg, H.; Karolinska Sjukhuset, Stockholm

    1987-01-01

    Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

  13. Special purpose processors for high energy physics applications

    International Nuclear Information System (INIS)

    Verkerk, C.

    1978-01-01

    The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

  14. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  15. Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors

    OpenAIRE

    Natvig, Lasse; Follan, Torbjørn; Støa, Simen; Magnussen, Sindre; Guirado, Antonio Garcia

    2015-01-01

    Climbing Mont Blanc (CMB) is an open online judge used for training in energy efficient programming of state-of-the-art heterogeneous multicores. It uses an Odroid-XU3 board from Hardkernel with an Exynos Octa processor and integrated power sensors. This processor is three-way heterogeneous containing 14 different cores of three different types. The board currently accepts C and C++ programs, with support for OpenCL v1.1, OpenMP 4.0 and Pthreads. Programs submitted using the graphical user in...

  16. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

  17. Experimental testing of the noise-canceling processor.

    Science.gov (United States)

    Collins, Michael D; Baer, Ralph N; Simpson, Harry J

    2011-09-01

    Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

  18. Development of a highly reliable CRT processor

    International Nuclear Information System (INIS)

    Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

    1996-01-01

    Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

  19. Computer Generated Inputs for NMIS Processor Verification

    International Nuclear Information System (INIS)

    J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

    2001-01-01

    Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

  20. 3081//sub E/ processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

    1983-03-01

    Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

  1. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  2. PixonVision real-time video processor

    Science.gov (United States)

    Puetter, R. C.; Hier, R. G.

    2007-09-01

    PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

  3. Processors and systems (picture processing)

    Energy Technology Data Exchange (ETDEWEB)

    Gemmar, P

    1983-01-01

    Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

  4. Special processor for in-core control systems

    International Nuclear Information System (INIS)

    Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

    1978-01-01

    The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

  5. Family law reform to change women's realities across 11 countries ...

    International Development Research Centre (IDRC) Digital Library (Canada)

    2016-12-08

    Dec 8, 2016 ... ... to reform discriminatory family laws in 11 countries (Brazil, Egypt, India, Iran, ... These laws determine a woman's right to marry, travel, hold a job, ... by WLP through advocacy, trainings, and public awareness campaigns.

  6. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  7. Effect of processor temperature on film dosimetry

    International Nuclear Information System (INIS)

    Srivastava, Shiv P.; Das, Indra J.

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

  8. The design of an asynchronous Tiny RISC TM/TR4101 microprocessor core

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Jensen, P.; Korger, P.

    1998-01-01

    This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper repo...

  9. Lattice gauge theory using parallel processors

    International Nuclear Information System (INIS)

    Lee, T.D.; Chou, K.C.; Zichichi, A.

    1987-01-01

    The book's contents include: Lattice Gauge Theory Lectures: Introduction and Current Fermion Simulations; Monte Carlo Algorithms for Lattice Gauge Theory; Specialized Computers for Lattice Gauge Theory; Lattice Gauge Theory at Finite Temperature: A Monte Carlo Study; Computational Method - An Elementary Introduction to the Langevin Equation, Present Status of Numerical Quantum Chromodynamics; Random Lattice Field Theory; The GF11 Processor and Compiler; and The APE Computer and First Physics Results; Columbia Supercomputer Project: Parallel Supercomputer for Lattice QCD; Statistical and Systematic Errors in Numerical Simulations; Monte Carlo Simulation for LGT and Programming Techniques on the Columbia Supercomputer; Food for Thought: Five Lectures on Lattice Gauge Theory

  10. Speech and language abilities of children with the familial form of 22q11.2 deletion syndrome

    Directory of Open Access Journals (Sweden)

    Rakonjac Marijana

    2016-01-01

    Full Text Available The 22q11.2 Deletion Syndrome (22q11.2DS, which encompasses Shprintzen syndrome, DiGeorge and velocardiofacial syndrome, is the most common microdeletion syndrome in humans with an estimated incidence of approximately 1/4000 per live births. After Down syndrome, it is the second most common genetic syndrome associated with congenital heart malformations. The mode of inheritance of the 22q11.2DS is autosomal dominant. In approximately 72 - 94% of the cases the deletion has occurred de novo, while in 6 to 28% of patients deletion was inherited from a parent. As a part of a multidisciplinary study we examined the speech and language abilities of members of two families with inherited form of 22q11.2DS. The presence of 22q11.2 microdeletion was revealed by fluorescence in situ hybridization (FISH and/or multiplex ligation-dependent probe amplification (MLPA. In one family we detected 1.5 Mb 22q11.2 microdeletion, while in the other family we found 3Mb microdeletion. Patients from both families showed delays in cognitive, socio-emotional, speech and language development. Furthermore, we found considerable variability in the phenotypic characteristics of 22q11.2DS and the degree of speech-language pathology not only between different families with 22q11.2 deletion, but also among members of the same family. In addition, we detected no correlation between the phenotype and the size of 22q11.2 microdeletion.

  11. Many - body simulations using an array processor

    International Nuclear Information System (INIS)

    Rapaport, D.C.

    1985-01-01

    Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

  12. Multi-processor network implementations in Multibus II and VME

    International Nuclear Information System (INIS)

    Briegel, C.

    1992-01-01

    ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

  13. Hereditary ectodermal dysplasia: Report of 11 patients from a family

    Directory of Open Access Journals (Sweden)

    Seema Vaidya

    2013-01-01

    Full Text Available Hereditary Ectodermal Dysplasia is an inherited disorder commonly involving skin, teeth, hair, and nails. We have observed ectodermal dysplasia (EDs in 11 individuals over two generations in one family. Smooth, dry, thin skin was seen in most affected individuals. All had fine, slow-growing scalp hair and body hair and some had sparse eyebrows and short eyelashes. Nearly all showed decrease in sweating. Severe teeth abnormalities were seen in all patients and fingernail abnormalities were not so severe but toenail abnormalities were seen in all patients. No other abnormalities were seen in affected individuals in this family. It is very rare to find such a large family having ectodermal dysplasia.

  14. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  15. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  16. Online track processor for the CDF upgrade

    International Nuclear Information System (INIS)

    Thomson, E. J.

    2002-01-01

    A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

  17. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

  18. Data register and processor for multiwire chambers

    International Nuclear Information System (INIS)

    Karpukhin, V.V.

    1985-01-01

    A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

  19. A Parallel Workload Model and its Implications for Processor Allocation

    Science.gov (United States)

    1996-11-01

    with SEV or AVG, both of which can tolerate c = 0.4 { 0.6 before their performance deteriorates signi cantly. On the other hand, Setia [10] has...Sanjeev. K Setia . The interaction between memory allocation and adaptive partitioning in message-passing multicomputers. In IPPS 󈨣 Workshop on Job...Scheduling Strategies for Parallel Processing, pages 89{99, 1995. [11] Sanjeev K. Setia and Satish K. Tripathi. An analysis of several processor

  20. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  1. Implementation and operation of VAX-based data acquisition system for the large coil task

    International Nuclear Information System (INIS)

    Baylor, L.R.; Blair, E.T.; Greenwood, D.E.; Munro, J.K.

    1985-01-01

    The VAX-based data acquisition system for the International Fusion Superconducting Magnet Test Facility (IFSMTF) at Oak Ridge National Laboratory (ORNL) is a second generation system that evolved from a PDP-11/60-based system used in the two-coil test and facility shakedown. The VAX 11/780 processor has been interfaced through a CAMAC fiber-optic byte serial highway to five existing LSI-11/23 frontend processors through dataway access port (DAP) modules. The VAX CAMAC interface has permitted the addition of analog input channels for the refrigeration system and analog and digital outputs to drive display devices. Software utilities are provided to operate the data acquisition hardware, maintain data base files, and display data. Graphical display of data is accomplished through the use of VAX IDL (Interactive Data Language), which provides device-independent data presentation. Output from IDL is available for Tektronix displays and has been extended to generate TKF and Versaplot graphics metafiles for hardcopy output to Versatec printer/plotters. In addition, a Sension display system is available for graphical display of real-time data in the form of strip chart and tabular displays. This paper describes the hardware and software design of the system and the operation of the system during the full-array testing sequence

  2. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  3. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  4. Architectural design and analysis of a programmable image processor

    International Nuclear Information System (INIS)

    Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

    2003-01-01

    In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

  5. Analytical Bounds on the Threads in IXP1200 Network Processor

    OpenAIRE

    Ramakrishna, STGS; Jamadagni, HS

    2003-01-01

    Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

  6. A UNIX-based prototype biomedical virtual image processor

    International Nuclear Information System (INIS)

    Fahy, J.B.; Kim, Y.

    1987-01-01

    The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

  7. The communication processor of TUMULT-64

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Jansen, P.G.

    1988-01-01

    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

  8. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  9. Accuracies Of Optical Processors For Adaptive Optics

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1992-01-01

    Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

  10. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  11. Lipsi: Probably the Smallest Processor in the World

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

  12. Recommending the heterogeneous cluster type multi-processor system computing

    International Nuclear Information System (INIS)

    Iijima, Nobukazu

    2010-01-01

    Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

  13. Bereavement and Coping of South Asian Families Post 9/11

    Science.gov (United States)

    Inman, Arpana G.; Yeh, Christine J.; Madan-Bahel, Anvita; Nath, Shivani

    2007-01-01

    Eleven first-generation South Asian family members who lost a relative in the World Trade Center attacks on September 11, 2001, were interviewed about their loss and their coping strategies. Data were analyzed using consensual qualitative research (CQR) methodology. Participant responses clearly delineated bereavement reactions and coping within a…

  14. Periodicities in the high-mass X-ray binary system RXJ0146.9+6121/LSI+61°235

    Science.gov (United States)

    Sarty, Gordon E.; Kiss, László L.; Huziak, Richard; Catalan, Lionel J. J.; Luciuk, Diane; Crawford, Timothy R.; Lane, David J.; Pickard, Roger D.; Grzybowski, Thomas A.; Closas, Pere; Johnston, Helen; Balam, David; Wu, Kinwah

    2009-01-01

    The high-mass X-ray binary RXJ0146.9+6121, with optical counterpart LSI+61°235 (V831Cas), is an intriguing system on the outskirts of the open cluster NGC663. It contains the slowest Be type X-ray pulsar known with a pulse period of around 1400s and, primarily from the study of variation in the emission line profile of Hα, it is known to have a Be decretion disc with a one-armed density wave period of approximately 1240d. Here we present the results of an extensive photometric campaign, supplemented with optical spectroscopy, aimed at measuring short time-scale periodicities. We find three significant periodicities in the photometric data at, in order of statistical significance, 0.34, 0.67 and 0.10d. We give arguments to support the interpretation that the 0.34 and 0.10d periods could be due to stellar oscillations of the B-type primary star and that the 0.67d period is the spin period of the Be star with a spin axis inclination of 23+10-8 degrees. We measured a systemic velocity of -37.0 +/- 4.3kms-1 confirming that LSI+61°235 has a high probability of membership in the young cluster NGC663 from which the system's age can be estimated as 20-25Myr. From archival RXTE All Sky Monitor (ASM) data we further find `super' X-ray outbursts roughly every 450d. If these super outbursts are caused by the alignment of the compact star with the one-armed decretion disc enhancement, then the orbital period is approximately 330d.

  15. First level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

  16. First-level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

  17. Multicentre evaluation of the Naída CI Q70 sound processor: feedback from cochlear implant users and professionals

    Directory of Open Access Journals (Sweden)

    Jeanette Martin

    2016-12-01

    Full Text Available The aim of this survey was to gather data from both implant recipients and professionals on the ease of use of the Naída CI Q70 (Naída CI sound processor from Advanced Bionics and on the usefulness of the new functions and features available. A secondary objective was to investigate fitting practices with the new processor. A comprehensive user satisfaction survey was conducted in a total of 186 subjects from 24 centres. In parallel, 23 professional questionnaires were collected from 11 centres. Overall, there was high satisfaction with the Naída CI processor from adults, children, experienced and new CI users as well as from professionals. The Naída CI processor was shown as being easy to use by all ages of recipients and by professionals. The majority of experienced CI users rated the Naída CI processor as being similar or better than their previous processor in all areas surveyed. The Naída CI was recommended by the professionals for fitting in all populations. Features like UltraZoom, ZoomControl and DuoPhone would not be fitted to very young children in contrast to adults. Positive ratings were obtained for ease of use, comfort and usefulness of the new functions and features of the Naída CI sound processor. Seventy-seven percent of the experienced CI users rated the new processor as being better than their previous sound processor from a general point of view. The survey also showed that fitting practices were influenced by the age of the user.

  18. A fast filter processor as a part of the trigger logic in an elastic scattering experiment

    International Nuclear Information System (INIS)

    Kenyon Gjerpe, I.

    1981-01-01

    A fast special purpose processor as a part of the trigger logic in an elastic scattering experiment is described. The decision to incorporate such a processor was taken because the trigger rate was estimated to be an order of magnitude higher than the date taking capability of the on-line minicomputer, a NORD 10. The processor is capable of checking the coplanarity and the opening angle of the two outgoing tracks within about 100 μs. This is done with a spatial resolution of 1 mm by using two points each track given by 3 MWPCs. For comparison this is two orders of magnitude faster than the same algorithm coded in assembly language on a PDP 11/40. The main contribution to this increased speed is due to extensive use of pipelining and parallelism. When running with the processor in the trigger, 75% more elastic events per incoming beam particle were collected, and 3 times as many elastic events per trigger were recorded on to tape for further in-depth analysis, than previously. Due to major improvements in the primary trigger logic this was less than the gain initially anticipated. A first version of the processor was designed and constructed in the CERN DD division by J. Joosten, M. Letheren and B. Martin under the supervision of C. Verkerk. The author was involved in the final design, construction and testing, and subsequently was responsible for the intergration, programming and running of the processor in the experiment. (orig.)

  19. A digital retina-like low-level vision processor.

    Science.gov (United States)

    Mertoguno, S; Bourbakis, N G

    2003-01-01

    This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

  20. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Kazimierz Wiatr

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  1. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  2. Programming the Linpack Benchmark for the IBM PowerXCell 8i Processor

    Directory of Open Access Journals (Sweden)

    Michael Kistler

    2009-01-01

    Full Text Available In this paper we present the design and implementation of the Linpack benchmark for the IBM BladeCenter QS22, which incorporates two IBM PowerXCell 8i1 processors. The PowerXCell 8i is a new implementation of the Cell Broadband Engine™2 architecture and contains a set of special-purpose processing cores known as Synergistic Processing Elements (SPEs. The SPEs can be used as computational accelerators to augment the main PowerPC processor. The added computational capability of the SPEs results in a peak double precision floating point capability of 108.8 GFLOPS. We explain how we modified the standard open source implementation of Linpack to accelerate key computational kernels using the SPEs of the PowerXCell 8i processors. We describe in detail the implementation and performance of the computational kernels and also explain how we employed the SPEs for high-speed data movement and reformatting. The result of these modifications is a Linpack benchmark optimized for the IBM PowerXCell 8i processor that achieves 170.7 GFLOPS on a BladeCenter QS22 with 32 GB of DDR2 SDRAM memory. Our implementation of Linpack also supports clusters of QS22s, and was used to achieve a result of 11.1 TFLOPS on a cluster of 84 QS22 blades. We compare our results on a single BladeCenter QS22 with the base Linpack implementation without SPE acceleration to illustrate the benefits of our optimizations.

  3. New development for low energy electron beam processor

    International Nuclear Information System (INIS)

    Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

    2003-01-01

    Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

  4. Identity by descent fine mapping of familial adult myoclonus epilepsy (FAME) to 2p11.2-2q11.2.

    Science.gov (United States)

    Henden, Lyndal; Freytag, Saskia; Afawi, Zaid; Baldassari, Sara; Berkovic, Samuel F; Bisulli, Francesca; Canafoglia, Laura; Casari, Giorgio; Crompton, Douglas Ewan; Depienne, Christel; Gecz, Jozef; Guerrini, Renzo; Helbig, Ingo; Hirsch, Edouard; Keren, Boris; Klein, Karl Martin; Labauge, Pierre; LeGuern, Eric; Licchetta, Laura; Mei, Davide; Nava, Caroline; Pippucci, Tommaso; Rudolf, Gabrielle; Scheffer, Ingrid Eileen; Striano, Pasquale; Tinuper, Paolo; Zara, Federico; Corbett, Mark; Bahlo, Melanie

    2016-10-01

    Familial adult myoclonus epilepsy (FAME) is a rare autosomal dominant disorder characterized by adult onset, involuntary muscle jerks, cortical myoclonus and occasional seizures. FAME is genetically heterogeneous with more than 70 families reported worldwide and five potential disease loci. The efforts to identify potential causal variants have been unsuccessful in all but three families. To date, linkage analysis has been the main approach to find and narrow FAME critical regions. We propose an alternative method, pedigree free identity-by-descent (IBD) mapping, that infers regions of the genome between individuals that have been inherited from a common ancestor. IBD mapping provides an alternative to linkage analysis in the presence of allelic and locus heterogeneity by detecting clusters of individuals who share a common allele. Succeeding IBD mapping, gene prioritization based on gene co-expression analysis can be used to identify the most promising candidate genes. We performed an IBD analysis using high-density single nucleotide polymorphism (SNP) array data followed by gene prioritization on a FAME cohort of ten European families and one Australian/New Zealander family; eight of which had known disease loci. By identifying IBD regions common to multiple families, we were able to narrow the FAME2 locus to a 9.78 megabase interval within 2p11.2-q11.2. We provide additional evidence of a founder effect in four Italian families and allelic heterogeneity with at least four distinct founders responsible for FAME at the FAME2 locus. In addition, we suggest candidate disease genes using gene prioritization based on gene co-expression analysis.

  5. A data base processor semantics specification package

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

  6. The GF11 project at IBM

    International Nuclear Information System (INIS)

    Sexton, J.C.

    1990-01-01

    The GF11 project at IBM's T. J. Watson Research Center is entering full production for QCD numerical calculations. This paper describes the GF11 hardware and system software, and discusses the first production program which has been developed to run on GF11. This program is a variation of the Cabbibo Marinari pure gauge Monte Carlo program for SU(3) and is currently sustaining almost 6 gigaflops on 360 processors in GF11

  7. The GF11 project at IBM

    Science.gov (United States)

    Sexton, James C.

    1990-08-01

    The GF11 project at IBM's T. J. Watson Research Center is entering full production for QCD numerical calculations. This paper describes the GF11 hardware and system software, and discusses the first production program which has been developed to run on GF11. This program is a variation of the Cabbibo Marinari pure gauge Monte Carlo program for SU(3) and is currently sustaining almost 6 gigaflops on 360 processors in GF11.

  8. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  9. MAP3D: a media processor approach for high-end 3D graphics

    Science.gov (United States)

    Darsa, Lucia; Stadnicki, Steven; Basoglu, Chris

    1999-12-01

    Equator Technologies, Inc. has used a software-first approach to produce several programmable and advanced VLIW processor architectures that have the flexibility to run both traditional systems tasks and an array of media-rich applications. For example, Equator's MAP1000A is the world's fastest single-chip programmable signal and image processor targeted for digital consumer and office automation markets. The Equator MAP3D is a proposal for the architecture of the next generation of the Equator MAP family. The MAP3D is designed to achieve high-end 3D performance and a variety of customizable special effects by combining special graphics features with high performance floating-point and media processor architecture. As a programmable media processor, it offers the advantages of a completely configurable 3D pipeline--allowing developers to experiment with different algorithms and to tailor their pipeline to achieve the highest performance for a particular application. With the support of Equator's advanced C compiler and toolkit, MAP3D programs can be written in a high-level language. This allows the compiler to successfully find and exploit any parallelism in a programmer's code, thus decreasing the time to market of a given applications. The ability to run an operating system makes it possible to run concurrent applications in the MAP3D chip, such as video decoding while executing the 3D pipelines, so that integration of applications is easily achieved--using real-time decoded imagery for texturing 3D objects, for instance. This novel architecture enables an affordable, integrated solution for high performance 3D graphics.

  10. XL-100S microprogrammable processor

    International Nuclear Information System (INIS)

    Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

    1983-01-01

    The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

  11. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  12. Simulation of a processor switching circuit with APLSV

    International Nuclear Information System (INIS)

    Dilcher, H.

    1979-01-01

    The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

  13. Accuracy Limitations in Optical Linear Algebra Processors

    Science.gov (United States)

    Batsell, Stephen Gordon

    1990-01-01

    One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

  14. The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

    International Nuclear Information System (INIS)

    Maenner, R.; Deluigi, B.

    1981-01-01

    The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

  15. Tumor-specific loss of 11p15.5 alleles in del11p13 Wilms tumor and in familial adrenocortical carcinoma

    International Nuclear Information System (INIS)

    Henry, I.; Grandjouan, S.; Couillin, P.

    1989-01-01

    The authors have compared constitutional and tumor genotypes in nine cases of hereditary Wilms tumor (WT) and in three unrelated cases of familial adrenocortical carcinoma (ADCC). Since susceptibility to these tumors can be observed in malformation syndromes associated with a constitutional deletion of band 11p13 (WT) and with a constitutional duplication of band 11p15.5 (WT, ADCC), they investigated these two candidate regions by using 11p polymorphic markers. As expected, somatic chromosomal events, resulting in a loss of heterozygosity limited to region 11p15.5, were observed in the tumor of two familial cases of adrenocortical carcinoma. Surprisingly, however, analysis of the WT of two patients with a constitutional deletion of band 11p13, associated with aniridia, genitourinary abnormalities, and mental retardation (WAGR syndrome), revealed a loss of heterozygosity limited to region 11p15.5. These data therefore suggest that observation of a specific loss of heterozygosity may not necessarily point to the site of the initial germinal mutation. Together with previous similar observations of a loss of heterozygosity limited to 11p15.5 in breast cancer and in rhabdomyosarcoma, the data suggest that region 11p15.5 may carry a non-tissue-specific gene that could be involved in genetic predisposition, in tumor progression, or in both

  16. A dedicated line-processor as used at the SHF

    International Nuclear Information System (INIS)

    Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

    1985-01-01

    A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

  17. Cochlear implants: 100 pediatric case conversions from the body worn to the nucleus esprit 22 ear level speech processor.

    Science.gov (United States)

    Dodd, M C; Nikolopoulos, T P; Totten, C; Cope, Y; O'Donoghue, G M

    2005-07-01

    To assess performance of Nucleus 22 mini system pediatric users converted from the Spectra 22 body-worn to the ESPrit 22 ear-level speech processor using aided thresholds and speech discrimination measures before and after the conversion. Spectra 22 body-worn speech processor users were chosen using preselection criteria (stable map, ability to report on the quality of the signal, no device problems). The subjects underwent tuning, map conversion, fitting of the ESPrit 22, and aided soundfield threshold and speech discrimination testing. The first 100 consecutive conversions are analyzed in this study. Fifty children (50%) were female, and 50 (50%) were male. The average age at implantation was 4.6 years (median 4.3 years, range 1.7 to 11 years). The average age of fitting the ear level speech processor was 11.1 years (median 11 years, range 6.2 to 18.2 years). Tertiary referral pediatric cochlear implant center in the United Kingdom. Of the 100 fittings attempted, all Spectra 22 maps could to be converted for use in the ESPrit 22. Of these 100 fittings, 44 were straightforward with no adjustment to map parameters being required, and 56 needed rate reductions and other map adjustments to achieve the conversion. The difference of the mean thresholds before and after the conversion did not exceed 2 dB across the frequencies studied (0.5-4 kHz). In 95% of the cases, the differences were less than 9 dB(A). With regard to speech discrimination testing, the mean threshold before the conversion was 53.4 dB and after the conversion 52.7 dB. Of the 100 conversions, only five children stopped using the ESPrit 22 despite fitting being achieved. Conversion from the Spectra 22 body worn to the ESPrit 22 ear level speech processor was found to be feasible in all the 100 cases studied. Only a minority (5%) of children chose not to use the ear level speech processor suggesting that children and parents were satisfied from the conversion.

  18. Embedded processor extensions for image processing

    Science.gov (United States)

    Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

    2008-04-01

    The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

  19. Sojourn time tails in processor-sharing systems

    NARCIS (Netherlands)

    Egorova, R.R.

    2009-01-01

    The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

  20. An interactive parallel processor for data analysis

    International Nuclear Information System (INIS)

    Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

    1984-01-01

    A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

  1. Optical Array Processor: Laboratory Results

    Science.gov (United States)

    Casasent, David; Jackson, James; Vaerewyck, Gerard

    1987-01-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

  2. Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

    OpenAIRE

    Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

    2016-01-01

    International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

  3. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  4. Synthetic Aperture Radar Technology Conference, New Mexico State University, Las Cruces, N. Mex., March 8-10, 1978, Proceedings

    Science.gov (United States)

    1978-01-01

    The following aspects of SAR development are discussed: calibration techniques, image simulation and interpretability, antennas, data processing, and system design. Papers are presented on such topics as a postlaunch calibration experiment for the Seasat-A SAR, computer simulation of an orbital SAR system, definition study of the Shuttle Imaging Radar, custom LSI circuits for spaceborne SAR processors, and random sampling adaptively focusing SAR.

  5. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  6. High-speed packet filtering utilizing stream processors

    Science.gov (United States)

    Hummel, Richard J.; Fulp, Errin W.

    2009-04-01

    Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

  7. Rab11 family expression in the human placenta: Localization at the maternal-fetal interface

    Science.gov (United States)

    Artemiuk, Patrycja A.; Hanscom, Sara R.; Lindsay, Andrew J.; Wuebbolt, Danielle; Breathnach, Fionnuala M.; Tully, Elizabeth C.; Khan, Amir R.; McCaffrey, Mary W.

    2017-01-01

    Rab proteins are a family of small GTPases involved in a variety of cellular processes. The Rab11 subfamily in particular directs key steps of intracellular functions involving vesicle trafficking of the endosomal recycling pathway. This Rab subfamily works through a series of effector proteins including the Rab11-FIPs (Rab11 Family-Interacting Proteins). While the Rab11 subfamily has been well characterized at the cellular level, its function within human organ systems is still being explored. In an effort to further study these proteins, we conducted a preliminary investigation of a subgroup of endosomal Rab proteins in a range of human cell lines by Western blotting. The results from this analysis indicated that Rab11a, Rab11c(Rab25) and Rab14 were expressed in a wide range of cell lines, including the human placental trophoblastic BeWo cell line. These findings encouraged us to further analyse the localization of these Rabs and their common effector protein, the Rab Coupling Protein (RCP), by immunofluorescence microscopy and to extend this work to normal human placental tissue. The placenta is a highly active exchange interface, facilitating transfer between mother and fetus during pregnancy. As Rab11 proteins are closely involved in transcytosis we hypothesized that the placenta would be an interesting human tissue model system for Rab investigation. By immunofluorescence microscopy, Rab11a, Rab11c(Rab25), Rab14 as well as their common FIP effector RCP showed prominent expression in the placental cell lines. We also identified the expression of these proteins in human placental lysates by Western blot analysis. Further, via fluorescent immunohistochemistry, we noted abundant localization of these proteins within key functional areas of primary human placental tissues, namely the outer syncytial layer of placental villous tissue and the endothelia of fetal blood vessels. Overall these findings highlight the expression of the Rab11 family within the human

  8. Enhancement of 6-pentyl-α-pyrone fermentation activity in an extractive liquid-surface immobilization (Ext-LSI) system by mixing anion-exchange resin microparticles.

    Science.gov (United States)

    Oda, Shinobu; Michihata, Sayumi; Sakamoto, Naoki; Horibe, Hideo; Kono, Akihiko; Ohashi, Shinichi

    2012-12-01

    The addition of anion-exchange resin microparticles into a polyacrylonitrile (PAN) ballooned microsphere layer drastically enhanced the fermentative activity of Trichoderma atroviride AG2755-5NM398 in an extractive liquid-surface immobilization (Ext-LSI) system. The production of 6-pentyl-α-pyrone (6PP), a fungicidal secondary metabolite, was 1.92-fold higher than the control (PAN alone). Copyright © 2012 The Society for Biotechnology, Japan. Published by Elsevier B.V. All rights reserved.

  9. Fast processor for dilepton triggers

    International Nuclear Information System (INIS)

    Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

    1983-01-01

    We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

  10. Design of RISC Processor Using VHDL and Cadence

    Science.gov (United States)

    Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

    The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

  11. DDX11L: a novel transcript family emerging from human subtelomeric regions

    Directory of Open Access Journals (Sweden)

    D'Urso Michele

    2009-05-01

    Full Text Available Abstract Background The subtelomeric regions of human chromosomes exhibit an extraordinary plasticity. To date, due to the high GC content and to the presence of telomeric repeats, the subtelomeric sequences are underrepresented in the genomic libraries and consequently their sequences are incomplete in the finished human genome sequence, and still much remains to be learned about subtelomere organization, evolution and function. Indeed, only in recent years, several studies have disclosed, within human subtelomeres, novel gene family members. Results During a project aimed to analyze genes located in the telomeric region of the long arm of the human X chromosome, we have identified a novel transcript family, DDX11L, members of which map to 1pter, 2q13/14.1, 2qter, 3qter, 6pter, 9pter/9qter, 11pter, 12pter, 15qter, 16pter, 17pter, 19pter, 20pter/20qter, Xpter/Xqter and Yqter. Furthermore, we partially sequenced the underrepresented subtelomeres of human chromosomes showing a common evolutionary origin. Conclusion Our data indicate that an ancestral gene, originated as a rearranged portion of the primate DDX11 gene, and propagated along many subtelomeric locations, is emerging within subtelomeres of human chromosomes, defining a novel gene family. These findings support the possibility that the high plasticity of these regions, sites of DNA exchange among different chromosomes, could trigger the emergence of new genes.

  12. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-02-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  13. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

  14. RSX system development under VAX/VMS compatibility mode

    International Nuclear Information System (INIS)

    Fuka, M.A.

    1983-01-01

    The Control System for the Proton Storage Ring now being built at Los Alamos will use a VAX-11/750 as its main control computer with several LSI-11/23 microprocessors reading and controlling the hardware. The VMS Compatibility Mode makes it possible to use the VAX as a development system for the LSI-11/23 microprocessors running the RSX-11S (stand-alone) operating system. Digital Equipment Corporation (DEC)-supplied software is used to generate the RSX-11S operating system and DECNET-11S network software. We use the VMS editors to create source files, the Macro-11 assembler and the PDP-11 Fortran-77 compiler to generate object code, and the RSX Task Builder to link the executable RSX task image. The RSX task then can be tested to some extent on the VAX before it is down-line loaded to the LSI-11/23 for further testing

  15. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

  16. A high-speed CAMAC data acquisition system for PDP-11

    International Nuclear Information System (INIS)

    Berg, D.M.; Heinicke, P.; Quigg, L.

    1985-01-01

    This paper describes a high-speed data acquisition system for a PDP-11 running under the RSX-11M operating system. It has been used by several high-energy physics experiments at Fermilab. The system consists of several coordinated tasks which acquire data through a CAMAC interface, log data to magnetic tape, supply data to independent monitoring and analysis tasks (such as RSXMULTI), and perform control functions. A data buffer extending beyond the 18-bit address space of the PDP-11 is implemented using Konelar bank-switchable memory. Supported configurations range from small systems with single data acquisition and analysis tasks on the same processor, to large multi-processor systems with data acquisition on several PDPs and analysis on separate PDPs or VAXs

  17. Air-Lubricated Thermal Processor For Dry Silver Film

    Science.gov (United States)

    Siryj, B. W.

    1980-09-01

    Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

  18. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  19. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

    1995-01-01

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  20. Fast track trigger processor for the OPAL detector at LEP

    Energy Technology Data Exchange (ETDEWEB)

    Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

    1986-09-20

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

  1. Benchmarking Data Analysis and Machine Learning Applications on the Intel KNL Many-Core Processor

    OpenAIRE

    Byun, Chansup; Kepner, Jeremy; Arcand, William; Bestor, David; Bergeron, Bill; Gadepally, Vijay; Houle, Michael; Hubbell, Matthew; Jones, Michael; Klein, Anna; Michaleas, Peter; Milechin, Lauren; Mullen, Julie; Prout, Andrew; Rosa, Antonio

    2017-01-01

    Knights Landing (KNL) is the code name for the second-generation Intel Xeon Phi product family. KNL has generated significant interest in the data analysis and machine learning communities because its new many-core architecture targets both of these workloads. The KNL many-core vector processor design enables it to exploit much higher levels of parallelism. At the Lincoln Laboratory Supercomputing Center (LLSC), the majority of users are running data analysis applications such as MATLAB and O...

  2. A digital, decentralized power station control system with bus-transmission facilitates the problem of backfitting

    International Nuclear Information System (INIS)

    Kaiser, G.E.; Schemmel, R.R.

    1985-01-01

    Current NPP control equipment technology is essentially characterized by the transmission of information in parallel using individual cables, and utilizes hardwired techniques for the processing of information. Progress in the area of semiconductor development characterized by micro-processors and LSI-circuits, has opened up new possibilities for the solution of the control tasks. The new power station control system PROCONTROL P utilizes these possibilities

  3. Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

    Science.gov (United States)

    Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

    2013-03-01

    With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

  4. Optical backplane interconnect switch for data processors and computers

    Science.gov (United States)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  5. New roles in hemicellulosic sugar fermentation for the uncultivated Bacteroidetes family BS11

    Energy Technology Data Exchange (ETDEWEB)

    Solden, Lindsey M.; Hoyt, David W.; Collins, William B.; Plank, Johanna E.; Daly, Rebecca A.; Hildebrand, Erik; Beavers, Timothy J.; Wolfe, Richard; Nicora, Carrie D.; Purvine, Sam O.; Carstensen, Michelle; Lipton, Mary S.; Spalinger, Donald E.; Firkins, Jeffrey L.; Wolfe, Barbara A.; Wrighton, Kelly C.

    2016-12-13

    Ruminants have co-evolved with their gastrointestinal microbial communities that aid in the digestion of plant materials, providing energy for the host. The ability of this microbiome to adapt to altered host diets may dramatically impact the survival of wild ruminant populations, especially under future climate change scenarios. To identify microorganisms capable of degrading climatedriven increases in woody biomass in arctic and boreal regions, we sampled rumen fluids from Alaskan moose foraging along a seasonal lignocellulose gradient. Winter diets with increased hemicellulose and lignin enriched for BS11, a Bacteroidetes family lacking cultivated or genomically sampled representatives. Our findings show that the BS11 are cosmopolitan host-associated bacteria prevalent in gastrointestinal tracts of ruminants and other mammals, including humans. Metagenomic reconstruction yielded the first five BS11 genomes, phylogenetically resolving two genera within this taxonomically undefined family. Genome-enabled metabolic analyses uncovered multiple pathways for degrading hemicellulose sugars to short-chain fatty acids, metabolites vital for ruminant energy. Active hemicellulosic fermentation, as well as butyrate and acetate production, were validated by shotgun proteomics and rumen metabolite detection using NMR, illuminating the vital role BS11 play in carbon transformations within the rumen. These results demonstrate that woody biomass selects for BS11 members, providing arctic herbivores with metabolic redundancy to sustain energy generation in a changing vegetative environment.

  6. Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

    Science.gov (United States)

    Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

    2009-01-30

    Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

  7. Fast digital processor for event selection according to particle number difference

    International Nuclear Information System (INIS)

    Basiladze, S.G.; Gus'kov, B.N.; Li Van Sun; Maksimov, A.N.; Parfenov, A.N.

    1978-01-01

    A fast digital processor for a magnetic spectrometer is described. It is used in experimental searches for charmed particles. The basic purpose of the processor is discriminating events in the difference of numbers of particles passing through two proportional chambers (PC). The processor consists of three units for detecting signals with PC, and a binary coder. The number of inputs of the processor is 32 for the first PC and 64 for the second. The difference in the number of particles discriminated is from 0 to 8. The resolution time is 180 ns. The processor is built in the CAMAC standard

  8. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  9. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  10. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  11. A Family-Based Association Study of CYP11A1 and CYP11B1 Gene Polymorphisms With Autism in Chinese Trios.

    Science.gov (United States)

    Deng, Hong-Zhu; You, Cong; Xing, Yu; Chen, Kai-Yun; Zou, Xiao-Bing

    2016-05-01

    Autism spectrum disorder is a group of neurodevelopmental disorders with the higher prevalence in males. Our previous studies have indicated lower progesterone levels in the children with autism spectrum disorder, suggesting involvement of the cytochrome P-450scc gene (CYP11A1) and cytochrome P-45011beta gene (CYP11B1) as candidate genes in autism spectrum disorder. The aim of this study was to investigate the family-based genetic association between single-nucleotide polymorphisms, rs2279357 in the CYP11A1 gene and rs4534 and rs4541 in the CYP11B1 gene and autism spectrum disorder in Chinese children, which were selected according to the location in the coding region and 5' and 3' regions and minor allele frequencies of greater than 0.05 in the Chinese populations. The transmission disequilibrium test and case-control association analyses were performed in 100 Chinese Han autism spectrum disorder family trios. The genotype and allele frequency of the 3 single-nucleotide polymorphisms had no statistical difference between the children with autism spectrum disorder and their parents (P> .05). Transmission disequilibrium test analysis showed transmission disequilibrium of CYP11A1 gene rs2279357 single-nucleotide polymorphisms (χ(2)= 5.038,Pautism spectrum disorder exists within or near the CYP11A1 gene in the Han Chinese population. © The Author(s) 2015.

  12. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  13. Case Study of Using High Performance Commercial Processors in Space

    Science.gov (United States)

    Ferguson, Roscoe C.; Olivas, Zulema

    2009-01-01

    The purpose of the Space Shuttle Cockpit Avionics Upgrade project (1999 2004) was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. An early version of this system was tested at the Johnson Space Center for one month by teams of astronauts. The results were positive, but NASA eventually cancelled the project towards the end of the development cycle. The goal to reduce crew workload and improve situational awareness resulted in the need for high performance Central Processing Units (CPUs). The choice of CPU selected was the PowerPC family, which is a reduced instruction set computer (RISC) known for its high performance. However, the requirement for radiation tolerance resulted in the re-evaluation of the selected family member of the PowerPC line. Radiation testing revealed that the original selected processor (PowerPC 7400) was too soft to meet mission objectives and an effort was established to perform trade studies and performance testing to determine a feasible candidate. At that time, the PowerPC RAD750s were radiation tolerant, but did not meet the required performance needs of the project. Thus, the final solution was to select the PowerPC 7455. This processor did not have a radiation tolerant version, but had some ability to detect failures. However, its cache tags did not provide parity and thus the project incorporated a software strategy to detect radiation failures. The strategy was to incorporate dual paths for software generating commands to the legacy Space Shuttle avionics to prevent failures due to the softness of the upgraded avionics.

  14. Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1989-10-01

    The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

  15. Evaluation of the Intel Westmere-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

  16. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  17. Development of level 2 processor for the readout of TMC

    International Nuclear Information System (INIS)

    Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

    1995-01-01

    We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

  18. Discovering Motifs in Biological Sequences Using the Micron Automata Processor.

    Science.gov (United States)

    Roy, Indranil; Aluru, Srinivas

    2016-01-01

    Finding approximately conserved sequences, called motifs, across multiple DNA or protein sequences is an important problem in computational biology. In this paper, we consider the (l, d) motif search problem of identifying one or more motifs of length l present in at least q of the n given sequences, with each occurrence differing from the motif in at most d substitutions. The problem is known to be NP-complete, and the largest solved instance reported to date is (26,11). We propose a novel algorithm for the (l,d) motif search problem using streaming execution over a large set of non-deterministic finite automata (NFA). This solution is designed to take advantage of the micron automata processor, a new technology close to deployment that can simultaneously execute multiple NFA in parallel. We demonstrate the capability for solving much larger instances of the (l, d) motif search problem using the resources available within a single automata processor board, by estimating run-times for problem instances (39,18) and (40,17). The paper serves as a useful guide to solving problems using this new accelerator technology.

  19. Assessing the predictive capability of optical imaging techniques, Spatial Frequency Domain Imaging (SFDI) and Laser Speckle Imaging (LSI), to the gold standard of clinical assessment in a controlled animal model

    Science.gov (United States)

    Ponticorvo, A.; Rowland, R.; Baldado, M.; Burmeister, D. M.; Christy, R. J.; Bernal, N.; Durkin, A. J.

    2018-02-01

    The current standard for assessment of burn severity and subsequent wound healing is through clinical examination, which is highly subjective. Accurate early assessment of burn severity is critical for dictating the course of wound management. Complicating matters is the fact that burn wounds are often large and can have multiple regions that vary in severity. In order to manage the treatment more effectively, a tool that can provide spatially resolved information related to mapping burn severity could aid clinicians when making decisions. Several new technologies focus on burn care in an attempt to help clinicians objectively determine burn severity. By quantifying perfusion, laser speckle imaging (LSI) has had success in categorizing burn wound severity at earlier time points than clinical assessment alone. Additionally, spatial frequency domain imaging (SFDI) is a new technique that can quantify the tissue structural damage associated with burns to achieve earlier categorization of burn severity. Here we compared the performance of a commercial LSI device (PeriCam PSI, Perimed Inc.), a SFDI device (Reflect RSTM, Modulated Imaging Inc.) and conventional clinical assessment in a controlled (porcine) model of graded burn wound severity over the course of 28 days. Specifically we focused on the ability of each system to predict the spatial heterogeneity of the healed wound at 28 days, based on the images at an early time point. Spatial heterogeneity was defined by clinical assessment of distinct regions of healing on day 28. Across six pigs, 96 burn wounds (3 cm diameter) were created. Clinical assessment at day 28 indicated that 39 had appeared to heal in a heterogeneous manner. Clinical observation at day 1 found 35 / 39 (90%) to be spatially heterogeneous in terms of burn severity. The LSI system was able to detect spatial heterogeneity of burn severity in 14 / 39 (36%) cases on day 1 and 23 / 39 cases (59%) on day 7. By contrast the SFDI system was able to

  20. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  1. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  2. INTEGRAL and XMM-Newton observations of the puzzling binary system LSI +61 303

    Science.gov (United States)

    Chernyakova, Masha; Neronov, A.; Walter, R.

    LSI +61° 303 is one of the few X-ray binaries with Be star companion from which both radio and high-energy gamma-ray emission have been observed. We present XMM-Newton and INTE- GRAL observations which reveal variability of the X-ray spectral index of the system. The X-ray spectrum is hard (photon index Γ ≃ 1.5) during the orbital phases of both high and low X-ray flux. However, the spectrum softens at the moment of transition from high to low X-ray state. The spectrum of the system in the hard X-ray band does not reveal the presence of a cut-off (or, at least a spectral break) at 10-60 keV energies, expected if the compact object is an accreting neu- tron star. The observed spectrum and spectral variability can be explained if the compact object in the system is a rotation powered pulsar. In this case the recently found X-ray spectral variability of the system on the several kiloseconds time scale can be explained by the clumpy structure of the Be star disk.

  3. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  4. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  5. Researching, building a soft-processor and Ethernet interface circuit using EDK

    International Nuclear Information System (INIS)

    Tuong Thi Thu Huong; Pham Ngoc Tuan; Truong Van Dat, Dang Lanh; Chau Thi Nhu Quynh

    2014-01-01

    The processor is an indispensable component in the measurement and automatic control systems. This report describes the fabrication of a soft-processor (32-bits, on-chip block RAM 64K, 50M clock, internal and peripheral bus) for receiving, sending and processing of data Ethernet packets. This processor is fabricated using the XPS component from EDK (Xilinx) software toolkit. After that, it is configured on the FPGA named Spartan XC3S500E circuit. A firmware of a processor for controlling the interface between processor and Ethernet port is written in C language and can play a role of a HOST (station) which has its own IP to connect to Ethernet network. Besides, there are some needed parts as follows: an Ethernet interfacing controller chip, a suitable cable providing a speed up to 100 Mbs and an application program running under Window XP environment written in LabView to communicate with soft-processor. (author)

  6. A high-accuracy optical linear algebra processor for finite element applications

    Science.gov (United States)

    Casasent, D.; Taylor, B. K.

    1984-01-01

    Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

  7. Integrated Target Acquisition and Fire Control Systems: Avionics Panel Symposium Held in Ottawa, Canada on 7-10 October 1991 (Systemes Integres d’Acquisition d’Objectifs et de Conduite de Tir)

    Science.gov (United States)

    1992-02-01

    quality imagery and engagement3 witth rapid imagery indirect fire to maximize interpretation to provide the effect of long range timely information...blackwht Fig 8 Accumulated histogram We used an LSI Logic L64250 Histogram Hough Processor ( HtP ) chip to perform histogram equalization. This device...serving as main controllers of the basic transmitted via data link or inserted manually by avionic system to ensure the moding and monitoring the crew

  8. Air Force Research Laboratory Sensors Directorate Communications Branch History from 1960-2011

    Science.gov (United States)

    2011-12-01

    the National Command Authority ( NCA ) and U.S. strategic and non-strategic forces. The E-6B was conceived as a replacement for the Air Force’s Airborne...application. The physical design will meet a l-cubic-foot volume goal, given LSI processor development and large- cathode , folded-dynode photomultiplier...development. Performance limiters are the input optics ’transmission at large zenith angles and photodetector cathode quantum efficiency at the

  9. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  10. Low voltage 80 KV to 125 KV electron processors

    International Nuclear Information System (INIS)

    Lauppi, U.V.

    1999-01-01

    The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

  11. A fast track trigger processor for the OPAL detector at LEP

    International Nuclear Information System (INIS)

    Carter, A.A.; Jaroslawski, S.; Wagner, A.

    1986-01-01

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented. (orig.)

  12. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  13. Expansion of ribosomally produced natural products: a nitrile hydratase- and Nif11-related precursor family

    Directory of Open Access Journals (Sweden)

    Mitchell Douglas A

    2010-05-01

    Full Text Available Abstract Background A new family of natural products has been described in which cysteine, serine and threonine from ribosomally-produced peptides are converted to thiazoles, oxazoles and methyloxazoles, respectively. These metabolites and their biosynthetic gene clusters are now referred to as thiazole/oxazole-modified microcins (TOMM. As exemplified by microcin B17 and streptolysin S, TOMM precursors contain an N-terminal leader sequence and C-terminal core peptide. The leader sequence contains binding sites for the posttranslational modifying enzymes which subsequently act upon the core peptide. TOMM peptides are small and highly variable, frequently missed by gene-finders and occasionally situated far from the thiazole/oxazole forming genes. Thus, locating a substrate for a particular TOMM pathway can be a challenging endeavor. Results Examination of candidate TOMM precursors has revealed a subclass with an uncharacteristically long leader sequence closely related to the enzyme nitrile hydratase. Members of this nitrile hydratase leader peptide (NHLP family lack the metal-binding residues required for catalysis. Instead, NHLP sequences display the classic Gly-Gly cleavage motif and have C-terminal regions rich in heterocyclizable residues. The NHLP family exhibits a correlated species distribution and local clustering with an ABC transport system. This study also provides evidence that a separate family, annotated as Nif11 nitrogen-fixing proteins, can serve as natural product precursors (N11P, but not always of the TOMM variety. Indeed, a number of cyanobacterial genomes show extensive N11P paralogous expansion, such as Nostoc, Prochlorococcus and Cyanothece, which replace the TOMM cluster with lanthionine biosynthetic machinery. Conclusions This study has united numerous TOMM gene clusters with their cognate substrates. These results suggest that two large protein families, the nitrile hydratases and Nif11, have been retailored for

  14. Satellite on-board real-time SAR processor prototype

    Science.gov (United States)

    Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

    2017-11-01

    A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

  15. Recursive Matrix Inverse Update On An Optical Processor

    Science.gov (United States)

    Casasent, David P.; Baranoski, Edward J.

    1988-02-01

    A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

  16. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  17. Graphical user interface for TOUGH/TOUGH2 - development of database, pre-processor, and post-processor

    Energy Technology Data Exchange (ETDEWEB)

    Sato, Tatsuya; Okabe, Takashi; Osato, Kazumi [Geothermal Energy Research and Development Co., Ltd., Tokyo (Japan)

    1995-03-01

    One of the advantages of the TOUGH/TOUGH2 (Pruess, 1987 and 1991) is the modeling using {open_quotes}free shape{close_quotes} polygonal blocks. However, the treatment of three-dimensional information, particularly for TOUGH/TOUGH2 is not easy because of the {open_quotes}free shape{close_quotes} polygonal blocks. Therefore, we have developed a database named {open_quotes}GEOBASE{close_quotes} and a pre/post-processor named {open_quotes}GEOGRAPH{close_quotes} for TOUGH/TOUGH2 on engineering work station (EWS). {open_quotes}GEOGRAPH{close_quotes} is based on the ORACLE{sup *1} relational database manager system to access data sets of surface exploration (geology, geophysics, geochemistry, etc.), drilling (well trajectory, geological column, logging, etc.), well testing (production test, injection test, interference test, tracer test, etc.) and production/injection history.{open_quotes}GEOGRAPH{close_quotes} consists of {open_quotes}Pre-processor{close_quotes} that can construct the three-dimensional free shape reservoir modeling by mouse operation on X-window and {open_quotes}Post-processor{close_quotes} that can display several kinds of two/three-dimensional maps and X-Y plots to compile data on {open_quotes}GEOBASE{close_quotes} and result of TOUGH/TOUGH2 calculation. This paper shows concept of the systems and examples of utilization.

  18. FY1995 study of low power LSI design automation software with parallel processing; 1995 nendo heiretsu shori wo katsuyoshita shodenryoku LSI muke sekkei jidoka software no kenkyu kaihatsu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The needs for low power LSIs have rapidly increased recently. For the low power LSI development, not only new circuit technologies but also new design automation tools supporting the new technologies are indispensable. The purpose of this project is to develop a new design automation software, which is able to design new digital LSIs with much lower power than that of conventional CMOS LSIs. A new design automation software for very low power LSIs has been developed targeting the pass-transistor logic SPL, a dedicated low power circuit technology. The software includes a logic synthesis function for pass-transistor-based macrocells and a macrocell placement function. Several new algorithms have been developed for the software, e.g. BDD construction. Some of them are designed and implemented for parallel processing in order to reduce the processing time. The logic synthesis function was tested on a set of benchmarks and finally applied to a low power CPU design. The designed 8-bit CPU was fully compatible with Zilog Z-80. The power dissipation of the CPU was compared with that of commercial CMOS Z-80. At most 82% of power of CMOS was reduced by the new CPU. On the other hand, parallel processing speed up was measured on the macrocell placement function. 34 folds speed up was realized. (NEDO)

  19. Biomass is beginning to threaten the wood-processors

    International Nuclear Information System (INIS)

    Beer, G.; Sobinkovic, B.

    2004-01-01

    In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

  20. EPROM-based LSI-11 for distributed instrumentation control

    International Nuclear Information System (INIS)

    Hunt, D.N.

    1981-01-01

    The LLNL Nuclear Chemistry Counting Facility (NCCF) is being converted to a modern production facility. A computer network has been designed and built to implement this conversion. The outermost node of the computer network is a dedicated EPROM-based controller. The controller handles the details of driving the attached nuclear instrumentation, providing a standard interface to the remainder of the network. This paper addresses the design and the implementation of the dedicated instrumentation controller

  1. The S-1 Spheromak Control System

    International Nuclear Information System (INIS)

    Mathe, P.; Mika, R.; Oliaro, G.

    1983-01-01

    The use of a CAMAC based DEC LSI-11/23 microcomputer to perform all control functions for the S-1 Spheromak is described. The system monitors and controls the three coil systems, Toroidal, Poloidal, and Equilibrium field coils and their associated power sources, the water cooling system, the personnel and machine safety system, the machine and diagnostic timing system and the control room display and operator interface. Future requirements include control of the vacuum system, the gas injection system and interface to the PPPL Data Acquisition System DEC10. The computer is connected to five remotely located CAMAC crates by a fiber-optic serial highway operating at five megahertz. These crates contain interface modules required to control the S-1 experiment. These modules include: D/A and A/D converters, fast transient digitizers, timing modules, temperature sensing modules, CRT alphanumeric display drivers, watchdog timers, and relay and TTL parallel I/O ports. The computer itself resides in crate number0 and consists of an LSI-11/23 with hardware floating post processor, memory management, 256K bytes of memory, four RS-232 serial ports and a 30 megabyte hard disk with a one megabyte floppy disk backup. The majority of software is written in FORTRAN with a few speed critical programs written in PDP-11 MACRO assembly language. The software simulates a sequential state machine which allows easily changeable logic since all logic is represented by standard Boolean Fortran statements. The RSX-11/m operating system allows multiple tasks to be active simultaneously. This provides computing time for operator interactions, editing of critical machine parameters, data analysis and transmission of data to other computers while still maintaining the scan activity which constantly monitors machine parameters

  2. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  3. Parallel processor for fast event analysis

    International Nuclear Information System (INIS)

    Hensley, D.C.

    1983-01-01

    Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

  4. Pericentric intrachromosomal insertion responsible for recurrence of del(11)(p13p14) in a family

    NARCIS (Netherlands)

    Henry, I.; Hoovers, J.; Barichard, F.; Berthéas, M. F.; Puech, A.; Prieur, F.; Gessler, M.; Bruns, G.; Mannens, M.; Junien, C.

    1993-01-01

    The combined use of qualitative and quantitative analysis of 11p13 polymorphic markers together with chromosomal in situ suppression hybridization (CISS) with biotin labeled probes mapping to 11p allowed us to characterize a complex rearrangement segregating in a family. We detected a pericentric

  5. Asymmetrical floating point array processors, their application to exploration and exploitation

    Energy Technology Data Exchange (ETDEWEB)

    Geriepy, B L

    1983-01-01

    An asymmetrical floating point array processor is a special-purpose scientific computer which operates under asymmetrical control of a host computer. Although an array processor can receive fixed point input and produce fixed point output, its primary mode of operation is floating point. The first generation of array processors was oriented towards time series information. The next generation of array processors has proved much more versatile and their applicability ranges from petroleum reservoir simulation to speech syntheses. Array processors are becoming commonplace in mining, the primary usage being construction of grids-by usual methods or by kriging. The Australian mining community is among the world's leaders in regard to computer-assisted exploration and exploitation systems. Part of this leadership role must be providing guidance to computer vendors in regard to current and future requirements.

  6. On the effective parallel programming of multi-core processors

    NARCIS (Netherlands)

    Varbanescu, A.L.

    2010-01-01

    Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

  7. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Baird, S.A.; Biddulph, P.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  8. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

  9. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  10. Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

    Science.gov (United States)

    Brooks, Geoffrey W.

    1996-03-01

    Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

  11. GNAQPMS v1.1: accelerating the Global Nested Air Quality Prediction Modeling System (GNAQPMS) on Intel Xeon Phi processors

    OpenAIRE

    H. Wang; H. Wang; H. Wang; H. Wang; H. Chen; H. Chen; Q. Wu; Q. Wu; J. Lin; X. Chen; X. Xie; R. Wang; R. Wang; X. Tang; Z. Wang

    2017-01-01

    The Global Nested Air Quality Prediction Modeling System (GNAQPMS) is the global version of the Nested Air Quality Prediction Modeling System (NAQPMS), which is a multi-scale chemical transport model used for air quality forecast and atmospheric environmental research. In this study, we present the porting and optimisation of GNAQPMS on a second-generation Intel Xeon Phi processor, codenamed Knights Landing (KNL). Compared with the first-generation Xeon Phi coprocessor (code...

  12. Development of a hard microcontroller

    International Nuclear Information System (INIS)

    Measel, P.R.; Sivo, L.L.; Quilitz, W.E.; Davidson, T.K.

    1976-01-01

    The applicability of commercially available microprocessors to certain systems requiring radiation survival was assessed. A microcontroller was designed and built to perform a monitor and control function of military operational ground equipment, and demonstrated to exceed the radiation hardness goal. The preparation of the microcontroller module required hardware and software design, selection of LSI and other piece part types, development of piece part and module electrical and radiation test techniques, and the performance of radiation tests on the LSI piece parts and the completed module. The microcontroller has a 16-bit central processor unit, a 4096 word read only memory, and a 256 word read-write memory. The module has circumvention circuitry, including a PIN diode radiation detector. The processor device used was the MMI 6701 T 2 L Schottky bipolar 4-bit slice. Electrical exerciser circuits were developed for in-situ electrical testing of microprocessors and memories during irradiation. A test program was developed for a Terradyne J283 microcircuit tester for more complete electrical characterization of the MMI 6701 microprocessor. A simple self-test algorithm was used in the microcontroller for performance testing during irradiation. For the operational demonstration of the microcontroller a TI 960A minicomputer was used to provide the required complex inputs to the module and verify the module outputs

  13. Industrial and scientific technology research and development project fiscal 1997 commissioned by the New Energy and Industrial Technology Development Organization. Report on research and development of a brain type computer architecture `trial fabrication and high-level evaluation on chips for a large-scale artificial neural system` and on results of evaluation studies on the chips; 1997 nendo sangyo kagaku gijutsu kenkyu kaihatsu jigyo Shin energy Sangyo Gijutsu Sogo Kaihatsu Kiko itaku. Nogata computer architecture no kenkyu kaihatsu `daikibo jinko shinkei kairo system yo chip no shisaku to kodo hyoka` chip hyoka kenkyu seika hokokusho

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1998-03-01

    In order to develop a brain type computer architecture, a brain mimic processor (BMP) has been developed (which was made in LSI in fiscal 1997), and studies are being made on developing its applications. Development has been made on an element in which linkage of one million cells with one thousand neural cells can be realized. Evaluation substrates mounted with the BMP, control software, and compilers were provided to 15 organizations including the National Research Institutes, universities, corporations, and other societies (for 19 themes) to evaluate capability of the LSI and its application development. All of the research organizations are using these items utilizing features of the LSI or the network for such purposes as learning, storage, recognition and control. The applicable theme may include infrared spectrum pattern recognition and domain division of document images using neural network functions. It can also include structural analysis of mass spectrum molecules, time series pattern recognition, location of corresponding points in images, estimation of moving images, satellite control, character recognition, short time storage, long-term association memory models, and invention process studies, all utilizing the functions of the BMP. 71 refs., 89 figs., 9 tabs.

  14. Real-time trajectory optimization on parallel processors

    Science.gov (United States)

    Psiaki, Mark L.

    1993-01-01

    A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

  15. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  16. A Processor-Sharing Scheduling Strategy for NFV Nodes

    Directory of Open Access Journals (Sweden)

    Giuseppe Faraci

    2016-01-01

    Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.

  17. Processor farming method for multi-scale analysis of masonry structures

    Science.gov (United States)

    Krejčí, Tomáš; Koudelka, Tomáš

    2017-07-01

    This paper describes a processor farming method for a coupled heat and moisture transport in masonry using a two-level approach. The motivation for the two-level description comes from difficulties connected with masonry structures, where the size of stone blocks is much larger than the size of mortar layers and very fine finite element mesh has to be used. The two-level approach is suitable for parallel computing because nearly all computations can be performed independently with little synchronization. This approach is called processor farming. The master processor is dealing with the macro-scale level - the structure and the slave processors are dealing with a homogenization procedure on the meso-scale level which is represented by an appropriate representative volume element.

  18. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  19. mAgic-FPU and MADE: A customizable VLIW core and the modular VLIW processor architecture description environment

    Science.gov (United States)

    Paolucci, Pier S.; Kajfasz, Philippe; Bonnot, Philippe; Candaele, Bernard; Maufroid, Daniel; Pastorelli, Elena; Ricciardi, Andrea; Fusella, Yves; Guarino, Eugenio

    2001-09-01

    mAgic-FPU is the architecture of a family of VLIW cores for configurable system level integration of floating and fixed point computing power. mAgic customization permits the designer to tune basic parameters, such as the computing power/memory access ratio of the core processor, the number of available arithmetic operation per cycle, the register file size and number of port, as well as of the number of arithmetic operators. The reconfiguration (e.g., of register file size and number of port, as well as of the number of arithmetic operators) is supported by the software environment MADE (Modular VLIW processor Architecture and Assembler Description Environment). MADE reads an architecture description file and produces a customized assembler-scheduler for the target VLIW architecture, configuring a general purpose VLIW optimizer-scheduler engine. The mAgic-FPU core architecture satisfies the requisite of portability among silicon foundries. The first members of the mAgic FPU core family architecture fit the requirements of 'Smart Antenna for Adaptive Beam-Forming processing' and 'Physical Sound Synthesis'. The first 1 GigaFlops mAgic core will run at 100 MHz within an area of 40 mm 2 in 0.25 μm ATMEL CMOS technology in first half 2002.

  20. Familial DiGeorge/velocardiofacial syndrome with deletions of chromosome area 22q11.2: Report of five families with a review of the literature

    Energy Technology Data Exchange (ETDEWEB)

    Leana-Cox, J.; Pangkanon, Suthipong; Eanet, K.R. [Univ. of Maryland School of Medicine, Baltimore, MD (United States)] [and others

    1996-11-11

    The DiGeorge (DG), velocardiofacial (VCF), and conotruncal anomaly-face (CTAF) syndromes were originally described as distinct disorders, although overlapping phenotypes have been recognized. It is now clear that all three syndromes result from apparently similar or identical 22q11.2 deletions, suggesting that they represent phenotypic variability of a single genetic syndrome. We report on 12 individuals in five families with del(22)(q11.2) by fluorescent in situ hybridization, and define the frequency of phenotypic abnormalities in those cases and in 70 individuals from 27 del(22)(q11.2) families from the literature. Common manifestations include mental impairment (97%), abnormal face (93%), cardiac malformations (681%), thymic (64%) and parathyroid (63%) abnormalities, and cleft palate or velopharyngeal insufficiency (48%). Familial DG, VCF, and CTAF syndromes due to del(22)(q11.2) show significant inter- and intrafamilial clinical variability consistent with the hypothesis that a single gene or group of tightly linked genes is the common cause of these syndromes. Up to 25% of 22q deletions are inherited, indicating that parents of affected children warrant molecular cytogenetic evaluation. We propose use of the compound term {open_quotes}DiGeorge/velocardiofacial (DGNCF) syndrome{close_quotes} in referring to this condition, as it calls attention to the phenotypic spectrum using historically familiar names. 41 refs., 2 figs., 2 tabs.

  1. Hardware processor for tracking particles in an alternating-gradient synchrotron

    International Nuclear Information System (INIS)

    Johnson, M.; Avilez, C.

    1987-01-01

    We discuss the design and performance of special-purpose processors for tracking particles through an alternating-gradient synchrotron. We present block diagram designs for two hardware processors. Both processors use algorithms based on the 'kick' approximation, i.e., transport matrices are used for dipoles and quadrupoles, and the thin-lens approximation is used for all higher multipoles. The faster processor makes extensive use of memory look-up tables for evaluating functions. For the case of magnets with multipoles up to pole 30 and using one kick per magnet, this processor can track 19 particles through an accelerator at a rate that is only 220 times slower than the time it takes real particles to travel around the machine. For a model consisting of only thin lenses, it is only 150 times slower than real particles. An additional factor of 2 can be obtained with chips now becoming available. The number of magnets in the accelerator is limited only by the amount of memory available for storing magnet parameters. (author) 20 refs., 7 figs., 2 tabs

  2. High-speed special-purpose processor for event selection by number of direct tracks

    International Nuclear Information System (INIS)

    Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.

    1986-01-01

    A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits

  3. Multibus-based parallel processor for simulation

    Science.gov (United States)

    Ogrady, E. P.; Wang, C.-H.

    1983-01-01

    A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

  4. Monitoring the performance of off-site processors

    International Nuclear Information System (INIS)

    Miller, C.C.

    1995-01-01

    Commercial nuclear power plants have been able to utilize the latest technologies and achieve large volume reduction by obtaining off-site waste processor services. Although the use of such services reduce the burden of waste processing it also reduces the utility's control over the process. Monitoring the performance of off-site processors is important so that the utility is cognizant of the waste disposition for required regulatory reporting. In addition to obtaining data for Reg Guide 1.21 reporting, Performance monitoring is important to determine which vendor and which services to utilize. Off-site processor services were initially offered for the decontamination of metallic waste. Since that time the list of services has expanded to include supercompaction, survey for release, incineration and metal melting. The number of vendors offering off-site services has increased and the services they offer vary. processing rates vary between vendors and have different charge bases. Determining which vendor to use for what service can be complicated and confusing

  5. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  6. Early experience with the cochlear ESPrit ear-level speech processor in children.

    Science.gov (United States)

    Totten, C; Cope, Y; McCormick, B

    2000-12-01

    The ESPrit ear-level speech processor has recently become available in the United Kingdom for use with the Nucleus CI24M multichannel cochlear implant. We report on the use of this ear-level processor with 6 children, ages 8 to 15 years. In this study, all patients were initially fitted with the SPrint body-worn processor, this being a prerequisite for programming the ESPrit. Five of the children were fitted successfully with the ESPrit and are using their devices consistently. The results show that patient experience with the ESPrit has been favorable, although there have been some device and programming difficulties. Aided threshold measures show that the ESPrit processor performs at least as well as the SPrint processor, with a trend toward improved aided thresholds for the ESPrit processor compared with the SPrint processor. Further study of the functional benefit of both of these devices may confirm these potential gains. The ESPrit device currently has a disadvantage for children in that it does not support FM radio hearing aid use. Finally, caution is advised in the fitting of the ESPrit in very young children or inexperienced listeners, because of difficulties in monitoring device function.

  7. Survey of cochlear implant user satisfaction with the Neptune™ waterproof sound processor

    Directory of Open Access Journals (Sweden)

    Jeroen J. Briaire

    2016-04-01

    Full Text Available A multi-center self-assessment survey was conducted to evaluate patient satisfaction with the Advanced Bionics Neptune™ waterproof sound processor used with the AquaMic™ totally submersible microphone. Subjective satisfaction with the different Neptune™ wearing options, comfort, ease of use, sound quality and use of the processor in a range of active and water related situations were assessed for 23 adults and 73 children, using an online and paper based questionnaire. Upgraded subjects compared their previous processor to the Neptune™. The Neptune™ was most popular for use in general sports and in the pool. Subjects were satisfied with the sound quality of the sound processor outside and under water and following submersion. Seventyeight percent of subjects rated waterproofness as being very useful and 83% of the newly implanted subjects selected waterproofness as one of the reasons why they chose the Neptune™ processor. Providing a waterproof sound processor is considered by cochlear implant recipients to be useful and important and is a factor in their processor choice. Subjects reported that they were satisfied with the Neptune™ sound quality, ease of use and different wearing options.

  8. Real time data acquisition for a time projection chamber using a high speed DEC-RT11 to UNIX UDP-TCP/IP interface

    International Nuclear Information System (INIS)

    Thomas, J.; Douglas, M.; Watanabe, R.; Henrikson, H.E.; Iqbal, M.Z.; Mitchell, L.W.; O'Callaghan, B.M.G.; Wong, H.T.K.; Melvin, J.D.

    1987-01-01

    The authors built a high pressure xenon Time Projection Chamber to study double beta decay, a process of fundamental interest which, if observed, would indicate that the neutrino is a massive Majorana particle. Raw data rates from the TPC exceed 200 Kbytes per second. The TPC is operated through a CAMAC interface with a DEC LSI-11/73 computer networked to a Tektronix 6130 workstation. Data is transmitted at about 15 Kbytes per second although the network is capable of transmitting data at 80 Kbytes per second. The only system level programming required was to write a UDP-TCP/IP driver for the DEC-DEQNA Ethenet board on the 11/73

  9. A word processor optimized for preparing journal articles and student papers.

    Science.gov (United States)

    Wolach, A H; McHale, M A

    2001-11-01

    A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

  10. Extended performance electric propulsion power processor design study. Volume 2: Technical summary

    Science.gov (United States)

    Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

    1977-01-01

    Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

  11. First Results of an “Artificial Retina” Processor Prototype

    International Nuclear Information System (INIS)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-01-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

  12. Silicon in cereal straw

    DEFF Research Database (Denmark)

    Murozuka, Emiko

    Silicon (Si) is known to be a beneficial element for plants. However, when plant residues are to be used as feedstock for second generation bioenergy, Si may reduce the suitability of the biomass for biochemical or thermal conversion technologies. The objective of this PhD study was to investigate......, a mutant in Si influx transporter BdLsi1 was identified. BdLsi1 belongs to the major intrinsic protein family. The mutant BdLsi1 protein had an amino acid change from proline to serine in the highly conserved NPA motif. The mutation caused a defect in channeling of Si as well as other substrates...... such as germanium and arsenite. The Si concentration in the mutant plant was significantly reduced by more than 80 %. Rice mutants defective in Si transporters OsLsi1 and OsLsi2 also showed significantly lower straw Si concentration. It is concluded that the quality of straw biomass for bioenergy purposes can...

  13. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    Science.gov (United States)

    Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

    2018-02-01

    We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

  14. M7--a high speed digital processor for second level trigger selections

    International Nuclear Information System (INIS)

    Droege, T.F.; Gaines, I.; Turner, K.J.

    1978-01-01

    A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

  15. A fast continuous magnetic field measurement system based on digital signal processors

    International Nuclear Information System (INIS)

    Velev, G.V.; Carcagno, R.; DiMarco, J.; Kotelnikov, S.; Lamm, M.; Makulski, A.; Maroussov, V.; Nehring, R.; Nogiec, J.; Orris, D.; Poukhov, O.; Prakoshyn, F.; Schlabach, P.; Tompkins, J.C.

    2005-01-01

    In order to study dynamic effects in accelerator magnets, such as the decay of the magnetic field during the dwell at injection and the rapid so-called ''snapback'' during the first few seconds of the resumption of the energy ramp, a fast continuous harmonics measurement system was required. A new magnetic field measurement system, based on the use of digital signal processors (DSP) and Analog to Digital (A/D) converters, was developed and prototyped at Fermilab. This system uses Pentek 6102 16 bit A/D converters and the Pentek 4288 DSP board with the SHARC ADSP-2106 family digital signal processor. It was designed to acquire multiple channels of data with a wide dynamic range of input signals, which are typically generated by a rotating coil probe. Data acquisition is performed under a RTOS, whereas processing and visualization are performed under a host computer. Firmware code was developed for the DSP to perform fast continuous readout of the A/D FIFO memory and integration over specified intervals, synchronized to the probe's rotation in the magnetic field. C, C++ and Java code was written to control the data acquisition devices and to process a continuous stream of data. The paper summarizes the characteristics of the system and presents the results of initial tests and measurements

  16. Teaching and Learning Physics in a 1:1 Laptop School

    Science.gov (United States)

    Zucker, Andrew A.; Hug, Sarah T.

    2008-12-01

    1:1 laptop programs, in which every student is provided with a personal computer to use during the school year, permit increased and routine use of powerful, user-friendly computer-based tools. Growing numbers of 1:1 programs are reshaping the roles of teachers and learners in science classrooms. At the Denver School of Science and Technology, a public charter high school where a large percentage of students come from low-income families, 1:1 laptops are used often by teachers and students. This article describes the school's use of laptops, the Internet, and related digital tools, especially for teaching and learning physics. The data are from teacher and student surveys, interviews, classroom observations, and document analyses. Physics students and teachers use an interactive digital textbook; Internet-based simulations (some developed by a Nobel Prize winner); word processors; digital drop boxes; email; formative electronic assessments; computer-based and stand-alone graphing calculators; probes and associated software; and digital video cameras to explore hypotheses, collaborate, engage in scientific inquiry, and to identify strengths and weaknesses of students' understanding of physics. Technology provides students at DSST with high-quality tools to explore scientific concepts and the experiences of teachers and students illustrate effective uses of digital technology for high school physics.

  17. Functional phosphodiesterase 11A mutations may modify the risk of familial and bilateral testicular germ cell tumors

    Science.gov (United States)

    Horvath, Anelia; Korde, Larissa; Greene, Mark H.; Libe, Rosella; Osorio, Paulo; Faucz, Fabio Rueda; Raffin-Sanson, Marie Laure; Tsang, Kit Man; Drori-Herishanu, Limor; Patronas, Yianna; Remmers, Elaine F; Nikita, Maria-Elena; Moran, Jason; Greene, Joseph; Nesterova, Maria; Merino, Maria; Bertherat, Jerome; Stratakis, Constantine A.

    2009-01-01

    Inactivating germline mutations in phosphodiesterase 11A (PDE11A) have been implicated in adrenal tumor susceptibility. PDE11A is highly-expressed in endocrine steroidogenic tissues, especially the testis, and mice with inactivated Pde11a exhibit male infertility, a known testicular germ cell tumor (TGCT) risk factor. We sequenced the PDE11A gene-coding region in 95 patients with TGCT from 64 unrelated kindreds. We identified 8 non-synonymous substitutions in 20 patients from 15 families: four (R52T; F258Y; G291R; V820M) were newly-recognized, three (R804H; R867G; M878V) were functional variants previously implicated in adrenal tumor predisposition, and one (Y727C) was a known polymorphism. We compared the frequency of these variants in our patients to unrelated controls that had been screened and found negative for any endocrine diseases: only the two previously-reported variants, R804H and R867G, known to be frequent in general population, were detected in these controls. The frequency of all PDE11A-gene variants (combined) was significantly higher among patients with TGCT (P=0.0002), present in 19% of the families of our cohort. Most variants were detected in the general population, but functional studies showed that all these mutations reduced PDE activity, and that PDE11A protein expression was decreased (or absent) in TGCT samples from carriers. This is the first demonstration of a PDE gene’s involvement in TGCT, although the cAMP signaling pathway has been investigated extensively in other reproductive organs and their diseases. In conclusion, we report that PDE11A-inactivating sequence variants may modify the risk of familial and bilateral TGCT. PMID:19549888

  18. Discussion paper for a highly parallel array processor-based machine

    International Nuclear Information System (INIS)

    Hagstrom, R.; Bolotin, G.; Dawson, J.

    1984-01-01

    The architectural plant for a quickly realizable implementation of a highly parallel special-purpose computer system with peak performance in the range of 6 billion floating point operations per second is discussed. The architecture is suitable to Lattice Gauge theoretical computations of fundamental physics interest and may be applicable to a range of other problems which deal with numerically intensive computational problems. The plan is quickly realizable because it employs a maximum of commercially available hardware subsystems and because the architecture is software-transparent to the individual processors, allowing straightforward re-use of whatever commercially available operating-systems and support software that is suitable to run on the commercially-produced processors. A tiny prototype instrument, designed along this architecture has already operated. A few elementary examples of programs which can run efficiently are presented. The large machine which the authors would propose to build would be based upon a highly competent array-processor, the ST-100 Array Processor, and specific design possibilities are discussed. The first step toward realizing this plan practically is to install a single ST-100 to allow algorithm development to proceed while a demonstration unit is built using two of the ST-100 Array Processors

  19. SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

    Science.gov (United States)

    Moyer, Ruth A.

    Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

  20. Review of ANSI N13.11: a status report

    International Nuclear Information System (INIS)

    Sims, C.S.

    1988-01-01

    In 1983, the American National Standards Institute (ANSI) issued the dosimetry standard titled Personnel Dosimetry Performance - Criteria for Testing as ANSI N13.11. This standard forms the basis for the National Voluntary Laboratory Accreditation Program (NVLAP) which has become familiar to dosimeter processors in recent years. This standard is particularly important because the Nuclear Regulatory Commission (NRC) requires that all licensees have personnel dosimetry devices processed by processors that are NVLAP accredited. This standard is currently undergoing review and modifications are going to be made. This paper contains a brief history of the events leading to the development of ANSI N13.11-1983, information concerning the present standard and associated performance test results, and the selection of the review group. Following that, the status of the review is presented and statements regarding the future outlook for the standard are made

  1. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Kuppangari Krishna RAO; Fazal NOORBASHA; Ram Asaray SINGH

    2010-01-01

    As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI) benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT) @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalab...

  2. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    Directory of Open Access Journals (Sweden)

    Hristov Ivan

    2018-01-01

    Full Text Available We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP” in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL. The results show 2 times better performance on KNL processor.

  3. HTGR core seismic analysis using an array processor

    International Nuclear Information System (INIS)

    Shatoff, H.; Charman, C.M.

    1983-01-01

    A Floating Point Systems array processor performs nonlinear dynamic analysis of the high-temperature gas-cooled reactor (HTGR) core with significant time and cost savings. The graphite HTGR core consists of approximately 8000 blocks of various shapes which are subject to motion and impact during a seismic event. Two-dimensional computer programs (CRUNCH2D, MCOCO) can perform explicit step-by-step dynamic analyses of up to 600 blocks for time-history motions. However, use of two-dimensional codes was limited by the large cost and run times required. Three-dimensional analysis of the entire core, or even a large part of it, had been considered totally impractical. Because of the needs of the HTGR core seismic program, a Floating Point Systems array processor was used to enhance computer performance of the two-dimensional core seismic computer programs, MCOCO and CRUNCH2D. This effort began by converting the computational algorithms used in the codes to a form which takes maximum advantage of the parallel and pipeline processors offered by the architecture of the Floating Point Systems array processor. The subsequent conversion of the vectorized FORTRAN coding to the array processor required a significant programming effort to make the system work on the General Atomic (GA) UNIVAC 1100/82 host. These efforts were quite rewarding, however, since the cost of running the codes has been reduced approximately 50-fold and the time threefold. The core seismic analysis with large two-dimensional models has now become routine and extension to three-dimensional analysis is feasible. These codes simulate the one-fifth-scale full-array HTGR core model. This paper compares the analysis with the test results for sine-sweep motion

  4. A single chip pulse processor for nuclear spectroscopy

    International Nuclear Information System (INIS)

    Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

    1985-01-01

    A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

  5. The hardware track finder processor in CMS at CERN

    CERN Document Server

    Kluge, A

    1997-01-01

    The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

  6. UA1 upgrade first-level calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

    1989-01-01

    A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

  7. Application of the Computer Capacity to the Analysis of Processors Evolution

    OpenAIRE

    Ryabko, Boris; Rakitskiy, Anton

    2017-01-01

    The notion of computer capacity was proposed in 2012, and this quantity has been estimated for computers of different kinds. In this paper we show that, when designing new processors, the manufacturers change the parameters that affect the computer capacity. This allows us to predict the values of parameters of future processors. As the main example we use Intel processors, due to the accessibility of detailed description of all their technical characteristics.

  8. Optimal processor for malfunction detection in operating nuclear reactor

    International Nuclear Information System (INIS)

    Ciftcioglu, O.

    1990-01-01

    An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

  9. An updated program-controlled analog processor, model AP-006, for semiconductor detector spectrometers

    International Nuclear Information System (INIS)

    Shkola, N.F.; Shevchenko, Yu.A.

    1989-01-01

    An analog processor, model AP-006, is reported. The processor is a development of a series of spectrometric units based on a shaper of the type 'DL dif +TVS+gated ideal integrator'. Structural and circuits design features are described. The results of testing the processor in a setup with a Si(Li) detecting unit over an input count-rate range of up to 5x10 5 cps are presented. Processor applications are illustrated. (orig.)

  10. Case Study of Using High Performance Commercial Processors in a Space Environment

    Science.gov (United States)

    Ferguson, Roscoe C.; Olivas, Zulema

    2009-01-01

    The purpose of the Space Shuttle Cockpit Avionics Upgrade project was to reduce crew workload and improve situational awareness. The upgrade was to augment the Shuttle avionics system with new hardware and software. A major success of this project was the validation of the hardware architecture and software design. This was significant because the project incorporated new technology and approaches for the development of human rated space software. An early version of this system was tested at the Johnson Space Center for one month by teams of astronauts. The results were positive, but NASA eventually cancelled the project towards the end of the development cycle. The goal to reduce crew workload and improve situational awareness resulted in the need for high performance Central Processing Units (CPUs). The choice of CPU selected was the PowerPC family, which is a reduced instruction set computer (RISC) known for its high performance. However, the requirement for radiation tolerance resulted in the reevaluation of the selected family member of the PowerPC line. Radiation testing revealed that the original selected processor (PowerPC 7400) was too soft to meet mission objectives and an effort was established to perform trade studies and performance testing to determine a feasible candidate. At that time, the PowerPC RAD750s where radiation tolerant, but did not meet the required performance needs of the project. Thus, the final solution was to select the PowerPC 7455. This processor did not have a radiation tolerant version, but faired better than the 7400 in the ability to detect failures. However, its cache tags did not provide parity and thus the project incorporated a software strategy to detect radiation failures. The strategy was to incorporate dual paths for software generating commands to the legacy Space Shuttle avionics to prevent failures due to the softness of the upgraded avionics.

  11. 40 CFR 80.840 - What requirements apply to transmix processors?

    Science.gov (United States)

    2010-07-01

    ... PROGRAMS (CONTINUED) REGULATION OF FUELS AND FUEL ADDITIVES Gasoline Toxics Gasoline Toxics Performance Requirements § 80.840 What requirements apply to transmix processors? Any transmix processor who produces gasoline or gasoline blendstock from transmix, or recovers gasoline or gasoline blendstock from transmix...

  12. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  13. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  14. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  15. Safe and Efficient Support for Embeded Multi-Processors in ADA

    Science.gov (United States)

    Ruiz, Jose F.

    2010-08-01

    New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

  16. A programmable systolic trigger processor for FERA bus data

    International Nuclear Information System (INIS)

    Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

    1992-09-01

    A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

  17. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

  18. Performance of Artificial Intelligence Workloads on the Intel Core 2 Duo Series Desktop Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2010-12-01

    Full Text Available As the processor architecture becomes more advanced, Intel introduced its Intel Core 2 Duo series processors. Performance impact on Intel Core 2 Duo processors are analyzed using SPEC CPU INT 2006 performance numbers. This paper studied the behavior of Artificial Intelligence (AI benchmarks on Intel Core 2 Duo series processors. Moreover, we estimated the task completion time (TCT @1 GHz, @2 GHz and @3 GHz Intel Core 2 Duo series processors frequency. Our results show the performance scalability in Intel Core 2 Duo series processors. Even though AI benchmarks have similar execution time, they have dissimilar characteristics which are identified using principal component analysis and dendogram. As the processor frequency increased from 1.8 GHz to 3.167 GHz the execution time is decreased by ~370 sec for AI workloads. In the case of Physics/Quantum Computing programs it was ~940 sec.

  19. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  20. Slowdown in the $M/M/1$ discriminatory processor-sharing queue

    NARCIS (Netherlands)

    Cheung, S.K.; Kim, Bara; Kim, Jeongsim

    2008-01-01

    We consider a queue with multiple K job classes, Poisson arrivals, and exponentially distributed required service times in which a single processor serves according to the discriminatory processor-sharing (DPS) discipline. For this queue, we obtain the first and second moments of the slowdown, which

  1. Online Fastbus processor for LEP

    International Nuclear Information System (INIS)

    Mueller, H.

    1986-01-01

    The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

  2. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  3. A Modular Pipelined Processor for High Resolution Gamma-Ray Spectroscopy

    Science.gov (United States)

    Veiga, Alejandro; Grunfeld, Christian

    2016-02-01

    The design of a digital signal processor for gamma-ray applications is presented in which a single ADC input can simultaneously provide temporal and energy characterization of gamma radiation for a wide range of applications. Applying pipelining techniques, the processor is able to manage and synchronize very large volumes of streamed real-time data. Its modular user interface provides a flexible environment for experimental design. The processor can fit in a medium-sized FPGA device operating at ADC sampling frequency, providing an efficient solution for multi-channel applications. Two experiments are presented in order to characterize its temporal and energy resolution.

  4. A survey of Tumult, a real-time multi-processor system

    International Nuclear Information System (INIS)

    Jansen, P.G.

    1986-01-01

    Tumult (Twente University MULTi processor system) is the name of an ongoing project aiming at the design and implementation of a modular extendible multiprocessor system. All memory is distributed and processors communicate in parallel via a fast and reliable local switching network instead of a shared bus. A distributed real-time operating system is being designed and implemented, consisting of a multi-tasking subsystem per processor. Processes can communicate via a message passing mechanism. Communication links and processes are dynamically created and disposed by the application. In this article a brief description of the system is given; communication aspects are emphasized. (Auth.)

  5. Reaction-diffusion path planning in a hybrid chemical and cellular-automaton processor

    International Nuclear Information System (INIS)

    Adamatzky, Andrew; Lacy Costello, Benjamin de

    2003-01-01

    To find the shortest collision-free path in a room containing obstacles we designed a chemical processor and coupled it with a cellular-automaton processor. In the chemical processor obstacles are represented by sites of high concentration of potassium iodide and a planar substrate is saturated with palladium chloride. Potassium iodide diffuses into the substrate and reacts with palladium chloride. A dark coloured precipitate of palladium iodide is formed almost everywhere except sites where two or more diffusion wavefronts collide. The less coloured sites are situated at the furthest distance from obstacles. Thus, the chemical processor develops a repulsive field, generated by obstacles. A snapshot of the chemical processor is inputted to a cellular automaton. The automaton behaves like a discrete excitable media; also, every cell of the automaton is supplied with a pointer that shows an origin of the cell's excitation. The excitation spreads along the cells corresponding to precipitate depleted sites of the chemical processor. When the destination-site is excited, waves travel on the lattice and update the orientations of the pointers. Thus, the automaton constructs a spanning tree, made of pointers, that guides a traveler towards the destination point. Thus, the automaton medium generates an attractive field and combination of this attractive field with the repulsive field, generated by the chemical processor, provides us with a solution of the collision-free path problem

  6. Reducing Competitive Cache Misses in Modern Processor Architectures

    OpenAIRE

    Prisagjanec, Milcho; Mitrevski, Pece

    2017-01-01

    The increasing number of threads inside the cores of a multicore processor, and competitive access to the shared cache memory, become the main reasons for an increased number of competitive cache misses and performance decline. Inevitably, the development of modern processor architectures leads to an increased number of cache misses. In this paper, we make an attempt to implement a technique for decreasing the number of competitive cache misses in the first level of cache memory. This tec...

  7. 16-Bit RISC Processor Design for Convolution Application

    OpenAIRE

    Anand Nandakumar Shardul

    2013-01-01

    In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

  8. X-ray properties of the Be/X-ray systems 2S0114+650 LSI+65 deg 010

    International Nuclear Information System (INIS)

    Koenigsberger, G.; Swank, J.H.; Szymkowiak, A.E.

    1982-12-01

    Results are presented from experiments on the Einstein Observatory, HEAO-1 and OSO-8 on the temporal and spectral properties of 2S0114+650. In a 12 hour Einstein MPC and SSS observation two episodes of flaring occurred by an order of magnitude over about 1 hour. Variability on shorter time scales showed a preferred period of 14.9 minutes, but periodic pulsations were not seen in the HEAO-1 and OSO-8 data. There is some evidence that the spectrum is steeper when the source is quiescent at low luminosity, but no large spectral changes attended the flares. Absorption column densities were consistent with interstellar reddening of the proposed companion, the Be star LSI+65 deg 010. In the minute and hour variability and in the spectral character, 2S0114+650 is similar to other Be star-neutron star binary X-ray sources. Variations over several days in the OSO-8 data suggest orbital effects

  9. Modal Processor Effects Inspired by Hammond Tonewheel Organs

    Directory of Open Access Journals (Sweden)

    Kurt James Werner

    2016-06-01

    Full Text Available In this design study, we introduce a novel class of digital audio effects that extend the recently introduced modal processor approach to artificial reverberation and effects processing. These pitch and distortion processing effects mimic the design and sonics of a classic additive-synthesis-based electromechanical musical instrument, the Hammond tonewheel organ. As a reverb effect, the modal processor simulates a room response as the sum of resonant filter responses. This architecture provides precise, interactive control over the frequency, damping, and complex amplitude of each mode. Into this framework, we introduce two types of processing effects: pitch effects inspired by the Hammond organ’s equal tempered “tonewheels”, “drawbar” tone controls, vibrato/chorus circuit, and distortion effects inspired by the pseudo-sinusoidal shape of its tonewheels and electromagnetic pickup distortion. The result is an effects processor that imprints the Hammond organ’s sonics onto any audio input.

  10. Safety-critical Java on a time-predictable processor

    DEFF Research Database (Denmark)

    Korsholm, Stephan E.; Schoeberl, Martin; Puffitsch, Wolfgang

    2015-01-01

    For real-time systems the whole execution stack needs to be time-predictable and analyzable for the worst-case execution time (WCET). This paper presents a time-predictable platform for safety-critical Java. The platform consists of (1) the Patmos processor, which is a time-predictable processor......; (2) a C compiler for Patmos with support for WCET analysis; (3) the HVM, which is a Java-to-C compiler; (4) the HVM-SCJ implementation which supports SCJ Level 0, 1, and 2 (for both single and multicore platforms); and (5) a WCET analysis tool. We show that real-time Java programs translated to C...... and compiled to a Patmos binary can be analyzed by the AbsInt aiT WCET analysis tool. To the best of our knowledge the presented system is the second WCET analyzable real-time Java system; and the first one on top of a RISC processor....

  11. Stepping motor control processor reference manual. Volume I

    International Nuclear Information System (INIS)

    Holloway, F.W.; VanArsdall, P.J.; Suski, G.J.; Gant, R.G.; Rash, M.

    1980-01-01

    This manual is intended to serve several purposes. The first goal is to describe the capabilities and operation of the SMC processor package from an operator or user point of view. Secondly, the manual will describe in some detail the basic hardware elements and how they can be used effectively to implement a step motor control system. Practical information on the use, installation and checkout of the hardware set is presented in the following sections along with programming suggestions. Available related system software is described in this manual for reference and as an aid in understanding the system architecture. Section two presents an overview and operations manual of the SMC processor describing its composition and functional capabilities. Section three contains hardware descriptions in some detail for the LLL-designed hardware used in the SMC processor. Basic theory of operation and important features are explained

  12. The Interface Between Redundant Processor Modules Of Safety Grade PLC Using Mass Storage DPRAM

    International Nuclear Information System (INIS)

    Hwang, Sung Jae; Song, Seong Hwan; No, Young Hun; Yun, Dong Hwa; Park, Gang Min; Kim, Min Gyu; Choi, Kyung Chul; Lee, Ui Taek

    2010-01-01

    Processor module of safety grade PLC (hereinafter called as POSAFE-Q) developed by POSCO ICT provides high reliability and safety. However, POSAFEQ would have suffered a malfunction when we think taking place of abnormal operation by exceptional environmental. POSAFE-Q would not able to conduct its function normally in such case. To prevent these situations, the necessity of redundant processor module has been raised. Therefore, redundant processor module, NCPU-2Q, has been developed which has not only functions of single processor module with high reliability and safety but also functions of redundant processor

  13. The performances of coffee processors and coffee market in the Republic of Serbia

    Directory of Open Access Journals (Sweden)

    Nuševa Daniela

    2017-01-01

    Full Text Available The main aim of this paper is to investigate the performances of coffee processors and coffee market in Serbia based on the market concentration analysis, profitability analysis, and profitability determinants analysis. The research was based on the sample of 40 observations of coffee processing companies divided into two groups: large and small coffee processors. The results indicate that two large coffee processors have dominant market share. Even though the Serbian coffee market is an oligopolistic, profitability analysis indicates that small coffee processors have a significant better profitability ratio than large coffee processors. Furthermore, results show that profitability ratio is positively related to the inventory turnover and negatively related to the market share.

  14. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

    2011-01-01

    Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi......Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper...

  15. The microelectronic and photonic test bed RISC processor and DRAM memory stack experiments

    International Nuclear Information System (INIS)

    Clark, K.A.; Meehan, T.J.

    1999-01-01

    This paper reports on the on-orbit data obtained from the MPTB RISC Processor Experiment, containing three Integrated Device Technologies R3081 processors. During operations, nine SEUs were observed in the processors, and four SEUs were observed in the memory and/or support circuitry. (authors)

  16. Digital image processing software system using an array processor

    International Nuclear Information System (INIS)

    Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.

    1981-01-01

    A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

  17. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  18. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2016-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  19. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  20. Scientific programming on massively parallel processor CP-PACS

    International Nuclear Information System (INIS)

    Boku, Taisuke

    1998-01-01

    The massively parallel processor CP-PACS takes various problems of calculation physics as the object, and it has been designed so that its architecture has been devised to do various numerical processings. In this report, the outline of the CP-PACS and the example of programming in the Kernel CG benchmark in NAS Parallel Benchmarks, version 1, are shown, and the pseudo vector processing mechanism and the parallel processing tuning of scientific and technical computation utilizing the three-dimensional hyper crossbar net, which are two great features of the architecture of the CP-PACS are described. As for the CP-PACS, the PUs based on RISC processor and added with pseudo vector processor are used. Pseudo vector processing is realized as the loop processing by scalar command. The features of the connection net of PUs are explained. The algorithm of the NPB version 1 Kernel CG is shown. The part that takes the time for processing most in the main loop is the product of matrix and vector (matvec), and the parallel processing of the matvec is explained. The time for the computation by the CPU is determined. As the evaluation of the performance, the evaluation of the time for execution, the short vector processing of pseudo vector processor based on slide window, and the comparison with other parallel computers are reported. (K.I.)

  1. Investigation of Large Scale Cortical Models on Clustered Multi-Core Processors

    Science.gov (United States)

    2013-02-01

    Playstation 3 with 6 available SPU cores outperforms the Intel Xeon processor (with 4 cores) by about 1.9 times for the HTM model and by 2.4 times...runtime breakdowns of the HTM and Dean models respectively on the Cell processor (on the Playstation 3) and the Intel Xeon processor ( 4 thread...YOUR FORM TO THE ABOVE ORGANIZATION. 1. REPORT DATE (DD-MM-YYYY) 2. REPORT TYPE 3. DATES COVERED (From - To) 4 . TITLE AND SUBTITLE 5a. CONTRACT NUMBER

  2. Automation of ORIGEN2 calculations for the transuranic waste baseline inventory database using a pre-processor and a post-processor

    International Nuclear Information System (INIS)

    Liscum-Powell, J.

    1997-06-01

    The purpose of the work described in this report was to automate ORIGEN2 calculations for the Waste Isolation Pilot Plant (WIPP) Transuranic Waste Baseline Inventory Database (WTWBID); this was done by developing a pre-processor to generate ORIGEN2 input files from WWBID inventory files and a post-processor to remove excess information from the ORIGEN2 output files. The calculations performed with ORIGEN2 estimate the radioactive decay and buildup of various radionuclides in the waste streams identified in the WTWBID. The resulting radionuclide inventories are needed for performance assessment calculations for the WIPP site. The work resulted in the development of PreORG, which requires interaction with the user to generate ORIGEN2 input files on a site-by-site basis, and PostORG, which processes ORIGEN2 output into more manageable files. Both programs are written in the FORTRAN 77 computer language. After running PreORG, the user will run ORIGEN2 to generate the desired data; upon completion of ORIGEN2 calculations, the user can run PostORG to process the output to make it more manageable. All the programs run on a 386 PC or higher with a math co-processor or a computer platform running under VMS operating system. The pre- and post-processors for ORIGEN2 were generated for use with Rev. 1 data of the WTWBID and can also be used with Rev. 2 and 3 data of the TWBID (Transuranic Waste Baseline Inventory Database)

  3. A design of a computer complex including vector processors

    International Nuclear Information System (INIS)

    Asai, Kiyoshi

    1982-12-01

    We, members of the Computing Center, Japan Atomic Energy Research Institute have been engaged for these six years in the research of adaptability of vector processing to large-scale nuclear codes. The research has been done in collaboration with researchers and engineers of JAERI and a computer manufacturer. In this research, forty large-scale nuclear codes were investigated from the viewpoint of vectorization. Among them, twenty-six codes were actually vectorized and executed. As the results of the investigation, it is now estimated that about seventy percents of nuclear codes and seventy percents of our total amount of CPU time of JAERI are highly vectorizable. Based on the data obtained by the investigation, (1)currently vectorizable CPU time, (2)necessary number of vector processors, (3)necessary manpower for vectorization of nuclear codes, (4)computing speed, memory size, number of parallel 1/0 paths, size and speed of 1/0 buffer of vector processor suitable for our applications, (5)necessary software and operational policy for use of vector processors are discussed, and finally (6)a computer complex including vector processors is presented in this report. (author)

  4. Parallel computation for distributed parameter system-from vector processors to Adena computer

    Energy Technology Data Exchange (ETDEWEB)

    Nogi, T

    1983-04-01

    Research on advanced parallel hardware and software architectures for very high-speed computation deserves and needs more support and attention to fulfil its promise. Novel architectures for parallel processing are being made ready. Architectures for parallel processing can be roughly divided into two groups. One is a vector processor in which a single central processing unit involves multiple vector-arithmetic registers. The other is a processor array in which slave processors are connected to a host processor to perform parallel computation. In this review, the concept and data structure of the Adena (alternating-direction edition nexus array) architecture, which is conformable to distributed-parameter simulation algorithms, are described. 5 references.

  5. Digital control card based on digital signal processor

    International Nuclear Information System (INIS)

    Hou Shigang; Yin Zhiguo; Xia Le

    2008-01-01

    A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

  6. Solute carrier protein family 11 member 1 (Slc11a1) activation efficiently inhibits Leishmania donovani survival in host macrophages.

    Science.gov (United States)

    Singh, Nisha; Gedda, Mallikarjuna Rao; Tiwari, Neeraj; Singh, Suya P; Bajpai, Surabhi; Singh, Rakesh K

    2017-09-01

    Visceral leishmaniasis (kala-azar), a life threatening disease caused by L. donovani , is a latent threat to more than 147 million people living in disease endemic South East Asia region of the Indian subcontinent. The therapeutic option to control leishmanial infections are very limited, and at present comprise only two drugs, an antifungal amphotericin B and an antitumor miltefosine, which are also highly vulnerable for parasitic resistance. Therefore, identification and development of alternate control measures is an exigent requirement to control leishmanial infections. In this study, we report that functionally induced expression of solute carrier protein family 11 member 1 ( Slc11a1), a transmembrane divalent cationic transporter recruited on the surface of phagolysosomes after phagocytosis of parasites, effectively inhibits Leishmania donovani growth in host macrophages. Further, the increased Slc11a1 functionality also resulted in increased production of NOx, TNF-α and IL-12 by activated macrophages. The findings of this study signify the importance of interplay between Slc11a1 expression and macrophages activation that can be effectively used to control of Leishmania growth and survival.

  7. Treecode with a Special-Purpose Processor

    Science.gov (United States)

    Makino, Junichiro

    1991-08-01

    We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

  8. Token-Aware Completion Functions for Elastic Processor Verification

    Directory of Open Access Journals (Sweden)

    Sudarshan K. Srinivasan

    2009-01-01

    Full Text Available We develop a formal verification procedure to check that elastic pipelined processor designs correctly implement their instruction set architecture (ISA specifications. The notion of correctness we use is based on refinement. Refinement proofs are based on refinement maps, which—in the context of this problem—are functions that map elastic processor states to states of the ISA specification model. Data flow in elastic architectures is complicated by the insertion of any number of buffers in any place in the design, making it hard to construct refinement maps for elastic systems in a systematic manner. We introduce token-aware completion functions, which incorporate a mechanism to track the flow of data in elastic pipelines, as a highly automated and systematic approach to construct refinement maps. We demonstrate the efficiency of the overall verification procedure based on token-aware completion functions using six elastic pipelined processor models based on the DLX architecture.

  9. A light hydrocarbon fuel processor producing high-purity hydrogen

    Science.gov (United States)

    Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

    This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

  10. Soft-core dataflow processor architecture optimised for radar signal processing: Article

    CSIR Research Space (South Africa)

    Broich, R

    2014-10-01

    Full Text Available Current radar signal processors lack either performance or flexibility. Custom soft-core processors exhibit potential in high-performance signal processing applications, yet remain relatively unexplored in research literature. In this paper, we use...

  11. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  12. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  13. Demonstration of two-qubit algorithms with a superconducting quantum processor.

    Science.gov (United States)

    DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

    2009-07-09

    Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

  14. Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

    2010-01-01

    The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

  15. OLYMPUS system and development of its pre-processor

    International Nuclear Information System (INIS)

    Okamoto, Masao; Takeda, Tatsuoki; Tanaka, Masatoshi; Asai, Kiyoshi; Nakano, Koh.

    1977-08-01

    The OLYMPUS SYSTEM developed by K. V. Roverts et al. was converted and introduced in computer system FACOM 230/75 of the JAERI Computing Center. A pre-processor was also developed for the OLYMPUS SYSTEM. The OLYMPUS SYSTEM is very useful for development, standardization and exchange of programs in thermonuclear fusion research and plasma physics. The pre-processor developed by the present authors is not only essential for the JAERI OLYMPUS SYSTEM, but also useful in manipulation, creation and correction of program files. (auth.)

  16. A fast processor for di-lepton triggers

    CERN Document Server

    Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

    1981-01-01

    As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

  17. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  18. A fast continuous magnetic field measurement system based on digital signal processors

    Energy Technology Data Exchange (ETDEWEB)

    Velev, G.V.; Carcagno, R.; DiMarco, J.; Kotelnikov, S.; Lamm, M.; Makulski, A.; /Fermilab; Maroussov, V.; /Purdue U.; Nehring, R.; Nogiec, J.; Orris, D.; /Fermilab; Poukhov,; Prakoshyn, F.; /Dubna, JINR; Schlabach, P.; Tompkins, J.C.; /Fermilab

    2005-09-01

    In order to study dynamic effects in accelerator magnets, such as the decay of the magnetic field during the dwell at injection and the rapid so-called ''snapback'' during the first few seconds of the resumption of the energy ramp, a fast continuous harmonics measurement system was required. A new magnetic field measurement system, based on the use of digital signal processors (DSP) and Analog to Digital (A/D) converters, was developed and prototyped at Fermilab. This system uses Pentek 6102 16 bit A/D converters and the Pentek 4288 DSP board with the SHARC ADSP-2106 family digital signal processor. It was designed to acquire multiple channels of data with a wide dynamic range of input signals, which are typically generated by a rotating coil probe. Data acquisition is performed under a RTOS, whereas processing and visualization are performed under a host computer. Firmware code was developed for the DSP to perform fast continuous readout of the A/D FIFO memory and integration over specified intervals, synchronized to the probe's rotation in the magnetic field. C, C++ and Java code was written to control the data acquisition devices and to process a continuous stream of data. The paper summarizes the characteristics of the system and presents the results of initial tests and measurements.

  19. Positive selection in the SLC11A1 gene in the family Equidae

    DEFF Research Database (Denmark)

    Bayerova, Zuzana; Janova, Eva; Matiasovic, Jan

    2016-01-01

    Immunity-related genes are a suitable model for studying effects of selection at the genomic level. Some of them are highly conserved due to functional constraints and purifying selection, while others are variable and change quickly to cope with the variation of pathogens. The SLC11A1 gene encodes...... a transporter protein mediating antimicrobial activity of macrophages. Little is known about the patterns of selection shaping this gene during evolution. Although it is a typical evolutionarily conserved gene, functionally important polymorphisms associated with various diseases were identified in humans...... and other species. We analyzed the genomic organization, genetic variation, and evolution of the SLC11A1 gene in the family Equidae to identify patterns of selection within this important gene. Nucleotide SLC11A1 sequences were shown to be highly conserved in ten equid species, with more than 97 % sequence...

  20. Mongoose: Creation of a Rad-Hard MIPS R3000

    Science.gov (United States)

    Lincoln, Dan; Smith, Brian

    1993-01-01

    This paper describes the development of a 32 Bit, full MIPS R3000 code-compatible Rad-Hard CPU, code named Mongoose. Mongoose progressed from contract award, through the design cycle, to operational silicon in 12 months to meet a space mission for NASA. The goal was the creation of a fully static device capable of operation to the maximum Mil-883 derated speed, worst-case post-rad exposure with full operational integrity. This included consideration of features for functional enhancements relating to mission compatibility and removal of commercial practices not supported by Rad-Hard technology. 'Mongoose' developed from an evolution of LSI Logic's MIPS-I embedded processor, LR33000, code named Cobra, to its Rad-Hard 'equivalent', Mongoose. The term 'equivalent' is used to infer that the core of the processor is functionally identical, allowing the same use and optimizations of the MIPS-I Instruction Set software tool suite for compilation, software program trace, etc. This activity was started in September of 1991 under a contract from NASA-Goddard Space Flight Center (GSFC)-Flight Data Systems. The approach affected a teaming of NASA-GSFC for program development, LSI Logic for system and ASIC design coupled with the Rad-Hard process technology, and Harris (GASD) for Rad-Hard microprocessor design expertise. The program culminated with the generation of Rad-Hard Mongoose prototypes one year later.

  1. Bulk-memory processor for data acquisition

    International Nuclear Information System (INIS)

    Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

    1981-01-01

    To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

  2. RISC Processors and High Performance Computing

    Science.gov (United States)

    Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

    1995-01-01

    This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

  3. Reduced power processor requirements for the 30-cm diameter HG ion thruster

    Science.gov (United States)

    Rawlin, V. K.

    1979-01-01

    The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

  4. A Family with Mental Retardation, Epilepsy and Cerebellar Hypoplasia Showing Linkage to Chromosome 20p11.21-q11.23

    Directory of Open Access Journals (Sweden)

    Fatih Bayrakli

    2014-01-01

    Full Text Available Background: Cerebellar hypoplasia (CH is a rare malformation caused by various etiologies, usually manifesting clinically as nonprogressive cerebellar ataxia with or without mental retardation. The molecular pathogenesis of the autosomal recessive cerebellar ataxias has a wide range of mechanisms. Differential diagnosis and categorization of the recessive cerebellar ataxias, however, need more specific, biochemical and genetic investigation. Methods: This study applied whole-genome linkage analysis to study a family with nonprogressive cerebellar ataxia and additional mental retardation, epilepsy, and facial dysmorphic features. Genotyping and linkage analysis was done using the GeneChip Mapping 250K NspI Array (Affymetrix Inc., Santa Clara, Calif., USA for genome-wide linkage analysis of the genotyping data from the affected children and their parents. Results: Allegro software version 1.2 was used for multipoint linkage analysis. We assumed an autosomal recessive inheritance pattern and assigned a penetrance of 0.999. Single-nucleotide polymorphism allele frequencies were estimated from the Affymetrix data of the Caucasian family studied. Using these parameters, a theoretical maximum logarithm of the odds score of 2.69 was identified at chromosome 20p11.21-q11.23. Conclusions: This chromosomal locus is unprecedented in autosomal recessive and nonprogressive ataxia disorder. Further investigation might reveal a new causative gene generating the CH phenotype.

  5. Sensitometric Control of Automatic Processors in a Hospital Center : Retrospective Study

    International Nuclear Information System (INIS)

    Lobato Busto, R.; Pombar Camean, M.

    1992-01-01

    This paper analyses the results obtained between February (1990) and July (1991) of the sensitometric control of the seven automatic processors which are in Hospital General de Galicia-Clinico Universitario (Santiago de Compostela). The deviations with regard to the reference values of each processor, permitting the precocious detection of disturbances before being revealed by the image, were analysed. In this analysis, it was achieved that the days in which the automatic processors were out of standing only varied between 2.3% and 5% from the checked days. (author)

  6. Rational calculation accuracy in acousto-optical matrix-vector processor

    Science.gov (United States)

    Oparin, V. V.; Tigin, Dmitry V.

    1994-01-01

    The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

  7. Post-silicon and runtime verification for modern processors

    CERN Document Server

    Wagner, Ilya

    2010-01-01

    The purpose of this book is to survey the state of the art and evolving directions in post-silicon and runtime verification. The authors start by giving an overview of the state of the art in verification, particularly current post-silicon methodologies in use in the industry, both for the domain of processor pipeline design and for memory subsystems. They then dive into the presentation of several new post-silicon verification solutions aimed at boosting the verification coverage of modern processors, dedicating several chapters to this topic. The presentation of runtime verification solution

  8. Ring-array processor distribution topology for optical interconnects

    Science.gov (United States)

    Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

    1992-01-01

    The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

  9. Reconfigurable lattice mesh designs for programmable photonic processors.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

    2016-05-30

    We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

  10. Interactive high-resolution isosurface ray casting on multicore processors.

    Science.gov (United States)

    Wang, Qin; JaJa, Joseph

    2008-01-01

    We present a new method for the interactive rendering of isosurfaces using ray casting on multi-core processors. This method consists of a combination of an object-order traversal that coarsely identifies possible candidate 3D data blocks for each small set of contiguous pixels, and an isosurface ray casting strategy tailored for the resulting limited-size lists of candidate 3D data blocks. While static screen partitioning is widely used in the literature, our scheme performs dynamic allocation of groups of ray casting tasks to ensure almost equal loads among the different threads running on multi-cores while maintaining spatial locality. We also make careful use of memory management environment commonly present in multi-core processors. We test our system on a two-processor Clovertown platform, each consisting of a Quad-Core 1.86-GHz Intel Xeon Processor, for a number of widely different benchmarks. The detailed experimental results show that our system is efficient and scalable, and achieves high cache performance and excellent load balancing, resulting in an overall performance that is superior to any of the previous algorithms. In fact, we achieve an interactive isosurface rendering on a 1024(2) screen for all the datasets tested up to the maximum size of the main memory of our platform.

  11. 77 FR 124 - Biological Processors of Alabama; Decatur, Morgan County, AL; Notice of Settlement

    Science.gov (United States)

    2012-01-03

    ... ENVIRONMENTAL PROTECTION AGENCY [FRL-9612-9] Biological Processors of Alabama; Decatur, Morgan... reimbursement of past response costs concerning the Biological Processors of Alabama Superfund Site located in... Ms. Paula V. Painter. Submit your comments by Site name Biological Processors of Alabama Superfund...

  12. The GASSIPLEX0.7-2 Integrated Front-End Analog Processor for the HMPID and Muon Tracker of ALICE

    CERN Document Server

    Santiard, Jean-Claude

    1999-01-01

    The most recent member of the Gasplex family has been designed in a 0.7 µm n-well CMOS process to meet specifications for the ALICE applications: 500 fC linear dynamic range and a peaking time of 1.2 µs. Its internal circuitry is optimized for the readout of gaseous detectors. A dedicated filter compensates the long hyperbolic signal tail produced by the slow motion of the ions and allows the shaper to achieve perfect return to the base line after 5 µs. Measurement of fabricated chips showed a noise performance of 530 e- rms at 0 pF external input capacitance and 1.2 µs peaking-time, with a noise slope of 11.2 e- rms/pF. The gain is 3.6 mv/fC over a linear dynamic range of 560 fC.Summary:The Gasplex is a 16-channel low noise signal processor built in a 1.5 µm technology and specially designed for gaseous detectors. Each channel consists of a Charge Sensitive Amplifier (CSA) followed by a filter, a Semi-Gaussian shaper and a Track/Hold circuit. The peaking time acts as a delay allowing an external trigger...

  13. Monte Carlo photon transport on shared memory and distributed memory parallel processors

    International Nuclear Information System (INIS)

    Martin, W.R.; Wan, T.C.; Abdel-Rahman, T.S.; Mudge, T.N.; Miura, K.

    1987-01-01

    Parallelized Monte Carlo algorithms for analyzing photon transport in an inertially confined fusion (ICF) plasma are considered. Algorithms were developed for shared memory (vector and scalar) and distributed memory (scalar) parallel processors. The shared memory algorithm was implemented on the IBM 3090/400, and timing results are presented for dedicated runs with two, three, and four processors. Two alternative distributed memory algorithms (replication and dispatching) were implemented on a hypercube parallel processor (1 through 64 nodes). The replication algorithm yields essentially full efficiency for all cube sizes; with the 64-node configuration, the absolute performance is nearly the same as with the CRAY X-MP. The dispatching algorithm also yields efficiencies above 80% in a large simulation for the 64-processor configuration

  14. Introduction to bit slices and microprogramming

    International Nuclear Information System (INIS)

    Van Dam, A.

    1981-01-01

    Bit-slice logic blocks are fourth-generation LSI components which are natural extensions of traditional mulitplexers, registers, decoders, counters, ALUs, etc. Their functionality is controlled by microprogramming, typically to implement CPUs and peripheral controllers where both speed and easy programmability are required for flexibility, ease of implementation and debugging, etc. Processors built from bit-slice logic give the designer an alternative for approaching the programmibility of traditional fixed-instruction-set microprocessors with a speed closer to that of hardwired random logic. (orig.)

  15. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

  16. User manual Dieka PreProcessor

    NARCIS (Netherlands)

    Valkering, Kasper

    2000-01-01

    This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

  17. Work and Family. Employers' Views. Monograph No. 11.

    Science.gov (United States)

    Wolcott, Ilene

    The increasing number of families in which both partners work has focused attention on the relationship between work and family environments, and the consequences when employers and employees attempt to balance work and family responsibilities. This qualitative study explored whether the connections between family and work life were identified as…

  18. Positive selection in the SLC11A1 gene in the family Equidae.

    Science.gov (United States)

    Bayerova, Zuzana; Janova, Eva; Matiasovic, Jan; Orlando, Ludovic; Horin, Petr

    2016-05-01

    Immunity-related genes are a suitable model for studying effects of selection at the genomic level. Some of them are highly conserved due to functional constraints and purifying selection, while others are variable and change quickly to cope with the variation of pathogens. The SLC11A1 gene encodes a transporter protein mediating antimicrobial activity of macrophages. Little is known about the patterns of selection shaping this gene during evolution. Although it is a typical evolutionarily conserved gene, functionally important polymorphisms associated with various diseases were identified in humans and other species. We analyzed the genomic organization, genetic variation, and evolution of the SLC11A1 gene in the family Equidae to identify patterns of selection within this important gene. Nucleotide SLC11A1 sequences were shown to be highly conserved in ten equid species, with more than 97 % sequence identity across the family. Single nucleotide polymorphisms (SNPs) were found in the coding and noncoding regions of the gene. Seven codon sites were identified to be under strong purifying selection. Codons located in three regions, including the glycosylated extracellular loop, were shown to be under diversifying selection. A 3-bp indel resulting in a deletion of the amino acid 321 in the predicted protein was observed in all horses, while it has been maintained in all other equid species. This codon comprised in an N-glycosylation site was found to be under positive selection. Interspecific variation in the presence of predicted N-glycosylation sites was observed.

  19. Low incidence of germline mutation in BRCA1 Exon 11 among early-onset and familial Filipino breast cancer patients

    International Nuclear Information System (INIS)

    Nato, Alejandro Q. Jr; Deocaris, Custer C.; Sajise, Sheila C.

    2002-01-01

    Breast cancer susceptibility gene, type 1 (BRCA1) has been thought to be responsible for about 45% of families with multiple breast carcinoma cases and for more than 80% of hereditary breast and ovarian cancer (HBOC) families. About 61-75% of the reported distinct alterations that result in truncated protein products have been found in exon 11 which comprises 61% (3427bp) of the coding sequence of BRCA1(5592bp). Protein truncation test (PTT) has become a popular method as an efficient means of screening mutations in a coding sequence that lead to a truncated protein product. In this study, 34 early-onset and/or familial breast cancer (FBC) patients were investigated. Twenty-six patients are early-onset B(o)C cases (diagnosed≤40 years old), 14 of which have familiality of the disease. Among the 8 patients that have been diagnosed above 40 years old, 7 have familial clustering. Through radioactive PTT analysis of the 34 BC cases in a 5-20% denaturing gradient polyacrylamide gel, we found only one mutation in exon 11 having a 29.7 kDa truncated protein product. Our results corroborate the findings of a recently reported study of unselected incident breast cancer cases in the Philippines where the prevalence of BRCA1 mutation is also low. This would, however, be the second documented mutation in BRCA1 exon 11 in a Filipino BC patient since 1998. (author)

  20. An intercomparison of Canadian external dosimetry processors for radiation protection

    International Nuclear Information System (INIS)

    1989-10-01

    The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations

  1. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

  2. Processor farming in two-level analysis of historical bridge

    Science.gov (United States)

    Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

    2017-11-01

    This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

  3. Array processors: an introduction to their architecture, software, and applications in nuclear medicine

    International Nuclear Information System (INIS)

    King, M.A.; Doherty, P.W.; Rosenberg, R.J.; Cool, S.L.

    1983-01-01

    Array processors are ''number crunchers'' that dramatically enhance the processing power of nuclear medicine computer systems for applicatons dealing with the repetitive operations involved in digital image processing of large segments of data. The general architecture and the programming of array processors are introduced, along with some applications of array processors to the reconstruction of emission tomographic images, digital image enhancement, and functional image formation

  4. Software implementation of a high speed interface between a PDP-10 and several PDP-11s

    International Nuclear Information System (INIS)

    De Mesa, N.P. III.

    1975-01-01

    The DMA10 is a high speed link between a PDP-10 and up to eight PDP-11s; specifically, the PDP-10 shares sections of its memory with the PDP-11s. The two segment concept on the PDP-10 of shared/reentrant code and non-shared code is implemented. The inclusion of read only memory on the PDP-11s allows for the development of ''PROM'' software which all the PDP-11s may share. The principal difference between the DMA10 and other communications interfaces is that it is not a block transfer device. Because of the shared memory concept the features of the DMA10 are high data bandwidth and minimal processor intervention between data transfers. Communication programs between the PDP-10 and the PDP-11 may be tested wholly in either processor, independent of the DMA10 interface. In the current mode of operation the PDP-11's simply act as device controllers. Future plans include separate operating systems in various PDP-11s

  5. The Danish real-time SAR processor: first results

    DEFF Research Database (Denmark)

    Dall, Jørgen; Jørgensen, Jørn Hjelm; Netterstrøm, Anders

    1993-01-01

    A real-time processor (RTP) for the Danish airborne Synthetic Aperture Radar (SAR) has been designed and constructed at the Electromagnetics Institute. The implementation was completed in mid 1992, and since then the RTP has been operated successfully on several test and demonstration flights....... The processor is capable of focusing the entire swath of the raw SAR data into full resolution, and depending on the choice made by the on-board operator, either a high resolution one-look zoom image or a spatially multilooked overview image is displayed. After a brief design review, the paper addresses various...

  6. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  7. Wavelength-encoded OCDMA system using opto-VLSI processors

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  8. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures

    Science.gov (United States)

    Manolakos, Elias S.

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub. PMID:26605332

  9. Efficient Multicriteria Protein Structure Comparison on Modern Processor Architectures.

    Science.gov (United States)

    Sharma, Anuj; Manolakos, Elias S

    2015-01-01

    Fast increasing computational demand for all-to-all protein structures comparison (PSC) is a result of three confounding factors: rapidly expanding structural proteomics databases, high computational complexity of pairwise protein comparison algorithms, and the trend in the domain towards using multiple criteria for protein structures comparison (MCPSC) and combining results. We have developed a software framework that exploits many-core and multicore CPUs to implement efficient parallel MCPSC in modern processors based on three popular PSC methods, namely, TMalign, CE, and USM. We evaluate and compare the performance and efficiency of the two parallel MCPSC implementations using Intel's experimental many-core Single-Chip Cloud Computer (SCC) as well as Intel's Core i7 multicore processor. We show that the 48-core SCC is more efficient than the latest generation Core i7, achieving a speedup factor of 42 (efficiency of 0.9), making many-core processors an exciting emerging technology for large-scale structural proteomics. We compare and contrast the performance of the two processors on several datasets and also show that MCPSC outperforms its component methods in grouping related domains, achieving a high F-measure of 0.91 on the benchmark CK34 dataset. The software implementation for protein structure comparison using the three methods and combined MCPSC, along with the developed underlying rckskel algorithmic skeletons library, is available via GitHub.

  10. Three Dimensional Simulation of Ion Thruster Plume-Spacecraft Interaction Based on a Graphic Processor Unit

    International Nuclear Information System (INIS)

    Ren Junxue; Xie Kan; Qiu Qian; Tang Haibin; Li Juan; Tian Huabing

    2013-01-01

    Based on the three-dimensional particle-in-cell (PIC) method and Compute Unified Device Architecture (CUDA), a parallel particle simulation code combined with a graphic processor unit (GPU) has been developed for the simulation of charge-exchange (CEX) xenon ions in the plume of an ion thruster. Using the proposed technique, the potential and CEX plasma distribution are calculated for the ion thruster plume surrounding the DS1 spacecraft at different thrust levels. The simulation results are in good agreement with measured CEX ion parameters reported in literature, and the GPU's results are equal to a CPU's. Compared with a single CPU Intel Core 2 E6300, 16-processor GPU NVIDIA GeForce 9400 GT indicates a speedup factor of 3.6 when the total macro particle number is 1.1×10 6 . The simulation results also reveal how the back flow CEX plasma affects the spacecraft floating potential, which indicates that the plume of the ion thruster is indeed able to alleviate the extreme negative floating potentials of spacecraft in geosynchronous orbit

  11. Portable, remotely operated, computer-controlled, quadrupole mass spectrometer for field use

    International Nuclear Information System (INIS)

    Friesen, R.D.; Newton, J.C.; Smith, C.F.

    1982-04-01

    A portable, remote-controlled mass spectrometer was required at the Nevada Test Site to analyze prompt post-event gas from the nuclear cavity in support of the underground testing program. A Balzers QMG-511 quadrupole was chosen for its ability to be interfaced to a DEC LSI-11 computer and to withstand the ground movement caused by this field environment. The inlet system valves, the pumps, the pressure and temperature transducers, and the quadrupole mass spectrometer are controlled by a read-only-memory-based DEC LSI-11/2 with a high-speed microwave link to the control point which is typically 30 miles away. The computer at the control point is a DEC LSI-11/23 running the RSX-11 operating system. The instrument was automated as much as possible because the system is run by inexperienced operators at times. The mass spectrometer has been used on an initial field event with excellent performance. The gas analysis system is described, including automation by a novel computer control method which reduces operator errors and allows dynamic access to the system parameters

  12. Comparison of speech perception performance between Sprint/Esprit 3G and Freedom processors in children implanted with nucleus cochlear implants.

    Science.gov (United States)

    Santarelli, Rosamaria; Magnavita, Vincenzo; De Filippi, Roberta; Ventura, Laura; Genovese, Elisabetta; Arslan, Edoardo

    2009-04-01

    To compare speech perception performance in children fitted with previous generation Nucleus sound processor, Sprint or Esprit 3G, and the Freedom, the most recently released system from the Cochlear Corporation that features a larger input dynamic range. Prospective intrasubject comparative study. University Medical Center. Seventeen prelingually deafened children who had received the Nucleus 24 cochlear implant and used the Sprint or Esprit 3G sound processor. Cochlear implantation with Cochlear device. Speech perception was evaluated at baseline (Sprint, n = 11; Esprit 3G, n = 6) and after 1 month's experience with the Freedom sound processor. Identification and recognition of disyllabic words and identification of vowels were performed via recorded voice in quiet (70 dB [A]), in the presence of background noise at various levels of signal-to-noise ratio (+10, +5, 0, -5) and at a soft presentation level (60 dB [A]). Consonant identification and recognition of disyllabic words, trisyllabic words, and sentences were evaluated in live voice. Frequency discrimination was measured in a subset of subjects (n = 5) by using an adaptive, 3-interval, 3-alternative, forced-choice procedure. Identification of disyllabic words administered at a soft presentation level showed a significant increase when switching to the Freedom compared with the previously worn processor in children using the Sprint or Esprit 3G. Identification and recognition of disyllabic words in the presence of background noise as well as consonant identification and sentence recognition increased significantly for the Freedom compared with the previously worn device only in children fitted with the Sprint. Frequency discrimination was significantly better when switching to the Freedom compared with the previously worn processor. Serial comparisons revealed that that speech perception performance evaluated in children aged 5 to 15 years was superior with the Freedom than previous generations of Nucleus

  13. ARM Processor Based Embedded System for Remote Data Acquisition

    OpenAIRE

    Raj Kumar Tiwari; Santosh Kumar Agrahari

    2014-01-01

    The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

  14. Application of Advanced Multi-Core Processor Technologies to Oceanographic Research

    Science.gov (United States)

    2013-09-30

    1 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. Application of Advanced Multi-Core Processor Technologies...STM32 NXP LPC series No Proprietary Microchip PIC32/DSPIC No > 500 mW; < 5 W ARM Cortex TI OMAP TI Sitara Broadcom BCM2835 Varies FPGA...state-of-the-art information processing architectures. OBJECTIVES Next-generation processor architectures (multi-core, multi-threaded) hold the

  15. Hardware processors for pattern recognition tasks in experiments with wire chambers

    International Nuclear Information System (INIS)

    Verkerk, C.

    1975-01-01

    Hardware processors for pattern recognition tasks in experiments with multiwire proportional chambers or drift chambers are described. They vary from simple ones used for deciding in real time if particle trajectories are straight to complex ones for recognition of curved tracks. Schematics and block-diagrams of different processors are shown

  16. Long-term effect of September 11 on the political behavior of victims’ families and neighbors

    Science.gov (United States)

    Hersh, Eitan D.

    2013-01-01

    This article investigates the long-term effect of September 11, 2001 on the political behaviors of victims’ families and neighbors. Relative to comparable individuals, family members and residential neighbors of victims have become—and have stayed—significantly more active in politics in the last 12 years, and they have become more Republican on account of the terrorist attacks. The method used to demonstrate these findings leverages the random nature of the terrorist attack to estimate a causal effect and exploits new techniques to link multiple, individual-level, governmental databases to measure behavioral change without relying on surveys or aggregate analysis. PMID:24324145

  17. Long-term effect of September 11 on the political behavior of victims' families and neighbors.

    Science.gov (United States)

    Hersh, Eitan D

    2013-12-24

    This article investigates the long-term effect of September 11, 2001 on the political behaviors of victims' families and neighbors. Relative to comparable individuals, family members and residential neighbors of victims have become--and have stayed--significantly more active in politics in the last 12 years, and they have become more Republican on account of the terrorist attacks. The method used to demonstrate these findings leverages the random nature of the terrorist attack to estimate a causal effect and exploits new techniques to link multiple, individual-level, governmental databases to measure behavioral change without relying on surveys or aggregate analysis.

  18. Amino acid sequences of ribosomal proteins S11 from Bacillus stearothermophilus and S19 from Halobacterium marismortui. Comparison of the ribosomal protein S11 family.

    Science.gov (United States)

    Kimura, M; Kimura, J; Hatakeyama, T

    1988-11-21

    The complete amino acid sequences of ribosomal proteins S11 from the Gram-positive eubacterium Bacillus stearothermophilus and of S19 from the archaebacterium Halobacterium marismortui have been determined. A search for homologous sequences of these proteins revealed that they belong to the ribosomal protein S11 family. Homologous proteins have previously been sequenced from Escherichia coli as well as from chloroplast, yeast and mammalian ribosomes. A pairwise comparison of the amino acid sequences showed that Bacillus protein S11 shares 68% identical residues with S11 from Escherichia coli and a slightly lower homology (52%) with the homologous chloroplast protein. The halophilic protein S19 is more related to the eukaryotic (45-49%) than to the eubacterial counterparts (35%).

  19. Thermal Dissipation Efficiency in a Micro-Processor Using Carbon Nanotubes Based Composite

    Science.gov (United States)

    Thang, Bui Hung; Van Quang, Cao; Nghia, Van Trong; Hong, Phan Ngoc; Van Chuc, Nguyen; Tam, Ngo Thi Thanh; Quang, Le Dinh; Khang, Dao Duc; Khoi, Phan Hong; Minh, Phan Ngoc

    2009-09-01

    Modern electronic and optoelectronic devices such as μ-processor, light emitting diode, semiconductor laser issued a challenge in the thermal dissipation problem. Finding an effective way for thermal dissipation therefore becomes a very important issue. It is known that carbon nanotubes (CNTs) is one of the most valuable materials with high thermal conductivity (2000 W/m.K compared to thermal conductivity of Ag 419 W/m.K). This suggested an approach in applying the CNTs as an essential component for thermal dissipation media to improve the performance of computer processor and other high power electronic devices. In this work multi walled carbon nanotubes (MWCNTs) based composites were utilized as the thermal dissipation media in a micro processor of a personal computer. The MWCNTs of different concentrations were added into polyaniline, commercial silicon thermal paste and commercial silver thermal paste by mechanical methods. A personal computer with configuration: Intel Pentium IV 3.066 GHz, 512 MB of RAM and Windows XP Service Pack 2 Operating System was employed. The thermal dissipation efficiency of the system was evaluated by directly measure the temperature of the μ-processor during the operation of the computer in different CPU speeds. The measured results showed that the CNTs based composite could reduce the temperature of the u-processor more than 5° C, and the time for increasing the temperature of the μ-processor was three times longer than that when using commercial thermal paste.

  20. Video frame processor

    International Nuclear Information System (INIS)

    Joshi, V.M.; Agashe, Alok; Bairi, B.R.

    1993-01-01

    This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

  1. Genetic heterogeneity in familial exudative vitreoretinopathy; exclusion of the EVR1 locus on chromosome 11q in a large autosomal dominant pedigree.

    Science.gov (United States)

    Bamashmus, M A; Downey, L M; Inglehearn, C F; Gupta, S R; Mansfield, D C

    2000-04-01

    Familial exudative vitreoretinopathy (FEVR) is associated with mutations in the Norrie disease gene in X linked pedigrees and with linkage to the EVR1 locus at 11q13 in autosomal dominant cases. A large autosomal dominant FEVR family was studied, both clinically and by linkage analysis, to determine whether it differed from the known forms of FEVR. Affected members and obligate gene carriers from this family were examined by slit lamp biomicroscopy, indirect ophthalmoscopy, and in some cases fluorescein angiography. Patient DNAs were genotyped for markers at the EVR1 locus on chromosome 11q13. The clinical evaluation in this family is consistent with previous descriptions of FEVR pedigrees, but linkage analysis proves that it has a form of FEVR genetically distinct from the EVR1 locus on 11q. This proves that there are at least three different loci associated with comparable FEVR phenotypes, a situation similar to that existing for many forms of retinal degeneration.

  2. Synchronization of faulty processors in coarse-grained TMR protected partially reconfigurable FPGA designs

    International Nuclear Information System (INIS)

    Kretzschmar, U.; Gomez-Cornejo, J.; Astarloa, A.; Bidarte, U.; Ser, J. Del

    2016-01-01

    The expansion of FPGA technology in numerous application fields is a fact. Single Event Effects (SEE) are a critical factor for the reliability of FPGA based systems. For this reason, a number of researches have been studying fault tolerance techniques to harden different elements of FPGA designs. Using Partial Reconfiguration (PR) in conjunction with Triple Modular Redundancy (TMR) is an emerging approach in recent publications dealing with the implementation of fault tolerant processors on SRAM-based FPGAs. While these works pay great attention to the repair of erroneous instances by means of reconfiguration, the essential step of synchronizing the repaired processors is insufficiently addressed. In this context, this paper poses four different synchronization approaches for soft core processors, which balance differently the trade-off between synchronization speed and hardware overhead. All approaches are assessed in practice by synchronizing TMR protected PicoBlaze processors implemented on a Virtex-5 FPGA. Nevertheless all methods are of a general nature and can be applied for different processor architectures in a straightforward fashion. - Highlights: • Four different synchronization methods for faulty processors are proposed. • The methods balance between synchronization speed and hardware overhead. • They can be applied to TMR-protected reconfigurable FPGA designs. • The proposed schemes are implemented and tested in real hardware.

  3. Simulation of Particulate Flows Multi-Processor Machines with Distributed Memory

    Energy Technology Data Exchange (ETDEWEB)

    Uhlmann, M.

    2004-07-01

    We presented a method for the parallelization of an immersed boundary algorithm for particulate flows using the MPI standard of communication. The treatment of the fluid phase used the domain decomposition technique over a Cartesian processor grid. The solution of the Helmholtz problem is approximately factorized an relies upon apparel tri-diagonal solver the Poisson problem is solved by means of a parallel multi-grid technique similar to MUDPACK. for the solid phase we employ a master-slaves technique where one processor handles all the particles contained in its Eulerian fluid sub-domain and zero or more neighbor processors collaborate in the computation of particle-related quantities whenever a particle position over laps the boundary of a sub-domain. the parallel efficiency for some preliminary computations is presented. (Author) 9 refs.

  4. General distributed control system for fusion experiments

    International Nuclear Information System (INIS)

    Klingner, P.L.; Levings, S.J.; Wilkins, R.W.

    1986-01-01

    A general control system using distributed LSI-11 microprocessors is being developed. Common software residues in each LSI-11 and is tailored to an application by control specifications downloaded from a host computer. The microprocessors, their control interfaces, and the micro-to-host communications are CAMAC based. The host computer also supports an operator interface, coordination of multiple microprocessors, and utilities to create and maintain the control specifications. Typical applications include monitoring safety interlocks as well as controlling vacuum systems, high voltage charging systems, and diagnostics

  5. MORPION: a fast hardware processor for straight line finding in MWPC

    International Nuclear Information System (INIS)

    Mur, M.

    1980-02-01

    A fast hardware processor for straight line finding in MWPC has been built in Saclay and successfully operated in the NA3 experiment at CERN. We give the motivations to build this processor, and describe the hardware implementation of the line finding algorithm. Finally its use and performance in NA3 are described

  6. Graphics processor efficiency for realization of rapid tabular computations

    International Nuclear Information System (INIS)

    Dudnik, V.A.; Kudryavtsev, V.I.; Us, S.A.; Shestakov, M.V.

    2016-01-01

    Capabilities of graphics processing units (GPU) and central processing units (CPU) have been investigated for realization of fast-calculation algorithms with the use of tabulated functions. The realization of tabulated functions is exemplified by the GPU/CPU architecture-based processors. Comparison is made between the operating efficiencies of GPU and CPU, employed for tabular calculations at different conditions of use. Recommendations are formulated for the use of graphical and central processors to speed up scientific and engineering computations through the use of tabulated functions

  7. FASTBUS Standard Routines implementation for Fermilab embedded processor boards

    International Nuclear Information System (INIS)

    Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

    1992-10-01

    In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

  8. Statistical analysis of quality control of automatic processor

    International Nuclear Information System (INIS)

    Niu Yantao; Zhao Lei; Zhang Wei; Yan Shulin

    2002-01-01

    Objective: To strengthen the scientific management of automatic processor and promote QC, based on analyzing QC management chart for automatic processor by statistical method, evaluating and interpreting the data and trend of the chart. Method: Speed, contrast, minimum density of step wedge of film strip were measured everyday and recorded on the QC chart. Mean (x-bar), standard deviation (s) and range (R) were calculated. The data and the working trend were evaluated and interpreted for management decisions. Results: Using relative frequency distribution curve constructed by measured data, the authors can judge whether it is a symmetric bell-shaped curve or not. If not, it indicates a few extremes overstepping control limits possibly are pulling the curve to the left or right. If it is a normal distribution, standard deviation (s) is observed. When x-bar +- 2s lies in upper and lower control limits of relative performance indexes, it indicates the processor works in stable status in this period. Conclusion: Guided by statistical method, QC work becomes more scientific and quantified. The authors can deepen understanding and application of the trend chart, and improve the quality management to a new step

  9. Broadband set-top box using MAP-CA processor

    Science.gov (United States)

    Bush, John E.; Lee, Woobin; Basoglu, Chris

    2001-12-01

    Advances in broadband access are expected to exert a profound impact in our everyday life. It will be the key to the digital convergence of communication, computer and consumer equipment. A common thread that facilitates this convergence comprises digital media and Internet. To address this market, Equator Technologies, Inc., is developing the Dolphin broadband set-top box reference platform using its MAP-CA Broadband Signal ProcessorT chip. The Dolphin reference platform is a universal media platform for display and presentation of digital contents on end-user entertainment systems. The objective of the Dolphin reference platform is to provide a complete set-top box system based on the MAP-CA processor. It includes all the necessary hardware and software components for the emerging broadcast and the broadband digital media market based on IP protocols. Such reference design requires a broadband Internet access and high-performance digital signal processing. By using the MAP-CA processor, the Dolphin reference platform is completely programmable, allowing various codecs to be implemented in software, such as MPEG-2, MPEG-4, H.263 and proprietary codecs. The software implementation also enables field upgrades to keep pace with evolving technology and industry demands.

  10. The Model of Communication Channel in the 802.11b Standard Wireless Network

    Directory of Open Access Journals (Sweden)

    Zdenek Nemec

    2008-01-01

    Full Text Available The paper deals with software modelling of a communication channel in the 802.11b standard wireless network physical layer. A computer model of signal processing was created to verify possibility of the proposal of localisation system. Functionality of the signal generation and processing model was verified by the Spectrum Analyzer. Simulations run inSimulink/Matlab SW. The Simulink is used for the signal processor model and a pure Matlab software is used for mathematical evaluations of data processor model and for determination of initial conditions.

  11. High-Performance Linear Algebra Processor using FPGA

    National Research Council Canada - National Science Library

    Johnson, J

    2004-01-01

    With recent advances in FPGA (Field Programmable Gate Array) technology it is now feasible to use these devices to build special purpose processors for floating point intensive applications that arise in scientific computing...

  12. Use of a track and vertex processor in a fixed-target charm experiment

    International Nuclear Information System (INIS)

    Schub, M.H.; Carey, T.A.; Hsiung, Y.B.; Kaplan, D.M.; Lee, C.; Miller, G.; Sa, J.; Teng, P.K.

    1996-01-01

    We have constructed and operated a high-speed parallel-pipelined track and vertex processor and used it to trigger data acquisition in a high-rate charm and beauty experiment at Fermilab. The processor uses information from hodoscopes and wire chambers to reconstruct tracks in the bend view of a magnetic spectrometer, and uses these tracks to find the corresponding tracks in a set of silicon-strip detectors. The processor then forms vertices and triggers the experiment if at least one vertex is downstream of the target. Under typical charm running conditions, with an interaction rate of ∼5 MHz, the processor rejects 80-90% of lower-level triggers while maintaining efficiency of ∼70% for two-prong D-meson decays. (orig.)

  13. Simplifying cochlear implant speech processor fitting

    NARCIS (Netherlands)

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

  14. A prediction method for job runtimes on shared processors: Survey, statistical analysis and new avenues

    NARCIS (Netherlands)

    Dobber, A.M.; van der Mei, R.D.; Koole, G.M.

    2007-01-01

    Grid computing is an emerging technology by which huge numbers of processors over the world create a global source of processing power. Their collaboration makes it possible to perform computations that are too extensive to perform on a single processor. On a grid, processors may connect and

  15. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  16. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  17. Evaluating Food Safety Knowledge and Practices of Food Processors and Sellers Working in Food Facilities in Hanoi, Vietnam.

    Science.gov (United States)

    Tran, Bach Xuan; DO, Hoa Thi; Nguyen, Luong Thanh; Boggiano, Victoria; LE, Huong Thi; LE, Xuan Thanh Thi; Trinh, Ngoc Bao; DO, Khanh Nam; Nguyen, Cuong Tat; Nguyen, Thanh Trung; Dang, Anh Kim; Mai, Hue Thi; Nguyen, Long Hoang; Than, Selena; Latkin, Carl A

    2018-04-01

    Consumption of fast food and street food is increasingly common among Vietnamese, particularly in large cities. The high daily demand for these convenient food services, together with a poor management system, has raised concerns about food hygiene and safety (FHS). This study aimed to examine the FHS knowledge and practices of food processors and sellers in food facilities in Hanoi, Vietnam, and to identify their associated factors. A cross-sectional study was conducted with 1,760 food processors and sellers in restaurants, fast food stores, food stalls, and street vendors in Hanoi in 2015. We assessed each participant's FHS knowledge using a self-report questionnaire and their FHS practices using a checklist. Tobit regression was used to determine potential factors associated with FHS knowledge and practices, including demographics, training experience, and frequency of health examination. Overall, we observed a lack of FHS knowledge among respondents across three domains, including standard requirements for food facilities (18%), food processing procedures (29%), and food poisoning prevention (11%). Only 25.9 and 38.1% of participants used caps and masks, respectively, and 12.8% of food processors reported direct hand contact with food. After adjusting for socioeconomic characteristics, these factors significantly predicted increased FHS knowledge and practice scores: (i) working at restaurants and food stalls, (ii) having FHS training, (iii) having had a physical examination, and (iv) having taken a stool test within the last year. These findings highlight the need of continuous training to improve FHS knowledge and practices among food processors and food sellers. Moreover, regular monitoring of food facilities, combined with medical examination of their staff, should be performed to ensure food safety.

  18. A Bayesian sequential processor approach to spectroscopic portal system decisions

    Energy Technology Data Exchange (ETDEWEB)

    Sale, K; Candy, J; Breitfeller, E; Guidry, B; Manatt, D; Gosnell, T; Chambers, D

    2007-07-31

    The development of faster more reliable techniques to detect radioactive contraband in a portal type scenario is an extremely important problem especially in this era of constant terrorist threats. Towards this goal the development of a model-based, Bayesian sequential data processor for the detection problem is discussed. In the sequential processor each datum (detector energy deposit and pulse arrival time) is used to update the posterior probability distribution over the space of model parameters. The nature of the sequential processor approach is that a detection is produced as soon as it is statistically justified by the data rather than waiting for a fixed counting interval before any analysis is performed. In this paper the Bayesian model-based approach, physics and signal processing models and decision functions are discussed along with the first results of our research.

  19. Parallelising a molecular dynamics algorithm on a multi-processor workstation

    Science.gov (United States)

    Müller-Plathe, Florian

    1990-12-01

    The Verlet neighbour-list algorithm is parallelised for a multi-processor Hewlett-Packard/Apollo DN10000 workstation. The implementation makes use of memory shared between the processors. It is a genuine master-slave approach by which most of the computational tasks are kept in the master process and the slaves are only called to do part of the nonbonded forces calculation. The implementation features elements of both fine-grain and coarse-grain parallelism. Apart from three calls to library routines, two of which are standard UNIX calls, and two machine-specific language extensions, the whole code is written in standard Fortran 77. Hence, it may be expected that this parallelisation concept can be transfered in parts or as a whole to other multi-processor shared-memory computers. The parallel code is routinely used in production work.

  20. Real time processor for array speckle interferometry

    International Nuclear Information System (INIS)

    Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

    1989-01-01

    With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

  1. UNIBUS processor interface for a FASTBUS data acquisition system

    International Nuclear Information System (INIS)

    Larwill, M.; Lagerlund, T.D.; Barsotti, E.; Taff, L.M.; Franzen, J.

    1981-01-01

    Current work on a FASTBUS data acquisition system at Fermilab is described. The system will consist of three pieces of FASTBUS hardware: a UNIBUS processor interface (UPI), a dual-ported bulk memory, and a FASTBUS ''event builder'' (i.e., data acquisition processor). Primary efforts have been on specifying and constructing a UPI. The present specification includes capability for all basic FASTBUS operations, including list processing of consecutive FASTBUS operations. Some possible FASTBUS data acquisition system architectures employing the UPI are discussed along with some detailed specifications of the UPI itself

  2. The UA1 trigger processor

    International Nuclear Information System (INIS)

    Grayer, G.H.

    1981-01-01

    Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

  3. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  4. Suboptimal processor for anomaly detection for system surveillance and diagnosis

    Energy Technology Data Exchange (ETDEWEB)

    Ciftcioglu, Oe.; Hoogenboom, J.E.; Dam, H. van

    1989-06-01

    Anomaly detection for nuclear reactor surveillance and diagnosis is described. The residual noise obtained as a result of autoregressive (AR) modelling is essential to obtain high sensitivity for anomaly detection. By means of the method of hypothesis testing a suboptimal anomaly detection processor is devised for system surveillance and diagnosis. Experiments are carried out to investigate the performance of the processor, which is in particular of interest for on-line and real-time applications.

  5. A Trade Study of Two Membrane-Aerated Biological Water Processors

    Science.gov (United States)

    Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

    2011-01-01

    Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

  6. Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

    Science.gov (United States)

    Casasent, D.; Jackson, J.

    1986-01-01

    A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

  7. Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

    Energy Technology Data Exchange (ETDEWEB)

    Nuvera Fuel Cells

    2005-04-15

    The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

  8. The Square Kilometre Array Science Data Processor. Preliminary compute platform design

    International Nuclear Information System (INIS)

    Broekema, P.C.; Nieuwpoort, R.V. van; Bal, H.E.

    2015-01-01

    The Square Kilometre Array is a next-generation radio-telescope, to be built in South Africa and Western Australia. It is currently in its detailed design phase, with procurement and construction scheduled to start in 2017. The SKA Science Data Processor is the high-performance computing element of the instrument, responsible for producing science-ready data. This is a major IT project, with the Science Data Processor expected to challenge the computing state-of-the art even in 2020. In this paper we introduce the preliminary Science Data Processor design and the principles that guide the design process, as well as the constraints to the design. We introduce a highly scalable and flexible system architecture capable of handling the SDP workload

  9. An enhanced Ada run-time system for real-time embedded processors

    Science.gov (United States)

    Sims, J. T.

    1991-01-01

    An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

  10. High speed vision processor with reconfigurable processing element array based on full-custom distributed memory

    Science.gov (United States)

    Chen, Zhe; Yang, Jie; Shi, Cong; Qin, Qi; Liu, Liyuan; Wu, Nanjian

    2016-04-01

    In this paper, a hybrid vision processor based on a compact full-custom distributed memory for near-sensor high-speed image processing is proposed. The proposed processor consists of a reconfigurable processing element (PE) array, a row processor (RP) array, and a dual-core microprocessor. The PE array includes two-dimensional processing elements with a compact full-custom distributed memory. It supports real-time reconfiguration between the PE array and the self-organized map (SOM) neural network. The vision processor is fabricated using a 0.18 µm CMOS technology. The circuit area of the distributed memory is reduced markedly into 1/3 of that of the conventional memory so that the circuit area of the vision processor is reduced by 44.2%. Experimental results demonstrate that the proposed design achieves correct functions.

  11. Initial explorations of ARM processors for scientific computing

    International Nuclear Information System (INIS)

    Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad

    2014-01-01

    Power efficiency is becoming an ever more important metric for both high performance and high throughput computing. Over the course of next decade it is expected that flops/watt will be a major driver for the evolution of computer architecture. Servers with large numbers of ARM processors, already ubiquitous in mobile computing, are a promising alternative to traditional x86-64 computing. We present the results of our initial investigations into the use of ARM processors for scientific computing applications. In particular we report the results from our work with a current generation ARMv7 development board to explore ARM-specific issues regarding the software development environment, operating system, performance benchmarks and issues for porting High Energy Physics software

  12. SPP: A data base processor data communications protocol

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    The design and implementation of a data communications protocol for the Intel Data Base Processor (DBP) is defined. The protocol is termed SPP (Service Port Protocol) since it enables data transfer between the host computer and the DBP service port. The protocol implementation is extensible in that it is explicitly layered and the protocol functionality is hierarchically organized. Extensive trace and performance capabilities have been supplied with the protocol software to permit optional efficient monitoring of the data transfer between the host and the Intel data base processor. Machine independence was considered to be an important attribute during the design and implementation of SPP. The protocol source is fully commented and is included in Appendix A of this report.

  13. Evaluation of This Process on Healt Indicators of 11 Provinces Practicing Model of Family Medicine Firstly

    Directory of Open Access Journals (Sweden)

    Nasir Nesanir

    2010-10-01

    Full Text Available AIM: The aim of This study is to eveluata the process On Healt Indicator In Between 2000 and 2007 years. Of 11 provinces practicing model of Family Medicine firstly. METHOD: This observational-descriptive study was made in May-June 2008 On Healt Indicator Of 11 provincespracticed the model of Family Medicine at least for a year. It vas taken through the Ministry of Health 20 Health Indicators belonging to the years 2000 and 2007 Of these provinces and also we benefited from data in annual studies from 2000 to 2006 of General Directorate of Primary Health Care of the Ministry of Health. RESULTS: There were. 3496 physicians and 6075 nurses, midwives in 2007 when 2677 physicians and 6042 nurse midwives were working in 2005 in 11 provinces. It was 90% in 2006 while immunization of DBT3 in 0 aged group was 80% in 2000 In 81 provinces , It was 92% and 90% in 11 provinces immunization of DBT3 in 0 aged group for the same years. Follow-up per number of pregnant women in Duzce in 2000 was 1.9 and it was 2.7 in 2005, it was 3.7in 2007. During the same years in Edirne the numbers were 9.0, 11.0, 4.6. Follow-up per number of confined in Eskisehir in 2000 was 1.2 and it was 2.1 in 2005 and it was 1.5 in 2007. in Izmir during the same years the numbers were 1.9, 2.4 and 2.2. In Duzce, the number of the observation per infant was 4.0 in 2000 and it was 7.7 in 2005 and it was 10.2 in 2007. In Eskisehir during the same year the numbers were 5.9, 9.4, 7.9. CONCLUSION: the number of physicians in primary care with this application has increased. In health-level indicators family medicine or primary health care services distinction is not whether the payment per service is deemed to be more specific. To better assess the health status indicators, field studies should be performed. [TAF Prev Med Bull 2010; 9(5.000: 493-504

  14. Techniques for optimizing inerting in electron processors

    International Nuclear Information System (INIS)

    Rangwalla, I.J.; Korn, D.J.; Nablo, S.V.

    1993-01-01

    The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NO x which can be transported from the process zone by the product into the work area. Since the tolerable levels for O 3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O 2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O 2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O 2 ). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O 2 ) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O 2 ) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

  15. Expert System Constant False Alarm Rate (CFAR) Processor

    National Research Council Canada - National Science Library

    Wicks, Michael C

    2006-01-01

    An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...

  16. Choosing processor array configuration by performance modeling for a highly parallel linear algebra algorithm

    International Nuclear Information System (INIS)

    Littlefield, R.J.; Maschhoff, K.J.

    1991-04-01

    Many linear algebra algorithms utilize an array of processors across which matrices are distributed. Given a particular matrix size and a maximum number of processors, what configuration of processors, i.e., what size and shape array, will execute the fastest? The answer to this question depends on tradeoffs between load balancing, communication startup and transfer costs, and computational overhead. In this paper we analyze in detail one algorithm: the blocked factored Jacobi method for solving dense eigensystems. A performance model is developed to predict execution time as a function of the processor array and matrix sizes, plus the basic computation and communication speeds of the underlying computer system. In experiments on a large hypercube (up to 512 processors), this model has been found to be highly accurate (mean error ∼ 2%) over a wide range of matrix sizes (10 x 10 through 200 x 200) and processor counts (1 to 512). The model reveals, and direct experiment confirms, that the tradeoffs mentioned above can be surprisingly complex and counterintuitive. We propose decision procedures based directly on the performance model to choose configurations for fastest execution. The model-based decision procedures are compared to a heuristic strategy and shown to be significantly better. 7 refs., 8 figs., 1 tab

  17. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

    Science.gov (United States)

    Cheung, Kit; Schultz, Simon R; Luk, Wayne

    2015-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

  18. Beeldverwerking met de Micron Automatic Processor

    OpenAIRE

    Goyens, Frank

    2017-01-01

    Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

  19. Compact gasoline fuel processor for passenger vehicle APU

    Science.gov (United States)

    Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

    Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

  20. A familial pericentric inversion of chromosome 11 associated with a microdeletion of 163 kb and microduplication of 288 kb at 11p13 and 11q22.3 without aniridia or eye anomalies.

    Science.gov (United States)

    Balay, Lara; Totten, Ellen; Okada, Luna; Zell, Sidney; Ticho, Benjamin; Israel, Jeannette; Kogan, Jillene

    2016-01-01

    Interstitial deletions of 11p13 involving MPPED2, DCDC5, DCDC1, DNAJC24, IMMP1L, and ELP4 are previously reported to have downstream transcriptional effects on the expression of PAX6, due to a downstream regulatory region (DRR). Currently, no clear genotype-phenotype correlations have been established allowing for conclusive information regarding the exact location of the PAX6 DRR, though its location has been approximated in mouse models to be within the Elp4 gene. Of the clinical reports currently published examining patients with intact PAX6 genes but harboring deletions identified in genes downstream of PAX6, 100% indicate phenotypes which include aniridia, whereas approximately half report additional eye deformities, autism, or intellectual disability. In this clinical report, we present a 12-year-old male patient, his brother, and mother with pericentric inversions of chromosome 11 associated with submicroscopic interstitial deletions of 11p13 and duplications of 11q22.3. The inversions were identified by standard cytogenetic analysis; microarray and FISH detected the chromosomal imbalance. The patient's phenotype includes intellectual disability, speech abnormalities, and autistic behaviors, but interestingly neither the patient, his brother, nor mother have aniridia or other eye anomalies. To the best of our knowledge, these findings in three family members represent the only reported cases with 11p13 deletions downstream of PAX6 not demonstrating phenotypic characteristics of aniridia or abnormal eye development. Although none of the deleted genes are obvious candidates for the patient's phenotype, the absence of aniridia in the presence of this deletion in all three family members further delineates the location of the DRR for PAX6. © 2015 Wiley Periodicals, Inc.

  1. Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

    OpenAIRE

    Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

    2016-01-01

    Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

  2. Using of opportunities of graphic processors for acceleration of scientific and technical calculations

    International Nuclear Information System (INIS)

    Dudnik, V.A.; Kudryavtsev, V.I.; Sereda, T.M.; Us, S.A.; Shestakov, M.V.

    2009-01-01

    The new opportunities of modern graphic processors (GPU) for acceleration of the scientific and technical calculations with the help of paralleling of a calculating task between the central processor and GPU are described. The description of using the technology NVIDIA CUDA for connection of parallel computing opportunities of GPU within the programme of the some intensive mathematical tasks is resulted. The examples of comparison of parameters of productivity in the process of these tasks' calculation without application of GPU and with use of opportunities NVIDIA CUDA for graphic processor GeForce 8800 are resulted

  3. Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

    NARCIS (Netherlands)

    Anjam, F.

    2013-01-01

    In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

  4. Real-Time Adaptive Lossless Hyperspectral Image Compression using CCSDS on Parallel GPGPU and Multicore Processor Systems

    Science.gov (United States)

    Hopson, Ben; Benkrid, Khaled; Keymeulen, Didier; Aranki, Nazeeh; Klimesh, Matt; Kiely, Aaron

    2012-01-01

    The proposed CCSDS (Consultative Committee for Space Data Systems) Lossless Hyperspectral Image Compression Algorithm was designed to facilitate a fast hardware implementation. This paper analyses that algorithm with regard to available parallelism and describes fast parallel implementations in software for GPGPU and Multicore CPU architectures. We show that careful software implementation, using hardware acceleration in the form of GPGPUs or even just multicore processors, can exceed the performance of existing hardware and software implementations by up to 11x and break the real-time barrier for the first time for a typical test application.

  5. Trigger and decision processors

    International Nuclear Information System (INIS)

    Franke, G.

    1980-11-01

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  6. Optical Finite Element Processor

    Science.gov (United States)

    Casasent, David; Taylor, Bradley K.

    1986-01-01

    A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

  7. Performance evaluation of integrated fuel processor for residential PEMFCs application

    International Nuclear Information System (INIS)

    Yu Taek Seo; Dong Joo Seo; Young-Seog Seo; Hyun-Seog Roh; Wang Lai Yoon; Jin Hyeok Jeong

    2006-01-01

    KIER has been developing the natural gas fuel processor to produce hydrogen rich gas for residential PEMFCs system. To realize a compact and high efficiency, the unit processes of steam reforming, water gas shift, and preferential oxidation are chemically and physically integrated in a package. Current fuel processor designed for 1 kW class PEMFCs shows thermal efficiency of 78% as a HHV basis with methane conversion of 90% at rated load operation. CO concentration below 10 ppm in the produced gas is achieved with preferential oxidation unit using Pt and Ru based catalyst under the condition of [O 2 ]/[CO]=2.0. The partial load operation have been carried out to test the performance of fuel processor from 40% to 80% load, showing stable methane conversion and CO concentration below 10 ppm. The durability test for the daily start-stop and 8 hr operation procedure is under investigation and shows no deterioration of its performance after 40 start-stop cycles. (authors)

  8. Radiation Tolerant Software Defined Video Processor, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — MaXentric's is proposing a radiation tolerant Software Define Video Processor, codenamed SDVP, for the problem of advanced motion imaging in the space environment....

  9. The fast tracker processor for hadronic collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

    2000-01-01

    Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

  10. Digital implementation of the preloaded filter pulse processor

    International Nuclear Information System (INIS)

    Westphal, G.P.; Cadek, G.R.; Keroe, N.; Sauter, TH.; Thorwartl, P.C.

    1995-01-01

    Adapting it's processing time to the respective pulse intervals, the Preloaded Filter (PLF) pulse processor offers optimum resolution together with highest possible throughput rates. The PLF algorithm could be formulated in a recursive manner which made possible it's implementation by means of a large field-programmable gate array, as a fast, pipe-lined digital processor with 10 MHz maximum throughput rate. While pre-filter digitization by an ADC with 12 bit resolution and 10M Hz sampling rate resulted in a poorer resolution than that of an analog filter, a digital PLF based on an ADC with 14 bit resolution and 10 MHz sampling rate, surpassed high-quality analog filters in resolution, throughput rate and long-term stability. (author) 6 refs.; 7 figs

  11. Biological Water Processor and Forward Osmosis Secondary Treatment

    Science.gov (United States)

    Shull, Sarah; Meyer, Caitlin

    2014-01-01

    The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

  12. Dual shear plate power processor packaging design. [for Solar Electric Propulsion spacecraft

    Science.gov (United States)

    Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.

    1975-01-01

    The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.

  13. Parallel processor programs in the Federal Government

    Science.gov (United States)

    Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.

    1985-01-01

    In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

  14. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    OpenAIRE

    Hristov Ivan; Goranov Goran; Hristova Radoslava

    2018-01-01

    We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named “Ivy Bridge-EP”) in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named “Knights Landing” (KNL). The results show 2 times better per...

  15. Global synchronization of parallel processors using clock pulse width modulation

    Science.gov (United States)

    Chen, Dong; Ellavsky, Matthew R.; Franke, Ross L.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Jeanson, Mark J.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Littrell, Daniel; Ohmacht, Martin; Reed, Don D.; Schenck, Brandon E.; Swetz, Richard A.

    2013-04-02

    A circuit generates a global clock signal with a pulse width modification to synchronize processors in a parallel computing system. The circuit may include a hardware module and a clock splitter. The hardware module may generate a clock signal and performs a pulse width modification on the clock signal. The pulse width modification changes a pulse width within a clock period in the clock signal. The clock splitter may distribute the pulse width modified clock signal to a plurality of processors in the parallel computing system.

  16. Pathway Processor 2.0: a web resource for pathway-based analysis of high-throughput data.

    Science.gov (United States)

    Beltrame, Luca; Bianco, Luca; Fontana, Paolo; Cavalieri, Duccio

    2013-07-15

    Pathway Processor 2.0 is a web application designed to analyze high-throughput datasets, including but not limited to microarray and next-generation sequencing, using a pathway centric logic. In addition to well-established methods such as the Fisher's test and impact analysis, Pathway Processor 2.0 offers innovative methods that convert gene expression into pathway expression, leading to the identification of differentially regulated pathways in a dataset of choice. Pathway Processor 2.0 is available as a web service at http://compbiotoolbox.fmach.it/pathwayProcessor/. Sample datasets to test the functionality can be used directly from the application. duccio.cavalieri@fmach.it Supplementary data are available at Bioinformatics online.

  17. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  18. Modcomp MAX IV System Processors reference guide

    Energy Technology Data Exchange (ETDEWEB)

    Cummings, J.

    1990-10-01

    A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

  19. A pre- and post-processor for the ICOOL muon transport code

    International Nuclear Information System (INIS)

    Fawley, W.M.

    2001-01-01

    ICOOL[1] is a Fortran77 macroparticle transport code widely used by researchers to study the front end of a neutrino factory/muon collider[2]. In part due to the desire that ICOOL be usable over multiple computer platforms and operating systems, the code uses simple text files for input/output services. This choice together with user-driven requests for greater and greater choice of lattice element type and configuration has led to ICOOL input decks becoming rather difficult to compose and modify easily. Moreover, the lack of a standard graphical post-processor has prevented many ICOOL users from extracting all but the most simple results from the output files. Here I present two attempts to improve this situation: First, a simple but quite general graphical pre-processor (NIME) written in the Tcl/TK[3] to permit users to write and maintain ASCII-formatted input files by use of simple macro definitions and expansions. Second, an interactive post-processor written in Fortran90 and NCAR graphics, which allows users to define, extract, and then examine the behavior of various particle subsets. In this paper I show some examples of use of both the pre- and post-processor for a standard ICOOL run

  20. Making the black box signal processor transparent explains the contradictions in x-ray spectroscopy

    International Nuclear Information System (INIS)

    Papp, T.; Maxwell, J.A.; Papp, A.T.

    2008-01-01

    Full text: There are significant differences in the experimental data needed in the analysis of x-ray spectra, and many of the results contradict basic conservation laws and simple arithmetic. We have identified that the main source of the unexplainable results is rooted in the signal processing electronics. We have developed a line of fully digital signal processors that have yielded improved resolution, line shape, tailing and pile up recognition. The signal processor is a time variant, non-paralyzable signal processor. The signal processor accounts for and registers all events, sorting them into two spectra, one spectrum for the desirable or accepted events, and one spectrum for the rejected events. Although the information on the rejected events is always necessary, we recently realized its additional benefits in high rate, (10 5 -10 6 cps) analytical measurements. Having all information available we were surprised to see how different conclusions and level of understandings are possible in detector characterization, detector efficiency, spectrum evaluation methodology, and that it explains many of the contradictions. We will demonstrate how the Coster-Kronig transition measurements often do not even comply with arithmetic, and why is it difficult to interpret the spectra with other processors. It will be presented that for different spectra in origin, like radioisotope measurements, x-ray fluorescence, and particle induced x-ray emission, the primary signal from the preamplifier is so different, that the signal processor is facing very different challenges, and different metrological approaches are necessary in data processing. This data processing methodology cannot be established on the partial and fractional information offered by other approaches. However, the maximum information utilization approach offered by our processor's rejected spectrum supplements the accepted spectrum to allow the development of straight forward and accurate metrology. All the

  1. Speeding up the MATLAB complex networks package using graphic processors

    International Nuclear Information System (INIS)

    Zhang Bai-Da; Wu Jun-Jie; Li Xin; Tang Yu-Hua

    2011-01-01

    The availability of computers and communication networks allows us to gather and analyse data on a far larger scale than previously. At present, it is believed that statistics is a suitable method to analyse networks with millions, or more, of vertices. The MATLAB language, with its mass of statistical functions, is a good choice to rapidly realize an algorithm prototype of complex networks. The performance of the MATLAB codes can be further improved by using graphic processor units (GPU). This paper presents the strategies and performance of the GPU implementation of a complex networks package, and the Jacket toolbox of MATLAB is used. Compared with some commercially available CPU implementations, GPU can achieve a speedup of, on average, 11.3×. The experimental result proves that the GPU platform combined with the MATLAB language is a good combination for complex network research. (interdisciplinary physics and related areas of science and technology)

  2. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  3. PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

    Directory of Open Access Journals (Sweden)

    R. Maheswari

    2012-04-01

    Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

  4. Bounds on achievable accuracy in analog optical linear-algebra processors

    Science.gov (United States)

    Batsell, Stephen G.; Walkup, John F.; Krile, Thomas F.

    1990-07-01

    Upper arid lower bounds on the number of bits of accuracy achievable are determined by applying a seconth-ortler statistical model to the linear algebra processor. The use of bounds was found necessary due to the strong signal-dependence of the noise at the output of the optical linear algebra processor (OLAP). 1 1. ACCURACY BOUNDS One of the limiting factors in applying OLAPs to real world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication ard addition operations spatial variations across arrays and crosstalk. We have previously examined these noise sources and determined a general model for the output noise mean and variance. The model demonstrates a strony signaldependency in the noise at the output of the processor which has been confirmed by our experiments. 1 We define accuracy similar to its definition for an analog signal input to an analog-to-digital (ND) converter. The number of bits of accuracy achievable is related to the log (base 2) of the number of separable levels at the P/D converter output. The number of separable levels is fouri by dividing the dynamic range by m times the standard deviation of the signal a. 2 Here m determines the error rate in the P/D conversion. The dynamic range can be expressed as the

  5. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  6. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

  7. Review of ANSI [American National Standards Institute] N13.11: A status report

    International Nuclear Information System (INIS)

    Sims, C.S.

    1988-01-01

    In 1983, the American National Standards Institute (ANSI) issued the dosimetry standard titled ''Personnel Dosimetry Performance -- Criteria for Testing'' as ANSI N13.11. This standard forms the basis for the National Voluntary Laboratory Accreditation Program (NVLAP) which has become familiar to dosimeter processors in recent years. This standard is particularly important because the Nuclear Regulatory Commission (NRC) requires that all licensees have personnel dosimetry devices processed by processors that are NVLAP accredited. This standard is currently undergoing review and modifications are going to be made. This paper contains a brief history of the events leading to the development of ANSI N13.11 - 1983, information concerning the present standard and associated performance test results, and the selection of the review group. Following that, the status of the review is presented and statements regarding the future outlook for the standard are made. 10 refs., 5 tabs

  8. The application of charge-coupled device processors in automatic-control systems

    Science.gov (United States)

    Mcvey, E. S.; Parrish, E. A., Jr.

    1977-01-01

    The application of charge-coupled device (CCD) processors to automatic-control systems is suggested. CCD processors are a new form of semiconductor component with the unique ability to process sampled signals on an analog basis. Specific implementations of controllers are suggested for linear time-invariant, time-varying, and nonlinear systems. Typical processing time should be only a few microseconds. This form of technology may become competitive with microprocessors and minicomputers in addition to supplementing them.

  9. Very wide register : an asymmetric register file organization for low power embedded processors.

    NARCIS (Netherlands)

    Raghavan, P.; Lambrechts, A.; Jayapala, M.; Catthoor, F.; Verkest, D.T.M.L.; Corporaal, H.

    2007-01-01

    In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the

  10. 7 CFR 201.73 - Processors and processing of all classes of certified seed.

    Science.gov (United States)

    2010-01-01

    ... (CONTINUED) FEDERAL SEED ACT FEDERAL SEED ACT REGULATIONS Certified Seed § 201.73 Processors and processing... of certified seed: (a) Facilities shall be available to perform processing without introducing... 7 Agriculture 3 2010-01-01 2010-01-01 false Processors and processing of all classes of certified...

  11. Homogeneity corrections in the Anger camera with micro-Z processor

    International Nuclear Information System (INIS)

    Knoop, B.; Jordan, K.

    1979-01-01

    Series of measurements largely covering the area of clinical use of the Anger camera were carried out to investigate the mode of action of inhomogeneity correction by the micro-Z processor. The variation of boundary conditions of measurements when measuring in patients is simulated as closely as possible by selecting suitable measuring arrangements. The measured results confirm both the concepts outlined above on the causes of inhomogeneity of the Anger camera and the suitability for inhomogeneity correction under clinical conditions of the methods applied in the micro-Z processor. (orig./HP) [de

  12. Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

    Science.gov (United States)

    Downie, John D.

    1990-01-01

    A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.

  13. 21 CFR 864.3875 - Automated tissue processor.

    Science.gov (United States)

    2010-04-01

    ... 21 Food and Drugs 8 2010-04-01 2010-04-01 false Automated tissue processor. 864.3875 Section 864.3875 Food and Drugs FOOD AND DRUG ADMINISTRATION, DEPARTMENT OF HEALTH AND HUMAN SERVICES (CONTINUED) MEDICAL DEVICES HEMATOLOGY AND PATHOLOGY DEVICES Pathology Instrumentation and Accessories § 864.3875...

  14. Interleaved Subtask Scheduling on Multi Processor SOC

    NARCIS (Netherlands)

    Zhe, M.

    2006-01-01

    The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

  15. Operation of the upgraded ATLAS Central Trigger Processor during the LHC Run 2

    DEFF Research Database (Denmark)

    Bertelsen, H.; Montoya, G. Carrillo; Deviveiros, P. O.

    2016-01-01

    The ATLAS Central Trigger Processor (CTP) is responsible for forming the Level-1 trigger decision based on the information from the calorimeter and muon trigger processors. In order to cope with the increase of luminosity and physics cross-sections in Run 2, several components of this system have...

  16. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  17. A VLSI image processor via pseudo-mersenne transforms

    International Nuclear Information System (INIS)

    Sei, W.J.; Jagadeesh, J.M.

    1986-01-01

    The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

  18. The analysis of a large Danish family supports the presence of a susceptibility locus for adenoma and colorectal cancer on chromosome 11q24

    DEFF Research Database (Denmark)

    Rudkjøbing, Laura Aviaja; Eiberg, Hans; Mikkelsen, Hanne Birte

    2015-01-01

    Hereditary colorectal cancer accounts for approximately 30 % of all colorectal cancers, but currently only 5 % of these families can be explained by highly penetrant, inherited mutations. In the remaining 25 % it is not possible to perform a gene test to identify the family members who would...... benefit from prophylactic screening. Consequently, all family members are asked to follow a screening program. The purpose of this study was to localize a new gene which causes colorectal cancer. We performed a linkage analysis using data from a SNP6.0 chip in one large family with 12 affected family...... areas on chromosome 2 and chromosome 11 with the highest possible LOD scores of 2.6. Two other studies have identified 11q24 as a candidate area for colorectal cancer susceptibility and this area is supported by our results....

  19. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    Energy Technology Data Exchange (ETDEWEB)

    Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  20. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    International Nuclear Information System (INIS)

    Barhen, Jacob; Kerekes, Ryan A.; St Charles, Jesse Lee; Buckner, Mark A.

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  1. A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

    Directory of Open Access Journals (Sweden)

    Hiroki Iwaizumi

    2013-01-01

    Full Text Available A processor design for singular value decomposition (SVD and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs and arithmetic instructions specialized in complex matrix operations.

  2. Natrium: Use of FPGA embedded processors for real-time data compression

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

    2011-12-15

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  3. Natrium: Use of FPGA embedded processors for real-time data compression

    International Nuclear Information System (INIS)

    Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

    2011-01-01

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  4. Scalable architecture for a room temperature solid-state quantum information processor.

    Science.gov (United States)

    Yao, N Y; Jiang, L; Gorshkov, A V; Maurer, P C; Giedke, G; Cirac, J I; Lukin, M D

    2012-04-24

    The realization of a scalable quantum information processor has emerged over the past decade as one of the central challenges at the interface of fundamental science and engineering. Here we propose and analyse an architecture for a scalable, solid-state quantum information processor capable of operating at room temperature. Our approach is based on recent experimental advances involving nitrogen-vacancy colour centres in diamond. In particular, we demonstrate that the multiple challenges associated with operation at ambient temperature, individual addressing at the nanoscale, strong qubit coupling, robustness against disorder and low decoherence rates can be simultaneously achieved under realistic, experimentally relevant conditions. The architecture uses a novel approach to quantum information transfer and includes a hierarchy of control at successive length scales. Moreover, it alleviates the stringent constraints currently limiting the realization of scalable quantum processors and will provide fundamental insights into the physics of non-equilibrium many-body quantum systems.

  5. Multi-mode sensor processing on a dynamically reconfigurable massively parallel processor array

    Science.gov (United States)

    Chen, Paul; Butts, Mike; Budlong, Brad; Wasson, Paul

    2008-04-01

    This paper introduces a novel computing architecture that can be reconfigured in real time to adapt on demand to multi-mode sensor platforms' dynamic computational and functional requirements. This 1 teraOPS reconfigurable Massively Parallel Processor Array (MPPA) has 336 32-bit processors. The programmable 32-bit communication fabric provides streamlined inter-processor connections with deterministically high performance. Software programmability, scalability, ease of use, and fast reconfiguration time (ranging from microseconds to milliseconds) are the most significant advantages over FPGAs and DSPs. This paper introduces the MPPA architecture, its programming model, and methods of reconfigurability. An MPPA platform for reconfigurable computing is based on a structural object programming model. Objects are software programs running concurrently on hundreds of 32-bit RISC processors and memories. They exchange data and control through a network of self-synchronizing channels. A common application design pattern on this platform, called a work farm, is a parallel set of worker objects, with one input and one output stream. Statically configured work farms with homogeneous and heterogeneous sets of workers have been used in video compression and decompression, network processing, and graphics applications.

  6. 'Iconic' tracking algorithms for high energy physics using the TRAX-I massively parallel processor

    International Nuclear Information System (INIS)

    Vesztergombi, G.

    1989-01-01

    TRAX-I, a cost-effective parallel microcomputer, applying associative string processor (ASP) architecture with 16 K parallel processing elements, is being built by Aspex Microsystems Ltd. (UK). When applied to the tracking problem of very complex events with several hundred tracks, the large number of processors allows one to dedicate one or more processors to each wire (in MWPC), each pixel (in digitized images from streamer chambers or other visual detectors), or each pad (in TPC) to perform very efficient pattern recognition. Some linear tracking algorithms based on this ''ionic'' representation are presented. (orig.)

  7. 'Iconic' tracking algorithms for high energy physics using the TRAX-I massively parallel processor

    International Nuclear Information System (INIS)

    Vestergombi, G.

    1989-11-01

    TRAX-I, a cost-effective parallel microcomputer, applying Associative String Processor (ASP) architecture with 16 K parallel processing elements, is being built by Aspex Microsystems Ltd. (UK). When applied to the tracking problem of very complex events with several hundred tracks, the large number of processors allows one to dedicate one or more processors to each wire (in MWPC), each pixel (in digitized images from streamer chambers or other visual detectors), or each pad (in TPC) to perform very efficient pattern recognition. Some linear tracking algorithms based on this 'iconic' representation are presented. (orig.)

  8. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  9. Sojourn time asymptotics in processor-sharing queues

    NARCIS (Netherlands)

    Borst, S.C.; Núñez Queija, R.; Zwart, B.

    2006-01-01

    Over the past few decades, the Processor-Sharing (PS) discipline has attracted a great deal of attention in the queueing literature. While the PS paradigm emerged in the sixties as an idealization of round-robin scheduling in time-shared computer systems, it has recently captured renewed interest as

  10. A Real-Time Sound Field Rendering Processor

    Directory of Open Access Journals (Sweden)

    Tan Yiyu

    2017-12-01

    Full Text Available Real-time sound field renderings are computationally intensive and memory-intensive. Traditional rendering systems based on computer simulations suffer from memory bandwidth and arithmetic units. The computation is time-consuming, and the sample rate of the output sound is low because of the long computation time at each time step. In this work, a processor with a hybrid architecture is proposed to speed up computation and improve the sample rate of the output sound, and an interface is developed for system scalability through simply cascading many chips to enlarge the simulated area. To render a three-minute Beethoven wave sound in a small shoe-box room with dimensions of 1.28 m × 1.28 m × 0.64 m, the field programming gate array (FPGA-based prototype machine with the proposed architecture carries out the sound rendering at run-time while the software simulation with the OpenMP parallelization takes about 12.70 min on a personal computer (PC with 32 GB random access memory (RAM and an Intel i7-6800K six-core processor running at 3.4 GHz. The throughput in the software simulation is about 194 M grids/s while it is 51.2 G grids/s in the prototype machine even if the clock frequency of the prototype machine is much lower than that of the PC. The rendering processor with a processing element (PE and interfaces consumes about 238,515 gates after fabricated by the 0.18 µm processing technology from the ROHM semiconductor Co., Ltd. (Kyoto Japan, and the power consumption is about 143.8 mW.

  11. A Time-Composable Operating System for the Patmos Processor

    DEFF Research Database (Denmark)

    Ziccardi, Marco; Schoeberl, Martin; Vardanega, Tullio

    2015-01-01

    -composable operating system, on top of a time-composable processor, facilitates incremental development, which is highly desirable for industry. This paper makes a twofold contribution. First, we present enhancements to the Patmos processor to allow achieving time composability at the operating system level. Second......, we extend an existing time-composable operating system, TiCOS, to make best use of advanced Patmos hardware features in the pursuit of time composability.......In the last couple of decades we have witnessed a steady growth in the complexity and widespread of real-time systems. In order to master the rising complexity in the timing behaviour of those systems, rightful attention has been given to the development of time-predictable computer architectures...

  12. A Geometric Algebra Co-Processor for Color Edge Detection

    Directory of Open Access Journals (Sweden)

    Biswajit Mishra

    2015-01-01

    Full Text Available This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA co-processor implemented on an Application Specific Integrated Circuit (ASIC. GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

  13. The Influence of the Silicon Component in the Paste for Processor Cooling

    Directory of Open Access Journals (Sweden)

    Antun Koren

    2003-12-01

    Full Text Available The development of computer coolers foreseen for the processors keeps step with the processors for PC platform. There are still working and development areas where one could find new technologies and the kinds of the alternative cooling which give better results that the existing classical methods. There are several kinds of alternative cooling, from cooling with the mixture of water and methanol to the usage of freon and liquid nitrogen as the cooling media. The purpose of this work is to point at some new alternative cooling methods and to compare them with the classical ones as well as to stress the problems in classical - mechanically treated cooler and additives of chemically prepared pastes for better heat conductivity from the core surface of the processor.

  14. Supertracker: A Programmable Parallel Pipeline Arithmetic Processor For Auto-Cueing Target Processing

    Science.gov (United States)

    Mack, Harold; Reddi, S. S.

    1980-04-01

    Supertracker represents a programmable parallel pipeline computer architecture that has been designed to meet the real time image processing requirements of auto-cueing target data processing. The prototype bread-board currently under development will be designed to perform input video preprocessing and processing for 525-line and 875-line TV formats FLIR video, automatic display gain and contrast control, and automatic target cueing, classification, and tracking. The video preprocessor is capable of performing operations full frames of video data in real time, e.g., frame integration, storage, 3 x 3 convolution, and neighborhood processing. The processor architecture is being implemented using bit-slice microprogrammable arithmetic processors, operating in parallel. Each processor is capable of up to 20 million operations per second. Multiple frame memories are used for additional flexibility.

  15. The associative memory system for the FTK processor at ATLAS

    CERN Document Server

    Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

    2014-01-01

    In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

  16. Low-Latency Embedded Vision Processor (LLEVS)

    Science.gov (United States)

    2016-03-01

    algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system

  17. 50 CFR 648.6 - Dealer/processor permits.

    Science.gov (United States)

    2010-10-01

    ... of incorporation if the business is a corporation, and a copy of the partnership agreement and the names and addresses of all partners, if the business is a partnership, name of at-sea processor vessel... the fishing year to an applicant, unless the applicant fails to submit a completed application. An...

  18. Event analysis using a massively parallel processor

    International Nuclear Information System (INIS)

    Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.

    1990-01-01

    This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable

  19. Fast Parallel Computation of Polynomials Using Few Processors

    DEFF Research Database (Denmark)

    Valiant, Leslie G.; Skyum, Sven; Berkowitz, S.

    1983-01-01

    It is shown that any multivariate polynomial of degree $d$ that can be computed sequentially in $C$ steps can be computed in parallel in $O((\\log d)(\\log C + \\log d))$ steps using only $(Cd)^{O(1)} $ processors....

  20. Huffman-based code compression techniques for embedded processors

    KAUST Repository

    Bonny, Mohamed Talal; Henkel, Jö rg

    2010-01-01

    % for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.

  1. Efficacy of Code Optimization on Cache-Based Processors

    Science.gov (United States)

    VanderWijngaart, Rob F.; Saphir, William C.; Chancellor, Marisa K. (Technical Monitor)

    1997-01-01

    In this paper a number of techniques for improving the cache performance of a representative piece of numerical software is presented. Target machines are popular processors from several vendors: MIPS R5000 (SGI Indy), MIPS R8000 (SGI PowerChallenge), MIPS R10000 (SGI Origin), DEC Alpha EV4 + EV5 (Cray T3D & T3E), IBM RS6000 (SP Wide-node), Intel PentiumPro (Ames' Whitney), Sun UltraSparc (NERSC's NOW). The optimizations all attempt to increase the locality of memory accesses. But they meet with rather varied and often counterintuitive success on the different computing platforms. We conclude that it may be genuinely impossible to obtain portable performance on the current generation of cache-based machines. At the least, it appears that the performance of modern commodity processors cannot be described with parameters defining the cache alone.

  2. From TEMPO+ to OPUS 2: what can music tests tell us about processor upgrades?

    Science.gov (United States)

    van Besouw, R M; Grasmeder, M L

    2011-08-01

    Tests for quantifying the music perception abilities of cochlear implant users are currently being developed and trialled at the South of England Cochlear Implant Centre. In addition to measures of speech perception, tests of rhythm, and pitch have been administered to MED-EL C40+ implant users before and after upgrading from the TEMPO+ processor with continuous interleaved sampling strategy to the OPUS 2 processor with fine structure processing strategy, with the aims of comparing device performance and evaluating the potential of music perception tests for informing processor upgrades and tuning. Eight experienced adult C40+ implant recipients performed tests of rhythm and pitch discrimination using the TEMPO+ processor and, after a minimum of 6 weeks acclimatization, using the OPUS 2 processor. Stimuli included piano and sine tones in two note ranges for the pitch tasks, and drum beats for the rhythm task. Rhythm, pitch, and speech perception scores were comparable for both processors. An effect of note range was observed (z = -2.52, p = 0.008 (two-tailed), r = -0.63), which indicated that the higher range of notes used for the pitch tasks was easier for participants than the lower range. Measures of pitch discrimination in different frequency ranges further informed changes made to one participant's map, resulting in improved pitch discrimination and speech perception scores. The outcomes of this study demonstrate that music perception tests can provide important additional measures for tuning cochlear implant parameters and assessing the impact of changes to device type and processing strategy.

  3. The hardware implementation of the CERN SPS ultrafast feedback processor demonstrator

    CERN Document Server

    Dusakto, J E; Fox, J D; Olsen, J; Rivetta, C H; Höfle, W

    2013-01-01

    An ultrafast 4GSa/s transverse feedback processor has been developed for proof-of-concept studies of feedback control of e-cloud driven and transverse mode coupled intra-bunch instabilities in the CERN SPS. This system consists of a high-speed ADC on the front end and equally fast DAC on the back end. All control and signal processing is implemented in FPGA logic. This system is capable of taking up to 16 sample slices across a single SPS bunch and processing each slice individually within a reconfigurable signal processor. This demonstrator system is a rapidly developed prototype, consisting of both commercial and custom-design components. It can stabilize the motion of a single particle bunch using closed loop feedback. The system can also run open loop as a high-speed arbitrary waveform generator and contains diagnostic features including a special ADC snapshot capture memory. This paper describes the overall system, the feedback processor and focuses on the hardware architecture, design ...

  4. The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Silverstein, S

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

  5. The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Silverstein, S; The ATLAS collaboration

    2009-01-01

    The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

  6. Methanol fuel processor and PEM fuel cell modeling for mobile application

    Energy Technology Data Exchange (ETDEWEB)

    Chrenko, Daniela [ISAT, University of Burgundy, Rue Mlle Bourgoise, 58000 Nevers (France); Gao, Fei; Blunier, Benjamin; Bouquain, David; Miraoui, Abdellatif [Transport and Systems Laboratory (SeT) - EA 3317/UTBM, Fuel cell Laboratory (FCLAB), University of Technology of Belfort-Montbeliard, Rue Thierry Mieg 90010, Belfort Cedex (France)

    2010-07-15

    The use of hydrocarbon fed fuel cell systems including a fuel processor can be an entry market for this emerging technology avoiding the problem of hydrogen infrastructure. This article presents a 1 kW low temperature PEM fuel cell system with fuel processor, the system is fueled by a mixture of methanol and water that is converted into hydrogen rich gas using a steam reformer. A complete system model including a fluidic fuel processor model containing evaporation, steam reformer, hydrogen filter, combustion, as well as a multi-domain fuel cell model is introduced. Experiments are performed with an IDATECH FCS1200 trademark fuel cell system. The results of modeling and experimentation show good results, namely with regard to fuel cell current and voltage as well as hydrogen production and pressure. The system is auto sufficient and shows an efficiency of 25.12%. The presented work is a step towards a complete system model, needed to develop a well adapted system control assuring optimized system efficiency. (author)

  7. Fast parallel computation of polynomials using few processors

    DEFF Research Database (Denmark)

    Valiant, Leslie; Skyum, Sven

    1981-01-01

    It is shown that any multivariate polynomial that can be computed sequentially in C steps and has degree d can be computed in parallel in 0((log d) (log C + log d)) steps using only (Cd)0(1) processors....

  8. Study of an analog/logic processor for the design of an auto patch hybrid computer

    International Nuclear Information System (INIS)

    Koched, Hassen

    1976-01-01

    This paper presents the experimental study of an analog multiprocessor designed at SES/CEN-Saclay. An application of such a device as a basic component of an auto-patch hybrid computer is presented. First, the description of the processor, and a presentation of the theoretical concepts which governed the design of the processor are given. Experiments on an hybrid computer are then presented. Finally, different systems of automatic patching are presented, and conveniently modified, for the use of such a processor. (author) [fr

  9. SAPIENS: Spreading Activation Processor for Information Encoded in Network Structures. Technical Report No. 296.

    Science.gov (United States)

    Ortony, Andrew; Radin, Dean I.

    The product of researchers' efforts to develop a computer processor which distinguishes between relevant and irrelevant information in the database, Spreading Activation Processor for Information Encoded in Network Structures (SAPIENS) exhibits (1) context sensitivity, (2) efficiency, (3) decreasing activation over time, (4) summation of…

  10. Feasibility analysis of real-time physical modeling using WaveCore processor technology on FPGA

    NARCIS (Netherlands)

    Verstraelen, Martinus Johannes Wilhelmina; Pfeifle, Florian; Bader, Rolf

    2015-01-01

    WaveCore is a scalable many-core processor technology. This technology is specifically developed and optimized for real-time acoustical modeling applications. The programmable WaveCore soft-core processor is silicon-technology independent and hence can be targeted to ASIC or FPGA technologies. The

  11. Assessment of directionality performances: comparison between Freedom and CP810 sound processors.

    Science.gov (United States)

    Razza, Sergio; Albanese, Greta; Ermoli, Lucilla; Zaccone, Monica; Cristofari, Eliana

    2013-10-01

    To compare speech recognition in noise for the Nucleus Freedom and CP810 sound processors using different directional settings among those available in the SmartSound portfolio. Single-subject, repeated measures study. Tertiary care referral center. Thirty-one monoaurally and binaurally implanted subjects (24 children and 7 adults) were enrolled. They were all experienced Nucleus Freedom sound processor users and achieved a 100% open set word recognition score in quiet listening conditions. Each patient was fitted with the Freedom and the CP810 processor. The program setting incorporated Adaptive Dynamic Range Optimization (ADRO) and adopted the directional algorithm BEAM (both devices) and ZOOM (only on CP810). Speech reception threshold (SRT) was assessed in a free-field layout, with disyllabic word list and interfering multilevel babble noise in the 3 different pre-processing configurations. On average, CP810 improved significantly patients' SRTs as compared to Freedom SP after 1 hour of use. Instead, no significant difference was observed in patients' SRT between the BEAM and the ZOOM algorithm fitted in the CP810 processor. The results suggest that hardware developments achieved in the design of CP810 allow an immediate and relevant directional advantage as compared to the previous-generation Freedom device.

  12. Exome sequencing identifies pathogenic variants of VPS13B in a patient with familial 16p11.2 duplication

    OpenAIRE

    Dastan, Jila; Chijiwa, Chieko; Tang, Flamingo; Martell, Sally; Qiao, Ying; Rajcan-Separovic, Evica; Lewis, M. E. Suzanne

    2016-01-01

    Background The recurrent microduplication of 16p11.2 (dup16p11.2) is associated with a broad spectrum of neurodevelopmental disorders (NDD) confounded by incomplete penetrance and variable expressivity. This inter- and intra-familial clinical variability highlights the importance of personalized genetic counselling in individuals at-risk. Case presentation In this study, we performed whole exome sequencing (WES) to look for other genomic alterations that could explain the clinical variability...

  13. In-Network Adaptation of Video Streams Using Network Processors

    Directory of Open Access Journals (Sweden)

    Mohammad Shorfuzzaman

    2009-01-01

    problem can be addressed, near the network edge, by applying dynamic, in-network adaptation (e.g., transcoding of video streams to meet available connection bandwidth, machine characteristics, and client preferences. In this paper, we extrapolate from earlier work of Shorfuzzaman et al. 2006 in which we implemented and assessed an MPEG-1 transcoding system on the Intel IXP1200 network processor to consider the feasibility of in-network transcoding for other video formats and network processor architectures. The use of “on-the-fly” video adaptation near the edge of the network offers the promise of simpler support for a wide range of end devices with different display, and so forth, characteristics that can be used in different types of environments.

  14. Optical chirp z-transform processor with a simplified architecture.

    Science.gov (United States)

    Ngo, Nam Quoc

    2014-12-29

    Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

  15. Lack of GNAQ and GNA11 germ-line mutations in familial melanoma pedigrees with uveal melanoma or blue nevi

    Directory of Open Access Journals (Sweden)

    Jason Ezra Hawkes

    2013-06-01

    Full Text Available Approximately 10% of melanoma cases are familial, but only 25-40% of familial melanoma cases can be attributed to germ-line mutations in the CDKN2A - the most significant high-risk melanoma susceptibility locus identified to date. The pathogenic mutation(s in most of the remaining familial melanoma pedigrees have not yet been identified. The most common mutations in nevi and sporadic melanoma are found in BRAF and NRAS, both of which result in constitutive activation of the MAPK pathway. However, these mutations are not found in uveal melanomas or the intradermal melanocytic proliferations known as blue nevi. Rather, multiple studies report a strong association between these lesions and somatic mutations in Guanine nucleotide-binding protein G(q subunit alpha (GNAQ, Guanine nucleotide-binding protein G(q subunit alpha-11 (GNA11 and BRCA1 associated protein-1 (BAP1. Recently, germ-line mutations in BAP1, the gene encoding a tumor suppressing deubiquitinating enzyme, have been associated with predisposition to a variety of cancers including uveal melanoma, but no studies have examined the association of germ-line mutations in GNAQ and GNA11 with uveal melanoma and blue nevi. We have now done so by sequencing exon 5 of both of these genes in 13 unique familial melanoma pedigrees, members of which have had either uveal or cutaneous melanoma and/or blue nevi. Germ-line DNA from a total of 22 individuals was used for sequencing; however no deleterious mutations were detected. Nevertheless, such candidate gene studies and the discovery of novel germ-line mutations associated with an increased MM susceptibility can lead to a better understanding of the pathways involved in melanocyte transformation, formulation of risk assessment, and the development of specific drug therapies.

  16. Computations on the massively parallel processor at the Goddard Space Flight Center

    Science.gov (United States)

    Strong, James P.

    1991-01-01

    Described are four significant algorithms implemented on the massively parallel processor (MPP) at the Goddard Space Flight Center. Two are in the area of image analysis. Of the other two, one is a mathematical simulation experiment and the other deals with the efficient transfer of data between distantly separated processors in the MPP array. The first algorithm presented is the automatic determination of elevations from stereo pairs. The second algorithm solves mathematical logistic equations capable of producing both ordered and chaotic (or random) solutions. This work can potentially lead to the simulation of artificial life processes. The third algorithm is the automatic segmentation of images into reasonable regions based on some similarity criterion, while the fourth is an implementation of a bitonic sort of data which significantly overcomes the nearest neighbor interconnection constraints on the MPP for transferring data between distant processors.

  17. Power estimation on functional level for programmable processors

    Directory of Open Access Journals (Sweden)

    M. Schneider

    2004-01-01

    Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

  18. Power estimation on functional level for programmable processors

    Science.gov (United States)

    Schneider, M.; Blume, H.; Noll, T. G.

    2004-05-01

    In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input

  19. Study on the management of the Boohung X-Dol 90 developer and fixing solution for automatic X-ray film processor

    International Nuclear Information System (INIS)

    Hyan, Yong Sil; Kim, Heung Tae; Kwon, Dal Gwan; Choi, Myung Joon; Cheung, Hwan

    1986-01-01

    Recently, Demands of Automatic X-ray film Processors are increasing more and more at University Hospitals and general Hospitals and Private clinics, but various troubles because of incorrect control were found out. Authors have researched to find out the function and Activity of Automatic X-ray film processor for 2 weeks Kodak RPX-OMAT Processor and Sakura GX3000 Processor and Doosan parka 2000 Processor and results obtained were as follows: 1. Automatic X-ray film processor have an advantage to conduct the rapid treatment of X-ray film processing but incorrect handling of developing and fixing agents were brought about a great change in Contrast and Optical density of X-ray film pictures. 2. About 300 X-ray film could be finished by same developing and fixing solution without exchanging any other solutions in each Automatic X-ray film processor

  20. Reconfigurable VLIW Processor for Software Defined Radio, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We will design and formally verify a VLIW processor that is radiation-hardened, and where the VLIW instructions consist of predicated RISC instructions from the...