Sampling phase lock loop (PLL) with low power clock buffer

NARCIS (Netherlands)

Gao, X.; Bahai, A.; Bohsali, M.; Djabbari, A.; Klumperink, Eric A.M.; Nauta, Bram; Socci, G.

2013-01-01

A sampling phase locked loop (PLL) circuit includes a pull-up/down buffer configured to convert an oscillator reference clock into a square wave sampling control signal input to a sampling phase detector. The buffer circuit is configured to reduce power by controlling the switching of the pull-up

Low Power LDPC Code Decoder Architecture Based on Intermediate Message Compression Technique

Science.gov (United States)

Shimizu, Kazunori; Togawa, Nozomu; Ikenaga, Takeshi; Goto, Satoshi

Reducing the power dissipation for LDPC code decoder is a major challenging task to apply it to the practical digital communication systems. In this paper, we propose a low power LDPC code decoder architecture based on an intermediate message-compression technique which features as follows: (i) An intermediate message compression technique enables the decoder to reduce the required memory capacity and write power dissipation. (ii) A clock gated shift register based intermediate message memory architecture enables the decoder to decompress the compressed messages in a single clock cycle while reducing the read power dissipation. The combination of the above two techniques enables the decoder to reduce the power dissipation while keeping the decoding throughput. The simulation results show that the proposed architecture improves the power efficiency up to 52% and 18% compared to that of the decoder based on the overlapped schedule and the rapid convergence schedule without the proposed techniques respectively.

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam

2011-12-01

Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

A SCHEDULING SCHEME WITH DYNAMIC FREQUENCY CLOCKING AND MULTIPLE VOLTAGES FOR LOW POWER DESIGNS

Institute of Scientific and Technical Information of China (English)

Wen Dongxin; Wang Ling; Yang Xiaozong

2007-01-01

In this letter, a scheduling scheme based on Dynamic Frequency Clocking (DFC) and multiple voltages is proposed for low power designs under the timing and the resource constraints.Unlike the conventional methods at high level synthesis where only voltages of nodes were considered,the scheme based on a gain function considers both voltage and frequency simultaneously to reduce energy consumption. Experiments with a number of DSP benchmarks show that the proposed scheme achieves an effective energy reduction.

Nine-channel mid-power bipolar pulse generator based on a field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Haylock, Ben, E-mail: benjamin.haylock2@griffithuni.edu.au; Lenzini, Francesco; Kasture, Sachin; Fisher, Paul; Lobino, Mirko [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Queensland Micro and Nanotechnology Centre, Griffith University, Brisbane (Australia); Streed, Erik W. [Centre for Quantum Dynamics, Griffith University, Brisbane (Australia); Institute for Glycomics, Griffith University, Gold Coast (Australia)

2016-05-15

Many channel arbitrary pulse sequence generation is required for the electro-optic reconfiguration of optical waveguide networks in Lithium Niobate. Here we describe a scalable solution to the requirement for mid-power bipolar parallel outputs, based on pulse patterns generated by an externally clocked field programmable gate array. Positive and negative pulses can be generated at repetition rates up to 80 MHz with pulse width adjustable in increments of 1.6 ns across nine independent outputs. Each channel can provide 1.5 W of RF power and can be synchronised with the operation of other components in an optical network such as light sources and detectors through an external clock with adjustable delay.

Design and Analysis of Double-Gate MOSFETs for Ultra-Low Power Radio Frequency Identification (RFID: Device and Circuit Co-Design

Directory of Open Access Journals (Sweden)

Tony T. Kim

2011-07-01

Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.

Design of an ultra-low-power digital processor for passive UHF RFID tags

Energy Technology Data Exchange (ETDEWEB)

Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan, E-mail: wanggen_shi@163.co [Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

2009-04-15

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 mum process of Chartered Semiconductor.

Design of an ultra-low-power digital processor for passive UHF RFID tags

International Nuclear Information System (INIS)

Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan

2009-01-01

A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.

Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

International Nuclear Information System (INIS)

Datta, Deepanjan; Ganguly, Samiran; Dasgupta, S

2007-01-01

Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p + poly-n + poly-p + poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime

Power gating of VLSI circuits using MEMS switches in low power applications

KAUST Repository

Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

2011-01-01

-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

Low band-to-band tunnelling and gate tunnelling current in novel nanoscale double-gate architecture: simulations and investigation

Energy Technology Data Exchange (ETDEWEB)

Datta, Deepanjan [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 (United States); Ganguly, Samiran [Department of Electronics Engineering, Indian School of Mines, Dhanbad-826004 (India); Dasgupta, S [Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee-247667 (India)

2007-05-30

Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p{sup +} poly-n{sup +} poly-p{sup +} poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.

From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits

International Nuclear Information System (INIS)

Register, L.F.; Basu, D.; Reddy, D.

2011-01-01

Colleagues and we recently proposed a new type of transistor, a Bilayer Pseudo Spin Field Effect Transistor (BiSFET), based on many-body coherent states in coupled electron and hole layers in graphene. Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineer able device parameters on the formation and gating of interlayer coherent state.

A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

Directory of Open Access Journals (Sweden)

Daniel Pacheco Bautista

2007-09-01

Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

Discrete Wigner formalism for qubits and noncontextuality of Clifford gates on qubit stabilizer states

Science.gov (United States)

Kocia, Lucas; Love, Peter

2017-12-01

We show that qubit stabilizer states can be represented by non-negative quasiprobability distributions associated with a Wigner-Weyl-Moyal formalism where Clifford gates are positive state-independent maps. This is accomplished by generalizing the Wigner-Weyl-Moyal formalism to three generators instead of two—producing an exterior, or Grassmann, algebra—which results in Clifford group gates for qubits that act as a permutation on the finite Weyl phase space points naturally associated with stabilizer states. As a result, a non-negative probability distribution can be associated with each stabilizer state's three-generator Wigner function, and these distributions evolve deterministically to one another under Clifford gates. This corresponds to a hidden variable theory that is noncontextual and local for qubit Clifford gates while Clifford (Pauli) measurements have a context-dependent representation. Equivalently, we show that qubit Clifford gates can be expressed as propagators within the three-generator Wigner-Weyl-Moyal formalism whose semiclassical expansion is truncated at order ℏ0 with a finite number of terms. The T gate, which extends the Clifford gate set to one capable of universal quantum computation, requires a semiclassical expansion of the propagator to order ℏ1. We compare this approach to previous quasiprobability descriptions of qubits that relied on the two-generator Wigner-Weyl-Moyal formalism and find that the two-generator Weyl symbols of stabilizer states result in a description of evolution under Clifford gates that is state-dependent, in contrast to the three-generator formalism. We have thus extended Wigner non-negative quasiprobability distributions from the odd d -dimensional case to d =2 qubits, which describe the noncontextuality of Clifford gates and contextuality of Pauli measurements on qubit stabilizer states.

System-wide power management control via clock distribution network

Science.gov (United States)

Coteus, Paul W.; Gara, Alan; Gooding, Thomas M.; Haring, Rudolf A.; Kopcsay, Gerard V.; Liebsch, Thomas A.; Reed, Don D.

2015-05-19

An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.

A novel power-efficient high-speed clock management unit using quantum-dot cellular automata

International Nuclear Information System (INIS)

Abutaleb, M. M.

2017-01-01

Quantum-dot cellular automata (QCA) is one of the most attractive alternatives for complementary metal-oxide semiconductor technology. The QCA widely supports a new paradigm in the field of nanotechnology that has the potential for high density, low power, and high speed. The clock manager is an essential building block in the new microwave and radio frequency integrated circuits. This paper describes a novel QCA-based clock management unit (CMU) that provides innovative clocking capabilities. The proposed CMU is achieved by utilizing edge-triggered D-type flip-flops (D-FFs) in the design of frequency synthesizer and phase splitter. Edge-triggered D-FF structures proposed in this paper have the successful QCA implementation and simulation with the least complexity and power dissipation as compared to earlier structures. The frequency synthesizer is used to generate new clock frequencies from the reference clock frequency based on a combination of power-of-two frequency dividers. The phase splitter is integrated with the frequency synthesizer to generate four clock signals that are 90"o out of phase with each other. This paper demonstrates that the proposed QCA CMU structure has a superior performance. Furthermore, the proposed CMU is straightforwardly scalable due to the use of modular component architecture.

A novel power-efficient high-speed clock management unit using quantum-dot cellular automata

Energy Technology Data Exchange (ETDEWEB)

Abutaleb, M. M., E-mail: mustafa-abotaleb@h-eng.helwan.edu.eg [Helwan University, Department of Electronics, Communications and Computer Engineering (Egypt)

2017-04-15

Quantum-dot cellular automata (QCA) is one of the most attractive alternatives for complementary metal-oxide semiconductor technology. The QCA widely supports a new paradigm in the field of nanotechnology that has the potential for high density, low power, and high speed. The clock manager is an essential building block in the new microwave and radio frequency integrated circuits. This paper describes a novel QCA-based clock management unit (CMU) that provides innovative clocking capabilities. The proposed CMU is achieved by utilizing edge-triggered D-type flip-flops (D-FFs) in the design of frequency synthesizer and phase splitter. Edge-triggered D-FF structures proposed in this paper have the successful QCA implementation and simulation with the least complexity and power dissipation as compared to earlier structures. The frequency synthesizer is used to generate new clock frequencies from the reference clock frequency based on a combination of power-of-two frequency dividers. The phase splitter is integrated with the frequency synthesizer to generate four clock signals that are 90{sup o} out of phase with each other. This paper demonstrates that the proposed QCA CMU structure has a superior performance. Furthermore, the proposed CMU is straightforwardly scalable due to the use of modular component architecture.

Clocking In Time to Gate Memory Processes: The Circadian Clock Is Part of the Ins and Outs of Memory

Directory of Open Access Journals (Sweden)

Oliver Rawashdeh

2018-01-01

Full Text Available Learning, memory consolidation, and retrieval are processes known to be modulated by the circadian (circa: about; dies: day system. The circadian regulation of memory performance is evolutionarily conserved, independent of the type and complexity of the learning paradigm tested, and not specific to crepuscular, nocturnal, or diurnal organisms. In mammals, long-term memory (LTM formation is tightly coupled to de novo gene expression of plasticity-related proteins and posttranslational modifications and relies on intact cAMP/protein kinase A (PKA/protein kinase C (PKC/mitogen-activated protein kinase (MAPK/cyclic adenosine monophosphate response element-binding protein (CREB signaling. These memory-essential signaling components cycle rhythmically in the hippocampus across the day and night and are clearly molded by an intricate interplay between the circadian system and memory. Important components of the circadian timing mechanism and its plasticity are members of the Period clock gene family (Per1, Per2. Interestingly, Per1 is rhythmically expressed in mouse hippocampus. Observations suggest important and largely unexplored roles of the clock gene protein PER1 in synaptic plasticity and in the daytime-dependent modulation of learning and memory. Here, we review the latest findings on the role of the clock gene Period 1 (Per1 as a candidate molecular and mechanistic blueprint for gating the daytime dependency of memory processing.

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

International Nuclear Information System (INIS)

Zhuge, Jing; Huang, Ru; Wang, Yangyuan; Verhulst, Anne S; Vandenberghe, William G; Dehaene, Wim; Groeseneken, Guido

2011-01-01

This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In 0.6 Ga 0.4 As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption

All-optical clocked flip-flops and random access memory cells using the nonlinear polarization rotation effect of low-polarization-dependent semiconductor optical amplifiers

Science.gov (United States)

Wang, Yongjun; Liu, Xinyu; Tian, Qinghua; Wang, Lina; Xin, Xiangjun

2018-03-01

Basic configurations of various all-optical clocked flip-flops (FFs) and optical random access memory (RAM) based on the nonlinear polarization rotation (NPR) effect of low-polarization-dependent semiconductor optical amplifiers (SOA) are proposed. As the constituent elements, all-optical logic gates and all-optical SR latches are constructed by taking advantage of the SOA's NPR switch. Different all-optical FFs (AOFFs), including SR-, D-, T-, and JK-types as well as an optical RAM cell were obtained by the combination of the proposed all-optical SR latches and logic gates. The effectiveness of the proposed schemes were verified by simulation results and demonstrated by a D-FF and 1-bit RAM cell experimental system. The proposed all-optical clocked FFs and RAM cell are significant to all-optical signal processing.

Low-power logic computing realized in a single electric-double-layer MoS2 transistor gated with polymer electrolyte

Science.gov (United States)

Guo, Junjie; Xie, Dingdong; Yang, Bingchu; Jiang, Jie

2018-06-01

Due to its mechanical flexibility, large bandgap and carrier mobility, atomically thin molybdenum disulphide (MoS2) has attracted widespread attention. However, it still lacks a facile route to fabricate a low-power high-performance logic gates/circuits before it gets the real application. Herein, we reported a facile and environment-friendly method to establish the low-power logic function in a single MoS2 field-effect transistor (FET) configuration gated with a polymer electrolyte. Such low-power and high-performance MoS2 FET can be implemented by using water-soluble polyvinyl alcohol (PVA) polymer as proton-conducting electric-double-layer (EDL) dielectric layer. It exhibited an ultra-low voltage (1.5 V) and a good performance with a high current on/off ratio (Ion/off) of 1 × 105, a large electron mobility (μ) of 47.5 cm2/V s, and a small subthreshold swing (S) of 0.26 V/dec, respectively. The inverter can be realized by using such a single MoS2 EDL FET with a gain of ∼4 at the operation voltage of only ∼1 V. Most importantly, the neuronal AND logic computing can be also demonstrated by using such a double-lateral-gate single MoS2 EDL transistor. These results show an effective step for future applications of 2D MoS2 FETs for integrated electronic engineering and low-energy environment-friendly green electronics.

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol) for the Gate Insulator of Pentacene-Based Thin-Film Transistors

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Wang, Shea-Jue; Hsia, Mao-Yuan; Lee, Win-Der; Huang, Bohr-Ran

2017-01-01

In this study, a proposed Microwave-Induction Heating (MIH) scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO) metal below the Poly(4-vinylphenol) (PVP) film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit) was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min) and low-power microwave-irradiation (50 W). PMID:28773101

Investigation of Rapid Low-Power Microwave-Induction Heating Scheme on the Cross-Linking Process of the Poly(4-vinylphenol for the Gate Insulator of Pentacene-Based Thin-Film Transistors

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2017-07-01

Full Text Available In this study, a proposed Microwave-Induction Heating (MIH scheme has been systematically studied to acquire suitable MIH parameters including chamber pressure, microwave power and heating time. The proposed MIH means that the thin indium tin oxide (ITO metal below the Poly(4-vinylphenol (PVP film is heated rapidly by microwave irradiation and the heated ITO metal gate can heat the PVP gate insulator, resulting in PVP cross-linking. It is found that the attenuation of the microwave energy decreases with the decreasing chamber pressure. The optimal conditions are a power of 50 W, a heating time of 5 min, and a chamber pressure of 20 mTorr. When suitable MIH parameters were used, the effect of PVP cross-linking and the device performance were similar to those obtained using traditional oven heating, even though the cross-linking time was significantly decreased from 1 h to 5 min. Besides the gate leakage current, the interface trap state density (Nit was also calculated to describe the interface status between the gate insulator and the active layer. The lowest interface trap state density can be found in the device with the PVP gate insulator cross-linked by using the optimal MIH condition. Therefore, it is believed that the MIH scheme is a good candidate to cross-link the PVP gate insulator for organic thin-film transistor applications as a result of its features of rapid heating (5 min and low-power microwave-irradiation (50 W.

Full-asynchronous gigabit-symmetric DPSK downstream and OOK upstream OCDMA-PON with source-free ONUs employing all-optical self-clocked time gate.

Science.gov (United States)

Dai, Bo; Shimizu, Satoshi; Wang, Xu; Wada, Naoya

2012-12-10

We propose an asynchronous gigabit-symmetric optical code division multiplexing access passive optical network (OCDMA-PON) in which optical network units (ONUs) are source-free. In the experiment, we demonstrate a duplex OCDMA system with a 50 km 10 Gbit/s/user 4-user DPSK-OCDMA downlink and a 50 km 10 Gbit/s/user 4-user OOK-OCDMA uplink and error-free duplex transmissions are achieved. Besides, we investigate an all-optical self-clocked time gate, which is used for the signal regeneration of decoded signals and ensures asynchronization in the up/downstream transmissions. Furthermore, we evaluate the power budget of the proposed duplex transmission.

Low Power Digital Clock Design Using LVCMOS Input/Output Standards on 45nm FPGA

DEFF Research Database (Denmark)

Pandey, Sujeet; Mehta, Rishabh; Kalia, Kartik

2016-01-01

metal oxide semiconductor i.e. LVCMOS and 45nm Spartan-6 FPGA family is used for simulation and amount of total power consumed is noted down. There is 90.02%, 98.88%, 99.86% and 100% reduction in the clock when we scale down frequency from 100GHz to 10GHz, 1GHz, 0.1GHz, and 0.01GHz respectively....

Radiation Tolerant Low Power Precision Time Source, Phase I

Data.gov (United States)

National Aeronautics and Space Administration — The availability of small, low power atomic clocks is now a reality for ground-based and airborne navigation systems. Kernco's Low Power Precision Time Source...

Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

Directory of Open Access Journals (Sweden)

Shikha Panwar

2014-01-01

Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

Gate-controlled tunneling of quantum Hall edge states in bilayer graphene

Science.gov (United States)

Zhu, Jun; Li, Jing; Wen, Hua

Controlled tunneling of integer and fractional quantum Hall edge states provides a powerful tool to probe the physics of 1D systems and exotic particle statistics. Experiments in GaAs 2DEGs employ either a quantum point contact or a line junction tunnel barrier. It is generally difficult to independently control the filling factors νL and νR on the two sides of the barrier. Here we show that in bilayer graphene both νL and νR as well as their Landau level structures can be independently controlled using a dual-split-gate structure. In addition, the height of the line-junction tunnel barrier implemented in our experiments is tunable via a 5th gate. By measuring the tunneling resistance across the junction RT we examine the equilibration of the edge states in a variety of νL/νR scenarios and under different barrier heights. Edge states from both sides are fully mixed in the case of a low barrier. As the barrier height increases, we observe plateaus in RT that correspond to sequential complete backscattering of edge states. Gate-controlled manipulation of edge states offers a new angle to the exploration of quantum Hall magnetism and fractional quantum Hall effect in bilayer graphene.

Low-power grating detection system chip for high-speed low-cost length and angle precision measurement

Science.gov (United States)

Hou, Ligang; Luo, Rengui; Wu, Wuchen

2006-11-01

This paper forwards a low power grating detection chip (EYAS) on length and angle precision measurement. Traditional grating detection method, such as resister chain divide or phase locked divide circuit are difficult to design and tune. The need of an additional CPU for control and display makes these methods' implementation more complex and costly. Traditional methods also suffer low sampling speed for the complex divide circuit scheme and CPU software compensation. EYAS is an application specific integrated circuit (ASIC). It integrates micro controller unit (MCU), power management unit (PMU), LCD controller, Keyboard interface, grating detection unit and other peripherals. Working at 10MHz, EYAS can afford 5MHz internal sampling rate and can handle 1.25MHz orthogonal signal from grating sensor. With a simple control interface by keyboard, sensor parameter, data processing and system working mode can be configured. Two LCD controllers can adapt to dot array LCD or segment bit LCD, which comprised output interface. PMU alters system between working and standby mode by clock gating technique to save power. EYAS in test mode (system action are more frequently than real world use) consumes 0.9mw, while 0.2mw in real world use. EYAS achieved the whole grating detection system function, high-speed orthogonal signal handling in a single chip with very low power consumption.

Design of low power common-gate low noise amplifier for 2.4 GHz wireless sensor network applications

International Nuclear Information System (INIS)

Zhang Meng; Li Zhiqun

2012-01-01

This paper presents a differential low power low noise amplifier designed for the wireless sensor network (WSN) in a TSMC 0.18 μm RF CMOS process. A two-stage cross-coupling cascaded common-gate (CG) topology has been designed as the amplifier. The first stage is a capacitive cross-coupling topology. It can reduce the power and noise simultaneously. The second stage is a positive feedback cross-coupling topology, used to set up a negative resistance to enhance the equivalent Q factor of the inductor at the load to improve the gain of the LNA. A differential inductor has been designed as the load to achieve reasonable gain. This inductor has been simulated by the means of momentum electromagnetic simulation in ADS. A 'π' circuit model has been built as the inductor model by iteration in ADS. The inductor has been fabricated separately to verify the model. The LNA has been fabricated and measured. The LNA works well centered at 2.44 GHz. The measured gain S 21 is variable with high gain at 16.8 dB and low gain at 1 dB. The NF (noise figure) at high gain mode is 3.6 dB, the input referenced 1 dB compression point (IP1dB) is about −8 dBm and the IIP3 is 2 dBm at low gain mode. The LNA consumes about 1.2 mA current from 1.8 V power supply.

Gate Drive For High Speed, High Power IGBTs

Energy Technology Data Exchange (ETDEWEB)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; /SLAC

2007-06-18

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3{micro}S with a rate of current rise of more than 10000A/{micro}S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt.

Gate Drive For High Speed, High Power IGBTs

International Nuclear Information System (INIS)

Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; SLAC

2007-01-01

A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3(micro)S with a rate of current rise of more than 10000A/(micro)S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt

Low power fluorine plasma effects on electrical reliability of AlGaN/GaN high electron mobility transistor

International Nuclear Information System (INIS)

Yang Ling; Zhou Xiao-Wei; Ma Xiao-Hua; Lv Ling; Zhang Jin-Cheng; Hao Yue; Cao Yan-Rong

2017-01-01

The new electrical degradation phenomenon of the AlGaN/GaN high electron mobility transistor (HEMT) treated by low power fluorine plasma is discovered. The saturated current, on-resistance, threshold voltage, gate leakage and breakdown voltage show that each experiences a significant change in a short time stress, and then keeps unchangeable. The migration phenomenon of fluorine ions is further validated by the electron redistribution and breakdown voltage enhancement after off-state stress. These results suggest that the low power fluorine implant ion stays in an unstable state. It causes the electrical properties of AlGaN/GaN HEMT to present early degradation. A new migration and degradation mechanism of the low power fluorine implant ion under the off-stress electrical stress is proposed. The low power fluorine ions would drift at the beginning of the off-state stress, and then accumulate between gate and drain nearby the gate side. Due to the strong electronegativity of fluorine, the accumulation of the front fluorine ions would prevent the subsequent fluorine ions from drifting, thereby alleviating further the degradation of AlGaN/GaN HEMT electrical properties. (paper)

Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

Energy Technology Data Exchange (ETDEWEB)

Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

2015-07-28

Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

State memory in solution gated epitaxial graphene

Science.gov (United States)

Butko, A. V.; Butko, V. Y.; Lebedev, S. P.; Lebedev, A. A.; Davydov, V. Y.; Smirnov, A. N.; Eliseyev, I. A.; Dunaevskiy, M. S.; Kumzerov, Y. A.

2018-06-01

We studied electrical transport in transistors fabricated on a surface of high quality epitaxial graphene with density of defects as low as 5·1010 cm-2 and observed quasistatic hysteresis with a time constant in a scale of hours. This constant is in a few orders of magnitude greater than the constant previously reported in CVD graphene. The hysteresis observed here can be described as a shift of ∼+2V of the Dirac point measured during a gate voltage increase from the position of the Dirac point measured during a gate voltage decrease. This hysteresis can be characterized as a nonvolatile quasistatic state memory effect in which the state of the gated graphene is determined by its initial state prior to entering the hysteretic region. Due to this effect the difference in resistance of the gated graphene measured in the hysteretic region at the same applied voltages can be as high as 70%. The observed effect can be explained by assuming that charge carriers in graphene and oppositely charged molecular ions from the solution form quasistable interfacial complexes at the graphene interface. These complexes likely preserve the initial state by preventing charge carriers in graphene from discharging in the hysteretic region.

One-liter Hg ion clock for space and ground applications

Science.gov (United States)

Prestage, John D.; Chung, Sang; Le, Thanh; Beach, Maggie; Maleki, Lute; Tjoelker, Robert L.

2003-01-01

We describe the development of a small Hg ion clock suitable for space use. A small clock occupying 1-2 liters volume and producing stability of 10 to the power negative twelve, divided by square root pi would significantly advance the state of space-qualified atomic clocks. Based on recent measurements, this technology should produce long-term stability as good as 10 to the power negative fifteen.

On Algebraic Study of Type-2 Fuzzy Finite State Automata

Directory of Open Access Journals (Sweden)

Anupam K. Singh

2017-08-01

Full Text Available Theories of fuzzy sets and type-2 fuzzy sets are powerful mathematical tools for modeling various types of uncertainty. In this paper we introduce the concept of type-2 fuzzy finite state automata and discuss the algebraic study of type-2 fuzzy finite state automata, i.e., to introduce the concept of homomorphisms between two type-2 fuzzy finite state automata, to associate a type-2 fuzzy transformation semigroup with a type-2 fuzzy finite state automata. Finally, we discuss several product of type-2 fuzzy finite state automata and shown that these product is a categorical product.

Silicon photonic crystal all-optical logic gates

Energy Technology Data Exchange (ETDEWEB)

Fu, Yulan [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Hu, Xiaoyong, E-mail: xiaoyonghu@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China); Gong, Qihuang, E-mail: qhgong@pku.edu.cn [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

2013-01-03

All-optical logic gates, including OR, XOR, NOT, XNOR, and NAND gates, are realized theoretically in a two-dimensional silicon photonic crystal using the light beam interference effect. The ingenious photonic crystal waveguide component design, the precisely controlled optical path difference, and the elaborate device configuration ensure the simultaneous realization of five types of logic gate with low-power and a contrast ratio between the logic states of “1” and “0” as high as 20 dB. High power is not necessary for operation of these logic gate devices. This offers a simple and effective approach for the realization of integrated all-optical logic devices.

Penn State DOE GATE Program

Energy Technology Data Exchange (ETDEWEB)

Anstrom, Joel

2012-08-31

The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints

Directory of Open Access Journals (Sweden)

Yoni Aizik

2011-01-01

Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.

Finite-State Methodology in Natural Language Processing

Directory of Open Access Journals (Sweden)

Michal Korzycki

2001-01-01

Full Text Available Recent mathematical and algorithmic results in the field of finite-state technology, as well the increase in computing power, have constructed the base for a new approach in natural language processing. However the task of creating an appropriate model that would describe the phenomena of the natural language is still to be achieved. ln this paper I'm presenting some notions related to the finite-state modelling of syntax and morphology.

Multiphase region of helimagnetic superlattices at low temperature in an extended six-state clock model

Science.gov (United States)

Lovelady, D. C.; Harper, H. M.; Brodsky, I. E.; Rabson, D. A.

2006-05-01

The variety of magnetic phases observed in rare-earth heterostructures at low temperatures (Jehan et al 1993 Phys. Rev. B 48 5594-606), such as Ho/Y, may be elucidated by an ANNNI-like model Hamiltonian. In previous work modelling bulk Ho (Seno, Rabson and Yeomans 1993 J. Phys. A: Math. Gen. 26 4887-905), such a Hamiltonian with a one-dimensional parameter space produced a single multiphase point. In contrast, the parameter space of the heterostructure model is three dimensional, and instead of an isolated multiphase point, we find two-dimensional multiphase regions. In an example of Villain's 'order from disorder' (Villain, Bidaux, Carton and Conte 1980 J. Physique 41 1263-72 Pimpinelli, Uimin and Villain 1991 J. Phys.: Condens. Matter 3 4693-719), an infinitesimal temperature breaks the ground-state degeneracy. In first order of a low-temperature expansion, we find that the degeneracy is broken everywhere in a multiphase region except on a line. A segment of the line appears to remain multiphase to all orders in a low-temperature expansion when the number L of magnetic layers between non-magnetic spacers is 4 but not for other values of L. For L = 4, the hierarchy of phases more closely resembles that in the ANNNI model than in the bulk six-state clock model on which the present model is based.

Multiphase region of helimagnetic superlattices at low temperature in an extended six-state clock model

International Nuclear Information System (INIS)

Lovelady, D C; Harper, H M; Brodsky, I E; Rabson, D A

2006-01-01

The variety of magnetic phases observed in rare-earth heterostructures at low temperatures (Jehan et al 1993 Phys. Rev. B 48 5594-606), such as Ho/Y, may be elucidated by an ANNNI-like model Hamiltonian. In previous work modelling bulk Ho (Seno, Rabson and Yeomans 1993 J. Phys. A: Math. Gen. 26 4887-905), such a Hamiltonian with a one-dimensional parameter space produced a single multiphase point. In contrast, the parameter space of the heterostructure model is three dimensional, and instead of an isolated multiphase point, we find two-dimensional multiphase regions. In an example of Villain's 'order from disorder' (Villain, Bidaux, Carton and Conte 1980 J. Physique 41 1263-72; Pimpinelli, Uimin and Villain 1991 J. Phys.: Condens. Matter 3 4693-719), an infinitesimal temperature breaks the ground-state degeneracy. In first order of a low-temperature expansion, we find that the degeneracy is broken everywhere in a multiphase region except on a line. A segment of the line appears to remain multiphase to all orders in a low-temperature expansion when the number L of magnetic layers between non-magnetic spacers is 4 but not for other values of L. For L = 4, the hierarchy of phases more closely resembles that in the ANNNI model than in the bulk six-state clock model on which the present model is based

Evaluation of Anisotropic Biaxial Stress Induced Around Trench Gate of Si Power Transistor Using Water-Immersion Raman Spectroscopy

Science.gov (United States)

Suzuki, Takahiro; Yokogawa, Ryo; Oasa, Kohei; Nishiwaki, Tatsuya; Hamamoto, Takeshi; Ogura, Atsushi

2018-05-01

The trench gate structure is one of the promising techniques to reduce on-state resistance (R on) for silicon power devices, such as insulated gate bipolar transistors and power metal-oxide-semiconductor field-effect transistors. In addition, it has been reported that stress is induced around the trench gate area, modifying the carrier mobilities. We evaluated the one-dimensional distribution and anisotropic biaxial stress by quasi-line excitation and water-immersion Raman spectroscopy, respectively. The results clearly confirmed anisotropic biaxial stress in state-of-the-art silicon power devices. It is theoretically possible to estimate carrier mobility using piezoresistance coefficients and anisotropic biaxial stress. The electron mobility was increased while the hole mobility was decreased or remained almost unchanged in the silicon (Si) power device. The stress significantly modifies the R on of silicon power transistors. Therefore, their performance can be improved using the stress around the trench gate.

Development of insulated gate bipolar transistor-based power ...

Indian Academy of Sciences (India)

[5] S V Nakhe et al, National Laser Symposium, 81–82 (2001). [6] E G Cook et al, 8th IEEE Pulsed Power Conference, June 1991. [7] L Druckmann et al, IEEE Power Modulator Symposium, 213–216 (1992). [8] Hybrid gate drivers and gate drive power supplies, M57962L datasheet from Mitsubishi. Electric Corpn. Pramana ...

A new quantum flux parametron logic gate with large input margin

International Nuclear Information System (INIS)

Hioe, W.; Hosoya, M.; Goto, E.

1991-01-01

This paper reports on the Quantum Flux Parametron (QFP) which is a flux transfer, flux activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device its correct operation may be affected by coupling to other QFPs. The problems include backcoupling from active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which being a linear input logic, has low input margin. A new logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise and reaction hazard are substantially reduced. Moreover, the input have little interaction hence input margin is greatly improved

Ultra-Low Power Consuming Direct Radiation Sensors Based on Floating Gate Structures

Directory of Open Access Journals (Sweden)

Evgeny Pikhay

2017-07-01

Full Text Available In this paper, we report on ultra-low power consuming single poly floating gate direct radiation sensors. The developed devices are intended for total ionizing dose (TID measurements and fabricated in a standard CMOS process flow. Sensor design and operation is discussed in detail. Original array sensors were suggested and fabricated that allowed high statistical significance of the radiation measurements and radiation imaging functions. Single sensors and array sensors were analyzed in combination with the specially developed test structures. This allowed insight into the physics of sensor operations and exclusion of the phenomena related to material degradation under irradiation in the interpretation of the measurement results. Response of the developed sensors to various sources of ionizing radiation (Gamma, X-ray, UV, energetic ions was investigated. The optimal design of sensor for implementation in dosimetry systems was suggested. The roadmap for future improvement of sensor performance is suggested.

Performance of a 229Thorium solid-state nuclear clock

International Nuclear Information System (INIS)

Kazakov, G A; Schreitl, M; Winkler, G; Schumm, T; Litvinov, A N; Romanenko, V I; Yatsenko, L P; Romanenko, A V

2012-01-01

The 7.8 eV nuclear isomer transition in 229 thorium has been suggested as a clock transition in a new type of optical frequency standard. Here we discuss the construction of a ‘solid-state nuclear clock’ from thorium nuclei implanted into single crystals transparent in the vacuum ultraviolet range. We investigate crystal-induced line shifts and broadening effects for the specific system of calcium fluoride. At liquid nitrogen temperatures, the clock performance will be limited by decoherence due to magnetic coupling of the thorium nuclei to neighboring nuclear moments, ruling out the commonly used Rabi or Ramsey interrogation schemes. We propose clock stabilization based on a fluorescence spectroscopy method and present optimized operation parameters. Taking advantage of the large number of quantum oscillators under continuous interrogation, a fractional instability level of 10 −19 might be reached within the solid-state approach. (paper)

Circadian Clock Synchronization of the Cell Cycle in Zebrafish Occurs through a Gating Mechanism Rather Than a Period-phase Locking Process.

Science.gov (United States)

Laranjeiro, Ricardo; Tamai, T Katherine; Letton, William; Hamilton, Noémie; Whitmore, David

2018-04-01

Studies from a number of model systems have shown that the circadian clock controls expression of key cell cycle checkpoints, thus providing permissive or inhibitory windows in which specific cell cycle events can occur. However, a major question remains: Is the clock actually regulating the cell cycle through such a gating mechanism or, alternatively, is there a coupling process that controls the speed of cell cycle progression? Using our light-responsive zebrafish cell lines, we address this issue directly by synchronizing the cell cycle in culture simply by changing the entraining light-dark (LD) cycle in the incubator without the need for pharmacological intervention. Our results show that the cell cycle rapidly reentrains to a shifted LD cycle within 36 h, with changes in p21 expression and subsequent S phase timing occurring within the first few hours of resetting. Reentrainment of mitosis appears to lag S phase resetting by 1 circadian cycle. The range of entrainment of the zebrafish clock to differing LD cycles is large, from 16 to 32 hour periods. We exploited this feature to explore cell cycle entrainment at both the population and single cell levels. At the population level, cell cycle length is shortened or lengthened under corresponding T-cycles, suggesting that a 1:1 coupling mechanism is capable of either speeding up or slowing down the cell cycle. However, analysis at the single cell level reveals that this, in fact, is not true and that a gating mechanism is the fundamental method of timed cell cycle regulation in zebrafish. Cell cycle length at the single cell level is virtually unaltered with varying T-cycles.

Low-Jitter Clock Multiplication: a Comparison between PLLs and DLLs

NARCIS (Netherlands)

van de Beek, R.C.H.; Klumperink, Eric A.M.; Vaucher, Cicero S.; Nauta, Bram

This paper shows that, for a given power budget, a practical phase-locked loop (PLL)-based clock multiplier generates less jitter than a delay-locked loop (DLL) equivalent. This is due to the fact that the delay cells in a PLL ring-oscillator can consume more power per cell than their counterparts

On-state voltage drop based power limit detection of IGBT inverters

DEFF Research Database (Denmark)

Trintis, Ionut; Ghimire, Pramod; Munk-Nielsen, Stig

2015-01-01

Power density is a key performance factor in order to reduce the cost and size of a power converter. Because of the unknown junction temperature, today’s design margins are relatively high to ensure safe and a reliable operation. In this paper, the on-state voltage drop is measured online for all...... insulated gate bipolar transistors (IGBTs) in the inverter, using advanced gate driver. The die temperature is estimated and monitored on each device during power converter operation. Based on the monitored temperature in real time, the maximum power capability is detected. The output power is increased...... until a safe operating temperature of power modules. This enable a power density is increased by 11.16 kW/litre to 19.13 kW/litre in a low voltage power stack which is typically used in wind power converters. Experiment results are shown for safe operation of converter at around 1.2 MW, which is built...

Gate errors in solid-state quantum-computer architectures

International Nuclear Information System (INIS)

Hu Xuedong; Das Sarma, S.

2002-01-01

We theoretically consider possible errors in solid-state quantum computation due to the interplay of the complex solid-state environment and gate imperfections. In particular, we study two examples of gate operations in the opposite ends of the gate speed spectrum, an adiabatic gate operation in electron-spin-based quantum dot quantum computation and a sudden gate operation in Cooper-pair-box superconducting quantum computation. We evaluate quantitatively the nonadiabatic operation of a two-qubit gate in a two-electron double quantum dot. We also analyze the nonsudden pulse gate in a Cooper-pair-box-based quantum-computer model. In both cases our numerical results show strong influences of the higher excited states of the system on the gate operation, clearly demonstrating the importance of a detailed understanding of the relevant Hilbert-space structure on the quantum-computer operations

Circadian clocks, epigenetics, and cancer

KAUST Repository

Masri, Selma; Kinouchi, Kenichiro; Sassone-Corsi, Paolo

2015-01-01

The interplay between circadian rhythm and cancer has been suggested for more than a decade based on the observations that shift work and cancer incidence are linked. Accumulating evidence implicates the circadian clock in cancer survival and proliferation pathways. At the molecular level, multiple control mechanisms have been proposed to link circadian transcription and cell-cycle control to tumorigenesis.The circadian gating of the cell cycle and subsequent control of cell proliferation is an area of active investigation. Moreover, the circadian clock is a transcriptional system that is intricately regulated at the epigenetic level. Interestingly, the epigenetic landscape at the level of histone modifications, DNA methylation, and small regulatory RNAs are differentially controlled in cancer cells. This concept raises the possibility that epigenetic control is a common thread linking the clock with cancer, though little scientific evidence is known to date.This review focuses on the link between circadian clock and cancer, and speculates on the possible connections at the epigenetic level that could further link the circadian clock to tumor initiation or progression.

Design of Low Inductance Switching Power Cell for GaN HEMT Based Inverter

Energy Technology Data Exchange (ETDEWEB)

Gurpinar, Emre [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States). Power Electronics and Electric Machinery Research Group; Iannuzzo, Francesco [Aalborg Univ., Aalborg (Denmark). Dept. of Energy Technology; Yang, Yongheng [Aalborg Univ., Aalborg (Denmark). Dept. of Energy Technology; Castellazzi, Alberto [Univ. of Nottingham (United Kingdom). Power Electronics, Machines and Control (PEMC); Blaabjerg, Frede [Aalborg Univ., Aalborg (Denmark). Dept. of Energy Technology

2017-11-23

Here in this paper, an ultra-low inductance power cell is designed for a three-Level Active Neutral Point Clamped (3LANPC) based on 650 V gallium nitride (GaN) HEMT devices. The 3L-ANPC topology with GaN HEMT devices and the selected modulation scheme suitable for wide-bandgap (WBG) devices are presented. The commutation loops, which mainly contribute to voltage overshoots and increase of switching losses, are discussed. The ultra-low inductance power cell design based on a fourlayer Printed Circuit Board (PCB) with the aim to maximize the switching performance of GaN HEMTs is explained. The design of gate drivers for the GaN HEMT devices is presented. Parasitic inductance and resistance of the proposed design are extracted with finite element analysis and discussed. Common mode behaviours based on the SPICE model of the converter are analyzed. Experimental results on the designed 3L-ANPC with the output power of up to 1 kW are presented, which verifies the performance of the proposed design in terms of ultra-low inductance.

Design of Low Inductance Switching Power Cell for GaN HEMT Based Inverter

International Nuclear Information System (INIS)

Gurpinar, Emre; Iannuzzo, Francesco; Yang, Yongheng; Castellazzi, Alberto; Blaabjerg, Frede

2017-01-01

Here in this paper, an ultra-low inductance power cell is designed for a three-Level Active Neutral Point Clamped (3LANPC) based on 650 V gallium nitride (GaN) HEMT devices. The 3L-ANPC topology with GaN HEMT devices and the selected modulation scheme suitable for wide-bandgap (WBG) devices are presented. The commutation loops, which mainly contribute to voltage overshoots and increase of switching losses, are discussed. The ultra-low inductance power cell design based on a fourlayer Printed Circuit Board (PCB) with the aim to maximize the switching performance of GaN HEMTs is explained. The design of gate drivers for the GaN HEMT devices is presented. Parasitic inductance and resistance of the proposed design are extracted with finite element analysis and discussed. Common mode behaviours based on the SPICE model of the converter are analyzed. Experimental results on the designed 3L-ANPC with the output power of up to 1 kW are presented, which verifies the performance of the proposed design in terms of ultra-low inductance.

Nuclear collective states at finite temperature

International Nuclear Information System (INIS)

Milian, A.; Barranco, M.; Mas, D.; Lombard, R.J.

1987-04-01

The Energy Density Method (EDM) has been used to study low-lying nuclear collective states as well as isoscalar giant resonances at finite temperature (T). Giant states have been studied by computing the corresponding strength function moments (sum rules) in the Random-Phase Approximation (RPA). For the description of the low lying states we have resorted to a variety of models from the rather sophisticated RPA method to liquid drop and schematic models. It has been found that low lying states are most affected by thermal effects, giant resonances being little affected in the range of temperatures here studied

Design Principles of A Sigma-delta Flux-gate Magnetometer

Science.gov (United States)

Magnes, W.; Valavanoglou, A.; Pierce, D.; Frank, A.; Schwingenschuh, K.

A state-of-the-art flux-gate magnetometer is characterised by magnetic field resolution of several pT in a wide frequency range, low power consumption, low weight and high robustness. Therefore, flux-gate magnetometers are frequently used for ground-based Earth's field observation as well as for measurements aboard scientific space missions. But both traditional analogue and recently developed digital flux-gate magnetometers need low power and high-resolution analogue-to-digital converters for signal quan- tization. The disadvantage of such converters is the low radiation hardness. This fact has led to the idea of combining a traditional analogue flux-gate regulation circuit with that of a discretely realized sigma-delta converter in order to get a radiation hard and further miniaturized magnetometer. The name sigma-delta converter is derived from putting an integrator in front of a 1-bit delta modulator which forms the sigma-delta loop. It is followed by a digital decimation filter realized in a field-programmable gate array (FPGA). The flux-gate regulation and the sigma-delta loop are quite similar in the way of realizing the integrator and feedback circuit, which makes it easy to com- bine these two systems. The presented talk deals with the design principles and the results of a first bread board model.

Logic synthesis for FPGA-based finite state machines

CERN Document Server

Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

2016-01-01

This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

dRail: a novel physical layout methodology for power gated circuits

OpenAIRE

Mistry, Jatin N.; Biggs, John; Myers, James; Al-Hashimi, Bashir M.; Flynn, David

2012-01-01

In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 proces...

Redox and the circadian clock in plant immunity: A balancing act.

Science.gov (United States)

Karapetyan, Sargis; Dong, Xinnian

2018-05-01

Plants' reliance on sunlight for energy makes their light-driven circadian clock a critical regulator in balancing the energy needs for vital activities such as growth and defense. Recent studies show that the circadian clock acts as a strategic planner to prime active defense responses towards the morning or daytime when conditions, such as the opening of stomata required for photosynthesis, are favorable for attackers. Execution of the defense response, on the other hand, is determined according to the cellular redox state and is regulated in part by the production of reactive oxygen and nitrogen species upon pathogen challenge. The interplay between redox and the circadian clock further gates the onset of defense response to a specific time of the day to avoid conflict with growth-related activities. In this review, we focus on discussing the roles of the circadian clock as a robust overseer and the cellular redox as a dynamic executor of plant defense. Copyright © 2017 The Authors. Published by Elsevier Inc. All rights reserved.

Design of Low Inductance Switching Power Cell for GaN HEMT Based Inverter

DEFF Research Database (Denmark)

Gurpinar, Emre; Iannuzzo, Francesco; Yang, Yongheng

2018-01-01

. The design of gate drivers for the GaN HEMT devices is presented. Parasitic inductance and resistance of the proposed design are extracted with finite element analysis and discussed. Common-mode behaviours based on the SPICE model of the converter are analyzed. Experimental results on the designed 3L......In this paper, an ultra-low inductance power cell is designed for a three-Level Active Neutral Point Clamped (3LANPC) based on 650 V gallium nitride (GaN) HEMT devices. The 3L-ANPC topology with GaN HEMT devices and the selected modulation scheme suitable for wide-bandgap (WBG) devices...... are presented. The commutation loops, which mainly contribute to voltage overshoots and increase of switching losses, are discussed. The ultra-low inductance power cell design based on a four-layer Printed Circuit Board (PCB) with the aim to maximize the switching performance of GaN HEMTs is explained...

Ultra low power full adder topologies

DEFF Research Database (Denmark)

Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the pr...... the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations....

Serializing off-the-shelf MOSFETs by Magnetically Coupling Their Gate Electrodes

DEFF Research Database (Denmark)

Dimopoulos, Emmanouil; Munk-Nielsen, Stig

2013-01-01

While the semiconductor industry struggles with the inherent trade-offs of solid-state devices, serialization of power switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), has been proven to be an advantageous alternative...... to acquire a high-efficient, high-voltage, fast-switching device. More than twenty years of research, on the serialization of solid-state devices, have resulted into several different stacking concepts. Among the prevailing ones, the gate balancing core technique, which has demonstrated very good performance...... in strings of high-power IGBT modules. In this paper, the limitations of the gate balancing core technique, when employed to serialize low or medium power off-the-shelf switches, are identified via experimental results. A new design specification for the interwinding capacitance of the employed transformer...

Logic reversibility and thermodynamic irreversibility demonstrated by DNAzyme-based Toffoli and Fredkin logic gates.

Science.gov (United States)

Orbach, Ron; Remacle, Françoise; Levine, R D; Willner, Itamar

2012-12-26

The Toffoli and Fredkin gates were suggested as a means to exhibit logic reversibility and thereby reduce energy dissipation associated with logic operations in dense computing circuits. We present a construction of the logically reversible Toffoli and Fredkin gates by implementing a library of predesigned Mg(2+)-dependent DNAzymes and their respective substrates. Although the logical reversibility, for which each set of inputs uniquely correlates to a set of outputs, is demonstrated, the systems manifest thermodynamic irreversibility originating from two quite distinct and nonrelated phenomena. (i) The physical readout of the gates is by fluorescence that depletes the population of the final state of the machine. This irreversible, heat-releasing process is needed for the generation of the output. (ii) The DNAzyme-powered logic gates are made to operate at a finite rate by invoking downhill energy-releasing processes. Even though the three bits of Toffoli's and Fredkin's logically reversible gates manifest thermodynamic irreversibility, we suggest that these gates could have important practical implication in future nanomedicine.

The Challenges of Implementing Fine-Grained Power Gating

NARCIS (Netherlands)

Niedermeier, A.; Svarstad, Kjetil; Bouwens, Frank; Hulzink, Jos; Huisken, Jos

2010-01-01

Power consumption in digital systems, especially in portable devices, is a crucial design factor. Due to downscaling of technology, dynamic switching power is not the only relevant source of power consumption anymore as power dissipation caused by leakage currents increases. Even though power gating

Analyzing Single-Event Gate Ruptures In Power MOSFET's

Science.gov (United States)

Zoutendyk, John A.

1993-01-01

Susceptibilities of power metal-oxide/semiconductor field-effect transistors (MOSFET's) to single-event gate ruptures analyzed by exposing devices to beams of energetic bromine ions while applying appropriate bias voltages to source, gate, and drain terminals and measuring current flowing into or out of each terminal.

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

Science.gov (United States)

Kimura, Keiji; Mase, Masayoshi; Mikami, Hiroki; Miyamoto, Takamichi; Shirako, Jun; Kasahara, Hironori

OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory; data transfer using a DMA controller; and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API

Heavy-ion-induced, gate-rupture in power MOSFETs

International Nuclear Information System (INIS)

Fischer, T.A.

1987-01-01

A new, heavy-ion-induced, burnout mechanism has been experimentally observed in power metal-oxide-semiconductor field-effect transistors (MOSFETs). This mechanism occurs when a heavy, charged particle passes through the gate oxide region of n- or p-channel devices having sufficient gate-to-source or gate-to-drain bias. The gate-rupture leads to significant permanent degradation of the device. A proposed failure mechanism is discussed and experimentally verified. In addition, the absolute immunity of p-channel devices to heavy-ion-induced, semiconductor burnout is demonstrated and discussed along with new, non-destructive, burnout testing methods

An optical fusion gate for W-states

Science.gov (United States)

Özdemir, Ş. K.; Matsunaga, E.; Tashima, T.; Yamamoto, T.; Koashi, M.; Imoto, N.

2011-10-01

We introduce a simple optical gate to fuse arbitrary-size polarization entangled W-states to prepare larger W-states. The gate requires a polarizing beam splitter (PBS), a half-wave plate (HWP) and two photon detectors. We study, numerically and analytically, the necessary resource consumption for preparing larger W-states by fusing smaller ones with the proposed fusion gate. We show analytically that resource requirement scales at most sub-exponentially with the increasing size of the state to be prepared. We numerically determine the resource cost for fusion without recycling where W-states of arbitrary size can be optimally prepared. Moreover, we introduce another strategy that is based on recycling and outperforms the optimal strategy for the non-recycling case.

An optical fusion gate for W-states

Energy Technology Data Exchange (ETDEWEB)

Oezdemir, S K [Department of Electrical and Systems Engineering, Washington University, St. Louis, MO 63130 (United States); Matsunaga, E; Tashima, T; Yamamoto, T; Koashi, M; Imoto, N, E-mail: ozdemir@ese.wustl.edu [Graduate School of Engineering Science, Osaka University, Toyonaka, Osaka 560-8531 (Japan)

2011-10-15

We introduce a simple optical gate to fuse arbitrary-size polarization entangled W-states to prepare larger W-states. The gate requires a polarizing beam splitter (PBS), a half-wave plate (HWP) and two photon detectors. We study, numerically and analytically, the necessary resource consumption for preparing larger W-states by fusing smaller ones with the proposed fusion gate. We show analytically that resource requirement scales at most sub-exponentially with the increasing size of the state to be prepared. We numerically determine the resource cost for fusion without recycling where W-states of arbitrary size can be optimally prepared. Moreover, we introduce another strategy that is based on recycling and outperforms the optimal strategy for the non-recycling case. (paper)

An optical fusion gate for W-states

International Nuclear Information System (INIS)

Oezdemir, S K; Matsunaga, E; Tashima, T; Yamamoto, T; Koashi, M; Imoto, N

2011-01-01

We introduce a simple optical gate to fuse arbitrary-size polarization entangled W-states to prepare larger W-states. The gate requires a polarizing beam splitter (PBS), a half-wave plate (HWP) and two photon detectors. We study, numerically and analytically, the necessary resource consumption for preparing larger W-states by fusing smaller ones with the proposed fusion gate. We show analytically that resource requirement scales at most sub-exponentially with the increasing size of the state to be prepared. We numerically determine the resource cost for fusion without recycling where W-states of arbitrary size can be optimally prepared. Moreover, we introduce another strategy that is based on recycling and outperforms the optimal strategy for the non-recycling case. (paper)

Z n clock models and chains of so(n)2 non-Abelian anyons: symmetries, integrable points and low energy properties

Science.gov (United States)

Finch, Peter E.; Flohr, Michael; Frahm, Holger

2018-02-01

We study two families of quantum models which have been used previously to investigate the effect of topological symmetries in one-dimensional correlated matter. Various striking similarities are observed between certain {Z}n quantum clock models, spin chains generalizing the Ising model, and chains of non-Abelian anyons constructed from the so(n)2 fusion category for odd n, both subject to periodic boundary conditions. In spite of the differences between these two types of quantum chains, e.g. their Hilbert spaces being spanned by tensor products of local spin states or fusion paths of anyons, the symmetries of the lattice models are shown to be closely related. Furthermore, under a suitable mapping between the parameters describing the interaction between spins and anyons the respective Hamiltonians share part of their energy spectrum (although their degeneracies may differ). This spin-anyon correspondence can be extended by fine-tuning of the coupling constants leading to exactly solvable models. We show that the algebraic structures underlying the integrability of the clock models and the anyon chain are the same. For n  =  3,5,7 we perform an extensive finite size study—both numerical and based on the exact solution—of these models to map out their ground state phase diagram and to identify the effective field theories describing their low energy behaviour. We observe that the continuum limit at the integrable points can be described by rational conformal field theories with extended symmetry algebras which can be related to the discrete ones of the lattice models.

A Low-Power All-Digital on-Chip CMOS Oscillator for a Wireless Sensor Node.

Science.gov (United States)

Sheng, Duo; Hong, Min-Rong

2016-10-14

This paper presents an all-digital low-power oscillator for reference clocks in wireless body area network (WBAN) applications. The proposed on-chip complementary metal-oxide-semiconductor (CMOS) oscillator provides low-frequency clock signals with low power consumption, high delay resolution, and low circuit complexity. The cascade-stage structure of the proposed design simultaneously achieves high resolution and a wide frequency range. The proposed hysteresis delay cell further reduces the power consumption and hardware costs by 92.4% and 70.4%, respectively, relative to conventional designs. The proposed design is implemented in a standard performance 0.18 μm CMOS process. The measured operational frequency ranged from 7 to 155 MHz, and the power consumption was improved to 79.6 μW (@7 MHz) with a 4.6 ps resolution. The proposed design can be implemented in an all-digital manner, which is highly desirable for system-level integration.

Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy

International Nuclear Information System (INIS)

Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki

2011-01-01

Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

International Nuclear Information System (INIS)

Klymenko, M. V.; Klein, M.; Levine, R. D.; Remacle, F.

2016-01-01

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states corresponds to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.

Operation of a quantum dot in the finite-state machine mode: Single-electron dynamic memory

Energy Technology Data Exchange (ETDEWEB)

Klymenko, M. V. [Department of Chemistry, University of Liège, B4000 Liège (Belgium); Klein, M. [The Fritz Haber Center for Molecular Dynamics and the Institute of Chemistry, The Hebrew University of Jerusalem, Jerusalem 91904 (Israel); Levine, R. D. [The Fritz Haber Center for Molecular Dynamics and the Institute of Chemistry, The Hebrew University of Jerusalem, Jerusalem 91904 (Israel); Crump Institute for Molecular Imaging and Department of Molecular and Medical Pharmacology, David Geffen School of Medicine and Department of Chemistry and Biochemistry, University of California, Los Angeles, California 90095 (United States); Remacle, F., E-mail: fremacle@ulg.ac.be [Department of Chemistry, University of Liège, B4000 Liège (Belgium); The Fritz Haber Center for Molecular Dynamics and the Institute of Chemistry, The Hebrew University of Jerusalem, Jerusalem 91904 (Israel)

2016-07-14

A single electron dynamic memory is designed based on the non-equilibrium dynamics of charge states in electrostatically defined metallic quantum dots. Using the orthodox theory for computing the transfer rates and a master equation, we model the dynamical response of devices consisting of a charge sensor coupled to either a single and or a double quantum dot subjected to a pulsed gate voltage. We show that transition rates between charge states in metallic quantum dots are characterized by an asymmetry that can be controlled by the gate voltage. This effect is more pronounced when the switching between charge states corresponds to a Markovian process involving electron transport through a chain of several quantum dots. By simulating the dynamics of electron transport we demonstrate that the quantum box operates as a finite-state machine that can be addressed by choosing suitable shapes and switching rates of the gate pulses. We further show that writing times in the ns range and retention memory times six orders of magnitude longer, in the ms range, can be achieved on the double quantum dot system using experimentally feasible parameters, thereby demonstrating that the device can operate as a dynamic single electron memory.

A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.

Science.gov (United States)

Jafari, Ali; Buswell, Nathanael; Ghovanloo, Maysam; Mohsenin, Tinoosh

2018-02-01

This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10 lower than FPGA power consumption and occupies an area of only 0.016 mm.

Synthesis of energy-efficient FSMs implemented in PLD circuits

Science.gov (United States)

Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz

2017-11-01

The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.

Proposal of unilateral single-flux-quantum logic gate

International Nuclear Information System (INIS)

Mikaye, H.; Fukaya, N.; Okabe, Y.; Sugamo, T.

1985-01-01

A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible

A probabilistic CNOT gate for coherent state qubits

International Nuclear Information System (INIS)

Oliveira, M.S.R.; Vasconcelos, H.M.; Silva, J.B.R.

2013-01-01

We propose a scheme for implementing a probabilistic controlled-NOT (CNOT) gate for coherent state qubits using only linear optics and a particular four-mode state. The proposed optical setup works, as a CNOT gate, near-faithful when |α| 2 ⩾25 and independent of the input state. The key element for realizing the proposed CNOT scheme is the entangled four-mode state.

A low-power high-flow shape memory alloy wire gas microvalve

International Nuclear Information System (INIS)

Gradin, Henrik; Braun, Stefan; Stemme, Göran; Van der Wijngaart, Wouter; Clausi, Donato; Peirs, Jan; Reynaerts, Dominiek

2012-01-01

In this paper the use of shape memory alloy (SMA) wire actuators for high gas flow control is investigated. A theoretical model for effective gas flow control is presented and gate microvalve prototypes are fabricated. The SMA wire actuator demonstrates the robust flow control of more than 1600 sccm at a pressure drop of 200 kPa. The valve can be successfully switched at over 10 Hz and at an actuation power of 90 mW. Compared to the current state-of-the-art high-flow microvalves, the proposed solution benefits from a low-voltage actuator with low overall power consumption. This paper demonstrate that SMA wire actuators are well suited for high-pressurehigh-flow applications. (paper)

Cellular Clocks : Coupled Circadian Dispatch and Cell Division Cycles

NARCIS (Netherlands)

Merrow, Martha; Roenneberg, Till

2004-01-01

Gating of cell division by the circadian clock is well known, yet its mechanism is little understood. Genetically tractable model systems have led to new hypotheses and questions concerning the coupling of these two cellular cycles.

A probabilistic CNOT gate for coherent state qubits

Energy Technology Data Exchange (ETDEWEB)

Oliveira, M.S.R.; Vasconcelos, H.M.; Silva, J.B.R., E-mail: joaobrs@ufc.br

2013-11-22

We propose a scheme for implementing a probabilistic controlled-NOT (CNOT) gate for coherent state qubits using only linear optics and a particular four-mode state. The proposed optical setup works, as a CNOT gate, near-faithful when |α|{sup 2}⩾25 and independent of the input state. The key element for realizing the proposed CNOT scheme is the entangled four-mode state.

Teleportation-based Toffoli gate on cluster states via the Bell state analysis

International Nuclear Information System (INIS)

Guo Ying; Huang Dazu; Lee, Moon Ho

2013-01-01

An optical Toffoli gate is demonstrated via teleportations on the six-qubit entangling cluster state generated from single-qubit photons. It is implemented on the basis of entanglement swapping of the combined quantum system with three independent Bell state measurements. The output of this gate is then restored by suitable local operations and classical communications. We evaluate the implementing performance of the Toffoli gate fidelity for the operation process in different computational bases. (paper)

A gate enhanced power U-shaped MOSFET integrated with a Schottky rectifier

International Nuclear Information System (INIS)

Wang Ying; Jiao Wen-Li; Hu Hai-Fan; Liu Yun-Tao; Cao Fei

2012-01-01

An accumulation gate enhanced power U-shaped metal-oxide-semiconductor field-effect-transistor (UMOSFET) integrated with a Schottky rectifier is proposed. In this device, a Schottky rectifier is integrated into each cell of the accumulation gate enhanced power UMOSFET. Specific on-resistances of 7.7 mΩ·mm 2 and 6.5 mΩ·mm 2 for the gate bias voltages of 5 V and 10 V are achieved, respectively, and the breakdown voltage is 61 V. The numerical simulation shows a 25% reduction in the reverse recovery time and about three orders of magnitude reduction in the leakage current as compared with the accumulation gate enhanced power UMOSFET. (condensed matter: structural, mechanical, and thermal properties)

Less-Conventional Low-Consumption Galvanic Separated MOSFET-IGBT Gate Drive Supply

Directory of Open Access Journals (Sweden)

Jean Marie Vianney Bikorimana

2017-01-01

Full Text Available A simple half-bridge, galvanic separated power supply which can be short circuit proof is proposed for gate driver local supplies. The supply is made while hacking a common mode type filter as a transformer, as the transformer shows a good insulation, it has a very low parasitic capacitance between primary and secondary coils, and it is cost-effective. Very low standby losses were observed during lab experiments. This makes it compatible with energy efficient drives and solar inverters.

Controlled phase gate for solid-state charge-qubit architectures

International Nuclear Information System (INIS)

Schirmer, S.G.; Oi, D.K.L.; Greentree, Andrew D.

2005-01-01

We describe a mechanism for realizing a controlled phase gate for solid-state charge qubits. By augmenting the positionally defined qubit with an auxiliary state, and changing the charge distribution in the three-dot system, we are able to effectively switch the Coulombic interaction, effecting an entangling gate. We consider two architectures, and numerically investigate their robustness to gate noise

Buckling Transitions and Clock Order of Two-Dimensional Coulomb Crystals

Directory of Open Access Journals (Sweden)

Daniel Podolsky

2016-08-01

Full Text Available Crystals of repulsively interacting ions in planar traps form hexagonal lattices, which undergo a buckling instability towards a multilayer structure as the transverse trap frequency is reduced. Numerical and experimental results indicate that the new structure is composed of three planes, whose separation increases continuously from zero. We study the effects of thermal and quantum fluctuations by mapping this structural instability to the six-state clock model. A prominent implication of this mapping is that at finite temperature, fluctuations split the buckling instability into two thermal transitions, accompanied by the appearance of an intermediate critical phase. This phase is characterized by quasi-long-range order in the spatial tripartite pattern. It is manifested by broadened Bragg peaks at new wave vectors, whose line shape provides a direct measurement of the temperature-dependent exponent η(T characteristic of the power-law correlations in the critical phase. A quantum phase transition is found at the largest value of the critical transverse frequency: Here, the critical intermediate phase shrinks to zero. Moreover, within the ordered phase, we predict a crossover from classical to quantum behavior, signifying the emergence of an additional characteristic scale for clock order. We discuss experimental realizations with trapped ions and polarized dipolar gases, and propose that within accessible technology, such experiments can provide a direct probe of the rich phase diagram of the quantum clock model, not easily observable in condensed matter analogues. Therefore, this work highlights the potential for ionic and dipolar systems to serve as simulators for complex models in statistical mechanics and condensed matter physics.

State Space Methods for Timed Petri Nets

DEFF Research Database (Denmark)

Christensen, Søren; Jensen, Kurt; Mailund, Thomas

2001-01-01

it possible to condense the usually infinite state space of a timed Petri net into a finite condensed state space without loosing analysis power. The second method supports on-the-fly verification of certain safety properties of timed systems. We discuss the application of the two methods in a number......We present two recently developed state space methods for timed Petri nets. The two methods reconciles state space methods and time concepts based on the introduction of a global clock and associating time stamps to tokens. The first method is based on an equivalence relation on states which makes...

NONO couples the circadian clock to the cell cycle.

Science.gov (United States)

Kowalska, Elzbieta; Ripperger, Juergen A; Hoegger, Dominik C; Bruegger, Pascal; Buch, Thorsten; Birchler, Thomas; Mueller, Anke; Albrecht, Urs; Contaldo, Claudio; Brown, Steven A

2013-01-29

Mammalian circadian clocks restrict cell proliferation to defined time windows, but the mechanism and consequences of this interrelationship are not fully understood. Previously we identified the multifunctional nuclear protein NONO as a partner of circadian PERIOD (PER) proteins. Here we show that it also conveys circadian gating to the cell cycle, a connection surprisingly important for wound healing in mice. Specifically, although fibroblasts from NONO-deficient mice showed approximately normal circadian cycles, they displayed elevated cell doubling and lower cellular senescence. At a molecular level, NONO bound to the p16-Ink4A cell cycle checkpoint gene and potentiated its circadian activation in a PER protein-dependent fashion. Loss of either NONO or PER abolished this activation and circadian expression of p16-Ink4A and eliminated circadian cell cycle gating. In vivo, lack of NONO resulted in defective wound repair. Because wound healing defects were also seen in multiple circadian clock-deficient mouse lines, our results therefore suggest that coupling of the cell cycle to the circadian clock via NONO may be useful to segregate in temporal fashion cell proliferation from tissue organization.

Complementary HFET technology for low-power mixed-mode applications

Energy Technology Data Exchange (ETDEWEB)

Baca, A.G.; Sherwin, M.E.; Zolper, J.C.; Dubbert, D.F.; Hietala, V.M.; Shul, R.J.; Sloan, L.R.; Hafich, M.J.

1996-06-01

Development of a complementary heterostructure field effect transistor (CHFET) technology for low-power, mixed-mode digital-microwave applications is presented. An earlier digital CHFET technology with independently optimizable transistors which operated with 319 ps loaded gate delays at 8.9 fJ is reviewed. Then work demonstrating the applicability of the digital nJFET device as a low-power microwave transistor in a hybrid microwave amplifier without any modification to the digital process is presented. A narrow band amplifier with a 0.7 {times} 100 {micro}m nJFET as the active element was designed, constructed, and tested. At 1 mW operating power, the amplifier showed 9.7 dB of gain at 2.15 GHz and a minimum noise figure of 2.5 dB. In addition, next generation CHFET transistors with sub 0.5 {micro}m gate lengths were developed. Cutoff frequencies, f{sub t} of 49 GHz and 11.5 GHz were achieved for n- and p-channel FETs with 0.3 and 0.4 {micro}m gates, respectively. These FETs will enable both digital and microwave circuits with enhanced performance.

Design for High Performance, Low Power, and Reliable 3D Integrated Circuits

CERN Document Server

Lim, Sung Kyu

2013-01-01

This book describes the design of through-silicon-via (TSV) based three-dimensional integrated circuits.  It includes details of numerous “manufacturing-ready” GDSII-level layouts of TSV-based 3D ICs, developed with tools covered in the book. Readers will benefit from the sign-off level analysis of timing, power, signal integrity, and thermo-mechanical reliability for 3D IC designs.  Coverage also includes various design-for-manufacturability (DFM), design-for-reliability (DFR), and design-for-testability (DFT) techniques that are considered critical to the 3D IC design process. Describes design issues and solutions for high performance and low power 3D ICs, such as the pros/cons of regular and irregular placement of TSVs, Steiner routing, buffer insertion, low power 3D clock routing, power delivery network design and clock design for pre-bond testability. Discusses topics in design-for-electrical-reliability for 3D ICs, such as TSV-to-TSV coupling, current crowding at the wire-to-TSV junction and the e...

Collaborative Systems – Finite State Machines

Directory of Open Access Journals (Sweden)

Ion IVAN

2011-01-01

Full Text Available In this paper the finite state machines are defined and formalized. There are presented the collaborative banking systems and their correspondence is done with finite state machines. It highlights the role of finite state machines in the complexity analysis and performs operations on very large virtual databases as finite state machines. It builds the state diagram and presents the commands and documents transition between the collaborative systems states. The paper analyzes the data sets from Collaborative Multicash Servicedesk application and performs a combined analysis in order to determine certain statistics. Indicators are obtained, such as the number of requests by category and the load degree of an agent in the collaborative system.

Review of mixer design for low voltage - low power applications

Science.gov (United States)

Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

2017-09-01

A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

An improved gate valve for critical applications in nuclear power plants

International Nuclear Information System (INIS)

Kalsi, M.S.; Alvarez, P.D.; Wang, J.K.; Somagyi, D.

1996-01-01

U.S. Nuclear Regulatory Commission Generic Letters 89-10 for motor-operated valves (MOVs) and 95-07 for all power-operated valves document in detail the problems related to the performance of the safety-related valves in nuclear power plants. The problems relate to lack of reliable operation under design basis conditions including higher than anticipated stem thrust, unpredictable valve behavior, damage to the valve internals under blowdown/high flow conditions, significant degradation of performance when cycled under AP and flow, thermal binding, and pressure locking. This paper describes an improved motor-operated flexible wedge gate valve design, the GE Sentinel Valve, which is the outcome of a comprehensive and systematic development effort undertaken to resolve the issues identified in the NRC Generic Letters 89-10 and 95-07. The new design provides a reliable, long-term, low maintenance cost solution to the nuclear power industry. One of the key features incorporated in the disc permits the disc flexibility to be varied independently of the disc thickness (pressure boundary) dictated by the ASME Section III Pressure Vessel ampersand Piping Code stress criteria. This feature allows the desired flexibility to be incorporated in the disc, thus eliminating thermal binding problems. A matrix of analyses was performed using finite element and computational fluid dynamics approaches to optimize design for stresses, flexibility, leak-tightness, fluid flow, and thermal effects. The design of the entire product line was based upon a consistent set of analyses and design rules which permit scaling to different valve sizes and pressure classes within the product line. The valve meets all of the ASME Section III Code design criteria and the N-Stamp requirements. The performance of the valve was validated by performing extensive separate effects and plant in-situ tests. This paper summarizes the key design features, analyses, and test results

An improved gate valve for critical applications in nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Kalsi, M.S.; Alvarez, P.D.; Wang, J.K.; Somagyi, D. [Kalsi Engineering, Inc., Sugar Land, TX (United States)] [and others

1996-12-01

U.S. Nuclear Regulatory Commission Generic Letters 89-10 for motor-operated valves (MOVs) and 95-07 for all power-operated valves document in detail the problems related to the performance of the safety-related valves in nuclear power plants. The problems relate to lack of reliable operation under design basis conditions including higher than anticipated stem thrust, unpredictable valve behavior, damage to the valve internals under blowdown/high flow conditions, significant degradation of performance when cycled under AP and flow, thermal binding, and pressure locking. This paper describes an improved motor-operated flexible wedge gate valve design, the GE Sentinel Valve, which is the outcome of a comprehensive and systematic development effort undertaken to resolve the issues identified in the NRC Generic Letters 89-10 and 95-07. The new design provides a reliable, long-term, low maintenance cost solution to the nuclear power industry. One of the key features incorporated in the disc permits the disc flexibility to be varied independently of the disc thickness (pressure boundary) dictated by the ASME Section III Pressure Vessel & Piping Code stress criteria. This feature allows the desired flexibility to be incorporated in the disc, thus eliminating thermal binding problems. A matrix of analyses was performed using finite element and computational fluid dynamics approaches to optimize design for stresses, flexibility, leak-tightness, fluid flow, and thermal effects. The design of the entire product line was based upon a consistent set of analyses and design rules which permit scaling to different valve sizes and pressure classes within the product line. The valve meets all of the ASME Section III Code design criteria and the N-Stamp requirements. The performance of the valve was validated by performing extensive separate effects and plant in-situ tests. This paper summarizes the key design features, analyses, and test results.

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure

OpenAIRE

Tenentes, V.; Rossi, D.; Sheng Yang,; Khursheed, S.; Al-Hashimi, B.M.; Gunn, S.R.

2017-01-01

In this paper, we present a novel coarse-grained technique for monitoring online the Bias Temperature Instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during stand-by operations, the value of which depends on the threshold voltage of the CMOS devices in the power-gated design (PGD). It does not require any distributed sensors, because the virtual-power network is alr...

FPGA Dynamic Power Minimization through Placement and Routing Constraints

Directory of Open Access Journals (Sweden)

Deepak Agarwal

2006-08-01

Full Text Available Field-programmable gate arrays (FPGAs are pervasive in embedded systems requiring low-power utilization. A novel power optimization methodology for reducing the dynamic power consumed by the routing of FPGA circuits by modifying the constraints applied to existing commercial tool sets is presented. The power optimization techniques influence commercial FPGA Place and Route (PAR tools by translating power goals into standard throughput and placement-based constraints. The Low-Power Intelligent Tool Environment (LITE is presented, which was developed to support the experimentation of power models and power optimization algorithms. The generated constraints seek to implement one of four power optimization approaches: slack minimization, clock tree paring, N-terminal net colocation, and area minimization. In an experimental study, we optimize dynamic power of circuits mapped into 0.12 μm Xilinx Virtex-II FPGAs. Results show that several optimization algorithms can be combined on a single design, and power is reduced by up to 19.4%, with an average power savings of 10.2%.

Performance analysis of a complete adiabatic logic system driven by the proposed power clock generator

International Nuclear Information System (INIS)

Kanungo, Jitendra; Dasgupta, S.

2014-01-01

We analyze the energy performance of a complete adiabatic circuit/system including the Power Clock Generator (PCG) at the 90 nm CMOS technology node. The energy performance in terms of the conversion efficiency of the PCG is extensively carried out under the variations of supply voltage, process corner and the driver transistor's width. We propose an energy-efficient singe cycle control circuit based on the two-stage comparator for the synchronous charge recovery sinusoidal power clock generator (PCG). The proposed PCG is used to drive the 4-bit adiabatic Ripple Carry Adder (RCA) and their simulation results are compared with the adiabatic RCA driven by the reported PCG. We have also simulated the logically equivalent static CMOS RCA circuit to compare the energy saving of adiabatic and non-adiabatic logic circuits. In the clock frequency range from 25 MHz to 1GHz, the proposed PCG gives a maximum conversion efficiency of 56.48%. This research work shows how the design of an efficient PCG increases the energy saving of adiabatic logic. (semiconductor integrated circuits)

Shining a light on the Arabidopsis circadian clock.

Science.gov (United States)

Oakenfull, Rachael J; Davis, Seth J

2017-11-01

The circadian clock provides essential timing information to ensure optimal growth to prevailing external environmental conditions. A major time-setting mechanism (zeitgeber) in clock synchronization is light. Differing light wavelengths, intensities, and photoperiodic duration are processed for the clock-setting mechanism. Many studies on light-input pathways to the clock have focused on Arabidopsis thaliana. Photoreceptors are specific chromic proteins that detect light signals and transmit this information to the central circadian oscillator through a number of different signalling mechanisms. The most well-characterized clock-mediating photoreceptors are cryptochromes and phytochromes, detecting blue, red, and far-red wavelengths of light. Ultraviolet and shaded light are also processed signals to the oscillator. Notably, the clock reciprocally generates rhythms of photoreceptor action leading to so-called gating of light responses. Intermediate proteins, such as Phytochrome interacting factors (PIFs), constitutive photomorphogenic 1 (COP1) and EARLY FLOWERING 3 (ELF3), have been established in signalling pathways downstream of photoreceptor activation. However, the precise details for these signalling mechanisms are not fully established. This review highlights both historical and recent efforts made to understand overall light input to the oscillator, first looking at how each wavelength of light is detected, this is then related to known input mechanisms and their interactions. © 2017 John Wiley & Sons Ltd.

Analysis of OFF-state and ON-state performance in a silicon-on-insulator power MOSFET with a low-k dielectric trench

International Nuclear Information System (INIS)

Wang Zhigang; Zhang Bo; Li Zhaoji

2013-01-01

A novel silicon-on-insulator (SOI) MOSFET with a variable low-k dielectric trench (LDT MOSFET) is proposed and its performance and characteristics are investigated. The trench in the drift region between drain and source is filled with low-k dielectric to extend the effective drift region. At OFF state, the low-k dielectric trench (LDT) can sustain high voltage and enhance the dielectric field due to the accumulation of ionized charges. At the same time, the vertical dielectric field in the buried oxide can also be enhanced by these ionized charges. Additionally, ON-state analysis of LDT MOSFET demonstrates excellent forward characteristics, such as low gate-to-drain charge density ( 2 ) and a robust safe operating area (0–84 V). (semiconductor devices)

A precise clock distribution network for MRPC-based experiments

International Nuclear Information System (INIS)

Wang, S.; Cao, P.; Shang, L.; An, Q.

2016-01-01

In high energy physics experiments, the MRPC (Multi-Gap Resistive Plate Chamber) detectors are widely used recently which can provide higher-resolution measurement for particle identification. However, the application of MRPC detectors leads to a series of challenges in electronics design with large number of front-end electronic channels, especially for distributing clock precisely. To deal with these challenges, this paper presents a universal scheme of clock transmission network for MRPC-based experiments with advantages of both precise clock distribution and global command synchronization. For precise clock distributing, the clock network is designed into a tree architecture with two stages: the first one has a point-to-multipoint long range bidirectional distribution with optical channels and the second one has a fan-out structure with copper link inside readout crates. To guarantee the precision of clock frequency or phase, the r-PTP (reduced Precision Time Protocol) and the DDMTD (digital Dual Mixer Time Difference) methods are used for frequency synthesis, phase measurement and adjustment, which is implemented by FPGA (Field Programmable Gate Array) in real-time. In addition, to synchronize global command execution, based upon this clock distribution network, synchronous signals are coded with clock for transmission. With technique of encoding/decoding and clock data recovery, signals such as global triggers or system control commands, can be distributed to all front-end channels synchronously, which greatly simplifies the system design. The experimental results show that both the clock jitter (RMS) and the clock skew can be less than 100 ps.

Gate-tunable Andreev bound states in InSb nanowire Josephson junction

Energy Technology Data Exchange (ETDEWEB)

Kang, Ning; Li, Sen; Fan, Dingxun; Xu, Hongqi [Key Laboratory for the Physics and Chemistry of Nanodevices, Department of Electronics, Peking University, Beijing 100871 (China); Caroff, Philippe [Division of Solid State Physics, Lund University, P. O. Box 118, S-221 00 Lund (Sweden)

2016-07-01

Hybrid InSb nanowire-superconductor devices are promising candidates for investigating Majorana modes in solid-state devices and future technologies of topological quantum manipulation. Here, we report low-temperature transport measurements on an individual InSb nanowire quantum dot coupled to superconducting contacts that exhibit an interplay between the Kondo effects and superconductivity. We observed two types of subgap resonance states within the superconducting gap, which can be attributed to gate-tunable Andreev bound states in Coulomb valleys with different Kondo temperatures. The presence of the gate-tunable 0 and pi junction allow us to investigate the fundamental 0- pi transition. Detailed magnetic field and temperature evolution of level spectroscopy demonstrate different behavior of two types of the Andreev bound states. Our results exhibit that the InSb nanowires can provide a promising platform for exploring phase coherence transport and the effect of spin-orbit coupling in semiconductor nanowire-superconductor hybrid device.

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

Directory of Open Access Journals (Sweden)

Yu-Min Lee

2002-01-01

Full Text Available Delay, power, skew, area and sensitivity are the most important concerns in current clock-tree design. We present in this paper an algorithm for simultaneously optimizing the above objectives by sizing wires and buffers in clock trees. Our algorithm, based on Lagrangian relaxation method, can optimally minimize delay, power and area simultaneously with very low skew and sensitivity. With linear storage overall and linear runtime per iteration, our algorithm is extremely economical, fast and accurate; for example, our algorithm can solve a 6201-wire-segment clock-tree problem using about 1-minute runtime and 1.3-MB memory and still achieve pico-second precision on an IBM RS/6000 workstation.

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Science.gov (United States)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2016-04-01

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Miniaturized, low power FGMOSFET radiation sensor and wireless dosimeter system

KAUST Repository

Arsalan, Muhammad; Shamim, Atif; Tarr, Nicholas Garry; Roy, Langis

2013-01-01

A miniaturized floating gate (FG) MOSFET radiation sensor system is disclosed, The sensor preferably comprises a matched pair of sensor and reference FGMOSFETs wherein the sensor FGMOSFET has a larger area floating gate with an extension over a field oxide layer, for accumulation of charge and increased sensitivity. Elimination of a conventional control gate and injector gate reduces capacitance, and increases sensitivity, and allows for fabrication using standard low cost CMOS technology. A sensor system may be provided with integrated signal processing electronics, for monitoring a change in differential channel current I.sub.D, indicative of radiation dose, and an integrated negative bias generator for automatic pre-charging from a low voltage power source. Optionally, the system may be coupled to a wireless transmitter. A compact wireless sensor System on Package solution is presented, suitable for dosimetry for radiotherapy or other biomedical applications.

Miniaturized, low power FGMOSFET radiation sensor and wireless dosimeter system

KAUST Repository

Arsalan, Muhammad

2013-08-27

A miniaturized floating gate (FG) MOSFET radiation sensor system is disclosed, The sensor preferably comprises a matched pair of sensor and reference FGMOSFETs wherein the sensor FGMOSFET has a larger area floating gate with an extension over a field oxide layer, for accumulation of charge and increased sensitivity. Elimination of a conventional control gate and injector gate reduces capacitance, and increases sensitivity, and allows for fabrication using standard low cost CMOS technology. A sensor system may be provided with integrated signal processing electronics, for monitoring a change in differential channel current I.sub.D, indicative of radiation dose, and an integrated negative bias generator for automatic pre-charging from a low voltage power source. Optionally, the system may be coupled to a wireless transmitter. A compact wireless sensor System on Package solution is presented, suitable for dosimetry for radiotherapy or other biomedical applications.

Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery Logic

Directory of Open Access Journals (Sweden)

Shipra Upadhyay

2013-01-01

Full Text Available Efficiency of adiabatic logic circuits is determined by the adiabatic and non-adiabatic losses incurred by them during the charging and recovery operations. The lesser will be these losses circuit will be more energy efficient. In this paper, a new approach is presented for minimizing power consumption in quasistatic energy recovery logic (QSERL circuit which involves optimization by removing the nonadiabatic losses completely by replacing the diodes with MOSFETs whose gates are controlled by power clocks. Proposed circuit inherits the advantages of quasistatic ERL (QSERL family but is with improved power efficiency and driving ability. In order to demonstrate workability of the newly developed circuit, a 4 × 4 bit array multiplier circuit has been designed. A mathematical expression to calculate energy dissipation in proposed inverter is developed. Performance of the proposed logic (improved quasistatic energy recovery logic (IQSERL is analyzed and compared with CMOS and reported QSERL in their representative inverters and multipliers in VIRTUOSO SPECTRE simulator of Cadence in 0.18 μm UMC technology. In our proposed (IQSERL inverter the power efficiency has been improved to almost 20% up to 50 MHz and 300 fF external load capacitance in comparison to CMOS and QSERL circuits.

Bennett clocking of quantum-dot cellular automata and the limits to binary logic scaling

International Nuclear Information System (INIS)

Lent, Craig S; Liu Mo; Lu Yuhui

2006-01-01

We examine power dissipation in different clocking schemes for molecular quantum-dot cellular automata (QCA) circuits. 'Landauer clocking' involves the adiabatic transition of a molecular cell from the null state to an active state carrying data. Cell layout creates devices which allow data in cells to interact and thereby perform useful computation. We perform direct solutions of the equation of motion for the system in contact with the thermal environment and see that Landauer's Principle applies: one must dissipate an energy of at least k B T per bit only when the information is erased. The ideas of Bennett can be applied to keep copies of the bit information by echoing inputs to outputs, thus embedding any logically irreversible circuit in a logically reversible circuit, at the cost of added circuit complexity. A promising alternative which we term 'Bennett clocking' requires only altering the timing of the clocking signals so that bit information is simply held in place by the clock until a computational block is complete, then erased in the reverse order of computation. This approach results in ultralow power dissipation without additional circuit complexity. These results offer a concrete example in which to consider recent claims regarding the fundamental limits of binary logic scaling

A note on powers in finite fields

Science.gov (United States)

Aabrandt, Andreas; Lundsgaard Hansen, Vagn

2016-08-01

The study of solutions to polynomial equations over finite fields has a long history in mathematics and is an interesting area of contemporary research. In recent years, the subject has found important applications in the modelling of problems from applied mathematical fields such as signal analysis, system theory, coding theory and cryptology. In this connection, it is of interest to know criteria for the existence of squares and other powers in arbitrary finite fields. Making good use of polynomial division in polynomial rings over finite fields, we have examined a classical criterion of Euler for squares in odd prime fields, giving it a formulation that is apt for generalization to arbitrary finite fields and powers. Our proof uses algebra rather than classical number theory, which makes it convenient when presenting basic methods of applied algebra in the classroom.

Plant operational states analysis in low power and shutdown PSA

International Nuclear Information System (INIS)

He Jiandong; Qiu Yongping; Zhang Qinfang; An Hongzhen; Li Maolin

2013-01-01

The purpose of Plant Operational States (POS) analysis is to disperse the continuous and dynamic process of low power and shutdown operation, which is the basis of developing event tree models for accident sequence analysis. According to the design of a 300 MW Nuclear Power Plant Project, operating experience and procedures of the reference plant, a detailed POS analysis is carried out based on relative criteria. Then, several kinds of POS are obtained, and the duration of each POS is calculated according to the operation records of the reference plant. The POS analysis is an important element in low power and shutdown PSA. The methodology and contents provide reference for POS analysis. (authors)

The design and development of low- and high-voltage ASICs for space-borne CCD cameras

Science.gov (United States)

Waltham, N.; Morrissey, Q.; Clapp, M.; Bell, S.; Jones, L.; Torbet, M.

2017-12-01

The CCD remains the pre-eminent visible and UV wavelength image sensor in space science, Earth and planetary remote sensing. However, the design of space-qualified CCD readout electronics is a significant challenge with requirements for low-volume, low-mass, low-power, high-reliability and tolerance to space radiation. Space-qualified components are frequently unavailable and up-screened commercial components seldom meet project or international space agency requirements. In this paper, we describe an alternative approach of designing and space-qualifying a series of low- and high-voltage mixed-signal application-specific integrated circuits (ASICs), the ongoing development of two low-voltage ASICs with successful flight heritage, and two new high-voltage designs. A challenging sub-system of any CCD camera is the video processing and digitisation electronics. We describe recent developments to improve performance and tolerance to radiation-induced single event latchup of a CCD video processing ASIC originally developed for NASA's Solar Terrestrial Relations Observatory and Solar Dynamics Observatory. We also describe a programme to develop two high-voltage ASICs to address the challenges presented with generating a CCD's bias voltages and drive clocks. A 0.35 μm, 50 V tolerant, CMOS process has been used to combine standard low-voltage 3.3 V transistors with high-voltage 50 V diffused MOSFET transistors that enable output buffers to drive CCD bias drains, gates and clock electrodes directly. We describe a CCD bias voltage generator ASIC that provides 24 independent and programmable 0-32 V outputs. Each channel incorporates a 10-bit digital-to-analogue converter, provides current drive of up to 20 mA into loads of 10 μF, and includes current-limiting and short-circuit protection. An on-chip telemetry system with a 12-bit analogue-to-digital converter enables the outputs and multiple off-chip camera voltages to be monitored. The ASIC can drive one or more CCDs and

Wide-bandwidth low-voltage PLL for powerPC(sup TM) microprocessors

Science.gov (United States)

Alvarez, Jose; Sanchez, Hector; Gerosa, Gianfranco; Countryman, Roger

1995-04-01

A 3.3 V Phase-Locked-Loop (PLL) clock synthesizer implemented in 0.5 micron CMOS technology is described. The PLL supports internal to external clock frequency ratios of 1, 1.5, 2, 3, and 4 as well as numerous static power down modes for PowerPC(sup TM) microprocessors. The CPU clock lock range spans from 6 to 175 MHz. Lock times below 15 mu s, PLL power dissipation below 10mW as well as phase error and jitter below +/- 100 ps have been measured. The total area of the PLL is 0.52 mm(exp 2).

Return on experience on control gates in nuclear power station

International Nuclear Information System (INIS)

Valendru, N.

2009-01-01

In application of an EDF internal directive, control gates are used at the exit of the Controlled Areas of each nuclear power station site for the radiological control of materials or wastes on pedestrians and vehicles. The author first presents the radiological control chain for people and its principles. This chain comprises the different controls performed within the controlled area, either at the exit of a works area or at the exit of the reactor building, the different controls performed at the exit of the controlled area (depending on the site classification), the control of pedestrians at the site exit, and the 'whole body' anthropo-gamma-metric control. For each of these controls, the authors indicate the detection objectives, the different contamination threshold values, and the type of gate used. In a second part, the authors more precisely present the new C2 gates which include gamma and beta sensors, indicate how control thresholds are adjusted on different power station sites, and discuss the lessons learned after the first years of use of these new gates (difficulties and problems faced as far as detection and detection thresholds are concerned, changes in organization)

DNA Replication Is Required for Circadian Clock Function by Regulating Rhythmic Nucleosome Composition.

Science.gov (United States)

Liu, Xiao; Dang, Yunkun; Matsu-Ura, Toru; He, Yubo; He, Qun; Hong, Christian I; Liu, Yi

2017-07-20

Although the coupling between circadian and cell cycles allows circadian clocks to gate cell division and DNA replication in many organisms, circadian clocks were thought to function independently of cell cycle. Here, we show that DNA replication is required for circadian clock function in Neurospora. Genetic and pharmacological inhibition of DNA replication abolished both overt and molecular rhythmicities by repressing frequency (frq) gene transcription. DNA replication is essential for the rhythmic changes of nucleosome composition at the frq promoter. The FACT complex, known to be involved in histone disassembly/reassembly, is required for clock function and is recruited to the frq promoter in a replication-dependent manner to promote replacement of histone H2A.Z by H2A. Finally, deletion of H2A.Z uncoupled the dependence of the circadian clock on DNA replication. Together, these results establish circadian clock and cell cycle as interdependent coupled oscillators and identify DNA replication as a critical process in the circadian mechanism. Published by Elsevier Inc.

Finite-time stabilisation of a class of switched nonlinear systems with state constraints

Science.gov (United States)

Huang, Shipei; Xiang, Zhengrong

2018-06-01

This paper investigates the finite-time stabilisation for a class of switched nonlinear systems with state constraints. Some power orders of the system are allowed to be ratios of positive even integers over odd integers. A Barrier Lyapunov function is introduced to guarantee that the state constraint is not violated at any time. Using the convex combination method and a recursive design approach, a state-dependent switching law and state feedback controllers of individual subsystems are constructed such that the closed-loop system is finite-time stable without violation of the state constraint. Two examples are provided to show the effectiveness of the proposed method.

Potential and limits to cluster-state quantum computing using probabilistic gates

International Nuclear Information System (INIS)

Gross, D.; Kieling, K.; Eisert, J.

2006-01-01

We establish bounds to the necessary resource consumption when building up cluster states for one-way computing using probabilistic gates. Emphasis is put on state preparation with linear optical gates, as the probabilistic character is unavoidable here. We identify rigorous general bounds to the necessary consumption of initially available maximally entangled pairs when building up one-dimensional cluster states with individually acting linear optical quantum gates, entangled pairs, and vacuum modes. As the known linear optics gates have a limited maximum success probability, as we show, this amounts to finding the optimal classical strategy of fusing pieces of linear cluster states. A formal notion of classical configurations and strategies is introduced for probabilistic nonfaulty gates. We study the asymptotic performance of strategies that can be simply described, and prove ultimate bounds to the performance of the globally optimal strategy. The arguments employ methods of random walks and convex optimization. This optimal strategy is also the one that requires the shortest storage time, and necessitates the fewest invocations of probabilistic gates. For two-dimensional cluster states, we find, for any elementary success probability, an essentially deterministic preparation of a cluster state with quadratic, hence optimal, asymptotic scaling in the use of entangled pairs. We also identify a percolation effect in state preparation, in that from a threshold probability on, almost all preparations will be either successful or fail. We outline the implications on linear optical architectures and fault-tolerant computations

The operations of quantum logic gates with pure and mixed initial states.

Science.gov (United States)

Chen, Jun-Liang; Li, Che-Ming; Hwang, Chi-Chuan; Ho, Yi-Hui

2011-04-07

The implementations of quantum logic gates realized by the rovibrational states of a C(12)O(16) molecule in the X((1)Σ(+)) electronic ground state are investigated. Optimal laser fields are obtained by using the modified multitarget optimal theory (MTOCT) which combines the maxima of the cost functional and the fidelity for state and quantum process. The projection operator technique together with modified MTOCT is used to get optimal laser fields. If initial states of the quantum gate are pure states, states at target time approach well to ideal target states. However, if the initial states are mixed states, the target states do not approach well to ideal ones. The process fidelity is introduced to investigate the reliability of the quantum gate operation driven by the optimal laser field. We found that the quantum gates operate reliably whether the initial states are pure or mixed.

Electronic states in crystals of finite size quantum confinement of bloch waves

CERN Document Server

Ren, Shang Yuan

2017-01-01

This book presents an analytical theory of the electronic states in ideal low dimensional systems and finite crystals based on a differential equation theory approach. It provides precise and fundamental understandings on the electronic states in ideal low-dimensional systems and finite crystals, and offers new insights into some of the basic problems in low-dimensional systems, such as the surface states and quantum confinement effects, etc., some of which are quite different from what is traditionally believed in the solid state physics community. Many previous predictions have been confirmed in subsequent investigations by other authors on various relevant problems. In this new edition, the theory is further extended to one-dimensional photonic crystals and phononic crystals, and a general theoretical formalism for investigating the existence and properties of surface states/modes in semi-infinite one-dimensional crystals is developed. In addition, there are various revisions and improvements, including us...

Feasibility of epicardial adipose tissue quantification in non-ECG-gated low-radiation-dose CT: comparison with prospectively ECG-gated cardiac CT

Energy Technology Data Exchange (ETDEWEB)

Simon-Yarza, Isabel; Viteri-Ramirez, Guillermo; Saiz-Mendiguren, Ramon; Slon-Roblero, Pedro J.; Paramo, Maria [Dept. of Radiology, Clinica Univ. de Navarra, Pamplona (Spain); Bastarrika, Gorka [Dept. of Radiology, Clinica Univ. de Navarra, Pamplona (Spain); Cardiac Imaging Unit, Clinica Univ. de Navarra, Pamplona (Spain)], e-mail: bastarrika@unav.es

2012-06-15

Background: Epicardial adipose tissue (EAT) is an important indicator of cardiovascular risk. This parameter is generally assessed on ECG-gated computed tomography (CT) images. Purpose: To evaluate feasibility and reliability of EAT quantification on non-gated thoracic low-radiation-dose CT examinations with respect to prospectively ECG-gated cardiac CT acquisition. Material and Methods: Sixty consecutive asymptomatic smokers (47 men; mean age 64 {+-} 9.8 years) underwent low-dose CT of the chest and prospectively ECG-gated cardiac CT acquisitions (64-slice dual-source CT). The two examinations were reconstructed with the same range, field of view, slice thickness, and convolution algorithm. Two independent observers blindly quantified EAT volume using commercially available software. Data were compared with paired sample Student t-test, concordance correlation coefficients (CCC), and Bland-Altman plots. Results: No statistically significant difference was observed for EAT volume quantification with low-dose-CT (141.7 {+-} 58.3 mL) with respect to ECG-gated CT (142.7 {+-} 57.9 mL). Estimation of CCC showed almost perfect concordance between the two techniques for EAT-volume assessment (CCC, 0.99; mean difference, 0.98 {+-} 5.1 mL). Inter-observer agreement for EAT volume estimation was CCC: 0.96 for low-dose-CT examinations and 0.95 for ECG-gated CT. Conclusion: Non-gated low-dose CT allows quantifying EAT with almost the same concordance and reliability as using dedicated prospectively ECG-gated cardiac CT acquisition protocols.

Feasibility of epicardial adipose tissue quantification in non-ECG-gated low-radiation-dose CT: comparison with prospectively ECG-gated cardiac CT

International Nuclear Information System (INIS)

Simon-Yarza, Isabel; Viteri-Ramirez, Guillermo; Saiz-Mendiguren, Ramon; Slon-Roblero, Pedro J.; Paramo, Maria; Bastarrika, Gorka

2012-01-01

Background: Epicardial adipose tissue (EAT) is an important indicator of cardiovascular risk. This parameter is generally assessed on ECG-gated computed tomography (CT) images. Purpose: To evaluate feasibility and reliability of EAT quantification on non-gated thoracic low-radiation-dose CT examinations with respect to prospectively ECG-gated cardiac CT acquisition. Material and Methods: Sixty consecutive asymptomatic smokers (47 men; mean age 64 ± 9.8 years) underwent low-dose CT of the chest and prospectively ECG-gated cardiac CT acquisitions (64-slice dual-source CT). The two examinations were reconstructed with the same range, field of view, slice thickness, and convolution algorithm. Two independent observers blindly quantified EAT volume using commercially available software. Data were compared with paired sample Student t-test, concordance correlation coefficients (CCC), and Bland-Altman plots. Results: No statistically significant difference was observed for EAT volume quantification with low-dose-CT (141.7 ± 58.3 mL) with respect to ECG-gated CT (142.7 ± 57.9 mL). Estimation of CCC showed almost perfect concordance between the two techniques for EAT-volume assessment (CCC, 0.99; mean difference, 0.98 ± 5.1 mL). Inter-observer agreement for EAT volume estimation was CCC: 0.96 for low-dose-CT examinations and 0.95 for ECG-gated CT. Conclusion: Non-gated low-dose CT allows quantifying EAT with almost the same concordance and reliability as using dedicated prospectively ECG-gated cardiac CT acquisition protocols

A Survey on Modeling and Simulation of MEMS Switches and Its Application in Power Gating Techniques

OpenAIRE

Pramod Kumar M.P; A.S. Augustine Fletcher

2014-01-01

Large numbers of techniques have been developed to reduce the leakage power, including supply voltage scaling, varying threshold voltages, smaller logic banks, etc. Power gating is a technique which is used to reduce the static power when the sleep transistor is in off condition. Micro Electro mechanical System (MEMS) switches have properties that are very close to an ideal switch, with infinite off-resistance due to an air gap and low on-resistance due to the ohmic metal to m...

[Elevated expression of CLOCK is associated with poor prognosis in hepatocellular carcinoma].

Science.gov (United States)

Li, Bo; Yang, Xiliang; Li, Jiaqi; Yang, Yi; Yan, Zhaoyong; Zhang, Hongxin; Mu, Jiao

2018-02-01

Objective To evaluate the expression of circadian locomotor output cycles kaput (CLOCK) and its effects on cell growth in hepatocellular carcinoma (HCC). Methods The expression of CLOCK in 158 pairs of human HCC tissues and matched noncancerous samples was detected by immunohistochemical (IHC) staining. The expression of CLOCK in HCC patients was also verified using the data from GEO and TCGA (a total of 356 cases). The relationship between CLOCK expression and clinicopathological features of HCC patients was analyzed by single factor statistical analysis. Kaplan-Meier survival curves of HCC patients were drawn to study the relationship between the expression level of CLOCK and the survival state. The effect of CLOCK on the growth of HepG2 cells was detected by MTS assay. Results The expression of CLOCK in HCC tissues was significantly higher than that in the adjacent tissues, and the up-regulation of CLOCK expression in HCC tissue was also confirmed in the public data of HCC (356 cases). HCC patients were divided into low CLOCK expression group and high CLOCK expression group. Univariate analysis showed that the expression of CLOCK was related to tumor size, TNM stage, and portal vein invasion in HCC patients. HCC patients with low CLOCK expression had longer overall survival time and relapse-free survival time than those with high CLOCK expression. The proliferation of cells significantly decreased after the expression of CLOCK was knocked down in HepG2 cells. Conclusion The expression of CLOCK in HCC tissues was much higher than that in normal liver tissues, and the high expression of CLOCK indicated the poor prognosis. The knockdown of CLOCK in HCC cells could inhibit the proliferation of HepG2 cells.

Ambipolar organic tri-gate transistor for low-power complementary electronics

NARCIS (Netherlands)

Torricelli, F.; Ghittorelli, M.; Smits, E.C.P.; Roelofs, C.; Janssen, R.A.J.; Gelinck, G.H.; Kovács-Vajna, Z.M.; Cantatore, E.

2016-01-01

Ambipolar transistors typically suffer from large off-current inherently due to ambipolar conduction. Using a tri-gate transistor it is shown that it is possible to electrostatically switch ambipolar polymer transistors from ambipolar to unipolar mode. In unipolar mode, symmetric characteristics

High-fidelity Rydberg quantum gate via a two-atom dark state

DEFF Research Database (Denmark)

Petrosyan, David; Motzoi, Felix; Saffman, Mark

2017-01-01

We propose a two-qubit gate for neutral atoms in which one of the logical state components adiabatically follows a two-atom dark state formed by the laser coupling to a Rydberg state and a strong, resonant dipole-dipole exchange interaction between two Rydberg excited atoms. Our gate exhibits...

Round Gating for Low Energy Block Ciphers

DEFF Research Database (Denmark)

Banik, Subhadeep; Bogdanov, Andrey; Regazzoni, Francesco

2016-01-01

design techniques for implementing block ciphers in a low energy fashion. We concentrate on round based implementation and we discuss how gating, applied at round level can affect and improve the energy consumption of the most common lightweight block cipher currently used in the internet of things....... Additionally, we discuss how to needed gating wave can be generated. Experimental results show that our technique is able to reduce the energy consumption in most block ciphers by over 60% while incurring only a minimal overhead in hardware....

Design of low-power coarse-grained reconfigurable architectures

CERN Document Server

Kim, Yoonjin

2010-01-01

Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks.The first half of the book explains how to reduce power in the configuration cache. T

Design of ternary clocked adiabatic static random access memory

International Nuclear Information System (INIS)

Wang Pengjun; Mei Fengna

2011-01-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions. (semiconductor integrated circuits)

Design of ternary clocked adiabatic static random access memory

Science.gov (United States)

Pengjun, Wang; Fengna, Mei

2011-10-01

Based on multi-valued logic, adiabatic circuits and the structure of ternary static random access memory (SRAM), a design scheme of a novel ternary clocked adiabatic SRAM is presented. The scheme adopts bootstrapped NMOS transistors, and an address decoder, a storage cell and a sense amplifier are charged and discharged in the adiabatic way, so the charges stored in the large switch capacitance of word lines, bit lines and the address decoder can be effectively restored to achieve energy recovery during reading and writing of ternary signals. The PSPICE simulation results indicate that the ternary clocked adiabatic SRAM has a correct logic function and low power consumption. Compared with ternary conventional SRAM, the average power consumption of the ternary adiabatic SRAM saves up to 68% in the same conditions.

High voltage generator circuit with low power and high efficiency applied in EEPROM

International Nuclear Information System (INIS)

Liu Yan; Zhang Shilin; Zhao Yiqiang

2012-01-01

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

High-precision high-sensitivity clock recovery circuit for a mobile payment application

International Nuclear Information System (INIS)

Sun Lichong; Yan Na; Min Hao; Ren Wenliang

2011-01-01

This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop. Compared with clock recovery in conventional 13.56 MHz transponders, this circuit can recover a high-precision consecutive carrier clock from the on/off keying (OOK) signal sent by interrogators. Fabricated by a SMIC 0.18-μm EEPROM CMOS process, this chip works from a single power supply as low as 1.5 V Measurement results show that this circuit provides 0.34% frequency deviation and 8 mV sensitivity. (semiconductor integrated circuits)

Single-Event Gate Rupture in Power MOSFETs: A New Radiation Hardness Assurance Approach

Science.gov (United States)

Lauenstein, Jean-Marie

2011-01-01

Almost every space mission uses vertical power metal-semiconductor-oxide field-effect transistors (MOSFETs) in its power-supply circuitry. These devices can fail catastrophically due to single-event gate rupture (SEGR) when exposed to energetic heavy ions. To reduce SEGR failure risk, the off-state operating voltages of the devices are derated based upon radiation tests at heavy-ion accelerator facilities. Testing is very expensive. Even so, data from these tests provide only a limited guide to on-orbit performance. In this work, a device simulation-based method is developed to measure the response to strikes from heavy ions unavailable at accelerator facilities but posing potential risk on orbit. This work is the first to show that the present derating factor, which was established from non-radiation reliability concerns, is appropriate to reduce on-orbit SEGR failure risk when applied to data acquired from ions with appropriate penetration range. A second important outcome of this study is the demonstration of the capability and usefulness of this simulation technique for augmenting SEGR data from accelerator beam facilities. The mechanisms of SEGR are two-fold: the gate oxide is weakened by the passage of the ion through it, and the charge ionized along the ion track in the silicon transiently increases the oxide electric field. Most hardness assurance methodologies consider the latter mechanism only. This work demonstrates through experiment and simulation that the gate oxide response should not be neglected. In addition, the premise that the temporary weakening of the oxide due to the ion interaction with it, as opposed to due to the transient oxide field generated from within the silicon, is validated. Based upon these findings, a new approach to radiation hardness assurance for SEGR in power MOSFETs is defined to reduce SEGR risk in space flight projects. Finally, the potential impact of accumulated dose over the course of a space mission on SEGR

Causes and consequences of hyperexcitation in central clock neurons.

Directory of Open Access Journals (Sweden)

Casey O Diekman

Full Text Available Hyperexcited states, including depolarization block and depolarized low amplitude membrane oscillations (DLAMOs, have been observed in neurons of the suprachiasmatic nuclei (SCN, the site of the central mammalian circadian (~24-hour clock. The causes and consequences of this hyperexcitation have not yet been determined. Here, we explore how individual ionic currents contribute to these hyperexcited states, and how hyperexcitation can then influence molecular circadian timekeeping within SCN neurons. We developed a mathematical model of the electrical activity of SCN neurons, and experimentally verified its prediction that DLAMOs depend on post-synaptic L-type calcium current. The model predicts that hyperexcited states cause high intracellular calcium concentrations, which could trigger transcription of clock genes. The model also predicts that circadian control of certain ionic currents can induce hyperexcited states. Putting it all together into an integrative model, we show how membrane potential and calcium concentration provide a fast feedback that can enhance rhythmicity of the intracellular circadian clock. This work puts forward a novel role for electrical activity in circadian timekeeping, and suggests that hyperexcited states provide a general mechanism for linking membrane electrical dynamics to transcription activation in the nucleus.

Low power adder based auditory filter architecture.

Science.gov (United States)

Rahiman, P F Khaleelur; Jayanthi, V S

2014-01-01

Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

Low Power Adder Based Auditory Filter Architecture

Directory of Open Access Journals (Sweden)

P. F. Khaleelur Rahiman

2014-01-01

Full Text Available Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

A low noise clock generator for high-resolution time-to-digital convertors

International Nuclear Information System (INIS)

Prinzie, J.; Leroux, P.; Christiaensen, J.; Moreira, P.; Steyaert, M.

2016-01-01

A robust PLL clock generator has been designed for the harsh environment in high-energy physics applications. The PLL operates with a reference clock frequency of 40 MHz to 50 MHz and performs a multiplication by 64. An LC tank VCO with low internal phase noise can generate a frequency from 2.2 GHz up to 3.2 GHz with internal discrete bank switching. The PLL includes an automatic bank selection algorithm to correctly select the correct range of the oscillator. The PLL has been fabricated in a 65 nm CMOS technology and consumes less than 30 mW. The additive jitter of the PLL has been measured to be less than 400 fs RMS

Experimental demonstration of a Hadamard gate for coherent state qubits

DEFF Research Database (Denmark)

Tipsmark, Anders; Dong, Ruifang; Laghaout, Amine

2011-01-01

We discuss and make an experimental test of a probabilistic Hadamard gate for coherent state qubits. The scheme is based on linear optical components, nonclassical resources, and the joint projective action of a photon counter and a homodyne detector. We experimentally characterize the gate for t...... for the coherent states of the computational basis by full tomographic reconstruction of the transformed output states. Based on the parameters of the experiment, we simulate the fidelity for all coherent state qubits on the Bloch sphere....

Experimental demonstration of a Hadamard gate for coherent state qubits

Energy Technology Data Exchange (ETDEWEB)

Tipsmark, Anders; Laghaout, Amine; Andersen, Ulrik L. [Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark); Dong, Ruifang [Quantum Frequency Standards Division, National Time Service Center (NTSC), Chinese Academy of Sciences, 710600 Lintong, Shaanxi (China); Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark); Marek, Petr [Department of Optics, Palacky University, 17. listopadu 12, CZ-77146 Olomouc (Czech Republic); Jezek, Miroslav [Department of Optics, Palacky University, 17. listopadu 12, CZ-77146 Olomouc (Czech Republic); Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark)

2011-11-15

We discuss and make an experimental test of a probabilistic Hadamard gate for coherent state qubits. The scheme is based on linear optical components, nonclassical resources, and the joint projective action of a photon counter and a homodyne detector. We experimentally characterize the gate for the coherent states of the computational basis by full tomographic reconstruction of the transformed output states. Based on the parameters of the experiment, we simulate the fidelity for all coherent state qubits on the Bloch sphere.

Gate-Driven Pure Spin Current in Graphene

Science.gov (United States)

Lin, Xiaoyang; Su, Li; Si, Zhizhong; Zhang, Youguang; Bournel, Arnaud; Zhang, Yue; Klein, Jacques-Olivier; Fert, Albert; Zhao, Weisheng

2017-09-01

The manipulation of spin current is a promising solution for low-power devices beyond CMOS. However, conventional methods, such as spin-transfer torque or spin-orbit torque for magnetic tunnel junctions, suffer from large power consumption due to frequent spin-charge conversions. An important challenge is, thus, to realize long-distance transport of pure spin current, together with efficient manipulation. Here, the mechanism of gate-driven pure spin current in graphene is presented. Such a mechanism relies on the electrical gating of carrier-density-dependent conductivity and spin-diffusion length in graphene. The gate-driven feature is adopted to realize the pure spin-current demultiplexing operation, which enables gate-controllable distribution of the pure spin current into graphene branches. Compared with the Elliott-Yafet spin-relaxation mechanism, the D'yakonov-Perel spin-relaxation mechanism results in more appreciable demultiplexing performance. The feature of the pure spin-current demultiplexing operation will allow a number of logic functions to be cascaded without spin-charge conversions and open a route for future ultra-low-power devices.

Could Atomic clocks be affected by neutrinos?

CERN Document Server

Hanafi, Hanaa

2016-01-01

An atomic clock is a clock device that uses an electronic transition frequency of the electromagnetic spectrum of atoms as a frequency standard in order to derive a time standard since time is the reciprocal of frequency. If the electronic transition frequencies are in an "optical region", we are talking in this case about optical atomic clocks. If they are in an "microwave region" these atomic clocks are made of the metallic element cesium so they are called Cesium atomic clocks. Atomic clocks are the most accurate time and frequency standards known despite the different perturbations that can affect them, a lot of researches were made in this domain to show how the transitions can be different for different type of perturbations..Since atomic clocks are very sensitive devices, based on coherent states (A coherent state tends to loose coherence after interacting). One question can arise (from a lot of questions) which is why cosmic neutrinos are not affecting these clocks? The answer to this question requir...

Phase locking and multiple oscillating attractors for the coupled mammalian clock and cell cycle.

Science.gov (United States)

Feillet, Céline; Krusche, Peter; Tamanini, Filippo; Janssens, Roel C; Downey, Mike J; Martin, Patrick; Teboul, Michèle; Saito, Shoko; Lévi, Francis A; Bretschneider, Till; van der Horst, Gijsbertus T J; Delaunay, Franck; Rand, David A

2014-07-08

Daily synchronous rhythms of cell division at the tissue or organism level are observed in many species and suggest that the circadian clock and cell cycle oscillators are coupled. For mammals, despite known mechanistic interactions, the effect of such coupling on clock and cell cycle progression, and hence its biological relevance, is not understood. In particular, we do not know how the temporal organization of cell division at the single-cell level produces this daily rhythm at the tissue level. Here we use multispectral imaging of single live cells, computational methods, and mathematical modeling to address this question in proliferating mouse fibroblasts. We show that in unsynchronized cells the cell cycle and circadian clock robustly phase lock each other in a 1:1 fashion so that in an expanding cell population the two oscillators oscillate in a synchronized way with a common frequency. Dexamethasone-induced synchronization reveals additional clock states. As well as the low-period phase-locked state there are distinct coexisting states with a significantly higher period clock. Cells transition to these states after dexamethasone synchronization. The temporal coordination of cell division by phase locking to the clock at a single-cell level has significant implications because disordered circadian function is increasingly being linked to the pathogenesis of many diseases, including cancer.

A low-power wave union TDC implemented in FPGA

International Nuclear Information System (INIS)

Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

2011-01-01

A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

Directory of Open Access Journals (Sweden)

A. Kishore Kumar

2013-01-01

Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

A low phase noise microwave frequency synthesis for a high-performance cesium vapor cell atomic clock

Energy Technology Data Exchange (ETDEWEB)

François, B.; Boudot, R. [FEMTO-ST, CNRS, Université de Franche-Comté, 26 chemin de l' Epitaphe, 25030 Besançon (France); Calosso, C. E. [INRIM, Strada delle Cacce 91, 10135 Torino (Italy); Danet, J. M. [LNE-SYRTE, Observatoire de Paris, CNRS-UPMC, 61 avenue de l' Observatoire, 75014 Paris (France)

2014-09-15

We report the development, absolute phase noise, and residual phase noise characterization of a 9.192 GHz microwave frequency synthesis chain devoted to be used as a local oscillator in a high-performance cesium vapor cell atomic clock based on coherent population trapping (CPT). It is based on frequency multiplication of an ultra-low phase noise 100 MHz oven-controlled quartz crystal oscillator using a nonlinear transmission line-based chain. Absolute phase noise performances of the 9.192 GHz output signal are measured to be −42, −100, −117 dB rad{sup 2}/Hz and −129 dB rad{sup 2}/Hz at 1 Hz, 100 Hz, 1 kHz, and 10 kHz offset frequencies, respectively. Compared to current results obtained in a state-of-the-art CPT-based frequency standard developed at LNE-SYRTE, this represents an improvement of 8 dB and 10 dB at f = 166 Hz and f = 10 kHz, respectively. With such performances, the expected Dick effect contribution to the atomic clock short term frequency stability is reported at a level of 6.2 × 10{sup −14} at 1 s integration time, that is a factor 3 higher than the atomic clock shot noise limit. Main limitations are pointed out.

Latest design of gate valves

Energy Technology Data Exchange (ETDEWEB)

Kurzhofer, U.; Stolte, J.; Weyand, M.

1996-12-01

Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

Robustness against parametric noise of nonideal holonomic gates

International Nuclear Information System (INIS)

Lupo, Cosmo; Aniello, Paolo; Napolitano, Mario; Florio, Giuseppe

2007-01-01

Holonomic gates for quantum computation are commonly considered to be robust against certain kinds of parametric noise, the cause of this robustness being the geometric character of the transformation achieved in the adiabatic limit. On the other hand, the effects of decoherence are expected to become more and more relevant when the adiabatic limit is approached. Starting from the system described by Florio et al. [Phys. Rev. A 73, 022327 (2006)], here we discuss the behavior of nonideal holonomic gates at finite operational time, i.e., long before the adiabatic limit is reached. We have considered several models of parametric noise and studied the robustness of finite-time gates. The results obtained suggest that the finite-time gates present some effects of cancellation of the perturbations introduced by the noise which mimic the geometrical cancellation effect of standard holonomic gates. Nevertheless, a careful analysis of the results leads to the conclusion that these effects are related to a dynamical instead of a geometrical feature

Robustness against parametric noise of nonideal holonomic gates

Science.gov (United States)

Lupo, Cosmo; Aniello, Paolo; Napolitano, Mario; Florio, Giuseppe

2007-07-01

Holonomic gates for quantum computation are commonly considered to be robust against certain kinds of parametric noise, the cause of this robustness being the geometric character of the transformation achieved in the adiabatic limit. On the other hand, the effects of decoherence are expected to become more and more relevant when the adiabatic limit is approached. Starting from the system described by Florio [Phys. Rev. A 73, 022327 (2006)], here we discuss the behavior of nonideal holonomic gates at finite operational time, i.e., long before the adiabatic limit is reached. We have considered several models of parametric noise and studied the robustness of finite-time gates. The results obtained suggest that the finite-time gates present some effects of cancellation of the perturbations introduced by the noise which mimic the geometrical cancellation effect of standard holonomic gates. Nevertheless, a careful analysis of the results leads to the conclusion that these effects are related to a dynamical instead of a geometrical feature.

Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

Science.gov (United States)

Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

2018-06-01

The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

Top-gate microcrystalline silicon TFTs processed at low temperature (<200 deg. C)

International Nuclear Information System (INIS)

Saboundji, A.; Coulon, N.; Gorin, A.; Lhermite, H.; Mohammed-Brahim, T.; Fonrodona, M.; Bertomeu, J.; Andreu, J.

2005-01-01

N-type as well P-type top-gate microcrystalline silicon thin film transistors (TFTs) are fabricated on glass substrates at a maximum temperature of 200 deg. C. The active layer is an undoped μc-Si film, 200 nm thick, deposited by Hot-Wire Chemical Vapor. The drain and source regions are highly phosphorus (N-type TFTs) or boron (P-type TFTs)-doped μc-films deposited by HW-CVD. The gate insulator is a silicon dioxide film deposited by RF sputtering. Al-SiO 2 -N type c-Si structures using this insulator present low flat-band voltage,-0.2 V, and low density of states at the interface D it =6.4x10 10 eV -1 cm -2 . High field effect mobility, 25 cm 2 /V s for electrons and 1.1 cm 2 /V s for holes, is obtained. These values are very high, particularly the hole mobility that was never reached previously

Blackbody radiation shift of the Ga+ clock transition

International Nuclear Information System (INIS)

Cheng, Yongjun; Mitroy, J

2013-01-01

The blackbody radiation shift of the Ga + clock transition is computed to be −0.0140 ± 0.0062 Hz at 300 K. The small shift is consistent with the blackbody radiation shifts of the clock transitions of other group III ions which are of a similar size. The polarizabilities of the Ga + states were computed using the configuration interaction method with an underlying semi-empirical core potential. Quadrupole and non-adiabatic dipole polarizabilities were also computed. A byproduct of the analysis involved calculations of the low-lying spectrum and oscillator strengths, including polarizabilities, of the Ga 2+ ion. (paper)

Philanthropy and the nation-state in global health: The Gates Foundation in India.

Science.gov (United States)

Mahajan, Manjari

2017-12-15

In recent years, philanthropic actors such as the Gates Foundation have been understood as commanding sweeping influence in global health. They have been associated with the outsourcing of public health services, shifting of policy priorities, and the eventual sidelining of national governments. This article makes a different argument about the impact of global philanthropic actors. It focuses on the work of the Gates Foundation in India over the last decade and a half, tracing how the foundation initially circumvented the national government but then moved on to a discourse of partnership. Ironically, after an early discounting of the role of the government, the foundation later sought to transition its programmes to the state. The foundation's evolving trajectory reflects its experiences on the ground and also the difficulties of realising its original ambitions. While the foundation's work in India is marked by ebbs and flows, the state's institutions remain constant. The article argues that there is not always a straightforward marginalisation of the government vis-à-vis global philanthropic actors. Actors such as the Gates Foundation, perceived as enormously powerful in global health institutions in Geneva and New York, may have a far more qualified impact in large developing countries such as India.

A high performance gate drive for large gate turn off thyristors

Energy Technology Data Exchange (ETDEWEB)

Szilagyi, C.P.

1993-01-01

Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.

Science.gov (United States)

Kazemi, Mohammad

2017-11-10

The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.

Measurement scheme for purity based on two two-body gates

Science.gov (United States)

Nakazato, H.; Tanaka, T.; Yuasa, K.; Florio, G.; Pascazio, S.

2012-04-01

A scheme for measuring the purity of a quantum system with a finite number of levels is presented. The method makes use of two swap gates and hinges only on measurements performed on a reference system, prepared in a certain pure state and coupled with the target system. Neither tomographic methods, with the complete reconstruction of the state, nor interferometric setups are needed.

Resistor Extends Life Of Battery In Clocked CMOS Circuit

Science.gov (United States)

Wells, George H., Jr.

1991-01-01

Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

Very fast, high peak-power, planar triode amplifiers for driving optical gates

International Nuclear Information System (INIS)

Howland, M.M.; Davis, S.J.; Gagnon, W.L.

1979-01-01

Recent extensions of the peak power capabilities of planar triodes have made possible the latter's use as very fast pulse amplifiers, to drive optical gates within high-power Nd:glass laser chains. These pulse amplifiers switch voltages in the 20 kV range with rise times of a few nanoseconds, into crystal optical gates that are essentially capacitive loads. This paper describes a simplified procedure for designing these pulse amplifiers. It further outlines the use of bridged-T constant resistance networks to transform load capacitance into pure resistance, independent of frequency

Water Energy Resources of the United States with Emphasis on Low Head/Low Power Resources: Appendix A - Assessment Results by Hydrologic Region

Energy Technology Data Exchange (ETDEWEB)

Hall, Douglas [Idaho National Lab. (INL), Idaho Falls, ID (United States). Idaho National Engineering and Environmental Lab. (INEEL)

2004-04-01

Analytical assessments of the water energy resources in the 20 hydrologic regions of the United States were performed using state-of-the-art digital elevation models and geographic information system tools. The principal focus of the study was on low head (less than 30 ft)/low power (less than 1 MW) resources in each region. The assessments were made by estimating the power potential of all the stream segments in a region, which averaged 2 miles in length. These calculations were performed using hydrography and hydraulic heads that were obtained from the U.S. Geological Survey’s Elevation Derivatives for National Applications dataset and stream flow predictions from a regression equation or equations developed specifically for the region. Stream segments excluded from development and developed hydropower were accounted for to produce an estimate of total available power potential. The total available power potential was subdivided into high power (1 MW or more), high head (30 ft or more)/low power, and low head/low power total potentials. The low head/low power potential was further divided to obtain the fractions of this potential corresponding to the operating envelopes of three classes of hydropower technologies: conventional turbines, unconventional systems, and microhydro (less than 100 kW). Summing information for all the regions provided total power potential in various power classes for the entire United States. Distribution maps show the location and concentrations of the various classes of low power potential. No aspect of the feasibility of developing these potential resources was evaluated. Results for each of the 20 hydrologic regions are presented in Appendix A

Decoding spatiotemporal spike sequences via the finite state automata dynamics of spiking neural networks

International Nuclear Information System (INIS)

Jin, Dezhe Z

2008-01-01

Temporally complex stimuli are encoded into spatiotemporal spike sequences of neurons in many sensory areas. Here, we describe how downstream neurons with dendritic bistable plateau potentials can be connected to decode such spike sequences. Driven by feedforward inputs from the sensory neurons and controlled by feedforward inhibition and lateral excitation, the neurons transit between UP and DOWN states of the membrane potentials. The neurons spike only in the UP states. A decoding neuron spikes at the end of an input to signal the recognition of specific spike sequences. The transition dynamics is equivalent to that of a finite state automaton. A connection rule for the networks guarantees that any finite state automaton can be mapped into the transition dynamics, demonstrating the equivalence in computational power between the networks and finite state automata. The decoding mechanism is capable of recognizing an arbitrary number of spatiotemporal spike sequences, and is insensitive to the variations of the spike timings in the sequences

Silicon, germanium, and III-V-based tunneling devices for low-power applications

Science.gov (United States)

Smith, Joshua T.

While the scaling of transistor dimensions has kept pace with Moore's Law, the voltages applied to these devices have not scaled in tandem, giving rise to ever-increasing power/heating challenges in state-of-the-art integrated circuits. A primary reason for this scaling mismatch is due to the thermal limit---the 60 mV minimum required at room temperature to change the current through the device by one order of magnitude. This voltage scaling limitation is inherent in devices that rely on the mechanism of thermal emission of charge carriers over a gate-controlled barrier to transition between the ON- and OFF-states, such as in the case of conventional CMOS-based technologies. To overcome this voltage scaling barrier, several steep-slope device concepts have been pursued that have experimentally demonstrated sub-60-mV/decade operation since 2004, including the tunneling-field effect transistor (TFET), impact ionization metal-oxide-semiconductor (IMOS), suspended-gate FET (SG-FET), and ferroelectric FET (Fe-FET). These reports have excited strong efforts within the semiconductor research community toward the realization of a low-power device that will support continued scaling efforts, while alleviating the heating issues prevalent in modern computer chips. Literature is replete with claims of sub-60-mV/decade operation, but often with neglect to other voltage scaling factors that offset this result. Ideally, a low-power device should be able to attain sub-60-mV/decade inverse subthreshold slopes (S) employing low supply and gate voltages with a foreseeable path toward integration. This dissertation describes the experimental development and realization of CMOS-compatible processes to enhance tunneling efficiency in Si and Si/Ge nanowire (NW) TFETs for improved average S (S avg) and ON-currents (ION), and a novel, III-V-based tunneling device alternative is also proposed. After reviewing reported efforts on the TFET, IMOS, and SG-FET, the TFET is highlighted as the

The development of gate monitor for low level radioactive waste

International Nuclear Information System (INIS)

Fujisawa, Morio; Watanabe, Michito; Kato, Tatsuo

1994-01-01

Low-level radioactive waste (LLW) generated from nuclear power plants in Japan, have been deposited in the yard of each power plant. At present, it is stored in about 500,000 drum cans (200l each). These drum cans are carried to Mutsu-ogawara Port by special transport ships and then transferred to Rokkasho LLW transport trucks (special vehicles) for storage. The gate monitor is used to automatically measure the dose rate on the vehicles loaded with transport vessels from a remote location, to ensure the safe transportation from Mutsu-ogawara Port the Burying Center. It is a new system which has been developed for effective measurement of dose rate on a number of transport vessels in a short time. This system is the first in the world for measuring dose rate on vehicles. Such a system cannot be found in any country of the world. (author)

Efficient Nonlocal M-Control and N-Target Controlled Unitary Gate Using Non-symmetric GHZ States

Science.gov (United States)

Chen, Li-Bing; Lu, Hong

2018-03-01

Efficient local implementation of a nonlocal M-control and N-target controlled unitary gate is considered. We first show that with the assistance of two non-symmetric qubit(1)-qutrit(N) Greenberger-Horne-Zeilinger (GHZ) states, a nonlocal 2-control and N-target controlled unitary gate can be constructed from 2 local two-qubit CNOT gates, 2 N local two-qutrit conditional SWAP gates, N local qutrit-qubit controlled unitary gates, and 2 N single-qutrit gates. At each target node, the two third levels of the two GHZ target qutrits are used to expose one and only one initial computational state to the local qutrit-qubit controlled unitary gate, instead of being used to hide certain states from the conditional dynamics. This scheme can be generalized straightforwardly to implement a higher-order nonlocal M-control and N-target controlled unitary gate by using M non-symmetric qubit(1)-qutrit(N) GHZ states as quantum channels. Neither the number of the additional levels of each GHZ target particle nor that of single-qutrit gates needs to increase with M. For certain realistic physical systems, the total gate time may be reduced compared with that required in previous schemes.

Reduced Voltage Scaling in Clock Distribution Networks

Directory of Open Access Journals (Sweden)

Khader Mohammad

2009-01-01

Full Text Available We propose a novel circuit technique to generate a reduced voltage swing (RVS signals for active power reduction on main buses and clocks. This is achieved without performance degradation, without extra power supply requirement, and with minimum area overhead. The technique stops the discharge path on the net that is swinging low at a certain voltage value. It reduces active power on the target net by as much as 33% compared to traditional full swing signaling. The logic 0 voltage value is programmable through control bits. If desired, the reduced-swing mode can also be disabled. The approach assumes that the logic 0 voltage value is always less than the threshold voltage of the nMOS receivers, which eliminate the need of the low to high voltage translation. The reduced noise margin and the increased leakage on the receiver transistors using this approach have been addressed through the selective usage of multithreshold voltage (MTV devices and the programmability of the low voltage value.

Carbon nanotube feedback-gate field-effect transistor: suppressing current leakage and increasing on/off ratio.

Science.gov (United States)

Qiu, Chenguang; Zhang, Zhiyong; Zhong, Donglai; Si, Jia; Yang, Yingjun; Peng, Lian-Mao

2015-01-27

Field-effect transistors (FETs) based on moderate or large diameter carbon nanotubes (CNTs) usually suffer from ambipolar behavior, large off-state current and small current on/off ratio, which are highly undesirable for digital electronics. To overcome these problems, a feedback-gate (FBG) FET structure is designed and tested. This FBG FET differs from normal top-gate FET by an extra feedback-gate, which is connected directly to the drain electrode of the FET. It is demonstrated that a FBG FET based on a semiconducting CNT with a diameter of 1.5 nm may exhibit low off-state current of about 1 × 10(-13) A, high current on/off ratio of larger than 1 × 10(8), negligible drain-induced off-state leakage current, and good subthreshold swing of 75 mV/DEC even at large source-drain bias and room temperature. The FBG structure is promising for CNT FETs to meet the standard for low-static-power logic electronics applications, and could also be utilized for building FETs using other small band gap semiconductors to suppress leakage current.

Poly(4-vinylphenol) gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Science.gov (United States)

Fan, Ching-Lin; Shang, Ming-Chi; Hsia, Mao-Yuan; Wang, Shea-Jue; Huang, Bohr-Ran; Lee, Win-Der

2016-03-01

A Microwave-Induction Heating (MIH) scheme is proposed for the poly(4-vinylphenol) (PVP) gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Design and simulation of a fast Josephson junction on-chip gated clock for frequency and time analysis

International Nuclear Information System (INIS)

Ruby, R.C.

1991-01-01

This paper reports that as the sophistication and speed of digital communication systems increase, there is a corresponding demand for more sophisticated and faster measurement instruments. One such instrument new on the market is the HP 5371A Frequency and Time Interval Analyzer (FTIA). Such an instrument is analogous to a conventional oscilloscope. Whereas the oscilloscope measures waveform amplitudes as a function of time, the FTIA measures phase, frequency, or timing events as functions of time. These applications are useful in such diverse areas as spread-spectrum radar, chirp filter designs, disk-head evaluation, and timing jitter analysis. The on-chip clock designed for this application uses a single Josephson Junction as the clock and a resonator circuit to fix the frequency. A zero-crossing detector is used to start and stop the clock. A SFQ counter is used to count the pulses generated by the clock and a reset circuit is used to reset the clock. Extensive simulations and modeling have been done based on measured values obtained from our Nb/Al 2 O 3 /Al/Nb process

One-way gates based on EPR, GHZ and decoherence-free states of W class

International Nuclear Information System (INIS)

Basharov, A.M.; Gorbachev, V.N.; Trubilko, A.I.; Yakovleva, E.S.

2009-01-01

The logical gates using quantum measurement as a primitive of quantum computation are considered. It is found that these gates achieved with EPR, GHZ and W entangled states have the same structure, allow encoding the classical information into states of quantum system and can perform any calculations. A particular case of decoherence-free W states is discussed as in this very case the logical gate is decoherence-free.

Study of a low power dissipation, miniature laser-pumped rubidium frequency standard

Institute of Scientific and Technical Information of China (English)

Liu Guo-Bin; Zhao Feng; Gu Si-Hong

2009-01-01

This paper studies a miniature low power consumption laser-pumped atom vapour cell clock scheme. Pumping 87Rb with a vertical cavity surface emitting laser diode pump and locking the laser frequency on a Doppler-broadened spectral line,it records a 5×10-11τ-1/2 (τ<500 s) frequency stability with a table-top system in a primary experiment.The study reveals that the evaluated scheme is at the level of 2.7 watts power consumption,90 cm3 volume and 10-12τ- 1/2 short-term frequency stability.

A capacitor cross-coupled common-gate low-noise amplifier

NARCIS (Netherlands)

Zhuo, W.; Li, X.; Shekhar, S.; Embabi, S.H.K.; Pineda de Gyvez, J.; Allstot, D.J.; Sanchez-Sinencio, E.

2005-01-01

The conventional common-gate low-noise amplifier (CGLNA) exhibits a relatively high noise figure (NF) at low operating frequencies relative to the MOSFET fT, which has limited its adoption notwithstanding its superior linearity, input matching, and stability compared to the inductively degenerated

Time without clocks - an attempt

International Nuclear Information System (INIS)

Karpman, G.

1978-01-01

A definition of time intervals separating two states of systems of elementary particles and observers is attempted. The definition is founded on the notion of instant state of the system and uses no information connected with the use of a clock. Applying the definition to a classical clock and to a sample of unstable particles, results are obtained in agreement with experiment. However, if the system contains 'few' elementary particles, the properties of the time interval present some different features. (author)

Initial atomic coherences and Ramsey frequency pulling in fountain clocks

Science.gov (United States)

Gerginov, Vladislav; Nemitz, Nils; Weyers, Stefan

2014-09-01

In the uncertainty budget of primary atomic cesium fountain clocks, evaluations of frequency-pulling shifts of the hyperfine clock transition caused by unintentional excitation of its nearby transitions (Rabi and Ramsey pulling) have been based so far on an approach developed for cesium beam clocks. We re-evaluate this type of frequency pulling in fountain clocks and pay particular attention to the effect of initial coherent atomic states. We find significantly enhanced frequency shifts caused by Ramsey pulling due to sublevel population imbalance and corresponding coherences within the state-selected hyperfine component of the initial atom ground state. Such shifts are experimentally investigated in an atomic fountain clock and quantitative agreement with the predictions of the model is demonstrated.

SiC Power MOSFET with Improved Gate Dielectric

Energy Technology Data Exchange (ETDEWEB)

Sbrockey, Nick M. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Tompa, Gary S. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Spencer, Michael G. [Structured Materials Industries, Inc., Piscataway, NJ (United States); Chandrashekhar, Chandra M.V. S. [Structured Materials Industries, Inc., Piscataway, NJ (United States)

2010-08-23

In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

Theory of the synchronous motion of an array of floating flap gates oscillating wave surge converter

Science.gov (United States)

Michele, Simone; Sammarco, Paolo; d'Errico, Michele

2016-08-01

We consider a finite array of floating flap gates oscillating wave surge converter (OWSC) in water of constant depth. The diffraction and radiation potentials are solved in terms of elliptical coordinates and Mathieu functions. Generated power and capture width ratio of a single gate excited by incoming waves are given in terms of the radiated wave amplitude in the far field. Similar to the case of axially symmetric absorbers, the maximum power extracted is shown to be directly proportional to the incident wave characteristics: energy flux, angle of incidence and wavelength. Accordingly, the capture width ratio is directly proportional to the wavelength, thus giving a design estimate of the maximum efficiency of the system. We then compare the array and the single gate in terms of energy production. For regular waves, we show that excitation of the out-of-phase natural modes of the array increases the power output, while in the case of random seas we show that the array and the single gate achieve the same efficiency.

Ionic screening effect on low-frequency drain current fluctuations in liquid-gated nanowire FETs

International Nuclear Information System (INIS)

Lu, Ming-Pei; Vire, Eric; Montès, Laurent

2015-01-01

The ionic screening effect plays an important role in determining the fundamental surface properties within liquid–semiconductor interfaces. In this study, we investigated the characteristics of low-frequency drain current noise in liquid-gated nanowire (NW) field effect transistors (FETs) to obtain physical insight into the effect of ionic screening on low-frequency current fluctuation. When the NW FET was operated close to the gate voltage corresponding to the maximum transconductance, the magnitude of the low-frequency noise for the NW exposed to a low-ionic-strength buffer (0.001 M) was approximately 70% greater than that when exposed to a high-ionic-strength buffer (0.1 M). We propose a noise model, considering the charge coupling efficiency associated with the screening competition between the electrolyte buffer and the NW, to describe the ionic screening effect on the low-frequency drain current noise in liquid-gated NW FET systems. This report not only provides a physical understanding of the ionic screening effect behind the low-frequency current noise in liquid-gated FETs but also offers useful information for developing the technology of NW FETs with liquid-gated architectures for application in bioelectronics, nanosensors, and hybrid nanoelectronics. (paper)

Power flow as a complement to statistical energy analysis and finite element analysis

Science.gov (United States)

Cuschieri, J. M.

1987-01-01

Present methods of analysis of the structural response and the structure-borne transmission of vibrational energy use either finite element (FE) techniques or statistical energy analysis (SEA) methods. The FE methods are a very useful tool at low frequencies where the number of resonances involved in the analysis is rather small. On the other hand SEA methods can predict with acceptable accuracy the response and energy transmission between coupled structures at relatively high frequencies where the structural modal density is high and a statistical approach is the appropriate solution. In the mid-frequency range, a relatively large number of resonances exist which make finite element method too costly. On the other hand SEA methods can only predict an average level form. In this mid-frequency range a possible alternative is to use power flow techniques, where the input and flow of vibrational energy to excited and coupled structural components can be expressed in terms of input and transfer mobilities. This power flow technique can be extended from low to high frequencies and this can be integrated with established FE models at low frequencies and SEA models at high frequencies to form a verification of the method. This method of structural analysis using power flo and mobility methods, and its integration with SEA and FE analysis is applied to the case of two thin beams joined together at right angles.

Improvement of an Atomic Clock using Squeezed Vacuum

DEFF Research Database (Denmark)

Kruse, I.; Lange, K; Peise, Jan

2016-01-01

, the vacuum noise restricts the precision of the interferometer to the standard quantum limit (SQL). Here, we propose and experimentally demonstrate a novel clock configuration that surpasses the SQL by squeezing the vacuum in the empty input state. We create a squeezed vacuum state containing an average of 0.......75 atoms to improve the clock sensitivity of 10000 atoms by 2.05+0.34−0.37  dB. The SQL poses a significant limitation for today’s microwave fountain clocks, which serve as the main time reference. We evaluate the major technical limitations and challenges for devising a next generation of fountain clocks...

Improvement of breakdown characteristics of an AlGaN/GaN HEMT with a U-type gate foot for millimeter-wave power application

International Nuclear Information System (INIS)

Kong Xin; Wei Ke; Liu Guo-Guo; Liu Xin-Yu

2012-01-01

In this study, the physics-based device simulation tool Silvaco ATLAS is used to characterize the electrical properties of an AlGaN/GaN high electron mobility transistor (HEMT) with a U-type gate foot. The U-gate AlGaN/GaN HEMT mainly features a gradually changed sidewall angle, which effectively mitigates the electric field in the channel, thus obtaining enhanced off-state breakdown characteristics. At the same time, only a small additional gate capacitance and decreased gate resistance ensure excellent RF characteristics for the U-gate device. U-gate AlGaN/GaN HEMTs are feasible through adjusting the etching conditions of an inductively coupled plasma system, without introducing any extra process steps. The simulation results are confirmed by experimental measurements. These features indicate that U-gate AlGaN/GaN HEMTs might be promising candidates for use in millimeter-wave power applications. (interdisciplinary physics and related areas of science and technology)

Poly(4-vinylphenol gate insulator with cross-linking using a rapid low-power microwave induction heating scheme for organic thin-film-transistors

Directory of Open Access Journals (Sweden)

Ching-Lin Fan

2016-03-01

Full Text Available A Microwave-Induction Heating (MIH scheme is proposed for the poly(4-vinylphenol (PVP gate insulator cross-linking process to replace the traditional oven heating cross-linking process. The cross-linking time is significantly decreased from 1 h to 5 min by heating the metal below the PVP layer using microwave irradiation. The necessary microwave power was substantially reduced to about 50 W by decreasing the chamber pressure. The MIH scheme is a good candidate to replace traditional thermal heating for cross-linking of PVP as the gate insulator for organic thin-film-transistors.

Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

International Nuclear Information System (INIS)

Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

2011-01-01

An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

Laser-assisted electron emission from gated field-emitters

CERN Document Server

Ishizuka, H; Yokoo, K; Mimura, H; Shimawaki, H; Hosono, A

2002-01-01

Enhancement of electron emission by illumination of gated field-emitters was studied using a 100 mW cw YAG laser at a wavelength of 532 nm, intensities up to 10 sup 7 W/m sup 2 and mechanically chopped with a rise time of 4 mu s. When shining an array of 640 silicon emitters, the emission current responded quickly to on-off of the laser. The increase of the emission current was proportional to the basic emission current at low gate voltages, but it was saturated at approx 3 mu A as the basic current approached 100 mu A with the increase of gate voltage. The emission increase was proportional to the square root of laser power at low gate voltages and to the laser power at elevated gate voltages. For 1- and 3-tip silicon emitters, the rise and fall of the current due to on-off of the laser showed a significant time lag. The magnitude of emission increase was independent of the position of laser spot on the emitter base and reached 2 mu A at a basic current of 5 mu A without showing signs of saturation. The mech...

A novel gate and drain engineered charge plasma tunnel field-effect transistor for low sub-threshold swing and ambipolar nature

Science.gov (United States)

Yadav, Dharmendra Singh; Raad, Bhagwan Ram; Sharma, Dheeraj

2016-12-01

In this paper, we focus on the improvement of figures of merit for charge plasma based tunnel field-effect transistor (TFET) in terms of ON-state current, threshold voltage, sub-threshold swing, ambipolar nature, and gate to drain capacitance which provides better channel controlling of the device with improved high frequency response at ultra-low supply voltages. Regarding this, we simultaneously employ work function engineering on the drain and gate electrode of the charge plasma TFET. The use of gate work function engineering modulates the barrier on the source/channel interface leads to improvement in the ON-state current, threshold voltage, and sub-threshold swing. Apart from this, for the first time use of work function engineering on the drain electrode increases the tunneling barrier for the flow of holes on the drain/channel interface, it results into suppression of ambipolar behavior. The lowering of gate to drain capacitance therefore enhanced high frequency parameters. Whereas, the presence of dual work functionality at the gate electrode and over the drain region improves the overall performance of the charge plasma based TFET.

Clock and trigger synchronization between several chassis of digital data acquisition modules

Energy Technology Data Exchange (ETDEWEB)

Hennig, W. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States)]. E-mail: whennig@xia.com; Tan, H. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Walby, M. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Grudberg, P. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Fallu-Labruyere, A. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Warburton, W.K. [XIA LLC, 31057 Genstar Road, Hayward, CA 94544 (United States); Vaman, C. [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States); Starosta, K. [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States); Miller, D. [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States)

2007-08-15

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size. The readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis. The data acquisition system is intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less than 1 ns, and can be extended to a larger number of chassis if desired.

Clock and trigger synchronization between several chassis of digital data acquisition modules

Science.gov (United States)

Hennig, W.; Tan, H.; Walby, M.; Grudberg, P.; Fallu-Labruyere, A.; Warburton, W. K.; Vaman, C.; Starosta, K.; Miller, D.

2007-08-01

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size. The readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis. The data acquisition system is intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less than 1 ns, and can be extended to a larger number of chassis if desired.

Clock and trigger synchronization between several chassis of digital data acquisition modules

International Nuclear Information System (INIS)

Hennig, W.; Tan, H.; Walby, M.; Grudberg, P.; Fallu-Labruyere, A.; Warburton, W.K.; Vaman, C.; Starosta, K.; Miller, D.

2007-01-01

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size. The readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis. The data acquisition system is intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less than 1 ns, and can be extended to a larger number of chassis if desired

Prediction of GNSS satellite clocks

International Nuclear Information System (INIS)

Broederbauer, V.

2010-01-01

This thesis deals with the characterisation and prediction of GNSS-satellite-clocks. A prerequisite to develop powerful algorithms for the prediction of clock-corrections is the thorough study of the behaviour of the different clock-types of the satellites. In this context the predicted part of the IGU-clock-corrections provided by the Analysis Centers (ACs) of the IGS was compared to the IGS-Rapid-clock solutions to determine reasonable estimates of the quality of already existing well performing predictions. For the shortest investigated interval (three hours) all ACs obtain almost the same accuracy of 0,1 to 0,4 ns. For longer intervals the individual predictions results start to diverge. Thus, for a 12-hours- interval the differences range from nearly 10 ns (GFZ, CODE) until up to some 'tens of ns'. Based on the estimated clock corrections provided via the IGS Rapid products a simple quadratic polynomial turns out to be sufficient to describe the time series of Rubidium-clocks. On the other hand Cesium-clocks show a periodical behaviour (revolution period) with an amplitude of up to 6 ns. A clear correlation between these amplitudes and the Sun elevation angle above the orbital planes can be demonstrated. The variability of the amplitudes is supposed to be caused by temperature-variations affecting the oscillator. To account for this periodical behaviour a quadratic polynomial with an additional sinus-term was finally chosen as prediction model both for the Cesium as well as for the Rubidium clocks. The three polynomial-parameters as well as amplitude and phase shift of the periodic term are estimated within a least-square-adjustment by means of program GNSS-VC/static. Input-data are time series of the observed part of the IGU clock corrections. With the estimated parameters clock-corrections are predicted for various durations. The mean error of the prediction of Rubidium-clock-corrections for an interval of six hours reaches up to 1,5 ns. For the 12-hours

Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

Science.gov (United States)

Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

2018-04-01

Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

Technology breakthroughs in high performance metal-oxide-semiconductor devices for ultra-high density, low power non-volatile memory applications

Science.gov (United States)

Hong, Augustin Jinwoo

Non-volatile memory devices have attracted much attention because data can be retained without power consumption more than a decade. Therefore, non-volatile memory devices are essential to mobile electronic applications. Among state of the art non-volatile memory devices, NAND flash memory has earned the highest attention because of its ultra-high scalability and therefore its ultra-high storage capacity. However, human desire as well as market competition requires not only larger storage capacity but also lower power consumption for longer battery life time. One way to meet this human desire and extend the benefits of NAND flash memory is finding out new materials for storage layer inside the flash memory, which is called floating gate in the state of the art flash memory device. In this dissertation, we study new materials for the floating gate that can lower down the power consumption and increase the storage capacity at the same time. To this end, we employ various materials such as metal nanodot, metal thin film and graphene incorporating complementary-metal-oxide-semiconductor (CMOS) compatible processes. Experimental results show excellent memory effects at relatively low operating voltages. Detailed physics and analysis on experimental results are discussed. These new materials for data storage can be promising candidates for future non-volatile memory application beyond the state of the art flash technologies.

Faraday-Shielded dc Stark-Shift-Free Optical Lattice Clock

Science.gov (United States)

Beloy, K.; Zhang, X.; McGrew, W. F.; Hinkley, N.; Yoon, T. H.; Nicolodi, D.; Fasano, R. J.; Schäffer, S. A.; Brown, R. C.; Ludlow, A. D.

2018-05-01

We demonstrate the absence of a dc Stark shift in an ytterbium optical lattice clock. Stray electric fields are suppressed through the introduction of an in-vacuum Faraday shield. Still, the effectiveness of the shielding must be experimentally assessed. Such diagnostics are accomplished by applying high voltage to six electrodes, which are grounded in normal operation to form part of the Faraday shield. Our measurements place a constraint on the dc Stark shift at the 10-20 level, in units of the clock frequency. Moreover, we discuss a potential source of error in strategies to precisely measure or cancel nonzero dc Stark shifts, attributed to field gradients coupled with the finite spatial extent of the lattice-trapped atoms. With this consideration, we find that Faraday shielding, complemented with experimental validation, provides both a practically appealing and effective solution to the problem of dc Stark shifts in optical lattice clocks.

Low-power crystal and MEMS oscillators the experience of watch developments

CERN Document Server

Eric Vittoz

2010-01-01

Electronic oscillators using an electromechanical device as a frequency reference are irreplaceable components of systems-on-chip for time-keeping, carrier frequency generation and digital clock generation. With their excellent frequency stability and very large quality factor Q, quartz crystal resonators have been the dominant solution for more than 70 years. But new possibilities are now offered by micro-electro-mechanical (MEM) resonators, that have a qualitatively identical equivalent electrical circuit. Low-Power Crystal and MEMS Oscillators concentrates on the analysis and design of the most important schemes of integrated oscillator circuits. It explains how these circuits can be optimized by best exploiting the very high Q of the resonator to achieve the minimum power consumption compatible with the requirements on frequency stability and phase noise. The author has 40 years of experience in designing very low-power, high-performance quartz oscillators for watches and other battery operated systems an...

Micro Mercury Ion Clock (MMIC)

Data.gov (United States)

National Aeronautics and Space Administration — Demonstrate micro clock based on trapped Hg ions with more than 10x size reduction and power; Fractional frequency stability at parts per 1014 level, adequate for...

Finite-State Complexity and the Size of Transducers

Directory of Open Access Journals (Sweden)

Cristian Calude

2010-08-01

Full Text Available Finite-state complexity is a variant of algorithmic information theory obtained by replacing Turing machines with finite transducers. We consider the state-size of transducers needed for minimal descriptions of arbitrary strings and, as our main result, we show that the state-size hierarchy with respect to a standard encoding is infinite. We consider also hierarchies yielded by more general computable encodings.

High-Dimensional Single-Photon Quantum Gates: Concepts and Experiments.

Science.gov (United States)

Babazadeh, Amin; Erhard, Manuel; Wang, Feiran; Malik, Mehul; Nouroozi, Rahman; Krenn, Mario; Zeilinger, Anton

2017-11-03

Transformations on quantum states form a basic building block of every quantum information system. From photonic polarization to two-level atoms, complete sets of quantum gates for a variety of qubit systems are well known. For multilevel quantum systems beyond qubits, the situation is more challenging. The orbital angular momentum modes of photons comprise one such high-dimensional system for which generation and measurement techniques are well studied. However, arbitrary transformations for such quantum states are not known. Here we experimentally demonstrate a four-dimensional generalization of the Pauli X gate and all of its integer powers on single photons carrying orbital angular momentum. Together with the well-known Z gate, this forms the first complete set of high-dimensional quantum gates implemented experimentally. The concept of the X gate is based on independent access to quantum states with different parities and can thus be generalized to other photonic degrees of freedom and potentially also to other quantum systems.

A Note on Powers in Finite Fields

DEFF Research Database (Denmark)

Aabrandt, Andreas; Hansen, Vagn Lundsgaard

2016-01-01

The study of solutions to polynomial equations over finite fields has a long history in mathematics and is an interesting area of contemporary research. In recent years the subject has found important applications in the modelling of problems from applied mathematical fields such as signal analys...... for squares in odd prime fields, giving it a formulation which is apt for generalization to arbitrary finite fields and powers. Our proof uses algebra rather than classical number theory, which makes it convenient when presenting basic methods of applied algebra in the classroom....

Removing the Restrictions Imposed on Finite State Machines ...

African Journals Online (AJOL)

This study determines an effective method of removing the fixed and finite state amount of memory that restricts finite state machines from carrying out compilation jobs that require larger amount of memory. The study is ... The conclusion reviewed the various steps followed and made projections for further reading. Keyword: ...

Digital power and performance analysis of inkjet printed ring oscillators based on electrolyte-gated oxide electronics

Science.gov (United States)

Cadilha Marques, Gabriel; Garlapati, Suresh Kumar; Dehm, Simone; Dasgupta, Subho; Hahn, Horst; Tahoori, Mehdi; Aghassi-Hagmann, Jasmin

2017-09-01

Printed electronic components offer certain technological advantages over their silicon based counterparts, like mechanical flexibility, low process temperatures, maskless and additive manufacturing possibilities. However, to be compatible to the fields of smart sensors, Internet of Things, and wearables, it is essential that devices operate at small supply voltages. In printed electronics, mostly silicon dioxide or organic dielectrics with low dielectric constants have been used as gate isolators, which in turn have resulted in high power transistors operable only at tens of volts. Here, we present inkjet printed circuits which are able to operate at supply voltages as low as ≤2 V. Our transistor technology is based on lithographically patterned drive electrodes, the dimensions of which are carefully kept well within the printing resolutions; the oxide semiconductor, the electrolytic insulator and the top-gate electrodes have been inkjet printed. Our inverters show a gain of ˜4 and 2.3 ms propagation delay time at 1 V supply voltage. Subsequently built 3-stage ring oscillators start to oscillate at a supply voltage of only 0.6 V with a frequency of ˜255 Hz and can reach frequencies up to ˜350 Hz at 2 V supply voltage. Furthermore, we have introduced a systematic methodology for characterizing ring oscillators in the printed electronics domain, which has been largely missing. Benefiting from this procedure, we are now able to predict the switching capacitance and driver capability at each stage, as well as the power consumption of our inkjet printed ring oscillators. These achievements will be essential for analyzing the performance and power characteristics of future inkjet printed digital circuits.

Motion and gravity effects in the precision of quantum clocks.

Science.gov (United States)

Lindkvist, Joel; Sabín, Carlos; Johansson, Göran; Fuentes, Ivette

2015-05-19

We show that motion and gravity affect the precision of quantum clocks. We consider a localised quantum field as a fundamental model of a quantum clock moving in spacetime and show that its state is modified due to changes in acceleration. By computing the quantum Fisher information we determine how relativistic motion modifies the ultimate bound in the precision of the measurement of time. While in the absence of motion the squeezed vacuum is the ideal state for time estimation, we find that it is highly sensitive to the motion-induced degradation of the quantum Fisher information. We show that coherent states are generally more resilient to this degradation and that in the case of very low initial number of photons, the optimal precision can be even increased by motion. These results can be tested with current technology by using superconducting resonators with tunable boundary conditions.

Golden Gate Bridge response: a study with low-amplitude data from three earthquakes

Science.gov (United States)

Çelebi, Mehmet

2012-01-01

The dynamic response of the Golden Gate Bridge, located north of San Francisco, CA, has been studied previously using ambient vibration data and finite element models. Since permanent seismic instrumentation was installed in 1993, only small earthquakes that originated at distances varying between ~11 to 122 km have been recorded. Nonetheless, these records prompted this study of the response of the bridge to low amplitude shaking caused by three earthquakes. Compared to previous ambient vibration studies, the earthquake response data reveal a slightly higher fundamental frequency (shorter-period) for vertical vibration of the bridge deck center span (~7.7–8.3 s versus 8.2–10.6 s), and a much higher fundamental frequency (shorter period) for the transverse direction of the deck (~11.24–16.3 s versus ~18.2 s). In this study, it is also shown that these two periods are dominant apparent periods representing interaction between tower, cable, and deck.

Design of a passive UHF RFID tag for the ISO18000-6C protocol

Energy Technology Data Exchange (ETDEWEB)

Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong, E-mail: wangyao220597@yahoo.com.cn [RFIC Laboratory CICS, School of Communication and Information Engineering, University of Electronic Science and Technology of China, Chengdu 611731 (China)

2011-05-15

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under {+-}4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 {mu}W with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 {mu}m CMOS technology and the chip size is 880 x 880 {mu}m{sup 2}. (semiconductor integrated circuits)

Design of a passive UHF RFID tag for the ISO18000-6C protocol

International Nuclear Information System (INIS)

Wang Yao; Wen Guangjun; Mao Wei; He Yanli; Zhu Xueyong

2011-01-01

This paper presents a new fully integrated wide-range UHF passive RFID tag chip design that is compatible with the ISO18000-6C protocol. In order to reduce the die area, an ultra-low power CMOS voltage regulator without resistors and an area-efficient amplitude shift keying demodulator with a novel adaptive average generator are both adopted. A low power clock generator is designed to guarantee the accuracy of the clock under ±4%. As the clock gating technology is employed to reduce the power consumption of the baseband processor, the total power consumption of the tag is about 14 μW with a sensitivity of -9.5 dBm. The detection distance can reach about 5 m under 4 W effective isotropic radiated power. The whole tag is fabricated in TSMC 0.18 μm CMOS technology and the chip size is 880 x 880 μm 2 . (semiconductor integrated circuits)

Finite time thermodynamics of power and refrigeration cycles

CERN Document Server

Kaushik, Shubhash C; Kumar, Pramod

2017-01-01

This book addresses the concept and applications of Finite Time Thermodynamics to various thermal energy conversion systems including heat engines, heat pumps, and refrigeration and air-conditioning systems. The book is the first of its kind, presenting detailed analytical formulations for the design and optimisation of various power producing and cooling cycles including but not limited to: • Vapour power cycles • Gas power cycles • Vapour compression cycles • Vapour absorption cycles • Rankine cycle coupled refrigeration systems Further, the book addresses the thermoeconomic analysis for the optimisation of thermal cycles, an important field of study in the present age and which is characterised by multi-objective optimization regarding energy, ecology, the environment and economics. Lastly, the book provides the readers with key techniques associated with Finite Time Thermodynamics, allowing them to understand the relevance of irreversibilitie s associated with real processes and the scientific r...

Byzantine-fault tolerant self-stabilizing protocol for distributed clock synchronization systems

Science.gov (United States)

Malekpour, Mahyar R. (Inventor)

2010-01-01

A rapid Byzantine self-stabilizing clock synchronization protocol that self-stabilizes from any state, tolerates bursts of transient failures, and deterministically converges within a linear convergence time with respect to the self-stabilization period. Upon self-stabilization, all good clocks proceed synchronously. The Byzantine self-stabilizing clock synchronization protocol does not rely on any assumptions about the initial state of the clocks. Furthermore, there is neither a central clock nor an externally generated pulse system. The protocol converges deterministically, is scalable, and self-stabilizes in a short amount of time. The convergence time is linear with respect to the self-stabilization period.

Input Stage for Low-Voltage, Low-Noise Preamplifiers Based on a Floating-Gate MOS Transistor

DEFF Research Database (Denmark)

Igor, Mucha

1997-01-01

A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe degradat......A novel input stage for low-voltage, low-noise preamplifiers for integrated capacitive sensors is presented. The input stage of the preamplifier employs floating-gate MOS transistors which are capable of storing the operation point of the input stage over several years without any severe...... degradation of the performance of the circuit and without the need for a repeating programming. In this way the noise originating from any resistance previously used for the definition of the operating point is avoided completely and, moreover, by avoiding the input high-pass filter both the saturation...

Modal Analysis of a Steel Radial Gate Exposed to Different Water Levels

Science.gov (United States)

Brusewicz, Krzysztof; Sterpejkowicz-Wersocki, Witold; Jankowski, Robert

2017-06-01

With the increase in water retention needs and planned river regulation, it might be important to investigate the dynamic resistance of vulnerable elements of hydroelectric power plants, including steelwater locks. The most frequent dynamic loads affecting hydroengineering structures in Poland include vibrations caused by heavy road and railway traffic, piling works and mining tremors. More destructive dynamic loads, including earthquakes, may also occur in our country, although their incidence is relatively low. However, given the unpredictable nature of such events, as well as serious consequences they might cause, the study of the seismic resistance of the steel water gate, as one of the most vulnerable elements of a hydroelectric power plant, seems to be important. In this study, a steel radial gate has been analyzed. As far as water gates are concerned, it is among the most popular solutions because of its relatively small weight, compared to plain gates. A modal analysis of the steel radial gate was conducted with the use of the FEM in the ABAQUS software. All structural members were modelled using shell elements with detailed geometry representing a real structure.Water was modelled as an added mass affecting the structure. Different water levels were used to determine the most vulnerable state of the working steel water gate. The results of the modal analysis allowed us to compare the frequencies and their eigenmodes in response to different loads, which is one of the first steps in researching the dynamic properties of steel water gates and their behaviour during extreme dynamic loads, including earthquakes.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

Science.gov (United States)

Szplet, R.; Kalisz, J.; Jachna, Z.

2009-02-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second.

A 45 ps time digitizer with a two-phase clock and dual-edge two-stage interpolation in a field programmable gate array device

International Nuclear Information System (INIS)

Szplet, R; Kalisz, J; Jachna, Z

2009-01-01

We present a time digitizer having 45 ps resolution, integrated in a field programmable gate array (FPGA) device. The time interval measurement is based on the two-stage interpolation method. A dual-edge two-phase interpolator is driven by the on-chip synthesized 250 MHz clock with precise phase adjustment. An improved dual-edge double synchronizer was developed to control the main counter. The nonlinearity of the digitizer's transfer characteristic is identified and utilized by the dedicated hardware code processor for the on-the-fly correction of the output data. Application of presented ideas has resulted in the measurement uncertainty of the digitizer below 70 ps RMS over the time interval ranging from 0 to 1 s. The use of the two-stage interpolation and a fast FIFO memory has allowed us to obtain the maximum measurement rate of five million measurements per second

A quantum analogy to the classical gravitomagnetic clock effect

Science.gov (United States)

Faruque, S. B.

2018-06-01

We present an approximation to the solution of Dirac equation in Schwarzschild field found through the use of Foldy-Wouthuysen Hamiltonian. We solve the equation for the positive energy states and found the frequencies by which the states oscillate. Difference of the periods of oscillation of the two states with two different total angular momentum quantum number j has an analogical form of the classical clock effect found in general relativity. But unlike the term that appears as clock effect in classical physics, here the term is quantized. Thus, we find a quantum analogue of the classical gravitomagnetic clock effect.

r-Universal reversible logic gates

International Nuclear Information System (INIS)

Vos, A de; Storme, L

2004-01-01

Reversible logic plays a fundamental role both in ultra-low power electronics and in quantum computing. It is therefore important to know which reversible logic gates can be used as building block for the reversible implementation of an arbitrary boolean function and which cannot

Experimental state control by fast non-Abelian holonomic gates with a superconducting qutrit

Science.gov (United States)

Danilin, S.; Vepsäläinen, A.; Paraoanu, G. S.

2018-05-01

Quantum state manipulation with gates based on geometric phases acquired during cyclic operations promises inherent fault-tolerance and resilience to local fluctuations in the control parameters. Here we create a general non-Abelian and non-adiabatic holonomic gate acting in the (| 0> ,| 2> ) subspace of a three-level (qutrit) transmon device fabricated in a fully coplanar design. Experimentally, this is realized by simultaneously coupling the first two transitions by microwave pulses with amplitudes and phases defined such that the condition of parallel transport is fulfilled. We demonstrate the creation of arbitrary superpositions in this subspace by changing the amplitudes of the pulses and the relative phase between them. We use two-photon pulses acting in the holonomic subspace to reveal the coherence of the state created by the geometric gate pulses and to prepare different superposition states. We also test the action of holonomic NOT and Hadamard gates on superpositions in the (| 0> ,| 2> ) subspace.

QCD bound states at finite temperature and baryon number

International Nuclear Information System (INIS)

Kalinovsky, Yu.L.; Muenchow, L.

1991-04-01

Quark-antiquark bound states are described within the Bethe-Salpeter equation for a class of quark models with instantaneous 4-quark interaction at finite temperature. Thereby decompositions of the Bethe-Salpeter vertex and wave functions according to their Lorentz structures and the particles content are used. As an application of general scheme, we determine the mass spectrum of low-lying mesons for a special Nambu-Jona-Lasinio model inspired by QCD for hadrons. (orig.)

Non-circadian expression masking clock-driven weak transcription rhythms in U2OS cells.

Directory of Open Access Journals (Sweden)

Julia Hoffmann

Full Text Available U2OS cells harbor a circadian clock but express only a few rhythmic genes in constant conditions. We identified 3040 binding sites of the circadian regulators BMAL1, CLOCK and CRY1 in the U2OS genome. Most binding sites even in promoters do not correlate with detectable rhythmic transcript levels. Luciferase fusions reveal that the circadian clock supports robust but low amplitude transcription rhythms of representative promoters. However, rhythmic transcription of these potentially clock-controlled genes is masked by non-circadian transcription that overwrites the weaker contribution of the clock in constant conditions. Our data suggest that U2OS cells harbor an intrinsically rather weak circadian oscillator. The oscillator has the potential to regulate a large number of genes. The contribution of circadian versus non-circadian transcription is dependent on the metabolic state of the cell and may determine the apparent complexity of the circadian transcriptome.

Ambipolar gate effect and low temperature magnetoresistance of ultrathin La0.8Ca0.2MnO3 films.

Science.gov (United States)

Eblen-Zayas, M; Bhattacharya, A; Staley, N E; Kobrinskii, A L; Goldman, A M

2005-01-28

Ultrathin La(0.8)Ca(0.2)MnO(3) films have been measured in a field-effect geometry. The gate electric field produces a significant ambipolar decrease in resistance at low temperatures. This is attributed to the development of a pseudogap in the density of states and the coupling of localized charge to strain. Within a mixed phase scenario, the gate effect and magnetoresistance are interpreted in the framework of a "general susceptibility," which describes how phase boundaries move through a hierarchical pinning landscape.

A low-power wide range transimpedance amplifier for biochemical sensing.

Science.gov (United States)

Rodriguez-Villegas, Esther

2007-01-01

This paper presents a novel low voltage and low power transimpedance amplifier for amperometric potentiostats. The power is optimized by having three different gain settings for different current ranges, which can be programmed with a biasing current. The voltage ranges have been optimized by using FGMOS transistors in a second voltage amplification stage that simultaneously allow for offset calibration as well as independent biasing of the gates. The circuit operates with input currents from 1 pA to 1 microA, with a maximum power supply voltage of 1.5 V and consumes 82.5 nW, 9.825 microW, 47.325 microW for currents varying from (1 pA, 0.25 nA), (0.25 nA, 62.5 nA) and (62.5 nA, 1 microA) respectively.

New designs of a complete set of Photonic Crystals logic gates

Science.gov (United States)

Hussein, Hussein M. E.; Ali, Tamer A.; Rafat, Nadia H.

2018-03-01

In this paper, we introduce new designs of all-optical OR, AND, XOR, NOT, NOR, NAND and XNOR logic gates based on the interference effect. The designs are built using 2D square lattice Photonic Crystal (PhC) structure of dielectric rods embedded in air background. The lattice constant, a, and the rod radius, r, are designed to achieve maximum operating range of frequencies using the gap map. We use the Plane Wave Expansion (PWE) method to obtain the band structure and the gap map of the proposed designs. The operating wavelengths achieve a wide band range that varies between 1266.9 nm and 1996 nm with center wavelength at 1550 nm. The Finite-Difference Time-Domain (FDTD) method is used to study the field behavior inside the PhC gates. The gates satisfy their truth tables with reasonable power contrast ratio between logic '1' and logic '0'.

Field Programmable Gate Array Control of Power Systems in Graduate Student Laboratories

National Research Council Canada - National Science Library

O'Connor, Joseph E

2008-01-01

...) continuously develops new design and education resources for students. One area of focus for students in the Power Electronics curriculum track is the development of a design center that explores Field Programmable Gate Array (FPGA...

Novel low-power ultrasound digital preprocessing architecture for wireless display.

Science.gov (United States)

Levesque, Philippe; Sawan, Mohamad

2010-03-01

A complete hardware-based ultrasound preprocessing unit (PPU) is presented as an alternative to available power-hungry devices. Intended to expand the ultrasonic applications, the proposed unit allows replacement of the cable of the ultrasonic probe by a wireless link to transfer data from the probe to a remote monitor. The digital back-end architecture of this PPU is fully pipelined, which permits sampling of ultrasonic signals at a frequency equal to the field-programmable gate array-based system clock, up to 100 MHz. Experimental results show that the proposed processing unit has an excellent performance, an equivalent 53.15 Dhrystone 2.1 MIPS/ MHz (DMIPS/MHz), compared with other software-based architectures that allow a maximum of 1.6 DMIPS/MHz. In addition, an adaptive subsampling method is proposed to operate the pixel compressor, which allows real-time image zooming and, by removing high-frequency noise, the lateral and axial resolutions are enhanced by 25% and 33%, respectively. Realtime images, acquired from a reference phantom, validated the feasibility of the proposed architecture. For a display rate of 15 frames per second, and a 5-MHz single-element piezoelectric transducer, the proposed digital PPU requires a dynamic power of only 242 mW, which represents around 20% of the best-available software-based system. Furthermore, composed by the ultrasound processor and the image interpolation unit, the digital processing core of the PPU presents good power-performance ratios of 26 DMIPS/mW and 43.9 DMIPS/mW at a 20-MHz and 100-MHz sample frequency, respectively.

Algorithmic-Reducibility = Renormalization-Group Fixed-Points; ``Noise''-Induced Phase-Transitions (NITs) to Accelerate Algorithmics (``NIT-Picking'') Replacing CRUTCHES!!!: Gauss Modular/Clock-Arithmetic Congruences = Signal X Noise PRODUCTS..

Science.gov (United States)

Siegel, J.; Siegel, Edward Carl-Ludwig

2011-03-01

Cook-Levin computational-"complexity"(C-C) algorithmic-equivalence reduction-theorem reducibility equivalence to renormalization-(semi)-group phase-transitions critical-phenomena statistical-physics universality-classes fixed-points, is exploited with Gauss modular/clock-arithmetic/model congruences = signal X noise PRODUCT reinterpretation. Siegel-Baez FUZZYICS=CATEGORYICS(SON of ``TRIZ''): Category-Semantics(C-S) tabular list-format truth-table matrix analytics predicts and implements "noise"-induced phase-transitions (NITs) to accelerate versus to decelerate Harel [Algorithmics(1987)]-Sipser[Intro. Theory Computation(1997) algorithmic C-C: "NIT-picking" to optimize optimization-problems optimally(OOPO). Versus iso-"noise" power-spectrum quantitative-only amplitude/magnitude-only variation stochastic-resonance, this "NIT-picking" is "noise" power-spectrum QUALitative-type variation via quantitative critical-exponents variation. Computer-"science" algorithmic C-C models: Turing-machine, finite-state-models/automata, are identified as early-days once-workable but NOW ONLY LIMITING CRUTCHES IMPEDING latter-days new-insights!!!

Sexual Differentiation of Circadian Clock Function in the Adrenal Gland.

Science.gov (United States)

Kloehn, Ian; Pillai, Savin B; Officer, Laurel; Klement, Claire; Gasser, Paul J; Evans, Jennifer A

2016-05-01

Sex differences in glucocorticoid production are associated with increased responsiveness of the adrenal gland in females. However, the adrenal-intrinsic mechanisms that establish sexual dimorphic function remain ill defined. Glucocorticoid production is gated at the molecular level by the circadian clock, which may contribute to sexual dimorphic adrenal function. Here we examine sex differences in the adrenal gland using an optical reporter of circadian clock function. Adrenal glands were cultured from male and female Period2::Luciferase (PER2::LUC) mice to assess clock function in vitro in real time. We confirm that there is a pronounced sex difference in the intrinsic capacity to sustain PER2::LUC rhythms in vitro, with higher amplitude rhythms in adrenal glands collected from males than from females. Changes in adrenal PER2::LUC rhythms over the reproductive life span implicate T as an important factor in driving sex differences in adrenal clock function. By directly manipulating hormone levels in adult mice in vivo, we demonstrate that T increases the amplitude of PER2::LUC rhythms in adrenal glands of both male and female mice. In contrast, we find little evidence that ovarian hormones modify adrenal clock function. Lastly, we find that T in vitro can increase the amplitude of PER2::LUC rhythms in male adrenals but not female adrenals, which suggests the existence of sex differences in the mechanisms of T action in vivo. Collectively these results reveal that activational effects of T alter circadian timekeeping in the adrenal gland, which may have implications for sex differences in stress reactivity and stress-related disorders.

Effective capacity of Nakagami-m fading channels with full channel state information in the low power regime

KAUST Repository

Benkhelifa, Fatma

2013-09-01

The effective capacity have been introduced by Wu and Neji as a link-layer model supporting statistical delay QoS requirements. In this paper, we propose to study the effective capacity of a Nakagami-m fading channel with full channel state information (CSI) at both the transmitter and at the receiver. We focus on the low Signal-to-Noise Ratio (SNR) regime. We show that the effective capacity for any arbitrary but finite statistically delay Quality of Service (QoS) exponent θ, scales essentially as S NRlog(1/SNR) exactly as the ergodic capacity, independently of any QoS constraint. We also characterize the minimum energy required for reliable communication, and the wideband slope to show that our results are in agreement with results established recently by Gursoy et al. We also propose an on-off power control scheme that achieves the capacity asymptotically using only one bit CSI feedback at the transmitter. Finally, some numerical results are presented to show the accuracy of our asymptotic results. © 2013 IEEE.

Experimental realization of universal geometric quantum gates with solid-state spins.

Science.gov (United States)

Zu, C; Wang, W-B; He, L; Zhang, W-G; Dai, C-Y; Wang, F; Duan, L-M

2014-10-02

Experimental realization of a universal set of quantum logic gates is the central requirement for the implementation of a quantum computer. In an 'all-geometric' approach to quantum computation, the quantum gates are implemented using Berry phases and their non-Abelian extensions, holonomies, from geometric transformation of quantum states in the Hilbert space. Apart from its fundamental interest and rich mathematical structure, the geometric approach has some built-in noise-resilience features. On the experimental side, geometric phases and holonomies have been observed in thermal ensembles of liquid molecules using nuclear magnetic resonance; however, such systems are known to be non-scalable for the purposes of quantum computing. There are proposals to implement geometric quantum computation in scalable experimental platforms such as trapped ions, superconducting quantum bits and quantum dots, and a recent experiment has realized geometric single-bit gates in a superconducting system. Here we report the experimental realization of a universal set of geometric quantum gates using the solid-state spins of diamond nitrogen-vacancy centres. These diamond defects provide a scalable experimental platform with the potential for room-temperature quantum computing, which has attracted strong interest in recent years. Our experiment shows that all-geometric and potentially robust quantum computation can be realized with solid-state spin quantum bits, making use of recent advances in the coherent control of this system.

Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

Science.gov (United States)

Choi, Woo Young; Lee, Hyun Kook

2016-01-01

The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

Low-energy. beta. -function in a finite super-Yang-Mills model with multiple mass scales

Energy Technology Data Exchange (ETDEWEB)

Foda, O.; Helayel-Neto, J.A. (International Centre for Theoretical Physics, Trieste (Italy))

1985-02-14

We compute the one-loop contribution to the low-energy light-fermion gauge coupling in a finite supersymmetric gauge theory with two mass scales: a heavy mass that breaks an initial N=4 supersymmetry down to N=2, but respects the finiteness, and a light mass that, for simplicity, is set to zero. We find that coupling grows with the mass of the heavy intermediate states. Hence the latter do not decouple at low energies, leading to large logarithms that invalidate low-energy perturbation theory. Consequently, further manipulations are required to obtain a meaningful perturbative expansion. Enforcing decoupling through finite renormalizations, that absorb the heavy mass effects into a redefinition of the parameters of the lagrangian, introduces an arbitrary subtraction mass ..mu... The requirement that the S-matrix elements be independent of ..mu.. leads to a non-trivial renormalization-group equation for the low-energy theory, with a non-vanishing ..beta..-function.

State-dependent changes in auditory sensory gating in different cortical areas in rats.

Directory of Open Access Journals (Sweden)

Renli Qi

Full Text Available Sensory gating is a process in which the brain's response to a repetitive stimulus is attenuated; it is thought to contribute to information processing by enabling organisms to filter extraneous sensory inputs from the environment. To date, sensory gating has typically been used to determine whether brain function is impaired, such as in individuals with schizophrenia or addiction. In healthy subjects, sensory gating is sensitive to a subject's behavioral state, such as acute stress and attention. The cortical response to sensory stimulation significantly decreases during sleep; however, information processing continues throughout sleep, and an auditory evoked potential (AEP can be elicited by sound. It is not known whether sensory gating changes during sleep. Sleep is a non-uniform process in the whole brain with regional differences in neural activities. Thus, another question arises concerning whether sensory gating changes are uniform in different brain areas from waking to sleep. To address these questions, we used the sound stimuli of a Conditioning-testing paradigm to examine sensory gating during waking, rapid eye movement (REM sleep and Non-REM (NREM sleep in different cortical areas in rats. We demonstrated the following: 1. Auditory sensory gating was affected by vigilant states in the frontal and parietal areas but not in the occipital areas. 2. Auditory sensory gating decreased in NREM sleep but not REM sleep from waking in the frontal and parietal areas. 3. The decreased sensory gating in the frontal and parietal areas during NREM sleep was the result of a significant increase in the test sound amplitude.

Lego clocks: building a clock from parts.

Science.gov (United States)

Brunner, Michael; Simons, Mirre J P; Merrow, Martha

2008-06-01

A new finding opens up speculation that the molecular mechanism of circadian clocks in Synechococcus elongatus is composed of multiple oscillator systems (Kitayama and colleagues, this issue, pp. 1513-1521), as has been described in many eukaryotic clock model systems. However, an alternative intepretation is that the pacemaker mechanism-as previously suggested-lies primarily in the rate of ATP hydrolysis by the clock protein KaiC.

Low-Power Built-In Self-Test Techniques for Embedded SRAMs

Directory of Open Access Journals (Sweden)

Shyue-Kung Lu

2007-01-01

Full Text Available The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

Regulation of circadian clock transcriptional output by CLOCK:BMAL1

Science.gov (United States)

Trott, Alexandra J.

2018-01-01

The mammalian circadian clock relies on the transcription factor CLOCK:BMAL1 to coordinate the rhythmic expression of 15% of the transcriptome and control the daily regulation of biological functions. The recent characterization of CLOCK:BMAL1 cistrome revealed that although CLOCK:BMAL1 binds synchronously to all of its target genes, its transcriptional output is highly heterogeneous. By performing a meta-analysis of several independent genome-wide datasets, we found that the binding of other transcription factors at CLOCK:BMAL1 enhancers likely contribute to the heterogeneity of CLOCK:BMAL1 transcriptional output. While CLOCK:BMAL1 rhythmic DNA binding promotes rhythmic nucleosome removal, it is not sufficient to generate transcriptionally active enhancers as assessed by H3K27ac signal, RNA Polymerase II recruitment, and eRNA expression. Instead, the transcriptional activity of CLOCK:BMAL1 enhancers appears to rely on the activity of ubiquitously expressed transcription factors, and not tissue-specific transcription factors, recruited at nearby binding sites. The contribution of other transcription factors is exemplified by how fasting, which effects several transcription factors but not CLOCK:BMAL1, either decreases or increases the amplitude of many rhythmically expressed CLOCK:BMAL1 target genes. Together, our analysis suggests that CLOCK:BMAL1 promotes a transcriptionally permissive chromatin landscape that primes its target genes for transcription activation rather than directly activating transcription, and provides a new framework to explain how environmental or pathological conditions can reprogram the rhythmic expression of clock-controlled genes. PMID:29300726

Implementation of quantum logic gates using polar molecules in pendular states.

Science.gov (United States)

Zhu, Jing; Kais, Sabre; Wei, Qi; Herschbach, Dudley; Friedrich, Bretislav

2013-01-14

We present a systematic approach to implementation of basic quantum logic gates operating on polar molecules in pendular states as qubits for a quantum computer. A static electric field prevents quenching of the dipole moments by rotation, thereby creating the pendular states; also, the field gradient enables distinguishing among qubit sites. Multi-target optimal control theory is used as a means of optimizing the initial-to-target transition probability via a laser field. We give detailed calculations for the SrO molecule, a favorite candidate for proposed quantum computers. Our simulation results indicate that NOT, Hadamard and CNOT gates can be realized with high fidelity, as high as 0.985, for such pendular qubit states.

Universal holonomic single quantum gates over a geometric spin with phase-modulated polarized light.

Science.gov (United States)

Ishida, Naoki; Nakamura, Takaaki; Tanaka, Touta; Mishima, Shota; Kano, Hiroki; Kuroiwa, Ryota; Sekiguchi, Yuhei; Kosaka, Hideo

2018-05-15

We demonstrate universal non-adiabatic non-abelian holonomic single quantum gates over a geometric electron spin with phase-modulated polarized light and 93% average fidelity. This allows purely geometric rotation around an arbitrary axis by any angle defined by light polarization and phase using a degenerate three-level Λ-type system in a negatively charged nitrogen-vacancy center in diamond. Since the control light is completely resonant to the ancillary excited state, the demonstrated holonomic gate not only is fast with low power, but also is precise without the dynamical phase being subject to control error and environmental noise. It thus allows pulse shaping for further fidelity.

Interface passivation and trap reduction via hydrogen fluoride for molybdenum disulfide on silicon oxide back-gate transistors

Science.gov (United States)

Hu, Yaoqiao; San Yip, Pak; Tang, Chak Wah; Lau, Kei May; Li, Qiang

2018-04-01

Layered semiconductor molybdenum disulfide (MoS2) has recently emerged as a promising material for flexible electronic and optoelectronic devices because of its finite bandgap and high degree of gate control. Here, we report a hydrogen fluoride (HF) passivation technique for improving the carrier mobility and interface quality of chemical vapor deposited monolayer MoS2 on a SiO2/Si substrate. After passivation, the fabricated MoS2 back-gate transistors demonstrate a more than double improvement in average electron mobility, a reduced gate hysteresis gap of 3 V, and a low interface trapped charge density of ˜5.8 × 1011 cm-2. The improvements are attributed to the satisfied interface dangling bonds, thus a reduction of interface trap states and trapped charges. Surface x-ray photoelectron spectroscopy analysis and first-principles simulation were performed to verify the HF passivation effect. The results here highlight the necessity of a MoS2/dielectric passivation strategy and provides a viable route for enhancing the performance of MoS2 nano-electronic devices.

Clock-Frequency Switching Technique for Energy Saving of Microcontroller Unit (MCU-Based Sensor Node

Directory of Open Access Journals (Sweden)

Pumin Duangmanee

2018-05-01

Full Text Available In this paper; a technique is proposed for reducing the energy consumption of microcontroller-based sensor nodes by switching the operating clock between low and high frequencies. The proposed concept is motivated by the fact that if the application codes of the microcontroller unit (MCU consist of no-wait state instruction sets, it consumes less energy when it operates with a higher frequency. When the application code of the MCU consists of wait instruction sets; e.g., a wait acknowledge signal, it switches to low clock frequency. The experimental results confirm that the proposed technique can reduce the MCU energy consumption up to 66.9%.

A high-precision synchronization circuit for clock distribution

International Nuclear Information System (INIS)

Lu Chong; Tan Hongzhou; Duan Zhikui; Ding Yi

2015-01-01

In this paper, a novel structure of a high-precision synchronization circuit, HPSC, using interleaved delay units and a dynamic compensation circuit is proposed. HPSCs are designed for synchronization of clock distribution networks in large-scale integrated circuits, where high-quality clocks are required. The application of a hybrid structure of a coarse delay line and dynamic compensation circuit performs roughly the alignment of the clock signal in two clock cycles, and finishes the fine tuning in the next three clock cycles with the phase error suppressed under 3.8 ps. The proposed circuit is implemented and fabricated using a SMIC 0.13 μm 1P6M process with a supply voltage at 1.2 V. The allowed operation frequency ranges from 200 to 800 MHz, and the duty cycle ranges between [20%, 80%]. The active area of the core circuits is 245 × 134 μm 2 , and the power consumption is 1.64 mW at 500 MHz. (paper)

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

KAUST Repository

Hinkle, Christopher L.; Galatage, Rohit V.; Chapman, Richard A.; Vogel, Eric M.; Alshareef, Husam N.; Freeman, Clive M.; Wimmer, Erich; Niimi, Hiroaki; Li-Fatou, Andrei V.; Shaw, Judy B.; Chambers, James J.

2010-01-01

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

KAUST Repository

Hinkle, Christopher L.

2010-06-01

In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

Random Sequence for Optimal Low-Power Laser Generated Ultrasound

Science.gov (United States)

Vangi, D.; Virga, A.; Gulino, M. S.

2017-08-01

Low-power laser generated ultrasounds are lately gaining importance in the research world, thanks to the possibility of investigating a mechanical component structural integrity through a non-contact and Non-Destructive Testing (NDT) procedure. The ultrasounds are, however, very low in amplitude, making it necessary to use pre-processing and post-processing operations on the signals to detect them. The cross-correlation technique is used in this work, meaning that a random signal must be used as laser input. For this purpose, a highly random and simple-to-create code called T sequence, capable of enhancing the ultrasound detectability, is introduced (not previously available at the state of the art). Several important parameters which characterize the T sequence can influence the process: the number of pulses Npulses , the pulse duration δ and the distance between pulses dpulses . A Finite Element FE model of a 3 mm steel disk has been initially developed to analytically study the longitudinal ultrasound generation mechanism and the obtainable outputs. Later, experimental tests have shown that the T sequence is highly flexible for ultrasound detection purposes, making it optimal to use high Npulses and δ but low dpulses . In the end, apart from describing all phenomena that arise in the low-power laser generation process, the results of this study are also important for setting up an effective NDT procedure using this technology.

Internal Clock Drift Estimation in Computer Clusters

Directory of Open Access Journals (Sweden)

Hicham Marouani

2008-01-01

Full Text Available Most computers have several high-resolution timing sources, from the programmable interrupt timer to the cycle counter. Yet, even at a precision of one cycle in ten millions, clocks may drift significantly in a single second at a clock frequency of several GHz. When tracing the low-level system events in computer clusters, such as packet sending or reception, each computer system records its own events using an internal clock. In order to properly understand the global system behavior and performance, as reported by the events recorded on each computer, it is important to estimate precisely the clock differences and drift between the different computers in the system. This article studies the clock precision and stability of several computer systems, with different architectures. It also studies the typical network delay characteristics, since time synchronization algorithms rely on the exchange of network packets and are dependent on the symmetry of the delays. A very precise clock, based on the atomic time provided by the GPS satellite network, was used as a reference to measure clock drifts and network delays. The results obtained are of immediate use to all applications which depend on computer clocks or network time synchronization accuracy.

Clock distribution system for digital computers

International Nuclear Information System (INIS)

Loomis, H.H.; Wyman, R.H.

1981-01-01

An apparatus is disclosed for eliminating, in each clock distribution amplifier of a clock distribution system, sequential pulse catch-up error due to one pulse ''overtaking'' a prior clock pulse. The apparatus includes timing means to produce a periodic electromagnetic signal with a fundamental frequency having a fundamental frequency component v'01(T); an array of N signal characteristic detector means, with detector means no. 1 receiving the timing means signal and producing a change-of-state signal v1(T) in response to receipt of a signal above a predetermined threshold; N substantially identical filter means, one filter means being operatively associated with each detector means, for receiving the change-of-state signal vn(T) and producing a modified change-of-state signal v'n(T) (N 1, . . . , n) having a fundamental frequency component that is substantially proportional to v'01(T- theta n(T) with a cumulative phase shift theta n(T) having a time derivative that may be made uniformly and arbitrarily small; and with the detector means n+1 (1 < or = n< n) receiving a modified change-of-state signal vn(T) from filter means no. N and, in response to receipt of such a signal above a predetermined threshold, producing a change-of-state signal vn+1

Light-effect transistor (LET) with multiple independent gating controls for optical logic gates and optical amplification

Science.gov (United States)

Marmon, Jason; Rai, Satish; Wang, Kai; Zhou, Weilie; Zhang, Yong

The pathway for CMOS technology beyond the 5-nm technology node remains unclear for both physical and technological reasons. A new transistor paradigm is required. A LET (Marmon et. al., Front. Phys. 2016, 4, No. 8) offers electronic-optical hybridization at the component level, and is capable of continuing Moore's law to the quantum scale. A LET overcomes a FET's fabrication complexity, e.g., physical gate and doping, by employing optical gating and photoconductivity, while multiple independent, optical gates readily realize unique functionalities. We report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs, incorporating an M-S-M structure, show output and transfer characteristics resembling advanced FETs, e.g., on/off ratios up to 106 with a source-drain voltage of 1.43V, gate-power of 260nW, and a subthreshold swing of 0.3nW/decade (excluding losses). A LET has potential for high-switching (THz) speeds and extremely low-switching energies (aJ) in the ballistic transport region. Our work offers new electronic-optical integration strategies for high speed and low energy computing approaches, which could potentially be extended to other materials and devices.

Noise in state of the art clocks and their impact for fundamental physics

Science.gov (United States)

Maleki, L.

2001-01-01

In this paper a review of the use of advanced atomic clocks in testing the fundamental physical laws will be presented. Noise sources of clocks will be discussed, together with an outline their characterization based on current models. The paper will conclude with a discussion of recent attempts to reduce the fundamental, as well as technical noise in atomic clocks.

High-power Al-free active region (λ= 852nm) DFB laser diodes for atomic clocks and interferometry applications

Science.gov (United States)

Ligeret, V.; Vermersch, F.-J.; Bansropun, S.; Lecomte, M.; Calligaro, M.; Parillaud, O.; Krakowski, M.

2017-11-01

Atomic clocks will be used in the future European positioning system Galileo. Among them, the optically pumped clocks provide a better alternative with comparable accuracy for a more compact system. For these systems, diode lasers emitting at 852nm are strategic components. The laser in a conventional bench for atomic clocks presents disadvantages for spatial applications. A better approach would be to realise a system based on a distributed-feedback laser (DFB). We have developed the technological foundations of such lasers operating at 852nm. These include an Al free active region, a single spatial mode ridge waveguide and a DFB structure. The device is a separate confinement heterostructure with a GaInP large optical cavity and a single compressive strained GaInAsP quantum well. The broad area laser diodes are characterised by low internal losses (value of less than 2MHz.

System and method for clock synchronization and position determination using entangled photon pairs

Science.gov (United States)

Shih, Yanhua (Inventor)

2010-01-01

A system and method for clock synchronization and position determination using entangled photon pairs is provided. The present invention relies on the measurement of the second order correlation function of entangled states. Photons from an entangled photon source travel one-way to the clocks to be synchronized. By analyzing photon registration time histories generated at each clock location, the entangled states allow for high accuracy clock synchronization as well as high accuracy position determination.

A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

Science.gov (United States)

Ramezani, Zeinab; Orouji, Ali A.

2018-03-01

In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

Low power interface IC's for electrostatic energy harvesting applications

Science.gov (United States)

Kempitiya, Asantha

The application of wireless distributed micro-sensor systems ranges from equipment diagnostic and control to real time structural and biomedical monitoring. A major obstacle in developing autonomous micro-sensor networks is the need for local electric power supply, since using a battery is often not a viable solution. This void has sparked significant interest in micro-scale power generators based on electrostatic, piezoelectric and electromagnetic energy conversion that can scavenge ambient energy from the environment. In comparison to existing energy harvesting techniques, electrostatic-based power generation is attractive as it can be integrated using mainstream silicon technologies while providing higher power densities through miniaturization. However the power output of reported electrostatic micro-generators to date does not meet the communication and computation requirements of wireless sensor nodes. The objective of this thesis is to investigate novel CMOS-based energy harvesting circuit (EHC) architectures to increase the level of harvested mechanical energy in electrostatic converters. The electronic circuits that facilitate mechanical to electrical energy conversion employing variable capacitors can either have synchronous or asynchronous architectures. The later does not require synchronization of electrical events with mechanical motion, which eliminates difficulties in gate clocking and the power consumption associated with complex control circuitry. However, the implementation of the EHC with the converter can be detrimental to system performance when done without concurrent optimization of both elements, an aspect mainly overlooked in the literature. System level analysis is performed to show that there is an optimum value for either the storage capacitor or cycle number for maximum scavenging of ambient energy. The analysis also shows that maximum power is extracted when the system approaches synchronous operation. However, there is a region of

Shutdown and low-power operation at commercial nuclear power plants in the United States

International Nuclear Information System (INIS)

1993-09-01

The report contains the results of the NRC Staff's evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements

Influence of Aripiprazole, Risperidone, and Amisulpride on Sensory and Sensorimotor Gating in Healthy ‘Low and High Gating' Humans and Relation to Psychometry

Science.gov (United States)

Csomor, Philipp A; Preller, Katrin H; Geyer, Mark A; Studerus, Erich; Huber, Theodor; Vollenweider, Franz X

2014-01-01

Despite advances in the treatment of schizophrenia spectrum disorders with atypical antipsychotics (AAPs), there is still need for compounds with improved efficacy/side-effect ratios. Evidence from challenge studies suggests that the assessment of gating functions in humans and rodents with naturally low-gating levels might be a useful model to screen for novel compounds with antipsychotic properties. To further evaluate and extend this translational approach, three AAPs were examined. Compounds without antipsychotic properties served as negative control treatments. In a placebo-controlled, within-subject design, healthy males received either single doses of aripiprazole and risperidone (n=28), amisulpride and lorazepam (n=30), or modafinil and valproate (n=30), and placebo. Prepulse inhibiton (PPI) and P50 suppression were assessed. Clinically associated symptoms were evaluated using the SCL-90-R. Aripiprazole, risperidone, and amisulpride increased P50 suppression in low P50 gaters. Lorazepam, modafinil, and valproate did not influence P50 suppression in low gaters. Furthermore, low P50 gaters scored significantly higher on the SCL-90-R than high P50 gaters. Aripiprazole increased PPI in low PPI gaters, whereas modafinil and lorazepam attenuated PPI in both groups. Risperidone, amisulpride, and valproate did not influence PPI. P50 suppression in low gaters appears to be an antipsychotic-sensitive neurophysiologic marker. This conclusion is supported by the association of low P50 suppression and higher clinically associated scores. Furthermore, PPI might be sensitive for atypical mechanisms of antipsychotic medication. The translational model investigating differential effects of AAPs on gating in healthy subjects with naturally low gating can be beneficial for phase II/III development plans by providing additional information for critical decision making. PMID:24801767

A low-energy β-function in a finite super-Yang-Mills model with multiple mass scales

International Nuclear Information System (INIS)

Foda, O.; Helayel-Neto, J.A.

1985-01-01

We compute the one-loop contribution to the low-energy light-fermion gauge coupling in a finite supersymmetric gauge theory with two mass scales: a heavy mass that breaks an initial N=4 supersymmetry down to N=2, but respects the finiteness, and a light mass that, for simplicity, is set to zero. We find that coupling grows with the mass of the heavy intermediate states. Hence the latter do not decouple at low energies, leading to large logarithms that invalidate low-energy perturbation theory. Consequently, further manipulations are required to obtain a meaningful perturbative expansion. Enforcing decoupling through finite renormalizations, that absorb the heavy mass effects into a redefinition of the parameters of the lagrangian, introduces an arbitrary subtraction mass μ. The requirement that the S-matrix elements be independent of μ leads to a non-trivial renormalization-group equation for the low-energy theory, with a non-vanishing β-function. (orig.)

A low-energy β-function in a finite super-Yang-Mills model with multiple mass scales

International Nuclear Information System (INIS)

Foda, O.; Helayel-Neto, J.A.

1984-08-01

We compute the one-loop contribution to the low-energy light-fermion gauge coupling in a finite supersymmetric gauge theory with two mass scales: a heavy mass that breaks an initial N=4 supersymmetry down to N=2, but respects the finiteness, and a light mass that, for simplicity, is set to zero. We find that the coupling grows with the mass of the heavy intermediate states. Hence the latter do not decouple at low energies, leading to large logarithms that invalidate low-energy perturbation theory. Consequently, further manipulations are required to obtain a meaningful perturbative expansion. Enforcing decoupling through finite renormalizations, that absorb the heavy mass effects into a redefinition of the parameters of the Lagrangian, introduces an arbitrary subtraction mass μ. The requirement that the S-matrix elements be independent of μ leads to a non-trivial renormalization-group equation for the low-energy theory, with a non-vanishing β-function. (author)

Irreversibility and dissipation in finite-state automata

International Nuclear Information System (INIS)

Ganesh, Natesh; Anderson, Neal G.

2013-01-01

Irreversibility and dissipation in finite-state automata (FSA) are considered from a physical-information-theoretic perspective. A quantitative measure for the computational irreversibility of finite automata is introduced, and a fundamental lower bound on the average energy dissipated per state transition is obtained and expressed in terms of FSA irreversibility. The irreversibility measure and energy bound are germane to any realization of a deterministic automaton that faithfully registers abstract FSA states in distinguishable states of a physical system coupled to a thermal environment, and that evolves via a sequence of interactions with an external system holding a physical instantiation of a random input string. The central result, which is shown to follow from quantum dynamics and entropic inequalities alone, can be regarded as a generalization of Landauer's Principle applicable to FSAs and tailorable to specified automata. Application to a simple FSA is illustrated.

III-V Ultra-Thin-Body InGaAs/InAs MOSFETs for Low Standby Power Logic Applications

Science.gov (United States)

Huang, Cheng-Ying

As device scaling continues to sub-10-nm regime, III-V InGaAs/InAs metal- oxide-semiconductor ?eld-e?ect transistors (MOSFETs) are promising candidates for replacing Si-based MOSFETs for future very-large-scale integration (VLSI) logic applications. III-V InGaAs materials have low electron effective mass and high electron velocity, allowing higher on-state current at lower VDD and reducing the switching power consumption. However, III-V InGaAs materials have a narrower band gap and higher permittivity, leading to large band-to-band tunneling (BTBT) leakage or gate-induced drain leakage (GIDL) at the drain end of the channel, and large subthreshold leakage due to worse electrostatic integrity. To utilize III-V MOSFETs in future logic circuits, III-V MOSFETs must have high on-state performance over Si MOSFETs as well as very low leakage current and low standby power consumption. In this dissertation, we will report InGaAs/InAs ultra-thin-body MOSFETs. Three techniques for reducing the leakage currents in InGaAs/InAs MOSFETs are reported as described below. 1) Wide band-gap barriers: We developed AlAs0.44Sb0.56 barriers lattice-match to InP by molecular beam epitaxy (MBE), and studied the electron transport in In0.53Ga0.47As/AlAs 0.44Sb0.56 heterostructures. The InGaAs channel MOSFETs using AlAs0.44Sb0.56 bottom barriers or p-doped In0.52 Al0.48As barriers were demonstrated, showing significant suppression on the back barrier leakage. 2) Ultra-thin channels: We investigated the electron transport in InGaAs and InAs ultra-thin quantum wells and ultra-thin body MOSFETs (t ch ~ 2-4 nm). For high performance logic, InAs channels enable higher on-state current, while for low power logic, InGaAs channels allow lower BTBT leakage current. 3) Source/Drain engineering: We developed raised InGaAs and recessed InP source/drain spacers. The raised InGaAs source/drain spacers improve electrostatics, reducing subthreshold leakage, and smooth the electric field near drain, reducing

Relativistic Ideal Clock

OpenAIRE

Bratek, Łukasz

2015-01-01

Two particularly simple ideal clocks exhibiting intrinsic circular motion with the speed of light and opposite spin alignment are described. The clocks are singled out by singularities of an inverse Legendre transformation for relativistic rotators of which mass and spin are fixed parameters. Such clocks work always the same way, no matter how they move. When subject to high accelerations or falling in strong gravitational fields of black holes, the clocks could be used to test the clock hypo...

Rough Finite State Automata and Rough Languages

Science.gov (United States)

Arulprakasam, R.; Perumal, R.; Radhakrishnan, M.; Dare, V. R.

2018-04-01

Sumita Basu [1, 2] recently introduced the concept of a rough finite state (semi)automaton, rough grammar and rough languages. Motivated by the work of [1, 2], in this paper, we investigate some closure properties of rough regular languages and establish the equivalence between the classes of rough languages generated by rough grammar and the classes of rough regular languages accepted by rough finite automaton.

A Primer for Telemetry Interfacing in Accordance with NASA Standards Using Low Cost FPGAs

Science.gov (United States)

McCoy, Jake; Schultz, Ted; Tutt, James; Rogers, Thomas; Miles, Drew; McEntaffer, Randall

2016-03-01

Photon counting detector systems on sounding rocket payloads often require interfacing asynchronous outputs with a synchronously clocked telemetry (TM) stream. Though this can be handled with an on-board computer, there are several low cost alternatives including custom hardware, microcontrollers and field-programmable gate arrays (FPGAs). This paper outlines how a TM interface (TMIF) for detectors on a sounding rocket with asynchronous parallel digital output can be implemented using low cost FPGAs and minimal custom hardware. Low power consumption and high speed FPGAs are available as commercial off-the-shelf (COTS) products and can be used to develop the main component of the TMIF. Then, only a small amount of additional hardware is required for signal buffering and level translating. This paper also discusses how this system can be tested with a simulated TM chain in the small laboratory setting using FPGAs and COTS specialized data acquisition products.

Toward A Neutral Mercury Optical Lattice Clock: Determination of the Magic Wavelength for the Ultraviolet clock Transition

International Nuclear Information System (INIS)

Mejri, Sinda

2012-01-01

A lattice clock combines the advantages of ion and neutral atom based clocks, namely the recoil and first order Doppler free spectroscopy allowed by the Lamb-Dicke regime. This lattice light field shifts the energy levels of the clock transition. However a wavelength can be found where the light-shift of the clock states cancelled to first order. In this thesis, we present the latest advances in optical lattice clock with mercury atoms developed at LNE-SYRTE. After a review of the current performances of different optical clock are currently under development, we focus on the concept of optical lattice clock and the features of the mercury that make him an excellent candidate for the realization of an optical lattice clock achievement the uncertainty of the level of 10 -17 . The second part is devoted to the characterization of the mercury MOT, using a sensitive detection system, which allowed us to evaluate the temperature of different isotopes present in the MOT and have a good evidence of sub-Doppler cooling for the fermionic isotopes. The third part of this these, present the experimental aspects of the implementation and the development of the laser source required for trapping mercury atoms operating near the predicted magic wavelength. Finally, we report on the Lamb-Dicke spectroscopy of the 1S0 →3 P0 clock transition in the 199 Hg atoms confined in lattice trap. With use of the ultra-stable laser system, linked to LNE-SYRTE primary frequency reference, we have determined the center frequency of the transition for a range of lattice wavelengths and different lattice depths. Analyzing these measurement, we have carried out the first experimental determination of the magic wavelength, which is the crucial step towards achieving a highly accurate frequency standard using mercury. (author)

A bunch clock for the Advanced Photon Source

International Nuclear Information System (INIS)

Lenkszus, F.R.; Laird, R.J.

1997-01-01

A bunch clock timing module has been developed for use by Advanced Photon Source beamlines. The module provides bunch pattern and timing information that can be used to trigger beamline data collection equipment. The module is fully integrated into the control system software (EPICS) which automatically loads it with the storage ring fill pattern at injection time. Fast timing outputs (1 ns FWHM) for each stored bunch are generated using the storage ring low-level rf and revolution clock as input references. Fiber-optic-based transmitters and receivers are used to transmit a 352-MHz low-level rf reference to distributed bunch clock modules. The bunch clock module is a single-width VME module and may be installed in a VME crate located near beamline instrumentation. A prototype has been in use on the SRI CAT beamline for over a year. The design and integration into the control system timing software along with measured performance results are presented

Design and Construction of an Atomic Clock on an Atom Chip

International Nuclear Information System (INIS)

Reinhard, Friedemann

2009-01-01

We describe the design and construction of an atomic clock on an atom chip, intended as a secondary standard, with a stability in the range of few 10 -13 at 1 s. This clock is based on a two-photon transition between the hyperfine states |F = 1; m F = -1> and |2; 1> of the electronic ground state of the 87 Rb atom. This transition is interrogated using a Ramsey scheme, operating on either a cloud of thermal atoms or a Bose-Einstein condensate. In contrast to atomic fountain clocks, this clock is magnetically trapped on an atom chip. We describe a theoretical model of the clock stability and the design and construction of a dedicated apparatus. It is able to control the magnetic field at the relative 10 -5 level and features a hybrid atom chip, containing DC conductors as well as a microwave transmission line for the clock interrogation. (author)

Burnout and gate rupture of power MOS transistors with fission fragments of 252Cf

International Nuclear Information System (INIS)

Tang Benqi; Wang Yanping; Geng Bin; Chen Xiaohua; He Chaohui; Yang Hailiang

2000-01-01

A study to determine the single event burnout (SEB) and single event gate rupture (SEGR) sensitivities of power MOSFET devices is carried out by exposure to fission fragments from 252 Cf source. The test method, test results, a description of observed burnout current waveforms and a discussion of a possible failure mechanism are presented. The test results include the observed dependence upon applied drain or gate to source bias and effect of external capacitors and limited resistors

Factors affecting finite strain estimation in low-grade, low-strain clastic rocks

Science.gov (United States)

Pastor-Galán, Daniel; Gutiérrez-Alonso, Gabriel; Meere, Patrick A.; Mulchrone, Kieran F.

2009-12-01

The computer strain analysis methods SAPE, MRL and DTNNM have permitted the characterization of finite strain in two different regions with contrasting geodynamic scenarios; (1) the Talas Ala Tau (Tien Shan, Kyrgyzs Republic) and (2) the Somiedo Nappe and Narcea Antiform (Cantabrian to West Asturian-Leonese Zone boundary, Variscan Belt, NW of Iberia). The performed analyses have revealed low-strain values and the regional strain trend in both studied areas. This study also investigates the relationship between lithology (grain size and percentage of matrix) and strain estimates the two methodologies used. The results show that these methods are comparable and the absence of significant finite strain lithological control in rocks deformed under low metamorphic and low-strain conditions.

The Circadian Molecular Clock Regulates Adult Hippocampal Neurogenesis by Controlling the Timing of Cell-Cycle Entry and Exit

Directory of Open Access Journals (Sweden)

Pascale Bouchard-Cannon

2013-11-01

Full Text Available The subgranular zone (SGZ of the adult hippocampus contains a pool of quiescent neural progenitor cells (QNPs that are capable of entering the cell cycle and producing newborn neurons. The mechanisms that control the timing and extent of adult neurogenesis are not well understood. Here, we show that QNPs of the adult SGZ express molecular-clock components and proliferate in a rhythmic fashion. The clock proteins PERIOD2 and BMAL1 are critical for proper control of neurogenesis. The absence of PERIOD2 abolishes the gating of cell-cycle entrance of QNPs, whereas genetic ablation of bmal1 results in constitutively high levels of proliferation and delayed cell-cycle exit. We use mathematical model simulations to show that these observations may arise from clock-driven expression of a cell-cycle inhibitor that targets the cyclin D/Cdk4-6 complex. Our findings may have broad implications for the circadian clock in timing cell-cycle events of other stem cell populations throughout the body.

Low temperature (100 °C) atomic layer deposited-ZrO2 for recessed gate GaN HEMTs on Si

Science.gov (United States)

Byun, Young-Chul; Lee, Jae-Gil; Meng, Xin; Lee, Joy S.; Lucero, Antonio T.; Kim, Si Joon; Young, Chadwin D.; Kim, Moon J.; Kim, Jiyoung

2017-08-01

In this paper, the effect of atomic layer deposited ZrO2 gate dielectrics, deposited at low temperature (100 °C), on the characteristics of recessed-gate High Electron Mobility Transistors (HEMTs) on Al0.25Ga0.75N/GaN/Si is investigated and compared with the characteristics of those with ZrO2 films deposited at typical atomic layer deposited (ALD) process temperatures (250 °C). Negligible hysteresis (ΔVth 4 V), and low interfacial state density (Dit = 3.69 × 1011 eV-1 cm-2) were observed on recessed gate HEMTs with ˜5 nm ALD-ZrO2 films grown at 100 °C. The excellent properties of recessed gate HEMTs are due to the absence of an interfacial layer and an amorphous phase of the film. An interfacial layer between 250 °C-ZrO2 and GaN is observed via high-resolution transmission electron microscopy and X-ray photoelectron spectroscopy. However, 100 °C-ZrO2 and GaN shows no significant interfacial layer formation. Moreover, while 100 °C-ZrO2 films maintain an amorphous phase on either substrate (GaN and Si), 250 °C-ZrO2 films exhibit a polycrystalline-phase when deposited on GaN and an amorphous phase when deposited on Si. Contrary to popular belief, the low-temperature ALD process for ZrO2 results in excellent HEMT performance.

High Performance Low Cost Digitally Controlled Power Conversion Technology

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes

2008-01-01

in order to reduce the power consumption of servers and datacenters. The work presented in this thesis includes digital control methods for switch-mode converters implemented in microcontrollers, digital signal controllers and field programmable gate arrays. Microcontrollers are cheap devices that can...... be used for real-time control of switch-mode converters. Software design in the assembly language of the microcontroller is important because of the limited resources of the microcontroller. Microcontrollers are best suited for power electronics applications with low bandwidth requirements because...... the execution time of the software algorithm that realises the digital control law will constitute a considerable delay in the control loop. Digital signal controllers are powerful devices capable of performing arithmetic functions much faster than a microcontroller can. Digital signal controllers are well...

Experimental evaluation of IGBT junction temperature measurement via peak gate current

DEFF Research Database (Denmark)

Baker, Nick; Munk-Nielsen, Stig; Iannuzzo, Francesco

2015-01-01

Temperature sensitive electrical parameters allow junction temperature measurements on power semiconductors without modification to module packaging. The peak gate current has recently been proposed for IGBT junction temperature measurement and relies on the temperature dependent resistance...... of the gate pad. Consequently, a consideration of chip geometry and location of the gate pad is required before interpreting temperature data from this method. Results are also compared with a traditional electrical temperature measurement method: the voltage drop under low current....

Sound Clocks and Sonic Relativity

Science.gov (United States)

Todd, Scott L.; Menicucci, Nicolas C.

2017-10-01

Sound propagation within certain non-relativistic condensed matter models obeys a relativistic wave equation despite such systems admitting entirely non-relativistic descriptions. A natural question that arises upon consideration of this is, "do devices exist that will experience the relativity in these systems?" We describe a thought experiment in which `acoustic observers' possess devices called sound clocks that can be connected to form chains. Careful investigation shows that appropriately constructed chains of stationary and moving sound clocks are perceived by observers on the other chain as undergoing the relativistic phenomena of length contraction and time dilation by the Lorentz factor, γ , with c the speed of sound. Sound clocks within moving chains actually tick less frequently than stationary ones and must be separated by a shorter distance than when stationary to satisfy simultaneity conditions. Stationary sound clocks appear to be length contracted and time dilated to moving observers due to their misunderstanding of their own state of motion with respect to the laboratory. Observers restricted to using sound clocks describe a universe kinematically consistent with the theory of special relativity, despite the preferred frame of their universe in the laboratory. Such devices show promise in further probing analogue relativity models, for example in investigating phenomena that require careful consideration of the proper time elapsed for observers.

Using a Voltage Domain Programmable Technique for Low-Power Management Cell-Based Design

Directory of Open Access Journals (Sweden)

Ching-Hwa Cheng

2011-09-01

Full Text Available The Multi-voltage technique is an effective way to reduce power consumption. In the proposed cell-based voltage domain programmable (VDP technique, the high and low voltages applied to logic gates are programmable. The flexible voltage domain reassignment allows the chip performance and power consumption to be dynamically adjusted. In the proposed technique, the power switches possess the feature of flexible programming after chip manufacturing. This VDP method does not use an external voltage regulator to regulate the supply voltage level from outside of the chip but can be easily integrated within the design. This novel technique is proven by use of a video decoder test chip, which shows 55% and 61% power reductions compared to conventional single-Vdd and low-voltage designs, respectively. This power-aware performance adjusting mechanism shows great power reduction with a good power-performance management mechanism.

Development of a Compact Range-gated Vision System to Monitor Structures in Low-visibility Environments

International Nuclear Information System (INIS)

Ahn, Yong-Jin; Park, Seung-Kyu; Baik, Sung-Hoon; Kim, Dong-Lyul; Choi, Young-Soo; Jeong, Kyung-Min

2015-01-01

Image acquisition in disaster area or radiation area of nuclear industry is an important function for safety inspection and preparing appropriate damage control plans. So, automatic vision system to monitor structures and facilities in blurred smoking environments such as the places of a fire and detonation is essential. Vision systems can't acquire an image when the illumination light is blocked by disturbance materials, such as smoke, fog and dust. To overcome the imaging distortion caused by obstacle materials, robust vision systems should have extra-functions, such as active illumination through disturbance materials. One of active vision system is a range-gated imaging system. The vision system based on the range-gated imaging system can acquire image data from the blurred and darken light environments. Range-gated imaging (RGI) is a direct active visualization technique using a highly sensitive image sensor and a high intensity illuminant. Currently, the range-gated imaging technique providing 2D and range image data is one of emerging active vision technologies. The range-gated imaging system gets vision information by summing time sliced vision images. In the RGI system, a high intensity illuminant illuminates for ultra-short time and a highly sensitive image sensor is gated by ultra-short exposure time to only get the illumination light. Here, the illuminant illuminates objects by flashing strong light through disturbance materials, such as smoke particles and dust particles. In contrast to passive conventional vision systems, the RGI active vision technology enables operation even in harsh environments like low-visibility smoky environment. In this paper, a compact range-gated vision system is developed to monitor structures in low-visibility environment. The system consists of illumination light, a range-gating camera and a control computer. Visualization experiments are carried out in low-visibility foggy environment to see imaging capability

Development of a Compact Range-gated Vision System to Monitor Structures in Low-visibility Environments

Energy Technology Data Exchange (ETDEWEB)

Ahn, Yong-Jin; Park, Seung-Kyu; Baik, Sung-Hoon; Kim, Dong-Lyul; Choi, Young-Soo; Jeong, Kyung-Min [KAERI, Daejeon (Korea, Republic of)

2015-05-15

Image acquisition in disaster area or radiation area of nuclear industry is an important function for safety inspection and preparing appropriate damage control plans. So, automatic vision system to monitor structures and facilities in blurred smoking environments such as the places of a fire and detonation is essential. Vision systems can't acquire an image when the illumination light is blocked by disturbance materials, such as smoke, fog and dust. To overcome the imaging distortion caused by obstacle materials, robust vision systems should have extra-functions, such as active illumination through disturbance materials. One of active vision system is a range-gated imaging system. The vision system based on the range-gated imaging system can acquire image data from the blurred and darken light environments. Range-gated imaging (RGI) is a direct active visualization technique using a highly sensitive image sensor and a high intensity illuminant. Currently, the range-gated imaging technique providing 2D and range image data is one of emerging active vision technologies. The range-gated imaging system gets vision information by summing time sliced vision images. In the RGI system, a high intensity illuminant illuminates for ultra-short time and a highly sensitive image sensor is gated by ultra-short exposure time to only get the illumination light. Here, the illuminant illuminates objects by flashing strong light through disturbance materials, such as smoke particles and dust particles. In contrast to passive conventional vision systems, the RGI active vision technology enables operation even in harsh environments like low-visibility smoky environment. In this paper, a compact range-gated vision system is developed to monitor structures in low-visibility environment. The system consists of illumination light, a range-gating camera and a control computer. Visualization experiments are carried out in low-visibility foggy environment to see imaging capability.

Implementation of high-speed–low-power adaptive finite impulse response filter with novel architecture

Directory of Open Access Journals (Sweden)

Manish Jaiswal

2015-03-01

Full Text Available An energy efficient high-speed adaptive finite impulse response filter with novel architecture is developed. Synthesis results along with novel architecture on different complementary metal–oxide semiconductor (CMOS families are presented. Analysis is performed using Artix-7, Spartan-6 and Virtex-4 for most popular adaptive least mean square filter for different orders such as N = 8, 16, 32. The presented work is done using MATLAB (2013b and Xilinx (14.2. From the synthesis results, it can be found that CMOS (28 nm achieves the lowest power and critical path delay compared to others, and thus proves its efficiency in terms of energy. Different parameters are considered such as look up tables and input–output blocks, along with their optimised results.

IMPROVING BANDWIDTH OF FLIPPED VOLTAGE FOLLOWER USING GATE-BODY DRIVEN TECHNIQUE

Directory of Open Access Journals (Sweden)

VANDANA NIRANJAN

2017-01-01

Full Text Available In this paper, a new approach to enhance the bandwidth of flipped voltage follower is explored. The proposed approach is based on gate-body driven technique. This technique boosts the transconductance in a MOS transistor as both gate and body/bulk terminals are tied together and used as signal input. This novel technique appears as a good solution to merge the advantages of gate-driven and bulk-driven techniques and suppress their disadvantages. The gate-body driven technique utilizes body effect to enable low voltage low power operation and improves the overall performance of flipped voltage follower, providing it with low output impedance, high input impedance and bandwidth extension ratio of 2.614. The most attractive feature is that bandwidth enhancement has been achieved without use of any passive component or extra circuitry. Simulations in PSpice environment for 180 nm CMOS technology verified the predicted theoretical results. The improved flipped voltage follower is particularly interesting for high frequency low noise signal processing applications.

High frequency MOSFET gate drivers technologies and applications

CERN Document Server

Zhang, Zhiliang

2017-01-01

This book describes high frequency power MOSFET gate driver technologies, including gate drivers for GaN HEMTs, which have great potential in the next generation of switching power converters. Gate drivers serve as a critical role between control and power devices.

Socio-economic applications of finite state mean field games

KAUST Repository

Gomes, Diogo A.; Machado Velho, Roberto; Wolfram, Marie Therese

2014-01-01

In this paper, we present different applications of finite state mean field games to socio-economic sciences. Examples include paradigm shifts in the scientific community or consumer choice behaviour in the free market. The corresponding finite

High peak power tubes and gate effect Klystrons

International Nuclear Information System (INIS)

Gerbelot, N.; Bres, M.; Faillon, G.; Buzzi, J.M.

1993-01-01

The conventional microwave tubes such as TWTs, Magnetrons, Klystrons... deliver the very high peak powers which are required by radar transmitters but more especially by many particle accelerators. In the range of a few hundred MHz to about 10 GHz, some dozen of MWs per unit are currently obtained and commercially available, according to the frequency and the pulse lengths. But peak power requirements are ever increasing, especially for the expected new linear particle acceleratores, where several hundred MWs per tube would be necessary. Also some special military transmitters begin to request GW pulses, with short pulse lengths - of course - but at nonnegligible repetition rates. Therefore several laboratories and microwave vacuum tube manufacturers have engaged - for several years - studies and development in the field of very high peak microwave power (HPM) toward two main directions: extended operation and extrapolation of the conventional tubes and devices; development of new concepts, among which the most promising are likely the high-current relativistic klystrons - that are also referred to as gate effect klystrons

A finite state model for respiratory motion analysis in image guided radiation therapy

International Nuclear Information System (INIS)

Wu Huanmei; Sharp, Gregory C; Salzberg, Betty; Kaeli, David; Shirato, Hiroki; Jiang, Steve B

2004-01-01

Effective image guided radiation treatment of a moving tumour requires adequate information on respiratory motion characteristics. For margin expansion, beam tracking and respiratory gating, the tumour motion must be quantified for pretreatment planning and monitored on-line. We propose a finite state model for respiratory motion analysis that captures our natural understanding of breathing stages. In this model, a regular breathing cycle is represented by three line segments, exhale, end-of-exhale and inhale, while abnormal breathing is represented by an irregular breathing state. In addition, we describe an on-line implementation of this model in one dimension. We found this model can accurately characterize a wide variety of patient breathing patterns. This model was used to describe the respiratory motion for 23 patients with peak-to-peak motion greater than 7 mm. The average root mean square error over all patients was less than 1 mm and no patient has an error worse than 1.5 mm. Our model provides a convenient tool to quantify respiratory motion characteristics, such as patterns of frequency changes and amplitude changes, and can be applied to internal or external motion, including internal tumour position, abdominal surface, diaphragm, spirometry and other surrogates

A finite state model for respiratory motion analysis in image guided radiation therapy

Energy Technology Data Exchange (ETDEWEB)

Wu Huanmei [College of Computer and Information Science, Northeastern University, Boston, MA 02115 (United States); Sharp, Gregory C [Department of Radiation Oncology, Massachusetts General Hospital and Harvard Medical School, Boston, MA 02114 (United States); Salzberg, Betty [College of Computer and Information Science, Northeastern University, Boston, MA 02115 (United States); Kaeli, David [Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115 (United States); Shirato, Hiroki [Department of Radiation Medicine, Hokkaido University School of Medicine, Sapporo (Japan); Jiang, Steve B [Department of Radiation Oncology, Massachusetts General Hospital and Harvard Medical School, Boston, MA 02114 (United States)

2004-12-07

Effective image guided radiation treatment of a moving tumour requires adequate information on respiratory motion characteristics. For margin expansion, beam tracking and respiratory gating, the tumour motion must be quantified for pretreatment planning and monitored on-line. We propose a finite state model for respiratory motion analysis that captures our natural understanding of breathing stages. In this model, a regular breathing cycle is represented by three line segments, exhale, end-of-exhale and inhale, while abnormal breathing is represented by an irregular breathing state. In addition, we describe an on-line implementation of this model in one dimension. We found this model can accurately characterize a wide variety of patient breathing patterns. This model was used to describe the respiratory motion for 23 patients with peak-to-peak motion greater than 7 mm. The average root mean square error over all patients was less than 1 mm and no patient has an error worse than 1.5 mm. Our model provides a convenient tool to quantify respiratory motion characteristics, such as patterns of frequency changes and amplitude changes, and can be applied to internal or external motion, including internal tumour position, abdominal surface, diaphragm, spirometry and other surrogates.

A low on-resistance SOI LDMOS using a trench gate and a recessed drain

International Nuclear Information System (INIS)

Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

2012-01-01

An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

Multiple Independent Gate FETs: How Many Gates Do We Need?

OpenAIRE

Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

2015-01-01

Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

State-to-State Mode Specificity: Energy Sequestration and Flow Gated by Transition State.

Science.gov (United States)

Zhao, Bin; Sun, Zhigang; Guo, Hua

2015-12-23

Energy flow and sequestration at the state-to-state level are investigated for a prototypical four-atom reaction, H2 + OH → H + H2O, using a transition-state wave packet (TSWP) method. The product state distribution is found to depend strongly on the reactant vibrational excitation, indicating mode specificity at the state-to-state level. From a local-mode perspective, it is shown that the vibrational excitation of the H2O product derives from two different sources, one attributable to the energy flow along the reaction coordinate into the newly formed OH bond and the other due to the sequestration of the vibrational energy in the OH spectator moiety during the reaction. The analysis provided a unified interpretation of some seemingly contradicting experimental observations. It is further shown that the transfer of vibrational energy from the OH reactant to H2O product is gated by the transition state, accomplished coherently by multiple TSWPs with the corresponding OH vibrational excitation.

Research on the Method of Noise Error Estimation of Atomic Clocks

Science.gov (United States)

Song, H. J.; Dong, S. W.; Li, W.; Zhang, J. H.; Jing, Y. J.

2017-05-01

The simulation methods of different noises of atomic clocks are given. The frequency flicker noise of atomic clock is studied by using the Markov process theory. The method for estimating the maximum interval error of the frequency white noise is studied by using the Wiener process theory. Based on the operation of 9 cesium atomic clocks in the time frequency reference laboratory of NTSC (National Time Service Center), the noise coefficients of the power-law spectrum model are estimated, and the simulations are carried out according to the noise models. Finally, the maximum interval error estimates of the frequency white noises generated by the 9 cesium atomic clocks have been acquired.

Non deterministic finite automata for power systems fault diagnostics

Directory of Open Access Journals (Sweden)

LINDEN, R.

2009-06-01

Full Text Available This paper introduces an application based on finite non-deterministic automata for power systems diagnosis. Automata for the simpler faults are presented and the proposed system is compared with an established expert system.

Artificial emotional model based on finite state machine

Institute of Scientific and Technical Information of China (English)

MENG Qing-mei; WU Wei-guo

2008-01-01

According to the basic emotional theory, the artificial emotional model based on the finite state machine(FSM) was presented. In finite state machine model of emotion, the emotional space included the basic emotional space and the multiple emotional spaces. The emotion-switching diagram was defined and transition function was developed using Markov chain and linear interpolation algorithm. The simulation model was built using Stateflow toolbox and Simulink toolbox based on the Matlab platform.And the model included three subsystems: the input one, the emotion one and the behavior one. In the emotional subsystem, the responses of different personalities to the external stimuli were described by defining personal space. This model takes states from an emotional space and updates its state depending on its current state and a state of its input (also a state-emotion). The simulation model realizes the process of switching the emotion from the neutral state to other basic emotions. The simulation result is proved to correspond to emotion-switching law of human beings.

Radiation-induced off-state leakage current in commercial power MOSFETs

International Nuclear Information System (INIS)

Dodd, Paul Emerson; Shaneyfelt, Marty Ray; Draper, Bruce Leroy; Felix, James Andrew; Schwank, James Ralph; Dalton, Scott Matthew

2005-01-01

The total dose hardness of several commercial power MOSFET technologies is examined. After exposure to 20 krad(SiO 2 ) most of the n- and p-channel devices examined in this work show substantial (2 to 6 orders of magnitude) increases in off-state leakage current. For the n-channel devices, the increase in radiation-induced leakage current follows standard behavior for moderately thick gate oxides, i.e., the increase in leakage current is dominated by large negative threshold voltage shifts, which cause the transistor to be partially on even when no bias is applied to the gate electrode. N-channel devices biased during irradiation show a significantly larger leakage current increase than grounded devices. The increase in leakage current for the p-channel devices, however, was unexpected. For the p-channel devices, it is shown using electrical characterization and simulation that the radiation-induced leakage current increase is related to an increase in the reverse bias leakage characteristics of the gated diode which is formed by the drain epitaxial layer and the body. This mechanism does not significantly contribute to radiation-induced leakage current in typical p-channel MOS transistors. The p-channel leakage current increase is nearly identical for both biased and grounded irradiations and therefore has serious implications for long duration missions since even devices which are usually powered off could show significant degradation and potentially fail.

Mixed Finite Element Simulation with Stability Analysis for Gas Transport in Low-Permeability Reservoirs

Directory of Open Access Journals (Sweden)

Mohamed F. El-Amin

2018-01-01

Full Text Available Natural gas exists in considerable quantities in tight reservoirs. Tight formations are rocks with very tiny or poorly connected pors that make flow through them very difficult, i.e., the permeability is very low. The mixed finite element method (MFEM, which is locally conservative, is suitable to simulate the flow in porous media. This paper is devoted to developing a mixed finite element (MFE technique to simulate the gas transport in low permeability reservoirs. The mathematical model, which describes gas transport in low permeability formations, contains slippage effect, as well as adsorption and diffusion mechanisms. The apparent permeability is employed to represent the slippage effect in low-permeability formations. The gas adsorption on the pore surface has been described by Langmuir isotherm model, while the Peng-Robinson equation of state is used in the thermodynamic calculations. Important compatibility conditions must hold to guarantee the stability of the mixed method by adding additional constraints to the numerical discretization. The stability conditions of the MFE scheme has been provided. A theorem and three lemmas on the stability analysis of the mixed finite element method (MFEM have been established and proven. A semi-implicit scheme is developed to solve the governing equations. Numerical experiments are carried out under various values of the physical parameters.

Implementation of a funnel-and-gate remediation system

International Nuclear Information System (INIS)

O'Brien, K.; Keyes, G.; Sherman, N.

1997-01-01

A funnel-and-gate trademark system incorporating activated carbon was deemed the most attractive remediation method for an active lumber mill in the western United States. Petroleum hydrocarbons, chlorinated solvents, pentachlorophenol, and tetrachlorophenol were detected in on-site groundwater samples. The shallow aquifer consists of a heterogeneous mixture of marine deposits and artificial fill, underlain by low-permeability siltstones and mudstone. In the funnel-and-gate trademark system, a low-permeability cutoff wall was installed to funnel groundwater flow to a smaller area (a open-quotes gateclose quotes) where a passive below-grade treatment system treats the plume as it flows through the gate. Groundwater flow modeling focused on the inhomogeneities of the aquifer and the spatial relationship between gate(s) and barrier walls. The gate design incorporates several factors, including contaminant concentration, flow rate, and time between carbon changeouts. To minimize back pressure and maximize residence time, each gate was designed using 1.25-meter (4-foot) diameter corrugated metal pipe filled with a 1.25-meter (4-foot) thick bed of activated carbon. The configuration will allow water to flow through the treatment gates without pumps. The installed system is 190 meters (625 feet) long and treats approximately 76 L/min (20 gpm) during the winter months

Optimization of ultra-low-power CMOS transistors

International Nuclear Information System (INIS)

Stockinger, M.

2000-01-01

Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

Socio-economic applications of finite state mean field games

KAUST Repository

Gomes, Diogo A.

2014-10-06

In this paper, we present different applications of finite state mean field games to socio-economic sciences. Examples include paradigm shifts in the scientific community or consumer choice behaviour in the free market. The corresponding finite state mean field game models are hyperbolic systems of partial differential equations, for which we present and validate different numerical methods. We illustrate the behaviour of solutions with various numerical experiments,which show interesting phenomena such as shock formation. Hence, we conclude with an investigation of the shock structure in the case of two-state problems.

A novel optical gating method for laser gated imaging

Science.gov (United States)

Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

2013-06-01

For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

Quantum entanglement of localized excited states at finite temperature

Energy Technology Data Exchange (ETDEWEB)

Caputa, Paweł [Yukawa Institute for Theoretical Physics (YITP), Kyoto University,Kyoto 606-8502 (Japan); Nordita, KTH Royal Institute of Technology and Stockholm University,Roslagstullsbacken 23, SE-106 91 Stockholm (Sweden); Simón, Joan; Štikonas, Andrius [School of Mathematics and Maxwell Institute for Mathematical Sciences,University of Edinburgh,King’s Buildings, Edinburgh EH9 3FD (United Kingdom); Takayanagi, Tadashi [Yukawa Institute for Theoretical Physics (YITP), Kyoto University,Kyoto 606-8502 (Japan); Kavli Institute for the Physics and Mathematics of the Universe (Kavli IPMU),University of Tokyo,Kashiwa, Chiba 277-8582 (Japan)

2015-01-20

In this work we study the time evolutions of (Renyi) entanglement entropy of locally excited states in two dimensional conformal field theories (CFTs) at finite temperature. We consider excited states created by acting with local operators on thermal states and give both field theoretic and holographic calculations. In free field CFTs, we find that the growth of Renyi entanglement entropy at finite temperature is reduced compared to the zero temperature result by a small quantity proportional to the width of the localized excitations. On the other hand, in finite temperature CFTs with classical gravity duals, we find that the entanglement entropy approaches a characteristic value at late time. This behaviour does not occur at zero temperature. We also study the mutual information between the two CFTs in the thermofield double (TFD) formulation and give physical interpretations of our results.

A low-power CMOS frequency synthesizer for GPS receivers

International Nuclear Information System (INIS)

Yu Yunfeng; Xiao Shimao; Zhuang Haixiao; Ma Chengyan; Ye Tianchun; Yue Jianlian

2010-01-01

A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 . (semiconductor integrated circuits)

Low operating voltage n-channel organic field effect transistors using lithium fluoride/PMMA bilayer gate dielectric

Energy Technology Data Exchange (ETDEWEB)

Kumar, S.; Dhar, A., E-mail: adhar@phy.iitkgp.ernet.in

2015-10-15

Highlights: • Alternative to chemically crosslinking of PMMA to achieve low leakage in provided. • Effect of LiF in reducing gate leakage through the OFET device is studied. • Effect of gate leakage on transistor performance has been investigated. • Low voltage operable and low temperature processed n-channel OFETs were fabricated. - Abstract: We report low temperature processed, low voltage operable n-channel organic field effect transistors (OFETs) using N,N′-Dioctyl-3,4,9,10-perylenedicarboximide (PTCDI-C{sub 8}) organic semiconductor and poly(methylmethacrylate) (PMMA)/lithium fluoride (LiF) bilayer gate dielectric. We have studied the role of LiF buffer dielectric in effectively reducing the gate leakage through the device and thus obtaining superior performance in contrast to the single layer PMMA dielectric devices. The bilayer OFET devices had a low threshold voltage (V{sub t}) of the order of 5.3 V. The typical values of saturation electron mobility (μ{sub s}), on/off ratio and inverse sub-threshold slope (S) for the range of devices made were estimated to be 2.8 × 10{sup −3} cm{sup 2}/V s, 385, and 3.8 V/decade respectively. Our work thus provides a potential substitution for much complicated process of chemically crosslinking PMMA to achieve low leakage, high capacitance, and thus low operating voltage OFETs.

Recurrent Artificial Neural Networks and Finite State Natural Language Processing.

Science.gov (United States)

Moisl, Hermann

It is argued that pessimistic assessments of the adequacy of artificial neural networks (ANNs) for natural language processing (NLP) on the grounds that they have a finite state architecture are unjustified, and that their adequacy in this regard is an empirical issue. First, arguments that counter standard objections to finite state NLP on the…

THE USE OF THE FINITE DIFFERENCE METHOD FOR CALCULATION OF ELECTRONIC STATES IN MIS-STRUCTURE WITH SINGLE DONOR 1

Directory of Open Access Journals (Sweden)

E. A. Levchuk

2018-01-01

Full Text Available Numerical modeling of electronic state evolution due to non-uniform external electric field in the structure metal-insulator-semiconductor with solitary donor center is carried out. Considering a nanometer disc-shaped gate as a source of the electric field, the problem for the Laplace equation in multilayered medium is solved numerically to determine the distribution of the gate potential. The energy spectrum of a bound electron is calculated from the problem for the stationary Schrödinger equation. Finite difference schemes are constructed to solve both the problems. Difference scheme for the Schrödinger equation takes into account cusp condition for the wave function at the donor location. To solve the problem for the Laplace equation, asymptotic boundary conditions for approximating the external field potential at large distances from the gate in different layers are suggested. These conditions allow to reduce the calculation domain for the electrostatic problem essentially. The effect of the boundary conditions on the accuracy of calculating the potential and energies is investigated. Using the developed difference schemes, the dependences of the energy spectrum of the bound electron on the gate potential are calculated, and the values of critical potential at which the wave function of the electron is relocated are determined. It has been found on the basis of calculation results, that governing parameter for the description of electronic behavior is the potential difference between the donor and semiconductor surface. It has been shown that critical potential difference does not depend on dielectric thickness and permittivity.

Comparisons of mental clocks.

Science.gov (United States)

Paivio, A

1978-02-01

Subjects in three experiments were presented with pairs of clock times and were required to choose the one in which the hour and minute hand formed the smaller angle. In Experiments 1 and 2, the times were presented digitally, necessitating a transformation into symbolic representations from which the angular size difference could be inferred. The results revealed orderly symbolic distance effects so that comparison reaction time increased as the angular size difference decreased. Moreover, subjects generally reported using imagery to make the judgment, and subjects scoring high on test of imagery ability were faster than those scoring low on such tests. Experiment 3 added a direct perceptual condition in which subjects compared angles between pairs of hands on two drawn (analog) clocks, as well as a mixed condition involving one digital and one analog clock time. The results showed comparable distance effects for all conditions. In addition, reaction time increased from the perceptual, to the mixed, to the pure-digital condition. These results are consistent with predictions from an image-based dual-coding theory.

Low Power Near Field Communication Methods for RFID Applications of SIM Cards.

Science.gov (United States)

Chen, Yicheng; Zheng, Zhaoxia; Gong, Mingyang; Yu, Fengqi

2017-04-14

Power consumption and communication distance have become crucial challenges for SIM card RFID (radio frequency identification) applications. The combination of long distance 2.45 GHz radio frequency (RF) technology and low power 2 kHz near distance communication is a workable scheme. In this paper, an ultra-low frequency 2 kHz near field communication (NFC) method suitable for SIM cards is proposed and verified in silicon. The low frequency transmission model based on electromagnetic induction is discussed. Different transmission modes are introduced and compared, which show that the baseband transmit mode has a better performance. The low-pass filter circuit and programmable gain amplifiers are applied for noise reduction and signal amplitude amplification. Digital-to-analog converters and comparators are used to judge the card approach and departure. A novel differential Manchester decoder is proposed to deal with the internal clock drift in range-controlled communication applications. The chip has been fully implemented in 0.18 µm complementary metal-oxide-semiconductor (CMOS) technology, with a 330 µA work current and a 45 µA idle current. The low frequency chip can be integrated into a radio frequency SIM card for near field RFID applications.

Optimization of powered Stirling heat engine with finite speed thermodynamics

International Nuclear Information System (INIS)

Ahmadi, Mohammad H.; Ahmadi, Mohammad Ali; Pourfayaz, Fathollah; Bidi, Mokhtar; Hosseinzade, Hadi; Feidt, Michel

2016-01-01

Highlights: • Based on finite speed method and direct method, the optimal performance is investigated. • The effects of major parameters on the optimal performance are investigated. • The accuracy of the results was compared with previous works. - Abstract: Popular thermodynamic analyses including finite time thermodynamic analysis was lately developed based upon external irreversibilities while internal irreversibilities such as friction, pressure drop and entropy generation were not considered. The aforementioned disadvantage reduces the reliability of the finite time thermodynamic analysis in the design of an accurate Stirling engine model. Consequently, the finite time thermodynamic analysis could not sufficiently satisfy researchers for implementing in design and optimization issues. In this study, finite speed thermodynamic analysis was employed instead of finite time thermodynamic analysis for studying Stirling heat engine. The finite speed thermodynamic analysis approach is based on the first law of thermodynamics for a closed system with finite speed and the direct method. The effects of heat source temperature, regenerating effectiveness, volumetric ratio, piston stroke as well as rotational speed are included in the analysis. Moreover, maximum output power in optimal rotational speed was calculated while pressure losses in the Stirling engine were systematically considered. The result reveals the accuracy and the reliability of the finite speed thermodynamic method in thermodynamic analysis of Stirling heat engine. The outcomes can help researchers in the design of an appropriate and efficient Stirling engine.

High mobility and low operating voltage ZnGaO and ZnGaLiO transistors with spin-coated Al2O3 as gate dielectric

International Nuclear Information System (INIS)

Xia, D X; Xu, J B

2010-01-01

Spin-coated alumina serving as a gate dielectric in thin film transistors shows interesting dielectric properties for low-voltage applications, despite a moderate capacitance. With Ga singly doped and Ga, Li co-doped ZnO as the active channel layers, typical mobilities of 4.7 cm 2 V -1 s -1 and 2.1 cm 2 V -1 s -1 are achieved, respectively. At a given gate bias, the operation current is much smaller than the previously reported values in low-voltage thin film transistors, primarily relying on the giant-capacitive dielectric. The reported devices combine advantages of high mobility, low power consumption, low cost and ease of fabrication. In addition to the transparent nature of both the dielectric and semiconducting active channels, the superior electrical properties of the devices may provide a new avenue for future transparent electronics. (fast track communication)

Balancing computation and communication power in power constrained clusters

Science.gov (United States)

Piga, Leonardo; Paul, Indrani; Huang, Wei

2018-05-29

Systems, apparatuses, and methods for balancing computation and communication power in power constrained environments. A data processing cluster with a plurality of compute nodes may perform parallel processing of a workload in a power constrained environment. Nodes that finish tasks early may be power-gated based on one or more conditions. In some scenarios, a node may predict a wait duration and go into a reduced power consumption state if the wait duration is predicted to be greater than a threshold. The power saved by power-gating one or more nodes may be reassigned for use by other nodes. A cluster agent may be configured to reassign the unused power to the active nodes to expedite workload processing.

AlGaN/GaN high-electron-mobility transistors with transparent gates by Al-doped ZnO

International Nuclear Information System (INIS)

Wang Chong; He Yun-Long; Zheng Xue-Feng; Ma Xiao-Hua; Zhang Jin-Cheng; Hao Yue

2013-01-01

AlGaN/GaN high-electron-mobility transistors (HEMTs) with Al-doped ZnO (AZO) transparent gate electrodes are fabricated, and Ni/Au/Ni-gated HEMTs are produced in comparison. The AZO-gated HEMTs show good DC characteristics and Schottky rectifying characteristics, and the gate electrodes achieve excellent transparencies. Compared with Ni/Au/Ni-gated HEMTs, AZO-gated HEMTs show a low saturation current, high threshold voltage, high Schottky barrier height, and low gate reverse leakage current. Due to the higher gate resistivity, AZO-gated HEMTs exhibit a current—gain cutoff frequency (f T ) of 10 GHz and a power gain cutoff frequency (f max ) of 5 GHz, and lower maximum oscillation frequency than Ni/Au/Ni-gated HEMTs. Moreover, the C—V characteristics are measured and the gate interface characteristics of the AZO-gated devices are investigated by a C—V dual sweep

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

International Nuclear Information System (INIS)

Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

2014-01-01

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

Directory of Open Access Journals (Sweden)

Muhammad Nawaz

2015-01-01

Full Text Available This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high-k gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-k gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 (k=3.9 to HfO2 (k=25. This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-{mu}m CMOS

Energy Technology Data Exchange (ETDEWEB)

Zhang Changchun; Wang Zhigong; Shi Si; Guo Yufeng, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

2010-03-15

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-{mu}m CMOS technology. The Pottbaecker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 x 440 {mu}m{sup 2}, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of -111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components. (semiconductor integrated circuits)

Performance projections and design optimization of planar double gate SOI MOSFETs for logic technology applications

International Nuclear Information System (INIS)

Kranti, Abhinav; Hao Ying; Armstrong, G Alastair

2008-01-01

In this paper, by investigating the influence of source/drain extension region engineering (also known as gate–source/drain underlap) in nanoscale planar double gate (DG) SOI MOSFETs, we offer new insights into the design of future nanoscale gate-underlap DG devices to achieve ITRS projections for high performance (HP), low standby power (LSTP) and low operating power (LOP) logic technologies. The impact of high-κ gate dielectric, silicon film thickness, together with parameters associated with the lateral source/drain doping profile, is investigated in detail. The results show that spacer width along with lateral straggle can not only effectively control short-channel effects, thus presenting low off-current in a gate underlap device, but can also be optimized to achieve lower intrinsic delay and higher on–off current ratio (I on /I off ). Based on the investigation of on-current (I on ), off-current (I off ), I on /I off , intrinsic delay (τ), energy delay product and static power dissipation, we present design guidelines to select key device parameters to achieve ITRS projections. Using nominal gate lengths for different technologies, as recommended from ITRS specification, optimally designed gate-underlap DG MOSFETs with a spacer-to-straggle (s/σ) ratio of 2.3 for HP/LOP and 3.2 for LSTP logic technologies will meet ITRS projection. However, a relatively narrow range of lateral straggle lying between 7 to 8 nm is recommended. A sensitivity analysis of intrinsic delay, on-current and off-current to important parameters allows a comparative analysis of the various design options and shows that gate workfunction appears to be the most crucial parameter in the design of DG devices for all three technologies. The impact of back gate misalignment on I on , I off and τ is also investigated for optimized underlap devices

Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

Directory of Open Access Journals (Sweden)

W. M. Tang

2012-01-01

Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

Topologically protected gates for quantum computation with non-Abelian anyons in the Pfaffian quantum Hall state

Science.gov (United States)

Georgiev, Lachezar S.

2006-12-01

We extend the topological quantum computation scheme using the Pfaffian quantum Hall state, which has been recently proposed by Das Sarma , in a way that might potentially allow for the topologically protected construction of a universal set of quantum gates. We construct, for the first time, a topologically protected controlled-NOT gate, which is entirely based on quasihole braidings of Pfaffian qubits. All single-qubit gates, except for the π/8 gate, are also explicitly implemented by quasihole braidings. Instead of the π/8 gate we try to construct a topologically protected Toffoli gate, in terms of the controlled-phase gate and CNOT or by a braid-group-based controlled-controlled- Z precursor. We also give a topologically protected realization of the Bravyi-Kitaev two-qubit gate g3 .

Alternative approach of developing all-optical Fredkin and Toffoli gates

Science.gov (United States)

Mandal, Dhoumendra; Mandal, Sumana; Garai, Sisir Kumar

2015-09-01

Reversible logic gates show potential roles in communication technology, and it has a wide area of applicability such as in sequential and combinational circuit of optical computing, optical signal processing, multi-valued logic operations, etc. because of its advantageous aspects of data-recovering capabilities, low power consumption, least power dissipation, faster speed of processing, less hardware complexity, etc. In a reversible logic gate not only the outputs can be determined from the inputs, but also the inputs can be uniquely recovered from the outputs. In this article an alternative approach has been made to develop three-input-output Fredkin and Toffoli gates using the frequency conversion property of semiconductor optical amplifier (SOA) and frequency-based beam routing by optical multiplexers and demultiplexers. Simulation results show the feasibility of our proposed scheme.

Stable, Extreme Temperature, High Radiation, Compact. Low Power Clock Oscillator for Space, Geothermal, Down-Hole & other High Reliability Applications, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — Efficient and stable clock signal generation requirements at extreme temperatures (-180C to +450C)and radiation (>250 Krad TID) are not met with the current...

Temperature-gated thermal rectifier for active heat flow control.

Science.gov (United States)

Zhu, Jia; Hippalgaonkar, Kedar; Shen, Sheng; Wang, Kevin; Abate, Yohannes; Lee, Sangwook; Wu, Junqiao; Yin, Xiaobo; Majumdar, Arun; Zhang, Xiang

2014-08-13

Active heat flow control is essential for broad applications of heating, cooling, and energy conversion. Like electronic devices developed for the control of electric power, it is very desirable to develop advanced all-thermal solid-state devices that actively control heat flow without consuming other forms of energy. Here we demonstrate temperature-gated thermal rectification using vanadium dioxide beams in which the environmental temperature actively modulates asymmetric heat flow. In this three terminal device, there are two switchable states, which can be regulated by global heating. In the "Rectifier" state, we observe up to 28% thermal rectification. In the "Resistor" state, the thermal rectification is significantly suppressed (Rectifier state. This temperature-gated rectifier can have substantial implications ranging from autonomous thermal management of heating and cooling systems to efficient thermal energy conversion and storage.

RF-Interrogated End-State Chip-Scale Atomic Clock

Science.gov (United States)

2007-11-01

coherent population trapping,” Electronics Letters 37, (24), 1449-1451. [2] R. Lutwak , P. Vlitas, M. Varghese, M. Mescher, D. K. Serkland, and G. M...367. [9] R. Lutwak , D. Emmons, T. English, W. Riley, A. Duwel, M. Varghese, D. K. Serland, and G. M. Peake, 2003, “Chip-Scale Atomic Clock, Recent

Improving Power Converter Reliability

DEFF Research Database (Denmark)

Ghimire, Pramod; de Vega, Angel Ruiz; Beczkowski, Szymon

2014-01-01

of a high-power IGBT module during converter operation, which may play a vital role in improving the reliability of the power converters. The measured voltage is used to estimate the module average junction temperature of the high and low-voltage side of a half-bridge IGBT separately in every fundamental......The real-time junction temperature monitoring of a high-power insulated-gate bipolar transistor (IGBT) module is important to increase the overall reliability of power converters for industrial applications. This article proposes a new method to measure the on-state collector?emitter voltage...... is measured in a wind power converter at a low fundamental frequency. To illustrate more, the test method as well as the performance of the measurement circuit are also presented. This measurement is also useful to indicate failure mechanisms such as bond wire lift-off and solder layer degradation...

Containment forces in low energy states of plasmoids

International Nuclear Information System (INIS)

Wells, D.R.; Hawkins, L.C.

1987-01-01

The application of Hamilton's principle to the problem of the determination of the structure of low free energy state plasmoids is discussed. It is shown that Clebsch representations of the vector fields and representations involving side conditions on the functional result in the same sets of Euler-Lagrange equations. The relationship of these representations to the problem of containment forces in vortex structures (plasmoids) is considered. It is demonstrated that the lowest free energy state of an incompressible plasma is always Lorentz force and Magnus force free. For a compressible plasma obeying the adiabatic gas laws, the Magnus force is finite. Introduction of conservation of angular momentum as an additional side condition also results in finite containment forces. (author)

A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

Energy Technology Data Exchange (ETDEWEB)

Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

2015-01-01

A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

Modeling and simulation of floating gate nanocrystal FET devices and circuits

Science.gov (United States)

Hasaneen, El-Sayed A. M.

The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to

Real-time field programmable gate array architecture for computer vision

Science.gov (United States)

Arias-Estrada, Miguel; Torres-Huitzil, Cesar

2001-01-01

This paper presents an architecture for real-time generic convolution of a mask and an image. The architecture is intended for fast low-level image processing. The field programmable gate array (FPGA)-based architecture takes advantage of the availability of registers in FPGAs to implement an efficient and compact module to process the convolutions. The architecture is designed to minimize the number of accesses to the image memory and it is based on parallel modules with internal pipeline operation in order to improve its performance. The architecture is prototyped in a FPGA, but it can be implemented on dedicated very- large-scale-integrated devices to reach higher clock frequencies. Complexity issues, FPGA resources utilization, FPGA limitations, and real-time performance are discussed. Some results are presented and discussed.

High Precision Clock Bias Prediction Model in Clock Synchronization System

Directory of Open Access Journals (Sweden)

Zan Liu

2016-01-01

Full Text Available Time synchronization is a fundamental requirement for many services provided by a distributed system. Clock calibration through the time signal is the usual way to realize the synchronization among the clocks used in the distributed system. The interference to time signal transmission or equipment failures may bring about failure to synchronize the time. To solve this problem, a clock bias prediction module is paralleled in the clock calibration system. And for improving the precision of clock bias prediction, the first-order grey model with one variable (GM(1,1 model is proposed. In the traditional GM(1,1 model, the combination of parameters determined by least squares criterion is not optimal; therefore, the particle swarm optimization (PSO is used to optimize GM(1,1 model. At the same time, in order to avoid PSO getting stuck at local optimization and improve its efficiency, the mechanisms that double subgroups and nonlinear decreasing inertia weight are proposed. In order to test the precision of the improved model, we design clock calibration experiments, where time signal is transferred via radio and wired channel, respectively. The improved model is built on the basis of clock bias acquired in the experiments. The results show that the improved model is superior to other models both in precision and in stability. The precision of improved model increased by 66.4%~76.7%.

The circadian molecular clock regulates adult hippocampal neurogenesis by controlling the timing of cell-cycle entry and exit.

Science.gov (United States)

Bouchard-Cannon, Pascale; Mendoza-Viveros, Lucia; Yuen, Andrew; Kærn, Mads; Cheng, Hai-Ying M

2013-11-27

The subgranular zone (SGZ) of the adult hippocampus contains a pool of quiescent neural progenitor cells (QNPs) that are capable of entering the cell cycle and producing newborn neurons. The mechanisms that control the timing and extent of adult neurogenesis are not well understood. Here, we show that QNPs of the adult SGZ express molecular-clock components and proliferate in a rhythmic fashion. The clock proteins PERIOD2 and BMAL1 are critical for proper control of neurogenesis. The absence of PERIOD2 abolishes the gating of cell-cycle entrance of QNPs, whereas genetic ablation of bmal1 results in constitutively high levels of proliferation and delayed cell-cycle exit. We use mathematical model simulations to show that these observations may arise from clock-driven expression of a cell-cycle inhibitor that targets the cyclin D/Cdk4-6 complex. Our findings may have broad implications for the circadian clock in timing cell-cycle events of other stem cell populations throughout the body. Copyright © 2013 The Authors. Published by Elsevier Inc. All rights reserved.

Deterministic nonlinear phase gates induced by a single qubit

Science.gov (United States)

Park, Kimin; Marek, Petr; Filip, Radim

2018-05-01

We propose deterministic realizations of nonlinear phase gates by repeating a finite sequence of non-commuting Rabi interactions between a harmonic oscillator and only a single two-level ancillary qubit. We show explicitly that the key nonclassical features of the ideal cubic phase gate and the quartic phase gate are generated in the harmonic oscillator faithfully by our method. We numerically analyzed the performance of our scheme under realistic imperfections of the oscillator and the two-level system. The methodology is extended further to higher-order nonlinear phase gates. This theoretical proposal completes the set of operations required for continuous-variable quantum computation.

The pollution of the 'iron gate' reservoir

International Nuclear Information System (INIS)

Babic-Mladenovic, M.; Varga, S; Popovic, L.; Damjanovic, M.

2002-01-01

The paper presents the characteristics of the Iron Gate I (the Djerdap) Water Power and Navigational System, one of the largest in Europe (completed in 1972 by joint efforts of Yugoslavia and Romania). In this paper the attention is devoted to review of the sediment monitoring program and impacts of reservoir sedimentation, as well as to the investigations of water and sediment quality. Special consideration is paid to the issue of sediment pollution research needs. Namely, the hot spot of the 'Iron Gate' sedimentation represents a scarcely known pollution of sediment deposits. The present pollution probably is considerable, since the 'Iron Gate' reservoir drains about 577000 km 2 , with over 80 million inhabitants, and developed municipal and industrial infrastructure. Therefore, in the thirty-year reservoir life various types of sediment-bound pollutants entered and deposited within it. Especially severe incidents happened during 1999 (as a result of NATO bombing campaign) and 2000 (two accidental pollutions in the Tisza river catchment). The study of the 'Iron Gate' reservoir pollution should be prepared in order to enlighten the present state of reservoir sedimentation and pollution. The main objectives of the study are to enhance the government and public awareness of the present environmental state of the 'Iron Gate' reservoir and to serve as a baseline for all future actions. (author)

Method and apparatus to debug an integrated circuit chip via synchronous clock stop and scan

Science.gov (United States)

Bellofatto, Ralph E [Ridgefield, CT; Ellavsky, Matthew R [Rochester, MN; Gara, Alan G [Mount Kisco, NY; Giampapa, Mark E [Irvington, NY; Gooding, Thomas M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Hehenberger, Lance G [Leander, TX; Ohmacht, Martin [Yorktown Heights, NY

2012-03-20

An apparatus and method for evaluating a state of an electronic or integrated circuit (IC), each IC including one or more processor elements for controlling operations of IC sub-units, and each the IC supporting multiple frequency clock domains. The method comprises: generating a synchronized set of enable signals in correspondence with one or more IC sub-units for starting operation of one or more IC sub-units according to a determined timing configuration; counting, in response to one signal of the synchronized set of enable signals, a number of main processor IC clock cycles; and, upon attaining a desired clock cycle number, generating a stop signal for each unique frequency clock domain to synchronously stop a functional clock for each respective frequency clock domain; and, upon synchronously stopping all on-chip functional clocks on all frequency clock domains in a deterministic fashion, scanning out data values at a desired IC chip state. The apparatus and methodology enables construction of a cycle-by-cycle view of any part of the state of a running IC chip, using a combination of on-chip circuitry and software.

A 10 MHz Bandwidth Continuous-Time Delta-Sigma Modulator for Portable Ultrasound Scanners

DEFF Research Database (Denmark)

Llimos Muntal, Pere; Jørgensen, Ivan Harald Holger; Bruun, Erik

2016-01-01

comparator and a pull-down clocked latch. The feedback signal is generated with voltage DACs based on transmission gates. Using this implementation, a small and low-power solution required for portable ultrasound scanner applications is achieved. The modulator has a bandwidth of 10 MHz with an oversampling......A fourth-order 1-bit continuous-time delta-sigma modulator designed in a 65 nm process for portable ultrasound scanners is presented in this paper. The loop filter consists of RCintegrators, with programmable capacitor arrays and resistors, and the quantizer is implemented with a high-speed clocked...

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey; Qaisi, Ramy M.; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

2013-01-01

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

KAUST Repository

Smith, Casey

2013-07-23

Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

Energy Technology Data Exchange (ETDEWEB)

Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

2015-08-31

This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

Ultra low power CMOS-based sensor for on-body radiation dose measurements

KAUST Repository

Arsalan, Muhammad

2012-03-01

For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA\\'s 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

Ultra low power CMOS-based sensor for on-body radiation dose measurements

KAUST Repository

Arsalan, Muhammad; Shamim, Atif; Shams, Maitham; Tarr, Nathan Garry; Roy, Langis

2012-01-01

For the first time, a dosimeter employing two floating gate radiation field effect transistors (FGRADFET) and operating at mere 0.1 V is presented. The novel dosimeter requires no power during irradiation and consumes only 1 μ Wduring readout. Besides the low power operation, structural changes at the device level have enhanced the sensitivity of the dosimeter considerably as compared to previous designs. The dosimeter is integrated with a wireless transmitter chip, thus eliminating all unwanted communication and power cables. It has been realized monolithically in DALSA's 0.8 μ m complementary metal-oxide-semiconductor process and characterized with X-ray and γ-ray sources. A maximum sensitivity of 5 mV/rad for X-rays and 1.1 mV/rad for gamma;-rays have been achieved in measurements. Due to its small size, low-power, and wireless operation, the design is highly suitable for miniaturized, wearable, and battery operated dosimeters intended for radiotherapy and space applications. © 2012 IEEE.

Development of an atomic clock on an atom chip: Optimisation of the coherence time and preliminary characterisation

International Nuclear Information System (INIS)

Lacroute, Clement

2010-01-01

We describe the construction and preliminary characterization of an atomic clock on an atom chip. A sample of magnetically trapped 87 Rb atoms is cooled below 1 μK, close to Bose- Einstein condensation temperature. The trapped states |F = 1; m F = -1> and |F = 2;m F = 1> define our two-photon clock transition. Atoms are trapped around a field B0 = 3.23 G, where the clock frequency is first-order insensitive to magnetic field fluctuations. We have designed an atom chip that includes a microwave coplanar waveguide which drives the 6.835 GHz transition. The whole clock cycle is performed in the vicinity of the chip surface, making the physics package compact (5 cm) 3 . We first describe the experimental setup of the clock, and the optical bench that has been developed and characterized during this thesis. We then give the results obtained for atom cooling, which led to obtaining a 3 10 4 atoms Bose-Einstein condensate. We finally present the results obtained by Ramsey spectroscopy of the clock transition. We measure coherence times exceeding 10 seconds with our setup, dominated by atom losses. A preliminary measurement shows that the clock relative frequency stability is of 6 10 -12 at 1 s, limited by technical noise. Our goal is to reach a stability in the low 10 -13 at 1 s, i.e. better than commercial clocks and competitive with today's best compact clocks. (author)

The gate oxide integrity of CVD tungsten polycide

International Nuclear Information System (INIS)

Wu, N.W.; Su, W.D.; Chang, S.W.; Tseng, M.F.

1988-01-01

CVD tungsten polycide has been demonstrated as a good gate material in recent very large scale integration (VLSI) technology. CVD tungsten silicide offers advantages of low resistivity, high temperature stability and good step coverage. On the other hand, the polysilicon underlayer preserves most characteristics of the polysilicon gate and acts as a stress buffer layer to absorb part of the thermal stress origin from the large thermal expansion coefficient of tungsten silicide. Nevertheless, the gate oxide of CVD tungsten polycide is less stable or reliable than that of polysilicon gate. In this paper, the gate oxide integrity of CVD tungsten polycide with various thickness combinations and different thermal processes have been analyzed by several electrical measurements including breakdown yield, breakdown fluence, room temperature TDDB, I-V characteristics, electron traps and interface state density

Efficient construction of two-dimensional cluster states with probabilistic quantum gates

International Nuclear Information System (INIS)

Chen Qing; Cheng Jianhua; Wang Kelin; Du Jiangfeng

2006-01-01

We propose an efficient scheme for constructing arbitrary two-dimensional (2D) cluster states using probabilistic entangling quantum gates. In our scheme, the 2D cluster state is constructed with starlike basic units generated from 1D cluster chains. By applying parallel operations, the process of generating 2D (or higher-dimensional) cluster states is significantly accelerated, which provides an efficient way to implement realistic one-way quantum computers

A CMOS Micro-power, Class-AB “Flipped” Voltage Follower using the quasi floating-gate technique

Directory of Open Access Journals (Sweden)

Juan Jesus Ocampo-Hidalgo

2017-05-01

Full Text Available This paper presents the design and characterization of a new analog voltage follower for low-voltage applications. The main idea is based on the “Flipped” Voltage Follower and the use of the quasi-floating gate technique for achieving class AB operation. A test cell was simulated and fabricated using a 0,5 μm CMOS technology. When the proposed circuit is supplied with VDD = 1,5 V, it presents a power consumption of only 413 μW. Measurement and experimental results show a gain bandwidth product of 10 MHz and a total harmonic distortion of 1,12 % at 1 MHz.

Chaotic logic gate: A new approach in set and design by genetic algorithm

International Nuclear Information System (INIS)

Beyki, Mahmood; Yaghoobi, Mahdi

2015-01-01

How to reconfigure a logic gate is an attractive subject for different applications. Chaotic systems can yield a wide variety of patterns and here we use this feature to produce a logic gate. This feature forms the basis for designing a dynamical computing device that can be rapidly reconfigured to become any wanted logical operator. This logic gate that can reconfigure to any logical operator when placed in its chaotic state is called chaotic logic gate. The reconfiguration realize by setting the parameter values of chaotic logic gate. In this paper we present mechanisms about how to produce a logic gate based on the logistic map in its chaotic state and genetic algorithm is used to set the parameter values. We use three well-known selection methods used in genetic algorithm: tournament selection, Roulette wheel selection and random selection. The results show the tournament selection method is the best method for set the parameter values. Further, genetic algorithm is a powerful tool to set the parameter values of chaotic logic gate

GaN-on-silicon high-electron-mobility transistor technology with ultra-low leakage up to 3000 V using local substrate removal and AlN ultra-wide bandgap

Science.gov (United States)

Dogmus, Ezgi; Zegaoui, Malek; Medjdoub, Farid

2018-03-01

We report on extremely low off-state leakage current in AlGaN/GaN-on-silicon metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) up to a high blocking voltage. Remarkably low off-state gate and drain leakage currents below 1 µA/mm up to 3 kV have been achieved owing to the use of a thick in situ SiN gate dielectric under the gate, and a local Si substrate removal technique combined with a cost effective 15-µm-thick AlN dielectric layer followed by a Cu deposition. This result establishes a manufacturable state-of-the-art high-voltage GaN-on-silicon power transistors while maintaining a low specific on-resistance of approximately 10 mΩ·cm2.

Finite-time generalized function matrix projective lag synchronization of coupled dynamical networks with different dimensions via the double power function nonlinear feedback control method

International Nuclear Information System (INIS)

Dai, Hao; Si, Gangquan; Jia, Lixin; Zhang, Yanbin

2014-01-01

This paper investigates the problem of finite-time generalized function matrix projective lag synchronization between two different coupled dynamical networks with different dimensions of network nodes. The double power function nonlinear feedback control method is proposed in this paper to guarantee that the state trajectories of the response network converge to the state trajectories of the drive network according to a function matrix in a given finite time. Furthermore, in comparison with the traditional nonlinear feedback control method, the new method improves the synchronization efficiency, and shortens the finite synchronization time. Numerical simulation results are presented to illustrate the effectiveness of this method. (papers)

A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

International Nuclear Information System (INIS)

Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

2013-01-01

A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

A General Finite Element Scheme for Limit State Analysis and Optimization

DEFF Research Database (Denmark)

Damkilde, Lars

1999-01-01

Limit State analysis which is based on a perfect material behaviour is used in many different applications primarily within Structural Engineering and Geotechnics. The calculation methods have not reached the same level of automation such as Finite Element Analysis for elastic structures....... The computer based systems are more ad hoc based and are typically not well-integrated with pre- and postprocessors well-known from commercial Finite Element codes.A finite element based formulation of limit state analysis is presented which allows an easy integration with standard Finite Element codes...... for elastic analysis. In this way the user is able to perform a limit state analysis on the same model used for elastic analysis only adding data for the yield surface.The method is based on the lower-bound theorem and uses stress-based elements with a linearized yield surface. The mathematical problem...

Socio-economic applications of finite state mean field games.

Science.gov (United States)

Gomes, Diogo; Velho, Roberto M; Wolfram, Marie-Therese

2014-11-13

In this paper, we present different applications of finite state mean field games to socio-economic sciences. Examples include paradigm shifts in the scientific community or consumer choice behaviour in the free market. The corresponding finite state mean field game models are hyperbolic systems of partial differential equations, for which we present and validate different numerical methods. We illustrate the behaviour of solutions with various numerical experiments, which show interesting phenomena such as shock formation. Hence, we conclude with an investigation of the shock structure in the case of two-state problems. © 2014 The Author(s) Published by the Royal Society. All rights reserved.

Switching current imbalance mitigation in power modules with parallel connected SiC MOSFETs

DEFF Research Database (Denmark)

Beczkowski, Szymon; Jørgensen, Asger Bjørn; Li, Helong

2017-01-01

Multichip power modules use parallel connected chips to achieve high current rating. Due to a finite flexibility in a DBC layout, some electrical asymmetries will occur in the module. Parallel connected transistors will exhibit uneven static and dynamic current sharing due to these asymmetries....... Especially important are the couplings between gate and power loops of individual transistors. Fast changing source currents cause gate voltage imbalances yielding uneven switching currents. Equalizing gate voltages seen by paralleled transistors, done by adjusting source bond wires, is proposed...... in this paper. Analysis is performed on an industry standard DBC layout using numerically extracted module parasitics. The method of tuning individual source inductances shows clear improvement in dynamic current balancing and prevents excessive current overshoot during transistors turn-on....

Development of MOS-FET based Marx generator with self-proved gate power

International Nuclear Information System (INIS)

Tokuchi, A.; Jiang, W.; Takayama, K.; Arai, T.; Kawakubo, T.; Adachi, T.

2012-01-01

New MOS-FET based Marx generator is described. An electric gate power for the MOS-FET is provided from the Marx main circuit itself. Four-stage Marx generator generates -12kV of the output voltage. The Marx Generator is successfully used to drive an Einzel lens chopper to generate a short pulsed ion beam for a KEK digital accelerator. (author)

Probing many-body interactions in an optical lattice clock

Energy Technology Data Exchange (ETDEWEB)

Rey, A.M., E-mail: arey@jilau1.colorado.edu [JILA, NIST and University of Colorado, Department of Physics, Boulder, CO 80309 (United States); Gorshkov, A.V. [Joint Quantum Institute, NIST and University of Maryland, Department of Physics, College Park, MD 20742 (United States); Kraus, C.V. [Institute for Quantum Optics and Quantum Information of the Austrian Academy of Sciences, A-6020 Innsbruck (Austria); Institute for Theoretical Physics, University of Innsbruck, A-6020 Innsbruck (Austria); Martin, M.J. [JILA, NIST and University of Colorado, Department of Physics, Boulder, CO 80309 (United States); Institute for Quantum Information and Matter, California Institute of Technology, Pasadena, CA 91125 (United States); Bishof, M.; Swallows, M.D.; Zhang, X.; Benko, C.; Ye, J. [JILA, NIST and University of Colorado, Department of Physics, Boulder, CO 80309 (United States); Lemke, N.D.; Ludlow, A.D. [National Institute of Standards and Technology, Boulder, CO 80305 (United States)

2014-01-15

We present a unifying theoretical framework that describes recently observed many-body effects during the interrogation of an optical lattice clock operated with thousands of fermionic alkaline earth atoms. The framework is based on a many-body master equation that accounts for the interplay between elastic and inelastic p-wave and s-wave interactions, finite temperature effects and excitation inhomogeneity during the quantum dynamics of the interrogated atoms. Solutions of the master equation in different parameter regimes are presented and compared. It is shown that a general solution can be obtained by using the so called Truncated Wigner Approximation which is applied in our case in the context of an open quantum system. We use the developed framework to model the density shift and decay of the fringes observed during Ramsey spectroscopy in the JILA {sup 87}Sr and NIST {sup 171}Yb optical lattice clocks. The developed framework opens a suitable path for dealing with a variety of strongly-correlated and driven open-quantum spin systems. -- Highlights: •Derived a theoretical framework that describes many-body effects in a lattice clock. •Validated the analysis with recent experimental measurements. •Demonstrated the importance of beyond mean field corrections in the dynamics.

Floquet states of a kicked particle in a singular potential: Exponential and power-law profiles

Science.gov (United States)

Paul, Sanku; Santhanam, M. S.

2018-03-01

It is well known that, in the chaotic regime, all the Floquet states of kicked rotor system display an exponential profile resulting from dynamical localization. If the kicked rotor is placed in an additional stationary infinite potential well, its Floquet states display power-law profile. It has also been suggested in general that the Floquet states of periodically kicked systems with singularities in the potential would have power-law profile. In this work, we study the Floquet states of a kicked particle in finite potential barrier. By varying the height of finite potential barrier, the nature of transition in the Floquet state from exponential to power-law decay profile is studied. We map this system to a tight-binding model and show that the nature of decay profile depends on energy band spanned by the Floquet states (in unperturbed basis) relative to the potential height. This property can also be inferred from the statistics of Floquet eigenvalues and eigenvectors. This leads to an unusual scenario in which the level spacing distribution, as a window in to the spectral correlations, is not a unique characteristic for the entire system.

Multiscale energy reallocation during low-frequency steady-state brain response.

Science.gov (United States)

Wang, Yifeng; Chen, Wang; Ye, Liangkai; Biswal, Bharat B; Yang, Xuezhi; Zou, Qijun; Yang, Pu; Yang, Qi; Wang, Xinqi; Cui, Qian; Duan, Xujun; Liao, Wei; Chen, Huafu

2018-05-01

Traditional task-evoked brain activations are based on detection and estimation of signal change from the mean signal. By contrast, the low-frequency steady-state brain response (lfSSBR) reflects frequency-tagging activity at the fundamental frequency of the task presentation and its harmonics. Compared to the activity at these resonant frequencies, brain responses at nonresonant frequencies are largely unknown. Additionally, because the lfSSBR is defined by power change, we hypothesize using Parseval's theorem that the power change reflects brain signal variability rather than the change of mean signal. Using a face recognition task, we observed power increase at the fundamental frequency (0.05 Hz) and two harmonics (0.1 and 0.15 Hz) and power decrease within the infra-slow frequency band ( .955) of their spatial distribution and brain-behavior relationship at all frequency bands. Additionally, the reallocation of finite energy was observed across various brain regions and frequency bands, forming a particular spatiotemporal pattern. Overall, results from this study strongly suggest that frequency-specific power and variability may measure the same underlying brain activity and that these results may shed light on different mechanisms between lfSSBR and brain activation, and spatiotemporal characteristics of energy reallocation induced by cognitive tasks. © 2018 Wiley Periodicals, Inc.

Simulating quantum search algorithm using vibronic states of I2 manipulated by optimally designed gate pulses

International Nuclear Information System (INIS)

Ohtsuki, Yukiyoshi

2010-01-01

In this paper, molecular quantum computation is numerically studied with the quantum search algorithm (Grover's algorithm) by means of optimal control simulation. Qubits are implemented in the vibronic states of I 2 , while gate operations are realized by optimally designed laser pulses. The methodological aspects of the simulation are discussed in detail. We show that the algorithm for solving a gate pulse-design problem has the same mathematical form as a state-to-state control problem in the density matrix formalism, which provides monotonically convergent algorithms as an alternative to the Krotov method. The sequential irradiation of separately designed gate pulses leads to the population distribution predicted by Grover's algorithm. The computational accuracy is reduced by the imperfect quality of the pulse design and by the electronic decoherence processes that are modeled by the non-Markovian master equation. However, as long as we focus on the population distribution of the vibronic qubits, we can search a target state with high probability without introducing error-correction processes during the computation. A generalized gate pulse-design scheme to explicitly include decoherence effects is outlined, in which we propose a new objective functional together with its solution algorithm that guarantees monotonic convergence.

A gate drive circuit for gate-turn-off (GTO) devices in series stack

International Nuclear Information System (INIS)

Despe, O.

1999-01-01

A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements

Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module

Science.gov (United States)

2015-02-01

executed with SolidWorks Flow Simulation , a computational fluid-dynamics code. The graph in Fig. 2 shows the timing and amplitudes of power pulses...defined a convective flow of air perpendicular to the bottom surface of the mounting plate, with a velocity of 10 ft/s. The thermal simulations were...Thermal Simulation of Switching Pulses in an Insulated Gate Bipolar Transistor (IGBT) Power Module by Gregory K Ovrebo ARL-TR-7210

Performance Evaluation of Clock Recovery for Coherent Mode Division Multiplexed Systems

DEFF Research Database (Denmark)

Medeiros Diniz, Júlio César; Piels, Molly; Zibar, Darko

2017-01-01

The impact of mode mixing and group delay spread on clock tone quality of a 6-mode 32 GBd NRZ-QPSK MDM system is investigated. Even for low group delay spread, strong coupling causes clock tone disappearance....

Gating of Connexin Channels by transjunctional-voltage: Conformations and models of open and closed states.

Science.gov (United States)

Bargiello, Thaddeus A; Oh, Seunghoon; Tang, Qingxiu; Bargiello, Nicholas K; Dowd, Terry L; Kwon, Taekyung

2018-01-01

Voltage is an important physiologic regulator of channels formed by the connexin gene family. Connexins are unique among ion channels in that both plasma membrane inserted hemichannels (undocked hemichannels) and intercellular channels (aggregates of which form gap junctions) have important physiological roles. The hemichannel is the fundamental unit of gap junction voltage-gating. Each hemichannel displays two distinct voltage-gating mechanisms that are primarily sensitive to a voltage gradient formed along the length of the channel pore (the transjunctional voltage) rather than sensitivity to the absolute membrane potential (V m or V i-o ). These transjunctional voltage dependent processes have been termed V j - or fast-gating and loop- or slow-gating. Understanding the mechanism of voltage-gating, defined as the sequence of voltage-driven transitions that connect open and closed states, first and foremost requires atomic resolution models of the end states. Although ion channels formed by connexins were among the first to be characterized structurally by electron microscopy and x-ray diffraction in the early 1980's, subsequent progress has been slow. Much of the current understanding of the structure-function relations of connexin channels is based on two crystal structures of Cx26 gap junction channels. Refinement of crystal structure by all-atom molecular dynamics and incorporation of charge changing protein modifications has resulted in an atomic model of the open state that arguably corresponds to the physiologic open state. Obtaining validated atomic models of voltage-dependent closed states is more challenging, as there are currently no methods to solve protein structure while a stable voltage gradient is applied across the length of an oriented channel. It is widely believed that the best approach to solve the atomic structure of a voltage-gated closed ion channel is to apply different but complementary experimental and computational methods and to use

Highly Efficient, Zero-Skew, Integrated Clock Distribution Networks Using Salphasic Principles

Directory of Open Access Journals (Sweden)

PASCA, A.

2016-02-01

Full Text Available The design of highly efficient clock distributions for integrated circuits is an active topic of research as there will never be a single solution for all systems. For high performance digital or mixed-signal circuits, achieving zero-skew clock over large areas usually comes with high costs in power requirements and design complexity. The present paper shows an overview of a recently proposed technique for ICs - on-die salphasic clock distribution, introduced by the author for CMOS processes. Initially reported in literature for rack-systems, the present paper shows that further refinements are needed for the concept to be applicable on a silicon die. Based on the formation of a standing wave (intrinsically presenting extended in-phase regions with a voltage peak at the input (creating a no-load condition, it is shown that any IC implementation must use transmission lines loss compensation techniques to maintain the proper standing wave configuration. Furthermore, the paper shows theoretical solutions and describes practical on-die techniques for pseudo-spherical bidimensional surfaces, which, with the already reported orthogonal and pseudo-orthogonal structures, can be used to distribute with minimal power requirements a zero-skew clock signal, over large silicon areas.

High-fidelity quantum gates on quantum-dot-confined electron spins in low-Q optical microcavities

Science.gov (United States)

Li, Tao; Gao, Jian-Cun; Deng, Fu-Guo; Long, Gui-Lu

2018-04-01

We propose some high-fidelity quantum circuits for quantum computing on electron spins of quantum dots (QD) embedded in low-Q optical microcavities, including the two-qubit controlled-NOT gate and the multiple-target-qubit controlled-NOT gate. The fidelities of both quantum gates can, in principle, be robust to imperfections involved in a practical input-output process of a single photon by converting the infidelity into a heralded error. Furthermore, the influence of two different decay channels is detailed. By decreasing the quality factor of the present microcavity, we can largely increase the efficiencies of these quantum gates while their high fidelities remain unaffected. This proposal also has another advantage regarding its experimental feasibility, in that both quantum gates can work faithfully even when the QD-cavity systems are non-identical, which is of particular importance in current semiconductor QD technology.

A self-interfering clock as a "which path" witness.

Science.gov (United States)

Margalit, Yair; Zhou, Zhifan; Machluf, Shimon; Rohrlich, Daniel; Japha, Yonathan; Folman, Ron

2015-09-11

In Einstein's general theory of relativity, time depends locally on gravity; in standard quantum theory, time is global-all clocks "tick" uniformly. We demonstrate a new tool for investigating time in the overlap of these two theories: a self-interfering clock, comprising two atomic spin states. We prepare the clock in a spatial superposition of quantum wave packets, which evolve coherently along two paths into a stable interference pattern. If we make the clock wave packets "tick" at different rates, to simulate a gravitational time lag, the clock time along each path yields "which path" information, degrading the pattern's visibility. In contrast, in standard interferometry, time cannot yield "which path" information. This proof-of-principle experiment may have implications for the study of time and general relativity and their impact on fundamental effects such as decoherence and the emergence of a classical world. Copyright © 2015, American Association for the Advancement of Science.

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

CERN Document Server

Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

2009-01-01

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

Gate-tunable large magnetoresistance in an all-semiconductor spin valve device.

Science.gov (United States)

Oltscher, M; Eberle, F; Kuczmik, T; Bayer, A; Schuh, D; Bougeard, D; Ciorga, M; Weiss, D

2017-11-27

A large spin-dependent and electric field-tunable magnetoresistance of a two-dimensional electron system is a key ingredient for the realization of many novel concepts for spin-based electronic devices. The low magnetoresistance observed during the last few decades in devices with lateral semiconducting transport channels between ferromagnetic source and drain contacts has been the main obstacle for realizing spin field effect transistor proposals. Here, we show both a large two-terminal magnetoresistance in a lateral spin valve device with a two-dimensional channel, with up to 80% resistance change, and tunability of the magnetoresistance by an electric gate. The enhanced magnetoresistance is due to finite electric field effects at the contact interface, which boost spin-to-charge conversion. The gating scheme that we use is based on switching between uni- and bidirectional spin diffusion, without resorting to spin-orbit coupling. Therefore, it can also be employed in materials with low spin-orbit coupling.

Clock Drawing in Spatial Neglect: A Comprehensive Analysis of Clock Perimeter, Placement, and Accuracy

Science.gov (United States)

Chen, Peii; Goedert, Kelly M.

2012-01-01

Clock drawings produced by right-brain-damaged (RBD) individuals with spatial neglect often contain an abundance of empty space on the left while numbers and hands are placed on the right. However, the clock perimeter is rarely compromised in neglect patients’ drawings. By analyzing clock drawings produced by 71 RBD and 40 healthy adults, this study investigated whether the geometric characteristics of the clock perimeter reveal novel insights to understanding spatial neglect. Neglect participants drew smaller clocks than either healthy or non-neglect RBD participants. While healthy participants’ clock perimeter was close to circular, RBD participants drew radially extended ellipses. The mechanisms for these phenomena were investigated by examining the relation between clock-drawing characteristics and performance on six subtests of the Behavioral Inattention Test (BIT). The findings indicated that the clock shape was independent of any BIT subtest or the drawing placement on the test sheet and that the clock size was significantly predicted by one BIT subtest: the poorer the figure and shape copying, the smaller the clock perimeter. Further analyses revealed that in all participants, clocks decreased in size as they were placed farther from the center of the paper. However, even when neglect participants placed their clocks towards the center of the page, they were smaller than those produced by healthy or non-neglect RBD participants. These results suggest a neglect-specific reduction in the subjectively available workspace for graphic production from memory, consistent with the hypothesis that neglect patients are impaired in the ability to enlarge the attentional aperture. PMID:22390278

Method and system employing finite state machine modeling to identify one of a plurality of different electric load types

Science.gov (United States)

Du, Liang; Yang, Yi; Harley, Ronald Gordon; Habetler, Thomas G.; He, Dawei

2016-08-09

A system is for a plurality of different electric load types. The system includes a plurality of sensors structured to sense a voltage signal and a current signal for each of the different electric loads; and a processor. The processor acquires a voltage and current waveform from the sensors for a corresponding one of the different electric load types; calculates a power or current RMS profile of the waveform; quantizes the power or current RMS profile into a set of quantized state-values; evaluates a state-duration for each of the quantized state-values; evaluates a plurality of state-types based on the power or current RMS profile and the quantized state-values; generates a state-sequence that describes a corresponding finite state machine model of a generalized load start-up or transient profile for the corresponding electric load type; and identifies the corresponding electric load type.

Equation of state at finite net-baryon density using Taylor coefficients up to sixth order

International Nuclear Information System (INIS)

Huovinen, Pasi; Petreczky, Péter; Schmidt, Christian

2014-01-01

We employ the lattice QCD data on Taylor expansion coefficients up to sixth order to construct an equation of state at finite net-baryon density. When we take into account how hadron masses depend on lattice spacing and quark mass, the coefficients evaluated using the p4 action are equal to those of hadron resonance gas at low temperature. Thus the parametrised equation of state can be smoothly connected to the hadron resonance gas equation of state. We see that the equation of state using Taylor coefficients up to second order is realistic only at low densities, and that at densities corresponding to s/n B ≳40, the expansion converges by the sixth order term

Edge states in gated bilayer-monolayer graphene ribbons and bilayer domain walls

Science.gov (United States)

Mirzakhani, M.; Zarenia, M.; Peeters, F. M.

2018-05-01

Using the effective continuum model, the electron energy spectrum of gated bilayer graphene with a step-like region of decoupled graphene layers at the edge of the sample is studied. Different types of coupled-decoupled interfaces are considered, i.e., zigzag (ZZ) and armchair junctions, which result in significant different propagating states. Two non-valley-polarized conducting edge states are observed for ZZ type, which are mainly located around the ZZ-ended graphene layers. Additionally, we investigated both BA-BA and BA-AB domain walls in the gated bilayer graphene within the continuum approximation. Unlike the BA-BA domain wall, which exhibits gapped insulating behaviour, the domain walls surrounded by different stackings of bilayer regions feature valley-polarized edge states. Our findings are consistent with other theoretical calculations, such as from the tight-binding model and first-principles calculations, and agree with experimental observations.

Silicon-Carbide Power MOSFET Performance in High Efficiency Boost Power Processing Unit for Extreme Environments

Science.gov (United States)

Ikpe, Stanley A.; Lauenstein, Jean-Marie; Carr, Gregory A.; Hunter, Don; Ludwig, Lawrence L.; Wood, William; Del Castillo, Linda Y.; Fitzpatrick, Fred; Chen, Yuan

2016-01-01

Silicon-Carbide device technology has generated much interest in recent years. With superior thermal performance, power ratings and potential switching frequencies over its Silicon counterpart, Silicon-Carbide offers a greater possibility for high powered switching applications in extreme environment. In particular, Silicon-Carbide Metal-Oxide- Semiconductor Field-Effect Transistors' (MOSFETs) maturing process technology has produced a plethora of commercially available power dense, low on-state resistance devices capable of switching at high frequencies. A novel hard-switched power processing unit (PPU) is implemented utilizing Silicon-Carbide power devices. Accelerated life data is captured and assessed in conjunction with a damage accumulation model of gate oxide and drain-source junction lifetime to evaluate potential system performance at high temperature environments.

Double-gated Si NW FET sensors: Low-frequency noise and photoelectric properties

International Nuclear Information System (INIS)

Gasparyan, F.; Khondkaryan, H.; Arakelyan, A.; Zadorozhnyi, I.; Pud, S.; Vitusevich, S.

2016-01-01

The transport, noise, and photosensitivity properties of an array of silicon nanowire (NW) p"+-p-p"+ field-effect transistors (FETs) are investigated. The peculiarities of photosensitivity and detectivity are analyzed over a wide spectrum range. The absorbance of p-Si NW shifts to the short wavelength region compared with bulk Si. The photocurrent and photosensitivity reach increased values in the UV range of the spectrum at 300 K. It is shown that sensitivity values can be tuned by the drain-source voltage and may reach record values of up to 2–4 A/W at a wavelength of 300 nm at room temperature. Low-frequency noise studies allow calculating the photodetectivity values, which increase with decreasing wavelength down to 300 nm. We show that the drain current of Si NW biochemical sensors substantially depends on pH value and the signal-to-noise ratio reaches the high value of 10"5. Increasing pH sensitivity with gate voltage is revealed for certain source-drain currents of pH-sensors based on Si NW FETs. The noise characteristic index decreases from 1.1 to 0.7 with the growth of the liquid gate voltage. Noise behavior is successfully explained in the framework of the correlated number-mobility unified fluctuation model. pH sensitivity increases as a result of the increase in liquid gate voltage, thus giving the opportunity to measure very low proton concentrations in the electrolyte medium at certain values of the liquid gate voltage.

A Faster Algorithm for Solving One-Clock Priced Timed Games

DEFF Research Database (Denmark)

Hansen, Thomas Dueholm; Ibsen-Jensen, Rasmus; Miltersen, Peter Bro

2013-01-01

previously known time bound for solving one-clock priced timed games was 2O(n2+m) , due to Rutkowski. For our improvement, we introduce and study a new algorithm for solving one-clock priced timed games, based on the sweep-line technique from computational geometry and the strategy iteration paradigm from......One-clock priced timed games is a class of two-player, zero-sum, continuous-time games that was defined and thoroughly studied in previous works. We show that one-clock priced timed games can be solved in time m 12 n n O(1), where n is the number of states and m is the number of actions. The best...

A Faster Algorithm for Solving One-Clock Priced Timed Games

DEFF Research Database (Denmark)

Hansen, Thomas Dueholm; Ibsen-Jensen, Rasmus; Miltersen, Peter Bro

2012-01-01

previously known time bound for solving one-clock priced timed games was 2^(O(n^2+m)), due to Rutkowski. For our improvement, we introduce and study a new algorithm for solving one-clock priced timed games, based on the sweep-line technique from computational geometry and the strategy iteration paradigm from......One-clock priced timed games is a class of two-player, zero-sum, continuous-time games that was defined and thoroughly studied in previous works. We show that one-clock priced timed games can be solved in time m 12^n n^(O(1)), where n is the number of states and m is the number of actions. The best...

Evaluation of Performance and Opportunities for Improvements in Automotive Power Electronics Systems: Preprint

Energy Technology Data Exchange (ETDEWEB)

Moreno, Gilberto; Bennion, Kevin; King, Charles; Narumanchi, Sreekant

2016-06-14

Thermal management strategies for automotive power electronic systems have evolved over time to reduce system cost and to improve reliability and thermal performance. In this study, we characterized the power electronic thermal management systems of two electric-drive vehicles--the 2012 Nissan LEAF and 2014 Honda Accord Hybrid. Tests were conducted to measure the insulated-gate bipolar transistor-to-coolant thermal resistances for both steady-state and transient conditions at various coolant flow rates. Water-ethylene glycol at a temperature of 65 degrees C was used as the coolant for these experiments. Computational fluid dynamics and finite element analysis models of the vehicle's power electronics thermal management system were then created and validated using experimentally obtained results. Results indicate that the Accord module provides lower steady-state thermal resistance as compared with the LEAF module. However, the LEAF design may provide improved performance in transient conditions and may have cost benefits.

Critical properties of the Kitaev-Heisenberg Model

Science.gov (United States)

Sizyuk, Yuriy; Price, Craig; Perkins, Natalia

2013-03-01

Collective behavior of local moments in Mott insulators in the presence of strong spin-orbit coupling is one of the most interesting questions in modern condensed matter physics. Here we study the finite temperature properties of the Kitaev-Heisenberg model which describe the interactions between the pseudospin J = 1 / 2 iridium moments on the honeycomb lattice. This model was suggested as a possible model to explain low-energy physics of AIr2O3 compounds. In our study we show that the Kitaev-Heisenberg model may be mapped into the six state clock model with an intermediate power-law phase at finite temperatures. In the framework of the Ginsburg-Landau theory, we provide an analysis of the critical properties of the finite-temperature ordering transitions. NSF grant DMR-1005932

On the capacity of multiaccess fading channels with full channel state information at low power regime

KAUST Repository

Rezki, Zouheir

2013-06-01

We study the throughput capacity region of the Gaussian multiaccess (MAC) fading channel with perfect channel state information (CSI) at the receiver (CSI-R) and at the transmitters (CSI-T), at low power regime. We show that it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum rate maximizer and that the coordinates of this point coincide with single user capacity bounds. Inspired from this result, we propose an on-off scheme, compute its achievable rate, and provide a necessary condition on the fading channels under which this scheme achieves single user capacity bounds of the MAC channel at asymptotically low power regime. We argue that this necessary condition characterizes a class of fading that encompasses all known wireless channels, where the capacity region of the MAC channel has a simple expression in terms of users\\' average power constraints only. © 2013 IEEE.

Analytic clock frequency selection for global DVFS

NARCIS (Netherlands)

Gerards, Marco Egbertus Theodorus; Hurink, Johann L.; Holzenspies, P.K.F.; Kuper, Jan; Smit, Gerardus Johannes Maria

2014-01-01

Computers can reduce their power consumption by decreasing their speed using Dynamic Voltage and Frequency Scaling (DVFS). A form of DVFS for multicore processors is global DVFS, where the voltage and clock frequency is shared among all processor cores. Because global DVFS is efficient and cheap to

Design and analysis of 30 nm T-gate InAlN/GaN HEMT with AlGaN back-barrier for high power microwave applications

Science.gov (United States)

Murugapandiyan, P.; Ravimaran, S.; William, J.; Meenakshi Sundaram, K.

2017-11-01

In this article, we present the DC and microwave characteristics of a novel 30 nm T-gate InAlN/AlN/GaN HEMT with AlGaN back-barrier. The device structure is simulated by using Synopsys Sentaurus TCAD Drift-Diffusion transport model at room temperature. The device features are heavily doped (n++ GaN) source/drain regions with Si3N4 passivated device surface for reducing the contact resistances and gate capacitances of the device, which uplift the microwave characteristics of the HEMTs. 30 nm gate length D-mode (E-mode) HEMT exhibited a peak drain current density Idmax of 2.3 (2.42) A/mm, transconductance gm of 1.24(1.65) S/mm, current gain cut-off frequency ft of 262 (246) GHz, power gain cut-off frequency fmax of 246(290) GHz and the three terminal off-state breakdown voltage VBR of 40(38) V. The preeminent microwave characteristics with the higher breakdown voltage of the proposed GaN-based HEMT are the expected to be the most optimistic applicant for future high power millimeter wave applications.

A GPS Satellite Clock Offset Prediction Method Based on Fitting Clock Offset Rates Data

Directory of Open Access Journals (Sweden)

WANG Fuhong

2016-12-01

Full Text Available It is proposed that a satellite atomic clock offset prediction method based on fitting and modeling clock offset rates data. This method builds quadratic model or linear model combined with periodic terms to fit the time series of clock offset rates, and computes the model coefficients of trend with the best estimation. The clock offset precisely estimated at the initial prediction epoch is directly adopted to calculate the model coefficient of constant. The clock offsets in the rapid ephemeris (IGR provided by IGS are used as modeling data sets to perform certain experiments for different types of GPS satellite clocks. The results show that the clock prediction accuracies of the proposed method for 3, 6, 12 and 24 h achieve 0.43, 0.58, 0.90 and 1.47 ns respectively, which outperform the traditional prediction method based on fitting original clock offsets by 69.3%, 61.8%, 50.5% and 37.2%. Compared with the IGU real-time clock products provided by IGS, the prediction accuracies of the new method have improved about 15.7%, 23.7%, 27.4% and 34.4% respectively.

Hysteresis behaviour of low-voltage organic field-effect transistors employing high dielectric constant polymer gate dielectrics

International Nuclear Information System (INIS)

Kim, Se Hyun; Yun, Won Min; Kwon, Oh-Kwan; Hong, Kipyo; Yang, Chanwoo; Park, Chan Eon; Choi, Woon-Seop

2010-01-01

Here, we report on the fabrication of low-voltage-operating pentacene-based organic field-effect transistors (OFETs) that utilize crosslinked cyanoethylated poly(vinyl alcohol) (CR-V) gate dielectrics. The crosslinked CR-V-based OFET could be operated successfully at low voltages (below 4 V), but abnormal behaviour during device operation, such as uncertainty in the field-effect mobility (μ) and hysteresis, was induced by the slow polarization of moieties embedded in the gate dielectric (e.g. polar functionalities, ionic impurities, water and solvent molecules). In an effort to improve the stability of OFET operation, we measured the dependence of μ and hysteresis on dielectric thickness, CR-V crosslinking conditions and sweep rate of the gate bias. The influence of the CR-V surface properties on μ, hysteresis, and the structural and morphological features of the pentacene layer grown on the gate dielectric was characterized and compared with the properties of pentacene grown on a polystyrene surface.

Six-Correction Logic (SCL Gates in Quantum-dot Cellular Automata (QCA

Directory of Open Access Journals (Sweden)

Md. Anisur Rahman

2015-11-01

Full Text Available Quantum Dot Cellular Automata (QCA is a promising nanotechnology in Quantum electronics for its ultra low power consumption, faster speed and small size features. It has significant advantages over the Complementary Metal–Oxide–Semiconductor (CMOS technology. This paper present, a novel QCA representation of Six-Correction Logic (SCL gate based on QCA logic gates: the Maj3, Maj AND gate and Maj OR. In order to design and verify the functionality of the proposed layout, QCADesigner a familiar QCA simulator has been employed. The simulation results confirm correctness of the claims and its usefulness in designing a digital circuits.

Analog storage integrated circuit

Science.gov (United States)

Walker, J.T.; Larsen, R.S.; Shapiro, S.L.

1989-03-07

A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.

Synthesizing genetic sequential logic circuit with clock pulse generator.

Science.gov (United States)

Chuang, Chia-Hua; Lin, Chun-Liang

2014-05-28

Rhythmic clock widely occurs in biological systems which controls several aspects of cell physiology. For the different cell types, it is supplied with various rhythmic frequencies. How to synthesize a specific clock signal is a preliminary but a necessary step to further development of a biological computer in the future. This paper presents a genetic sequential logic circuit with a clock pulse generator based on a synthesized genetic oscillator, which generates a consecutive clock signal whose frequency is an inverse integer multiple to that of the genetic oscillator. An analogous electronic waveform-shaping circuit is constructed by a series of genetic buffers to shape logic high/low levels of an oscillation input in a basic sinusoidal cycle and generate a pulse-width-modulated (PWM) output with various duty cycles. By controlling the threshold level of the genetic buffer, a genetic clock pulse signal with its frequency consistent to the genetic oscillator is synthesized. A synchronous genetic counter circuit based on the topology of the digital sequential logic circuit is triggered by the clock pulse to synthesize the clock signal with an inverse multiple frequency to the genetic oscillator. The function acts like a frequency divider in electronic circuits which plays a key role in the sequential logic circuit with specific operational frequency. A cascaded genetic logic circuit generating clock pulse signals is proposed. Based on analogous implement of digital sequential logic circuits, genetic sequential logic circuits can be constructed by the proposed approach to generate various clock signals from an oscillation signal.

Generating feasible transition paths for testing from an extended finite state machine (EFSM) with the counter problem

OpenAIRE

Kalaji, AS; Hierons, RM; Swift, S

2009-01-01

The extended finite state machine (EFSM) is a powerful approach for modeling state-based systems. However, testing from EFSMs is complicated by the existence of infeasible paths. One important problem is the existence of a transition with a guard that references a counter variable whose value depends on previous transitions. The presence of such transitions in paths often leads to infeasible paths. This paper proposes a novel approach to bypass the counter problem. The proposed approach is ev...

Active gated imaging for automotive safety applications

Science.gov (United States)

Grauer, Yoav; Sonn, Ezri

2015-03-01

The paper presents the Active Gated Imaging System (AGIS), in relation to the automotive field. AGIS is based on a fast gated-camera equipped with a unique Gated-CMOS sensor, and a pulsed Illuminator, synchronized in the time domain to record images of a certain range of interest which are then processed by computer vision real-time algorithms. In recent years we have learned the system parameters which are most beneficial to night-time driving in terms of; field of view, illumination profile, resolution and processing power. AGIS provides also day-time imaging with additional capabilities, which enhances computer vision safety applications. AGIS provides an excellent candidate for camera-based Advanced Driver Assistance Systems (ADAS) and the path for autonomous driving, in the future, based on its outstanding low/high light-level, harsh weather conditions capabilities and 3D potential growth capabilities.

Duo gating on a 3D topological insulator - independent tuning of both topological surface states

Science.gov (United States)

Li, Chuan; de Ronde, Bob; Snelder, Marieke; Stehno, Martin; Huang, Yingkai; Golden, Mark; Brinkman, Alexander; ICE Team; IOP Collaboration

ABSTRACT: Topological insulators are associated with a trove of exciting physics, such as the ability to host robust anyons, Majorana Bound States, which can be used for quantum computation. For future Majorana devices it is desirable to have the Fermi energy tuned as close as possible to the Dirac point of the topological surface state. Based on previous work on gating BSTS, we report the experimental progress towards gate-tuning of the top and bottom topological surface states of BiSbTeSe2 crystal flakes. When the Fermi level is moved across the Dirac point conduction is shown to change from electron dominated transport to hole dominated transport independently for either surface. In the high magnetic field, one can tune the system precisely between the different landau levels of both surfaces, thus a full gating map of the possible landau levels combination is established. In addition, we provide a simple capacitance model to explain the general hysteresis behaviors in topological insulator systems.

Evidence for widespread dysregulation of circadian clock progression in human cancer

Directory of Open Access Journals (Sweden)

Jarrod Shilts

2018-01-01

Full Text Available The ubiquitous daily rhythms in mammalian physiology are guided by progression of the circadian clock. In mice, systemic disruption of the clock can promote tumor growth. In vitro, multiple oncogenes can disrupt the clock. However, due to the difficulties of studying circadian rhythms in solid tissues in humans, whether the clock is disrupted within human tumors has remained unknown. We sought to determine the state of the circadian clock in human cancer using publicly available transcriptome data. We developed a method, called the clock correlation distance (CCD, to infer circadian clock progression in a group of samples based on the co-expression of 12 clock genes. Our method can be applied to modestly sized datasets in which samples are not labeled with time of day and coverage of the circadian cycle is incomplete. We used the method to define a signature of clock gene co-expression in healthy mouse organs, then validated the signature in healthy human tissues. By then comparing human tumor and non-tumor samples from twenty datasets of a range of cancer types, we discovered that clock gene co-expression in tumors is consistently perturbed. Subsequent analysis of data from clock gene knockouts in mice suggested that perturbed clock gene co-expression in human cancer is not caused solely by the inactivation of clock genes. Furthermore, focusing on lung cancer, we found that human lung tumors showed systematic changes in expression in a large set of genes previously inferred to be rhythmic in healthy lung. Our findings suggest that clock progression is dysregulated in many solid human cancers and that this dysregulation could have broad effects on circadian physiology within tumors. In addition, our approach opens the door to using publicly available data to infer circadian clock progression in a multitude of human phenotypes.

Low-power non-volatile spintronic memory: STT-RAM and beyond

International Nuclear Information System (INIS)

Wang, K L; Alzate, J G; Khalili Amiri, P

2013-01-01

The quest for novel low-dissipation devices is one of the most critical for the future of semiconductor technology and nano-systems. The development of a low-power, universal memory will enable a new paradigm of non-volatile computation. Here we consider STT-RAM as one of the emerging candidates for low-power non-volatile memory. We show different configurations for STT memory and demonstrate strategies to optimize key performance parameters such as switching current and energy. The energy and scaling limits of STT-RAM are discussed, leading us to argue that alternative writing mechanisms may be required to achieve ultralow power dissipation, a necessary condition for direct integration with CMOS at the gate level for non-volatile logic purposes. As an example, we discuss the use of the giant spin Hall effect as a possible alternative to induce magnetization reversal in magnetic tunnel junctions using pure spin currents. Further, we concentrate on magnetoelectric effects, where electric fields are used instead of spin-polarized currents to manipulate the nanomagnets, as another candidate solution to address the challenges of energy efficiency and density. The possibility of an electric-field-controlled magnetoelectric RAM as a promising candidate for ultralow-power non-volatile memory is discussed in the light of experimental data demonstrating voltage-induced switching of the magnetization and reorientation of the magnetic easy axis by electric fields in nanomagnets. (paper)

An Updated Perspective of Single Event Gate Rupture and Single Event Burnout in Power MOSFETs

Science.gov (United States)

Titus, Jeffrey L.

2013-06-01

Studies over the past 25 years have shown that heavy ions can trigger catastrophic failure modes in power MOSFETs [e.g., single-event gate rupture (SEGR) and single-event burnout (SEB)]. In 1996, two papers were published in a special issue of the IEEE Transaction on Nuclear Science [Johnson, Palau, Dachs, Galloway and Schrimpf, “A Review of the Techniques Used for Modeling Single-Event Effects in Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 546-560, April. 1996], [Titus and Wheatley, “Experimental Studies of Single-Event Gate Rupture and Burnout in Vertical Power MOSFETs,” IEEE Trans. Nucl. Sci., vol. 43, no. 2, pp. 533-545, Apr. 1996]. Those two papers continue to provide excellent information and references with regard to SEB and SEGR in vertical planar MOSFETs. This paper provides updated references/information and provides an updated perspective of SEB and SEGR in vertical planar MOSFETs as well as provides references/information to other device types that exhibit SEB and SEGR effects.

Gate-controlled switching between persistent and inverse persistent spin helix states

International Nuclear Information System (INIS)

Yoshizumi, K.; Sasaki, A.; Kohda, M.; Nitta, J.

2016-01-01

We demonstrate gate-controlled switching between persistent spin helix (PSH) state and inverse PSH state, which are detected by quantum interference effect on magneto-conductance. These special symmetric spin states showing weak localization effect give rise to a long spin coherence when the strength of Rashba spin-orbit interaction (SOI) is close to that of Dresselhaus SOI. Furthermore, in the middle of two persistent spin helix states, where the Rashba SOI can be negligible, the bulk Dresselhaus SOI parameter in a modulation doped InGaAs/InAlAs quantum well is determined.

Gate-controlled switching between persistent and inverse persistent spin helix states

Energy Technology Data Exchange (ETDEWEB)

Yoshizumi, K.; Sasaki, A.; Kohda, M.; Nitta, J. [Department of Materials Science, Tohoku University, Sendai 980-8579 (Japan)

2016-03-28

We demonstrate gate-controlled switching between persistent spin helix (PSH) state and inverse PSH state, which are detected by quantum interference effect on magneto-conductance. These special symmetric spin states showing weak localization effect give rise to a long spin coherence when the strength of Rashba spin-orbit interaction (SOI) is close to that of Dresselhaus SOI. Furthermore, in the middle of two persistent spin helix states, where the Rashba SOI can be negligible, the bulk Dresselhaus SOI parameter in a modulation doped InGaAs/InAlAs quantum well is determined.

Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

Science.gov (United States)

Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

2016-11-01

In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

A Pseudo Fractional-N Clock Generator with 50% Duty Cycle Output

Science.gov (United States)

Yang, Wei-Bin; Lo, Yu-Lung; Chao, Ting-Sheng

A proposed pseudo fractional-N clock generator with 50% duty cycle output is presented by using the pseudo fractional-N controller for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated with the particular phase combinations of a four-stage voltage-controlled oscillator (VCO). It has been fabricated in a 0.13µm CMOS technology, and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed pseudo fractional-N clock generator is from 71.4MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rates of the output clock frequencies are from 0.8% to 2% and the measured power dissipation of the pseudo fractional-N controller is 146µW at 304MHz.

Phase noise analysis of clock recovery based on an optoelectronic phase-locked loop

DEFF Research Database (Denmark)

Zibar, Darko; Mørk, Jesper; Oxenløwe, Leif Katsuo

2007-01-01

A detailed theoretical analysis of a clock-recovery (CR) scheme based on an optoelectronic phase-locked loop is presented. The analysis emphasizes the phase noise performance, taking into account the noise of the input data signal, the local voltage-controlled oscillator (VCO), and the laser....... It is shown that a large loop length results in a higher timing jitter of the recovered clock signal. The impact of the loop length on the clock signal jitter can be reduced by using a low-noise VCO and a low loop filter bandwidth. Using the model, the timing jitter of the recovered optical and electrical...... clock signal can be evaluated. We numerically investigate the timing jitter requirements for combined electrical/optical local oscillators, in order for the recovered clock signal to have less jitter than that of the input signal. The timing jitter requirements for the free-running laser and the VCO...

A study on low-power, nanosecond operation and multilevel bipolar resistance switching in Ti/ZrO2/Pt nonvolatile memory with 1T1R architecture

International Nuclear Information System (INIS)

Wu, Ming-Chi; Tseng, Tseung-Yuen; Jang, Wen-Yueh; Lin, Chen-Hsi

2012-01-01

Low-power, bipolar resistive switching (RS) characteristics in the Ti/ZrO 2 /Pt nonvolatile memory with one transistor and one resistor (1T1R) architecture were reported. Multilevel storage behavior was observed by modulating the amplitude of the MOSFET gate voltage, in which the transistor functions as a current limiter. Furthermore, multilevel storage was also executed by controlling the reset voltage, leading the resistive random access memory (RRAM) to the multiple metastable low resistance state (LRS). The experimental results on the measured electrical properties of the various sized devices confirm that the RS mechanism of the Ti/ZrO 2 /Pt structure obeys the conducting filaments model. In application, the devices exhibit high-speed switching performances (250 ns) with suitable high/low resistance state ratio (HRS/LRS > 10). The LRS of the devices with 10 year retention ability at 80 °C, based on the Arrhenius equation, is also demonstrated in the thermal accelerating test. Furthermore, the ramping gate voltage method with fixed drain voltage is used to switch the 1T1R memory cells for upgrading the memory performances. Our experimental results suggest that the ZrO 2 -based RRAM is a prospective alternative for nonvolatile multilevel memory device applications. (paper)

Complete permutation Gray code implemented by finite state machine

Directory of Open Access Journals (Sweden)

Li Peng

2014-09-01

Full Text Available An enumerating method of complete permutation array is proposed. The list of n! permutations based on Gray code defined over finite symbol set Z(n = {1, 2, …, n} is implemented by finite state machine, named as n-RPGCF. An RPGCF can be used to search permutation code and provide improved lower bounds on the maximum cardinality of a permutation code in some cases.

Expanding Access and Opportunity: The Impact of the Gates Millennium Scholars Program

Science.gov (United States)

Ramsey, Jennifer

2010-01-01

In 1999, the Bill & Melinda Gates Foundation began an innovative scholarship program that provides full financial support to low-income minority students across the United States. The Gates Millennium Scholars (GMS) program has already awarded more than 10,000 scholarships to exceptional students, with the ultimate goal of funding at least…

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

Science.gov (United States)

Singh, Kunwar; Tiwari, Satish Chandra; Gupta, Maneesha

2014-01-01

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

Sub-50 nm gate length SOI transistor development for high performance microprocessors

International Nuclear Information System (INIS)

Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

2004-01-01

Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

Association between circadian clock genes and diapause incidence in Drosophila triauraria.

Directory of Open Access Journals (Sweden)

Hirokazu Yamada

Full Text Available Diapause is an adaptive response triggered by seasonal photoperiodicity to overcome unfavorable seasons. The photoperiodic clock is a system that controls seasonal physiological processes, but our knowledge about its physiological mechanisms and genetic architecture remains incomplete. The circadian clock is another system that controls daily rhythmic physiological phenomena. It has been argued that there is a connection between the two clocks. To examine the genetic connection between them, we analyzed the associations of five circadian clock genes (period, timeless, Clock, cycle and cryptochrome with the occurrence of diapause in Drosophila triauraria, which shows a robust reproductive diapause with clear photoperiodicity. Non-diapause strains found in low latitudes were compared in genetic crosses with the diapause strain, in which the diapause trait is clearly dominant. Single nucleotide polymorphism and deletion analyses of the five circadian clock genes in backcross progeny revealed that allelic differences in timeless and cryptochrome between the strains were additively associated with the differences in the incidence of diapause. This suggests that there is a molecular link between certain circadian clock genes and the occurrence of diapause.

Gate-voltage control of equal-spin Andreev reflection in half-metal/semiconductor/superconductor junctions

Energy Technology Data Exchange (ETDEWEB)

Wu, Xiuqiang, E-mail: xianqiangzhe@126.com [National Laboratory of Solid State Microstructures and Department of Physics, Nanjing University, Nanjing 210093 (China); Meng, Hao, E-mail: menghao1982@shu.edu.cn [School of Physics and Telecommunication Engineering, Shanxi University of Technology, Hanzhong 723001 (China)

2016-04-22

With the Blonder–Tinkham–Klapwijk (BTK) approach, we investigate conductance spectrum in Ferromagnet/Semiconductor/Superconductor (FM/Sm/SC) double tunnel junctions where strong Rashba spin–orbit interaction (RSOI) is taken into account in semiconductors. For the half-metal limit, we find that the in-gap conductance becomes finite except at zero voltage when inserting a ferromagnetic insulator (FI) at the Sm/SC interface, which means that the appearance of a long-range triplet states in the half-metal. This is because of the emergence of the unconventional equal-spin Andreev reflection (ESAR). When the FI locates at the FM/Sm interface, however, we find the vanishing in-gap conductance due to the absence of the ESAR. Moreover, the non-zero in-gap conductance shows a nonmonotonic dependence on RSOI which can be controlled by applying an external gate voltage. Our results can be used to generate and manipulate the long-range spin triplet correlation in the nascent field of superconducting spintronics. - Highlights: • We study the equal-spin Andreev reflection in half-metal/semiconductor/superconductor (HM/Sm/SC) junctions. • The equal-spin Andreev reflection appearance when inserting a ferromagnetic insulator at the Sm/SC interface. • The finite in-gap conductance is attributed to the emergence of the equal-spin Andreev reflection. • The finite in-gap conductance shows a nonmonotonic dependence on Rashba spin–orbit interaction. • The finite in-gap conductance can be controlled by applying an external gate voltage.

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

Science.gov (United States)

Cheng, Xin; Zhang, Yu; Xie, Guangjun; Yang, Yizhong; Zhang, Zhang

2018-03-01

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE) circuit is introduced. The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly. In addition, a buffer with ultra-low output impedance is presented to improve line and load regulations. This design is fabricated by SMIC 0.18 μm CMOS technology. Experimental results show that, the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA. The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV. Moreover, the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively. Project supported by the National Natural Science Foundation of China (Nos. 61401137, 61404043, 61674049).

Simple-design ultra-low phase noise microwave frequency synthesizers for high-performing Cs and Rb vapor-cell atomic clocks

Energy Technology Data Exchange (ETDEWEB)

François, B. [FEMTO-ST, CNRS, Université de Franche-Comté, 26 chemin de l’Epitaphe, 25030 Besançon (France); INRIM, Strada delle Cacce 91, 10135 Torino (Italy); Calosso, C. E.; Micalizio, S. [INRIM, Strada delle Cacce 91, 10135 Torino (Italy); Abdel Hafiz, M.; Boudot, R. [FEMTO-ST, CNRS, Université de Franche-Comté, 26 chemin de l’Epitaphe, 25030 Besançon (France)

2015-09-15

We report on the development and characterization of novel 4.596 GHz and 6.834 GHz microwave frequency synthesizers devoted to be used as local oscillators in high-performance Cs and Rb vapor-cell atomic clocks. The key element of the synthesizers is a custom module that integrates a high spectral purity 100 MHz oven controlled quartz crystal oscillator frequency-multiplied to 1.6 GHz with minor excess noise. Frequency multiplication, division, and mixing stages are then implemented to generate the exact output atomic resonance frequencies. Absolute phase noise performances of the output 4.596 GHz signal are measured to be −109 and −141 dB rad{sup 2}/Hz at 100 Hz and 10 kHz Fourier frequencies, respectively. The phase noise of the 6.834 GHz signal is −105 and −138 dB rad{sup 2}/Hz at 100 Hz and 10 kHz offset frequencies, respectively. The performances of the synthesis chains contribute to the atomic clock short term fractional frequency stability at a level of 3.1 × 10{sup −14} for the Cs cell clock and 2 × 10{sup −14} for the Rb clock at 1 s averaging time. This value is comparable with the clock shot noise limit. We describe the residual phase noise measurements of key components and stages to identify the main limitations of the synthesis chains. The residual frequency stability of synthesis chains is measured to be at the 10{sup −15} level for 1 s integration time. Relevant advantages of the synthesis design, using only commercially available components, are to combine excellent phase noise performances, simple-architecture, low-cost, and to be easily customized for signal output generation at 4.596 GHz or 6.834 GHz for applications to Cs or Rb vapor-cell frequency standards.

Confined States and Tunnelling in Gated Graphene Nanoribbons

Science.gov (United States)

Guilleminot, E.,; Meza-Montes, L.

Graphene Quantum Dots (GQDs) are promising candidates for the development of quantum information processors. We propose a scheme to determine electronic states of GQDs as defined by voltage gates applied to armchair graphene nanoribbons. Using transfer matrix method based on the set of solutions proposed by Burkard et al ., we study confined states of double wells and the transmission of electrons through double barrier systems. Comparison with previous results for systems on the graphene sheet shows good agreement. Confined states of a double well turn out to be very sensitive to deformation of the potential profile, showing strong localization of the electron for asymmetric systems, which also depends on the considered state. Spikes of high transmission appeared for periodic values of the incident angle of the electron travelling through a double barrier and disappear as the systems approaches to a single barrier as one barrier vanishes. We remark effects not shown in usual semiconductor heterostructures. Partially supported by VIEP-BUAP, Mexico,.

Differential maturation of rhythmic clock gene expression during early development in medaka (Oryzias latipes).

Science.gov (United States)

Cuesta, Ines H; Lahiri, Kajori; Lopez-Olmeda, Jose Fernando; Loosli, Felix; Foulkes, Nicholas S; Vallone, Daniela

2014-05-01

One key challenge for the field of chronobiology is to identify how circadian clock function emerges during early embryonic development. Teleosts such as the zebrafish are ideal models for studying circadian clock ontogeny since the entire process of development occurs ex utero in an optically transparent chorion. Medaka (Oryzias latipes) represents another powerful fish model for exploring early clock function with, like the zebrafish, many tools available for detailed genetic analysis. However, to date there have been no reports documenting circadian clock gene expression during medaka development. Here we have characterized the expression of key clock genes in various developmental stages and in adult tissues of medaka. As previously reported for other fish, light dark cycles are required for the emergence of clock gene expression rhythms in this species. While rhythmic expression of per and cry genes is detected very early during development and seems to be light driven, rhythmic clock and bmal expression appears much later around hatching time. Furthermore, the maturation of clock function seems to correlate with the appearance of rhythmic expression of these positive elements of the clock feedback loop. By accelerating development through elevated temperatures or by artificially removing the chorion, we show an earlier onset of rhythmicity in clock and bmal expression. Thus, differential maturation of key elements of the medaka clock mechanism depends on the developmental stage and the presence of the chorion.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Science.gov (United States)

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-09-26

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

Valuing modular nuclear power plants in finite time decision horizon

International Nuclear Information System (INIS)

Jain, Shashi; Roelofs, Ferry; Oosterlee, Cornelis W.