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Sample records for low-power embedded processors

  1. Very wide register : an asymmetric register file organization for low power embedded processors.

    NARCIS (Netherlands)

    Raghavan, P.; Lambrechts, A.; Jayapala, M.; Catthoor, F.; Verkest, D.T.M.L.; Corporaal, H.

    2007-01-01

    In current embedded systems processors, multi-ported register files are one of the most power hungry parts of the processor, even when they are clustered. This paper presents a novel register file architecture, which has single ported cells and asymmetric interfaces to the memory and to the

  2. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  3. Fast decision algorithms in low-power embedded processors for quality-of-service based connectivity of mobile sensors in heterogeneous wireless sensor networks.

    Science.gov (United States)

    Jaraíz-Simón, María D; Gómez-Pulido, Juan A; Vega-Rodríguez, Miguel A; Sánchez-Pérez, Juan M

    2012-01-01

    When a mobile wireless sensor is moving along heterogeneous wireless sensor networks, it can be under the coverage of more than one network many times. In these situations, the Vertical Handoff process can happen, where the mobile sensor decides to change its connection from a network to the best network among the available ones according to their quality of service characteristics. A fitness function is used for the handoff decision, being desirable to minimize it. This is an optimization problem which consists of the adjustment of a set of weights for the quality of service. Solving this problem efficiently is relevant to heterogeneous wireless sensor networks in many advanced applications. Numerous works can be found in the literature dealing with the vertical handoff decision, although they all suffer from the same shortfall: a non-comparable efficiency. Therefore, the aim of this work is twofold: first, to develop a fast decision algorithm that explores the entire space of possible combinations of weights, searching that one that minimizes the fitness function; and second, to design and implement a system on chip architecture based on reconfigurable hardware and embedded processors to achieve several goals necessary for competitive mobile terminals: good performance, low power consumption, low economic cost, and small area integration.

  4. A low power biomedical signal processor ASIC based on hardware software codesign.

    Science.gov (United States)

    Nie, Z D; Wang, L; Chen, W G; Zhang, T; Zhang, Y T

    2009-01-01

    A low power biomedical digital signal processor ASIC based on hardware and software codesign methodology was presented in this paper. The codesign methodology was used to achieve higher system performance and design flexibility. The hardware implementation included a low power 32bit RISC CPU ARM7TDMI, a low power AHB-compatible bus, and a scalable digital co-processor that was optimized for low power Fast Fourier Transform (FFT) calculations. The co-processor could be scaled for 8-point, 16-point and 32-point FFTs, taking approximate 50, 100 and 150 clock circles, respectively. The complete design was intensively simulated using ARM DSM model and was emulated by ARM Versatile platform, before conducted to silicon. The multi-million-gate ASIC was fabricated using SMIC 0.18 microm mixed-signal CMOS 1P6M technology. The die area measures 5,000 microm x 2,350 microm. The power consumption was approximately 3.6 mW at 1.8 V power supply and 1 MHz clock rate. The power consumption for FFT calculations was less than 1.5 % comparing with the conventional embedded software-based solution.

  5. Promise of a low power mobile CPU based embedded system in artificial leg control.

    Science.gov (United States)

    Hernandez, Robert; Zhang, Fan; Zhang, Xiaorong; Huang, He; Yang, Qing

    2012-01-01

    This paper presents the design and implementation of a low power embedded system using mobile processor technology (Intel Atom™ Z530 Processor) specifically tailored for a neural-machine interface (NMI) for artificial limbs. This embedded system effectively performs our previously developed NMI algorithm based on neuromuscular-mechanical fusion and phase-dependent pattern classification. The analysis shows that NMI embedded system can meet real-time constraints with high accuracies for recognizing the user's locomotion mode. Our implementation utilizes the mobile processor efficiently to allow a power consumption of 2.2 watts and low CPU utilization (less than 4.3%) while executing the complex NMI algorithm. Our experiments have shown that the highly optimized C program implementation on the embedded system has superb advantages over existing PC implementations on MATLAB. The study results suggest that mobile-CPU-based embedded system is promising for implementing advanced control for powered lower limb prostheses.

  6. Low-Power Embedded DSP Core for Communication Systems

    Science.gov (United States)

    Tsao, Ya-Lan; Chen, Wei-Hao; Tan, Ming Hsuan; Lin, Maw-Ching; Jou, Shyh-Jye

    2003-12-01

    This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35[InlineEquation not available: see fulltext.]m SPQM and 0.25[InlineEquation not available: see fulltext.]m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a[InlineEquation not available: see fulltext.] version is 100 MHz (0.35[InlineEquation not available: see fulltext.]m) and 140 MHz (0.25[InlineEquation not available: see fulltext.]m).

  7. Low-power analogue processor for Bonner sphere spectrometers

    International Nuclear Information System (INIS)

    Ciobanu, M.I.; Alevra, A.V.

    1998-01-01

    The electronic system proposed is compact, small-size (the dimensions of the prototype are 107 x 105 x 58 mm) and battery-powered. The whole detection system is portable and independent of the mains supply and is well shielded against external disturbances. Technical details of the analog processor are given. (M.D.)

  8. Embedded processor extensions for image processing

    Science.gov (United States)

    Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

    2008-04-01

    The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

  9. Low-Latency Embedded Vision Processor (LLEVS)

    Science.gov (United States)

    2016-03-01

    algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system

  10. Design of an ultra-low-power digital processor for passive UHF RFID tags

    Energy Technology Data Exchange (ETDEWEB)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan, E-mail: wanggen_shi@163.co [Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

    2009-04-15

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 mum process of Chartered Semiconductor.

  11. Design of an ultra-low-power digital processor for passive UHF RFID tags

    International Nuclear Information System (INIS)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan

    2009-01-01

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.

  12. Code compression for VLIW embedded processors

    Science.gov (United States)

    Piccinelli, Emiliano; Sannino, Roberto

    2004-04-01

    The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

  13. Composable processor virtualization for embedded systems

    NARCIS (Netherlands)

    Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

    2010-01-01

    Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

  14. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  15. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    Science.gov (United States)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STAR- Dundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITAR- free and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  16. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  17. Huffman-based code compression techniques for embedded processors

    KAUST Repository

    Bonny, Mohamed Talal; Henkel, Jö rg

    2010-01-01

    % for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.

  18. Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems

    Directory of Open Access Journals (Sweden)

    Jennifer Hasler

    2018-06-01

    Full Text Available We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns. This paper begins the discussion of security opportunities for, and issues using, FPAA devices for small embedded IoT platforms. These FPAAs enable devices often utilized for low-power context aware computation. Embedded FPAA devices have both positive Security attributes, as well as potential vulnerabilities. FPAA devices can be part of the resulting secure computation, such as implementing unique functions. FPAA devices can be used investigate security of analog/mixed signal capabilities. The paper concludes with summarizing key improvements for secure ultra-low power embedded FPAA devices.

  19. Parallel embedded systems: where real-time and low-power meet

    DEFF Research Database (Denmark)

    Karakehayov, Zdravko; Guo, Yu

    2008-01-01

    This paper introduces a combination of models and proofs for optimal power management via Dynamic Frequency Scaling and Dynamic Voltage Scaling. The approach is suitable for systems on a chip or microcontrollers where processors run in parallel with embedded peripherals. We have developed...... a software tool, called CASTLE, to provide computer assistance in the design process of energy-aware embedded systems. The tool considers single processor and parallel architectures. An example shows an energy reduction of 23% when the tool allocates two microcontrollers for parallel execution....

  20. FASTBUS Standard Routines implementation for Fermilab embedded processor boards

    International Nuclear Information System (INIS)

    Pangburn, J.; Patrick, J.; Kent, S.; Oleynik, G.; Pordes, R.; Votava, M.; Heyes, G.; Watson, W.A. III

    1992-10-01

    In collaboration with CEBAF, Fermilab's Online Support Department and the CDF experiment have produced a new implementation of the IEEE FASTBUS Standard Routines for two embedded processor FASTBUS boards: the Fermilab Smart Crate Controller (FSCC) and the FASTBUS Readout Controller (FRC). Features of this implementation include: portability (to other embedded processor boards), remote source-level debugging, high speed, optional generation of very high-speed code for readout applications, and built-in Sun RPC support for execution of FASTBUS transactions and lists over the network

  1. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito

    2011-01-01

    Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper, establi......Multi-core processors are about to conquer embedded systems — it is not the question of whether they are coming but how the architectures of the microcontrollers should look with respect to the strict requirements in the field. We present the step from one to multiple cores in this paper...

  2. Low-Power Built-In Self-Test Techniques for Embedded SRAMs

    Directory of Open Access Journals (Sweden)

    Shyue-Kung Lu

    2007-01-01

    Full Text Available The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

  3. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Directory of Open Access Journals (Sweden)

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  4. Experience with low-power x86 processors (Atom) for HEP usage. An initial analysis of the Intel® dual core Atom™ N330 processor

    CERN Document Server

    Balazs, G; Nowak, A; CERN. Geneva. IT Department

    2009-01-01

    In this paper we compare a system based on an Intel Atom N330 low-power processor to a modern Intel Xeon® dual-socket server using CERN IT’s standard criteria for comparing price-performance and performance per watt. The Xeon server corresponds to what is typically acquired as servers in the LHC Computing Grid. The comparisons used public pricing information from November 2008. After the introduction in section 1, section 2 describes the hardware and software setup. In section 3 we describe the power measurements we did and in section 4 we discuss the throughput performance results. In section 5 we summarize our initial conclusions. We then go on to describe our long term vision and possible future scenarios for using such low-power processors, and finally we list interesting development directions.

  5. A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

    Directory of Open Access Journals (Sweden)

    Jian (Denny Lin

    2014-05-01

    Full Text Available With the advanced technology used to design VLSI (Very Large Scale Integration circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

  6. ARM Processor Based Embedded System for Remote Data Acquisition

    OpenAIRE

    Raj Kumar Tiwari; Santosh Kumar Agrahari

    2014-01-01

    The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

  7. Multi-Threaded Dense Linear Algebra Libraries for Low-Power Asymmetric Multicore Processors

    OpenAIRE

    Catalán, Sandra; Herrero, José R.; Igual, Francisco D.; Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

    2015-01-01

    Dense linear algebra libraries, such as BLAS and LAPACK, provide a relevant collection of numerical tools for many scientific and engineering applications. While there exist high performance implementations of the BLAS (and LAPACK) functionality for many current multi-threaded architectures,the adaption of these libraries for asymmetric multicore processors (AMPs)is still pending. In this paper we address this challenge by developing an asymmetry-aware implementation of the BLAS, based on the...

  8. A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors

    OpenAIRE

    Hwan Su Jung; Ahn Jun Gil; Jong Tae Kim

    2017-01-01

    Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 ...

  9. An Embedded Sensor Node Microcontroller with Crypto-Processors.

    Science.gov (United States)

    Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

    2016-04-27

    Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed.

  10. Huffman-based code compression techniques for embedded processors

    KAUST Repository

    Bonny, Mohamed Talal

    2010-09-01

    The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures

  11. A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

    International Nuclear Information System (INIS)

    Zhang Junyu; Wang Yong; Liu Jing; Zhang Manhong; Xu Zhongguang; Huo Zongliang; Liu Ming

    2012-01-01

    We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the 'erased states' can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications. (semiconductor devices)

  12. Review of battery powered embedded systems design for mission-critical low-power applications

    Science.gov (United States)

    Malewski, Matthew; Cowell, David M. J.; Freear, Steven

    2018-06-01

    The applications and uses of embedded systems is increasingly pervasive. Mission and safety critical systems relying on embedded systems pose specific challenges. Embedded systems is a multi-disciplinary domain, involving both hardware and software. Systems need to be designed in a holistic manner so that they are able to provide the desired reliability and minimise unnecessary complexity. The large problem landscape means that there is no one solution that fits all applications of embedded systems. With the primary focus of these mission and safety critical systems being functionality and reliability, there can be conflicts with business needs, and this can introduce pressures to reduce cost at the expense of reliability and functionality. This paper examines the challenges faced by battery powered systems, and then explores at more general problems, and several real-world embedded systems.

  13. Development of Ultra-Low Power Metal Oxide Sensors and Arrays for Embedded Applications

    Science.gov (United States)

    Lutz, Brent; Wind, Rikard; Kostelecky, Clayton; Routkevitch, Dmitri; Deininger, Debra

    2011-09-01

    Metal oxide semiconductor sensors are widely used as individual sensors and in arrays, and a variety of designs for low power microhotplates have been demonstrated.1 Synkera Technologies has developed an embeddable chemical microsensor platform, based on a unique ceramic MEMS technology, for practical implementation in cell phones and other mobile electronic devices. Key features of this microsensor platform are (1) small size, (2) ultra-low power consumption, (3) high chemical sensitivity, (4) accurate response to a wide-range of threats, and (5) low cost. The sensor platform is enabled by a combination of advances in ceramic micromachining, and precision deposition of sensing films inside the high aspect ratio pores of anodic aluminum oxide (AAO).

  14. Ultra-Low Power Optical Transistor Using a Single Quantum Dot Embedded in a Photonic Wire

    DEFF Research Database (Denmark)

    Nguyen, H.A.; Grange, T.; Malik, N.S.

    2017-01-01

    Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons.......Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons....

  15. Embedded SoPC Design with Nios II Processor and Verilog Examples

    CERN Document Server

    Chu, Pong P

    2012-01-01

    Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

  16. Pixel detector bias supply and control using embedded multicore processors

    CERN Document Server

    AUTHOR|(CDS)2099144; Akram Alomainy

    The aim of the project is to create a software controlled, open source, low footprint and low power high voltage bias supply and current monitor for a pixelated radiation sensor. The solution is based on the LT3905 integrated circuit and the multi-core XMOS xCore 200 microcontroller and it is intended to be used in a battery powered, mobile platform for educational settings.

  17. Design of Low Power Algorithms for Automatic Embedded Analysis of Patch ECG Signals

    DEFF Research Database (Denmark)

    Saadi, Dorthe Bodholt

    , several different cable-free wireless patch-type ECG recorders have recently reached the market. One of these recorders is the ePatch designed by the Danish company DELTA. The extended monitoring period available with the patch recorders has demonstrated to increase the diagnostic yield of outpatient ECG....... Such algorithms could allow the real-time transmission of clinically relevant information to a central monitoring station. The first step in embedded ECG interpretation is the automatic detection of each individual heartbeat. An important part of this project was therefore to design a novel algorithm...

  18. Design concepts for a virtualizable embedded MPSoC architecture enabling virtualization in embedded multi-processor systems

    CERN Document Server

    Biedermann, Alexander

    2014-01-01

    Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concepts for the design of energy aware systems, self-healing systems as well as parallelized systems. For the latter, the novel so-called Agile Processing scheme is introduced by the author, which enables a seamless transition between sequential and parallel execution schemes. The design of such virtualizable systems is further aided by introduction

  19. Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems

    Science.gov (United States)

    Zhao, Huatao; Luo, Xiao; Zhu, Chen; Watanabe, Takahiro; Zhu, Tianbo

    2017-07-01

    In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache resource demands as the cache allocation bases, so that we can optimally configure the cache hierarchy to meet the runtime demand. The BACH was implemented on the GEM5 simulator. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead.

  20. Design of massively parallel hardware multi-processors for highly-demanding embedded applications

    NARCIS (Netherlands)

    Jozwiak, L.; Jan, Y.

    2013-01-01

    Many new embedded applications require complex computations to be performed to tight schedules, while at the same time demanding low energy consumption and low cost. For implementation of these highly-demanding applications, highly-optimized application-specific multi-processor system-on-a-chip

  1. Safe and Efficient Support for Embeded Multi-Processors in ADA

    Science.gov (United States)

    Ruiz, Jose F.

    2010-08-01

    New software demands increasing processing power, and multi-processor platforms are spreading as the answer to achieve the required performance. Embedded real-time systems are also subject to this trend, but in the case of real-time mission-critical systems, the properties of reliability, predictability and analyzability are also paramount. The Ada 2005 language defined a subset of its tasking model, the Ravenscar profile, that provides the basis for the implementation of deterministic and time analyzable applications on top of a streamlined run-time system. This Ravenscar tasking profile, originally designed for single processors, has proven remarkably useful for modelling verifiable real-time single-processor systems. This paper proposes a simple extension to the Ravenscar profile to support multi-processor systems using a fully partitioned approach. The implementation of this scheme is simple, and it can be used to develop applications amenable to schedulability analysis.

  2. Natrium: Use of FPGA embedded processors for real-time data compression

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

    2011-12-15

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  3. Natrium: Use of FPGA embedded processors for real-time data compression

    International Nuclear Information System (INIS)

    Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

    2011-01-01

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  4. An enhanced Ada run-time system for real-time embedded processors

    Science.gov (United States)

    Sims, J. T.

    1991-01-01

    An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

  5. Reward-based learning under hardware constraints - Using a RISC processor embedded in a neuromorphic substrate

    Directory of Open Access Journals (Sweden)

    Simon eFriedmann

    2013-09-01

    Full Text Available In this study, we propose and analyze in simulations a new, highly flexible method of imple-menting synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. Thestudy focuses on globally modulated STDP, as a special use-case of this method. Flexibility isachieved by embedding a general-purpose processor dedicated to plasticity into the wafer. Toevaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spiketrain learning task. A single layer of neurons is trained to fire at specific points in time withonly the reward as feedback. This model is simulated to measure its performance, i.e. the in-crease in received reward after learning. Using this performance as baseline, we then simulatethe model with various constraints imposed by the proposed implementation and compare theperformance. The simulated constraints include discretized synaptic weights, a restricted inter-face between analog synapses and embedded processor, and mismatch of analog circuits. Wefind that probabilistic updates can increase the performance of low-resolution weights, a simpleinterface between analog synapses and processor is sufficient for learning, and performance isinsensitive to mismatch. Further, we consider communication latency between wafer and theconventional control computer system that is simulating the environment. This latency increasesthe delay, with which the reward is sent to the embedded processor. Because of the time continu-ous operation of the analog synapses, delay can cause a deviation of the updates as compared tothe not delayed situation. We find that for highly accelerated systems latency has to be kept to aminimum. This study demonstrates the suitability of the proposed implementation to emulatethe selected reward modulated STDP learning rule. It is therefore an ideal candidate for imple-mentation in an upgraded version of the wafer-scale system developed within the BrainScaleSproject.

  6. Quality-Driven Model-Based Design of MultiProcessor Embedded Systems for Highlydemanding Applications

    DEFF Research Database (Denmark)

    Jozwiak, Lech; Madsen, Jan

    2013-01-01

    The recent spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a complete complex multi-processor system on a single chip (MPSoC), global networking and mobile wire-less communication, and facilitated a fast progress in these areas. New important...... accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern embedded application impose very stringent functional and parametric demands. Moreover, the spectacular advances in microelectronics introduced...

  7. Development of a processor embedded timing unit for the synchronized operation in KSTAR

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Woongryol, E-mail: wrlee@nfri.re.kr; Lee, Taegu; Hong, Jaesic

    2016-11-15

    Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

  8. Development of a processor embedded timing unit for the synchronized operation in KSTAR

    International Nuclear Information System (INIS)

    Lee, Woongryol; Lee, Taegu; Hong, Jaesic

    2016-01-01

    Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

  9. Compilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor

    Directory of Open Access Journals (Sweden)

    Masa-aki FUKASE

    2007-12-01

    Full Text Available The development of single chip VLSI processors is the key technology of ever growing pervasive computing to answer overall demands for usability, mobility, speed, security, etc. We have so far developed a hardware cryptography-embedded multimedia mobile processor architecture, HCgorilla. Since HCgorilla integrates a wide range of techniques from architectures to applications and languages, one-sided design approach is not always useful. HCgorilla needs more complicated strategy, that is, hardware/software (H/S codesign. Thus, we exploit the software support of HCgorilla composed of a Java interface and parallelizing compilers. They are assumed to be installed in servers in order to reduce the load and increase the performance of HCgorilla-embedded clients. Since compilers are the essence of software's responsibility, we focus in this article on our recent results about the design, specifications, and prototyping of parallelizing compilers for HCgorilla. The parallelizing compilers are composed of a multicore compiler and a LIW compiler. They are specified to abstract parallelism from executable serial codes or the Java interface output and output the codes executable in parallel by HCgorilla. The prototyping compilers are written in Java. The evaluation by using an arithmetic test program shows the reasonability of the prototyping compilers compared with hand compilers.

  10. MatLab script to C code converter for embedded processors of FLASH LLRF control system

    Science.gov (United States)

    Bujnowski, K.; Siemionczyk, A.; Pucyk, P.; Szewiński, J.; Pożniak, K. T.; Romaniuk, R. S.

    2008-01-01

    The low level RF control system (LLRF) of FEL serves for stabilization of the electromagnetic (EM) field in the superconducting niobium, resonant, microwave cavities and for controlling high power (MW) klystron. LLRF system of FLASH accelerator bases on FPGA technology and embedded microprocessors. Basic and auxiliary functions of the systems are listed as well as used algorithms for superconductive cavity parameters identification. These algorithms were prepared originally in Matlab. The main part of the paper presents implementation of the cavity parameters identification algorithm in a PowerPC processor embedded in the FPGA circuit VirtexIIPro. A construction of a very compact Matlab script converter to C code was presented, referred to as M2C. The application is designed specifically for embedded systems of very confined resources. The generated code is optimized for the weight. The code should be transferable between different hardware platforms. The converter generates a code for Linux and for stand-alone applications. Functional structure of the program was described and the way it is acting. FLEX and BIZON tools were used for construction of the converter. The paper concludes with an example of the M2C application to convert a complex identification algorithm for superconductive cavities in FLASH laser.

  11. A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

    Science.gov (United States)

    Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

    2016-04-01

    A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

  12. Open-source implementation of an ad-hoc IEEE802.11a/g/p software-defined radio on low-power and low-cost general purpose processors

    Directory of Open Access Journals (Sweden)

    S. Ciccia

    2017-12-01

    Full Text Available This work proposes a low-cost and low-power software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. A state-of-the-art version of the IEEE 802.11 a/g/p software for GNU Radio (a free and open-source software development framework is available online, but we show here that its computational complexity prevents operations in low-power general purpose processors, even at throughputs below the standard. We therefore propose an evolution of this software that achieves a faster and lighter IEEE 802.11 a/g/p transmitter and receiver, suitable for low-power general purpose processors, for which GNU Radio provides very limited support; we discuss and describe the software radio processing structuring that is necessary to achieve the goal, providing a review of signal processing techniques. In particular, we emphasize the advanced reduced-instruction set (RISC machine (ARM study case, for which we also optimize some of the processing libraries. The presented software will remain open-source.

  13. Design and development of low-power driven hybrid electroluminescent lamp from carbon nanotube embedded phosphor material

    International Nuclear Information System (INIS)

    Yadav, Deepika; Mishra, Savvi; Shanker, Virendra; Haranath, D.

    2013-01-01

    Highlights: •We are first to report CNT embedded ZnS:Mn hybrid EL system. •Achieved efficient orange-red EL emission at low operating voltages ( AC ). •Facile technique to induce conductive paths inside the ZnS particle to trigger EL. •Detailed electrical characterization of EL lamp is presented. -- Abstract: We present a novel methodology to design a hybrid electroluminescent (EL) lamp by embedding carbon nanotubes (CNTs) inside the ZnS:Mn phosphor particles by conventional solid state diffusion technique. By doing so, the phosphor particles exhibited increase in EL brightness and efficiency at low operating voltages ( AC ). Interestingly, shorter the length of CNTs used, greater was the field enhancement effect and lower was the operating voltages to glow the EL lamps. The role of CNTs have been identified to form conductive paths inside the ZnS particle thereby triggering EL due to electron injection to luminescent centers (Mn 2+ ) at nominal voltages. In addition, a detailed electrical characterization of the novel EL lamp along with its spectral energy distribution studies are presented

  14. Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

    Science.gov (United States)

    Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

    2013-01-01

    In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

  15. Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays

    International Nuclear Information System (INIS)

    Douglas Curry; Alicia Hofler; Hai Dong; Trent Allison; J. Hovater; Kelly Mahoney

    2005-01-01

    At Jefferson Lab, we have been evaluating soft core processors running an EPICS IOC over μClinux on our custom hardware. A soft core processor is a flexible CPU architecture that is configured in the FPGA as opposed to a hard core processor which is fixed in silicon. Combined with an on-board Ethernet port, the technology incorporates the IOC and digital control hardware within a single FPGA. By eliminating the general purpose computer IOC, the designer is no longer tied to a specific platform, e.g. PC, VME, or VXI, to serve as the intermediary between the high level controls and the field hardware. This paper will discuss the design and development process as well as specific applications for JLab's next generation low-level RF controls and Machine Protection Systems

  16. Low power arcjet performance

    Science.gov (United States)

    Curran, Francis M.; Sarmiento, Charles J.

    1990-01-01

    An experimental investigation was performed to evaluate arcjet operation at low power. A standard, 1 kW, constricted arcjet was run using nozzles with three different constrictor diameters. Each nozzle was run over a range of current and mass flow rates to explore stability and performance in the low power regime. A standard pulse-width modulated power processor was modified to accommodate the high operating voltages required under certain conditions. Stable, reliable operation at power levels below 0.5 kW was obtained at efficiencies between 30 and 40 percent. The operating range was found to be somewhat dependent on constrictor geometry at low mass flow rates. Quasi-periodic voltage fluctuations were observed at the low power end of the operating envelope. The nozzle insert geometry was found to have little effect on the performance of the device. The observed performance levels show that specific impulse levels above 350 seconds can be obtained at the 0.5 kW power level.

  17. An Evaluation of an Ada Implementation of the Rete Algorithm for Embedded Flight Processors

    Science.gov (United States)

    1990-12-01

    computers was desired. The VAX VMS operating system has many built-in methods for determining program performance (including VAX PCA), but these methods... overviev , of the target environment-- the MIL-STD-1750A VHSIC Avionic Modular Processor ( VA.IP, running under the Ada Avionics Real-Time Software (AARTS... computers . Mil-STD-1750A, the Air Force’s standard flight computer architecture, however, places severe constraints on applications software processing

  18. An embedded real-time red peach detection system based on an OV7670 camera, ARM Cortex-M4 processor and 3D Look-Up Tables

    OpenAIRE

    Teixidó Cairol, Mercè; Font Calafell, Davinia; Pallejà Cabrè, Tomàs; Tresánchez Ribes, Marcel; Nogués Aymamí, Miquel; Palacín Roca, Jordi

    2012-01-01

    This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future...

  19. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

  20. Embedded SoPC design with NIOS II processor and VHDL examples

    CERN Document Server

    Chu, Pong P

    2011-01-01

    The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelb

  1. Introduction to co-simulation of software and hardware in embedded processor systems

    Energy Technology Data Exchange (ETDEWEB)

    Dreike, P.L.; McCoy, J.A.

    1996-09-01

    From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

  2. Analysis and optimization of fault-tolerant embedded systems with hardened processors

    DEFF Research Database (Denmark)

    Izosimov, Viacheslav; Polian, Ilia; Pop, Paul

    2009-01-01

    In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels...... of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault......-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled....

  3. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

  4. Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

    Science.gov (United States)

    Badoni, D.; Bizzarri, M.; Bonaiuto, V.; Checcucci, B.; De Simone, N.; Federici, L.; Fucci, A.; Paoluzzi, G.; Papi, A.; Piccini, M.; Salamon, A.; Salina, G.; Santovetti, E.; Sargeni, F.; Venditti, S.

    2014-01-01

    The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K+→π+ ν bar nu with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K+→π+ π0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests.

  5. Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

    International Nuclear Information System (INIS)

    Badoni, D; Fucci, A; Paoluzzi, G; Salamon, A; Salina, G; Bizzarri, M; Bonaiuto, V; Simone, N De; Federici, L; Sargeni, F; Checcucci, B; Papi, A; Piccini, M; Santovetti, E; Venditti, S

    2014-01-01

    The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K + →π +  ν ν-bar with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K + →π +  π 0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests

  6. Low power digital signal processing

    DEFF Research Database (Denmark)

    Paker, Ozgun

    2003-01-01

    hardwired ASICs and more than 6 21 times lower than current state of the art low-power DSP processors. An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved...... to be a viable alternative to conventional expensive test equipment. Finally, the work presented in this thesis has been published at several IEEE workshops and conferences, and in the Journal of VLSI Signal Processing....

  7. An Embedded Real-Time Red Peach Detection System Based on an OV7670 Camera, ARM Cortex-M4 Processor and 3D Look-Up Tables

    Directory of Open Access Journals (Sweden)

    Marcel Tresanchez

    2012-10-01

    Full Text Available This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6 processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

  8. An embedded real-time red peach detection system based on an OV7670 camera, ARM cortex-M4 processor and 3D look-up tables.

    Science.gov (United States)

    Teixidó, Mercè; Font, Davinia; Pallejà, Tomàs; Tresanchez, Marcel; Nogués, Miquel; Palacín, Jordi

    2012-10-22

    This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT) defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

  9. CASPER: Embedding Power Estimation and Hardware-Controlled Power Management in a Cycle-Accurate Micro-Architecture Simulation Platform for Many-Core Multi-Threading Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Arun Ravindran

    2012-02-01

    Full Text Available Despite the promising performance improvement observed in emerging many-core architectures in high performance processors, high power consumption prohibitively affects their use and marketability in the low-energy sectors, such as embedded processors, network processors and application specific instruction processors (ASIPs. While most chip architects design power-efficient processors by finding an optimal power-performance balance in their design, some use sophisticated on-chip autonomous power management units, which dynamically reduce the voltage or frequencies of idle cores and hence extend battery life and reduce operating costs. For large scale designs of many-core processors, a holistic approach integrating both these techniques at different levels of abstraction can potentially achieve maximal power savings. In this paper we present CASPER, a robust instruction trace driven cycle-accurate many-core multi-threading micro-architecture simulation platform where we have incorporated power estimation models of a wide variety of tunable many-core micro-architectural design parameters, thus enabling processor architects to explore a sufficiently large design space and achieve power-efficient designs. Additionally CASPER is designed to accommodate cycle-accurate models of hardware controlled power management units, enabling architects to experiment with and evaluate different autonomous power-saving mechanisms to study the run-time power-performance trade-offs in embedded many-core processors. We have implemented two such techniques in CASPER–Chipwide Dynamic Voltage and Frequency Scaling, and Performance Aware Core-Specific Frequency Scaling, which show average power savings of 35.9% and 26.2% on a baseline 4-core SPARC based architecture respectively. This power saving data accounts for the power consumption of the power management units themselves. The CASPER simulation platform also provides users with complete support of SPARCV9

  10. VON WISPR Family Processors: Volume 1

    National Research Council Canada - National Science Library

    Wagstaff, Ronald

    1997-01-01

    ...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

  11. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

  12. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  13. CRISP : a scalable VLIW processor for low power multimedia systems

    NARCIS (Netherlands)

    Barat Quesada, F.

    2005-01-01

    Over the last couple of years, the demand for portable multimedia devices has been growing at an impressive rate. The ideal multimedia device will present high quality multimedia content, and will be networked, portable, inexpensive and easy to use. In order to cope with the dynamism of current and

  14. JIST: Just-In-Time Scheduling Translation for Parallel Processors

    Directory of Open Access Journals (Sweden)

    Giovanni Agosta

    2005-01-01

    Full Text Available The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

  15. Low Power Computing in Distributed Systems

    Science.gov (United States)

    2006-04-01

    performance applications. It has been adopted in embedded systems such as the Stargate from Crossbow [15] and the PASTA 4 0 0.1 0.2 0.3 0.4 (A) flo at...current consumption of the Stargate board is measured by an Agilent digital multimeter 34401A. The digital multimeter is connected with the PC for data...floating point operation vs. integer operation Power supply Digital multimeter Stargate board with Xscale processor 5 2.2 Library math function vs

  16. Low power constant fraction discriminator

    International Nuclear Information System (INIS)

    Krishnan, Shanti; Raut, S.M.; Mukhopadhyay, P.K.

    2001-01-01

    This paper describes the design of a low power ultrafast constant fraction discriminator, which significantly reduces the power consumption. A conventional fast discriminator consumes about 1250 MW of power whereas this low power version consumes about 440 MW. In a multi detector system, where the number of discriminators is very large, reduction of power is of utmost importance. This low power discriminator is being designed for GRACE (Gamma Ray Atmospheric Cerenkov Experiments) telescope where 1000 channels of discriminators are required. A novel method of decreasing power consumption has been described. (author)

  17. C-HEAP : a heterogeneous multi-processor architecture template and scalable and flexible protocol for the design of embedded signal processing systems

    NARCIS (Netherlands)

    Nieuwland, A.K.; Kang, J.; Gangwal, O.P.; Sethuraman, R.; Busá, N.G.; Goossens, K.G.W.; Peset Llopis, R.; Lippens, P.E.R.

    2002-01-01

    The key issue in the design of Systems-on-a-Chip (SoC) is to trade-off efficiency against flexibility, and time to market versus cost. Current deep submicron processing technologies enable integration of multiple software programmable processors (e.g., CPUs, DSPs) and dedicated hardware components

  18. Low Power/Low Voltage Interface Circuitry for Capacitive Sensors

    DEFF Research Database (Denmark)

    Furst, Claus Efdmann

    This thesis focuses mainly on low power/low voltage interface circuits, implemented in CMOS, for capacitive sensors. A brief discussion of demands and possibilities for analog signal processing in the future is presented. Techniques for low power design is presented. This is done by analyzing power...... power consumption. It is shown that the Sigma-Delta modulator is advantageous when embedded in a feedback loop with a mechanical sensor. Here a micro mechanical capacitive microphone. Feedback and detection circuitry for a capacitive microphone is presented. Practical implementations of low power....../low voltage interface circuitry is presented. It is demonstrated that an amplifier optimized for a capacitive microphone implemented in a standard 0.7 micron CMOS technology competes well with a traditional JFET amplifier. Furthermore a low power/low voltage 3rd order Sigma-Delta modulator is presented...

  19. Low-power wind plants

    International Nuclear Information System (INIS)

    Kovalenko, V.I.; Shevchenko, Yu.V.; Shikhajlov, N.A.; Kokhanevich, V.P.; Tanan, G.L.

    1993-01-01

    Design peculiarities, as well as the prospects of development and introduction of the low-power (from 0.5 up to 4 kW) wind power plants (WPP) are considered. The variants of WPP with vertical and horizontal rotation axis are described. The data characterizing cost and structure of expenditures on WPP manufacture and operation are given

  20. Design of low-power coarse-grained reconfigurable architectures

    CERN Document Server

    Kim, Yoonjin

    2010-01-01

    Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks.The first half of the book explains how to reduce power in the configuration cache. T

  1. Green Secure Processors: Towards Power-Efficient Secure Processor Design

    Science.gov (United States)

    Chhabra, Siddhartha; Solihin, Yan

    With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

  2. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  3. Low power unattended defense reactor

    International Nuclear Information System (INIS)

    Kirchner, W.L.; Meier, K.L.

    1984-01-01

    A small, low power, passive, nuclear reactor electric power supply has been designed for unattended defense applications. Through innovative utilization of existing proven technologies and components, a highly reliable, ''walk-away safe'' design has been obtained. Operating at a thermal power level of 200 kWt, the reactor uses low enrichment uranium fuel in a graphite block core to generate heat that is transferred through heat pipes to a thermoelectric (TE) converter. Waste heat is removed from the TEs by circulation of ambient air. Because such a power supply offers the promise of minimal operation and maintenance (OandM) costs as well as no fuel logistics, it is particularly attractive for remote, unattended applications such as the North Warning System

  4. Low power unattended defense reactor

    International Nuclear Information System (INIS)

    Kirchner, W.L.; Meier, K.L.

    1984-01-01

    A small, low power, passive, nuclear reactor electric power supply has been designed for unattended defense applications. Through innovative utilization of existing proven technologies and components, a highly reliable, walk-away safe design has been obtained. Operating at a thermal power level of 200 kWt, the reactor uses low enrichment uranium fuel in a graphite block core to generate heat that is transferred through heat pipes to a thermoelectric (TE) converter. Waste heat is removed from the TEs by circulation of ambient air. Because such a power supply offers the promise of minimal operation and maintenance (O and M) costs as well as no fuel logistics, it is particularly attractive for remote, unattended applications such as the North Warning System

  5. Suitability of tile-based rendering for low-power 3d graphics accelerators

    NARCIS (Netherlands)

    Antochi, I.

    2007-01-01

    In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these

  6. NInFEA: an embedded framework for the real-time evaluation of fetal ECG extraction algorithms.

    Science.gov (United States)

    Pani, Danilo; Barabino, Gianluca; Raffo, Luigi

    2013-02-01

    Fetal electrocardiogram (ECG) extraction from non-invasive biopotential recordings is a long-standing research topic. Despite the significant number of algorithms presented in the scientific literature, it is difficult to find information about embedded hardware implementations able to provide real-time support for the required features, bridging the gap between theory and practice. This article presents the NInFEA (non-invasive fetal ECG analysis) tool, an embedded hardware/software framework based on the hybrid dual-core OMAP-L137 low-power processor for the real-time evaluation of fetal ECG extraction algorithms. The hybrid platform, including a digital signal processor (DSP) and a general-purpose processor (GPP), allows achieving the best performance compared with single-core architectures. The GPP provides a portable graphical user interface, whereas the DSP is extensively used for advanced signal processing tasks. As a case study, three state-of-the-art fetal ECG extraction algorithms have been ported onto NInFEA, along with some support routines needed to provide the additional information required by the clinicians and supported by the user interface. NInFEA can be regarded both as a reference design for similar applications and as a common embedded low-power testbed for real-time fetal ECG extraction algorithms.

  7. Low-Power Wireless Sensor Network Infrastructures

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg

    Advancements in wireless communication and electronics improving form factor and hardware capabilities has expanded the applicability of wireless sensor networks. Despite these advancements, devices are still limited in terms of energy which creates the need for duty-cycling and low-power protocols...... peripherals need to by duty-cycled and the low-power wireless radios are severely influenced by the environmental effects causing bursty and unreliable wireless channels. This dissertation presents a communication stack providing services for low-power communication, secure communication, data collection......, and network management which enables construction of low-power wireless sensor network applications. More specifically, these services are designed with the extreme low-power scenarios of the SensoByg project in mind and are implemented as follows. First, low-power communication is implemented with Auto...

  8. Embedded Hardware

    CERN Document Server

    Ganssle, Jack G; Eady, Fred; Edwards, Lewin; Katz, David J; Gentile, Rick

    2007-01-01

    The Newnes Know It All Series takes the best of what our authors have written to create hard-working desk references that will be an engineer's first port of call for key information, design techniques and rules of thumb. Guaranteed not to gather dust on a shelf!. Circuit design using microcontrollers is both a science and an art. This book covers it all. It details all of the essential theory and facts to help an engineer design a robust embedded system. Processors, memory, and the hot topic of interconnects (I/O) are completely covered. Our authors bring a wealth of experience and ideas; thi

  9. High voltage generator circuit with low power and high efficiency applied in EEPROM

    International Nuclear Information System (INIS)

    Liu Yan; Zhang Shilin; Zhao Yiqiang

    2012-01-01

    This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

  10. Multithreading for Embedded Reconfigurable Multicore Systems

    NARCIS (Netherlands)

    Zaykov, P.G.

    2014-01-01

    In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor

  11. Multithreading for embedded reconfigurable multicore systems

    NARCIS (Netherlands)

    Zaykov, P.G.

    2014-01-01

    In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor

  12. A low-power asynchronous data-path for a FIR filter bank

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1996-01-01

    This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application....... The algorithm requires a fixed number of steps and the moderate speed requirement allows a sequential implementation. The latter, in combination with a huge predominance of numerically small data values in the input data stream, is the key to a low-power asynchronous implementation. Power is minimized in two...

  13. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  14. Perspectives on Low Power and Shutdown Risk

    International Nuclear Information System (INIS)

    Camp, Allen L.; Whitehead, Donnie W.; Wheeler, Timothy A.; Lehner, John; Chu, Tsong-Lun; Lois, Erasmai; Drouin, Mary

    2000-01-01

    This paper presents results from a program sponsored by the US Nuclear Regulatory Commission to examine the risks from low power and shutdown operations. Significant progress has been made by the industry in reducing such risks; however, important operational events continue to occur. Current perceptions of low power and shutdown risks are discussed in the paper along with an assessment of the current methods for understanding important events and quantifying their associated risk

  15. Ultra low power full adder topologies

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag T.; Mahmoodi, Hamid

    In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the pr...... the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations....

  16. System Control Applications of Low-Power Radio Frequency Devices

    Science.gov (United States)

    van Rensburg, Roger

    2017-09-01

    This paper conceptualizes a low-power wireless sensor network design for application employment to reduce theft of portable computer devices used in educational institutions today. The aim of this study is to design and develop a reliable and robust wireless network that can eradicate accessibility of a device’s human interface. An embedded system supplied by an energy harvesting source, installed on the portable computer device, may represent one of multiple slave nodes which request regular updates from a standalone master station. A portable computer device which is operated in an undesignated area or in a field perimeter where master to slave communication is restricted, indicating a possible theft scenario, will initiate a shutdown of its operating system and render the device unusable. Consequently, an algorithm in the device firmware may ensure the necessary steps are executed to track the device, irrespective whether the device is enabled. Design outcomes thus far indicate that a wireless network using low-power embedded hardware, is feasible for anti-theft applications. By incorporating one of the latest Bluetooth low-energy, ANT+, ZigBee or Thread wireless technologies, an anti-theft system may be implemented that has the potential to reduce major portable computer device theft in institutions of digitized learning.

  17. Low Power Multi-Hop Networking Analysis in Intelligent Environments.

    Science.gov (United States)

    Etxaniz, Josu; Aranguren, Gerardo

    2017-05-19

    Intelligent systems are driven by the latest technological advances in many different areas such as sensing, embedded systems, wireless communications or context recognition. This paper focuses on some of those areas. Concretely, the paper deals with wireless communications issues in embedded systems. More precisely, the paper combines the multi-hop networking with Bluetooth technology and a quality of service (QoS) metric, the latency. Bluetooth is a radio license-free worldwide communication standard that makes low power multi-hop wireless networking available. It establishes piconets (point-to-point and point-to-multipoint links) and scatternets (multi-hop networks). As a result, many Bluetooth nodes can be interconnected to set up ambient intelligent networks. Then, this paper presents the results of the investigation on multi-hop latency with park and sniff Bluetooth low power modes conducted over the hardware test bench previously implemented. In addition, the empirical models to estimate the latency of multi-hop communications over Bluetooth Asynchronous Connectionless Links (ACL) in park and sniff mode are given. The designers of devices and networks for intelligent systems will benefit from the estimation of the latency in Bluetooth multi-hop communications that the models provide.

  18. The design of infrared information collection circuit based on embedded technology

    Science.gov (United States)

    Liu, Haoting; Zhang, Yicong

    2013-07-01

    S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

  19. The Inertial Stellar Compass (ISC): A Multifunction, Low Power, Attitude Determination Technology Breakthrough

    Science.gov (United States)

    Bauer, Frank H. (Technical Monitor); Dennehy, Neil; Gambino, Joel; Maynard, Andrew; Brady, T.; Buckley, S.; Zinchuk, J.

    2003-01-01

    The Inertial Stellar Compass (ISC) is a miniature, low power, stellar inertial attitude determination system with an accuracy of better than 0.1 degree (1 sigma) in three axes. The ISC consumes only 3.5 Watts of power and is contained in a 2.5 kg package. With its embedded on-board processor, the ISC provides attitude quaternion information and has Lost-in-Space (LIS) initialization capability. The attitude accuracy and LIS capability are provided by combining a wide field of view Active Pixel Sensor (APS) star camera and Micro- ElectroMechanical System (MEMS) inertial sensor information in an integrated sensor system. The performance and small form factor make the ISC a useful sensor for a wide range of missions. In particular, the ISC represents an enabling, fully integrated, micro-satellite attitude determination system. Other applications include using the ISC as a single sensor solution for attitude determination on medium performance spacecraft and as a bolt on independent safe-hold sensor or coarse acquisition sensor for many other spacecraft. NASA's New Millennium Program (NMP) has selected the ISC technology for a Space Technology 6 (ST6) flight validation experiment scheduled for 2004. NMP missions, such a s ST6, are intended to validate advanced technologies that have not flown in space in order to reduce the risk associated with their infusion into future NASA missions. This paper describes the design, operation, and performance of the ISC and outlines the technology validation plan. A number of mission applications for the ISC technology are highlighted, both for the baseline ST6 ISC configuration and more ambitious applications where ISC hardware and software modifications would be required. These applications demonstrate the wide range of Space and Earth Science missions that would benefit from infusion of the ISC technology.

  20. 16-Bit RISC Processor Design for Convolution Application

    OpenAIRE

    Anand Nandakumar Shardul

    2013-01-01

    In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

  1. A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.

    Science.gov (United States)

    Jafari, Ali; Buswell, Nathanael; Ghovanloo, Maysam; Mohsenin, Tinoosh

    2018-02-01

    This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10 lower than FPGA power consumption and occupies an area of only 0.016 mm.

  2. A heterogeneous multiprocessor architecture for low-power audio signal processing applications

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

    2001-01-01

    . The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occurs at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs...... of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word×16 bit program memory, a 64 word×16 bit data memory and a 25 word×16 bit coefficient memory....... Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1...

  3. Interleaved Subtask Scheduling on Multi Processor SOC

    NARCIS (Netherlands)

    Zhe, M.

    2006-01-01

    The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

  4. Low power signal processing research at Stanford

    Science.gov (United States)

    Burr, J.; Williamson, P. R.; Peterson, A.

    1991-01-01

    This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

  5. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  6. Low power laser in Odonto-stomathology

    International Nuclear Information System (INIS)

    Valiente Zaldivar, Carolina

    2009-01-01

    The use of low power laser technology in our country, and mainly in Odonto-stomathology, have gad a constant evolution and development since the 80's, being significant the social repercution between professionals and patients, achieving and alternative of treatment, which is non painful, and the results, either analgesic, anti-inflammatory, and stimulating of the tissue regeneration. This work intends to show the therapeutic procedure, and the different clinical entities, treated with Cuban instruments, that contains red or infrared diode lasers. The experience, during more than 20 years of the use of this kind of low power lasers, with different radiation techniques, includes: laser therapy or their combination with acupuncture points, so-called Laser puncture, which makes this technology an alternative of treatment for several clinical entities in correspondence with alterations of the tissues of the tooth, the mucose, neuronal alterations, and so on, procedures that are generalized in more that 60 services of our country. (Author)

  7. Low-Power Public Key Cryptography

    Energy Technology Data Exchange (ETDEWEB)

    BEAVER,CHERYL L.; DRAELOS,TIMOTHY J.; HAMILTON,VICTORIA A.; SCHROEPPEL,RICHARD C.; GONZALES,RITA A.; MILLER,RUSSELL D.; THOMAS,EDWARD V.

    2000-11-01

    This report presents research on public key, digital signature algorithms for cryptographic authentication in low-powered, low-computation environments. We assessed algorithms for suitability based on their signature size, and computation and storage requirements. We evaluated a variety of general purpose and special purpose computing platforms to address issues such as memory, voltage requirements, and special functionality for low-powered applications. In addition, we examined custom design platforms. We found that a custom design offers the most flexibility and can be optimized for specific algorithms. Furthermore, the entire platform can exist on a single Application Specific Integrated Circuit (ASIC) or can be integrated with commercially available components to produce the desired computing platform.

  8. Low Cost, Low Power, High Sensitivity Magnetometer

    Science.gov (United States)

    2008-12-01

    which are used to measure the small magnetic signals from brain. Other types of vector magnetometers are fluxgate , coil based, and magnetoresistance...concentrator with the magnetometer currently used in Army multimodal sensor systems, the Brown fluxgate . One sees the MEMS fluxgate magnetometer is...Guedes, A.; et al., 2008: Hybrid - LOW COST, LOW POWER, HIGH SENSITIVITY MAGNETOMETER A.S. Edelstein*, James E. Burnette, Greg A. Fischer, M.G

  9. Integrated low power ultrasound sensor interfaces

    OpenAIRE

    Gustafsson, Martin

    2005-01-01

    Imagine that the technical development can take the ultrasound measurement systems from the large piece of machinery today, to a coin size system tomorrow. The factor that has reduced the size of electronic systems over time is integration and integrated circuits. In this thesis circuit simulator models of complete ultrasound systems are used to design custom integrated circuits. These circuits are optimized for low power consumption and small size. The models that are used predict the acoust...

  10. Imprecise Arithmetic for Low Power Image Processing

    DEFF Research Database (Denmark)

    Albicocco, Pietro; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2012-01-01

    Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, additio...... and multiplication, in an imprecise manner by simplifying the hardware implementation. With the proposed ”sloppy” operations, we obtain a reduction in delay, area and power dissipation, and the error introduced is still acceptable for applications such as image processing.......Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, addition...

  11. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Directory of Open Access Journals (Sweden)

    Seung-Ho Ok

    2017-02-01

    Full Text Available Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV, three-dimensional (3D stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  12. Fast Low Power ADC with Integrated Digital Data Processor, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Innovative data measurement/acquisition systems are needed to support future Earth System Science measurements of the Earth's atmosphere and surface. An adequate...

  13. Ultra - Low - Power Asynchronous Processor and FPGA Design using Straintronics Nanomagnets

    Science.gov (United States)

    2013-05-01

    i‐th filter BW  The  coefficients   are  generated  inside  the  controller.  The  architecture  avoids  multipliers  and  shares  the  coefficients ...illustrated  in  Fig  25  –b.  i)  The  E‐field  causes  a  strain  in  PZT   leading  to a deformation S =  .  ii) Strain gets  transformed  to  free NM.  iii... PZT  is a parallel place capacitance while MTJ  is a variable resistance. This  is shown  in Fig  26. Shape anisotropy and uniaxial crystalline

  14. Multithreading in vector processors

    Science.gov (United States)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  15. A low power Multi-Channel Analyzer

    International Nuclear Information System (INIS)

    Anderson, G.A.; Brackenbush, L.W.

    1993-06-01

    The instrumentation used in nuclear spectroscopy is generally large, is not portable, and requires a lot of power. Key components of these counting systems are the computer and the Multi-Channel Analyzer (MCA). To assist in performing measurements requiring portable systems, a small, very low power MCA has been developed at Pacific Northwest Laboratory (PNL). This MCA is interfaced with a Hewlett Packard palm top computer for portable applications. The MCA can also be connected to an IBM/PC for data storage and analysis. In addition, a real-time time display mode allows the user to view the spectra as they are collected

  16. Cold neutron radiography using low power accelerator

    International Nuclear Information System (INIS)

    Kiyanagi, Yoshiaki; Iwasa, Hirokatu

    1993-01-01

    A cold neutron source which can be adopted at a low power accelerator was studied. Time-of-flight radiography using the cold neutron source was performed. It is suggested that time-of-flight cold neutron radiography has possibility to distinguish the materials more clearly than the traditional film method since large contrast differences can be obtained by using digital data of the neutron intensity at different energies from thermal to cold region. Material will be identified at the same time by this method. (author)

  17. Voltage scheduling for low power/energy

    Science.gov (United States)

    Manzak, Ali

    2001-07-01

    Power considerations have become an increasingly dominant factor in the design of both portable and desk-top systems. An effective way to reduce power consumption is to lower the supply voltage since voltage is quadratically related to power. This dissertation considers the problem of lowering the supply voltage at (i) the system level and at (ii) the behavioral level. At the system level, the voltage of the variable voltage processor is dynamically changed with the work load. Processors with limited sized buffers as well as those with very large buffers are considered. Given the task arrival times, deadline times, execution times, periods and switching activities, task scheduling algorithms that minimize energy or peak power are developed for the processors equipped with very large buffers. A relation between the operating voltages of the tasks for minimum energy/power is determined using the Lagrange multiplier method, and an iterative algorithm that utilizes this relation is developed. Experimental results show that the voltage assignment obtained by the proposed algorithm is very close (0.1% error) to that of the optimal energy assignment and the optimal peak power (1% error) assignment. Next, on-line and off-fine minimum energy task scheduling algorithms are developed for processors with limited sized buffers. These algorithms have polynomial time complexity and present optimal (off-line) and close-to-optimal (on-line) solutions. A procedure to calculate the minimum buffer size given information about the size of the task (maximum, minimum), execution time (best case, worst case) and deadlines is also presented. At the behavioral level, resources operating at multiple voltages are used to minimize power while maintaining the throughput. Such a scheme has the advantage of allowing modules on the critical paths to be assigned to the highest voltage levels (thus meeting the required timing constraints) while allowing modules on non-critical paths to be assigned

  18. Embedded Systems Design with FPGAs

    CERN Document Server

    Pnevmatikatos, Dionisios; Sklavos, Nicolas

    2013-01-01

    This book presents methodologies for modern applications of embedded systems design, using field programmable gate array (FPGA) devices.  Coverage includes state-of-the-art research from academia and industry on a wide range of topics, including advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration and applications. Describes a variety of methodologies for modern embedded systems design;  Implements methodologies presented on FPGAs; Covers a wide variety of applications for reconfigurable embedded systems, including Bioinformatics, Communications and networking, Application acceleration, Medical solutions, Experiments for high energy physics, Astronomy, Aerospace, Biologically inspired systems and Computational fluid dynamics (CFD).

  19. A heterogeneous multi-core platform for low power signal processing in systems-on-chip

    DEFF Research Database (Denmark)

    Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

    2002-01-01

    is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more......This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

  20. Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor SOC

    NARCIS (Netherlands)

    Nelson, A.T.; Goossens, K.G.W.; Akesson, K.B.

    2015-01-01

    Embedded systems often contain multiple applications, some of which have real-time requirements and whose performance must be guaranteed. To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM

  1. Low power adder based auditory filter architecture.

    Science.gov (United States)

    Rahiman, P F Khaleelur; Jayanthi, V S

    2014-01-01

    Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT) based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  2. Low Power Adder Based Auditory Filter Architecture

    Directory of Open Access Journals (Sweden)

    P. F. Khaleelur Rahiman

    2014-01-01

    Full Text Available Cochlea devices are powered up with the help of batteries and they should possess long working life to avoid replacing of devices at regular interval of years. Hence the devices with low power consumptions are required. In cochlea devices there are numerous filters, each responsible for frequency variant signals, which helps in identifying speech signals of different audible range. In this paper, multiplierless lookup table (LUT based auditory filter is implemented. Power aware adder architectures are utilized to add the output samples of the LUT, available at every clock cycle. The design is developed and modeled using Verilog HDL, simulated using Mentor Graphics Model-Sim Simulator, and synthesized using Synopsys Design Compiler tool. The design was mapped to TSMC 65 nm technological node. The standard ASIC design methodology has been adapted to carry out the power analysis. The proposed FIR filter architecture has reduced the leakage power by 15% and increased its performance by 2.76%.

  3. Low power reactor for remote applications

    International Nuclear Information System (INIS)

    Meier, K.L.; Palmer, R.G.; Kirchner, W.L.

    1985-01-01

    A compact, low power reactor is being designed to provide electric power for remote, unattended applications. Because of the high fuel and maintenance costs for conventional power sources such as diesel generators, a reactor power supply appears especially attractive for remote and inaccessible locations. Operating at a thermal power level of 135 kWt, the power supply achieves a gross electrical output of 25 kWe from an organic Rankine cycle (ORC) engine. By intentional selection of design features stressing inherent safety, operation in an unattended mode is possible with minimal risk to the environment. Reliability is achieved through the use of components representing existing, proven technology. Low enrichment uranium particle fuel, in graphite core blocks, cooled by heat pipes coupled to an ORC converter insures long-term, virtually maintenance free, operation of this reactor for remote applications. 10 refs., 7 figs., 3 tabs

  4. Radiation Tolerant Low Power Precision Time Source, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — The availability of small, low power atomic clocks is now a reality for ground-based and airborne navigation systems. Kernco's Low Power Precision Time Source...

  5. A pulse amplitude discriminator with very low-power consuming

    International Nuclear Information System (INIS)

    Deng Changming; Liu Zhengshan; Zhang Zhiyong; Cheng Chang

    2000-01-01

    A low-power pulse amplitude discriminator is described. The discriminator circuit is mainly composed of an integrated voltage comparator, MAX921, and owns the characters of very low-power and low operating voltage

  6. Integrated fuel processor development

    International Nuclear Information System (INIS)

    Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

    2001-01-01

    The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

  7. Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster

    Science.gov (United States)

    Göddeke, Dominik; Komatitsch, Dimitri; Geveler, Markus; Ribbrock, Dirk; Rajovic, Nikola; Puzovic, Nikola; Ramirez, Alex

    2013-03-01

    Power consumption and energy efficiency are becoming critical aspects in the design and operation of large scale HPC facilities, and it is unanimously recognised that future exascale supercomputers will be strongly constrained by their power requirements. At current electricity costs, operating an HPC system over its lifetime can already be on par with the initial deployment cost. These power consumption constraints, and the benefits a more energy-efficient HPC platform may have on other societal areas, have motivated the HPC research community to investigate the use of energy-efficient technologies originally developed for the embedded and especially mobile markets. However, lower power does not always mean lower energy consumption, since execution time often also increases. In order to achieve competitive performance, applications then need to efficiently exploit a larger number of processors. In this article, we discuss how applications can efficiently exploit this new class of low-power architectures to achieve competitive performance. We evaluate if they can benefit from the increased energy efficiency that the architecture is supposed to achieve. The applications that we consider cover three different classes of numerical solution methods for partial differential equations, namely a low-order finite element multigrid solver for huge sparse linear systems of equations, a Lattice-Boltzmann code for fluid simulation, and a high-order spectral element method for acoustic or seismic wave propagation modelling. We evaluate weak and strong scalability on a cluster of 96 ARM Cortex-A9 dual-core processors and demonstrate that the ARM-based cluster can be more efficient in terms of energy to solution when executing the three applications compared to an x86-based reference machine.

  8. Energy neutral and low power wireless communications

    Science.gov (United States)

    Orhan, Oner

    Wireless sensor nodes are typically designed to have low cost and small size. These design objectives impose restrictions on the capacity and efficiency of the transceiver components and energy storage units that can be used. As a result, energy becomes a bottleneck and continuous operation of the sensor network requires frequent battery replacements, increasing the maintenance cost. Energy harvesting and energy efficient transceiver architectures are able to overcome these challenges by collecting energy from the environment and utilizing the energy in an intelligent manner. However, due to the nature of the ambient energy sources, the amount of useful energy that can be harvested is limited and unreliable. Consequently, optimal management of the harvested energy and design of low power transceivers pose new challenges for wireless network design and operation. The first part of this dissertation is on energy neutral wireless networking, where optimal transmission schemes under different system setups and objectives are investigated. First, throughput maximization for energy harvesting two-hop networks with decode-and-forward half-duplex relays is studied. For a system with two parallel relays, various combinations of the following four transmission modes are considered: Broadcast from the source, multi-access from the relays, and successive relaying phases I and II. Next, the energy cost of the processing circuitry as well as the transmission energy are taken into account for communication over a broadband fading channel powered by an energy harvesting transmitter. Under this setup, throughput maximization, energy maximization, and transmission completion time minimization problems are studied. Finally, source and channel coding for an energy-limited wireless sensor node is investigated under various energy constraints including energy harvesting, processing and sampling costs. For each objective, optimal transmission policies are formulated as the solutions of a

  9. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  10. 3081/E processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.

    1984-04-01

    The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

  11. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  12. Adaptive signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

  13. Adaptive signal processor

    International Nuclear Information System (INIS)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  14. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  15. Computers as components principles of embedded computing system design

    CERN Document Server

    Wolf, Marilyn

    2012-01-01

    Computers as Components: Principles of Embedded Computing System Design, 3e, presents essential knowledge on embedded systems technology and techniques. Updated for today's embedded systems design methods, this edition features new examples including digital signal processing, multimedia, and cyber-physical systems. Author Marilyn Wolf covers the latest processors from Texas Instruments, ARM, and Microchip Technology plus software, operating systems, networks, consumer devices, and more. Like the previous editions, this textbook: Uses real processors to demonstrate both technology and tec

  16. Low power acoustic harvesting of aerosols

    Energy Technology Data Exchange (ETDEWEB)

    Kaduchak, G. (Gregory); Sinha, D. N. (Dipen N)

    2001-01-01

    A new acoustic device for levitation and/or concentration of aerosols and sniall liquid/solid samples (up to several millimeters in diameter) in air has been developed. The device is inexpensive, low-power, and, in its simplest embodiment, does not require accurate alignmen1 of a resonant cavity. It is constructed from a cylindrical PZT tube of outside diameter D = 19.0 mm and thickness-to-radius ratio h/a - 0.03. The lowest-order breathing mode of the tube is tuned to match a resonant mode of the interior air-filled cylindrical cavity. A high Q cavity results that can be driven efficiently. An acoustic standing wave is created in the inteirior cavity of the cylindrical shell where particle concrmtration takes place at the nodal planes of the field. It is shown that drops of water in excess of 1 mm in diameter may be levitated against the force of gravity for approxirnately 100 mW of input electrical power. The main objective of the research is to implement this lowpower device to concentrate and harvest aerosols in a flowing system. Several different cavity geonietries iwe presented for efficient collection of 1 he conaartratetl aerosols. Concentraiion factors greater than 40 iue demonstrated for particles of size 0.7 1.1 in a flow volume of 50 L/minute.

  17. New generation low power radiation survey instruments

    International Nuclear Information System (INIS)

    Waechter, D.A.; Bjarke, G.O.; Trujillo, F.; Umbarger, C.J.; Wolf, M.A.

    1984-01-01

    A number of new, ultra-low-powered radiation instruments have recently been developed at Los Alamos. Among these are two instruments which use a novel power source to eliminate costly batteries. The newly developed gamma detecting radiac, nicknamed the Firefly, and the alpha particle detecting instrument, called the Simple Cordless Alpha Monitor, both use recent advances in miniaturization and powersaving electronics to yield devices which are small, rugged, and very power-frugal. The two instruments consume so little power that the need for batteries to run them is eliminated. They are, instead, powered by a charged capacitor which will operate the instruments for an hour or more. Use of a capacitor as a power source eliminates many problems commonly associated with battery-operated instruments, such as having to open the case to change batteries, battery storage life, availability of batteries in the field, and some savings in weight. Both line power and mechanical sources are used to charge the storage capacitors which power the instruments

  18. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  19. Embedded Systems

    Indian Academy of Sciences (India)

    Embedded system, micro-con- troller ... Embedded systems differ from general purpose computers in many ... Low cost: As embedded systems are extensively used in con- .... operating systems for the desktop computers where scheduling.

  20. Embedded Leverage

    DEFF Research Database (Denmark)

    Frazzini, Andrea; Heje Pedersen, Lasse

    find that asset classes with embedded leverage offer low risk-adjusted returns and, in the cross-section, higher embedded leverage is associated with lower returns. A portfolio which is long low-embedded-leverage securities and short high-embedded-leverage securities earns large abnormal returns...

  1. 3081//sub E/ processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

    1983-03-01

    Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

  2. Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

    OpenAIRE

    Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

    2016-01-01

    Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

  3. A Trade Study of Two Membrane-Aerated Biological Water Processors

    Science.gov (United States)

    Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

    2011-01-01

    Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

  4. Hacking and penetration testing with low power devices

    CERN Document Server

    Polstra, Philip

    2014-01-01

    Hacking and Penetration Testing with Low Power Devices shows you how to perform penetration tests using small, low-powered devices that are easily hidden and may be battery-powered. It shows how to use an army of devices, costing less than you might spend on a laptop, from distances of a mile or more. Hacking and Penetration Testing with Low Power Devices shows how to use devices running a version of The Deck, a full-featured penetration testing and forensics Linux distribution, and can run for days or weeks on batteries due to their low power consumption. Author Philip Polstra shows how to

  5. A single chip pulse processor for nuclear spectroscopy

    International Nuclear Information System (INIS)

    Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

    1985-01-01

    A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

  6. Inexpensive, Low Power, Open-Source Data Logging hardware development

    Science.gov (United States)

    Sandell, C. T.; Schulz, B.; Wickert, A. D.

    2017-12-01

    Over the past six years, we have developed a suite of open-source, low-cost, and lightweight data loggers for scientific research. These loggers employ the popular and easy-to-use Arduino programming environment, but consist of custom hardware optimized for field research. They may be connected to a broad and expanding range of off-the-shelf sensors, with software support built in directly to the "ALog" library. Three main models exist: The ALog (for Autonomous or Arduino Logger) is the extreme low-power model for years-long deployments with only primary AA or D batteries. The ALog shield is a stripped-down ALog that nests with a standard Arduino board for prototyping or education. The TLog (for Telemetering Logger) contains an embedded radio with 500 m range and a GPS for communications and precision timekeeping. This enables meshed networks of loggers that can send their data back to an internet-connected "home base" logger for near-real-time field data retrieval. All boards feature feature a high-precision clock, full size SD card slot for high-volume data storage, large screw terminals to connect sensors, interrupts, SPI and I2C communication capability, and 3.3V/5V power outputs. The ALog and TLog have fourteen 16-bit analog inputs with a precision voltage reference for precise analog measurements. Their components are rated -40 to +85 degrees C, and they have been tested in harsh field conditions. These low-cost and open-source data loggers have enabled our research group to collect field data across North and South America on a limited budget, support student projects, and build toward better future scientific data systems.

  7. ALICE chip processor

    CERN Multimedia

    Maximilien Brice

    2003-01-01

    This tiny chip provides data processing for the time projection chamber on ALICE. Known as the ALICE TPC Read Out (ALTRO), this device was designed to minimize the size and power consumption of the TPC front end electronics. This single chip contains 16 low-power analogue-to-digital converters with six million transistors of digital processing and 8 kbits of data storage.

  8. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  9. The Molen Polymorphic Media Processor

    NARCIS (Netherlands)

    Kuzmanov, G.K.

    2004-01-01

    In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

  10. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  11. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    International Nuclear Information System (INIS)

    Zacharias, Sven; Newe, Thomas

    2011-01-01

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  12. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    Energy Technology Data Exchange (ETDEWEB)

    Zacharias, Sven; Newe, Thomas, E-mail: Sven.Zacharias@ul.ie [University of Limerick (Ireland)

    2011-08-17

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  13. Competition at the Wireless Sensor Network MAC Layer: Low Power Probing interfering with X-MAC

    Science.gov (United States)

    Zacharias, Sven; Newe, Thomas

    2011-08-01

    Wireless Sensor Networks (WSNs) combine sensors with computer networks and enable very dense, in-situ and live measurements of data over a large area. Since this emerging technology has the potential to be embedded almost everywhere for numberless applications, interference between different networks can become a serious issue. For most WSNs, it is assumed today that the network medium access is non-competitive. On the basis of X-MAC interfered by Low Power Probing, this paper shows the danger and the effects of different sensor networks communicating on a single wireless channel of the 2.4 GHz band, which is used by the IEEE 802.15.4 standard.

  14. A HARDWARE SUPPORTED OPERATING SYSTEM KERNEL FOR EMBEDDED HARD REAL-TIME APPLICATIONS

    NARCIS (Netherlands)

    COLNARIC, M; HALANG, WA; TOL, RM

    1994-01-01

    The concept of the kernel, i.e. the time critical part of a real-time operating system, and its dedicated co-processor, especially tailored for embedded applications, are presented. The co-processor acts as a system controller and operates in conjunction with one or more conventional processors in

  15. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  16. Certifiable Java for Embedded Systems

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Dalsgaard, Andreas Engelbredt; Hansen, Rene Rydhof

    2014-01-01

    The Certifiable Java for Embedded Systems (CJ4ES) project aimed to develop a prototype development environment and platform for safety-critical software for embedded applications. There are three core constituents: A profile of the Java programming language that is tailored for safety......-critical applications, a predictable Java processor built with FPGA technology, and an Eclipse based application development environment that binds the profile and the platform together and provides analyses that help to provide evidence that can be used as part of a safety case. This paper summarizes key contributions...

  17. Embedded multiprocessors scheduling and synchronization

    CERN Document Server

    Sriram, Sundararajan

    2009-01-01

    Techniques for Optimizing Multiprocessor Implementations of Signal Processing ApplicationsAn indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications. Reviews important research in key areas related to the multiprocessor implementation of multi

  18. Development of an Erlang System Adaopted to Embedded Devices

    OpenAIRE

    Andersson, Fredrik; Bergström, Fabian

    2011-01-01

    Erlang is a powerful and robust language for writing massively parallel and distributed applications. With the introduction of multi-core ARM processors, the embedded market will be looking for ways of taking advantage of the newfound opportunities for parallelism. To support the development of embedded applications using Erlang we want to provide Erlang and Embedded developers with a run-time system suited for embedded devices. We have managed to shrink the disk size of the Erlang runtime sy...

  19. Design of ultra-low power impulse radios

    CERN Document Server

    Apsel, Alyssa; Dokania, Rajeev

    2014-01-01

    This book covers the fundamental principles behind the design of ultra-low power radios and how they can form networks to facilitate a variety of applications within healthcare and environmental monitoring, since they may operate for years off a small battery or even harvest energy from the environment. These radios are distinct from conventional radios in that they must operate with very constrained resources and low overhead.  This book provides a thorough discussion of the challenges associated with designing radios with such constrained resources, as well as fundamental design concepts and practical approaches to implementing working designs.  Coverage includes integrated circuit design, timing and control considerations, fundamental theory behind low power and time domain operation, and network/communication protocol considerations.   • Enables detailed understanding of the design space for ultra-low power radio; • Provides detailed discussion and examples of the design of a practical low power ...

  20. Low Power Microrobotics Utilizing Biologically Inspired Energy Generation

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase I study, the study team will investigate the usability of a microbial fuel cell to power a small microrover, design low-power electronics for effective...

  1. Dual Mode Low Power Hall Thruster, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Sample and return missions desire and missions like Saturn Observer require a low power Hall thruster that can operate at high thrust to power as well as high...

  2. Wireless powering for low-power distributed sensors

    Directory of Open Access Journals (Sweden)

    Popović Zoya B.

    2006-01-01

    Full Text Available In this paper, an overview of the field of wireless powering is presented with an emphasis on low-power applications. Several rectenna elements and arrays are discussed in more detail: (1 a 10-GHz array for powering sensors in aircraft wings; (2 a single antenna in the 2.4-GHz ISM band for low-power assisted-living sensors; and (3 a broadband array for power harvesting in the 2-18GHz frequency range.

  3. LSP 156, Low Power Embedded Analytics: FY15 Line Supported Information, Computation, and Exploitation Program

    Science.gov (United States)

    2015-12-04

    group and an industry partner, Quanta Research, with additional support from Xilinx, Samsung , and Intel developed the architecture and prototype...key-value store databases, and the ability to interact with diverse database technologies such as SQL, Accumulo [6] and SciDB. D4M is implemented

  4. Design and implementation of an ultra-low power passive UHF RFID tag

    International Nuclear Information System (INIS)

    Shen Jinpeng; Wang Xin'an; Liu Shan; Zong Hongqiang; Huang Jinfeng; Yang Xin; Feng Xiaoxing; Ge Binjie

    2012-01-01

    This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of −12 dBm. (semiconductor integrated circuits)

  5. A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

    Science.gov (United States)

    Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

    2014-04-01

    This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

  6. Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems

    Science.gov (United States)

    Etxaniz, Josu; Aranguren, Gerardo

    2017-01-01

    Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS) metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks. PMID:28468294

  7. Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems

    Directory of Open Access Journals (Sweden)

    Josu Etxaniz

    2017-04-01

    Full Text Available Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks.

  8. Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems.

    Science.gov (United States)

    Etxaniz, Josu; Aranguren, Gerardo

    2017-04-30

    Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS) metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks.

  9. Video frame processor

    International Nuclear Information System (INIS)

    Joshi, V.M.; Agashe, Alok; Bairi, B.R.

    1993-01-01

    This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

  10. Trigger and decision processors

    International Nuclear Information System (INIS)

    Franke, G.

    1980-11-01

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  11. Optical Finite Element Processor

    Science.gov (United States)

    Casasent, David; Taylor, Bradley K.

    1986-01-01

    A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

  12. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  13. 47 CFR 73.6019 - Digital Class A TV station protection of low power TV, TV translator, digital low power TV and...

    Science.gov (United States)

    2010-10-01

    ... power TV, TV translator, digital low power TV and digital TV translator stations. 73.6019 Section 73... low power TV, TV translator, digital low power TV and digital TV translator stations. An application... A TV station will not be accepted if it fails to protect authorized low power TV, TV translator...

  14. Real-Time Operating Systems for Multicore Embedded Systems

    OpenAIRE

    Tomiyama, Hiroyuki; Honda, Shinya; Takada, Hiroaki

    2008-01-01

    Multicore systems-on-chip have become popular inthe design of embedded systems in order to simultaneously achieve high performance and low power consumption. On the software side, real-time operating systems are necessary in orderto handle growing complexity of embedded software. This paper describes requirements, design principles and implementation techniques for real-time operating systems to be used inasymmetric multicore systems.

  15. Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

    Science.gov (United States)

    Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

    2013-03-01

    With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

  16. The Associative Memory Boards for the FTK Processor at ATLAS

    CERN Document Server

    Calabro, D; The ATLAS collaboration; Citraro, S; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    The Associative Memory (AM) system, the main part of the FastTracker (FTK) processor, is designed to perform pattern matching using the information of the silicon tracking detectors. It finds track candidates at low resolution that are seeds for the following step performing precise track fitting. The system has to support challenging data traffic, handled by a group of modern low cost FPGAs, the Xilinx Spartan6 chips, which have Low-Power Gigabit Transceivers (GTP). Each GTP transceiver is a combined transmitter and receiver capable of operating at data rates up to 3.2 Gb/s. \

  17. Study of methodology for low power/shutdown fire PSA

    International Nuclear Information System (INIS)

    Yan Zhen; Li Zhaohua; Li Lin; Song Lei

    2014-01-01

    As a risk assessment technology based on probability, the fire PSA is accepted abroad by nuclear industry in its application in the risk assessment for nuclear power plants. Based on the industry experience, the fire-induced impact on the plant safety during low power and shutdown operation cannot be neglected, therefore fire PSA can be used to assess the corresponding fire risk. However, there is no corresponding domestic guidance/standard as well as accepted analysis methodology up to date. Through investigating the latest evolvement on fire PSA during low power and shutdown operation, and integrating its characteristic with the corresponding engineering experience, an engineering methodology to evaluate the fire risk during low power and shutdown operation for nuclear power plant is established in this paper. In addition, an analysis demonstration as an example is given. (authors)

  18. Composable Virtual Platforms for Mixed-Criticality Embedded Systems

    NARCIS (Netherlands)

    Beyranvand Nejad, A.

    2014-01-01

    Recent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as

  19. Composable virtual platforms for mixed-criticality embedded systems

    NARCIS (Netherlands)

    Nejad, A.B.

    2014-01-01

    Recent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as

  20. Low Power Systolic Array Based Digital Filter for DSP Applications

    Directory of Open Access Journals (Sweden)

    S. Karthick

    2015-01-01

    Full Text Available Main concepts in DSP include filtering, averaging, modulating, and correlating the signals in digital form to estimate characteristic parameter of a signal into a desirable form. This paper presents a brief concept of low power datapath impact for Digital Signal Processing (DSP based biomedical application. Systolic array based digital filter used in signal processing of electrocardiogram analysis is presented with datapath architectural innovations in low power consumption perspective. Implementation was done with ASIC design methodology using TSMC 65 nm technological library node. The proposed systolic array filter has reduced leakage power up to 8.5% than the existing filter architectures.

  1. Authenticated Encryption for Low-Power Reconfigurable Wireless Devices

    DEFF Research Database (Denmark)

    Khajuria, Samant; Andersen, Birger

    2013-01-01

    this enabling technology, these radios have to propose cryptographic services such as con- fidentiality, integrity and authentication. Therefore, integration of security services to these low-power devices is very challenging and crucial as they have limited resources and computational capabilities....... In this paper, we present a crypto solution for reconfigurable devices. The solution is a single pass Authenticated Encryption (AE) scheme that is designed for protecting both message confidentiality and its authenticity. This makes AE very attractive for low-cost low-power hardware implementation. For test...

  2. Plant operational states analysis in low power and shutdown PSA

    International Nuclear Information System (INIS)

    He Jiandong; Qiu Yongping; Zhang Qinfang; An Hongzhen; Li Maolin

    2013-01-01

    The purpose of Plant Operational States (POS) analysis is to disperse the continuous and dynamic process of low power and shutdown operation, which is the basis of developing event tree models for accident sequence analysis. According to the design of a 300 MW Nuclear Power Plant Project, operating experience and procedures of the reference plant, a detailed POS analysis is carried out based on relative criteria. Then, several kinds of POS are obtained, and the duration of each POS is calculated according to the operation records of the reference plant. The POS analysis is an important element in low power and shutdown PSA. The methodology and contents provide reference for POS analysis. (authors)

  3. Aiding operator performance at low power feedwater control

    International Nuclear Information System (INIS)

    Woods, D.D.

    1986-01-01

    Control of the feedwater system during low power operations (approximately 2% to 30% power) is a difficult task where poor performance (excessive trips) has a high cost to utilities. This paper describes several efforts in the human factors aspects of this task that are underway to improve feedwater control. A variety of knowledge acquisition techniques have been used to understand the details of what makes feedwater control at low power difficult and what knowledge and skill distinguishes expert operators at this task from less experienced ones. The results indicate that there are multiple factors that contribute to task difficulty

  4. Comparison of Preamplifiers for Low-power Consumption Design

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seung Hyun; Kim, Han Soo; Lee, Kyu Hong; Choi, Hyo Jeong; Na, Teresa W.; Ha, Jang Ho [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of); Chai, Jong Seo [Sungkyunkwan University, Suwon (Korea, Republic of)

    2011-10-15

    The commonly used electronic devices in radiation detector system are the preamplifier, the amplifier, ADC, and etc. to extract the signal from the detector and to process the signal. These components are composed of semiconductor devices like BJT, MOSFET, OPAMP, and etc. Performance and power consumption of these components are various according to the composition of semiconductor devices. In this study, preamplifiers, which are composed of high efficiency semiconductor devices, are compared to design low-power consumption and high performance preamplifier. To confirm the purpose, preamplifiers are designed for low-power consumption and high gain by some OPAMP (Operational Amplifier). The comparison was performed by experimental result and design simulation

  5. Performance of Distributed CFAR Processors in Pearson Distributed Clutter

    OpenAIRE

    Messali Zoubeida; Soltani Faouzi

    2007-01-01

    This paper deals with the distributed constant false alarm rate (CFAR) radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA), order statistics (OS), and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S) random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating ...

  6. Low Power system Design techniques for mobile computers

    NARCIS (Netherlands)

    Havinga, Paul J.M.; Smit, Gerardus Johannes Maria

    1997-01-01

    Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: min imizing capacitance, avoiding

  7. Encoded low swing for ultra low power interconnect

    NARCIS (Netherlands)

    Krishnan, R.; Pineda de Gyvez, J.

    2003-01-01

    We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we

  8. Conceptual Study for development of a low power research reactor

    International Nuclear Information System (INIS)

    Park, C.; Kim, H. S.; Park, J. H.; Chae, H. T.; Lee, B. C.

    2013-01-01

    Even though the nuclear society is again facing with difficult situations after Fukusima accident, some countries still continues to consider nuclear power as one option of national energy sources and to introduce nuclear energy. As a research reactor has been regarded as a step-stone to establish infrastructures for the nuclear power development program, some countries that have plan to introduce the nuclear power energy are considering to construct a research reactor. Particularly, a low power research reactor whose main purpose is basic researches on the nuclear technology and education/training would be of interest to developing countries when taking the economy and level of science and technology into consideration. And many low power research reactors at operation are obsolescent and their numbers are decreasing. Hence, some concepts on a low power research reactor are being studied for the future needs. This paper presents the conceptual study on the basic requirements and the preliminary design features of a low power research reactor

  9. Benefits of low-power lasers on oral soft tissue

    Science.gov (United States)

    Eduardo, Carlos d. P.; Cecchini, Silvia C. M.; Cecchini, Renata C.

    1996-04-01

    The last five years have represented a great advance in relation to laser development. Countries like Japan, United States, French, England, Israel and others, have been working on the association of researches and clinical applications, in the field of laser. Low power lasers like He-Ne laser, emitting at 632,8 nm and Ga-As-Al laser, at 790 nm, have been detached acting not only as a coadjutant but some times as an specific treatment. Low power lasers provide non thermal effect at wavelengths believed to stimulate circulation and cellular activity. These lasers have been used to promote wound healing and reduce inflammation edema and pain. This work presents a five year clinical study with good results related to oral tissue healing. Oral cavity lesions, like herpes and aphthous ulcers were irradiated with Ga-Al- As laser. In both cases, an excellent result was obtained. The low power laser application decrease the painful sintomatology immediately and increase the reparation process of these lesions. An excellent result was obtained with application of low power laser in herpetic lesions associated with a secondary infection situated at the lip commissure covering the internal tissue of the mouth. The healing occurred after one week. An association of Ga-Al-As laser and Nd:YAG laser have been also proven to be good therapy for these kind of lesions. This association of low and high power laser has been done since 1992 and it seems to be a complement of the conventional therapies.

  10. Designing Asynchronous Circuits for Low Power: An IFIR Filter

    DEFF Research Database (Denmark)

    Nielsen, Lars Skovby; Sparsø, Jens

    1999-01-01

    This paper addresses the design of asynchronous circuits for low power through an example: a filter bank for a digital hearing aid. The asynchronous design re-implements an existing synchronous circuit which is used in a commercial product. For comparison, both designs have been fabricated...

  11. Analytical models for low-power rectenna design

    NARCIS (Netherlands)

    Akkermans, J.A.G.; Beurden, van M.C.; Doodeman, G.J.N.; Visser, H.J.

    2005-01-01

    The design of a low-cost rectenna for low-power applications is presented. The rectenna is designed with the use of analytical models and closed-form analytical expressions. This allows for a fast design of the rectenna system. To acquire a small-area rectenna, a layered design is proposed.

  12. Application of low power X-ray tubes in geology

    International Nuclear Information System (INIS)

    Massalski, J.M.; Zaraska, W.

    1981-01-01

    Low power X-ray tubes with transmission anodes for X-ray fluorescence analysis with energy dispersion were elaborated. Paper contains experimental results of application of X-ray tubes in the apparatus for nondestructive measurements of the concentration of some elements in borehole cores. (author)

  13. Error Immune Logic for Low-Power Probabilistic Computing

    Directory of Open Access Journals (Sweden)

    Bo Marr

    2010-01-01

    design for the maximum amount of energy savings per a given error rate. Spice simulation results using a commercially available and well-tested 0.25 μm technology are given verifying the ultra-low power, probabilistic full-adder designs. Further, close to 6X energy savings is achieved for a probabilistic full-adder over the deterministic case.

  14. Level shifter for low power applications with body bias technique

    African Journals Online (AJOL)

    user

    In present work three new designs of level shifter in 0.35µm technology using body ... level shifters, namely conventional type-I, conventional type-II and contention mitigated have been improved by varying the ..... single-chip mobile processor.

  15. Distributed processor systems

    International Nuclear Information System (INIS)

    Zacharov, B.

    1976-01-01

    In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)

  16. Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

    Institute of Scientific and Technical Information of China (English)

    Lou Wenfeng; Feng Peng; Wang Haiyong; Wu Nanjian

    2012-01-01

    A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology.The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.

  17. Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

    International Nuclear Information System (INIS)

    Lou Wenfeng; Feng Peng; Wang Haiyong; Wu Nanjian

    2012-01-01

    A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of −193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about −115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than −52 dBc. The whole frequency synthesizer consumes only 4.35 mA and 1.8 V. (semiconductor integrated circuits)

  18. Modern Embedded Computing Designing Connected, Pervasive, Media-Rich Systems

    CERN Document Server

    Barry, Peter

    2012-01-01

    Modern embedded systems are used for connected, media-rich, and highly integrated handheld devices such as mobile phones, digital cameras, and MP3 players. All of these embedded systems require networking, graphic user interfaces, and integration with PCs, as opposed to traditional embedded processors that can perform only limited functions for industrial applications. While most books focus on these controllers, Modern Embedded Computing provides a thorough understanding of the platform architecture of modern embedded computing systems that drive mobile devices. The book offers a comprehen

  19. Hybrid NEMS-CMOS Architectures for Ultra Low Power Smart Systems : Architectures for Ultra Low Power Smart Systems

    NARCIS (Netherlands)

    Enachescu, M.

    2016-01-01

    The availability of inexpensive and powerful processors provides the means for the computation ecosystem to change its fundamental paradigm towards the Internet of Things (IoT) where ubiquitous nanosystems add intelligence to every object that surrounds us. The new trend for most of those systems is

  20. System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor.

    Science.gov (United States)

    Delgado-Restituto, Manuel; Rodriguez-Perez, Alberto; Darie, Angela; Soto-Sanchez, Cristina; Fernandez-Jover, Eduardo; Rodriguez-Vazquez, Angel

    2017-04-01

    This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

  1. Processors and systems (picture processing)

    Energy Technology Data Exchange (ETDEWEB)

    Gemmar, P

    1983-01-01

    Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

  2. Seismometer array station processors

    International Nuclear Information System (INIS)

    Key, F.A.; Lea, T.G.; Douglas, A.

    1977-01-01

    A description is given of the design, construction and initial testing of two types of Seismometer Array Station Processor (SASP), one to work with data stored on magnetic tape in analogue form, the other with data in digital form. The purpose of a SASP is to detect the short period P waves recorded by a UK-type array of 20 seismometers and to edit these on to a a digital library tape or disc. The edited data are then processed to obtain a rough location for the source and to produce seismograms (after optimum processing) for analysis by a seismologist. SASPs are an important component in the scheme for monitoring underground explosions advocated by the UK in the Conference of the Committee on Disarmament. With digital input a SASP can operate at 30 times real time using a linear detection process and at 20 times real time using the log detector of Weichert. Although the log detector is slower, it has the advantage over the linear detector that signals with lower signal-to-noise ratio can be detected and spurious large amplitudes are less likely to produce a detection. It is recommended, therefore, that where possible array data should be recorded in digital form for input to a SASP and that the log detector of Weichert be used. Trial runs show that a SASP is capable of detecting signals down to signal-to-noise ratios of about two with very few false detections, and at mid-continental array sites it should be capable of detecting most, if not all, the signals with magnitude above msub(b) 4.5; the UK argues that, given a suitable network, it is realistic to hope that sources of this magnitude and above can be detected and identified by seismological means alone. (author)

  3. Low-power-laser therapy used in tendon damage

    Science.gov (United States)

    Strupinska, Ewa

    1996-03-01

    The following paper covers evaluation of low-power laser therapy results in chronic Achilles tendon damage and external Epicondylalia (tennis elbow). Fifty patients with Achilles damage (18 women and 32 men, age average 30, 24 plus or minus 10, 39 years) and fifty patients having external Epicondyalgiae (31 women and 19 men, age average 44, 36 plus or minus 10, 88 years) have been examined. The patients were irradiated by semiconductor infrared laser wavelength 904 nm separately or together with helium-neon laser wavelength 632.8 nm. The results of therapy have been based on the patient's interviews and examinations of patients as well as on the Laitinen pain questionnaire. The results prove analgesic effects in usage of low- power laser radiation therapy can be obtained.

  4. Low-power attitude determination for magnetometry planetary missions

    DEFF Research Database (Denmark)

    Christensen, Thorbjørn Helvig

    This work covers the subject of orientation or attitude in space and on the surface of a planet. Different attitude sensor technologies have been investigated with emphasis on very low power consumption and mass. In addition robust methods for attitude determination have been covered again...... with emphasis on the limited budget onboard very small satellites. A true low-power attitude sensor using the Anisotropic Magneto Resistor effect have been designed to late prototype state. Two prototypes of the AMR magnetometer have been built. One of the prototypes has an analog output and the second...... calibration has been performed on both of the prototypes of the AMR magnetometer with very good overall result. Different attitude representations such as orthogonal matrices, Euler angles and quaternions are presented. Also methods for attitude determination of a sensor platform with more than one vector...

  5. Low Power and High Sensitivity MOSFET-Based Pressure Sensor

    International Nuclear Information System (INIS)

    Zhang Zhao-Hua; Ren Tian-Ling; Zhang Yan-Hong; Han Rui-Rui; Liu Li-Tian

    2012-01-01

    Based on the metal-oxide-semiconductor field effect transistor (MOSFET) stress sensitive phenomenon, a low power MOSFET pressure sensor is proposed. Compared with the traditional piezoresistive pressure sensor, the present pressure sensor displays high performances on sensitivity and power consumption. The sensitivity of the MOSFET sensor is raised by 87%, meanwhile the power consumption is decreased by 20%. (cross-disciplinary physics and related areas of science and technology)

  6. Cost-effectiveness of low-power nuclear power plants

    International Nuclear Information System (INIS)

    Mitenkov, F.M.; Vostokov, V.S.; Drozhkin, V.N.; Samoilov, O.B.

    1994-01-01

    Many potential consumers of electricity and heat, consuming several thousands of kilowatts (up to 10-15 MW), have now been identified. This is significant primarily for regions far from power grids and other centralized sources of energy, such as, for example, Yakutiya, Northeastern Siberia, and elsewhere. These consumers are now supplied with fossil fuel, which is often difficult and expensive to deliver. For this reason it is very important to develop low-power nuclear power plants for remote regions

  7. Capacity of Fading Channels in the Low Power Regime

    KAUST Repository

    Benkhelifa, Fatma

    2013-01-01

    The low power regime has attracted various researchers in the information theory and communication communities to understand the performance limits of wireless systems. Indeed, the energy consumption is becoming one of the major limiting factors in wireless systems. As such, energy-efficient wireless systems are of major importance to the next generation wireless systems designers. The capacity is a metric that measures the performance limit of a wireless system. The study of the ergodic capacity of some fading channels in the low power regime is the main subject of this thesis. In our study, we consider that the receiver has always a full knowledge of the channel state information. However, we assume that the transmitter has possibly imperfect knowledge of the channel state information, i.e. he knows either perfectly the channel or only an estimated version of the channel. Both radio frequency and free space optical communication channel models are considered. The main contribution of this work is the explicit characterization of how the capacity scales as function of the signal-to-noise ratio in the low power regime. This allows us to characterize the gain due to the perfect knowledge compared to no knowledge of the channel state information at the transmitter. In particular, we show that the gain increases logarithmically for radio frequency communication. However, the gain increases as log2(Pavg) or log4(Pavg) for free-space optical communication, where Pavg is the average power constraint imposed to the input. Furthermore, we characterize the capacity of cascaded fading channels and we applied the result to Rayleigh-product fading channel and to a free-space optical link over gamma-gamma atmospheric turbulence in the presence of pointing errors. Finally, we study the capacity of Nakagami-m fading channel under quality of service constraints, namely the effective capacity. We have shown that the effective capacity converges to Shannon capacity in the very low

  8. Remarks on building of low-powered airplanes

    Science.gov (United States)

    Langsdorff, Werner V

    1924-01-01

    If the low-powered airplane is to be used advantageously by private individuals, the most important consideration is a smaller fuel consumption and, hence, a lower engine power. From experiments with gliders, it appears entirely possible, by utilizing ascending winds (on the weather side of mountains and those generated by the heat of the sun) and by employing engine flight intermittently, as required to fly long distances over land.

  9. Characteristics of the low power cylindrical anode layer ion source

    International Nuclear Information System (INIS)

    Zhao Jie; Tang Deli; Cheng Changming; Geng Shaofei

    2009-01-01

    A low power cylindrical anode layer ion source and its working characteristic, and the beam distribution are introduced. This ion source has two working states, emanative state and collimated state, and the normal parameters of this system are: working voltage 200-1200 V, discharge current 0.1-1.4A, air pressure 1.9 x 10 -2 -1.7 x 10 -1 Pa, gas flow 5-20 sccm. (authors)

  10. An Electronic System for Ultra-low Power Hearing Implants

    Science.gov (United States)

    2013-02-15

    Battery Charger Circuit ," IEEE Transactions on Biomedical Circuits and Systems, Vol. 5, No.2, pp. 131-137,2011. [6] K. H. Wee, L. Turicchia, and R...analyzers [1], [2], useful in several hearing systems. 4) We have designed and built a lithium-ion battery -recharging circuit that exploits a novel analog...lab and the use of intelligent low-power filters and circuits have been successful in reducing noise exposure while improving speech intelligibility

  11. Ultra low power signal oriented approach for wireless health monitoring.

    Science.gov (United States)

    Marinkovic, Stevan; Popovici, Emanuel

    2012-01-01

    In recent years there is growing pressure on the medical sector to reduce costs while maintaining or even improving the quality of care. A potential solution to this problem is real time and/or remote patient monitoring by using mobile devices. To achieve this, medical sensors with wireless communication, computational and energy harvesting capabilities are networked on, or in, the human body forming what is commonly called a Wireless Body Area Network (WBAN). We present the implementation of a novel Wake Up Receiver (WUR) in the context of standardised wireless protocols, in a signal-oriented WBAN environment and present a novel protocol intended for wireless health monitoring (WhMAC). WhMAC is a TDMA-based protocol with very low power consumption. It utilises WBAN-specific features and a novel ultra low power wake up receiver technology, to achieve flexible and at the same time very low power wireless data transfer of physiological signals. As the main application is in the medical domain, or personal health monitoring, the protocol caters for different types of medical sensors. We define four sensor modes, in which the sensors can transmit data, depending on the sensor type and emergency level. A full power dissipation model is provided for the protocol, with individual hardware and application parameters. Finally, an example application shows the reduction in the power consumption for different data monitoring scenarios.

  12. Simulation and Embedded Smart Control

    DEFF Research Database (Denmark)

    Conrad, Finn; Fan, Zhun; Sørensen, Torben

    2006-01-01

    The paper presents results obtained from a Danish mechatronic research program focusing on intelligent motion control, simulation and embedded smart controllers for hydraulic actuators and robots as well as results from the EU projects. A mechatronic test facility with digital controllers...... for a hydraulic robot was implemented. The controllers apply digital signal processors (DSPs), and Field Programmable Gate Array, short named as FPGA, respectively. The DSP controller utilizes the dSPACE System that is suitable for real-time experimentation, evaluation and validation of control laws...... and algorithms. Furthermore, a developed IT-tool concept for controller and system design utilizing the ISO 10303 STEP Standard is proposed....

  13. Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

    Directory of Open Access Journals (Sweden)

    Oscar Montiel-Ross

    2012-01-01

    Full Text Available This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

  14. Embedded defects

    International Nuclear Information System (INIS)

    Barriola, M.; Vachaspati, T.; Bucher, M.

    1994-01-01

    We give a prescription for embedding classical solutions and, in particular, topological defects in field theories which are invariant under symmetry groups that are not necessarily simple. After providing examples of embedded defects in field theories based on simple groups, we consider the electroweak model and show that it contains the Z string and a one-parameter family of strings called the W(α) string. It is argued that although the members of this family are gauge equivalent when considered in isolation, each member becomes physically distinct when multistring configurations are considered. We then turn to the issue of stability of embedded defects and demonstrate the instability of a large class of such solutions in the absence of bound states or condensates. The Z string is shown to be unstable for all values of the Higgs boson mass when θ W =π/4. W strings are also shown to be unstable for a large range of parameters. Embedded monopoles suffer from the Brandt-Neri-Coleman instability. Finally, we connect the electroweak string solutions to the sphaleron

  15. 47 CFR 74.710 - Digital low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.710 Digital low power TV and TV translator station protection. (a) An application to construct a new low power TV, TV translator, or TV...

  16. 47 CFR 74.795 - Digital low power TV and TV translator transmission system facilities.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.795 Digital low power TV and TV translator transmission system facilities. (a) A digital low power TV or TV translator station shall operate...

  17. 47 CFR 74.792 - Digital low power TV and TV translator station protected contour.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.792 Digital low power TV and TV translator station protected contour. (a) A digital low power TV or TV translator will be protected from...

  18. 47 CFR 74.707 - Low power TV and TV translator station protection.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV and TV translator station... SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.707 Low power TV and TV translator station protection. (a)(1) A low power TV or TV translator will be protected from interference from other...

  19. Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors

    OpenAIRE

    Catalán, Sandra; Igual, Francisco D.; Mayo, Rafael; Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

    2015-01-01

    Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications. In this paper, we design and embed several architecture-aware ...

  20. Embedded systems design with special arithmetic and number systems

    CERN Document Server

    Sousa, Leonel; Chang, Chip-Hong

    2017-01-01

    This book introduces readers to alternative approaches to designing efficient embedded systems using unconventional number systems. The authors describe various systems that can be used for designing efficient embedded and application-specific processors, such as Residue Number System, Logarithmic Number System, Redundant Binary Number System Double-Base Number System, Decimal Floating Point Number System and Continuous Valued Number System. Readers will learn the strategies and trade-offs of using unconventional number systems in application-specific processors and be able to apply and design appropriate arithmetic operations from these number systems to boost the performance of digital systems. • Serves as a single-source reference to designing embedded systems with unconventional number systems • Covers theory as well as implementation on application-specific processors • Explains mathematical concepts in a manner accessible to readers with diverse backgrounds.

  1. Circuits and Systems for Low-Power Miniaturized Wireless Sensors

    Science.gov (United States)

    Nagaraju, Manohar

    The field of electronic sensors has witnessed a tremendous growth over the last decade particularly with the proliferation of mobile devices. New applications in Internet of Things (IoT), wearable technology, are further expected to fuel the demand for sensors from current numbers in the range of billions to trillions in the next decade. The main challenges for a trillion sensors are continued miniaturization, low-cost and large-scale manufacturing process, and low power consumption. Traditional integration and circuit design techniques in sensor systems are not suitable for applications in smart dust, IoT etc. The first part of this thesis demonstrates an example sensor system for biosignal recording and illustrates the tradeoffs in the design of low-power miniaturized sensors. The different components of the sensor system are integrated at the board level. The second part of the thesis demonstrates fully integrated sensors that enable extreme miniaturization of a sensing system with the sensor element, processing circuitry, a frequency reference for communication and the communication circuitry in a single hermetically sealed die. Design techniques to reduce the power consumption of the sensor interface circuitry at the architecture and circuit level are demonstrated. The principles are used to design sensors for two of the most common physical variables, mass and pressure. A low-power wireless mass and pressure sensor suitable for a wide variety of biological/chemical sensing applications and Tire Pressure Monitoring Systems (TPMS) respectively are demonstrated. Further, the idea of using high-Q resonators for a Voltage Controlled Oscillator (VCO) is proposed and a low-noise, wide bandwidth FBAR-based VCO is presented.

  2. Assessment of nuclear reactor concepts for low power space applications

    Science.gov (United States)

    Klein, Andrew C.; Gedeon, Stephen R.; Morey, Dennis C.

    1988-01-01

    The results of a preliminary small reactor concepts feasibility and safety evaluation designed to provide a first order validation of the nuclear feasibility and safety of six small reactor concepts are given. These small reactor concepts have potential space applications for missions in the 1 to 20 kWe power output range. It was concluded that low power concepts are available from the U.S. nuclear industry that have the potential for meeting both the operational and launch safety space mission requirements. However, each design has its uncertainties, and further work is required. The reactor concepts must be mated to a power conversion technology that can offer safe and reliable operation.

  3. EXPERIMENTAL INVESTIGATION OF AN AIR CHARGED LOW POWERED STIRLING ENGINE

    Directory of Open Access Journals (Sweden)

    Can ÇINAR

    2004-01-01

    Full Text Available In this study, an air charged, low powered manufactured ? type Stirling engine was investigated experimentally. Tests were conducted at 800, 900 and 1000 °C hot source temperatures, 1, 1.5, 2, 2.5, 3, 3.5 bars air charge pressure. The variation of engine power depending on the charge pressure and hot source temperature for two different heat transfer area was investigated experimentally. Maximum output power was obtained at 1000 °C and 3 bars charge pressure as 58 W at 441 rpm. Engine speed was reached at 846 rpm without load.

  4. Extreme low-power mixed signal IC design

    CERN Document Server

    Tajalli, Armin

    2010-01-01

    This book describes a completely novel class of techniques for designing ultra-low-power integrated circuits (ICs). In many applications such as battery operated systems and battery-less (energy-scavenging) systems, power dissipation is a critical parameter. As a result, there is a growing demand for reducing the power (energy) consumption in ICs to extremely low levels, not achievable by using classical ""subthreshold CMOS"" techniques. This book introduces a new family of ""subthreshold circuits"" called ""source-coupled circuits"". This family of circuits can be used for implementing digita

  5. Ultra-low-power short-range radios

    CERN Document Server

    Chandrakasan, Anantha

    2015-01-01

    This book explores the design of ultra-low-power radio-frequency integrated circuits (RFICs), with communication distances ranging from a few centimeters to a few meters. Such radios have unique challenges compared to longer-range, higher-powered systems. As a result, many different applications are covered, ranging from body-area networks to transcutaneous implant communications and Internet-of-Things devices. A mix of introductory and cutting-edge design techniques and architectures which facilitate each of these applications are discussed in detail. Specifically, this book covers:.

  6. Low-power signal processing devices for portable ECG detection.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Cheng, Chih-Jen; Wang, Cheng-Pin; Kao, Wei-Chun

    2008-01-01

    An analog front end for diagnosing and monitoring the behavior of the heart is presented. This sensing front end has two low-power processing devices, including a 5(th)-order Butterworth operational transconductance-C (OTA-C) filter and an 8-bit successive approximation analog-to-digital converter (SAADC). The components fabricated in a 0.18-microm CMOS technology feature with power consumptions of 453 nW (filter) and 940 nW (ADC) at a supply voltage of 1 V, respectively. The system specifications in terms of output noise and linearity associated with the two integrated circuits are described in this paper.

  7. Standard filter approximations for low power Continuous Wavelet Transforms.

    Science.gov (United States)

    Casson, Alexander J; Rodriguez-Villegas, Esther

    2010-01-01

    Analogue domain implementations of the Continuous Wavelet Transform (CWT) have proved popular in recent years as they can be implemented at very low power consumption levels. This is essential for use in wearable, long term physiological monitoring systems. Present analogue CWT implementations rely on taking mathematical a approximation of the wanted mother wavelet function to give a filter transfer function that is suitable for circuit implementation. This paper investigates the use of standard filter approximations (Butterworth, Chebyshev, Bessel) as an alternative wavelet approximation technique. This extends the number of approximation techniques available for generating analogue CWT filters. An example ECG analysis shows that signal information can be successfully extracted using these CWT approximations.

  8. A low power ADS for transmutation studies in fast systems

    Science.gov (United States)

    Panza, Fabio; Firpo, Gabriele; Lomonaco, Guglielmo; Osipenko, Mikhail; Ricco, Giovanni; Ripani, Marco; Saracco, Paolo; Viberti, Carlo Maria

    2017-12-01

    In this work, we report studies on a fast low power accelerator driven system model as a possible experimental facility, focusing on its capabilities in terms of measurement of relevant integral nuclear quantities. In particular, we performed Monte Carlo simulations of minor actinides and fission products irradiation and estimated the fission rate within fission chambers in the reactor core and the reflector, in order to evaluate the transmutation rates and the measurement sensitivity. We also performed a photo-peak analysis of available experimental data from a research reactor, in order to estimate the expected sensitivity of this analysis method on the irradiation of samples in the ADS considered.

  9. Speed of sound in biodiesel produced by low power ultrasound

    Science.gov (United States)

    Oliveira, P. A.; Silva, R. M. B.; Morais, G. C.; Alvarenga, A. V.; Costa-Felix, R. P. B.

    2018-03-01

    The quality control of the biodiesel produced is an important issue to be addressed for every manufacturer or retailer. The speed of sound is a property that has an influence on the quality of the produced fuel. This work presents the evaluation about the speed of sound in biodiesel produced with the aid of low power ultrasound in the frequencies of 1 MHz and 3 MHz. The speed of sound was measured by pulse-echo technique. The ultrasonic frequency used during reaction affects the speed of sound in biodiesel. The larger expanded uncertainty for adjusted curve was 4.9 m.s-1.

  10. LOW-POWER AC LOADS AND ELECTRICAL POWER QUALITY

    Directory of Open Access Journals (Sweden)

    EPURE S.

    2016-12-01

    Full Text Available This paper deals with experimental study and numerical simulation of single phase AC low power loads: artificial light sources, personal computers, refrigeration units, air conditioning units and TV receivers. These loads are in such large numbers that represents the main source of disturbances (harmonic current, reactive power and unbalanced three-phase network. The obtained simulation models, verified by comparison with experimental results may be used in larger simulation models for testing and sizing the optimum parameters of active power filters. Models can also be used to study the interactions between grid elements and various loads or situations.

  11. XL-100S microprogrammable processor

    International Nuclear Information System (INIS)

    Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

    1983-01-01

    The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

  12. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  13. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  14. PCB Embedded Inductor for High-Frequency ZVS SEPIC Converter

    DEFF Research Database (Denmark)

    Dou, Yi; Ouyang, Ziwei; Thummala, Prasanth

    2018-01-01

    The volume and temperature rise of passive components, especially inductors, limit the momentum toward high power density in high-frequency power converters. To address the limitations, PCB integration of passive components should be considered with the benefit of low profile, excellent thermal...... characteristic and cost reduction. This paper investigates an embedded structure of inductors to further increase the power density of a low power DC-DC converter. A pair of coupling inductors have been embedded into the PCB. The detailed embedded process has been described and the characteristics of embedded...

  15. Optical Array Processor: Laboratory Results

    Science.gov (United States)

    Casasent, David; Jackson, James; Vaerewyck, Gerard

    1987-01-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

  16. Fast processor for dilepton triggers

    International Nuclear Information System (INIS)

    Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

    1983-01-01

    We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

  17. Random Sequence for Optimal Low-Power Laser Generated Ultrasound

    Science.gov (United States)

    Vangi, D.; Virga, A.; Gulino, M. S.

    2017-08-01

    Low-power laser generated ultrasounds are lately gaining importance in the research world, thanks to the possibility of investigating a mechanical component structural integrity through a non-contact and Non-Destructive Testing (NDT) procedure. The ultrasounds are, however, very low in amplitude, making it necessary to use pre-processing and post-processing operations on the signals to detect them. The cross-correlation technique is used in this work, meaning that a random signal must be used as laser input. For this purpose, a highly random and simple-to-create code called T sequence, capable of enhancing the ultrasound detectability, is introduced (not previously available at the state of the art). Several important parameters which characterize the T sequence can influence the process: the number of pulses Npulses , the pulse duration δ and the distance between pulses dpulses . A Finite Element FE model of a 3 mm steel disk has been initially developed to analytically study the longitudinal ultrasound generation mechanism and the obtainable outputs. Later, experimental tests have shown that the T sequence is highly flexible for ultrasound detection purposes, making it optimal to use high Npulses and δ but low dpulses . In the end, apart from describing all phenomena that arise in the low-power laser generation process, the results of this study are also important for setting up an effective NDT procedure using this technology.

  18. Low-power cryptographic coprocessor for autonomous wireless sensor networks

    Science.gov (United States)

    Olszyna, Jakub; Winiecki, Wiesław

    2013-10-01

    The concept of autonomous wireless sensor networks involves energy harvesting, as well as effective management of system resources. Public-key cryptography (PKC) offers the advantage of elegant key agreement schemes with which a secret key can be securely established over unsecure channels. In addition to solving the key management problem, the other major application of PKC is digital signatures, with which non-repudiation of messages exchanges can be achieved. The motivation for studying low-power and area efficient modular arithmetic algorithms comes from enabling public-key security for low-power devices that can perform under constrained environment like autonomous wireless sensor networks. This paper presents a cryptographic coprocessor tailored to the autonomous wireless sensor networks constraints. Such hardware circuit is aimed to support the implementation of different public-key cryptosystems based on modular arithmetic in GF(p) and GF(2m). Key components of the coprocessor are described as GEZEL models and can be easily transformed to VHDL and implemented in hardware.

  19. Wake-up receiver based ultra-low-power WBAN

    CERN Document Server

    Lont, Maarten; Roermund, Arthur van

    2014-01-01

    This book presents the cross-layer design and optimization of wake-up receivers for wireless body area networks (WBAN), with an emphasis on low-power circuit design. This includes the analysis of medium access control (MAC) protocols, mixer-first receiver design, and implications of receiver impairments on wideband frequency-shift-keying (FSK) receivers. Readers will learn how the overall power consumption is reduced by exploiting the characteristics of body area networks. Theoretical models presented are validated with two different receiver implementations, in 90nm and 40nm CMOS technology.   • Provides an overview of wireless body area network design from the network layer to the circuit implementation, and an overview of the cross-layer design trade-offs; • Discusses design at both the network or MAC-layer and circuit-level, with an emphasis on circuit design; • Covers the design of low-power frequency shift keying (FSK) wake-up-receivers; • Validates theory presented with two different recei...

  20. A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

    Directory of Open Access Journals (Sweden)

    Hiroki Iwaizumi

    2013-01-01

    Full Text Available A processor design for singular value decomposition (SVD and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs and arithmetic instructions specialized in complex matrix operations.

  1. Performance of Distributed CFAR Processors in Pearson Distributed Clutter

    Directory of Open Access Journals (Sweden)

    Messali Zoubeida

    2007-01-01

    Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the "OR" fusion rule.

  2. Performance of Distributed CFAR Processors in Pearson Distributed Clutter

    Directory of Open Access Journals (Sweden)

    Faouzi Soltani

    2007-01-01

    Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the “OR” fusion rule.

  3. Tools for Embedded Computing Systems Software

    Science.gov (United States)

    1978-01-01

    A workshop was held to assess the state of tools for embedded systems software and to determine directions for tool development. A synopsis of the talk and the key figures of each workshop presentation, together with chairmen summaries, are presented. The presentations covered four major areas: (1) tools and the software environment (development and testing); (2) tools and software requirements, design, and specification; (3) tools and language processors; and (4) tools and verification and validation (analysis and testing). The utility and contribution of existing tools and research results for the development and testing of embedded computing systems software are described and assessed.

  4. Scheduling Driven Partitioning of Heterogeneous Embedded Systems

    DEFF Research Database (Denmark)

    Pop, Paul; Eles, Petru; Peng, Zebo

    1998-01-01

    In this paper we present an algorithm for system level hardware/software partitioning of heterogeneous embedded systems. The system is represented as an abstract graph which captures both data-flow and the flow of control. Given an architecture consisting of several processors, ASICs and shared...... busses, our partitioning algorithm finds the partitioning with the smallest hardware cost and is able to predict and guarantee the performance of the system in terms of worst case delay....

  5. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

  6. Biophysical basis of low-power-laser effects

    Science.gov (United States)

    Karu, Tiina I.

    1996-06-01

    Biological responses of cells to visible and near IR (laser) radiation occur due to physical and/or chemical changes in photoacceptor molecules, components of respiratory chains (cyt a/a3 in mitochondria). As a result of the photoexcitation of electronic states, the following physical and/or chemical changes can occur: alteration of redox properties and acceleration of electron transfer, changes in biochemical activity due to local transient heating of chromophores, one-electron auto-oxidation and O2- production, and photodynamic action and 1O2 production. Different reaction channels can be activated to achieve the photobiological macroeffect. The primary physical and/or chemical changes induced by light in photoacceptor molecules are followed by a cascade of biochemical reactions in the cell that do not need further light activation and occur in the dark (photosignal transduction and amplification chains). These actions are connected with changes in cellular homeostasis parameters. The crucial step here is thought to be an alteration of the cellular redox state: a shift towards oxidation is associated with stimulation of cellular vitality, and a shift towards reduction is linked to inhibition. Cells with a lower than normal pH, where the redox state is shifted in the reduced direction, are considered to be more sensitive to the stimulative action of light than those with the respective parameters being optimal or near optimal. This circumstance explains the possible variations in observed magnitudes of low-power laser effects. Light action on the redox state of a cell via the respiratory chain also explains the diversity of low-power laser effects. Beside explaining many controversies in the field of low-power laser effects (i.e., the diversity of effects, the variable magnitude or absence of effects in certain studies), the proposed redox-regulation mechanism may be a fundamental explanation for some clinical effects of irradiation, for example the positive

  7. [Low power laser biostimulation in the treatment of bronchial asthma].

    Science.gov (United States)

    Milojević, Momir; Kuruc, Vesna

    2003-01-01

    Modern concept of acupuncture is based on the fact there are designated locations on the surface of human body, which are related to integrative systems of an organism by means of sensory nerves, correlating and synchronizing organ functioning, depending on external and internal conditions, by means of nervous and neurohumoral regulation of metabolic and regenerative processes, including also mobilisation of immunological, protective and antistress reactions. Apart from standard needle acupuncture, other methods of stimulating acupuncture points are also applied. Due to invention of low power lasers, irradiation laser acupuncture has been introduced into routine medical practice, characterised by painless and aseptic technique and outstanding clinical results. The investigation was aimed at defining therapeutic effects of low power laser irradiation by stimulating acupuncture points or local treatment of asthma. A prospective analysis included 50 patients treated at the Institute of Pulmonary Diseases in Sremska Kamenica during 2000, 2001 and 2002. Together with conservative treatment of present disease, these patients were treated with laser stimulation of acupuncture points in duration of ten days. During treatment changes of functional respiratory parameters were recorded. Results were compared with those in the control group. The control group consisted of the same number of patients and differed from the examination group only by not using laser stimulation. Patients with bronchial asthma presented with significant improvement (p lower frequency and intensity of attacks. The mechanism of laser stimulation activity in treatment of bronchial asthma is explained in detail, correlating our results to those obtained by other authors. A ten-day course of low-power laser stimulation of acupuncture points in patients with bronchial asthma improves both the lung function and gas exchange parameters. Positive effects of laser treatment in patients with bronchial asthma

  8. Low-power FLC-based retromodulator communications system

    Science.gov (United States)

    Swenson, Charles M.; Steed, Clark A.; de La Rue, Imelda A.; Fugate, Robert Q.

    1997-05-01

    On September 15, 1996, researchers from Utah State University/Space Dynamics Lab in conjunction with Phillips Lab/Starfire Optical Range and Kjome Research successfully flew and tested a retromodulator laser communication package on a high altitude balloon. This paper addresses the layout and hardware used for the communication link, as well as presenting some preliminary data collected during the 6 hour flight of the balloon. The package was a proof of concept demonstration system for a low-power laser communications systems for small, low Earth orbiting satellites. The ferroelectric liquid crystal based retromodulator design of Utah State provided test patterns for modulation rates up to 20 kilo bits per second. Data was successfully downlinked using a 1200 bps RS232 format and a simplistic receiver. The Starfire Optical Range 1.5-meter telescope located on Kirtland AFB, tracked the balloon, which reached a float altitude of 31 km and collected the modulated light reflected from the payload.

  9. A low-power wave union TDC implemented in FPGA

    International Nuclear Information System (INIS)

    Wu, Jinyuan; Shi, Yanchen; Zhu, Douglas

    2011-01-01

    A low-power time-to-digital convertor (TDC) for an application inside a vacuum has been implemented based on the Wave Union TDC scheme in a low-cost field programmable gate array (FPGA) device. Bench top tests have shown that a time measurement resolution better than 30 ps (standard deviation of time differences between two channels) is achieved. Special firmware design practices are taken to reduce power consumption. The measurements indicate that with 32 channels fitting in the FPGA device, the power consumption on the FPGA core voltage is approximately 9.3 mW/channel and the total power consumption including both core and I/O banks is less than 27 mW/channel.

  10. Sub-10ps monolithic and low-power photodetector readout

    International Nuclear Information System (INIS)

    Varner, Gary S.; Ruckman, Larry L.

    2009-01-01

    Recent advances in photon detectors have resulted in high-density imaging arrays that offer many performance and cost advantages. In particular, the excellent transit time spread of certain devices show promise to provide tangible benefits in applications such as Positron Emission Tomography (PET). Meanwhile, high-density, high-performance readout techniques have not kept on pace for exploiting these developments. Photodetector readout for next generation high event rate particle identification and time-resolved PET requires a highly-integrated, low-power, and cost-effective readout technique. We propose fast waveform sampling as a method that meets these criteria and demonstrate that sub-10ps resolution can be obtained for an existing device

  11. Energy scavenging sensors for ultra-low power sensor networks

    Science.gov (United States)

    O'Brien, Dominic C.; Liu, Jing Jing; Faulkner, Grahame E.; Vachiramon, Pithawat; Collins, Steve; Elston, Steven J.

    2010-08-01

    The 'internet of things' will require very low power wireless communications, preferably using sensors that scavenge power from their environment. Free space optics allows communications over long ranges, with simple transceivers at each end, offering the possibility of low energy consumption. In addition there can be sufficient energy in the communications beam to power simple terminals. In this paper we report experimental results from an architecture that achieves this. A base station that tracks sensors in its coverage area and communicates with them using low divergence optical beams is presented. Sensor nodes use modulated retro-reflectors to communicate with the base station, and the nodes are powered by the illuminating beam. The paper presents design and implementation details, as well as future directions for this work.

  12. New reactor safety circuit for low-power-level operation

    International Nuclear Information System (INIS)

    McDowell, W.P.; Keefe, D.J.; Rusch, G.K.

    1978-01-01

    In the operation of nuclear reactors at low-power levels, one of the primary instrumentation problems is that the statistical fluctuations of reactor neutron population are accentuated by conventional log-count-rate and differentiating circuits and can cause frequent spurious scrams unless long time constants are incorporated in the circuit. Excessive time constants may introduce undesirable delay in the circuit response to legitimate scram signals. The paper develops the concept of a count doubling-time monitor which generates a scram signal if the number of counts from a pulse type neutron detector doubles in a given period of time. The paper demonstrates the theoretical relation between count doubling time and asymptomatic periods. A practical circuit to implement the function is described

  13. Low-power adaptive filter based on RNS components

    DEFF Research Database (Denmark)

    Bernocchi, Gian Luca; Cardarilli, Gian Carlo; Del Re, Andrea

    2007-01-01

    In this paper a low-power implementation of an adaptive FIR filter is presented. The filter is designed to meet the constraints of channel equalization for fixed wireless communications that typically requires a large number of taps, but a serial updating of the filter coefficients, based...... on the least mean squares (LMS) algorithm, is allowed. Previous work showed that the use of the residue number system (RNS) for the variable FIR filter grants advantages both in area and power consumption. On the other hand, the use of a binary serial implementation of the adaptation algorithm eliminates...... the need for complex scaling circuits in RNS. The advantages in terms of area and speed of the presented filter, with respect to its two's complement counterpart, are evaluated for implementations in standard cells....

  14. Low power consumption and high temperature durability for radiation sensor

    International Nuclear Information System (INIS)

    Matsumoto, Yoshinori; Ueno, Hiroto

    2015-01-01

    Low power consumption and high temperature operation are important in an environmental monitoring system. The power consumption of 3 mW is achieved for the radiation sensor using low voltage operational amplifier and comparator in the signal processing circuit. The leakage reverse current of photodiode causes the charge amplifier saturation over 50degC. High temperature durability was improved by optimizing the circuit configuration and the values of feedback resistance and capacitance in the charge amplifier. The pulse response of the radiation sensor was measured up to 55degC. The custom detection circuit was designed by 0.6 μm CMOS process at 5-V supply voltage. The operation temperature was improved up to 65degC. (author)

  15. Flight experience with lightweight, low-power miniaturized instrumentation systems

    Science.gov (United States)

    Hamory, Philip J.; Murray, James E.

    1992-01-01

    Engineers at the NASA Dryden Flight Research Facility (NASA-Dryden) have conducted two flight research programs with lightweight, low-power miniaturized instrumentation systems built around commercial data loggers. One program quantified the performance of a radio-controlled model airplane. The other program was a laminar boundary-layer transition experiment on a manned sailplane. The purpose of this paper is to report NASA-Dryden personnel's flight experience with the miniaturized instrumentation systems used on these two programs. The paper will describe the data loggers, the sensors, and the hardware and software developed to complete the systems. The paper also describes how the systems were used and covers the challenges encountered to make them work. Examples of raw data and derived results will be shown as well. Finally, future plans for these systems will be discussed.

  16. Low Power Measurements on a Finger Drift Tube Linac

    CERN Document Server

    Schempp, A

    2004-01-01

    The efficiency of RFQs decreases at higher particle energies. The DTL structures used in this energy regions have a defocusing influence on the beam. To achieve a focusing effect, fingers with quadrupole symmetry were added to the drift tubes. Driven by the same power supply as the drift tubes, the fingers do not need an additional power source or feedthrough. Beam dynamics have been studied with PARMTEQ . Detailed analysis of the field distribution was done and the geometry of the finger array has been optimized with respect to beam dynamics. A spiral loaded cavity with finger drift tubes was built up and low power measurements were done. In this contribution, the results of the rf simulating with Microwave Studio are shown in comparison with bead pertubation measurement on a prototype cavity.

  17. Smartphone-Driven Low-Power Light-Emitting Device

    Directory of Open Access Journals (Sweden)

    Hea-Ja An

    2017-01-01

    Full Text Available Low-level light (laser therapy (LLLT has been widely researched in the recent past. Existing LLLT studies were performed based on laser. Recently, studies using LED have increased. This study presents a smartphone-driven low-power light-emitting device for use in colour therapy as an alternative medicine. The device consists of a control unit and a colour probe. The device is powered by and communicates with a smartphone using USB On-The-Go (OTG technology. The control unit controls emitting time and intensity of illumination with the configuration value of a smartphone application. Intensity is controlled by pulse width modulation (PWM without feedback. A calibration is performed to resolve a drawback of no feedback. To calibrate, intensity is measured in every 10 percent PWM output. PWM value is linearly calibrated to obtain accurate intensity. The device can control the intensity of illumination, and so, it can find application in varied scenarios.

  18. Review of mixer design for low voltage - low power applications

    Science.gov (United States)

    Nurulain, D.; Musa, F. A. S.; Isa, M. Mohamad; Ahmad, N.; Kasjoo, S. R.

    2017-09-01

    A mixer is used in almost all radio frequency (RF) or microwave systems for frequency translation. Nowadays, the increase market demand encouraged the industry to deliver circuit designs to create proficient and convenient equipment with very low power (LP) consumption and low voltage (LV) supply in both digital and analogue circuits. This paper focused on different Complementary Metal Oxide Semiconductor (CMOS) design topologies for LV and LP mixer design. Floating Gate Metal Oxide Semiconductor (FGMOS) is an alternative technology to replace CMOS due to their high ability for LV and LP applications. FGMOS only required a few transistors per gate and can have a shift in threshold voltage (VTH) to increase the LP and LV performances as compared to CMOS, which makes an attractive option to replace CMOS.

  19. Experimental study of rectenna coupling at low power level

    International Nuclear Information System (INIS)

    Douyère, A; Alicalapa, F; Lan Sun Luk, J-D; Rivière, S

    2013-01-01

    The experimental results presented in this paper focus on the performance of a rectenna array by studying the effect of mutual coupling between two rectennas. The measurements in several planes of the space are investigated and used to help us to define the minimum distance for future rectenna arrays that can be used at a low power density level. The single element chosen for the array is composed of a rectifier circuit and a CSPA (Circular Slot Patch Antenna). This study shows that at a distance greater than 6cm (λ/2) between two rectennas in reception, we observe that the DC received voltage is constant in the Y plane, while in the X plane, the DC received voltage remains constant whatever the distance. We deduce that these rectennas are uncoupled in this case. We can consider each rectenna like an independent system.

  20. Optimization of passive low power wireless electromagnetic energy harvesters.

    Science.gov (United States)

    Nimo, Antwi; Grgić, Dario; Reindl, Leonhard M

    2012-10-11

    This work presents the optimization of antenna captured low power radio frequency (RF) to direct current (DC) power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor) resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at -30 dBm antenna input power. Additionally, a wireless harvester (rectenna) is built and tested for receiving range performance.

  1. A low power 12-bit ADC for nuclear instrumentation

    International Nuclear Information System (INIS)

    Adachi, R.; Landis, D.; Madden, N.; Silver, E.; LeGros, M.

    1992-10-01

    A low power, successive approximation, analog-to-digital converter (ADC) for low rate, low cost, battery powered applications is described. The ADC is based on a commercial 50 mW successive approximation CMOS device (CS5102). An on-chip self-calibration circuit reduces the inherent differential nonlinearity to 7%. A further reduction of the differential nonlinearity to 0.5% is attained with a four bit Gatti function. The Gatti function is distributed to minimize battery power consumption. All analog functions reside with the ADC while the noisy digital functions reside in the personal computer based histogramming memory. Fiber optic cables carry afl digital information between the ADC and the personal computer based histogramming memory

  2. Recent advances in flexible low power cholesteric LCDs

    Science.gov (United States)

    Khan, Asad; Shiyanovskaya, Irina; Montbach, Erica; Schneider, Tod; Nicholson, Forrest; Miller, Nick; Marhefka, Duane; Ernst, Todd; Doane, J. W.

    2006-05-01

    Bistable reflective cholesteric displays are a liquid crystal display technology developed to fill a market need for very low power displays. Their unique look, high reflectivity, bistability, and simple structure make them an ideal flat panel display choice for handheld or other portable devices where small lightweight batteries with long lifetimes are important. Applications ranging from low resolution large signs to ultra high resolution electronic books can utilize cholesteric displays to not only benefit from the numerous features, but also create enabling features that other flat panel display technologies cannot. Flexible displays are the focus of attention of numerous research groups and corporations worldwide. Cholesteric displays have been demonstrated to be highly amenable to flexible substrates. This paper will review recent advances in flexible cholesteric displays including both phase separation and emulsification approaches to encapsulation. Both approaches provide unique benefits to various aspects of manufacturability, processes, flexibility, and conformability.

  3. A low-power CMOS frequency synthesizer for GPS receivers

    International Nuclear Information System (INIS)

    Yu Yunfeng; Xiao Shimao; Zhuang Haixiao; Ma Chengyan; Ye Tianchun; Yue Jianlian

    2010-01-01

    A low-power frequency synthesizer for GPS/Galileo L1/E1 band receivers implemented in a 0.18 μm CMOS process is introduced. By adding clock-controlled transistors at latch outputs to reduce the time constant at sensing time, the working frequency of the high-speed source-coupled logic prescaler supplying quadrature local oscillator signals has been increased, compared with traditional prescalers. Measurement results show that this synthesizer achieves an in-band phase noise of -87 dBc/Hz at 15 kHz offset, with spurs less than -65 dBc. The whole synthesizer consumes 6 mA in the case of a 1.8 V supply, and its core area is 0.6 mm 2 . (semiconductor integrated circuits)

  4. Low power cw-laser signatures on human skin

    International Nuclear Information System (INIS)

    Lihachev, A; Lesinsh, J; Jakovels, D; Spigulis, J

    2011-01-01

    Impact of cw laser radiation on autofluorescence features of human skin is studied. Two methods of autofluorescence detection are applied: the spectral method with the use of a fibreoptic probe and spectrometer for determining the autofluorescence recovery kinetics at a fixed skin area of ∼12 mm 2 , and the multispectral visualisation method with the use of a multispectral imaging camera for visualising long-term autofluorescence changes in a skin area of ∼4 cm 2 . The autofluorescence recovery kinetics after preliminary laser irradiation is determined. Skin autofluorescence images with visible long-term changes - 'signatures' of low power laser treatment are acquired. (application of lasers and laser-optical methods in life sciences)

  5. Sub-10ps monolithic and low-power photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Varner, Gary S.; Ruckman, Larry L.

    2009-02-20

    Recent advances in photon detectors have resulted in high-density imaging arrays that offer many performance and cost advantages. In particular, the excellent transit time spread of certain devices show promise to provide tangible benefits in applications such as Positron Emission Tomography (PET). Meanwhile, high-density, high-performance readout techniques have not kept on pace for exploiting these developments. Photodetector readout for next generation high event rate particle identification and time-resolved PET requires a highly-integrated, low-power, and cost-effective readout technique. We propose fast waveform sampling as a method that meets these criteria and demonstrate that sub-10ps resolution can be obtained for an existing device.

  6. Neutron energy spectra calculations in the low power research reactor

    International Nuclear Information System (INIS)

    Omar, H.; Khattab, K.; Ghazi, N.

    2011-01-01

    The neutron energy spectra have been calculated in the fuel region, inner and outer irradiation sites of the zero power research reactor using the MCNP-4C code and the combination of the WIMS-D/4 transport code for generation of group constants and the three-dimensional CITATION diffusion code for core analysis calculations. The neutron energy spectrum has been divided into three regions and compared with the proposed empirical correlations. The calculated thermal and fast neutron fluxes in the low power research reactor MNSR inner and outer irradiation sites have been compared with the measured results. Better agreements have been noticed between the calculated and measured results using the MCNP code than those obtained by the CITATION code. (author)

  7. Biomedical effects of low-power laser controlled by electroacupuncture

    Science.gov (United States)

    Kalenchits, Nadezhda I.; Nicolaenko, Andrej A.; Shpilevoj, Boris N.

    1997-12-01

    The methods and technical facilities of testing the biomedical effects caused by the influence of low-power laser radiation in the process of laser therapy are presented. Described studies have been conducted by means of the complex of fireware facilities consisting of the system of electroacupuncture diagnostics (EA) and a system of laser therapy on the basis of multichannel laser and magneto-laser devices. The task of laser therapy was concluded in undertaking acupuncture anaesthetization, achievement of antioedemic and dispersional actions, raising tone of musculus and nervous system, normalization of immunity factors under the control of system EA. The 82 percent to 95 percent agreement of the result of an electroacupuncture diagnostics with clinical diagnoses were achieved.

  8. New-generation low-power radiation survey instruments

    International Nuclear Information System (INIS)

    Waechter, D.A.; Bjarke, G.O.; Wolf, M.A.; Trujillo, F.; Umbarger, C.J.

    1983-01-01

    A number of new, ultra-low-powered radiation instruments have recently been developed at Los Alamos. Among these are two instruments which use a novel power source to eliminate costly batteries. The newly developed gamma detecting radiac, nicknamed the Firefly, and the alpha particle detecting instrument, called the Simple Cordless Alpha Monitor, both use recent advances in miniaturization and power-saving electronics to yield devices which are small, rugged, and very power-frugal. The two instruments consume so little power that the need for batteries to run them is eliminated. They are, instead, powered by a charged capacitor which will operate the instruments for an hour or more. Both line power and mechanical sources are used to charge the storage capacitors which power the instruments

  9. Low-Power Architecture for an Optical Life Gas Analyzer

    Science.gov (United States)

    Pilgrim, Jeffrey; Vakhtin, Andrei

    2012-01-01

    Analog and digital electronic control architecture has been combined with an operating methodology for an optical trace gas sensor platform that allows very low power consumption while providing four independent gas measurements in essentially real time, as well as a user interface and digital data storage and output. The implemented design eliminates the cross-talk between the measurement channels while maximizing the sensitivity, selectivity, and dynamic range for each measured gas. The combination provides for battery operation on a simple camcorder battery for as long as eight hours. The custom, compact, rugged, self-contained design specifically targets applications of optical major constituent and trace gas detection for multiple gases using multiple lasers and photodetectors in an integrated package.

  10. High-Voltage, Low-Power BNC Feedthrough Terminator

    Science.gov (United States)

    Bearden, Douglas

    2012-01-01

    This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

  11. Deterministic chaos in the processor load

    International Nuclear Information System (INIS)

    Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

    2007-01-01

    In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

  12. Achievable rate of spectrum sharing cognitive radio systems over fading channels at low-power regime

    KAUST Repository

    Sboui, Lokman; Rezki, Zouheir; Alouini, Mohamed-Slim

    2014-01-01

    the previously achieved rate at the low-power regime. Interestingly, we show that the low-power regime analysis provides a specific insight into the maximum achievable rate behavior of CR that has not been reported by previous studies.

  13. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  14. Static Schedulers for Embedded Real-Time Systems

    Science.gov (United States)

    1989-12-01

    Because of the need for having efficient scheduling algorithms in large scale real time systems , software engineers put a lot of effort on developing...provide static schedulers for he Embedded Real Time Systems with single processor using Ada programming language. The independent nonpreemptable...support the Computer Aided Rapid Prototyping for Embedded Real Time Systems so that we determine whether the system, as designed, meets the required

  15. A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors

    Directory of Open Access Journals (Sweden)

    Ricardo Acevedo-Avila

    2016-05-01

    Full Text Available Blob detection is a common task in vision-based applications. Most existing algorithms are aimed at execution on general purpose computers; while very few can be adapted to the computing restrictions present in embedded platforms. This paper focuses on the design of an algorithm capable of real-time blob detection that minimizes system memory consumption. The proposed algorithm detects objects in one image scan; it is based on a linked-list data structure tree used to label blobs depending on their shape and node information. An example application showing the results of a blob detection co-processor has been built on a low-powered field programmable gate array hardware as a step towards developing a smart video surveillance system. The detection method is intended for general purpose application. As such, several test cases focused on character recognition are also examined. The results obtained present a fair trade-off between accuracy and memory requirements; and prove the validity of the proposed approach for real-time implementation on resource-constrained computing platforms.

  16. A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors.

    Science.gov (United States)

    Acevedo-Avila, Ricardo; Gonzalez-Mendoza, Miguel; Garcia-Garcia, Andres

    2016-05-28

    Blob detection is a common task in vision-based applications. Most existing algorithms are aimed at execution on general purpose computers; while very few can be adapted to the computing restrictions present in embedded platforms. This paper focuses on the design of an algorithm capable of real-time blob detection that minimizes system memory consumption. The proposed algorithm detects objects in one image scan; it is based on a linked-list data structure tree used to label blobs depending on their shape and node information. An example application showing the results of a blob detection co-processor has been built on a low-powered field programmable gate array hardware as a step towards developing a smart video surveillance system. The detection method is intended for general purpose application. As such, several test cases focused on character recognition are also examined. The results obtained present a fair trade-off between accuracy and memory requirements; and prove the validity of the proposed approach for real-time implementation on resource-constrained computing platforms.

  17. 47 CFR 74.785 - Low power TV digital data service pilot project.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Low power TV digital data service pilot project... Power TV, TV Translator, and TV Booster Stations § 74.785 Low power TV digital data service pilot project. Low power TV stations authorized pursuant to the LPTV Digital Data Services Act (Public Law 106...

  18. 76 FR 11680 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2011-03-03

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A... Commission's Rules to Establish Rules for Digital Low Power, Television Translator, and Television Booster... Digital Low Power Television Translator, Television Booster Stations, and to Amend Rules for Digital Class...

  19. 76 FR 23795 - Low-Power Television and Translator Upgrade Program: Notice of Final Closing Date

    Science.gov (United States)

    2011-04-28

    .... 110418247-1247-01] Low-Power Television and Translator Upgrade Program: Notice of Final Closing Date AGENCY... receipt of applications for the Low-Power Television and Translator Upgrade Program (Upgrade Program) will... Rules to Establish Rules for Digital Low Power Television, Television Translator, and Television Booster...

  20. Ultra-low power high precision magnetotelluric receiver array based customized computer and wireless sensor network

    Science.gov (United States)

    Chen, R.; Xi, X.; Zhao, X.; He, L.; Yao, H.; Shen, R.

    2016-12-01

    Dense 3D magnetotelluric (MT) data acquisition owns the benefit of suppressing the static shift and topography effect, can achieve high precision and high resolution inversion for underground structure. This method may play an important role in mineral exploration, geothermal resources exploration, and hydrocarbon exploration. It's necessary to reduce the power consumption greatly of a MT signal receiver for large-scale 3D MT data acquisition while using sensor network to monitor data quality of deployed MT receivers. We adopted a series of technologies to realized above goal. At first, we designed an low-power embedded computer which can couple with other parts of MT receiver tightly and support wireless sensor network. The power consumption of our embedded computer is less than 1 watt. Then we designed 4-channel data acquisition subsystem which supports 24-bit analog-digital conversion, GPS synchronization, and real-time digital signal processing. Furthermore, we developed the power supply and power management subsystem for MT receiver. At last, a series of software, which support data acquisition, calibration, wireless sensor network, and testing, were developed. The software which runs on personal computer can monitor and control over 100 MT receivers on the field for data acquisition and quality control. The total power consumption of the receiver is about 2 watts at full operation. The standby power consumption is less than 0.1 watt. Our testing showed that the MT receiver can acquire good quality data at ground with electrical dipole length as 3 m. Over 100 MT receivers were made and used for large-scale geothermal exploration in China with great success.

  1. Online Fastbus processor for LEP

    International Nuclear Information System (INIS)

    Mueller, H.

    1986-01-01

    The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

  2. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  3. Integrating an embedded system in a microwave moisture meter

    Science.gov (United States)

    The conversion of a PC- or laptop-controlled microwave moisture meter to a stand-alone meter hosting its own embedded system is discussed. The moisture meter measures the attenuation and phase shift of low power microwaves traversing the sample, from which the dielectric properties are calculated. T...

  4. Integrating an Embedded System within a Microwave Moisture Meter

    Science.gov (United States)

    In this paper, the conversion of a PC or laptop-controlled microwave moisture meter to a stand-alone meter hosting its own embedded system is discussed. The moisture meter uses low-power microwaves to measure the attenuation and phase shift of the sample, from which the dielectric properties are cal...

  5. Optimization of ultra-low-power CMOS transistors

    International Nuclear Information System (INIS)

    Stockinger, M.

    2000-01-01

    Ultra-low-power CMOS integrated circuits have constantly gained importance due to the fast growing portable electronics market. High-performance applications like mobile telephones ask for high-speed computations and low stand-by power consumption to increase the actual operating time. This means that transistors with low leakage currents and high drive currents have to be provided. Common fabrication methods will soon reach their limits if the on-chip feature size of CMOS technology continues to shrink at this very fast rate. New device architectures will help to keep track with the roadmap of the semiconductor industry. Especially doping profiles offer much freedom for performance improvements as they determine the 'inner functioning' of a transistor. In this work automated doping profile optimization is performed on MOS transistors within the TCAD framework SIESTA. The doping between and under the source/drain wells is discretized on an orthogonal optimization grid facilitating almost arbitrary two-dimensional shapes. A linear optimizer issued to find the optimum doping profile by variation of the doping parameters utilizing numerical device simulations with MINIMOS-NT. Gaussian functions are used in further optimization runs to make the doping profiles smooth. Two device generations are considered, one with 0.25 μm, the other with 0.1 μm gate length. The device geometries and source/drain doping profiles are kept fixed during optimization and supply voltages are chosen suitable for ultra-low-power purposes. In a first optimization study the drive current of NMOS transistors is maximized while keeping the leakage current below a limit of 1 pA/μm. This results in peaking channel doping devices (PCD) with narrow doping peaks placed asymmetrically in the channel. Drive current improvements of 45 % and 71 % for the 0.25 μm and 0.1 μm devices, respectively, are achieved compared to uniformly doped devices. The PCD device is studied in detail and explanations for

  6. Embedded Face Detection and Recognition

    Directory of Open Access Journals (Sweden)

    Göksel Günlü

    2012-10-01

    Full Text Available The need to increase security in open or public spaces has in turn given rise to the requirement to monitor these spaces and analyse those images on-site and on-time. At this point, the use of smart cameras – of which the popularity has been increasing – is one step ahead. With sensors and Digital Signal Processors (DSPs, smart cameras generate ad hoc results by analysing the numeric images transmitted from the sensor by means of a variety of image-processing algorithms. Since the images are not transmitted to a distance processing unit but rather are processed inside the camera, it does not necessitate high-bandwidth networks or high processor powered systems; it can instantaneously decide on the required access. Nonetheless, on account of restricted memory, processing power and overall power, image processing algorithms need to be developed and optimized for embedded processors. Among these algorithms, one of the most important is for face detection and recognition. A number of face detection and recognition methods have been proposed recently and many of these methods have been tested on general-purpose processors. In smart cameras – which are real-life applications of such methods – the widest use is on DSPs. In the present study, the Viola-Jones face detection method – which was reported to run faster on PCs – was optimized for DSPs; the face recognition method was combined with the developed sub-region and mask-based DCT (Discrete Cosine Transform. As the employed DSP is a fixed-point processor, the processes were performed with integers insofar as it was possible. To enable face recognition, the image was divided into sub-regions and from each sub-region the robust coefficients against disruptive elements – like face expression, illumination, etc. – were selected as the features. The discrimination of the selected features was enhanced via LDA (Linear Discriminant Analysis and then employed for recognition. Thanks to its

  7. Efficient Implementation of Solvers for Linear Model Predictive Control on Embedded Devices

    DEFF Research Database (Denmark)

    Frison, Gianluca; Kwame Minde Kufoalor, D.; Imsland, Lars

    2014-01-01

    This paper proposes a novel approach for the efficient implementation of solvers for linear MPC on embedded devices. The main focus is to explain in detail the approach used to optimize the linear algebra for selected low-power embedded devices, and to show how the high-performance implementation...

  8. Consideration on a Low Power Solar Energy Renewable Source

    Directory of Open Access Journals (Sweden)

    Andrei Marusca

    2008-05-01

    Full Text Available This paper presents the contribution of theauthors regarding the implementation of a low powersolar energy renewable source. To optimize theconversion efficiency of the solar irradiance intoelectrical energy an embedded system was designed. Theembedded system can accomplish the maximum powerpoint tracking by evaluation the output voltage andcurrent of the photovoltaic panels and calculate a propercommand for the DC-DC converter of the renewablesource. The key device in this system is a midrange 8 bitmicrocontroller that consists of acquisition, commandand control integrated hardware resources.

  9. Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

    Science.gov (United States)

    DeGregorio, Kelly; Wilson, Dale G.

    2009-01-01

    Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

  10. Low Power Shutdown PSA for CANDU Type Plants

    Energy Technology Data Exchange (ETDEWEB)

    Bae, Yeon Kyoung; Kim, Myung Su [KHNP CRI, Daejeon (Korea, Republic of)

    2016-10-15

    KHNP also have concentrated on full power PSA. Some recently constructed OPR1000 type plants and APR1400 type plants have performed the low power and shutdown (LPSD) PSA. The purpose of LPSD PSA is to identify the main contributors on the accident sequences of core damage and to find the measure of safety improvement. After the Fukushima accident, Korean regulatory agency required the shutdown severe accident management guidelines (SSAMG) development for safety enhancement. For the reliability of SSAMG, KHNP should develop the LPSD PSA. Especially, the LPSD PSA for CANDU type plant had developed for the first time in Korea. This paper illustrates how the LPSD PSA for CANDU type developed and the core damage frequency (CDF) is different with that of full power PSA. KHNP performed LPSD PSA to develop the SSAMG after the Fukushima accidents. The results show that risk at the specific operation mode during outage is higher than that of full power operation. Also, the results indicated that recovery failure of class 4 power at the POS 5A, 5B contribute dominantly to the total CDF from importances analysis. LPSD PSA results such as CDF with initiating events and POSs, risk results with plant damage state, and containment failure probability and frequency with POSs can be used by inputs for developing the SSAMG.

  11. Quantum broadcasting problem in classical low-power signal processing

    International Nuclear Information System (INIS)

    Janzing, Dominik; Steudel, Bastian

    2007-01-01

    We prove a no-broadcasting theorem for the Holevo information of a noncommuting ensemble stating that no operation can generate a bipartite ensemble such that both copies have the same information as the original. We argue that upper bounds on the average information over both copies imply lower bounds on the quantum capacity required to send the ensemble without information loss. This is because a channel with zero quantum capacity has a unitary extension transferring at least as much information to its environment as it transfers to the output. For an ensemble being the time orbit of a pure state under a Hamiltonian evolution, we derive such a bound on the required quantum capacity in terms of properties of the input and output energy distribution. Moreover, we discuss relations between the broadcasting problem and entropy power inequalities. The broadcasting problem arises when a signal should be transmitted by a time-invariant device such that the outgoing signal has the same timing information as the incoming signal had. Based on previous results we argue that this establishes a link between quantum information theory and the theory of low power computing because the loss of timing information implies loss of free energy

  12. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Science.gov (United States)

    Nimo, Antwi; Grgić, Dario; Reindl, Leonhard M.

    2012-01-01

    This work presents the optimization of antenna captured low power radio frequency (RF) to direct current (DC) power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor) resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna) is built and tested for receiving range performance. PMID:23202014

  13. Optimization of Passive Low Power Wireless Electromagnetic Energy Harvesters

    Directory of Open Access Journals (Sweden)

    Dario Grgić

    2012-10-01

    Full Text Available This work presents the optimization of antenna captured low power radio frequency (RF to direct current (DC power converters using Schottky diodes for powering remote wireless sensors. Linearized models using scattering parameters show that an antenna and a matched diode rectifier can be described as a form of coupled resonator with different individual resonator properties. The analytical models show that the maximum voltage gain of the coupled resonators is mainly related to the antenna, diode and load (remote sensor resistances at matched conditions or resonance. The analytical models were verified with experimental results. Different passive wireless RF power harvesters offering high selectivity, broadband response and high voltage sensitivity are presented. Measured results show that with an optimal resistance of antenna and diode, it is possible to achieve high RF to DC voltage sensitivity of 0.5 V and efficiency of 20% at −30 dBm antenna input power. Additionally, a wireless harvester (rectenna is built and tested for receiving range performance.

  14. Low power consumption mini rotary actuator with SMA wires

    Science.gov (United States)

    Manfredi, Luigi; Huan, Yu; Cuschieri, Alfred

    2017-11-01

    Shape memory alloys (SMAs) are smart materials widely used as actuators for their high power to weight ratio despite their well-known low energy efficiency and limited mechanical bandwidth. For robotic applications, SMAs exhibit limitations due to high power consumption and limited stroke, varying from 4% to 7% of the total length. Hysteresis, during the contraction and extension cycle, requires a complex control algorithm. On the positive side, the small size and low weight are eminently suited for the design of mini actuators for robotic platforms. This paper describes the design and construction of a light weight and low power consuming mini rotary actuator with on-board contact-less position and force sensors. The design is specifically intended to reduce (i) energy consumption, (ii) dimensions of the sensory system, and (iii) provide a simple control without any need for SMA characterisation. The torque produced is controlled by on-board force sensors. Experiments were performed to investigate the energy consumption and performance (step and sinusoidal angle profiles with a frequency varying from 0.5 to 10 Hz and maximal amplitude of {15}\\circ ). We describe a transient capacitor effect related to the SMA wires during the sinusoidal profile when the active SMA wire is powered and the antagonist one switched-off, resulting in a transient current time varying from 300 to 400 ms.

  15. ``Low Power Wireless Technologies: An Approach to Medical Applications''

    Science.gov (United States)

    Bellido O., Francisco J.; González R., Miguel; Moreno M., Antonio; de La Cruz F, José Luis

    Wireless communication supposed a great both -quantitative and qualitative, jump in the management of the information, allowing the access and interchange of it without the need of a physical cable connection. The wireless transmission of voice and information has remained in constant evolution, arising new standards like BluetoothTM, WibreeTM or ZigbeeTM developed under the IEEE 802.15 norm. These newest wireless technologies are oriented to systems of communication of short-medium distance and optimized for a low cost and minor consume, becoming recognized as a flexible and reliable medium for data communications across a broad range of applications due to the potential that the wireless networks presents to operate in demanding environments providing clear advantages in cost, size, power, flexibility, and distributed intelligence. About the medical applications, the remote health or telecare (also called eHealth) is getting a bigger place into the manufacturers and medical companies, in order to incorporate products for assisted living and remote monitoring of health parameteres. At this point, the IEEE 1073, Personal Health Devices Working Group, stablish the framework for these kind of applications. Particularly, the 1073.3.X describes the physical and transport layers, where the new ultra low power short range wireless technologies can play a big role, providing solutions that allow the design of products which are particularly appropriate for monitor people’s health with interoperability requirements.

  16. Nanoelectromechanical Switches for Low-Power Digital Computing

    Directory of Open Access Journals (Sweden)

    Alexis Peschot

    2015-08-01

    Full Text Available The need for more energy-efficient solid-state switches beyond complementary metal-oxide-semiconductor (CMOS transistors has become a major concern as the power consumption of electronic integrated circuits (ICs steadily increases with technology scaling. Nano-Electro-Mechanical (NEM relays control current flow by nanometer-scale motion to make or break physical contact between electrodes, and offer advantages over transistors for low-power digital logic applications: virtually zero leakage current for negligible static power consumption; the ability to operate with very small voltage signals for low dynamic power consumption; and robustness against harsh environments such as extreme temperatures. Therefore, NEM logic switches (relays have been investigated by several research groups during the past decade. Circuit simulations calibrated to experimental data indicate that scaled relay technology can overcome the energy-efficiency limit of CMOS technology. This paper reviews recent progress toward this goal, providing an overview of the different relay designs and experimental results achieved by various research groups, as well as of relay-based IC design principles. Remaining challenges for realizing the promise of nano-mechanical computing, and ongoing efforts to address these, are discussed.

  17. Recirculating steam generator operation at very low power

    International Nuclear Information System (INIS)

    Holcblat, A.

    2001-01-01

    The behaviour of recirculating SG's at very low power has been thoroughly investigated by laboratory and on-site tests as well as numerical simulations. A special experimental program dedicated to recirculation threshold determination has been performed on the Freon SG mock-up CLOTAIRE. These laboratory data are completed with transients of feedwater injections at hot stand-by on two instrumented SG's, one boiler type SG and one economizer type SG. The phenomena are different on both types. In boiler SG's, the SG behaves like a U-tube and recirculation stops around 2% load at stand-by temperature and water level. In economizer SG's, the presence of 2 separate down-comers and a divider plate inside the tube bundle allows a recirculation loop by-passing the separators. The mixing of saturated and cold water induced by this loop limits down-comer cooling and thus alleviates the thermal load on the tube sheet. These tests were used to validate the SG transient analysis 1-D code ANETH. (author)

  18. Low power offloading strategy for femto-cloud mobile network

    Directory of Open Access Journals (Sweden)

    Anwesha Mukherjee

    2016-03-01

    Full Text Available Nowadays offloading is a popular method of mobile cloud computing where the required computation takes place remotely inside the cloud. But whether to process an application inside the mobile device or to the cloud is a challenging issue because communication with the cloud involves latency and power consumption. This paper has proposed a method of decision making regarding whether to offload or not-to-offload an application to the cloud. According to the proposed strategy, application is offloaded only if it results in lower power consumption than local execution within the mobile device itself. If this condition is satisfied, computation time and deadline of the job are considered as the basic parameters to decide whether to offload or not. Experimental results demonstrate that the proposed offloading algorithm reduces the power consumption to approximately 3–32%. To achieve power-efficiency and security both, femto-cloud architecture is used in the proposed work. In this case offloading from the mobile device to the cloud takes place through the low power and secure femtocell base station. Simulation results present that using femto-cloud architecture 70–83% and 52–66% power savings are achieved than using macrocell and microcell base stations respectively while offloading an application to the cloud.

  19. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  20. An optimized low-power voltage controlled oscillator

    Science.gov (United States)

    Shah, Kriyang; Le, Hai Phuong; Singh, Jugdutt

    2007-01-01

    This paper presents an optimised low-power low-phase-noise Voltage Controlled Oscillator (VCO) for Bluetooth wireless applications. The system level design issues and tradeoffs related to Direct Conversion Receiver (DCR) and Low Intermediate Frequency (IF) architecture for Bluetooth are discussed. Subsequently, for a low IF architecture, the critical VCO performance parameters are derived from system specifications. The VCO presented in the paper is optimised by implementing a novel biasing circuit that employs two current mirrors, one at the top and the other one at the bottom of the cross-coupled complementary VCO, to give the exact replica of the current in both the arms of current mirror circuit. This approach, therefore, significantly reduces the system power consumption as well as improves the system performance. Results show that, the VCO consumes only 281μW of power at 2V supply. Its phase noise performance are -115dBc/Hz, -130dBc/Hz and -141dBc/Hz at the offset frequency of 1MHz, 3MHz and 5MHz respectively. Results indicate that 31% reduction in power consumption is achieved as compared to the traditional VCO design. These characteristics make the designed VCO a better candidate for Bluetooth wireless application where power consumption is the major issue.

  1. Quality of the current low power and shutdown PSA practice

    International Nuclear Information System (INIS)

    Jang, Seung Cheol; Park, Jin Hee; Lim, Ho Gon; Kim, Tae Woon

    2004-01-01

    A probabilistic safety assessment (PSA) for the low-power and shutdown (LPSD) modes in a Korea standard nuclear power plant (KSNP) has been performed for the purpose of estimating the LPSD risk and identifying the vulnerabilities of LPSD operations. Both the operational experience and PSA results indicate that the risks from LPSD operations could be comparable with those from power operations. However, the application of the LPSD risk insights to risk-informed decision making has been slow to be adopted in practice. It is largely due to the question of whether the current LPSD PSA practice is appropriate for application to risk-informed decision making or not. Such a question has to do with the quality of the current LPSD PSA practice. In this paper, we have performed self-assessment of the KSNP LPSD PSA quality based on the ANS Standard (draft as of 13 Sep. 2002). The aims of the work are to find the LPSD PSA technical areas insufficient for application to risk-informed decision making and to efficiently allocate the limited research resources to improve the LPSD PSA model quality. Many useful findings regarding the current LPSD PSA quality are presented in this paper

  2. Low power gas sensor array on flexible acetate substrate

    Science.gov (United States)

    Benedict, Samatha; Basu, Palash Kumar; Bhat, Navakanta

    2017-07-01

    In this paper, we present a novel approach of fabricating a low-cost and low power gas sensor array on flexible acetate sheets for sensing CO, SO2, H2 and NO2 gases. The array has four sensor elements with an integrated microheater which can be individually controlled enabling the monitoring of four gases. The thermal properties of the microheater characterized by IR imaging are presented. The microheater with an active area of 15 µm  ×  5 µm reaches a temperature of 300 °C, consuming 2 mW power, the lowest reported on flexible substrates. A sensing electrode is patterned on top of the microheater, and a nanogap (100 nm) is created by an electromigration process. This nanogap is bridged by four sensing materials doped with platinum, deposited using a solution dispensing technique. The sensing material characterization is completed using energy dispersive x-ray analysis. The sensing characteristics of ZnO for CO, V2O5 for SO2, SnO2 for H2 and WO3 for NO2 gases are studied at different microheater voltages. The sensing characteristics of ZnO at different bending angles is also studied, which shows that the microheater and the sensing material are intact without any breaking upto a bending angle of 20°. The ZnO CO sensor shows sensitivity of 146.2% at 1 ppm with good selectivity.

  3. Low power RF measurements of travelling wave type linear accelerator

    International Nuclear Information System (INIS)

    Reddy, Sivananda; Wanmode, Yashwant; Bhisikar, A.; Shrivastava, Purushottam

    2015-01-01

    RRCAT is engaged in the development of travelling wave (TW) type linear accelerator for irradiation of industrial and agricultural products. TW accelerator designed for 2π/3 mode to operate at frequency of 2856 MHz. It consists of input coupler, buncher cells, regular cells and output coupler. Low power measurement of this structure includes measurement of resonant frequency of the cells for different resonant modes and quality factor, tuning of input-output coupler and measurement of phase advance per cell and electric field in the structure. Steele's non-resonant perturbation technique has been used for measurement of phase advance per cell and electric field in the structure. Kyhl's method has been used for the tuning of input-output coupler. Computer based automated bead pull set-up has been developed for measurement of phase advance per cell and electric field profile in the structure. All the codes are written in Python for interfacing of Vector Network Analyzer (VNA) , stepper motor with computer. These codes also automate the measurement process. This paper describes the test set- up for measurement and results of measurement of travelling wave type linear accelerating structure. (author)

  4. Low power femtosecond tip-based nanofabrication with advanced control

    Science.gov (United States)

    Liu, Jiangbo; Guo, Zhixiong; Zou, Qingze

    2018-02-01

    In this paper, we propose an approach to enable the use of low power femtosecond laser in tip-based nanofabrication (TBN) without thermal damage. One major challenge in laser-assisted TBN is in maintaining precision control of the tip-surface positioning throughout the fabrication process. An advanced iterative learning control technique is exploited to overcome this challenge in achieving high-quality patterning of arbitrary shape on a metal surface. The experimental results are analyzed to understand the ablation mechanism involved. Specifically, the near-field radiation enhancement is examined via the surface-enhanced Raman scattering effect, and it was revealed the near-field enhanced plasma-mediated ablation. Moreover, silicon nitride tip is utilized to alleviate the adverse thermal damage. Experiment results including line patterns fabricated under different writing speeds and an "R" pattern are presented. The fabrication quality with regard to the line width, depth, and uniformity is characterized to demonstrate the efficacy of the proposed approach.

  5. Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

    2010-01-01

    The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

  6. Embedded and real-time operating systems

    CERN Document Server

    Wang, K C

    2017-01-01

    This book covers the basic concepts and principles of operating systems, showing how to apply them to the design and implementation of complete operating systems for embedded and real-time systems. It includes all the foundational and background information on ARM architecture, ARM instructions and programming, toolchain for developing programs, virtual machines for software implementation and testing, program execution image, function call conventions, run-time stack usage and link C programs with assembly code. It describes the design and implementation of a complete OS for embedded systems in incremental steps, explaining the design principles and implementation techniques. For Symmetric Multiprocessing (SMP) embedded systems, the author examines the ARM MPcore processors, which include the SCU and GIC for interrupts routing and interprocessor communication and synchronization by Software Generated Interrupts (SGIs). Throughout the book, complete working sample systems demonstrate the design principles and...

  7. Delay-Limited Capacity in the Low Power Regime

    KAUST Repository

    Rezki, Zouheir

    2016-02-11

    Outage performance of the M-block fading with additive white Gaussian noise (BF-AWGN) is investigated in the low-power regime. We consider delay-constrained constant-rate communications with perfect channel state information (CSI) at both the transmitter and the receiver (CSI-TR), under a shortterm power constraint (STPC) and a long-term power constraint (LTPC). Subject to STPC, we show that selection diversity that allocates all the power to the strongest block is asymptotically optimal. Then, we provide a simple characterization of the outage probability in the regime of interest. We quantify the reward due to CSI-TR over the constant-rate constant-power scheme and show that this reward increases with the delay constraint. For instance, for Rayleigh fading, we find that a power gain up to 4.3 dB is achievable. Subject to LTPC, we show that the above guidelines still holds and that the outage performance improves due to the flexibility of the LTPC over the STPC. More interestingly, we prove that LTPC allows zero-outage communication even at low SNR and characterize the delaylimited capacity at low SNR in a simple form. More precisely, we establish that the delay-limited capacity scales linearly with the power constraint, for a given M < 1. Our framework highlights the benefit of fading at low SNR as the delay-limited capacity may outperform the AWGN capacity. For instance, for Rayleigh fading and with M = 3, the delay-limited capacity is 16% higher than the capacity of an AWGN channel.

  8. Low Power Design for Future Wearable and Implantable Devices

    Directory of Open Access Journals (Sweden)

    Katrine Lundager

    2016-10-01

    Full Text Available With the fast progress in miniaturization of sensors and advances in micromachinery systems, a gate has been opened to the researchers to develop extremely small wearable/implantable microsystems for different applications. However, these devices are reaching not to a physical limit but a power limit, which is a critical limit for further miniaturization to develop smaller and smarter wearable/implantable devices (WIDs, especially for multi-task continuous computing purposes. Developing smaller and smarter devices with more functionality requires larger batteries, which are currently the main power provider for such devices. However, batteries have a fixed energy density, limited lifetime and chemical side effect plus the fact that the total size of the WID is dominated by the battery size. These issues make the design very challenging or even impossible. A promising solution is to design batteryless WIDs scavenging energy from human or environment including but not limited to temperature variations through thermoelectric generator (TEG devices, body movement through Piezoelectric devices, solar energy through miniature solar cells, radio-frequency (RF harvesting through antenna etc. However, the energy provided by each of these harvesting mechanisms is very limited and thus cannot be used for complex tasks. Therefore, a more comprehensive solution is the use of different harvesting mechanisms on a single platform providing enough energy for more complex tasks without the need of batteries. In addition to this, complex tasks can be done by designing Integrated Circuits (ICs, as the main core and the most power consuming component of any WID, in an extremely low power mode by lowering the supply voltage utilizing low-voltage design techniques. Having the ICs operational at very low voltages, will enable designing battery-less WIDs for complex tasks, which will be discussed in details throughout this paper. In this paper, a path towards battery

  9. Low power data acquisition unit for autonomous geophysical instrumentation

    Science.gov (United States)

    Prystai, Andrii

    2017-04-01

    The development of an autonomous instrumentation for field research is always a challenge which needs knowledge and application of recent advances in technology and components production. Using this information a super-low power, low-cost, stand-alone GPS time synchronized data acquisition unit was created. It comprises an extended utilization of the microcontroller modules and peripherals and special firmware with flexible PLL parameters. The present report is devoted to a discussion of synchronization mode of data sampling in autonomous field instruments with possibility of GPS random breaks. In the result the achieved sampling timing accuracy is better than ± 60 ns without phase jumps and distortion plus fixed shift depending on the sample rate. The main application of the system is for simultaneous measurement of several channels from magnetic and electric sensors in field conditions for magneto-telluric instruments. First utilization of this system was in the new developed versions of LEMI-026 magnetometer and LEMI-423 field station, where it was applied for digitizing of up to 6 analogue channels with 32-bit resolution in the range ± 2.5V, digital filtration (LPF) and maximum sample rate 4kS/s. It is ready for record in 5 minutes after being turned on. Recently, this system was successfully utilized with the drone-portable magnetometers destined for the search of metallic objects, like UXO, in rural areas, research of engineering underground structure and for mapping ore bodies. The successful tests of drone-portable system were made and tests results are also discussed.

  10. Low power interface IC's for electrostatic energy harvesting applications

    Science.gov (United States)

    Kempitiya, Asantha

    interest where the storage capacitor can be optimized to produce almost 70% of the ideal power taken as the power harvested with synchronous converters when neglecting the power consumption associated with synchronizing control circuitry. Theoretical predictions are confirmed by measurements on an asynchronous EHC implemented with a macro-scale electrostatic converter prototype. Based on the preceding analysis, the design of a novel ultra low power electrostatic integrated energy harvesting circuit is proposed for efficient harvesting of mechanical energy. The fundamental challenges of designing reliable low power sensing circuits for charge constrained electrostatic energy harvesters with capacity to self power its controller and driver stages are addressed. Experimental results are presented for a controller design implemented in AMI 0.7muM high voltage CMOS process using a macro-scale electrostatic converter prototype. The EHC produces 1.126muW for a power investment of 417nW with combined conduction and controller losses of 450nW which is a 20-30% improvement compared to prior art on electrostatic EHCs operating under charge constrain. Inherently dual plate variable capacitors harvest energy only during half of the mechanical cycle with the other half unutilized for energy conversion. To harvest mechanical energy over the complete mechanical vibration cycle, a low power energy harvesting circuit (EHC) that performs charge constrained synchronous energy conversion on a tri-plate variable capacitor for maximizing energy conversion is proposed. The tri-plate macro electrostatic generator with capacitor variation of 405pF to 1.15nF and 405pF to 1.07nF on two complementary adjacent capacitors is fabricated and used in the characterization of the designed EHC. The integrated circuit fabricated in AMI 0.7muM high voltage CMOS process, produces a total output power of 497nW to a 10muF reservoir capacitor from a 98Hz vibration signal. In summary, the thesis lays out the

  11. Embedded Systems for Smart Appliances and Energy Management

    CERN Document Server

    Neumann, Peter; Mahlknecht, Stefan

    2013-01-01

    This book provides a comprehensive introduction to embedded systems for smart appliances and energy management, bringing together for the first time a multidisciplinary blend of topics from embedded systems, information technology and power engineering.  Coverage includes challenges for future resource distribution grids, energy management in smart appliances, micro energy generation, demand response management, ultra-low power stand by, smart standby and communication networks in home and building automation.   Provides a comprehensive, multidisciplinary introduction to embedded systems for smart appliances and energy management; Equips researchers and engineers with information required to succeed in designing energy management for smart appliances; Includes coverage of resource distribution grids, energy management in smart appliances, micro energy generation, demand response management, ultra-low power stand by, smart standby and communication networks in home and building automation.  

  12. Making embedded systems design patterns for great software

    CERN Document Server

    White, Elecia

    2011-01-01

    Interested in developing embedded systems? Since they don't tolerate inefficiency, these systems require a disciplined approach to programming. This easy-to-read guide helps you cultivate a host of good development practices, based on classic software design patterns and new patterns unique to embedded programming. Learn how to build system architecture for processors, not operating systems, and discover specific techniques for dealing with hardware difficulties and manufacturing requirements. Written by an expert who's created embedded systems ranging from urban surveillance and DNA scanner

  13. Embedded palmprint recognition system using OMAP 3530.

    Science.gov (United States)

    Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

    2012-01-01

    We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the central pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance.

  14. Java Dust: How Small Can Embedded Java Be?

    DEFF Research Database (Denmark)

    Caska, James; Schoeberl, Martin

    2011-01-01

    Java is slowly being accepted as a language and platform for embedded devices. However, the memory requirements of the Java library and runtime are still troublesome. A Java system is considered small when it requires less than 1 MB, and within the embedded domain small microcontollers with a few...... KB on-chip Flash memory and even less on-chip RAM are very common. For such small devices Java is a clearly challenging. In this paper we present the combination of the Java compiler Muvium for microcontrollers with the tiny soft-core Leros for an FPGA. To the best of our knowledge, the presented...... embedded Java system is the smallest Java system available. The Leros processor consumes less than 5% of the logic cells of the smallest FPGA from Altera and the Muvium compiler produces a JVM, including the Java application, that can execute in a few KB ROM and less than 1 KB RAM. The Leros processor...

  15. Accuracies Of Optical Processors For Adaptive Optics

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1992-01-01

    Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

  16. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  17. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  18. The UA1 trigger processor

    International Nuclear Information System (INIS)

    Grayer, G.H.

    1981-01-01

    Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

  19. Research on laser detonation pulse circuit with low-power based on super capacitor

    Science.gov (United States)

    Wang, Hao-yu; Hong, Jin; He, Aifeng; Jing, Bo; Cao, Chun-qiang; Ma, Yue; Chu, En-yi; Hu, Ya-dong

    2018-03-01

    According to the demand of laser initiating device miniaturization and low power consumption of weapon system, research on the low power pulse laser detonation circuit with super capacitor. Established a dynamic model of laser output based on super capacitance storage capacity, discharge voltage and programmable output pulse width. The output performance of the super capacitor under different energy storage capacity and discharge voltage is obtained by simulation. The experimental test system was set up, and the laser diode of low power pulsed laser detonation circuit was tested and the laser output waveform of laser diode in different energy storage capacity and discharge voltage was collected. Experiments show that low power pulse laser detonation based on super capacitor energy storage circuit discharge with high efficiency, good transient performance, for a low power consumption requirement, for laser detonation system and low power consumption and provide reference light miniaturization of engineering practice.

  20. Data register and processor for multiwire chambers

    International Nuclear Information System (INIS)

    Karpukhin, V.V.

    1985-01-01

    A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

  1. Many - body simulations using an array processor

    International Nuclear Information System (INIS)

    Rapaport, D.C.

    1985-01-01

    Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

  2. Sensitometric control of roentgen film processors

    International Nuclear Information System (INIS)

    Forsberg, H.; Karolinska Sjukhuset, Stockholm

    1987-01-01

    Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

  3. Low power laser irradiation does not affect the generation of signals in a sensory receptor

    Energy Technology Data Exchange (ETDEWEB)

    Lundeberg, T.; Zhou, J.

    1989-01-01

    The effect of low power Helium-Neon (He-Ne) and Gallium-Arsenide (Ga-As) laser on the slowly adapting crustacean stretch receptor was studied. The results showed that low power laser irradiation did not affect the membrane potential of the stretch receptor. These results are discussed in relation to the use of low power laser irradiation on the skin overlaying acupuncture points in treatment of pain syndrome.

  4. A Portable Low-Power Acquisition System with a Urease Bioelectrochemical Sensor for Potentiometric Detection of Urea Concentrations.

    Science.gov (United States)

    Ma, Wei-Jhe; Luo, Ching-Hsing; Lin, Jiun-Ling; Chou, Sin-Houng; Chen, Ping-Hung; Syu, Mei-Jywan; Kuo, Shin-Hung; Lai, Shin-Chi

    2016-04-02

    This paper presents a portable low-power battery-driven bioelectrochemical signal acquisition system for urea detection. The proposed design has several advantages, including high performance, low cost, low-power consumption, and high portability. A LT1789-1 low-supply-voltage instrumentation amplifier (IA) was used to measure and amplify the open-circuit potential (OCP) between the working and reference electrodes. An MSP430 micro-controller was programmed to process and transduce the signals to the custom-developed software by ZigBee RF module in wireless mode and UART in able mode. The immobilized urease sensor was prepared by embedding urease into the polymer (aniline-co-o-phenylenediamine) polymeric matrix and then coating/depositing it onto a MEMS-fabricated Au working electrode. The linear correlation established between the urea concentration and the potentiometric change is in the urea concentrations range of 3.16 × 10(-4) to 3.16 × 10(-2) M with a sensitivity of 31.12 mV/log [M] and a precision of 0.995 (R² = 0.995). This portable device not only detects urea concentrations, but can also operate continuously with a 3.7 V rechargeab-le lithium-ion battery (500 mA·h) for at least four days. Accordingly, its use is feasible and even promising for home-care applications.

  5. A Portable Low-Power Acquisition System with a Urease Bioelectrochemical Sensor for Potentiometric Detection of Urea Concentrations

    Directory of Open Access Journals (Sweden)

    Wei-Jhe Ma

    2016-04-01

    Full Text Available This paper presents a portable low-power battery-driven bioelectrochemical signal acquisition system for urea detection. The proposed design has several advantages, including high performance, low cost, low-power consumption, and high portability. A LT1789-1 low-supply-voltage instrumentation amplifier (IA was used to measure and amplify the open-circuit potential (OCP between the working and reference electrodes. An MSP430 micro-controller was programmed to process and transduce the signals to the custom-developed software by ZigBee RF module in wireless mode and UART in able mode. The immobilized urease sensor was prepared by embedding urease into the polymer (aniline-co-o-phenylenediamine polymeric matrix and then coating/depositing it onto a MEMS-fabricated Au working electrode. The linear correlation established between the urea concentration and the potentiometric change is in the urea concentrations range of 3.16 × 10−4 to 3.16 × 10−2 M with a sensitivity of 31.12 mV/log [M] and a precision of 0.995 (R2 = 0.995. This portable device not only detects urea concentrations, but can also operate continuously with a 3.7 V rechargeab-le lithium-ion battery (500 mA·h for at least four days. Accordingly, its use is feasible and even promising for home-care applications.

  6. A Portable Low-Power Acquisition System with a Urease Bioelectrochemical Sensor for Potentiometric Detection of Urea Concentrations

    Science.gov (United States)

    Ma, Wei-Jhe; Luo, Ching-Hsing; Lin, Jiun-Ling; Chou, Sin-Houng; Chen, Ping-Hung; Syu, Mei-Jywan; Kuo, Shin-Hung; Lai, Shin-Chi

    2016-01-01

    This paper presents a portable low-power battery-driven bioelectrochemical signal acquisition system for urea detection. The proposed design has several advantages, including high performance, low cost, low-power consumption, and high portability. A LT1789-1 low-supply-voltage instrumentation amplifier (IA) was used to measure and amplify the open-circuit potential (OCP) between the working and reference electrodes. An MSP430 micro-controller was programmed to process and transduce the signals to the custom-developed software by ZigBee RF module in wireless mode and UART in able mode. The immobilized urease sensor was prepared by embedding urease into the polymer (aniline-co-o-phenylenediamine) polymeric matrix and then coating/depositing it onto a MEMS-fabricated Au working electrode. The linear correlation established between the urea concentration and the potentiometric change is in the urea concentrations range of 3.16 × 10−4 to 3.16 × 10−2 M with a sensitivity of 31.12 mV/log [M] and a precision of 0.995 (R2 = 0.995). This portable device not only detects urea concentrations, but can also operate continuously with a 3.7 V rechargeab-le lithium-ion battery (500 mA·h) for at least four days. Accordingly, its use is feasible and even promising for home-care applications. PMID:27049390

  7. Ultra-low power all-optical switch using a single quantum dot embedded in a photonic wire

    DEFF Research Database (Denmark)

    Nguyen, H.A.; Grange, T.; Malik, N.S.

    [1,2]. We exploit here its broad operation bandwidth (>100 nm around 950 nm) to efficiently address two different transitions of the QD with two cw laser beams (fig. 1b). The laser coupled to the upper transition leads to a Rabi splitting of the intermediate state (Autler-Townes effect), affecting...

  8. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  9. Conceptualizing Embedded Configuration

    DEFF Research Database (Denmark)

    Oddsson, Gudmundur Valur; Hvam, Lars; Lysgaard, Ole

    2006-01-01

    and services. The general idea can be named embedded configuration. In this article we intend to conceptualize embedded configuration, what it is and is not. The difference between embedded configuration, sales configuration and embedded software is explained. We will look at what is needed to make embedded...... configuration systems. That will include requirements to product modelling techniques. An example with consumer electronics will illuminate the elements of embedded configuration in settings that most can relate to. The question of where embedded configuration would be relevant is discussed, and the current...

  10. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    Kaerhae, K.; Jouhiaho, A.

    2009-01-01

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  11. The definitive guide to ARM Cortex-M3 and Cortex-M4 processors

    CERN Document Server

    Yiu, Joseph

    2013-01-01

    This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes.  Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Tw

  12. Embedded Hyperchaotic Generators: A Comparative Analysis

    Science.gov (United States)

    Sadoudi, Said; Tanougast, Camel; Azzaz, Mohamad Salah; Dandache, Abbas

    In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchaotic generator which leads to designs with small logic area cost, satisfactory throughput rates, low power consumption and low latency required for embedded applications such as secure digital communications between embedded systems. To implement the four-dimensional (4D) chaotic systems, we use a new structural hardware architecture based on direct VHDL description of the forth order Runge-Kutta method (RK-4). The comparative analysis shows that the hyperchaotic Lorenz generator provides attractive performances compared to that of others. In fact, its hardware implementation requires only 2067 CLB-slices, 36 multipliers and no block RAMs, and achieves a throughput rate of 101.6 Mbps, at the output of the FPGA circuit, at a clock frequency of 25.315 MHz with a low latency time of 316 ns. Consequently, these good implementation performances offer to the embedded hyperchaotic Lorenz generator the advantage of being the best candidate for embedded communications applications.

  13. Tinuso: A processor architecture for a multi-core hardware simulation platform

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven

    2010-01-01

    Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

  14. Piezoelectric energy harvesting for powering low power electronics

    Energy Technology Data Exchange (ETDEWEB)

    Leinonen, M.; Palosaari, J.; Hannu, J.; Juuti, J.; Jantunen, H. (Univ. of Oulu, Dept. of Electrical and Information Engineering (Finland)). email: jajuu@ee.oulu.fi

    2009-07-01

    Although wireless data transmission techniques are commonly used in electronic devices, they still suffer from wires for the power supply or from batteries which require charging, replacement and other maintenance. The vision for the portable electronics and industrial measurement systems of the future is that they are intelligent and independent on their energy supply. The major obstacle in this path is the energy source which enables all other functions and 'smartness' of the systems as the computing power is also restricted by the available energy. The development of long-life energy harvesters would reduce the need for batteries and wires thus enabling cost-effective and environment friendlier solutions for various applications such as autonomous wireless sensor networks, powering of portable electronics and other maintenance-free systems. One of the most promising techniques is mechanical energy harvesting e.g. by piezoelectric components where deformations produced by different means is directly converted to electrical charge via direct piezoelectric effect. Subsequently the electrical energy can be regulated or stored for further use. The total mechanical energy in vibration of machines can be very large and usually only a fraction of it can be transformed to electrical energy. Recently, piezoelectric vibration based energy harvesters have been developed widely for different energy consumption and application areas. As an example for low energy device an piezoelectric energy harvester based on impulse type excitations has been developed for active RFID identification. Moreover, piezoharvester with externally leveraged mechanism for force amplification was reported to be able to generate mean power of 0.4 mW from backpack movement. Significantly higher power levels are expected from larger scale testing in Israel, where piezoelectric material is embedded under active walking street, road, airport or railroad. The energy is harvested from human or

  15. Micro processors for plant protection

    International Nuclear Information System (INIS)

    McAffer, N.T.C.

    1976-01-01

    Micro computers can be used satisfactorily in general protection duties with economic advantages over hardwired systems. The reliability of such protection functions can be enhanced by keeping the task performed by each protection micro processor simple and by avoiding such a task being dependent on others in any substantial way. This implies that vital work done for any task is kept within it and that any communications from it to outside or to it from outside are restricted to those for controlling data transfer. Also that the amount of this data should be the minimum consistent with satisfactory task execution. Technology is changing rapidly and devices may become obsolete and be supplanted by new ones before their theoretical reliability can be confirmed or otherwise by field service. This emphasises the need for users to pool device performance data so that effective reliability judgements can be made within the lifetime of the devices. (orig.) [de

  16. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  17. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

  18. The communication processor of TUMULT-64

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Jansen, P.G.

    1988-01-01

    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

  19. An interactive parallel processor for data analysis

    International Nuclear Information System (INIS)

    Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

    1984-01-01

    A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

  20. Mixed-signal early vision chip with embedded image and programming memories and digital I/O

    Science.gov (United States)

    Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

    2003-04-01

    From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

  1. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  2. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  3. Development of a highly reliable CRT processor

    International Nuclear Information System (INIS)

    Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

    1996-01-01

    Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

  4. Online track processor for the CDF upgrade

    International Nuclear Information System (INIS)

    Thomson, E. J.

    2002-01-01

    A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

  5. Computer Generated Inputs for NMIS Processor Verification

    International Nuclear Information System (INIS)

    J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

    2001-01-01

    Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

  6. Safety-critical Java for embedded systems

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Dalsgaard, Andreas Engelbredt; Hansen, René Rydhof

    2016-01-01

    This paper presents the motivation for and outcomes of an engineering research project on certifiable Javafor embedded systems. The project supports the upcoming standard for safety-critical Java, which defines asubset of Java and libraries aiming for development of high criticality systems....... The outcome of this projectinclude prototype safety-critical Java implementations, a time-predictable Java processor, analysis tools formemory safety, and example applications to explore the usability of safety-critical Java for this applicationarea. The text summarizes developments and key contributions...

  7. 47 CFR 74.793 - Digital low power TV and TV translator station protection of broadcast stations.

    Science.gov (United States)

    2010-10-01

    ... 47 Telecommunication 4 2010-10-01 2010-10-01 false Digital low power TV and TV translator station... DISTRIBUTIONAL SERVICES Low Power TV, TV Translator, and TV Booster Stations § 74.793 Digital low power TV and TV translator station protection of broadcast stations. (a) An application to construct a new digital low power...

  8. Quality-driven model-based design of multi-processor accelerators : an application to LDPC decoders

    NARCIS (Netherlands)

    Jan, Y.

    2012-01-01

    The recent spectacular progress in nano-electronic technology has enabled the implementation of very complex multi-processor systems on single chips (MPSoCs). However in parallel, new highly demanding complex embedded applications are emerging, in fields like communication and networking,

  9. 76 FR 81998 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2011-12-29

    ... NUCLEAR REGULATORY COMMISSION [NRC-2011-0295] Methodology for Low Power/Shutdown Fire PRA AGENCY..., ``Methodology for Low Power/Shutdown Fire PRA--Draft Report for Comment.'' DATES: Submit comments by March 01... risk assessment (PRA) method for quantitatively analyzing fire risk in commercial nuclear power plants...

  10. Radio frequency energy harvesting and low power data transmission for autonomous wireless sensor nodes

    NARCIS (Netherlands)

    Rodrigues Mansano, A.L.

    2016-01-01

    Since the Internet of Things (IoT) is expected to be the new technology to drive the semiconductor industry, significant research efforts have been made to develop new circuit and system techniques for autonomous/very low-power operation of wireless sensor nodes. Very low-power consumption of

  11. 76 FR 44821 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-07-27

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend Rules... Digital Low Power Television, Television Translator, and Television Booster Stations and to Amend Rules... translator facilities in the 700 MHz band. These provisions provide procedures for a primary wireless...

  12. 76 FR 72849 - Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend...

    Science.gov (United States)

    2011-11-28

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and To Amend Rules... for Digital Low Power Television, Television Translator, and Television Booster Stations and to Amend... television, TV translator, and Class A television station DTV licensees''). The Commission has also revised...

  13. 75 FR 63766 - Digital Low Power Television, Television Translator, and Television Booster Stations and Digital...

    Science.gov (United States)

    2010-10-18

    ...] Digital Low Power Television, Television Translator, and Television Booster Stations and Digital Class A... TV, TV Translator or TV Booster Station, FCC Form 346; 47 CFR 74.793(d); LPTV Out-of-Core Digital... collection requirements: 47 CFR 74.793(d) proposes that certain digital low power and TV translator stations...

  14. FPGA Based Low Power Router Design Using High Speed Transeceiver Logic IO Standard

    DEFF Research Database (Denmark)

    Thind, Vandana; Hussain, Dil muhammed Akbar

    2015-01-01

    and information. Router is main component of computer networks is an intelligent device uses to transfer data packets between various computer networks. Router must consume low power to perform its work in an efficient manner. To achieve the same the work has been done to make a FPGA based low power design using...

  15. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  16. A low-power bidirectional telemetry device with a near-field charging feature for a cardiac microstimulator.

    Science.gov (United States)

    Shuenn-Yuh Lee; Chih-Jen Cheng; Ming-Chun Liang

    2011-08-01

    In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

  17. Analytical Bounds on the Threads in IXP1200 Network Processor

    OpenAIRE

    Ramakrishna, STGS; Jamadagni, HS

    2003-01-01

    Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

  18. Adaptive Motion Estimation Processor for Autonomous Video Devices

    Directory of Open Access Journals (Sweden)

    Dias T

    2007-01-01

    Full Text Available Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 μm CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6 mW and 15 mW.

  19. Engineering embedded systems physics, programs, circuits

    CERN Document Server

    Hintenaus, Peter

    2015-01-01

    This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation. Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use. Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like ...

  20. PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

    Directory of Open Access Journals (Sweden)

    R. Maheswari

    2012-04-01

    Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

  1. Effect of processor temperature on film dosimetry

    International Nuclear Information System (INIS)

    Srivastava, Shiv P.; Das, Indra J.

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

  2. Optical Associative Processors For Visual Perception"

    Science.gov (United States)

    Casasent, David; Telfer, Brian

    1988-05-01

    We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

  3. Parallel processors and nonlinear structural dynamics algorithms and software

    Science.gov (United States)

    Belytschko, Ted

    1989-01-01

    A nonlinear structural dynamics finite element program was developed to run on a shared memory multiprocessor with pipeline processors. The program, WHAMS, was used as a framework for this work. The program employs explicit time integration and has the capability to handle both the nonlinear material behavior and large displacement response of 3-D structures. The elasto-plastic material model uses an isotropic strain hardening law which is input as a piecewise linear function. Geometric nonlinearities are handled by a corotational formulation in which a coordinate system is embedded at the integration point of each element. Currently, the program has an element library consisting of a beam element based on Euler-Bernoulli theory and trianglar and quadrilateral plate element based on Mindlin theory.

  4. Embedded System Implementation on FPGA System With μCLinux OS

    International Nuclear Information System (INIS)

    Amin, Ahmad Fairuz Muhd; Aris, Ishak; Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah

    2011-01-01

    Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

  5. Embedded System Implementation on FPGA System With μCLinux OS

    Science.gov (United States)

    Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

    2011-02-01

    Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

  6. Embedded System Implementation on FPGA System With {mu}CLinux OS

    Energy Technology Data Exchange (ETDEWEB)

    Amin, Ahmad Fairuz Muhd [Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Aris, Ishak [Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia); Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah, E-mail: gs20613@mutiara.upm.edu.my, E-mail: ishak@eng.upm.edu.my, E-mail: rsa@eng.upm.edu.my [Department of Computer and Communication Systems Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia)

    2011-02-15

    Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), {mu}Clinux. In this paper, an example of web server is explained and demonstrated

  7. Development of Innovative Design Processor

    International Nuclear Information System (INIS)

    Park, Y.S.; Park, C.O.

    2004-01-01

    The nuclear design analysis requires time-consuming and erroneous model-input preparation, code run, output analysis and quality assurance process. To reduce human effort and improve design quality and productivity, Innovative Design Processor (IDP) is being developed. Two basic principles of IDP are the document-oriented design and the web-based design. The document-oriented design is that, if the designer writes a design document called active document and feeds it to a special program, the final document with complete analysis, table and plots is made automatically. The active documents can be written with ordinary HTML editors or created automatically on the web, which is another framework of IDP. Using the proper mix-up of server side and client side programming under the LAMP (Linux/Apache/MySQL/PHP) environment, the design process on the web is modeled as a design wizard style so that even a novice designer makes the design document easily. This automation using the IDP is now being implemented for all the reload design of Korea Standard Nuclear Power Plant (KSNP) type PWRs. The introduction of this process will allow large reduction in all reload design efforts of KSNP and provide a platform for design and R and D tasks of KNFC. (authors)

  8. Onboard spectral imager data processor

    Science.gov (United States)

    Otten, Leonard J.; Meigs, Andrew D.; Franklin, Abraham J.; Sears, Robert D.; Robison, Mark W.; Rafert, J. Bruce; Fronterhouse, Donald C.; Grotbeck, Ronald L.

    1999-10-01

    Previous papers have described the concept behind the MightySat II.1 program, the satellite's Fourier Transform imaging spectrometer's optical design, the design for the spectral imaging payload, and its initial qualification testing. This paper discusses the on board data processing designed to reduce the amount of downloaded data by an order of magnitude and provide a demonstration of a smart spaceborne spectral imaging sensor. Two custom components, a spectral imager interface 6U VME card that moves data at over 30 MByte/sec, and four TI C-40 processors mounted to a second 6U VME and daughter card, are used to adapt the sensor to the spacecraft and provide the necessary high speed processing. A system architecture that offers both on board real time image processing and high-speed post data collection analysis of the spectral data has been developed. In addition to the on board processing of the raw data into a usable spectral data volume, one feature extraction technique has been incorporated. This algorithm operates on the basic interferometric data. The algorithm is integrated within the data compression process to search for uploadable feature descriptions.

  9. A data base processor semantics specification package

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

  10. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  11. Polymorphic Embedding of DSLs

    DEFF Research Database (Denmark)

    Hofer, Christian; Ostermann, Klaus; Rendel, Tillmann

    2008-01-01

    propose polymorphic embedding of DSLs, where many different interpretations of a DSL can be provided as reusable components, and show how polymorphic embedding can be realized in the programming language Scala. With polymorphic embedding, the static type-safety, modularity, composability and rapid...

  12. Accident sequence analysis for a BWR [Boiling Water Reactor] during low power and shutdown operations

    International Nuclear Information System (INIS)

    Whitehead, D.W.; Hake, T.M.

    1990-01-01

    Most previous Probabilistic Risk Assessments have excluded consideration of accidents initiated in low power and shutdown modes of operation. A study of the risk associated with operation in low power and shutdown is being performed at Sandia National Laboratories for a US Boiling Water Reactor (BWR). This paper describes the proposed methodology for the analysis of the risk associated with the operation of a BWR during low power and shutdown modes and presents preliminary information resulting from the application of the methodology. 2 refs., 2 tabs

  13. Low-Power Differential SRAM design for SOC Based on the 25-um Technology

    Science.gov (United States)

    Godugunuri, Sivaprasad; Dara, Naveen; Sambasiva Nayak, R.; Nayeemuddin, Md; Singh, Yadu, Dr.; Veda, R. N. S. Sunil

    2017-08-01

    In recent, the SOC styles area unit the vast complicated styles in VLSI these SOC styles having important low-power operations problems, to comprehend this we tend to enforced low-power SRAM. However these SRAM Architectures critically affects the entire power of SOC and competitive space. To beat the higher than disadvantages, during this paper, a low-power differential SRAM design is planned. The differential SRAM design stores multiple bits within the same cell, operates at minimum in operation low-tension and space per bit. The differential SRAM design designed supported the 25-um technology using Tanner-EDA Tool.

  14. Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU

    OpenAIRE

    Grasso, Ivan; Radojkovic, Petar; Rajovic, Nikola; Gelado Fernandez, Isaac; Ramírez Bellido, Alejandro

    2014-01-01

    A lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that could be used for HPC, their performance and energy capabilities have never been evaluated. Two reasons contribute to the above. Primarily, embedded GPUs until now, have not supported 64-bit floating point arithmetic - a requirement for HPC. Secondly, embedded GPUs did not pr...

  15. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  16. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  17. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

    1995-01-01

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  18. Self-Organization in Embedded Real-Time Systems

    CERN Document Server

    Brinkschulte, Uwe; Rettberg, Achim

    2013-01-01

    This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems.  Self-organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self-organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self-X features such as self-configuration, self-optimization, self-adaptation, self-healing and self-protection. Presents open components for embedded real-time adaptive and self-organizing applications; Describes innovative techniques in: scheduling, memory management, quality of service, communications supporting organic real-time applications; Covers multi-/many-core embedded systems supporting real-time adaptive systems and power-aware, adaptive hardware and software systems; Includes case studies of open embedded real-time self-organizi...

  19. Accuracy Limitations in Optical Linear Algebra Processors

    Science.gov (United States)

    Batsell, Stephen Gordon

    1990-01-01

    One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

  20. Delay-limited capacity of fading multiple access and broadcast channels in the low power regime

    KAUST Repository

    Rezki, Zouheir; Alouini, Mohamed-Slim

    2015-01-01

    show that for fading channels where the MAC capacity region is strictly positive, it has a multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power, the boundary

  1. On the capacity of multiaccess fading channels with full channel state information at low power regime

    KAUST Repository

    Rezki, Zouheir; Alouini, Mohamed-Slim

    2013-01-01

    multidimensional rectangle structure and thus is simply characterized by single user capacity points. More specifically, we show that at low power regime, the boundary surface of the capacity region shrinks to a single point corresponding to the sum rate maximizer

  2. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  3. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  4. Ultra low-power biomedical signal processing : An analog wavelet filter approach for pacemakers

    NARCIS (Netherlands)

    Pavlík Haddad, S.A.

    2006-01-01

    The purpose of this thesis is to describe novel signal processing methodologies and analog integrated circuit techniques for low-power biomedical systems. Physiological signals, such as the electrocardiogram (ECG), the electroencephalogram (EEG) and the electromyogram (EMG) are mostly

  5. Low-Power Large-Area Radiation Detector for Space Science Measurements

    Data.gov (United States)

    National Aeronautics and Space Administration — The objective of this task is to develop a low-power, large-area detectors from SiC, taking advantage of very low thermal noise characteristics and high radiation...

  6. Probabilistic safety assessments of nuclear power plants for low power and shutdown modes

    International Nuclear Information System (INIS)

    2000-03-01

    Within the past several years the results of nuclear power plant operating experience and performance of probabilistic safety assessments (PSAs) for low power and shutdown operating modes have revealed that the risk from operating modes other than full power may contribute significantly to the overall risk from plant operations. These early results have led to an increased focus on safety during low power and shutdown operating modes and to an increased interest of many plant operators in performing shutdown and low power PSAs. This publication was developed to provide guidance and insights on the performance of PSA for shutdown and low power operating modes. The preparation of this publication was initiated in 1994. Two technical consultants meetings were conducted in 1994 and one in February 1999 in support of the development of this report

  7. Compact Low-Power Driver for Deformable Mirror Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Boston Micromachines Corporation (BMC), a leading developer of unique, high-resolution micromachined deformable mirrors (DMs), will develop a compact, low-power,...

  8. Shutdown and low-power operation at commercial nuclear power plants in the United States

    International Nuclear Information System (INIS)

    1993-09-01

    The report contains the results of the NRC Staff's evaluation of shutdown and low-power operations at US commercial nuclear power plants. The report describes studies conducted by the staff in the following areas: Operating experience related to shutdown and low-power operations, probabilistic risk assessment of shutdown and low-power conditions and utility programs for planning and conducting activities during periods the plant is shut down. The report also documents evaluations of a number of technical issues regarding shutdown and low-power operations performed by the staff, including the principal findings and conclusions. Potential new regulatory requirements are discussed, as well as potential changes in NRC programs. A draft report was issued for comment in February 1992. This report is the final version and includes the responses to the comments along with the staff regulatory analysis of potential new requirements

  9. Low power consumption O-band VCSEL sources for upstream channels in PON systems

    DEFF Research Database (Denmark)

    Vegas Olmos, Juan José; Rodes Lopez, Roberto; Tafur Monroy, Idelfonso

    2012-01-01

    This paper presents an experimental validation of a low power optical network unit employing vertical-cavity surface-emitting lasers as upstream sources for passive optical networks with an increased power budget, enabling even larger splitting ratios....

  10. Backreflectance from the blood plexus in the skin under the low-power laser heating

    Energy Technology Data Exchange (ETDEWEB)

    Naumenko, E.K. [Institute of Physics National Academy of Sciences of Belarus, Nezavisimosti Avenue, 68, 220072 Minsk (Belarus); Korolevich, A.N. [Institute of Physics National Academy of Sciences of Belarus, Nezavisimosti Avenue, 68, 220072 Minsk (Belarus) and Physics Department, Minho University, Campus Gualtar, 4709 Braga (Portugal)]. E-mail: akaralevich@fisica.uminho.pt; Dubina, N.S. [GP ' MTZ Medservice' , Stahanovskaia Street, 10A, 220009 Minsk (Belarus); Vecherinsky, S.I. [GP ' MTZ Medservice' , Stahanovskaia Street, 10A, 220009 Minsk (Belarus); Belsley, M. [Physics Department, Minho University, Campus Gualtar, 4709 Braga (Portugal)

    2007-07-15

    The intensity of light backscattered when low-power laser radiation is incident on the skin is investigated in vivo. The exposure of blood to low-power laser light in the absorption range of haemoglobin leads to an increased intensity of the backscattered light. The theoretical calculation using the existing optical model of erythrocyte aggregation suggests that the fragmentation of erythrocyte aggregates is the most probable mechanism leading to the enhanced backscattering.

  11. Multichannel analyzer embedded in FPGA

    International Nuclear Information System (INIS)

    Garcia D, A.; Hernandez D, V. M.; Vega C, H. R.; Ordaz G, O. O.; Bravo M, I.

    2017-10-01

    Ionizing radiation has different applications, so it is a very significant and useful tool, which in turn can be dangerous for living beings if they are exposed to uncontrolled doses. However, due to its characteristics, it cannot be perceived by any of the senses of the human being, so that in order to know the presence of it, radiation detectors and additional devices are required to quantify and classify it. A multichannel analyzer is responsible for separating the different pulse heights that are generated in the detectors, in a certain number of channels; according to the number of bits of the analog to digital converter. The objective of the work was to design and implement a multichannel analyzer and its associated virtual instrument, for nuclear spectrometry. The components of the multichannel analyzer were created in VHDL hardware description language and packaged in the Xilinx Vivado design suite, making use of resources such as the ARM processing core that the System on Chip Zynq contains and the virtual instrument was developed on the LabView programming graphics platform. The first phase was to design the hardware architecture to be embedded in the FPGA and for the internal control of the multichannel analyzer the application was generated for the ARM processor in C language. For the second phase, the virtual instrument was developed for the management, control and visualization of the results. The data obtained as a result of the development of the system were observed graphically in a histogram showing the spectrum measured. The design of the multichannel analyzer embedded in FPGA was tested with two different radiation detection systems (hyper-pure germanium and scintillation) which allowed determining that the spectra obtained are similar in comparison with the commercial multichannel analyzers. (Author)

  12. Review of the status of low power research reactors and considerations for its development

    International Nuclear Information System (INIS)

    Lim, In Cheol; Wu, Sang Ik; Lee, Byung Chul; Ha, Jae Joo

    2012-01-01

    At present, 232 research reactors in the world are in operation and two thirds of them have a power less than 1 MW. Many countries have used research reactors as the tools for educating and training students or engineers and for scientific service such as neutron activation analysis. As the introduction of a research reactor is considered a stepping stone for a nuclear power development program, many newcomers are considering having a low power research reactor. The IAEA has continued to provide forums for the exchange of information and experiences regarding low power research reactors. Considering these, the Agency is recently working on the preparation of a guide for the preparation of technical specification possibly for a member state to use when wanting to purchase a low power research reactor. In addition, ANS has stated that special consideration should be given to the continued national support to maintain and expand research and test reactor programs and to the efforts in identifying and addressing the future needs by working toward the development and deployment of next generation nuclear research and training facilities. Thus, more interest will be given to low power research reactors and its role as a facility for education and training. Considering these, the status of low power research reactors was reviewed, and some aspects to be considered in developing a low power research reactor were studied

  13. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

  14. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar.

    Science.gov (United States)

    Tsao, Kuei-Chi; Lee, Ling; Chu, Ta-Shun; Huang, Yuan-Hao

    2018-04-05

    Complementary metal-oxide-semiconductor (CMOS) radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP) is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA). The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  15. A Two-Stage Reconstruction Processor for Human Detection in Compressive Sensing CMOS Radar

    Directory of Open Access Journals (Sweden)

    Kuei-Chi Tsao

    2018-04-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS radar has recently gained much research attraction because small and low-power CMOS devices are very suitable for deploying sensing nodes in a low-power wireless sensing system. This study focuses on the signal processing of a wireless CMOS impulse radar system that can detect humans and objects in the home-care internet-of-things sensing system. The challenges of low-power CMOS radar systems are the weakness of human signals and the high computational complexity of the target detection algorithm. The compressive sensing-based detection algorithm can relax the computational costs by avoiding the utilization of matched filters and reducing the analog-to-digital converter bandwidth requirement. The orthogonal matching pursuit (OMP is one of the popular signal reconstruction algorithms for compressive sensing radar; however, the complexity is still very high because the high resolution of human respiration leads to high-dimension signal reconstruction. Thus, this paper proposes a two-stage reconstruction algorithm for compressive sensing radar. The proposed algorithm not only has lower complexity than the OMP algorithm by 75% but also achieves better positioning performance than the OMP algorithm especially in noisy environments. This study also designed and implemented the algorithm by using Vertex-7 FPGA chip (Xilinx, San Jose, CA, USA. The proposed reconstruction processor can support the 256 × 13 real-time radar image display with a throughput of 28.2 frames per second.

  16. OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

    Science.gov (United States)

    Kimura, Keiji; Mase, Masayoshi; Mikami, Hiroki; Miyamoto, Takamichi; Shirako, Jun; Kasahara, Hironori

    OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory; data transfer using a DMA controller; and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API

  17. Architectural design and analysis of a programmable image processor

    International Nuclear Information System (INIS)

    Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

    2003-01-01

    In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

  18. A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

    Directory of Open Access Journals (Sweden)

    Muhammad Asif

    2015-01-01

    Full Text Available One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

  19. Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

    Directory of Open Access Journals (Sweden)

    John M. McNichols

    2013-01-01

    Full Text Available This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC. While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.

  20. Embedding beyond electrostatics

    DEFF Research Database (Denmark)

    Nåbo, Lina J.; Olsen, Jógvan Magnus Haugaard; Holmgaard List, Nanna

    2016-01-01

    We study excited states of cholesterol in solution and show that, in this specific case, solute wave-function confinement is the main effect of the solvent. This is rationalized on the basis of the polarizable density embedding scheme, which in addition to polarizable embedding includes non-electrostatic...... repulsion that effectively confines the solute wave function to its cavity. We illustrate how the inclusion of non-electrostatic repulsion results in a successful identification of the intense π → π∗ transition, which was not possible using an embedding method that only includes electrostatics....... This underlines the importance of non-electrostatic repulsion in quantum-mechanical embedding-based methods....

  1. Embedded systems handbook

    CERN Document Server

    Zurawski, Richard

    2005-01-01

    Embedded systems are nearly ubiquitous, and books on individual topics or components of embedded systems are equally abundant. Unfortunately, for those designers who thirst for knowledge of the big picture of embedded systems there is not a drop to drink. Until now. The Embedded Systems Handbook is an oasis of information, offering a mix of basic and advanced topics, new solutions and technologies arising from the most recent research efforts, and emerging trends to help you stay current in this ever-changing field.With preeminent contributors from leading industrial and academic institutions

  2. Web Server Embedded System

    Directory of Open Access Journals (Sweden)

    Adharul Muttaqin

    2014-07-01

    Full Text Available Abstrak Embedded sistem saat ini menjadi perhatian khusus pada teknologi komputer, beberapa sistem operasi linux dan web server yang beraneka ragam juga sudah dipersiapkan untuk mendukung sistem embedded, salah satu aplikasi yang dapat digunakan dalam operasi pada sistem embedded adalah web server. Pemilihan web server pada lingkungan embedded saat ini masih jarang dilakukan, oleh karena itu penelitian ini dilakukan dengan menitik beratkan pada dua buah aplikasi web server yang tergolong memiliki fitur utama yang menawarkan “keringanan” pada konsumsi CPU maupun memori seperti Light HTTPD dan Tiny HTTPD. Dengan menggunakan parameter thread (users, ramp-up periods, dan loop count pada stress test embedded system, penelitian ini menawarkan solusi web server manakah diantara Light HTTPD dan Tiny HTTPD yang memiliki kecocokan fitur dalam penggunaan embedded sistem menggunakan beagleboard ditinjau dari konsumsi CPU dan memori. Hasil penelitian menunjukkan bahwa dalam hal konsumsi CPU pada beagleboard embedded system lebih disarankan penggunaan Light HTTPD dibandingkan dengan tiny HTTPD dikarenakan terdapat perbedaan CPU load yang sangat signifikan antar kedua layanan web tersebut Kata kunci: embedded system, web server Abstract Embedded systems are currently of particular concern in computer technology, some of the linux operating system and web server variegated also prepared to support the embedded system, one of the applications that can be used in embedded systems are operating on the web server. Selection of embedded web server on the environment is still rarely done, therefore this study was conducted with a focus on two web application servers belonging to the main features that offer a "lightness" to the CPU and memory consumption as Light HTTPD and Tiny HTTPD. By using the parameters of the thread (users, ramp-up periods, and loop count on a stress test embedded systems, this study offers a solution of web server which between the Light

  3. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    Energy Technology Data Exchange (ETDEWEB)

    Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  4. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    International Nuclear Information System (INIS)

    Barhen, Jacob; Kerekes, Ryan A.; St Charles, Jesse Lee; Buckner, Mark A.

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  5. Embedded systems handbook networked embedded systems

    CERN Document Server

    Zurawski, Richard

    2009-01-01

    Considered a standard industry resource, the Embedded Systems Handbook provided researchers and technicians with the authoritative information needed to launch a wealth of diverse applications, including those in automotive electronics, industrial automated systems, and building automation and control. Now a new resource is required to report on current developments and provide a technical reference for those looking to move the field forward yet again. Divided into two volumes to accommodate this growth, the Embedded Systems Handbook, Second Edition presents a comprehensive view on this area

  6. Low-power analog integrated circuits for wireless ECG acquisition systems.

    Science.gov (United States)

    Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

    2012-09-01

    This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

  7. The data embedding method

    Energy Technology Data Exchange (ETDEWEB)

    Sandford, M.T. II; Bradley, J.N.; Handel, T.G.

    1996-06-01

    Data embedding is a new steganographic method for combining digital information sets. This paper describes the data embedding method and gives examples of its application using software written in the C-programming language. Sandford and Handel produced a computer program (BMPEMBED, Ver. 1.51 written for IBM PC/AT or compatible, MS/DOS Ver. 3.3 or later) that implements data embedding in an application for digital imagery. Information is embedded into, and extracted from, Truecolor or color-pallet images in Microsoft{reg_sign} bitmap (.BMP) format. Hiding data in the noise component of a host, by means of an algorithm that modifies or replaces the noise bits, is termed {open_quote}steganography.{close_quote} Data embedding differs markedly from conventional steganography, because it uses the noise component of the host to insert information with few or no modifications to the host data values or their statistical properties. Consequently, the entropy of the host data is affected little by using data embedding to add information. The data embedding method applies to host data compressed with transform, or {open_quote}lossy{close_quote} compression algorithms, as for example ones based on discrete cosine transform and wavelet functions. Analysis of the host noise generates a key required for embedding and extracting the auxiliary data from the combined data. The key is stored easily in the combined data. Images without the key cannot be processed to extract the embedded information. To provide security for the embedded data, one can remove the key from the combined data and manage it separately. The image key can be encrypted and stored in the combined data or transmitted separately as a ciphertext much smaller in size than the embedded data. The key size is typically ten to one-hundred bytes, and it is in data an analysis algorithm.

  8. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  9. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-02-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  10. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

  11. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Baird, S.A.; Biddulph, P.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  12. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  13. Embedded Linux platform for data acquisition systems

    International Nuclear Information System (INIS)

    Patel, Jigneshkumar J.; Reddy, Nagaraj; Kumari, Praveena; Rajpal, Rachana; Pujara, Harshad; Jha, R.; Kalappurakkal, Praveen

    2014-01-01

    Highlights: • The design and the development of data acquisition system on FPGA based reconfigurable hardware platform. • Embedded Linux configuration and compilation for FPGA based systems. • Hardware logic IP core and its Linux device driver development for the external peripheral to interface it with the FPGA based system. - Abstract: This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx

  14. Embedded Linux platform for data acquisition systems

    Energy Technology Data Exchange (ETDEWEB)

    Patel, Jigneshkumar J., E-mail: jjp@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Reddy, Nagaraj, E-mail: nagaraj.reddy@coreel.com [Sandeepani School of Embedded System Design, Bangalore, Karnataka (India); Kumari, Praveena, E-mail: praveena@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Rajpal, Rachana, E-mail: rachana@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Pujara, Harshad, E-mail: pujara@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Jha, R., E-mail: rjha@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Kalappurakkal, Praveen, E-mail: praveen.k@coreel.com [Sandeepani School of Embedded System Design, Bangalore, Karnataka (India)

    2014-05-15

    Highlights: • The design and the development of data acquisition system on FPGA based reconfigurable hardware platform. • Embedded Linux configuration and compilation for FPGA based systems. • Hardware logic IP core and its Linux device driver development for the external peripheral to interface it with the FPGA based system. - Abstract: This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx

  15. Radiation Tolerant Embedded Memory

    National Research Council Canada - National Science Library

    Smith, Brian

    2003-01-01

    ... event effects, and will scale to smaller geometries to provide the same performance. we then designed arrays of that memory to build up blocks to be used in complex Cool-RAD(tm) parts such as microprocessors and digital signal processors.

  16. Real-Time Monitoring and Fault Diagnosis of a Low Power Hub Motor Using Feedforward Neural Network

    Directory of Open Access Journals (Sweden)

    Mehmet Şimşir

    2016-01-01

    Full Text Available Low power hub motors are widely used in electromechanical systems such as electrical bicycles and solar vehicles due to their robustness and compact structure. Such systems driven by hub motors (in wheel motors encounter previously defined and undefined faults under operation. It may inevitably lead to the interruption of the electromechanical system operation; hence, economic losses take place at certain times. Therefore, in order to maintain system operation sustainability, the motor should be precisely monitored and the faults are diagnosed considering various significant motor parameters. In this study, the artificial feedforward backpropagation neural network approach is proposed to real-time monitor and diagnose the faults of the hub motor by measuring seven main system parameters. So as to construct a necessary model, we trained the model, using a data set consisting of 4160 samples where each has 7 parameters, by the MATLAB environment until the best model is obtained. The results are encouraging and meaningful for the specific motor and the developed model may be applicable to other types of hub motors. The prosperous model of the whole system was embedded into Arduino Due microcontroller card and the mobile real-time monitoring and fault diagnosis system prototype for hub motor was designed and manufactured.

  17. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  18. Parallel processor for fast event analysis

    International Nuclear Information System (INIS)

    Hensley, D.C.

    1983-01-01

    Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

  19. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  20. Smart Multicore Embedded Systems

    DEFF Research Database (Denmark)

    This book provides a single-source reference to the state-of-the-art of high-level programming models and compilation tool-chains for embedded system platforms. The authors address challenges faced by programmers developing software to implement parallel applications in embedded systems, where ve...

  1. Java Source Code Analysis for API Migration to Embedded Systems

    Energy Technology Data Exchange (ETDEWEB)

    Winter, Victor [Univ. of Nebraska, Omaha, NE (United States); McCoy, James A. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Guerrero, Jonathan [Univ. of Nebraska, Omaha, NE (United States); Reinke, Carl Werner [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Perry, James Thomas [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2015-02-01

    Embedded systems form an integral part of our technological infrastructure and oftentimes play a complex and critical role within larger systems. From the perspective of reliability, security, and safety, strong arguments can be made favoring the use of Java over C in such systems. In part, this argument is based on the assumption that suitable subsets of Java’s APIs and extension libraries are available to embedded software developers. In practice, a number of Java-based embedded processors do not support the full features of the JVM. For such processors, source code migration is a mechanism by which key abstractions offered by APIs and extension libraries can made available to embedded software developers. The analysis required for Java source code-level library migration is based on the ability to correctly resolve element references to their corresponding element declarations. A key challenge in this setting is how to perform analysis for incomplete source-code bases (e.g., subsets of libraries) from which types and packages have been omitted. This article formalizes an approach that can be used to extend code bases targeted for migration in such a manner that the threats associated the analysis of incomplete code bases are eliminated.

  2. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  3. Simulation of a parallel processor on a serial processor: The neutron diffusion equation

    International Nuclear Information System (INIS)

    Honeck, H.C.

    1981-01-01

    Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

  4. Low Power Design with High-Level Power Estimation and Power-Aware Synthesis

    CERN Document Server

    Ahuja, Sumit; Shukla, Sandeep Kumar

    2012-01-01

    Low-power ASIC/FPGA based designs are important due to the need for extended battery life, reduced form factor, and lower packaging and cooling costs for electronic devices. These products require fast turnaround time because of the increasing demand for handheld electronic devices such as cell-phones, PDAs and high performance machines for data centers. To achieve short time to market, design flows must facilitate a much shortened time-to-product requirement. High-level modeling, architectural exploration and direct synthesis of design from high level description enable this design process. This book presents novel research techniques, algorithms,methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design. Integrates power estimation and reduction for high level synthesis, with low-power, high-level design; Shows spec...

  5. Design of Low Power Multiplier with Energy Efficient Full Adder Using DPTAAL

    Directory of Open Access Journals (Sweden)

    A. Kishore Kumar

    2013-01-01

    Full Text Available Asynchronous adiabatic logic (AAL is a novel lowpower design technique which combines the energy saving benefits of asynchronous systems with adiabatic benefits. In this paper, energy efficient full adder using double pass transistor with asynchronous adiabatic logic (DPTAAL is used to design a low power multiplier. Asynchronous adiabatic circuits are very low power circuits to preserve energy for reuse, which reduces the amount of energy drawn directly from the power supply. In this work, an 8×8 multiplier using DPTAAL is designed and simulated, which exhibits low power and reliable logical operations. To improve the circuit performance at reduced voltage level, double pass transistor logic (DPL is introduced. The power results of the proposed multiplier design are compared with the conventional CMOS implementation. Simulation results show significant improvement in power for clock rates ranging from 100 MHz to 300 MHz.

  6. Laser Cutting of Thick Diamond Films Using Low-Power Laser

    Energy Technology Data Exchange (ETDEWEB)

    Park, Y.J.; Baik, Y.J. [Korea Institute of Science and Technology, Seoul (Korea)

    2000-02-01

    Laser cutting of thick diamond films is studied rising a low-power(10 W) copper vapor laser. Due to the existence of the saturation depth in laser cutting, thick diamond films are not easily cut by low-power lasers. In this study, we have adopted a low thermal- conductivity underlayer of alumina and a heating stage (up to 500 deg. C in air) to prevent the laser energy from consuming-out and, in turn, enhance the cutting efficiency. Aspect ratio increases twice from 3.5 to 7 when the alumina underlayer used. Adopting a heating stage also increases aspect ratio and more than 10 is obtained at higher temperatures than 400 deg. C. These results show that thick diamond films can be cut, with low-power lasers, simply by modifying the thermal property of underlayer. (author). 13 refs., 5 figs.

  7. Embedded engineering education

    CERN Document Server

    Kaštelan, Ivan; Temerinac, Miodrag; Barak, Moshe; Sruk, Vlado

    2016-01-01

    This book focuses on the outcome of the European research project “FP7-ICT-2011-8 / 317882: Embedded Engineering Learning Platform” E2LP. Additionally, some experiences and researches outside this project have been included. This book provides information about the achieved results of the E2LP project as well as some broader views about the embedded engineering education. It captures project results and applications, methodologies, and evaluations. It leads to the history of computer architectures, brings a touch of the future in education tools and provides a valuable resource for anyone interested in embedded engineering education concepts, experiences and material. The book contents 12 original contributions and will open a broader discussion about the necessary knowledge and appropriate learning methods for the new profile of embedded engineers. As a result, the proposed Embedded Computer Engineering Learning Platform will help to educate a sufficient number of future engineers in Europe, capable of d...

  8. Silicon on ferroelectic insulator field effect transistor (SOF-FET) a new device for the next generation ultra low power circuits

    Science.gov (United States)

    Es-Sakhi, Azzedin D.

    Field effect transistors (FETs) are the foundation for all electronic circuits and processors. These devices have progressed massively to touch its final steps in sub-nanometer level. Left and right proposals are coming to rescue this progress. Emerging nano-electronic devices (resonant tunneling devices, single-atom transistors, spin devices, Heterojunction Transistors rapid flux quantum devices, carbon nanotubes, and nanowire devices) took a vast share of current scientific research. Non-Si electronic materials like III-V heterostructure, ferroelectric, carbon nanotubes (CNTs), and other nanowire based designs are in developing stage to become the core technology of non-classical CMOS structures. FinFET present the current feasible commercial nanotechnology. The scalability and low power dissipation of this device allowed for an extension of silicon based devices. High short channel effect (SCE) immunity presents its major advantage. Multi-gate structure comes to light to improve the gate electrostatic over the channel. The new structure shows a higher performance that made it the first candidate to substitute the conventional MOSFET. The device also shows a future scalability to continue Moor's Law. Furthermore, the device is compatible with silicon fabrication process. Moreover, the ultra-low-power (ULP) design required a subthreshold slope lower than the thermionic-emission limit of 60mV/ decade (KT/q). This value was unbreakable by the new structure (SOI-FinFET). On the other hand most of the previews proposals show the ability to go beyond this limit. However, those pre-mentioned schemes have publicized a very complicated physics, design difficulties, and process non-compatibility. The objective of this research is to discuss various emerging nano-devices proposed for ultra-low-power designs and their possibilities to replace the silicon devices as the core technology in the future integrated circuit. This thesis proposes a novel design that exploits the

  9. Special purpose processors for high energy physics applications

    International Nuclear Information System (INIS)

    Verkerk, C.

    1978-01-01

    The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

  10. VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture

    NARCIS (Netherlands)

    Gruian, Flavius; Westmijze, M.

    2008-01-01

    This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The

  11. Composable local memory organisation for streaming applications on embedded MPSoCs

    NARCIS (Netherlands)

    Ambrose, J.; Molnos, A.; Nelson, A.; Cotofana, S.; Goossens, K.G.W.; Juurlink, B.

    2011-01-01

    Multi-Processor Systems on a Chip (MPSoCs) are suitable platforms for the implementation of complex embedded applications. An MPSoC is composable if the functional and temporal behaviour of each application is independent of the absence or presence of other applications. Composability is required

  12. A Low-Power Correlator ASIC for Arrays with Many Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

  13. An ultra-low-power CMOS temperature sensor for RFID applications

    International Nuclear Information System (INIS)

    Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao

    2009-01-01

    An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-μm CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 μA and 1.8 V for continuous operation and achieves an accuracy of ±0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

  14. Advanced Technology for Ultra-Low Power System-on-Chip (SoC)

    Science.gov (United States)

    2017-06-01

    was proposed for lower power applications with Ioff=10pA/μm and VDD=0.5V. In this project, the optimized structure shows great potential in both Lg...AFRL-RY-WP-TR-2017-0115 ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON-CHIP (SoC) Jason Woo, Weicong Li, and Peng Lu University of California...September 2015 – 31 March 2017 4. TITLE AND SUBTITLE ADVANCED TECHNOLOGY FOR ULTRA-LOW POWER SYSTEM-ON- CHIP (SoC) 5a. CONTRACT NUMBER FA8650-15-1-7574 5b

  15. Ultra-low power transmitter for encoding non-MR signals in Magnetic Resonance (MR) recordings

    DEFF Research Database (Denmark)

    Petersen, Jan Raagaard; Pedersen, Jan Ole; Zhurbenko, Vitaliy

    collection of data from non-MRI sensors. The transmitter consumes only 1.3mW while transmitting 2.7µW at 120MHz with high frequency stability. The presented design is useful in low power applications requiring high frequency stability and is intended for wireless transmission of non-MR signal recordings......Advancing Magnetic Resonance Imaging (MRI) technology requires integration of the MRI scanners with sensors and systems for monitoring various non-MRI signals. In this paper, we present design and integration of a low power AM radio transmitter into a 3T MRI scanner, which can be used for efficient...

  16. An ultra-low-power CMOS temperature sensor for RFID applications

    Energy Technology Data Exchange (ETDEWEB)

    Xu Conghui; Gao Peijun; Che Wenyi; Tan Xi; Yan Na; Min Hao, E-mail: yanna@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-04-15

    An ultra-low-power CMOS temperature sensor with analog-to-digital readout circuitry for RFID applications was implemented in a 0.18-mum CMOS process. To achieve ultra-low power consumption, an error model is proposed and the corresponding novel temperature sensor front-end with a new double-measure method is presented. Analog-to-digital conversion is accomplished by a sigma-delta converter. The complete system consumes only 26 muA and 1.8 V for continuous operation and achieves an accuracy of +-0.65 deg. C from -20 to 120 deg. C after calibration at one temperature.

  17. Optimizing efficiency on conventional transformer based low power AC/DC standby power supplies

    DEFF Research Database (Denmark)

    Nielsen, Nils

    2004-01-01

    This article describes the research results for simple and cheap methods to reduce the idle- and load-losses in very low power conventional transformer based power supplies intended for standby usage. In this case "very low power" means 50 Hz/230 V-AC to 5 V-DC@1 W. The efficiency is measured...... on two common power supply topologies designed for this power level. The two described topologies uses either a series (or linear) or a buck regulation approach. Common to the test power supplies is they either are using a standard cheap off-the-shelf transformer, or one, which are loss optimized by very...

  18. Embedded Linux in het onderwijs

    NARCIS (Netherlands)

    Dr Ruud Ermers

    2008-01-01

    Embedded Linux wordt bij steeds meer grote bedrijven ingevoerd als embedded operating system. Binnen de opleiding Technische Informatica van Fontys Hogeschool ICT is Embedded Linux geïntroduceerd in samenwerking met het lectoraat Architectuur van Embedded Systemen. Embedded Linux is als vakgebied

  19. Research on applications of ARM-LINUX embedded systems in manufacturing the nuclear equipment

    International Nuclear Information System (INIS)

    Nguyen Van Sy; Phan Luong Tuan; Nguyen Xuan Vinh; Dang Quang Bao

    2016-01-01

    A new microprocessor system that is ARM processor with open source Linux operating system is studied with the objective to apply ARM-Linux embedded systems in manufacturing the nuclear equipment. We use the development board of the company to learn and to build the workflow for an embedded system, then basing on the knowledge we design a motherboard embedded systems interface with the peripherals is buttons, LEDs through GPIO interface and connected with GM counting system via RS232 interface. The results of this study are: i) The procedures for working with embedded systems: process customization, installation embedded operating system and installation process, configure the development tools on the host computer; ii) ARM-Linux motherboard embedded systems interface with the peripherals and GM counting system, indicating the counts from GM counting system on the touch screen. (author)

  20. Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture

    Science.gov (United States)

    Klarer, Paul R.; Hayward, David R.; Amai, Wendy A.

    2006-10-03

    This invention relates to system architectures, specifically failure-tolerant and self-reconfiguring embedded system architectures. The invention provides both a method and architecture for redundancy. There can be redundancy in both software and hardware for multiple levels of redundancy. The invention provides a self-reconfiguring architecture for activating redundant modules whenever other modules fail. The architecture comprises: a communication backbone connected to two or more processors and software modules running on each of the processors. Each software module runs on one processor and resides on one or more of the other processors to be available as a backup module in the event of failure. Each module and backup module reports its status over the communication backbone. If a primary module does not report, its backup module takes over its function. If the primary module becomes available again, the backup module returns to its backup status.

  1. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  2. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

  3. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

  4. Beeldverwerking met de Micron Automatic Processor

    OpenAIRE

    Goyens, Frank

    2017-01-01

    Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

  5. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

  6. Simplifying cochlear implant speech processor fitting

    NARCIS (Netherlands)

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

  7. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    This book presents the papers given at a conference which reviewed the new developments in parallel and vector processing. Topics considered at the conference included hardware (array processors, supercomputers), programming languages, software aids, numerical methods (e.g., Monte Carlo algorithms, iterative methods, finite elements, optimization), and applications (e.g., neutron transport theory, meteorology, image processing)

  8. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  9. User manual Dieka PreProcessor

    NARCIS (Netherlands)

    Valkering, Kasper

    2000-01-01

    This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

  10. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  11. Event analysis using a massively parallel processor

    International Nuclear Information System (INIS)

    Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.

    1990-01-01

    This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable

  12. Introduction to embedded systems using microcontrollers and the MSP430

    CERN Document Server

    Jiménez, Manuel; Couvertier, Isidoro

    2014-01-01

    This textbook serves as an introduction to the subject of embedded systems design, using microcontrollers as core components.  It develops concepts from the ground up, covering the development of embedded systems technology, architectural and organizational aspects of controllers and systems, processor models, and peripheral devices. Since microprocessor-based embedded systems tightly blend hardware and software components in a single application, the book also introduces the subjects of data representation formats, data operations, and programming styles. The practical component of the book is tailored around the architecture of a widely used Texas Instrument’s microcontroller, the MSP430. Instructor’s supplemental materials available through the book web site include solutions to selected problems and exercises and power point slides for lectures. The site also includes materials for students that include links to application examples and to sites elsewhere in the web with application notes, downloadab...

  13. Brauer type embedding problems

    CERN Document Server

    Ledet, Arne

    2005-01-01

    This monograph is concerned with Galois theoretical embedding problems of so-called Brauer type with a focus on 2-groups and on finding explicit criteria for solvability and explicit constructions of the solutions. The advantage of considering Brauer type embedding problems is their comparatively simple condition for solvability in the form of an obstruction in the Brauer group of the ground field. This book presupposes knowledge of classical Galois theory and the attendant algebra. Before considering questions of reducing the embedding problems and reformulating the solvability criteria, the

  14. Time-dependent embedding

    OpenAIRE

    Inglesfield, J. E.

    2007-01-01

    A method of solving the time-dependent Schr\\"odinger equation is presented, in which a finite region of space is treated explicitly, with the boundary conditions for matching the wave-functions on to the rest of the system replaced by an embedding term added on to the Hamiltonian. This time-dependent embedding term is derived from the Fourier transform of the energy-dependent embedding potential, which embeds the time-independent Schr\\"odinger equation. Results are presented for a one-dimensi...

  15. The selection of embedded computer using in the nuclear physics instruments

    International Nuclear Information System (INIS)

    Zhang Jianchuan; Nan Gangyang; Wang Yanyu; Su Hong

    2010-01-01

    It introduces the requirement for embedded PC and the benefits of using it in the experimental nuclear physics instrument developing and improving project. A cording to the specific requirements in the project of improving laboratory instruments. several kinds of embedded computer are compared and specifically tested. Thus, a x86 architecture embedded computer, which have ultra-low-power consumption and a small in size, is selected to be the main component of the controller using in the nuclear physics instrument, and this will be used in the high-speed data acquisition and electronic control system. (authors)

  16. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  17. Trends in languages for embedded systems

    International Nuclear Information System (INIS)

    Boasson, M.

    1986-01-01

    Characteristics of embedded systems are discussed. In particular, the role of the computer in such systems is highlighted. Special emphasis is placed on the different requirements different kinds of systems may place on program execution. From such requirements necessary programming constructs are derived and in an overview of currently used languages it is shown how evolution led to modern languages like Ada and CHILL. With the advent of cheap, fast and small processing units, exploitation of parallelism for enhancing system performance is becoming increasingly tempting. However, few languages support the design of such multi-processor systems. Some methods for dealing with this problem are discussed. Finally, systems architectures and associated languages for the use of techniques originally developed for AI research are adumbrated. (Auth.)

  18. Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

    DEFF Research Database (Denmark)

    Sparsø, Jens

    2012-01-01

    This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

  19. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

    1983-01-01

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  20. Optimizing Parameters of Axial Pressure-Compounded Ultra-Low Power Impulse Turbines at Preliminary Design

    Science.gov (United States)

    Kalabukhov, D. S.; Radko, V. M.; Grigoriev, V. A.

    2018-01-01

    Ultra-low power turbine drives are used as energy sources in auxiliary power systems, energy units, terrestrial, marine, air and space transport within the confines of shaft power N td = 0.01…10 kW. In this paper we propose a new approach to the development of surrogate models for evaluating the integrated efficiency of multistage ultra-low power impulse turbine with pressure stages. This method is based on the use of existing mathematical models of ultra-low power turbine stage efficiency and mass. It has been used in a method for selecting the rational parameters of two-stage axial ultra-low power turbine. The article describes the basic features of an algorithm for two-stage turbine parameters optimization and for efficiency criteria evaluating. Pledged mathematical models are intended for use at the preliminary design of turbine drive. The optimization method was tested at preliminary design of an air starter turbine. Validation was carried out by comparing the results of optimization calculations and numerical gas-dynamic simulation in the Ansys CFX package. The results indicate a sufficient accuracy of used surrogate models for axial two-stage turbine parameters selection

  1. Low-Power Silicon-based Thermal Sensors and Actuators for Chemical Applications

    NARCIS (Netherlands)

    Vereshchagina, E.

    2011-01-01

    In the Hot Silicon project low and ultra-low-power Si-based hot surface devices have been developed, i.e. thermal sensors and actuators, for application in catalytic gas micro sensors, micro- and nano- calorimeters. This work include several scientific and technological aspects: • Design and

  2. 77 FR 10576 - Methodology for Low Power/Shutdown Fire PRA

    Science.gov (United States)

    2012-02-22

    ... NUCLEAR REGULATORY COMMISSION [NRC-2011-0295] Methodology for Low Power/Shutdown Fire PRA AGENCY.../Shutdown Fire PRA.'' In response to request from members of the public, the NRC is extending the public... risk assessment (PRA) method for quantitatively analyzing fire risk in commercial nuclear power plants...

  3. AutoSync : Automatic duty-cycle control for synchronous low-power listening

    DEFF Research Database (Denmark)

    Hansen, Morten Tranberg; Kusy, Branislav; Jurdak, Raja

    2012-01-01

    Low power listening (LPL) has been widely adopted to save energy in wireless sensor networks. However, LPL is ineffective in adapting to dynamic networks with asymmetric traffic patterns, as it sets a network-wide check interval. As a result, nodes with low data traffic waste significant energy...

  4. Adiabatic superconducting cells for ultra-low-power artificial neural networks

    Directory of Open Access Journals (Sweden)

    Andrey E. Schegolev

    2016-10-01

    Full Text Available We propose the concept of using superconducting quantum interferometers for the implementation of neural network algorithms with extremely low power dissipation. These adiabatic elements are Josephson cells with sigmoid- and Gaussian-like activation functions. We optimize their parameters for application in three-layer perceptron and radial basis function networks.

  5. Channel coding study for ultra-low power wireless design of autonomous sensor works

    NARCIS (Netherlands)

    Zhang, P.; Huang, Li; Willems, F.M.J.

    2011-01-01

    Ultra-low power wireless design is highly demanded for building up autonomous wireless sensor networks (WSNs) for many application areas. To keep certain quality of service with limited power budget, channel coding techniques can be applied to maintain the robustness and reliability of WSNs. In this

  6. A high resolution, low power time-of-flight system for the space experiment AMS

    International Nuclear Information System (INIS)

    Alvisi, D.; Anselmo, F.; Baldini, L.; Bari, G.; Basile, M.; Bellagamba, L.; Bruni, A.; Bruni, G.; Boscherini, D.; Casadei, D.; Cara Romeo, G.; Castellini, G.; Cifarelli, L.; Cindolo, F.; Contin, A.; De Pasquale, S.; Giusti, P.; Iacobucci, G.; Laurenti, G.; Levi, G.; Margotti, A.; Massam, T.; Nania, R.; Palmonari, F.; Polini, A.; Recupero, S.; Sartorelli, G.; Williams, C.; Zichichi, A.

    1999-01-01

    The system of plastic scintillator counters for the AMS experiment is described. The main characteristics of the detector are: (a) large sensitive area (four 1.6 m 2 planes) with small dead space; (b) low-power consumption (150 W for the power and the read-out electronics of 336 PMs); (c) 120 ps time resolution

  7. Low-power laser therapy for carpal tunnel syndrome: effective optical power

    Directory of Open Access Journals (Sweden)

    Yan Chen

    2016-01-01

    Full Text Available Low-power laser therapy has been used for the non-surgical treatment of mild to moderate carpal tunnel syndrome, although its efficacy has been a long-standing controversy. The laser parameters in low-power laser therapy are closely related to the laser effect on human tissue. To evaluate the efficacy of low-power laser therapy, laser parameters should be accurately measured and controlled, which has been ignored in previous clinical trials. Here, we report the measurement of the effective optical power of low-power laser therapy for carpal tunnel syndrome. By monitoring the backside reflection and scattering laser power from human skin at the wrist, the effective laser power can be inferred. Using clinical measurements from 30 cases, we found that the effective laser power differed significantly among cases, with the measured laser reflection coefficient ranging from 1.8% to 54%. The reflection coefficient for 36.7% of these 30 cases was in the range of 10–20%, but for 16.7% of cases, it was higher than 40%. Consequently, monitoring the effective optical power during laser irradiation is necessary for the laser therapy of carpal tunnel syndrome.

  8. Materialistic Aspects of Raising Resource of Pressurized Water Reactors for Low-Power Nuclear Plants

    International Nuclear Information System (INIS)

    Parshin, A.M.; Muratov, O.E.

    2005-01-01

    The opportunity of using ships reactors for low-power nuclear plants is considered. Some aspects of working constructional materials on cases of water-water reactors of ships nuclear units are considered. Advantages of raising resource of ships reactors are shown

  9. MiniDSS: a low-power and high-precision miniaturized digital sun sensor

    NARCIS (Netherlands)

    Boer, B.M. de; Durkut, M.; Laan, E.; Hakkesteegt, H.; Theuwissen, A.; Xie, N.; Leijtens, J.L.; Urquijo, E.; Bruins, P.

    2012-01-01

    A high-precision and low-power miniaturized digital sun sensor has been developed at TNO. The single-chip sun sensor comprises an application specific integrated circuit (ASIC) on which an active pixel sensor (APS), read-out and processing circuitry as well as communication circuitry are combined.

  10. Low power and self-reconfigurable WBAN controller for continuous bio-signal monitoring system

    NARCIS (Netherlands)

    Lee, S.; Yoo, H.J.

    2013-01-01

    The WBAN controller with Branched Bus (BB) topology and Continuous Data Transmission (CDT) protocol with low power consumption and self- reconfigurability is proposed for wearable healthcare applications. The BB topology and CDT protocol is a combination of conventional Bus and Star topology and a

  11. Achievable rate of spectrum sharing cognitive radio systems over fading channels at low-power regime

    KAUST Repository

    Sboui, Lokman

    2014-11-01

    We study the achievable rate of cognitive radio (CR) spectrum sharing systems at the low-power regime for general fading channels and then for Nakagami fading. We formally define the low-power regime and present the corresponding closed-form expressions of the achievable rate lower bound under various types of interference and/or power constraints, depending on the available channel state information of the cross link (CL) between the secondary-user transmitter and the primary-user receiver. We explicitly characterize two regimes where either the interference constraint or the power constraint dictates the optimal power profile. Our framework also highlights the effects of different fading parameters on the secondary link (SL) ergodic achievable rate. We also study more realistic scenarios when there is either 1-bit quantized channel feedback from the CL alone or 2-bit feedback from both the CL and the SL and propose simple power control schemes and show that these schemes achieve the previously achieved rate at the low-power regime. Interestingly, we show that the low-power regime analysis provides a specific insight into the maximum achievable rate behavior of CR that has not been reported by previous studies.

  12. Loss optimizing low power 50 Hz transformers intended for AC/DC standby power supplies

    DEFF Research Database (Denmark)

    Nielsen, Nils

    2004-01-01

    This paper presents the measured efficiency on selected low power conventional 50 Hz/230 V-AC transformers. The small transformers are intended for use in 1 W@5 V-DC series- or buck-regulated power supplies for standby purposes. The measured efficiency is compared for cheap off-the-self transformer...

  13. Robust sigma delta converters : and their application in low-power highly-digitized flexible receivers

    NARCIS (Netherlands)

    Veldhoven, van R.H.M.; Roermund, van A.H.M.

    2011-01-01

    Sigma Delta converters are a very popular choice for the A/D converter in multi-standard, mobile and cellular receivers. Key A/D converter specifications are high dynamic range, robustness, scalability, low-power and low EMI. Robust Sigma Delta Converters presents a requirement derivation of a Sigma

  14. Low power wide spectrum optical transmitter using avalanche mode LEDs in SOI CMOS technology

    NARCIS (Netherlands)

    Agarwal, V.; Dutta, S; Annema, AJ; Hueting, RJE; Steeneken, P.G.; Nauta, B

    2017-01-01

    This paper presents a low power monolithically integrated optical transmitter with avalanche mode light emitting diodes in a 140 nm silicon-on-insulator CMOS technology. Avalanche mode LEDs in silicon exhibit wide-spectrum electroluminescence (400 nm < λ < 850 nm), which has a significant

  15. A new universal gate for low power SoC applications

    Indian Academy of Sciences (India)

    This paper formulates a new design technique for an area and energy ... Low power; CMOS; pass-transistor; NAND gate; Koomey's law. 1. ... amount of battery you need will fall by a factor of two every year and a half' (Koomey Jonathan.

  16. A low power bipolar amplifier integrated circuit for the ZEUS silicon strip system

    Energy Technology Data Exchange (ETDEWEB)

    Barberis, E. (Inst. for Particle Physics, Univ. of California, Santa Cruz, CA (United States)); Cartiglia, N. (Inst. for Particle Physics, Univ. of California, Santa Cruz, CA (United States)); Dorfan, D.E. (Inst. for Particle Physics, Univ. of California, Santa Cruz, CA (United States)); Spencer, E. (Inst. for Particle Physics, Univ. of California, Santa Cruz, CA (United States))

    1993-05-01

    A fast low power bipolar chip consisting of 64 amplifier-comparators has been developed for use with silicon strip detectors for systems where high radiation levels and high occupancy considerations are important. The design is described and test results are presented. (orig.)

  17. A low power consumption and multi-function mini-printer for the portable nuclear instruments

    International Nuclear Information System (INIS)

    Jin Yuheng; Zhang Jiahong

    1994-01-01

    The authors presents a method of fitting a commercial printing calculator to the low power consumption and multi-function mini-printer. It can be employed as a compact data recorder and simple data processing device attached to the portable nuclear instruments, which are powered by dry batteries

  18. A low-power CMOS operational amplifier IC for a heterogeneous paper-based potentiostat

    CSIR Research Space (South Africa)

    Bezuidenhout, Petrone H

    2016-09-01

    Full Text Available substrates. This paper deals with the design of a low-power paper-based amperometric front-end for a low-cost and rapid detection environment. In amperometric detection a voltage signal is provided to a sensor system, while a small current value generated...

  19. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    Science.gov (United States)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  20. A low-power CMOS integrated sensor for CO2 detection in the percentage range

    NARCIS (Netherlands)

    Humbert, A.; Tuerlings, B.J.; Hoofman, R.J.O.M.; Tan, Z.; Gravesteijn, D.J.; Pertijs, M.A.P.; Bastiaansen, C.W.M.; Soccol, D.

    2013-01-01

    Within the Catrene project PASTEUR, a low-cost, low-power capacitive carbon dioxide sensor has been developed for tracking CO2 concentration in the percentage range. This paper describes this sensor, which operates at room temperature where it exhibits short response times as well as reversible

  1. 47 CFR 73.3521 - Mutually exclusive applications for low power television, television translators and television...

    Science.gov (United States)

    2010-10-01

    ... television, television translators and television booster stations. 73.3521 Section 73.3521 Telecommunication... Applicable to All Broadcast Stations § 73.3521 Mutually exclusive applications for low power television, television translators and television booster stations. When there is a pending application for a new low...

  2. Low cost low power 24 GHz FMCW radar transceiver for indoor presence detection

    NARCIS (Netherlands)

    Suijker, E.M.; Bolt, R.J.; Wanum, M. van; Heijningen, M. van; Maas, A.P.M.; Vliet, F.E. van

    2014-01-01

    In this paper a first time right 24 GHz FMCW radar transceiver is presented. The MMIC has a low power consumption of 86 mW and an output power of -10 dBm. Due to the integrated IF amplifier, the conversion gain of the receiver is 51 dB and the base band signals are directly processed with an ADC.

  3. Wireless coexistence and interference test method for low-power wireless sensor networks

    NARCIS (Netherlands)

    Serra, R.; Nabi, Majid

    2015-01-01

    Wireless sensor networks (WSNs) are being increasingly introduced for critical applications such as safety, security and health. One the main characteristic requirements of such networks are that they should function with relative low power. Therefore the wireless links are more vulnerable.

  4. Analysis of Opportunity to Create Self-Regulating Reactor Facility of Extra-Low Power

    International Nuclear Information System (INIS)

    Kazansky, Y.A.; Levtchenko, V.A.; Yuriev, Y.S.

    2002-01-01

    This paper deals with fundamental possibilities (economy, safety, self-regulation) of creating an extra-low power reactor facility for heat supply. It contains the results of calculations for thermal and fast neutron reactors. The concept of this type of a reactor had been developed by the contributors earlier

  5. Low-power critical facilities: their role in the nuclear renaissance

    International Nuclear Information System (INIS)

    Didsbury, R.

    2011-01-01

    This paper discusses the role of low power critical facilities and their role in the nuclear renaissance. It outline the role of human capital in some detail. sufficient conditions for the renaissance are that nuclear power is safe, sustainable, economical and proliferation resistant.

  6. Low power excitation of gyrotron-type modes in cylindrical waveguide using quasi-optical techniques

    International Nuclear Information System (INIS)

    Alexandrov, N.L.; Whaley, D.R.; Tran, M.Q.; Denisov, D.R.

    1995-03-01

    Experimental results of low power excitation of a 118 GHz TE 22,6 rotating mode are presented. A rectangular mode is converted to a TE 22,6 circular waveguide using quasi-optical techniques. A good conversion efficiency is measured and the experimentally observed field intensity profiles show the percentage of unwanted modes to be small. (author) 10 figs., 10 refs

  7. Low Power Implementation of Non Power-of-Two FFTs on Coarse-Grain Reconfigurable Architectures

    NARCIS (Netherlands)

    Zhang, Q.; Wolkotte, P.T.; Smit, Gerardus Johannes Maria; Rivaton, Arnaud; Quevremont, Jérôme

    2005-01-01

    The DRM standard for digital radio broadcast in the AM band requires integrated devices for radio receivers at very low power. A System on Chip (SoC) call DiMITRI was developed based on a dual ARM9 RISC core architecture. Analyses showed that most computation power is used in the Coded Orthogonal

  8. How to create a very-low cost, very-low-power, credit-card-sized and real-time ready datalogger

    Science.gov (United States)

    Bès de Berc, Maxime; Grunberg, Marc; Engels, Fabien

    2014-05-01

    In some cases a field instrumentalist could have to add some extra sensors in a remote station. Additional ADCs (Analogic Digital Converters) are not always implemented on commercial dataloggers, or may already be used. Adding more ADCs often implies an expensive development, or buy a new datalogger. We present here a very simple way to deploy an embedded ARM computer, use its features and embedded ADCs to create datas in a seismological standard format and integrating it within the real-time data stream from the station. In the past few years, because of the market growth of telephony and mobile applications, the ARM processor from ARM Ltd has become very common and available at a reasonable price. This processor has the particularity to be an excellent compromise between its frequency and its power consumption. That's why most of smartphones and tablets feature nowadays that kind of processor. It is also available on the market as Soc (System on Chip) or complete embedded computer. The most known is probably the Raspberry Pi, but many ohers exist like the BeagleBone or BeagleBoard. This kind of computer can be bought between 35€ for Raspberry Pi and several hundred Euro for more industrial products. Each model often embed some ADCs on its chip or some special buses, allowing additional ADCs to be easily used. Our experiment has been made on a BeagleBone platform, available at 78€. We chose it because its a more mature product than Raspberry Pi, it has all connectors and options needed: seven ADCs, an USB port for local backup, an Ethernet port for real-time streams, and some useful things like GPIO and I2C buses. Our goal was to plug temperature and humidity sensors on the ADCs, read datas, record them in mini-SEED format (Standard for the Exchange of the Earthquake Data), and transmit those datas to a central server as a secondary source for a remote station, by using Seedlink, which is a standard for seismology. Seedlink is a real-time data acquisition

  9. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  10. Electronics for embedded systems

    CERN Document Server

    Bindal, Ahmet

    2017-01-01

    This book provides semester-length coverage of electronics for embedded systems, covering most common analog and digital circuit-related issues encountered while designing embedded system hardware. It is written for students and young professionals who have basic circuit theory background and want to learn more about passive circuits, diode and bipolar transistor circuits, the state-of-the-art CMOS logic family and its interface with older logic families such as TTL, sensors and sensor physics, operational amplifier circuits to condition sensor signals, data converters and various circuits used in electro-mechanical device control in embedded systems. The book also provides numerous hardware design examples by integrating the topics learned in earlier chapters. The last chapter extensively reviews the combinational and sequential logic design principles to be able to design the digital part of embedded system hardware.

  11. Embedded Fragments Registry (EFR)

    Data.gov (United States)

    Department of Veterans Affairs — In 2009, the Department of Defense estimated that approximately 40,000 service members who served in OEF/OIF may have embedded fragment wounds as the result of small...

  12. Smart Multicore Embedded Systems

    DEFF Research Database (Denmark)

    This book provides a single-source reference to the state-of-the-art of high-level programming models and compilation tool-chains for embedded system platforms. The authors address challenges faced by programmers developing software to implement parallel applications in embedded systems, where very...... specificities of various embedded systems from different industries. Parallel programming tool-chains are described that take as input parameters both the application and the platform model, then determine relevant transformations and mapping decisions on the concrete platform, minimizing user intervention...... and hiding the difficulties related to the correct and efficient use of memory hierarchy and low level code generation. Describes tools and programming models for multicore embedded systems Emphasizes throughout performance per watt scalability Discusses realistic limits of software parallelization Enables...

  13. Introduction to Embedded Systems Using ANSI C and the Arduino Development Environment

    CERN Document Server

    Russell, David

    2010-01-01

    Many electrical and computer engineering projects involve some kind of embedded system in which a microcontroller sits at the center as the primary source of control. The recently-developed Arduino development platform includes an inexpensive hardware development board hosting an eight-bit ATMEL ATmega-family processor and a Java-based software-development environment. These features allow an embedded systems beginner the ability to focus their attention on learning how to write embedded software instead of wasting time overcoming the engineering CAD tools learning curve. The goal of this text

  14. Lipsi: Probably the Smallest Processor in the World

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

  15. Evaluation of the Intel iWarp parallel processor for space flight applications

    Science.gov (United States)

    Hine, Butler P., III; Fong, Terrence W.

    1993-01-01

    The potential of a DARPA-sponsored advanced processor, the Intel iWarp, for use in future SSF Data Management Systems (DMS) upgrades is evaluated through integration into the Ames DMS testbed and applications testing. The iWarp is a distributed, parallel computing system well suited for high performance computing applications such as matrix operations and image processing. The system architecture is modular, supports systolic and message-based computation, and is capable of providing massive computational power in a low-cost, low-power package. As a consequence, the iWarp offers significant potential for advanced space-based computing. This research seeks to determine the iWarp's suitability as a processing device for space missions. In particular, the project focuses on evaluating the ease of integrating the iWarp into the SSF DMS baseline architecture and the iWarp's ability to support computationally stressing applications representative of SSF tasks.

  16. On-board landmark navigation and attitude reference parallel processor system

    Science.gov (United States)

    Gilbert, L. E.; Mahajan, D. T.

    1978-01-01

    An approach to autonomous navigation and attitude reference for earth observing spacecraft is described along with the landmark identification technique based on a sequential similarity detection algorithm (SSDA). Laboratory experiments undertaken to determine if better than one pixel accuracy in registration can be achieved consistent with onboard processor timing and capacity constraints are included. The SSDA is implemented using a multi-microprocessor system including synchronization logic and chip library. The data is processed in parallel stages, effectively reducing the time to match the small known image within a larger image as seen by the onboard image system. Shared memory is incorporated in the system to help communicate intermediate results among microprocessors. The functions include finding mean values and summation of absolute differences over the image search area. The hardware is a low power, compact unit suitable to onboard application with the flexibility to provide for different parameters depending upon the environment.

  17. Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

    International Nuclear Information System (INIS)

    Alberti, F; Citterio, M; Liberali, V; Meroni, C; Andreani, A; Stabile, A; Annovi, A; Beretta, M; Crescioli, F; Dell'Orso, M; Piendibene, M; Volpi, G; Giannetti, P; Lanza, A; Magalotti, D; Sacco, I

    2013-01-01

    Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

  18. Bulk-memory processor for data acquisition

    International Nuclear Information System (INIS)

    Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

    1981-01-01

    To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

  19. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  20. Real time processor for array speckle interferometry

    International Nuclear Information System (INIS)

    Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

    1989-01-01

    With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods