Low-Power Embedded DSP Core for Communication Systems

Science.gov (United States)

Tsao, Ya-Lan; Chen, Wei-Hao; Tan, Ming Hsuan; Lin, Maw-Ching; Jou, Shyh-Jye

2003-12-01

This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35[InlineEquation not available: see fulltext.]m SPQM and 0.25[InlineEquation not available: see fulltext.]m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a[InlineEquation not available: see fulltext.] version is 100 MHz (0.35[InlineEquation not available: see fulltext.]m) and 140 MHz (0.25[InlineEquation not available: see fulltext.]m).

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

Embedded SoPC Design with Nios II Processor and Verilog Examples

CERN Document Server

Chu, Pong P

2012-01-01

Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

Huffman-based code compression techniques for embedded processors

KAUST Repository

Bonny, Mohamed Talal; Henkel, Jö rg

2010-01-01

% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures, namely ARM and MIPS. © 2010 ACM.

A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

Science.gov (United States)

Töreyin, Hakan; Bhatti, Pamela T

2016-06-01

A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

Security Implications for Ultra-Low Power Configurable SoC FPAA Embedded Systems

Directory of Open Access Journals (Sweden)

Jennifer Hasler

2018-06-01

Full Text Available We discuss the impact of physical computing techniques to classifying network security issues for ultra-low power networked IoT devices. Physical computing approaches enable at least a factor of 1000 improvement in computational energy efficiency empowering a new generation of local computational structures for embedded IoT devices. These techniques offer computational capability to address network security concerns. This paper begins the discussion of security opportunities for, and issues using, FPAA devices for small embedded IoT platforms. These FPAAs enable devices often utilized for low-power context aware computation. Embedded FPAA devices have both positive Security attributes, as well as potential vulnerabilities. FPAA devices can be part of the resulting secure computation, such as implementing unique functions. FPAA devices can be used investigate security of analog/mixed signal capabilities. The paper concludes with summarizing key improvements for secure ultra-low power embedded FPAA devices.

Multimode power processor

Science.gov (United States)

O'Sullivan, George A.; O'Sullivan, Joseph A.

1999-01-01

In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

Energy Technology Data Exchange (ETDEWEB)

NONE

1997-03-01

The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

MatLab script to C code converter for embedded processors of FLASH LLRF control system

Science.gov (United States)

Bujnowski, K.; Siemionczyk, A.; Pucyk, P.; Szewiński, J.; Pożniak, K. T.; Romaniuk, R. S.

2008-01-01

The low level RF control system (LLRF) of FEL serves for stabilization of the electromagnetic (EM) field in the superconducting niobium, resonant, microwave cavities and for controlling high power (MW) klystron. LLRF system of FLASH accelerator bases on FPGA technology and embedded microprocessors. Basic and auxiliary functions of the systems are listed as well as used algorithms for superconductive cavity parameters identification. These algorithms were prepared originally in Matlab. The main part of the paper presents implementation of the cavity parameters identification algorithm in a PowerPC processor embedded in the FPGA circuit VirtexIIPro. A construction of a very compact Matlab script converter to C code was presented, referred to as M2C. The application is designed specifically for embedded systems of very confined resources. The generated code is optimized for the weight. The code should be transferable between different hardware platforms. The converter generates a code for Linux and for stand-alone applications. Functional structure of the program was described and the way it is acting. FLEX and BIZON tools were used for construction of the converter. The paper concludes with an example of the M2C application to convert a complex identification algorithm for superconductive cavities in FLASH laser.

ARM Processor Based Embedded System for Remote Data Acquisition

OpenAIRE

Raj Kumar Tiwari; Santosh Kumar Agrahari

2014-01-01

The embedded systems are widely used for the data acquisition. The data acquired may be used for monitoring various activity of the system or it can be used to control the parts of the system. Accessing various signals with remote location has greater advantage for multisite operation or unmanned systems. The remote data acquisition used in this paper is based on ARM processor. The Cortex M3 processor used in this system has in-built Ethernet controller which facilitate to acquire the remote ...

Low-Power Built-In Self-Test Techniques for Embedded SRAMs

Directory of Open Access Journals (Sweden)

Shyue-Kung Lu

2007-01-01

Full Text Available The severity of power consumption during parallel BIST of embedded memory cores is growing significantly. In order to alleviate this problem, a row bank-based precharge technique based on the divided wordline (DWL architecture is proposed for low-power testing of embedded SRAMs. The memory cell array is first divided into row banks. The effectiveness of the row bank-based precharge technique is due to the predictable address sequence during test. In low-power test mode, instead of precharging the entire memory array, only the current accessed row bank is precharged. This will result in significant power saving for the precharge circuitry. The precharge power can be reduced to 1/b of that of the traditional precharge techniques, where b denotes the number of row banks in the memory array. With simple transmission gates and inverters, the modified precharge control circuitry was also designed. The hardware overhead for implementing the low-power technique is almost negligible. Moreover, the corresponding BIST design to implement the low-power technique is almost the same as the conventional BIST designs. It is also notable that the inherent low-power characteristics of the DWL architecture can be preserved. According to experimental results, 48.9% power reduction can be achieved for a 256 × 256 bit-oriented SRAM. The memory is divided into 8 row banks. Moreover, if the number of row banks increases, the power saving will also increase.

Experience with low-power x86 processors (Atom) for HEP usage. An initial analysis of the Intel® dual core Atom™ N330 processor

CERN Document Server

Balazs, G; Nowak, A; CERN. Geneva. IT Department

2009-01-01

In this paper we compare a system based on an Intel Atom N330 low-power processor to a modern Intel Xeon® dual-socket server using CERN IT’s standard criteria for comparing price-performance and performance per watt. The Xeon server corresponds to what is typically acquired as servers in the LHC Computing Grid. The comparisons used public pricing information from November 2008. After the introduction in section 1, section 2 describes the hardware and software setup. In section 3 we describe the power measurements we did and in section 4 we discuss the throughput performance results. In section 5 we summarize our initial conclusions. We then go on to describe our long term vision and possible future scenarios for using such low-power processors, and finally we list interesting development directions.

A Practical Framework to Study Low-Power Scheduling Algorithms on Real-Time and Embedded Systems

Directory of Open Access Journals (Sweden)

Jian (Denny Lin

2014-05-01

Full Text Available With the advanced technology used to design VLSI (Very Large Scale Integration circuits, low-power and energy-efficiency have played important roles for hardware and software implementation. Real-time scheduling is one of the fields that has attracted extensive attention to design low-power, embedded/real-time systems. The dynamic voltage scaling (DVS and CPU shut-down are the two most popular techniques used to design the algorithms. In this paper, we firstly review the fundamental advances in the research of energy-efficient, real-time scheduling. Then, a unified framework with a real Intel PXA255 Xscale processor, namely real-energy, is designed, which can be used to measure the real performance of the algorithms. We conduct a case study to evaluate several classical algorithms by using the framework. The energy efficiency and the quantitative difference in their performance, as well as the practical issues found in the implementation of these algorithms are discussed. Our experiments show a gap between the theoretical and real results. Our framework not only gives researchers a tool to evaluate their system designs, but also helps them to bridge this gap in their future works.

Low-power analogue processor for Bonner sphere spectrometers

International Nuclear Information System (INIS)

Ciobanu, M.I.; Alevra, A.V.

1998-01-01

The electronic system proposed is compact, small-size (the dimensions of the prototype are 107 x 105 x 58 mm) and battery-powered. The whole detection system is portable and independent of the mains supply and is well shielded against external disturbances. Technical details of the analog processor are given. (M.D.)

An Embedded Sensor Node Microcontroller with Crypto-Processors.

Science.gov (United States)

Panić, Goran; Stecklina, Oliver; Stamenković, Zoran

2016-04-27

Wireless sensor network applications range from industrial automation and control, agricultural and environmental protection, to surveillance and medicine. In most applications, data are highly sensitive and must be protected from any type of attack and abuse. Security challenges in wireless sensor networks are mainly defined by the power and computing resources of sensor devices, memory size, quality of radio channels and susceptibility to physical capture. In this article, an embedded sensor node microcontroller designed to support sensor network applications with severe security demands is presented. It features a low power 16-bitprocessor core supported by a number of hardware accelerators designed to perform complex operations required by advanced crypto algorithms. The microcontroller integrates an embedded Flash and an 8-channel 12-bit analog-to-digital converter making it a good solution for low-power sensor nodes. The article discusses the most important security topics in wireless sensor networks and presents the architecture of the proposed hardware solution. Furthermore, it gives details on the chip implementation, verification and hardware evaluation. Finally, the chip power dissipation and performance figures are estimated and analyzed.

System-level power optimization for real-time distributed embedded systems

Science.gov (United States)

Luo, Jiong

Power optimization is one of the crucial design considerations for modern electronic systems. In this thesis, we present several system-level power optimization techniques for real-time distributed embedded systems, based on dynamic voltage scaling, dynamic power management, and management of peak power and variance of the power profile. Dynamic voltage scaling has been widely acknowledged as an important and powerful technique to trade off dynamic power consumption and delay. Efficient dynamic voltage scaling requires effective variable-voltage scheduling mechanisms that can adjust voltages and clock frequencies adaptively based on workloads and timing constraints. For this purpose, we propose static variable-voltage scheduling algorithms utilizing criticalpath driven timing analysis for the case when tasks are assumed to have uniform switching activities, as well as energy-gradient driven slack allocation for a more general scenario. The proposed techniques can achieve closeto-optimal power savings with very low computational complexity, without violating any real-time constraints. We also present algorithms for power-efficient joint scheduling of multi-rate periodic task graphs along with soft aperiodic tasks. The power issue is addressed through both dynamic voltage scaling and power management. Periodic task graphs are scheduled statically. Flexibility is introduced into the static schedule to allow the on-line scheduler to make local changes to PE schedules through resource reclaiming and slack stealing, without interfering with the validity of the global schedule. We provide a unified framework in which the response times of aperiodic tasks and power consumption are dynamically optimized simultaneously. Interconnection network fabrics point to a new generation of power-efficient and scalable interconnection architectures for distributed embedded systems. As the system bandwidth continues to increase, interconnection networks become power/energy limited as

A 600-µW ultra-low-power associative processor for image pattern recognition employing magnetic tunnel junction-based nonvolatile memories with autonomic intelligent power-gating scheme

Science.gov (United States)

Ma, Yitao; Miura, Sadahiko; Honjo, Hiroaki; Ikeda, Shoji; Hanyu, Takahiro; Ohno, Hideo; Endoh, Tetsuo

2016-04-01

A novel associative processor using magnetic tunnel junction (MTJ)-based nonvolatile memories has been proposed and fabricated under a 90 nm CMOS/70 nm perpendicular-MTJ (p-MTJ) hybrid process for achieving the exceptionally low-power performance of image pattern recognition. A four-transistor 2-MTJ (4T-2MTJ) spin transfer torque magnetoresistive random access memory was adopted to completely eliminate the standby power. A self-directed intelligent power-gating (IPG) scheme specialized for this associative processor is employed to optimize the operation power by only autonomously activating currently accessed memory cells. The operations of a prototype chip at 20 MHz are demonstrated by measurement. The proposed processor can successfully carry out single texture pattern matching within 6.5 µs using 128-dimension bag-of-feature patterns, and the measured average operation power of the entire processor core is only 600 µW. Compared with the twin chip designed with 6T static random access memory, 91.2% power reductions are achieved. More than 88.0% power reductions are obtained compared with the latest associative memories. The further power performance analysis is discussed in detail, which verifies the special superiority of the proposed processor in power consumption for large-capacity memory-based VLSI systems.

Design concepts for a virtualizable embedded MPSoC architecture enabling virtualization in embedded multi-processor systems

CERN Document Server

Biedermann, Alexander

2014-01-01

Alexander Biedermann presents a generic hardware-based virtualization approach, which may transform an array of any off-the-shelf embedded processors into a multi-processor system with high execution dynamism. Based on this approach, he highlights concepts for the design of energy aware systems, self-healing systems as well as parallelized systems. For the latter, the novel so-called Agile Processing scheme is introduced by the author, which enables a seamless transition between sequential and parallel execution schemes. The design of such virtualizable systems is further aided by introduction

Reward-based learning under hardware constraints - Using a RISC processor embedded in a neuromorphic substrate

Directory of Open Access Journals (Sweden)

Simon eFriedmann

2013-09-01

Full Text Available In this study, we propose and analyze in simulations a new, highly flexible method of imple-menting synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. Thestudy focuses on globally modulated STDP, as a special use-case of this method. Flexibility isachieved by embedding a general-purpose processor dedicated to plasticity into the wafer. Toevaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spiketrain learning task. A single layer of neurons is trained to fire at specific points in time withonly the reward as feedback. This model is simulated to measure its performance, i.e. the in-crease in received reward after learning. Using this performance as baseline, we then simulatethe model with various constraints imposed by the proposed implementation and compare theperformance. The simulated constraints include discretized synaptic weights, a restricted inter-face between analog synapses and embedded processor, and mismatch of analog circuits. Wefind that probabilistic updates can increase the performance of low-resolution weights, a simpleinterface between analog synapses and processor is sufficient for learning, and performance isinsensitive to mismatch. Further, we consider communication latency between wafer and theconventional control computer system that is simulating the environment. This latency increasesthe delay, with which the reward is sent to the embedded processor. Because of the time continu-ous operation of the analog synapses, delay can cause a deviation of the updates as compared tothe not delayed situation. We find that for highly accelerated systems latency has to be kept to aminimum. This study demonstrates the suitability of the proposed implementation to emulatethe selected reward modulated STDP learning rule. It is therefore an ideal candidate for imple-mentation in an upgraded version of the wafer-scale system developed within the BrainScaleSproject.

Reward-based learning under hardware constraints-using a RISC processor embedded in a neuromorphic substrate.

Science.gov (United States)

Friedmann, Simon; Frémaux, Nicolas; Schemmel, Johannes; Gerstner, Wulfram; Meier, Karlheinz

2013-01-01

In this study, we propose and analyze in simulations a new, highly flexible method of implementing synaptic plasticity in a wafer-scale, accelerated neuromorphic hardware system. The study focuses on globally modulated STDP, as a special use-case of this method. Flexibility is achieved by embedding a general-purpose processor dedicated to plasticity into the wafer. To evaluate the suitability of the proposed system, we use a reward modulated STDP rule in a spike train learning task. A single layer of neurons is trained to fire at specific points in time with only the reward as feedback. This model is simulated to measure its performance, i.e., the increase in received reward after learning. Using this performance as baseline, we then simulate the model with various constraints imposed by the proposed implementation and compare the performance. The simulated constraints include discretized synaptic weights, a restricted interface between analog synapses and embedded processor, and mismatch of analog circuits. We find that probabilistic updates can increase the performance of low-resolution weights, a simple interface between analog synapses and processor is sufficient for learning, and performance is insensitive to mismatch. Further, we consider communication latency between wafer and the conventional control computer system that is simulating the environment. This latency increases the delay, with which the reward is sent to the embedded processor. Because of the time continuous operation of the analog synapses, delay can cause a deviation of the updates as compared to the not delayed situation. We find that for highly accelerated systems latency has to be kept to a minimum. This study demonstrates the suitability of the proposed implementation to emulate the selected reward modulated STDP learning rule. It is therefore an ideal candidate for implementation in an upgraded version of the wafer-scale system developed within the BrainScaleS project.

The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

Directory of Open Access Journals (Sweden)

Seung-Ho Ok

2017-02-01

Full Text Available Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV, three-dimensional (3D stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

An enhanced Ada run-time system for real-time embedded processors

Science.gov (United States)

Sims, J. T.

1991-01-01

An enhanced Ada run-time system has been developed to support real-time embedded processor applications. The primary focus of this development effort has been on the tasking system and the memory management facilities of the run-time system. The tasking system has been extended to support efficient and precise periodic task execution as required for control applications. Event-driven task execution providing a means of task-asynchronous control and communication among Ada tasks is supported in this system. Inter-task control is even provided among tasks distributed on separate physical processors. The memory management system has been enhanced to provide object allocation and protected access support for memory shared between disjoint processors, each of which is executing a distinct Ada program.

Natrium: Use of FPGA embedded processors for real-time data compression

Energy Technology Data Exchange (ETDEWEB)

Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

2011-12-15

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Natrium: Use of FPGA embedded processors for real-time data compression

International Nuclear Information System (INIS)

Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

2011-01-01

We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

Open-source implementation of an ad-hoc IEEE802.11a/g/p software-defined radio on low-power and low-cost general purpose processors

Directory of Open Access Journals (Sweden)

S. Ciccia

2017-12-01

Full Text Available This work proposes a low-cost and low-power software-defined radio open-source platform with IEEE 802.11 a/g/p wireless communication capability. A state-of-the-art version of the IEEE 802.11 a/g/p software for GNU Radio (a free and open-source software development framework is available online, but we show here that its computational complexity prevents operations in low-power general purpose processors, even at throughputs below the standard. We therefore propose an evolution of this software that achieves a faster and lighter IEEE 802.11 a/g/p transmitter and receiver, suitable for low-power general purpose processors, for which GNU Radio provides very limited support; we discuss and describe the software radio processing structuring that is necessary to achieve the goal, providing a review of signal processing techniques. In particular, we emphasize the advanced reduced-instruction set (RISC machine (ARM study case, for which we also optimize some of the processing libraries. The presented software will remain open-source.

A Case Study of Limited Dynamic Voltage Frequency Scaling in Low-Power Processors

OpenAIRE

Hwan Su Jung; Ahn Jun Gil; Jong Tae Kim

2017-01-01

Power management techniques are necessary to save power in the microprocessor. By changing the frequency and/or operating voltage of processor, DVFS can control power consumption. In this paper, we perform a case study to find optimal power state transition for DVFS. We propose the equation to find the optimal ratio between executions of states while taking into account the deadline of processing time and the power state transition delay overhead. The experiment is performed on the Cortex-M4 ...

Compilation Techniques Specific for a Hardware Cryptography-Embedded Multimedia Mobile Processor

Directory of Open Access Journals (Sweden)

Masa-aki FUKASE

2007-12-01

Full Text Available The development of single chip VLSI processors is the key technology of ever growing pervasive computing to answer overall demands for usability, mobility, speed, security, etc. We have so far developed a hardware cryptography-embedded multimedia mobile processor architecture, HCgorilla. Since HCgorilla integrates a wide range of techniques from architectures to applications and languages, one-sided design approach is not always useful. HCgorilla needs more complicated strategy, that is, hardware/software (H/S codesign. Thus, we exploit the software support of HCgorilla composed of a Java interface and parallelizing compilers. They are assumed to be installed in servers in order to reduce the load and increase the performance of HCgorilla-embedded clients. Since compilers are the essence of software's responsibility, we focus in this article on our recent results about the design, specifications, and prototyping of parallelizing compilers for HCgorilla. The parallelizing compilers are composed of a multicore compiler and a LIW compiler. They are specified to abstract parallelism from executable serial codes or the Java interface output and output the codes executable in parallel by HCgorilla. The prototyping compilers are written in Java. The evaluation by using an arithmetic test program shows the reasonability of the prototyping compilers compared with hand compilers.

Composable processor virtualization for embedded systems

NARCIS (Netherlands)

Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

2010-01-01

Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

Extended performance electric propulsion power processor design study. Volume 2: Technical summary

Science.gov (United States)

Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

1977-01-01

Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

NInFEA: an embedded framework for the real-time evaluation of fetal ECG extraction algorithms.

Science.gov (United States)

Pani, Danilo; Barabino, Gianluca; Raffo, Luigi

2013-02-01

Fetal electrocardiogram (ECG) extraction from non-invasive biopotential recordings is a long-standing research topic. Despite the significant number of algorithms presented in the scientific literature, it is difficult to find information about embedded hardware implementations able to provide real-time support for the required features, bridging the gap between theory and practice. This article presents the NInFEA (non-invasive fetal ECG analysis) tool, an embedded hardware/software framework based on the hybrid dual-core OMAP-L137 low-power processor for the real-time evaluation of fetal ECG extraction algorithms. The hybrid platform, including a digital signal processor (DSP) and a general-purpose processor (GPP), allows achieving the best performance compared with single-core architectures. The GPP provides a portable graphical user interface, whereas the DSP is extensively used for advanced signal processing tasks. As a case study, three state-of-the-art fetal ECG extraction algorithms have been ported onto NInFEA, along with some support routines needed to provide the additional information required by the clinicians and supported by the user interface. NInFEA can be regarded both as a reference design for similar applications and as a common embedded low-power testbed for real-time fetal ECG extraction algorithms.

Review of battery powered embedded systems design for mission-critical low-power applications

Science.gov (United States)

Malewski, Matthew; Cowell, David M. J.; Freear, Steven

2018-06-01

The applications and uses of embedded systems is increasingly pervasive. Mission and safety critical systems relying on embedded systems pose specific challenges. Embedded systems is a multi-disciplinary domain, involving both hardware and software. Systems need to be designed in a holistic manner so that they are able to provide the desired reliability and minimise unnecessary complexity. The large problem landscape means that there is no one solution that fits all applications of embedded systems. With the primary focus of these mission and safety critical systems being functionality and reliability, there can be conflicts with business needs, and this can introduce pressures to reduce cost at the expense of reliability and functionality. This paper examines the challenges faced by battery powered systems, and then explores at more general problems, and several real-world embedded systems.

Interleaved Subtask Scheduling on Multi Processor SOC

NARCIS (Netherlands)

Zhe, M.

2006-01-01

The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

Embedded control system for high power RF amplifiers

International Nuclear Information System (INIS)

Sharma, Deepak Kumar; Gupta, Alok Kumar; Jain, Akhilesh; Hannurkar, P.R.

2011-01-01

RF power devices are usually very sensitive to overheat and reflected RF power; hence a protective interlock system is required to be embedded with high power solid state RF amplifiers. The solid state RF amplifiers have salient features of graceful degradation and very low mean time to repair (MTTR). In order to exploit these features in favour of lowest system downtime, a real-time control system is embedded with high power RF amplifiers. The control system is developed with the features of monitoring, measurement and network publishing of various parameters, historical data logging, alarm generation, displaying data to the operator and tripping the system in case of any interlock failure. This paper discusses the design philosophy, features, functions and implementation details of the embedded control system. (author)

A digital retina-like low-level vision processor.

Science.gov (United States)

Mertoguno, S; Bourbakis, N G

2003-01-01

This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

Reduced power processor requirements for the 30-cm diameter HG ion thruster

Science.gov (United States)

Rawlin, V. K.

1979-01-01

The characteristics of power processors strongly impact the overall performance and cost of electric propulsion systems. A program was initiated to evaluate simplifications of the thruster-power processor interface requirements. The power processor requirements are mission dependent with major differences arising for those missions which require a nearly constant thruster operating point (typical of geocentric and some inbound planetary missions) and those requiring operation over a large range of input power (such as outbound planetary missions). This paper describes the results of tests which have indicated that as many as seven of the twelve power supplies may be eliminated from the present Functional Model Power Processor used with 30-cm diameter Hg ion thrusters.

Low Power Computing in Distributed Systems

Science.gov (United States)

2006-04-01

performance applications. It has been adopted in embedded systems such as the Stargate from Crossbow [15] and the PASTA 4 0 0.1 0.2 0.3 0.4 (A) flo at...current consumption of the Stargate board is measured by an Agilent digital multimeter 34401A. The digital multimeter is connected with the PC for data...floating point operation vs. integer operation Power supply Digital multimeter Stargate board with Xscale processor 5 2.2 Library math function vs

A High-Speed and Low-Energy-Consumption Processor for SVD-MIMO-OFDM Systems

Directory of Open Access Journals (Sweden)

Hiroki Iwaizumi

2013-01-01

Full Text Available A processor design for singular value decomposition (SVD and compression/decompression of feedback matrices, which are mandatory operations for SVD multiple-input multiple-output orthogonal frequency-division multiplexing (MIMO-OFDM systems, is proposed and evaluated. SVD-MIMO is a transmission method for suppressing multistream interference and improving communication quality by beamforming. An application specific instruction-set processor (ASIP architecture is adopted to achieve flexibility in terms of operations and matrix size. The proposed processor realizes a high-speed/low-power design and real-time processing by the parallelization of floating-point units (FPUs and arithmetic instructions specialized in complex matrix operations.

Quality-Driven Model-Based Design of MultiProcessor Embedded Systems for Highlydemanding Applications

DEFF Research Database (Denmark)

Jozwiak, Lech; Madsen, Jan

2013-01-01

The recent spectacular progress in modern nano-dimension semiconductor technology enabled implementation of a complete complex multi-processor system on a single chip (MPSoC), global networking and mobile wire-less communication, and facilitated a fast progress in these areas. New important...... accessible or distant) objects, installations, machines or devices, or even implanted in human or animal body can serve as examples. However, many of the modern embedded application impose very stringent functional and parametric demands. Moreover, the spectacular advances in microelectronics introduced...

JIST: Just-In-Time Scheduling Translation for Parallel Processors

Directory of Open Access Journals (Sweden)

Giovanni Agosta

2005-01-01

Full Text Available The application fields of bytecode virtual machines and VLIW processors overlap in the area of embedded and mobile systems, where the two technologies offer different benefits, namely high code portability, low power consumption and reduced hardware cost. Dynamic compilation makes it possible to bridge the gap between the two technologies, but special attention must be paid to software instruction scheduling, a must for the VLIW architectures. We have implemented JIST, a Virtual Machine and JIT compiler for Java Bytecode targeted to a VLIW processor. We show the impact of various optimizations on the performance of code compiled with JIST through the experimental study on a set of benchmark programs. We report significant speedups, and increments in the number of instructions issued per cycle up to 50% with respect to the non-scheduling version of the JITcompiler. Further optimizations are discussed.

A Raspberry Pi Cluster Instrumented for Fine-Grained Power Measurement

Directory of Open Access Journals (Sweden)

Michael F. Cloutier

2016-09-01

Full Text Available Power consumption has become an increasingly important metric when building large supercomputing clusters. One way to reduce power usage in large clusters is to use low-power embedded processors rather than the more typical high-end server CPUs (central processing units. We investigate various power-related metrics for seventeen different embedded ARM development boards in order to judge the appropriateness of using them in a computing cluster. We then build a custom cluster out of Raspberry Pi boards, which is specially designed for per-node detailed power measurement. In addition to serving as an embedded cluster testbed, our cluster’s power measurement, visualization and thermal features make it an excellent low-cost platform for education and experimentation.

A novel 2 T P-channel nano-crystal memory for low power/high speed embedded NVM applications

International Nuclear Information System (INIS)

Zhang Junyu; Wang Yong; Liu Jing; Zhang Manhong; Xu Zhongguang; Huo Zongliang; Liu Ming

2012-01-01

We introduce a novel 2 T P-channel nano-crystal memory structure for low power and high speed embedded non-volatile memory (NVM) applications. By using the band-to-band tunneling-induced hot-electron (BTBTIHE) injection scheme, both high-speed and low power programming can be achieved at the same time. Due to the use of a select transistor, the 'erased states' can be set to below 0 V, so that the periphery HV circuit (high-voltage generating and management) and read-out circuit can be simplified. Good memory cell performance has also been achieved, including a fast program/erase (P/E) speed (a 1.15 V memory window under 10 μs program pulse), an excellent data retention (only 20% charge loss for 10 years). The data shows that the device has strong potential for future embedded NVM applications. (semiconductor devices)

Very Long Instruction Word Processors

Indian Academy of Sciences (India)

Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

Application of embedded database to digital power supply system in HIRFL

International Nuclear Information System (INIS)

Wu Guanghua; Yan Huaihai; Chen Youxin; Huang Yuzhen; Zhou Zhongzu; Gao Daqing

2014-01-01

Background: This paper introduces the application of embedded MySQL database in the real-time monitoring system of the digital power supply system in Heavy Ion Research Facility in Lanzhou (HIRFL). Purpose: The aim is to optimize the real-time monitoring system of the digital power supply system for better performance. Methods: The MySQL database is designed and implemented under Linux operation system running on ARM processor, together with the related functions for real-time data monitoring, such as collection, storage and query. All status parameters of digital power supply system is collected and communicated with ARM by a FPGA, whilst the user interface is realized by Qt toolkits at ARM end. Results: The actual operation indicates that digital power supply can realize the function of real-time data monitoring, collection, storage and so on. Conclusion: Through practical application, we have found some aspects we can improve and we will try to optimize them in the future. (authors)

Embedded System Implementation on FPGA System With μCLinux OS

International Nuclear Information System (INIS)

Amin, Ahmad Fairuz Muhd; Aris, Ishak; Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah

2011-01-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With μCLinux OS

Science.gov (United States)

Fairuz Muhd Amin, Ahmad; Aris, Ishak; Syamsul Azmir Raja Abdullah, Raja; Kalos Zakiah Sahbudin, Ratna

2011-02-01

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), μClinux. In this paper, an example of web server is explained and demonstrated

Embedded System Implementation on FPGA System With {mu}CLinux OS

Energy Technology Data Exchange (ETDEWEB)

Amin, Ahmad Fairuz Muhd [Institute of Advanced Technology, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Aris, Ishak [Department of Electrical and Electronic Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia); Abdullah, Raja Syamsul Azmir Raja; Sahbudin, Ratna Kalos Zakiah, E-mail: gs20613@mutiara.upm.edu.my, E-mail: ishak@eng.upm.edu.my, E-mail: rsa@eng.upm.edu.my [Department of Computer and Communication Systems Engineering, Universiti Putra Malaysia, 43400, Serdang, Selangor (Malaysia)

2011-02-15

Embedded systems are taking on more complicated tasks as the processors involved become more powerful. The embedded systems have been widely used in many areas such as in industries, automotives, medical imaging, communications, speech recognition and computer vision. The complexity requirements in hardware and software nowadays need a flexibility system for further enhancement in any design without adding new hardware. Therefore, any changes in the design system will affect the processor that need to be changed. To overcome this problem, a System On Programmable Chip (SOPC) has been designed and developed using Field Programmable Gate Array (FPGA). A softcore processor, NIOS II 32-bit RISC, which is the microprocessor core was utilized in FPGA system together with the embedded operating system(OS), {mu}Clinux. In this paper, an example of web server is explained and demonstrated

Smart Power Supply for Battery-Powered Systems

Science.gov (United States)

Krasowski, Michael J.; Greer, Lawrence; Prokop, Norman F.; Flatico, Joseph M.

2010-01-01

A power supply for battery-powered systems has been designed with an embedded controller that is capable of monitoring and maintaining batteries, charging hardware, while maintaining output power. The power supply is primarily designed for rovers and other remote science and engineering vehicles, but it can be used in any battery alone, or battery and charging source applications. The supply can function autonomously, or can be connected to a host processor through a serial communications link. It can be programmed a priori or on the fly to return current and voltage readings to a host. It has two output power busses: a constant 24-V direct current nominal bus, and a programmable bus for output from approximately 24 up to approximately 50 V. The programmable bus voltage level, and its output power limit, can be changed on the fly as well. The power supply also offers options to reduce the programmable bus to 24 V when the set power limit is reached, limiting output power in the case of a system fault detected in the system. The smart power supply is based on an embedded 8051-type single-chip microcontroller. This choice was made in that a credible progression to flight (radiation hard, high reliability) can be assumed as many 8051 processors or gate arrays capable of accepting 8051-type core presently exist and will continue to do so for some time. To solve the problem of centralized control, this innovation moves an embedded microcontroller to the power supply and assigns it the task of overseeing the operation and charging of the power supply assets. This embedded processor is connected to the application central processor via a serial data link such that the central processor can request updates of various parameters within the supply, such as battery current, bus voltage, remaining power in battery estimations, etc. This supply has a direct connection to the battery bus for common (quiescent) power application. Because components from multiple vendors may have

Development of an Erlang System Adaopted to Embedded Devices

OpenAIRE

Andersson, Fredrik; Bergström, Fabian

2011-01-01

Erlang is a powerful and robust language for writing massively parallel and distributed applications. With the introduction of multi-core ARM processors, the embedded market will be looking for ways of taking advantage of the newfound opportunities for parallelism. To support the development of embedded applications using Erlang we want to provide Erlang and Embedded developers with a run-time system suited for embedded devices. We have managed to shrink the disk size of the Erlang runtime sy...

Dual shear plate power processor packaging design. [for Solar Electric Propulsion spacecraft

Science.gov (United States)

Franzon, A. O.; Fredrickson, C. D.; Ross, R. G.

1975-01-01

The use of solar electric propulsion (SEP) for spacecraft primary propulsion imposes an extreme range of operational and environmental design requirements associated with the diversity of missions for which solar electric primary propulsion is advantageous. One SEP element which is particularly sensitive to these environmental extremes is the power processor unit (PPU) which powers and controls the electric ion thruster. An improved power processor thermal-mechanical packaging approach, referred to as dual shear plate packaging, has been designed to accommodate these different requirements with minimum change to the power processor design. Details of this packaging design are presented together with test results obtained from thermal-vacuum and structural-vibration tests conducted with prototype hardware.

New development for low energy electron beam processor

International Nuclear Information System (INIS)

Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

2003-01-01

Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

Huffman-based code compression techniques for embedded processors

KAUST Repository

Bonny, Mohamed Talal

2010-09-01

The size of embedded software is increasing at a rapid pace. It is often challenging and time consuming to fit an amount of required software functionality within a given hardware resource budget. Code compression is a means to alleviate the problem by providing substantial savings in terms of code size. In this article we introduce a novel and efficient hardware-supported compression technique that is based on Huffman Coding. Our technique reduces the size of the generated decoding table, which takes a large portion of the memory. It combines our previous techniques, Instruction Splitting Technique and Instruction Re-encoding Technique into new one called Combined Compression Technique to improve the final compression ratio by taking advantage of both previous techniques. The instruction Splitting Technique is instruction set architecture (ISA)-independent. It splits the instructions into portions of varying size (called patterns) before Huffman coding is applied. This technique improves the final compression ratio by more than 20% compared to other known schemes based on Huffman Coding. The average compression ratios achieved using this technique are 48% and 50% for ARM and MIPS, respectively. The Instruction Re-encoding Technique is ISA-dependent. It investigates the benefits of reencoding unused bits (we call them reencodable bits) in the instruction format for a specific application to improve the compression ratio. Reencoding those bits can reduce the size of decoding tables by up to 40%. Using this technique, we improve the final compression ratios in comparison to the first technique to 46% and 45% for ARM and MIPS, respectively (including all overhead that incurs). The Combined Compression Technique improves the compression ratio to 45% and 42% for ARM and MIPS, respectively. In our compression technique, we have conducted evaluations using a representative set of applications and we have applied each technique to two major embedded processor architectures

Development of a processor embedded timing unit for the synchronized operation in KSTAR

Energy Technology Data Exchange (ETDEWEB)

Lee, Woongryol, E-mail: wrlee@nfri.re.kr; Lee, Taegu; Hong, Jaesic

2016-11-15

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

Development of a processor embedded timing unit for the synchronized operation in KSTAR

International Nuclear Information System (INIS)

Lee, Woongryol; Lee, Taegu; Hong, Jaesic

2016-01-01

Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

VON WISPR Family Processors: Volume 1

National Research Council Canada - National Science Library

Wagstaff, Ronald

1997-01-01

...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

Low power arcjet performance

Science.gov (United States)

Curran, Francis M.; Sarmiento, Charles J.

1990-01-01

An experimental investigation was performed to evaluate arcjet operation at low power. A standard, 1 kW, constricted arcjet was run using nozzles with three different constrictor diameters. Each nozzle was run over a range of current and mass flow rates to explore stability and performance in the low power regime. A standard pulse-width modulated power processor was modified to accommodate the high operating voltages required under certain conditions. Stable, reliable operation at power levels below 0.5 kW was obtained at efficiencies between 30 and 40 percent. The operating range was found to be somewhat dependent on constrictor geometry at low mass flow rates. Quasi-periodic voltage fluctuations were observed at the low power end of the operating envelope. The nozzle insert geometry was found to have little effect on the performance of the device. The observed performance levels show that specific impulse levels above 350 seconds can be obtained at the 0.5 kW power level.

Design Principles for Synthesizable Processor Cores

DEFF Research Database (Denmark)

Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

2012-01-01

As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

Power estimation on functional level for programmable processors

Directory of Open Access Journals (Sweden)

M. Schneider

2004-01-01

Full Text Available In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA. Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA. This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated

Power estimation on functional level for programmable processors

Science.gov (United States)

Schneider, M.; Blume, H.; Noll, T. G.

2004-05-01

In diesem Beitrag werden verschiedene Ansätze zur Verlustleistungsschätzung von programmierbaren Prozessoren vorgestellt und bezüglich ihrer Übertragbarkeit auf moderne Prozessor-Architekturen wie beispielsweise Very Long Instruction Word (VLIW)-Architekturen bewertet. Besonderes Augenmerk liegt hierbei auf dem Konzept der sogenannten Functional-Level Power Analysis (FLPA). Dieser Ansatz basiert auf der Einteilung der Prozessor-Architektur in funktionale Blöcke wie beispielsweise Processing-Unit, Clock-Netzwerk, interner Speicher und andere. Die Verlustleistungsaufnahme dieser Bl¨ocke wird parameterabhängig durch arithmetische Modellfunktionen beschrieben. Durch automatisierte Analyse von Assemblercodes des zu schätzenden Systems mittels eines Parsers können die Eingangsparameter wie beispielsweise der erzielte Parallelitätsgrad oder die Art des Speicherzugriffs gewonnen werden. Dieser Ansatz wird am Beispiel zweier moderner digitaler Signalprozessoren durch eine Vielzahl von Basis-Algorithmen der digitalen Signalverarbeitung evaluiert. Die ermittelten Schätzwerte für die einzelnen Algorithmen werden dabei mit physikalisch gemessenen Werten verglichen. Es ergibt sich ein sehr kleiner maximaler Schätzfehler von 3%. In this contribution different approaches for power estimation for programmable processors are presented and evaluated concerning their capability to be applied to modern digital signal processor architectures like e.g. Very Long InstructionWord (VLIW) -architectures. Special emphasis will be laid on the concept of so-called Functional-Level Power Analysis (FLPA). This approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory and others. The power consumption of these blocks is described by parameter dependent arithmetic model functions. By application of a parser based automized analysis of assembler codes of the systems to be estimated the input

Multithreading for Embedded Reconfigurable Multicore Systems

NARCIS (Netherlands)

Zaykov, P.G.

2014-01-01

In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor

Multithreading for embedded reconfigurable multicore systems

NARCIS (Netherlands)

Zaykov, P.G.

2014-01-01

In this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor

An embedded real-time red peach detection system based on an OV7670 camera, ARM Cortex-M4 processor and 3D Look-Up Tables

OpenAIRE

Teixidó Cairol, Mercè; Font Calafell, Davinia; Pallejà Cabrè, Tomàs; Tresánchez Ribes, Marcel; Nogués Aymamí, Miquel; Palacín Roca, Jordi

2012-01-01

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future...

Programming the Linpack Benchmark for the IBM PowerXCell 8i Processor

Directory of Open Access Journals (Sweden)

Michael Kistler

2009-01-01

Full Text Available In this paper we present the design and implementation of the Linpack benchmark for the IBM BladeCenter QS22, which incorporates two IBM PowerXCell 8i1 processors. The PowerXCell 8i is a new implementation of the Cell Broadband Engine™2 architecture and contains a set of special-purpose processing cores known as Synergistic Processing Elements (SPEs. The SPEs can be used as computational accelerators to augment the main PowerPC processor. The added computational capability of the SPEs results in a peak double precision floating point capability of 108.8 GFLOPS. We explain how we modified the standard open source implementation of Linpack to accelerate key computational kernels using the SPEs of the PowerXCell 8i processors. We describe in detail the implementation and performance of the computational kernels and also explain how we employed the SPEs for high-speed data movement and reformatting. The result of these modifications is a Linpack benchmark optimized for the IBM PowerXCell 8i processor that achieves 170.7 GFLOPS on a BladeCenter QS22 with 32 GB of DDR2 SDRAM memory. Our implementation of Linpack also supports clusters of QS22s, and was used to achieve a result of 11.1 TFLOPS on a cluster of 84 QS22 blades. We compare our results on a single BladeCenter QS22 with the base Linpack implementation without SPE acceleration to illustrate the benefits of our optimizations.

The design of infrared information collection circuit based on embedded technology

Science.gov (United States)

Liu, Haoting; Zhang, Yicong

2013-07-01

S3C2410 processor is a 16/32 bit RISC embedded processor which based on ARM920T core and AMNA bus, and mainly for handheld devices, and high cost, low-power applications. This design introduces a design plan of the PIR sensor system, circuit and its assembling, debugging. The Application Circuit of the passive PIR alarm uses the invisibility of the infrared radiation well into the alarm system, and in order to achieve the anti-theft alarm and security purposes. When the body goes into the range of PIR sensor detection, sensors will detect heat sources and then the sensor will output a weak signal. The Signal should be amplified, compared and delayed; finally light emitting diodes emit light, playing the role of a police alarm.

A heterogeneous multiprocessor architecture for low-power audio signal processing applications

DEFF Research Database (Denmark)

Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

2001-01-01

. The processors are tailored for different classes of filtering algorithms (FIR, IIR, N-LMS etc.), and in a typical system the communication among processors occurs at the sampling rate only. The processors are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs...... of the application at hand using a normal synthesis based ASIC design flow. To give an impression of the size of a processor we mention that one of the FIR processors in a prototype design has 16 instructions, a 32 word×16 bit program memory, a 64 word×16 bit data memory and a 25 word×16 bit coefficient memory....... Early results obtained from the design of a prototype chip containing filter processors for a hearing aid application, indicate a power consumption that is an order of magnitude better than current state of the art low-power audio DSPs implemented using full-custom techniques. This is due to: (1...

Simulation of a parallel processor on a serial processor: The neutron diffusion equation

International Nuclear Information System (INIS)

Honeck, H.C.

1981-01-01

Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

Design of low-power coarse-grained reconfigurable architectures

CERN Document Server

Kim, Yoonjin

2010-01-01

Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks.The first half of the book explains how to reduce power in the configuration cache. T

Digital signal array processor for NSLS booster power supply upgrade

International Nuclear Information System (INIS)

Olsen, R.; Dabrowski, J.; Murray, J.

1993-01-01

The booster at the NSLS is being upgraded from 0.75 to 2 pulses per second. To accomplish this, new power supplied for the dipole, quadrupole, and sextupole have been installed. This paper will outline the design and function of the digital signal processor used as the primary control element in the power supply control system

A Low-Power Wearable Stand-Alone Tongue Drive System for People With Severe Disabilities.

Science.gov (United States)

Jafari, Ali; Buswell, Nathanael; Ghovanloo, Maysam; Mohsenin, Tinoosh

2018-02-01

This paper presents a low-power stand-alone tongue drive system (sTDS) used for individuals with severe disabilities to potentially control their environment such as computer, smartphone, and wheelchair using their voluntary tongue movements. A low-power local processor is proposed, which can perform signal processing to convert raw magnetic sensor signals to user-defined commands, on the sTDS wearable headset, rather than sending all raw data out to a PC or smartphone. The proposed sTDS significantly reduces the transmitter power consumption and subsequently increases the battery life. Assuming the sTDS user issues one command every 20 ms, the proposed local processor reduces the data volume that needs to be wirelessly transmitted by a factor of 64, from 9.6 to 0.15 kb/s. The proposed processor consists of three main blocks: serial peripheral interface bus for receiving raw data from magnetic sensors, external magnetic interference attenuation to attenuate external magnetic field from the raw magnetic signal, and a machine learning classifier for command detection. A proof-of-concept prototype sTDS has been implemented with a low-power IGLOO-nano field programmable gate array (FPGA), bluetooth low energy, battery and magnetic sensors on a headset, and tested. At clock frequency of 20 MHz, the processor takes 6.6 s and consumes 27 nJ for detecting a command with a detection accuracy of 96.9%. To further reduce power consumption, an application-specified integrated circuit processor for the sTDS is implemented at the postlayout level in 65-nm CMOS technology with 1-V power supply, and it consumes 0.43 mW, which is 10 lower than FPGA power consumption and occupies an area of only 0.016 mm.

Dual-core Itanium Processor

CERN Multimedia

2006-01-01

Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

Low Power/Low Voltage Interface Circuitry for Capacitive Sensors

DEFF Research Database (Denmark)

Furst, Claus Efdmann

This thesis focuses mainly on low power/low voltage interface circuits, implemented in CMOS, for capacitive sensors. A brief discussion of demands and possibilities for analog signal processing in the future is presented. Techniques for low power design is presented. This is done by analyzing power...... power consumption. It is shown that the Sigma-Delta modulator is advantageous when embedded in a feedback loop with a mechanical sensor. Here a micro mechanical capacitive microphone. Feedback and detection circuitry for a capacitive microphone is presented. Practical implementations of low power....../low voltage interface circuitry is presented. It is demonstrated that an amplifier optimized for a capacitive microphone implemented in a standard 0.7 micron CMOS technology competes well with a traditional JFET amplifier. Furthermore a low power/low voltage 3rd order Sigma-Delta modulator is presented...

An analysis of electric utility embedded power supply costs

International Nuclear Information System (INIS)

Kahal, M.; Brown, D.

1998-01-01

There is little doubt that for the vast majority of electric utilities the embedded costs of power supply exceed market prices, giving rise to the stranded cost problem. Beyond that simple generalization, there are a number of crucial questions, which this study attempts to answer. What are the regional patterns of embedded cost differences? To what extent is the cost problem attributable to nuclear power? How does the cost of purchased power compare to the cost of utility self-generation? What is the breakdown of utility embedded generation costs between operating costs - which are potentially avoidable--and ownership costs, which by definition are ''sunk'' and therefore not avoidable? How will embedded generation costs and market prices compare over time? These are the crucial questions for states as they address retail-restructuring proposal. This study presents an analysis of generation costs, which addresses these key questions. A computerized costing model was developed and applied using FERC Form 1 data for 1995. The model analyzed embedded power supply costs (i.e.; self-generation plus purchased power) for two groups of investor-owned utilities, 49 non-nuclear vs. 63 nuclear. These two subsamples represent substantially the entire US investor-owned electric utility industry. For each utility, embedded cost is estimated both at busbar and at meter

Self-Organization in Embedded Real-Time Systems

CERN Document Server

Brinkschulte, Uwe; Rettberg, Achim

2013-01-01

This book describes the emerging field of self-organizing, multicore, distributed and real-time embedded systems.  Self-organization of both hardware and software can be a key technique to handle the growing complexity of modern computing systems. Distributed systems running hundreds of tasks on dozens of processors, each equipped with multiple cores, requires self-organization principles to ensure efficient and reliable operation. This book addresses various, so-called Self-X features such as self-configuration, self-optimization, self-adaptation, self-healing and self-protection. Presents open components for embedded real-time adaptive and self-organizing applications; Describes innovative techniques in: scheduling, memory management, quality of service, communications supporting organic real-time applications; Covers multi-/many-core embedded systems supporting real-time adaptive systems and power-aware, adaptive hardware and software systems; Includes case studies of open embedded real-time self-organizi...

Enabling MPEG-2 video playback in embedded systems through improved data cache efficiency

Science.gov (United States)

Soderquist, Peter; Leeser, Miriam E.

1999-01-01

Digital video decoding, enabled by the MPEG-2 Video standard, is an important future application for embedded systems, particularly PDAs and other information appliances. Many such system require portability and wireless communication capabilities, and thus face severe limitations in size and power consumption. This places a premium on integration and efficiency, and favors software solutions for video functionality over specialized hardware. The processors in most embedded system currently lack the computational power needed to perform video decoding, but a related and equally important problem is the required data bandwidth, and the need to cost-effectively insure adequate data supply. MPEG data sets are very large, and generate significant amounts of excess memory traffic for standard data caches, up to 100 times the amount required for decoding. Meanwhile, cost and power limitations restrict cache sizes in embedded systems. Some systems, including many media processors, eliminate caches in favor of memories under direct, painstaking software control in the manner of digital signal processors. Yet MPEG data has locality which caches can exploit if properly optimized, providing fast, flexible, and automatic data supply. We propose a set of enhancements which target the specific needs of the heterogeneous types within the MPEG decoder working set. These optimizations significantly improve the efficiency of small caches, reducing cache-memory traffic by almost 70 percent, and can make an enhanced 4 KB cache perform better than a standard 1 MB cache. This performance improvement can enable high-resolution, full frame rate video playback in cheaper, smaller system than woudl otherwise be possible.

Embedded Solenoid Transformer for Power Conversion

DEFF Research Database (Denmark)

2015-01-01

A resonant power converter for operation in the radio frequency range, preferably in the VHF, comprises at least one PCB-embedded transformer. The transformer is configured for radio frequency operation and comprises a printed circuit board defining a horizontal plane, the printed circuit board...... comprising at least two horizontal conductive layers separated by an isolating layer, a first embedded solenoid forming a primary winding of the transformer and a second embedded solenoid being arranged parallel to the first solenoid and forming a secondary winding of the transformer, wherein the first...

Diverse Power Iteration Embeddings and Its Applications

Energy Technology Data Exchange (ETDEWEB)

Huang H.; Yoo S.; Yu, D.; Qin, H.

2014-12-14

Abstract—Spectral Embedding is one of the most effective dimension reduction algorithms in data mining. However, its computation complexity has to be mitigated in order to apply it for real-world large scale data analysis. Many researches have been focusing on developing approximate spectral embeddings which are more efficient, but meanwhile far less effective. This paper proposes Diverse Power Iteration Embeddings (DPIE), which not only retains the similar efficiency of power iteration methods but also produces a series of diverse and more effective embedding vectors. We test this novel method by applying it to various data mining applications (e.g. clustering, anomaly detection and feature selection) and evaluating their performance improvements. The experimental results show our proposed DPIE is more effective than popular spectral approximation methods, and obtains the similar quality of classic spectral embedding derived from eigen-decompositions. Moreover it is extremely fast on big data applications. For example in terms of clustering result, DPIE achieves as good as 95% of classic spectral clustering on the complex datasets but 4000+ times faster in limited memory environment.

An Efficient Power Estimation Methodology for Complex RISC Processor-based Platforms

OpenAIRE

Rethinagiri , Santhosh Kumar; Ben Atitallah , Rabie; Dekeyser , Jean-Luc; Niar , Smail; Senn , Eric

2012-01-01

International audience; In this contribution, we propose an efficient power estima- tion methodology for complex RISC processor-based plat- forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evalu- ate accurately the activities used in the related power mod- els. The combination of the two parts above leads to a het- erogeneou...

Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

OpenAIRE

Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

2016-01-01

Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

Implementation of an EPICS IOC on an Embedded Soft Core Processor Using Field Programmable Gate Arrays

International Nuclear Information System (INIS)

Douglas Curry; Alicia Hofler; Hai Dong; Trent Allison; J. Hovater; Kelly Mahoney

2005-01-01

At Jefferson Lab, we have been evaluating soft core processors running an EPICS IOC over μClinux on our custom hardware. A soft core processor is a flexible CPU architecture that is configured in the FPGA as opposed to a hard core processor which is fixed in silicon. Combined with an on-board Ethernet port, the technology incorporates the IOC and digital control hardware within a single FPGA. By eliminating the general purpose computer IOC, the designer is no longer tied to a specific platform, e.g. PC, VME, or VXI, to serve as the intermediary between the high level controls and the field hardware. This paper will discuss the design and development process as well as specific applications for JLab's next generation low-level RF controls and Machine Protection Systems

Power-Energy Simulation for Multi-Core Processors in Bench-marking

Directory of Open Access Journals (Sweden)

Mona A. Abou-Of

2017-01-01

Full Text Available At Microarchitectural level, multi-core processor, as a complex System on Chip, has sophisticated on-chip components including cores, shared caches, interconnects and system controllers such as memory and ethernet controllers. At technological level, architects should consider the device types forecast in the International Technology Roadmap for Semiconductors (ITRS. Energy simulation enables architects to study two important metrics simultaneously. Timing is a key element of the CPU performance that imposes constraints on the CPU target clock frequency. Power and the resulting heat impose more severe design constraints, such as core clustering, while semiconductor industry is providing more transistors in the die area in pace with Moore’s law. Energy simulators provide a solution for such serious challenge. Energy is modelled either by combining performance benchmarking tool with a power simulator or by an integrated framework of both performance simulator and power profiling system. This article presents and asses trade-offs between different architectures using four cores battery-powered mobile systems by running a custom-made and a standard benchmark tools. The experimental results assure the Energy/ Frequency convexity rule over a range of frequency settings on different number of enabled cores. The reported results show that increasing the number of cores has a great effect on increasing the power consumption. However, a minimum energy dissipation will occur at a lower frequency which reduces the power consumption. Despite that, increasing the number of cores will also increase the effective cores value which will reflect a better processor performance.

Computers as components principles of embedded computing system design

CERN Document Server

Wolf, Marilyn

2012-01-01

Computers as Components: Principles of Embedded Computing System Design, 3e, presents essential knowledge on embedded systems technology and techniques. Updated for today's embedded systems design methods, this edition features new examples including digital signal processing, multimedia, and cyber-physical systems. Author Marilyn Wolf covers the latest processors from Texas Instruments, ARM, and Microchip Technology plus software, operating systems, networks, consumer devices, and more. Like the previous editions, this textbook: Uses real processors to demonstrate both technology and tec

Design and implementation of an ultra-low power passive UHF RFID tag

International Nuclear Information System (INIS)

Shen Jinpeng; Wang Xin'an; Liu Shan; Zong Hongqiang; Huang Jinfeng; Yang Xin; Feng Xiaoxing; Ge Binjie

2012-01-01

This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 μm CMOS process with a die size of 800 × 800 μm 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 μW with a sensitivity of −12 dBm. (semiconductor integrated circuits)

3081/E processor

International Nuclear Information System (INIS)

Kunz, P.F.; Gravina, M.; Oxoby, G.

1984-04-01

The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

FPGA Based Low Power ROM Design Using Capacitance Scaling

DEFF Research Database (Denmark)

Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

2015-01-01

An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

Energy efficiency vs. performance of the numerical solution of PDEs: An application study on a low-power ARM-based cluster

Science.gov (United States)

Göddeke, Dominik; Komatitsch, Dimitri; Geveler, Markus; Ribbrock, Dirk; Rajovic, Nikola; Puzovic, Nikola; Ramirez, Alex

2013-03-01

Power consumption and energy efficiency are becoming critical aspects in the design and operation of large scale HPC facilities, and it is unanimously recognised that future exascale supercomputers will be strongly constrained by their power requirements. At current electricity costs, operating an HPC system over its lifetime can already be on par with the initial deployment cost. These power consumption constraints, and the benefits a more energy-efficient HPC platform may have on other societal areas, have motivated the HPC research community to investigate the use of energy-efficient technologies originally developed for the embedded and especially mobile markets. However, lower power does not always mean lower energy consumption, since execution time often also increases. In order to achieve competitive performance, applications then need to efficiently exploit a larger number of processors. In this article, we discuss how applications can efficiently exploit this new class of low-power architectures to achieve competitive performance. We evaluate if they can benefit from the increased energy efficiency that the architecture is supposed to achieve. The applications that we consider cover three different classes of numerical solution methods for partial differential equations, namely a low-order finite element multigrid solver for huge sparse linear systems of equations, a Lattice-Boltzmann code for fluid simulation, and a high-order spectral element method for acoustic or seismic wave propagation modelling. We evaluate weak and strong scalability on a cluster of 96 ARM Cortex-A9 dual-core processors and demonstrate that the ARM-based cluster can be more efficient in terms of energy to solution when executing the three applications compared to an x86-based reference machine.

Instruction transfer and storage exploration for low energy embedded VLIWs

NARCIS (Netherlands)

Aa, van der T.

2005-01-01

Portable consumer electronics to play multimedia have to be high performant and flexible. Energy consumption has to be kept as low as possible to ensure a long battery lifetime. To be flexible, these systems often contain an instruction set processor. Very Long Instruction Word (VLIW) processors

A low-cost high-performance embedded platform for accelerator controls

International Nuclear Information System (INIS)

Cleva, Stefano; Bogani, Alessio Igor; Pivetta, Lorenzo

2012-01-01

Over the last years the mobile and hand-held device market has seen a dramatic performance improvement of the microprocessors employed for these systems. As an interesting side effect, this brings the opportunity of adopting these microprocessors to build small low-cost embedded boards, featuring lots of processing power and input/output capabilities. Moreover, being capable of running a full featured operating system such as Gnu/Linux, and even a control system toolkit such as Tango, these boards can also be used in control systems as front-end or embedded computers. In order to evaluate the feasibility of this idea, an activity has started at Elettra to select, evaluate and validate a commercial embedded device able to guarantee production grade reliability, competitive costs and an open source platform. The preliminary results of this work are presented. (author)

Nested Interrupt Analysis of Low Cost and High Performance Embedded Systems Using GSPN Framework

Science.gov (United States)

Lin, Cheng-Min

Interrupt service routines are a key technology for embedded systems. In this paper, we introduce the standard approach for using Generalized Stochastic Petri Nets (GSPNs) as a high-level model for generating CTMC Continuous-Time Markov Chains (CTMCs) and then use Markov Reward Models (MRMs) to compute the performance for embedded systems. This framework is employed to analyze two embedded controllers with low cost and high performance, ARM7 and Cortex-M3. Cortex-M3 is designed with a tail-chaining mechanism to improve the performance of ARM7 when a nested interrupt occurs on an embedded controller. The Platform Independent Petri net Editor 2 (PIPE2) tool is used to model and evaluate the controllers in terms of power consumption and interrupt overhead performance. Using numerical results, in spite of the power consumption or interrupt overhead, Cortex-M3 performs better than ARM7.

Low power digital signal processing

DEFF Research Database (Denmark)

Paker, Ozgun

2003-01-01

hardwired ASICs and more than 6 21 times lower than current state of the art low-power DSP processors. An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved...... to be a viable alternative to conventional expensive test equipment. Finally, the work presented in this thesis has been published at several IEEE workshops and conferences, and in the Journal of VLSI Signal Processing....

Applying formal method to design of nuclear power plant embedded protection system

International Nuclear Information System (INIS)

Kim, Jin Hyun; Kim, Il Gon; Sung, Chang Hoon; Choi, Jin Young; Lee, Na Young

2001-01-01

Nuclear power embedded protection systems is a typical safety-critical system, which detects its failure and shutdowns its operation of nuclear reactor. These systems are very dangerous so that it absolutely requires safety and reliability. Therefore nuclear power embedded protection system should fulfill verification and validation completely from the design stage. To develop embedded system, various V and V method have been provided and especially its design using Formal Method is studied in other advanced country. In this paper, we introduce design method of nuclear power embedded protection systems using various Formal-Method in various respect following nuclear power plant software development guideline

16-Bit RISC Processor Design for Convolution Application

OpenAIRE

Anand Nandakumar Shardul

2013-01-01

In this project, we propose a 16-bit non-pipelined RISC processor, which is used for signal processing applications. The processor consists of the blocks, namely, program counter, clock control unit, ALU, IDU and registers. Advantageous architectural modifications have been made in the incremented circuit used in program counter and carry select adder unit of the ALU in the RISC CPU core. Furthermore, a high speed and low power modified modifies multiplier has been designed and introduced in ...

Design of embedded control system for high-power tetrode modulator

International Nuclear Information System (INIS)

Tu Rui; Yao Lieying; Xuan Weimin

2010-01-01

The design of embedded control system for the high-power tetrode modulator and its test results are given. This control system is a closed-loop feedback system based on the DSP and embedded into the high-voltage modulator. A new modified method of VF fiber transmission is used in the embedded control system. The new method improves the speed of the transmission of feedback system. The results of the experiment demonstrate that the embedded feedback control system greatly increases the response speed of the whole system and improves the performance of the high-power tetrode on the HL-2A tokamak. This embedded feedback control system greatly simplifies the complexity of the original centralized control system. The operation of the control system is reliable. (authors)

A embedded Linux system based on PowerPC

International Nuclear Information System (INIS)

Ye Mei; Zhao Jingwei; Chu Yuanping

2006-01-01

The authors will introduce a Embedded Linux System based on PowerPC as well as the base method on how to establish the system. The goal of the system is to build a test system of VMEbus device. It also can be used to setup the small data acquisition and control system. Two types of compiler are provided by the developer system according to the features of the system and the Power PC. At the top of the article some typical embedded Operation system will be introduced and the features of different system will be provided. And then the method on how to build a embedded Linux system as well as the key technique will be discussed in detail. Finally a successful read-write example will be given based on the test system. (authors)

A low-power asynchronous data-path for a FIR filter bank

DEFF Research Database (Denmark)

Nielsen, Lars Skovby; Sparsø, Jens

1996-01-01

This paper describes a number of design issues relating to the implementation of low-power asynchronous signal processing circuits. Specifically, the paper addresses the design of a dedicated processor structure that implements an audio FIR filter bank which is part of an industrial application....... The algorithm requires a fixed number of steps and the moderate speed requirement allows a sequential implementation. The latter, in combination with a huge predominance of numerically small data values in the input data stream, is the key to a low-power asynchronous implementation. Power is minimized in two...

On-Road Driver Monitoring System Based on a Solar-Powered In-Vehicle Embedded Platform

OpenAIRE

Yen-Lin Chen; Chao-Wei Yu; Zi-Jie Chien; Chin-Hsuan Liu; Hsin-Han Chiang

2014-01-01

This study presents an on-road driver monitoring system, which is implemented on a stand-alone in-vehicle embedded system and driven by effective solar cells. The driver monitoring function is performed by an efficient eye detection technique. Through the driver’s eye movements captured from the camera, the attention states of the driver can be determined and any fatigue states can be avoided. This driver monitoring technique is implemented on a low-power embedded in-vehicle platform. Besides...

Embedded systems design with special arithmetic and number systems

CERN Document Server

Sousa, Leonel; Chang, Chip-Hong

2017-01-01

This book introduces readers to alternative approaches to designing efficient embedded systems using unconventional number systems. The authors describe various systems that can be used for designing efficient embedded and application-specific processors, such as Residue Number System, Logarithmic Number System, Redundant Binary Number System Double-Base Number System, Decimal Floating Point Number System and Continuous Valued Number System. Readers will learn the strategies and trade-offs of using unconventional number systems in application-specific processors and be able to apply and design appropriate arithmetic operations from these number systems to boost the performance of digital systems. • Serves as a single-source reference to designing embedded systems with unconventional number systems • Covers theory as well as implementation on application-specific processors • Explains mathematical concepts in a manner accessible to readers with diverse backgrounds.

PCB Embedded Inductor for High-Frequency ZVS SEPIC Converter

DEFF Research Database (Denmark)

Dou, Yi; Ouyang, Ziwei; Thummala, Prasanth

2018-01-01

The volume and temperature rise of passive components, especially inductors, limit the momentum toward high power density in high-frequency power converters. To address the limitations, PCB integration of passive components should be considered with the benefit of low profile, excellent thermal...... characteristic and cost reduction. This paper investigates an embedded structure of inductors to further increase the power density of a low power DC-DC converter. A pair of coupling inductors have been embedded into the PCB. The detailed embedded process has been described and the characteristics of embedded...

Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

Directory of Open Access Journals (Sweden)

Oscar Montiel-Ross

2012-01-01

Full Text Available This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

Embedded Face Detection and Recognition

Directory of Open Access Journals (Sweden)

Göksel Günlü

2012-10-01

Full Text Available The need to increase security in open or public spaces has in turn given rise to the requirement to monitor these spaces and analyse those images on-site and on-time. At this point, the use of smart cameras – of which the popularity has been increasing – is one step ahead. With sensors and Digital Signal Processors (DSPs, smart cameras generate ad hoc results by analysing the numeric images transmitted from the sensor by means of a variety of image-processing algorithms. Since the images are not transmitted to a distance processing unit but rather are processed inside the camera, it does not necessitate high-bandwidth networks or high processor powered systems; it can instantaneously decide on the required access. Nonetheless, on account of restricted memory, processing power and overall power, image processing algorithms need to be developed and optimized for embedded processors. Among these algorithms, one of the most important is for face detection and recognition. A number of face detection and recognition methods have been proposed recently and many of these methods have been tested on general-purpose processors. In smart cameras – which are real-life applications of such methods – the widest use is on DSPs. In the present study, the Viola-Jones face detection method – which was reported to run faster on PCs – was optimized for DSPs; the face recognition method was combined with the developed sub-region and mask-based DCT (Discrete Cosine Transform. As the employed DSP is a fixed-point processor, the processes were performed with integers insofar as it was possible. To enable face recognition, the image was divided into sub-regions and from each sub-region the robust coefficients against disruptive elements – like face expression, illumination, etc. – were selected as the features. The discrimination of the selected features was enhanced via LDA (Linear Discriminant Analysis and then employed for recognition. Thanks to its

Multi-Threaded Dense Linear Algebra Libraries for Low-Power Asymmetric Multicore Processors

OpenAIRE

Catalán, Sandra; Herrero, José R.; Igual, Francisco D.; Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

2015-01-01

Dense linear algebra libraries, such as BLAS and LAPACK, provide a relevant collection of numerical tools for many scientific and engineering applications. While there exist high performance implementations of the BLAS (and LAPACK) functionality for many current multi-threaded architectures,the adaption of these libraries for asymmetric multicore processors (AMPs)is still pending. In this paper we address this challenge by developing an asymmetry-aware implementation of the BLAS, based on the...

How to create a very-low cost, very-low-power, credit-card-sized and real-time ready datalogger

Science.gov (United States)

Bès de Berc, Maxime; Grunberg, Marc; Engels, Fabien

2014-05-01

In some cases a field instrumentalist could have to add some extra sensors in a remote station. Additional ADCs (Analogic Digital Converters) are not always implemented on commercial dataloggers, or may already be used. Adding more ADCs often implies an expensive development, or buy a new datalogger. We present here a very simple way to deploy an embedded ARM computer, use its features and embedded ADCs to create datas in a seismological standard format and integrating it within the real-time data stream from the station. In the past few years, because of the market growth of telephony and mobile applications, the ARM processor from ARM Ltd has become very common and available at a reasonable price. This processor has the particularity to be an excellent compromise between its frequency and its power consumption. That's why most of smartphones and tablets feature nowadays that kind of processor. It is also available on the market as Soc (System on Chip) or complete embedded computer. The most known is probably the Raspberry Pi, but many ohers exist like the BeagleBone or BeagleBoard. This kind of computer can be bought between 35€ for Raspberry Pi and several hundred Euro for more industrial products. Each model often embed some ADCs on its chip or some special buses, allowing additional ADCs to be easily used. Our experiment has been made on a BeagleBone platform, available at 78€. We chose it because its a more mature product than Raspberry Pi, it has all connectors and options needed: seven ADCs, an USB port for local backup, an Ethernet port for real-time streams, and some useful things like GPIO and I2C buses. Our goal was to plug temperature and humidity sensors on the ADCs, read datas, record them in mini-SEED format (Standard for the Exchange of the Earthquake Data), and transmit those datas to a central server as a secondary source for a remote station, by using Seedlink, which is a standard for seismology. Seedlink is a real-time data acquisition

Video coding for decoding power-constrained embedded devices

Science.gov (United States)

Lu, Ligang; Sheinin, Vadim

2004-01-01

Low power dissipation and fast processing time are crucial requirements for embedded multimedia devices. This paper presents a technique in video coding to decrease the power consumption at a standard video decoder. Coupled with a small dedicated video internal memory cache on a decoder, the technique can substantially decrease the amount of data traffic to the external memory at the decoder. A decrease in data traffic to the external memory at decoder will result in multiple benefits: faster real-time processing and power savings. The encoder, given prior knowledge of the decoder"s dedicated video internal memory cache management scheme, regulates its choice of motion compensated predictors to reduce the decoder"s external memory accesses. This technique can be used in any standard or proprietary encoder scheme to generate a compliant output bit stream decodable by standard CPU-based and dedicated hardware-based decoders for power savings with the best quality-power cost trade off. Our simulation results show that with a relatively small amount of dedicated video internal memory cache, the technique may decrease the traffic between CPU and external memory over 50%.

Powering embedded electronics for wind turbine monitoring using multi-source energy harvesting techniques

Science.gov (United States)

Anton, S. R.; Taylor, S. G.; Raby, E. Y.; Farinholt, K. M.

2013-03-01

With a global interest in the development of clean, renewable energy, wind energy has seen steady growth over the past several years. Advances in wind turbine technology bring larger, more complex turbines and wind farms. An important issue in the development of these complex systems is the ability to monitor the state of each turbine in an effort to improve the efficiency and power generation. Wireless sensor nodes can be used to interrogate the current state and health of wind turbine structures; however, a drawback of most current wireless sensor technology is their reliance on batteries for power. Energy harvesting solutions present the ability to create autonomous power sources for small, low-power electronics through the scavenging of ambient energy; however, most conventional energy harvesting systems employ a single mode of energy conversion, and thus are highly susceptible to variations in the ambient energy. In this work, a multi-source energy harvesting system is developed to power embedded electronics for wind turbine applications in which energy can be scavenged simultaneously from several ambient energy sources. Field testing is performed on a full-size, residential scale wind turbine where both vibration and solar energy harvesting systems are utilized to power wireless sensing systems. Two wireless sensors are investigated, including the wireless impedance device (WID) sensor node, developed at Los Alamos National Laboratory (LANL), and an ultra-low power RF system-on-chip board that is the basis for an embedded wireless accelerometer node currently under development at LANL. Results indicate the ability of the multi-source harvester to successfully power both sensors.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

Millar James

2006-01-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

Directory of Open Access Journals (Sweden)

James Millar

2006-10-01

Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

A Trade Study of Two Membrane-Aerated Biological Water Processors

Science.gov (United States)

Allada, Ram; Lange, Kevin; Vega. Leticia; Roberts, Michael S.; Jackson, Andrew; Anderson, Molly; Pickering, Karen

2011-01-01

Biologically based systems are under evaluation as primary water processors for next generation life support systems due to their low power requirements and their inherent regenerative nature. This paper will summarize the results of two recent studies involving membrane aerated biological water processors and present results of a trade study comparing the two systems with regards to waste stream composition, nutrient loading and system design. Results of optimal configurations will be presented.

An Embedded Real-Time Red Peach Detection System Based on an OV7670 Camera, ARM Cortex-M4 Processor and 3D Look-Up Tables

Directory of Open Access Journals (Sweden)

Marcel Tresanchez

2012-10-01

Full Text Available This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6 processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

An embedded real-time red peach detection system based on an OV7670 camera, ARM cortex-M4 processor and 3D look-up tables.

Science.gov (United States)

Teixidó, Mercè; Font, Davinia; Pallejà, Tomàs; Tresanchez, Marcel; Nogués, Miquel; Palacín, Jordi

2012-10-22

This work proposes the development of an embedded real-time fruit detection system for future automatic fruit harvesting. The proposed embedded system is based on an ARM Cortex-M4 (STM32F407VGT6) processor and an Omnivision OV7670 color camera. The future goal of this embedded vision system will be to control a robotized arm to automatically select and pick some fruit directly from the tree. The complete embedded system has been designed to be placed directly in the gripper tool of the future robotized harvesting arm. The embedded system will be able to perform real-time fruit detection and tracking by using a three-dimensional look-up-table (LUT) defined in the RGB color space and optimized for fruit picking. Additionally, two different methodologies for creating optimized 3D LUTs based on existing linear color models and fruit histograms were implemented in this work and compared for the case of red peaches. The resulting system is able to acquire general and zoomed orchard images and to update the relative tracking information of a red peach in the tree ten times per second.

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

2014-01-01

The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

Embedded Systems Design with FPGAs

CERN Document Server

Pnevmatikatos, Dionisios; Sklavos, Nicolas

2013-01-01

This book presents methodologies for modern applications of embedded systems design, using field programmable gate array (FPGA) devices.  Coverage includes state-of-the-art research from academia and industry on a wide range of topics, including advanced electronic design automation (EDA), novel system architectures, embedded processors, arithmetic, dynamic reconfiguration and applications. Describes a variety of methodologies for modern embedded systems design;  Implements methodologies presented on FPGAs; Covers a wide variety of applications for reconfigurable embedded systems, including Bioinformatics, Communications and networking, Application acceleration, Medical solutions, Experiments for high energy physics, Astronomy, Aerospace, Biologically inspired systems and Computational fluid dynamics (CFD).

PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

Directory of Open Access Journals (Sweden)

R. Maheswari

2012-04-01

Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

Voltage scheduling for low power/energy

Science.gov (United States)

Manzak, Ali

2001-07-01

Power considerations have become an increasingly dominant factor in the design of both portable and desk-top systems. An effective way to reduce power consumption is to lower the supply voltage since voltage is quadratically related to power. This dissertation considers the problem of lowering the supply voltage at (i) the system level and at (ii) the behavioral level. At the system level, the voltage of the variable voltage processor is dynamically changed with the work load. Processors with limited sized buffers as well as those with very large buffers are considered. Given the task arrival times, deadline times, execution times, periods and switching activities, task scheduling algorithms that minimize energy or peak power are developed for the processors equipped with very large buffers. A relation between the operating voltages of the tasks for minimum energy/power is determined using the Lagrange multiplier method, and an iterative algorithm that utilizes this relation is developed. Experimental results show that the voltage assignment obtained by the proposed algorithm is very close (0.1% error) to that of the optimal energy assignment and the optimal peak power (1% error) assignment. Next, on-line and off-fine minimum energy task scheduling algorithms are developed for processors with limited sized buffers. These algorithms have polynomial time complexity and present optimal (off-line) and close-to-optimal (on-line) solutions. A procedure to calculate the minimum buffer size given information about the size of the task (maximum, minimum), execution time (best case, worst case) and deadlines is also presented. At the behavioral level, resources operating at multiple voltages are used to minimize power while maintaining the throughput. Such a scheme has the advantage of allowing modules on the critical paths to be assigned to the highest voltage levels (thus meeting the required timing constraints) while allowing modules on non-critical paths to be assigned

Suitability of tile-based rendering for low-power 3d graphics accelerators

NARCIS (Netherlands)

Antochi, I.

2007-01-01

In this dissertation, we address low-power high performance 3D graphics accelerator architectures. The purpose of these accelerators is to relieve the burden of graphical computations from the main processor and also to achieve a better energy efficiency than can be achieved by executing these

Reliability analysis of wind embedded power generation system for ...

African Journals Online (AJOL)

This paper presents a method for Reliability Analysis of wind energy embedded in power generation system for Indian scenario. This is done by evaluating the reliability index, loss of load expectation, for the power generation system with and without integration of wind energy sources in the overall electric power system.

Composable Virtual Platforms for Mixed-Criticality Embedded Systems

NARCIS (Netherlands)

Beyranvand Nejad, A.

2014-01-01

Recent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as

Composable virtual platforms for mixed-criticality embedded systems

NARCIS (Netherlands)

Nejad, A.B.

2014-01-01

Recent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as

The power processor of a high temperature superconducting energy storage system

Energy Technology Data Exchange (ETDEWEB)

Ollila, J. [Power Electronics, Tampere University of Technology, Tampere (Finland)

1997-12-31

This report introduces the structure and properties of a power processor unit for a high temperature superconducting magnetic energy storage system which is bused in an UPS demonstration application. The operation is first demonstrated using simulations. The software based operating and control system utilising combined Delta-Sigma and Sliding-Mode control is described shortly. Preliminary test results using a conventional NbTi superconducting energy y storage magnet operating at 4.2 K is shown. (orig.)

A HARDWARE SUPPORTED OPERATING SYSTEM KERNEL FOR EMBEDDED HARD REAL-TIME APPLICATIONS

NARCIS (Netherlands)

COLNARIC, M; HALANG, WA; TOL, RM

1994-01-01

The concept of the kernel, i.e. the time critical part of a real-time operating system, and its dedicated co-processor, especially tailored for embedded applications, are presented. The co-processor acts as a system controller and operates in conjunction with one or more conventional processors in

Regulatory Experience of the Embedded Digital Devices for Safety I and C Systems on Nuclear Power Plants

Energy Technology Data Exchange (ETDEWEB)

Kim, Y. M.; Lee, H. K.; Park, H. S. [Korea Institute of Nuclear Safety, Daejeon (Korea, Republic of)

2016-10-15

Conventional I and C(Instrumentation and Control) systems are tend to becoming unavailable and being replaced by smart equipment. These smart equipment is usually called embedded digital devices (EDDs) or industrial digital devices of limited functionality. Usually, some of these devices are found embedded in plant equipment such as sensing instrumentation, motors, pumps, actuators and breakers. They typically have a micro-processor, RAM, communication interface, a power source, etc. The U.S. Nuclear Regulatory Commission (US NRC) is concerning that these EDDs might exist in procured equipment used in safety systems without the devices having been explicitly identified in procurement documentation. This paper addresses the regulatory experiences of KINS of the EDDs for safety I and C systems and the future works for them. In this paper, we showed regulatory experiences of EDDs which used for safety grade equipment. EDDs might exist in safety grade procured equipment without explicit identification. Undetected defects of EDDs might be the potential safety concerns. EDDs should meet certain specific requirements in order to be selected and used in safety I and C system. We have plan to develop technical positions for identification and qualifying them. The technical position will address, but may not be limited to, quality and reliability, CCFs via software errors, EMC, and CGID for EDDs.

Introduction to embedded systems using microcontrollers and the MSP430

CERN Document Server

Jiménez, Manuel; Couvertier, Isidoro

2014-01-01

This textbook serves as an introduction to the subject of embedded systems design, using microcontrollers as core components.  It develops concepts from the ground up, covering the development of embedded systems technology, architectural and organizational aspects of controllers and systems, processor models, and peripheral devices. Since microprocessor-based embedded systems tightly blend hardware and software components in a single application, the book also introduces the subjects of data representation formats, data operations, and programming styles. The practical component of the book is tailored around the architecture of a widely used Texas Instrument’s microcontroller, the MSP430. Instructor’s supplemental materials available through the book web site include solutions to selected problems and exercises and power point slides for lectures. The site also includes materials for students that include links to application examples and to sites elsewhere in the web with application notes, downloadab...

Pixel detector bias supply and control using embedded multicore processors

CERN Document Server

AUTHOR|(CDS)2099144; Akram Alomainy

The aim of the project is to create a software controlled, open source, low footprint and low power high voltage bias supply and current monitor for a pixelated radiation sensor. The solution is based on the LT3905 integrated circuit and the multi-core XMOS xCore 200 microcontroller and it is intended to be used in a battery powered, mobile platform for educational settings.

A single chip pulse processor for nuclear spectroscopy

International Nuclear Information System (INIS)

Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

1985-01-01

A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

Science.gov (United States)

Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

2013-03-01

With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

Density matrix embedding in an antisymmetrized geminal power bath

International Nuclear Information System (INIS)

Tsuchimochi, Takashi; Welborn, Matthew; Van Voorhis, Troy

2015-01-01

Density matrix embedding theory (DMET) has emerged as a powerful tool for performing wave function-in-wave function embedding for strongly correlated systems. In traditional DMET, an accurate calculation is performed on a small impurity embedded in a mean field bath. Here, we extend the original DMET equations to account for correlation in the bath via an antisymmetrized geminal power (AGP) wave function. The resulting formalism has a number of advantages. First, it allows one to properly treat the weak correlation limit of independent pairs, which DMET is unable to do with a mean-field bath. Second, it associates a size extensive correlation energy with a given density matrix (for the models tested), which AGP by itself is incapable of providing. Third, it provides a reasonable description of charge redistribution in strongly correlated but non-periodic systems. Thus, AGP-DMET appears to be a good starting point for describing electron correlation in molecules, which are aperiodic and possess both strong and weak electron correlation

Digital Signal Processor System for AC Power Drivers

Directory of Open Access Journals (Sweden)

Ovidiu Neamtu

2009-10-01

Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

Power management implementation in FreeRTOS on LM3S3748

Directory of Open Access Journals (Sweden)

Simonović Mirela

2013-01-01

Full Text Available Power consumption has become a major concern of embedded systems today. With the aim to reduce power consumption during the runtime, operating systems are dealing with power management. In this work, the FreeRTOS port is extended with power management features on LM3S3748 microcontroller. Tickless idle technique is implemented to provide more powersaving during the processor idle periods.

Dataflow formalisation of real-time streaming applications on a composable and predictable multi-processor SOC

NARCIS (Netherlands)

Nelson, A.T.; Goossens, K.G.W.; Akesson, K.B.

2015-01-01

Embedded systems often contain multiple applications, some of which have real-time requirements and whose performance must be guaranteed. To efficiently execute applications, modern embedded systems contain Globally Asynchronous Locally Synchronous (GALS) processors, network on chip, DRAM and SRAM

Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

Science.gov (United States)

Badoni, D.; Bizzarri, M.; Bonaiuto, V.; Checcucci, B.; De Simone, N.; Federici, L.; Fucci, A.; Paoluzzi, G.; Papi, A.; Piccini, M.; Salamon, A.; Salina, G.; Santovetti, E.; Sargeni, F.; Venditti, S.

2014-01-01

The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K+→π+ ν bar nu with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K+→π+ π0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests.

Use of FPGA embedded processors for fast cluster reconstruction in the NA62 liquid krypton electromagnetic calorimeter

International Nuclear Information System (INIS)

Badoni, D; Fucci, A; Paoluzzi, G; Salamon, A; Salina, G; Bizzarri, M; Bonaiuto, V; Simone, N De; Federici, L; Sargeni, F; Checcucci, B; Papi, A; Piccini, M; Santovetti, E; Venditti, S

2014-01-01

The goal of the NA62 experiment at the CERN SPS is the measurement of the Branching Ratio of the very rare kaon decay K + →π +  ν ν-bar with a 10% accuracy by collecting 100 events in two years of data taking. An efficient photon veto system is needed to reject the K + →π +  π 0 background and a liquid krypton electromagnetic calorimeter will be used for this purpose in the 1-10 mrad angular region. The L0 trigger system for the calorimeter consists of a peak reconstruction algorithm implemented on FPGA by using a mixed parallel architecture based on soft core Altera NIOS II embedded processors together with custom VHDL modules. This solution allows an efficient and flexible reconstruction of the energy-deposition peak. The system will be totally composed of 36 TEL62 boards, 108 mezzanine cards and 215 high-performance FPGAs. We describe the design, current status and the results of the first performance tests

Imprecise Arithmetic for Low Power Image Processing

DEFF Research Database (Denmark)

Albicocco, Pietro; Cardarilli, Gian Carlo; Nannarelli, Alberto

2012-01-01

Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, additio...... and multiplication, in an imprecise manner by simplifying the hardware implementation. With the proposed ”sloppy” operations, we obtain a reduction in delay, area and power dissipation, and the error introduced is still acceptable for applications such as image processing.......Sometimes reducing the precision of a numerical processor, by introducing errors, can lead to significant performance (delay, area and power dissipation) improvements without compromising the overall quality of the processing. In this work, we show how to perform the two basic operations, addition...

Thermal performance of a PCB embedded pulsating heat pipe for power electronics applications

International Nuclear Information System (INIS)

Kearney, Daniel J.; Suleman, Omar; Griffin, Justin; Mavrakis, Georgios

2016-01-01

Highlights: • Planar, compact PCB embedded pulsating heat pipe for heat spreading applications. • Embedded heat pipe operates at sub-ambient pressure with environmentally. • Compatible fluids. • Range of optimum operating conditions, orientations and fill ratios identified. - Abstract: Low voltage power electronics applications (<1.2 kV) are pushing the design envelope towards increased functionality, better reliability, low profile and reduced cost. One packaging method to enable these constraints is the integration of active power electronic devices into the printed circuit board improving electrical and thermal performance. This development requires a reliable passive thermal management solution to mitigate hot spots due to the increased heat flux density. To this end, a 44 channel open looped pulsating heat pipe (OL-PHP) is experimentally investigated for two independent dielectric working fluids – Novec"T"M 649 and Novec"T"M 774 – due to their lower pressure operation and low global warming potential compared to traditional two-phase coolants. The OL-PHP is investigated in vertical (90°) orientation with fill ratios ranging from 0.30 to 0.70. The results highlight the steady state operating conditions for each working fluid with instantaneous plots of pressure, temperature, and thermal resistance; the minimum potential bulk thermal resistance for each fill ratio and the effective thermal conductivity achievable for the OL-PHP.

Digital Processor Module Reliability Analysis of Nuclear Power Plant

International Nuclear Information System (INIS)

Lee, Sang Yong; Jung, Jae Hyun; Kim, Jae Ho; Kim, Sung Hun

2005-01-01

The system used in plant, military equipment, satellite, etc. consists of many electronic parts as control module, which requires relatively high reliability than other commercial electronic products. Specially, Nuclear power plant related to the radiation safety requires high safety and reliability, so most parts apply to Military-Standard level. Reliability prediction method provides the rational basis of system designs and also provides the safety significance of system operations. Thus various reliability prediction tools have been developed in recent decades, among of them, the MI-HDBK-217 method has been widely used as a powerful tool for the prediction. In this work, It is explained that reliability analysis work for Digital Processor Module (DPM, control module of SMART) is performed by Parts Stress Method based on MIL-HDBK-217F NOTICE2. We are using the Relex 7.6 of Relex software corporation, because reliability analysis process requires enormous part libraries and data for failure rate calculation

Low voltage 80 KV to 125 KV electron processors

International Nuclear Information System (INIS)

Lauppi, U.V.

1999-01-01

The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

Modern Embedded Computing Designing Connected, Pervasive, Media-Rich Systems

CERN Document Server

Barry, Peter

2012-01-01

Modern embedded systems are used for connected, media-rich, and highly integrated handheld devices such as mobile phones, digital cameras, and MP3 players. All of these embedded systems require networking, graphic user interfaces, and integration with PCs, as opposed to traditional embedded processors that can perform only limited functions for industrial applications. While most books focus on these controllers, Modern Embedded Computing provides a thorough understanding of the platform architecture of modern embedded computing systems that drive mobile devices. The book offers a comprehen

A light hydrocarbon fuel processor producing high-purity hydrogen

Science.gov (United States)

Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

Embedded SoPC design with NIOS II processor and VHDL examples

CERN Document Server

Chu, Pong P

2011-01-01

The book is divided into four major parts. Part I covers HDL constructs and synthesis of basic digital circuits. Part II provides an overview of embedded software development with the emphasis on low-level I/O access and drivers. Part III demonstrates the design and development of hardware and software for several complex I/O peripherals, including PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card. Part IV provides three case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelb

High-speed BWR power plant simulations on the special-purpose peripheral processor AD10

International Nuclear Information System (INIS)

Wulff, W.; Cheng, H.S.; Lekach, S.V.; Mallen, A.N.

1985-01-01

A newly developed technique is described for fast, on-line simulations of normal and accidental transients in nuclear power plants. The technique is based on the utilization of the special-purpose peripheral processor AD10, which is specifically designed for high-speed systems simulations through integration of large systems of nonlinear ordinary differential equations. The Peach Bottom-II Boiling Water Reactor power plant has been simulated and results are presented. It is shown that the new technique not only advances safety analyses but also supports plant monitoring, failure diagnosis and accident mitigation, as well as the training of nuclear power plant operators. (author)

Static Schedulers for Embedded Real-Time Systems

Science.gov (United States)

1989-12-01

Because of the need for having efficient scheduling algorithms in large scale real time systems , software engineers put a lot of effort on developing...provide static schedulers for he Embedded Real Time Systems with single processor using Ada programming language. The independent nonpreemptable...support the Computer Aided Rapid Prototyping for Embedded Real Time Systems so that we determine whether the system, as designed, meets the required

Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

Science.gov (United States)

Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

2010-01-01

The Advanced Avionics and Processor Systems (AAPS) project, formerly known as the Radiation Hardened Electronics for Space Environments (RHESE) project, endeavors to develop advanced avionic and processor technologies anticipated to be used by NASA s currently evolving space exploration architectures. The AAPS project is a part of the Exploration Technology Development Program, which funds an entire suite of technologies that are aimed at enabling NASA s ability to explore beyond low earth orbit. NASA s Marshall Space Flight Center (MSFC) manages the AAPS project. AAPS uses a broad-scoped approach to developing avionic and processor systems. Investment areas include advanced electronic designs and technologies capable of providing environmental hardness, reconfigurable computing techniques, software tools for radiation effects assessment, and radiation environment modeling tools. Near-term emphasis within the multiple AAPS tasks focuses on developing prototype components using semiconductor processes and materials (such as Silicon-Germanium (SiGe)) to enhance a device s tolerance to radiation events and low temperature environments. As the SiGe technology will culminate in a delivered prototype this fiscal year, the project emphasis shifts its focus to developing low-power, high efficiency total processor hardening techniques. In addition to processor development, the project endeavors to demonstrate techniques applicable to reconfigurable computing and partially reconfigurable Field Programmable Gate Arrays (FPGAs). This capability enables avionic architectures the ability to develop FPGA-based, radiation tolerant processor boards that can serve in multiple physical locations throughout the spacecraft and perform multiple functions during the course of the mission. The individual tasks that comprise AAPS are diverse, yet united in the common endeavor to develop electronics capable of operating within the harsh environment of space. Specifically, the AAPS tasks for

Design and development of low-power driven hybrid electroluminescent lamp from carbon nanotube embedded phosphor material

International Nuclear Information System (INIS)

Yadav, Deepika; Mishra, Savvi; Shanker, Virendra; Haranath, D.

2013-01-01

Highlights: •We are first to report CNT embedded ZnS:Mn hybrid EL system. •Achieved efficient orange-red EL emission at low operating voltages ( AC ). •Facile technique to induce conductive paths inside the ZnS particle to trigger EL. •Detailed electrical characterization of EL lamp is presented. -- Abstract: We present a novel methodology to design a hybrid electroluminescent (EL) lamp by embedding carbon nanotubes (CNTs) inside the ZnS:Mn phosphor particles by conventional solid state diffusion technique. By doing so, the phosphor particles exhibited increase in EL brightness and efficiency at low operating voltages ( AC ). Interestingly, shorter the length of CNTs used, greater was the field enhancement effect and lower was the operating voltages to glow the EL lamps. The role of CNTs have been identified to form conductive paths inside the ZnS particle thereby triggering EL due to electron injection to luminescent centers (Mn 2+ ) at nominal voltages. In addition, a detailed electrical characterization of the novel EL lamp along with its spectral energy distribution studies are presented

Accuracy-Energy Configurable Sensor Processor and IoT Device for Long-Term Activity Monitoring in Rare-Event Sensing Applications

Directory of Open Access Journals (Sweden)

Daejin Park

2014-01-01

Full Text Available A specially designed sensor processor used as a main processor in IoT (internet-of-thing device for the rare-event sensing applications is proposed. The IoT device including the proposed sensor processor performs the event-driven sensor data processing based on an accuracy-energy configurable event-quantization in architectural level. The received sensor signal is converted into a sequence of atomic events, which is extracted by the signal-to-atomic-event generator (AEG. Using an event signal processing unit (EPU as an accelerator, the extracted atomic events are analyzed to build the final event. Instead of the sampled raw data transmission via internet, the proposed method delays the communication with a host system until a semantic pattern of the signal is identified as a final event. The proposed processor is implemented on a single chip, which is tightly coupled in bus connection level with a microcontroller using a 0.18 μm CMOS embedded-flash process. For experimental results, we evaluated the proposed sensor processor by using an IR- (infrared radio- based signal reflection and sensor signal acquisition system. We successfully demonstrated that the expected power consumption is in the range of 20% to 50% compared to the result of the basement in case of allowing 10% accuracy error.

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

CERN Document Server

Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

2015-01-01

The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

Java Dust: How Small Can Embedded Java Be?

DEFF Research Database (Denmark)

Caska, James; Schoeberl, Martin

2011-01-01

Java is slowly being accepted as a language and platform for embedded devices. However, the memory requirements of the Java library and runtime are still troublesome. A Java system is considered small when it requires less than 1 MB, and within the embedded domain small microcontollers with a few...... KB on-chip Flash memory and even less on-chip RAM are very common. For such small devices Java is a clearly challenging. In this paper we present the combination of the Java compiler Muvium for microcontrollers with the tiny soft-core Leros for an FPGA. To the best of our knowledge, the presented...... embedded Java system is the smallest Java system available. The Leros processor consumes less than 5% of the logic cells of the smallest FPGA from Altera and the Muvium compiler produces a JVM, including the Java application, that can execute in a few KB ROM and less than 1 KB RAM. The Leros processor...

Power generation from thermoelectric system-embedded Plexiglas for green building technology

KAUST Repository

Inayat, Salman Bin

2012-06-09

Thermoelectric materials embedded through or inside exterior glass windows can act as a viable source of supplemental power in geographic locations where hot weather dominates. This thermoelectricity is generated because of the thermal difference between the high temperature outside and the relatively cold temperature inside. Using physical vapor deposition process, we experimentally verify this concept by embedding bismuth telluride and antimony telluride through the 5 mm Plexiglas to demonstrate 10 nW of thermopower generation with a temperature gradient of 21 °C. Albeit tiny at this point with non-optimized design and development, this concept can be extended for relatively large-scale power generation as an additional power supply for green building technology.

Co-design for an SoC embedded network controller

Institute of Scientific and Technical Information of China (English)

无

2006-01-01

With the development of Ethernet systems and the growing capacity of modern silicon technology, embedded communication networks are playing an increasingly important role in embedded and safety critical systems. Hardware/software co-design is a methodology for solving design problems in processor based embedded systems. In this work, we implemented a new 1-cycle pipeline microprocessor and a fast Ethernet transceiver and established a low cost, high performance embedded network controller, and designed a TCP/IP stack to access the Internet. We discussed the hardware/software architecture in the forepart, and then the whole system-on-a-chip on Altera Stratix EP1S25F780C6 device. Using the FPGA environment and SmartBit tester, we tested the system's throughput. Our simulation results showed that the maximum throughput of Ethernet packets is up to 7 Mbps, that of UDP packets is up to 5.8 Mbps, and that of TCP packets is up to 3.4 Mbps, which showed that this embedded system can easily transmit basic voice and video signals through Ethernet, and that using only one chip can realize that many electronic devices access to the Internet directly and get high performance.

The optimization of H.264/AVC baseline decoder on low-cost TriMedia DSP processor

Science.gov (United States)

Wang, Sung-Wen; Yang, Ya-Ting; Li, Chia-Ying; Tung, Yi-Shin; Wu, Ja-Ling

2004-11-01

The emerging video coding standard, H.264/AVC, exhibits the unprecedented coding performance. Comparing to traditional coders, e.g., MPEG-2 and MEPG-4 ASP, about half bitrate saving is shown in the official verification test. Such outstanding performance makes it become the video compression candidate for the upcoming HD-DVD. As a side effect, it was also blamed that H.264/AVC is much more logically complex and requires more computation power than any of the existing standards. A low-cost and efficient implementation of the international standard hence plays an important role of its success. In this paper, we realize an H.264/AVC baseline decoder by a low-cost DSP processor, i.e., Philips" TriMedia TM-1300, and illustrate that less computation demand for H.264/AVC decoding becomes feasible by using effective software core. To this end, we first consider different approaches and take advantage of SIMD instruction set to optimize critical time-consuming coding modules, such as the fractional motion compensation, spatial prediction and inverse transform. Next, we also present some other optimization approaches for entropy decoding and in-loop deblocking filtering, even though they cannot get benefits from utilizing SIMD. In our experiments, by exploiting appropriate instruction level parallelism and efficient algorithms, the decoding speed can be improved by a factor of 8~10; a CIF video sequence can be decoded at up to 19.74~28.97 fps on a 166-MHz TriMedia TM-1300 processor compared to 2.40~2.98 fps by the standard reference software.

A configurable and low-power mixed signal SoC for portable ECG monitoring applications.

Science.gov (United States)

Kim, Hyejung; Kim, Sunyoung; Van Helleputte, Nick; Artes, Antonio; Konijnenburg, Mario; Huisken, Jos; Van Hoof, Chris; Yazicioglu, Refet Firat

2014-04-01

This paper describes a mixed-signal ECG System-on-Chip (SoC) that is capable of implementing configurable functionality with low-power consumption for portable ECG monitoring applications. A low-voltage and high performance analog front-end extracts 3-channel ECG signals and single channel electrode-tissue-impedance (ETI) measurement with high signal quality. This can be used to evaluate the quality of the ECG measurement and to filter motion artifacts. A custom digital signal processor consisting of 4-way SIMD processor provides the configurability and advanced functionality like motion artifact removal and R peak detection. A built-in 12-bit analog-to-digital converter (ADC) is capable of adaptive sampling achieving a compression ratio of up to 7, and loop buffer integration reduces the power consumption for on-chip memory access. The SoC is implemented in 0.18 μm CMOS process and consumes 32 μ W from a 1.2 V while heart beat detection application is running, and integrated in a wireless ECG monitoring system with Bluetooth protocol. Thanks to the ECG SoC, the overall system power consumption can be reduced significantly.

Power cycling test of a 650 V discrete GaN-on-Si power device with a laminated packaging embedding technology

DEFF Research Database (Denmark)

Song, Sungyoung; Munk-Nielsen, Stig; Uhrenfeldt, Christian

2017-01-01

A GaN-on-Si power device is a strong candidate to replace power components based on silicon in high-end market for low-voltage applications, thanks to its electrical characteristics. To maximize opportunities of the GaN device in field applications, a package technology plays an important role...... in a discrete GaN power device. A few specialized package technologies having very lower stray inductance and higher thermal conductivity have been proposed for discrete GaN-on-Si power devices. Despite their superior performance, there has been little discussion of their reliability. The paper presents a power...... cycling test of a discrete GaN power device employing a laminated embedded packaging technology subjected to 125 degrees Celsius junction temperature swing. Failure modes are described with collected electrical characteristics and measured temperature data under the test. In conclusion, physical...

Temperature measurement in low pressure plasmas. Temperaturmessungen im Niederdruckplasma

Energy Technology Data Exchange (ETDEWEB)

Rosenbauer, K.A.; Wilting, H.; Schramm, G. (Duesseldorf Univ. (Germany, F.R.). Abt. fuer Histologie und Embryologie)

1989-11-01

The present work discusses the influence of various parameters on the substrate temperature in a low pressure plasma. The measurement method chosen utilized Signotherm (Merck) temperature sensors embedded in silicon between two glass substrates. All measurements were made in a 200 G Plasma Processor from Technics Plasma GmbH. The substrate temperature is dependent on the process time, the RF power, the process gas and the position in the chamber. The substrate temperature increases with increasing process time and increasing power. Due to the location of the microwave port from the magnetron to the chamber, the substrate temperature is highest in the center of the chamber. Measurements performed in an air plasma yielded higher results than in an oxygen plasma. (orig.).

Real-time portable system for fabric defect detection using an ARM processor

Science.gov (United States)

Fernandez-Gallego, J. A.; Yañez-Puentes, J. P.; Ortiz-Jaramillo, B.; Alvarez, J.; Orjuela-Vargas, S. A.; Philips, W.

2012-06-01

Modern textile industry seeks to produce textiles as little defective as possible since the presence of defects can decrease the final price of products from 45% to 65%. Automated visual inspection (AVI) systems, based on image analysis, have become an important alternative for replacing traditional inspections methods that involve human tasks. An AVI system gives the advantage of repeatability when implemented within defined constrains, offering more objective and reliable results for particular tasks than human inspection. Costs of automated inspection systems development can be reduced using modular solutions with embedded systems, in which an important advantage is the low energy consumption. Among the possibilities for developing embedded systems, the ARM processor has been explored for acquisition, monitoring and simple signal processing tasks. In a recent approach we have explored the use of the ARM processor for defects detection by implementing the wavelet transform. However, the computation speed of the preprocessing was not yet sufficient for real time applications. In this approach we significantly improve the preprocessing speed of the algorithm, by optimizing matrix operations, such that it is adequate for a real time application. The system was tested for defect detection using different defect types. The paper is focused in giving a detailed description of the basis of the algorithm implementation, such that other algorithms may use of the ARM operations for fast implementations.

Development of a 30-cm ion thruster thermal-vacuum power processor

Science.gov (United States)

Herron, B. G.

1976-01-01

The 30-cm Hg electron-bombardment ion thruster presently under development has reached engineering model status and is generally accepted as the prime propulsion thruster module to be used on the earliest solar electric propulsion missions. This paper presents the results of a related program to develop a transistorized 3-kW Thermal-Vacuum Breadboard (TVBB) Power Processor for this thruster. Emphasized in the paper are the implemented electrical and mechanical designs as well as the resultant system performance achieved over a range of test conditions. In addition, design modifications affording improved performance are identified and discussed.

Certifiable Java for Embedded Systems

DEFF Research Database (Denmark)

Schoeberl, Martin; Dalsgaard, Andreas Engelbredt; Hansen, Rene Rydhof

2014-01-01

The Certifiable Java for Embedded Systems (CJ4ES) project aimed to develop a prototype development environment and platform for safety-critical software for embedded applications. There are three core constituents: A profile of the Java programming language that is tailored for safety......-critical applications, a predictable Java processor built with FPGA technology, and an Eclipse based application development environment that binds the profile and the platform together and provides analyses that help to provide evidence that can be used as part of a safety case. This paper summarizes key contributions...

Embedded Systems for Smart Appliances and Energy Management

CERN Document Server

Neumann, Peter; Mahlknecht, Stefan

2013-01-01

This book provides a comprehensive introduction to embedded systems for smart appliances and energy management, bringing together for the first time a multidisciplinary blend of topics from embedded systems, information technology and power engineering.  Coverage includes challenges for future resource distribution grids, energy management in smart appliances, micro energy generation, demand response management, ultra-low power stand by, smart standby and communication networks in home and building automation.   Provides a comprehensive, multidisciplinary introduction to embedded systems for smart appliances and energy management; Equips researchers and engineers with information required to succeed in designing energy management for smart appliances; Includes coverage of resource distribution grids, energy management in smart appliances, micro energy generation, demand response management, ultra-low power stand by, smart standby and communication networks in home and building automation.  

Making embedded systems design patterns for great software

CERN Document Server

White, Elecia

2011-01-01

Interested in developing embedded systems? Since they don't tolerate inefficiency, these systems require a disciplined approach to programming. This easy-to-read guide helps you cultivate a host of good development practices, based on classic software design patterns and new patterns unique to embedded programming. Learn how to build system architecture for processors, not operating systems, and discover specific techniques for dealing with hardware difficulties and manufacturing requirements. Written by an expert who's created embedded systems ranging from urban surveillance and DNA scanner

Design for the power-supply controller base on embedded operating system

International Nuclear Information System (INIS)

Guo Yuhui; Chinese Academy of Sciences, Beijing; Wang Yanyu; Qiao Weimin; Huang Jijiang; Lin Feiyu

2008-01-01

In order to realize the power-supply equipment long-distance monitor, adopts embedded RTOS (NutOS) and the TCP/1P protocol power-supply controller. Independently designs partially the software and hardware, through socket programming system long-distance control is realized. (authors)

Lawrence Livermore National Laboratory selects Intel Itanium 2 processors for world's most powerful Linux cluster

CERN Multimedia

2003-01-01

"Intel Corporation, system manufacturer California Digital and the University of California at Lawrence Livermore National Laboratory (LLNL) today announced they are building one of the world's most powerful supercomputers. The supercomputer project, codenamed "Thunder," uses nearly 4,000 Intel® Itanium® 2 processors... is expected to be complete in January 2004" (1 page).

Design and Implementation of an Embedded NIOS II System for JPEG2000 Tier II Encoding

Directory of Open Access Journals (Sweden)

John M. McNichols

2013-01-01

Full Text Available This paper presents a novel implementation of the JPEG2000 standard as a system on a chip (SoC. While most of the research in this field centers on acceleration of the EBCOT Tier I encoder, this work focuses on an embedded solution for EBCOT Tier II. Specifically, this paper proposes using an embedded softcore processor to perform Tier II processing as the back end of an encoding pipeline. The Altera NIOS II processor is chosen for the implementation and is coupled with existing embedded processing modules to realize a fully embedded JPEG2000 encoder. The design is synthesized on a Stratix IV FPGA and is shown to out perform other comparable SoC implementations by 39% in computation time.

Development of Ultra-Low Power Metal Oxide Sensors and Arrays for Embedded Applications

Science.gov (United States)

Lutz, Brent; Wind, Rikard; Kostelecky, Clayton; Routkevitch, Dmitri; Deininger, Debra

2011-09-01

Metal oxide semiconductor sensors are widely used as individual sensors and in arrays, and a variety of designs for low power microhotplates have been demonstrated.1 Synkera Technologies has developed an embeddable chemical microsensor platform, based on a unique ceramic MEMS technology, for practical implementation in cell phones and other mobile electronic devices. Key features of this microsensor platform are (1) small size, (2) ultra-low power consumption, (3) high chemical sensitivity, (4) accurate response to a wide-range of threats, and (5) low cost. The sensor platform is enabled by a combination of advances in ceramic micromachining, and precision deposition of sensing films inside the high aspect ratio pores of anodic aluminum oxide (AAO).

System-Level Design of a 64-Channel Low Power Neural Spike Recording Sensor.

Science.gov (United States)

Delgado-Restituto, Manuel; Rodriguez-Perez, Alberto; Darie, Angela; Soto-Sanchez, Cristina; Fernandez-Jover, Eduardo; Rodriguez-Vazquez, Angel

2017-04-01

This paper reports an integrated 64-channel neural spike recording sensor, together with all the circuitry to process and configure the channels, process the neural data, transmit via a wireless link the information and receive the required instructions. Neural signals are acquired, filtered, digitized and compressed in the channels. Additionally, each channel implements an auto-calibration algorithm which individually configures the transfer characteristics of the recording site. The system has two transmission modes; in one case the information captured by the channels is sent as uncompressed raw data; in the other, feature vectors extracted from the detected neural spikes are released. Data streams coming from the channels are serialized by the embedded digital processor. Experimental results, including in vivo measurements, show that the power consumption of the complete system is lower than 330 μW.

The TIGER trigger processor for the CAMERA detector at COMPASS-II

Energy Technology Data Exchange (ETDEWEB)

Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut der Universitaet Freiburg, Freiburg im Breisgau (Germany)

2013-07-01

In today's nuclear and high-energy physics experiments the background-induced occupancy of the detector channels can be quite high; therefore it is important to have sophisticated trigger subsystems which process the data in real-time to generate trigger objects for the global trigger decision. In this work we present a FPGA based low-latency trigger processor for the COMPASS-II experiment. TIGER is a high-performance trigger processor that was developed to fit perfectly in the GANDALF framework and extend its versatility. It is designed as a VXS module and is allocated to the central VXS switch slot, which has a direct link from every payload slot. The synchronous transfer protocol was optimized for low latencies and offers a bandwidth of up to 8 Gbit/s per link. The centerpiece of the board is a Xilinx Virtex-6 SX315T FPGA, offering vast programmable logic, embedded memory and DSP resources. It is accompanied by DDR3 memory, a COM Express CPU and a MXM GPU. Besides the VXS backplane ports, the board features two SFP+ transceivers, 32 LVDS inputs and 32 LVDS outputs to interface with the global trigger system and a Gigabit Ethernet port for configuration and monitoring.

NMR-MPar: A Fault-Tolerance Approach for Multi-Core and Many-Core Processors

Directory of Open Access Journals (Sweden)

Vanessa Vargas

2018-03-01

Full Text Available Multi-core and many-core processors are a promising solution to achieve high performance by maintaining a lower power consumption. However, the degree of miniaturization makes them more sensitive to soft-errors. To improve the system reliability, this work proposes a fault-tolerance approach based on redundancy and partitioning principles called N-Modular Redundancy and M-Partitions (NMR-MPar. By combining both principles, this approach allows multi-/many-core processors to perform critical functions in mixed-criticality systems. Benefiting from the capabilities of these devices, NMR-MPar creates different partitions that perform independent functions. For critical functions, it is proposed that N partitions with the same configuration participate of an N-modular redundancy system. In order to validate the approach, a case study is implemented on the KALRAY Multi-Purpose Processing Array (MPPA-256 many-core processor running two parallel benchmark applications. The traveling salesman problem and matrix multiplication applications were selected to test different device’s resources. The effectiveness of NMR-MPar is assessed by software-implemented fault-injection. For evaluation purposes, it is considered that the system is intended to be used in avionics. Results show the improvement of the application reliability by two orders of magnitude when implementing NMR-MPar on the system. Finally, this work opens the possibility to use massive parallelism for dependable applications in embedded systems.

OpenCL code generation for low energy wide SIMD architectures with explicit datapath.

NARCIS (Netherlands)

She, D.; He, Y.; Waeijen, L.J.W.; Corporaal, H.; Jeschke, H.; Silvén, O.

2013-01-01

Energy efficiency is one of the most important aspects in designing embedded processors. The use of a wide SIMD processor architecture is a promising approach to build energy-efficient high performance embedded processors. In this paper, we propose a configurable wide SIMD architecture that utilizes

Hybrid NEMS-CMOS Architectures for Ultra Low Power Smart Systems : Architectures for Ultra Low Power Smart Systems

NARCIS (Netherlands)

Enachescu, M.

2016-01-01

The availability of inexpensive and powerful processors provides the means for the computation ecosystem to change its fundamental paradigm towards the Internet of Things (IoT) where ubiquitous nanosystems add intelligence to every object that surrounds us. The new trend for most of those systems is

A 481pJ/decision 3.4M decision/s Multifunctional Deep In-memory Inference Processor using Standard 6T SRAM Array

OpenAIRE

Kang, Mingu; Gonugondla, Sujan; Patil, Ameya; Shanbhag, Naresh

2016-01-01

This paper describes a multi-functional deep in-memory processor for inference applications. Deep in-memory processing is achieved by embedding pitch-matched low-SNR analog processing into a standard 6T 16KB SRAM array in 65 nm CMOS. Four applications are demonstrated. The prototype achieves up to 5.6X (9.7X estimated for multi-bank scenario) energy savings with negligible (

Run Control Communication for the Upgrade of the ATLAS Muon-to-Central-Trigger-Processor Interface (MUCTPI)

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00223859; The ATLAS collaboration; Armbruster, Aaron James; Carrillo-Montoya, German D.; Chelstowska, Magda Anna; Czodrowski, Patrick; Deviveiros, Pier-Olivier; Eifert, Till; Ellis, Nicolas; Galster, Gorm Aske Gram Krohn; Haas, Stefan; Helary, Louis; Lagkas Nikolos, Orestis; Marzin, Antoine; Pauly, Thilo; Ryjov, Vladimir; Schmieden, Kristof; Silva Oliveira, Marcos Vinicius; Stelzer, Harald Joerg; Vichoudis, Paschalis; Wengler, Thorsten; Farthouat, Philippe

2018-01-01

The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used the SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the Yocto/OpenEmbedded framework. This approach was successfully...

Behavior-aware cache hierarchy optimization for low-power multi-core embedded systems

Science.gov (United States)

Zhao, Huatao; Luo, Xiao; Zhu, Chen; Watanabe, Takahiro; Zhu, Tianbo

2017-07-01

In modern embedded systems, the increasing number of cores requires efficient cache hierarchies to ensure data throughput, but such cache hierarchies are restricted by their tumid size and interference accesses which leads to both performance degradation and wasted energy. In this paper, we firstly propose a behavior-aware cache hierarchy (BACH) which can optimally allocate the multi-level cache resources to many cores and highly improved the efficiency of cache hierarchy, resulting in low energy consumption. The BACH takes full advantage of the explored application behaviors and runtime cache resource demands as the cache allocation bases, so that we can optimally configure the cache hierarchy to meet the runtime demand. The BACH was implemented on the GEM5 simulator. The experimental results show that energy consumption of a three-level cache hierarchy can be saved from 5.29% up to 27.94% compared with other key approaches while the performance of the multi-core system even has a slight improvement counting in hardware overhead.

Embedded Linux platform for data acquisition systems

International Nuclear Information System (INIS)

Patel, Jigneshkumar J.; Reddy, Nagaraj; Kumari, Praveena; Rajpal, Rachana; Pujara, Harshad; Jha, R.; Kalappurakkal, Praveen

2014-01-01

Highlights: • The design and the development of data acquisition system on FPGA based reconfigurable hardware platform. • Embedded Linux configuration and compilation for FPGA based systems. • Hardware logic IP core and its Linux device driver development for the external peripheral to interface it with the FPGA based system. - Abstract: This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx

Embedded Linux platform for data acquisition systems

Energy Technology Data Exchange (ETDEWEB)

Patel, Jigneshkumar J., E-mail: jjp@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Reddy, Nagaraj, E-mail: nagaraj.reddy@coreel.com [Sandeepani School of Embedded System Design, Bangalore, Karnataka (India); Kumari, Praveena, E-mail: praveena@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Rajpal, Rachana, E-mail: rachana@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Pujara, Harshad, E-mail: pujara@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Jha, R., E-mail: rjha@ipr.res.in [Institute for Plasma Research, Gandhinagar, Gujarat (India); Kalappurakkal, Praveen, E-mail: praveen.k@coreel.com [Sandeepani School of Embedded System Design, Bangalore, Karnataka (India)

2014-05-15

Highlights: • The design and the development of data acquisition system on FPGA based reconfigurable hardware platform. • Embedded Linux configuration and compilation for FPGA based systems. • Hardware logic IP core and its Linux device driver development for the external peripheral to interface it with the FPGA based system. - Abstract: This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx

Embedded palmprint recognition system using OMAP 3530.

Science.gov (United States)

Shen, Linlin; Wu, Shipei; Zheng, Songhao; Ji, Zhen

2012-01-01

We have proposed in this paper an embedded palmprint recognition system using the dual-core OMAP 3530 platform. An improved algorithm based on palm code was proposed first. In this method, a Gabor wavelet is first convolved with the palmprint image to produce a response image, where local binary patterns are then applied to code the relation among the magnitude of wavelet response at the central pixel with that of its neighbors. The method is fully tested using the public PolyU palmprint database. While palm code achieves only about 89% accuracy, over 96% accuracy is achieved by the proposed G-LBP approach. The proposed algorithm was then deployed to the DSP processor of OMAP 3530 and work together with the ARM processor for feature extraction. When complicated algorithms run on the DSP processor, the ARM processor can focus on image capture, user interface and peripheral control. Integrated with an image sensing module and central processing board, the designed device can achieve accurate and real time performance.

System Control Applications of Low-Power Radio Frequency Devices

Science.gov (United States)

van Rensburg, Roger

2017-09-01

This paper conceptualizes a low-power wireless sensor network design for application employment to reduce theft of portable computer devices used in educational institutions today. The aim of this study is to design and develop a reliable and robust wireless network that can eradicate accessibility of a device’s human interface. An embedded system supplied by an energy harvesting source, installed on the portable computer device, may represent one of multiple slave nodes which request regular updates from a standalone master station. A portable computer device which is operated in an undesignated area or in a field perimeter where master to slave communication is restricted, indicating a possible theft scenario, will initiate a shutdown of its operating system and render the device unusable. Consequently, an algorithm in the device firmware may ensure the necessary steps are executed to track the device, irrespective whether the device is enabled. Design outcomes thus far indicate that a wireless network using low-power embedded hardware, is feasible for anti-theft applications. By incorporating one of the latest Bluetooth low-energy, ANT+, ZigBee or Thread wireless technologies, an anti-theft system may be implemented that has the potential to reduce major portable computer device theft in institutions of digitized learning.

On-Road Driver Monitoring System Based on a Solar-Powered In-Vehicle Embedded Platform

Directory of Open Access Journals (Sweden)

Yen-Lin Chen

2014-01-01

Full Text Available This study presents an on-road driver monitoring system, which is implemented on a stand-alone in-vehicle embedded system and driven by effective solar cells. The driver monitoring function is performed by an efficient eye detection technique. Through the driver’s eye movements captured from the camera, the attention states of the driver can be determined and any fatigue states can be avoided. This driver monitoring technique is implemented on a low-power embedded in-vehicle platform. Besides, this study also proposed monitoring machinery that can detect the brightness around the car to effectively determine whether this in-vehicle system is driven by the solar cells or by the vehicle battery. On sunny days, the in-vehicle system can be powered by solar cell in places without the vehicle battery. While in the evenings or on rainy days, the ambient solar brightness is insufficient, and the system is powered by the vehicle battery. The proposed system was tested under the conditions that the solar irradiance is 10 to 113 W/m2 and solar energy and brightness at 10 to 170. From the testing results, when the outside solar radiation is high, the brightness of the inside of the car is increased, and the eye detection accuracy can also increase as well. Therefore, this solar powered driver monitoring system can be efficiently applied to electric cars to save energy consumption and promote the driving safety.

Mixed-signal early vision chip with embedded image and programming memories and digital I/O

Science.gov (United States)

Linan-Cembrano, Gustavo; Rodriguez-Vazquez, Angel; Dominguez-Castro, Rafael; Espejo, Servando

2003-04-01

From a system level perspective, this paper presents a 128x128 flexible and reconfigurable Focal-Plane Analog Programmable Array Processor, which has been designed as a single chip in a 0.35μm standard digital 1P-5M CMOS technology. The core processing array has been designed to achieve high-speed of operation and large-enough accuracy (~7bit) with low power consumption. The chip includes on-chip program memory to allow for the execution of complex, sequential and/or bifurcation flow image processing algorithms. It also includes the structures and circuits needed to guarantee its embedding into conventional digital hosting systems: external data interchange and control are completely digital. The chip contains close to four million transistors, 90% of them working in analog mode. The chip features up to 330GOPs (Giga Operations per second), and uses the power supply (180GOP/Joule) and the silicon area (3.8 GOPS/mm2) efficiently, as it is able to maintain VGA processing throughputs of 100Frames/s with about 15 basic image processing tasks on each frame.

Java Source Code Analysis for API Migration to Embedded Systems

Energy Technology Data Exchange (ETDEWEB)

Winter, Victor [Univ. of Nebraska, Omaha, NE (United States); McCoy, James A. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Guerrero, Jonathan [Univ. of Nebraska, Omaha, NE (United States); Reinke, Carl Werner [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Perry, James Thomas [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2015-02-01

Embedded systems form an integral part of our technological infrastructure and oftentimes play a complex and critical role within larger systems. From the perspective of reliability, security, and safety, strong arguments can be made favoring the use of Java over C in such systems. In part, this argument is based on the assumption that suitable subsets of Java’s APIs and extension libraries are available to embedded software developers. In practice, a number of Java-based embedded processors do not support the full features of the JVM. For such processors, source code migration is a mechanism by which key abstractions offered by APIs and extension libraries can made available to embedded software developers. The analysis required for Java source code-level library migration is based on the ability to correctly resolve element references to their corresponding element declarations. A key challenge in this setting is how to perform analysis for incomplete source-code bases (e.g., subsets of libraries) from which types and packages have been omitted. This article formalizes an approach that can be used to extend code bases targeted for migration in such a manner that the threats associated the analysis of incomplete code bases are eliminated.

Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

Energy Technology Data Exchange (ETDEWEB)

Nuvera Fuel Cells

2005-04-15

The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

Additively Manufactured IN718 Components with Wirelessly Powered and Interrogated Embedded Sensing

Energy Technology Data Exchange (ETDEWEB)

Attridge, Paul [United Technologies Research Center, East Hartford, CT (United States); Bajekal, Sanjay [United Technologies Research Center, East Hartford, CT (United States); Klecka, Michael [United Technologies Research Center, East Hartford, CT (United States); Wu, Xin [United Technologies Research Center, East Hartford, CT (United States); Savulak, Steve [United Technologies Research Center, East Hartford, CT (United States); Viens, Dan [United Technologies Research Center, East Hartford, CT (United States); Carey, Michael [United Technologies Research Center, East Hartford, CT (United States); Miano, John [United Technologies Research Center, East Hartford, CT (United States); Rioux, William [United Technologies Research Center, East Hartford, CT (United States); Zacchio, Joseph [United Technologies Research Center, East Hartford, CT (United States); Dunst, Richard [National Energy Technology Lab. (NETL), Pittsburgh, PA, (United States); Straub, Doug [National Energy Technology Lab. (NETL), Pittsburgh, PA, (United States); Mantese, Joseph [United Technologies Research Center, East Hartford, CT (United States)

2017-07-14

A methodology is described for embedding commercial-off-the-shelf sensors together with wireless communication and power circuit elements using direct laser metal sintered additively manufactured components. Physics based models of the additive manufacturing processes and sensor/wireless level performance models guided the design and embedment processes. A combination of cold spray deposition and laser engineered net shaping was used to fashion the transmitter/receiving elements and embed the sensors, thereby providing environmental protection and component robustness/survivability for harsh conditions. By design, this complement of analog and digital sensors were wirelessly powered and interrogated using a health and utilization monitoring system; enabling real-time, in situ prognostics and diagnostics.

Tinuso: A processor architecture for a multi-core hardware simulation platform

DEFF Research Database (Denmark)

Schleuniger, Pascal; Karlsson, Sven

2010-01-01

Multi-core systems have the potential to improve performance, energy and cost properties of embedded systems but also require new design methods and tools to take advantage of the new architectures. Due to the limited accuracy and performance of pure software simulators, we are working on a cycle...... accurate hardware simulation platform. We have developed the Tinuso processor architecture for this platform. Tinuso is a processor architecture optimized for FPGA implementation. The instruction set makes use of predicated instructions and supports C/C++ and assembly language programming. It is designed...... to be easy extendable to maintain the exibility required for the research on multi-core systems. Tinuso contains a co-processor interface to connect to a network interface. This interface allow for communication over an on-chip network. A clock frequency estimation study on a deeply pipelined Tinuso...

Commodity multi-processor systems in the ATLAS level-2 trigger

International Nuclear Information System (INIS)

Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

2000-01-01

Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

Commodity multi-processor systems in the ATLAS level-2 trigger

CERN Document Server

Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

2000-01-01

Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

Low Power Multi-Hop Networking Analysis in Intelligent Environments.

Science.gov (United States)

Etxaniz, Josu; Aranguren, Gerardo

2017-05-19

Intelligent systems are driven by the latest technological advances in many different areas such as sensing, embedded systems, wireless communications or context recognition. This paper focuses on some of those areas. Concretely, the paper deals with wireless communications issues in embedded systems. More precisely, the paper combines the multi-hop networking with Bluetooth technology and a quality of service (QoS) metric, the latency. Bluetooth is a radio license-free worldwide communication standard that makes low power multi-hop wireless networking available. It establishes piconets (point-to-point and point-to-multipoint links) and scatternets (multi-hop networks). As a result, many Bluetooth nodes can be interconnected to set up ambient intelligent networks. Then, this paper presents the results of the investigation on multi-hop latency with park and sniff Bluetooth low power modes conducted over the hardware test bench previously implemented. In addition, the empirical models to estimate the latency of multi-hop communications over Bluetooth Asynchronous Connectionless Links (ACL) in park and sniff mode are given. The designers of devices and networks for intelligent systems will benefit from the estimation of the latency in Bluetooth multi-hop communications that the models provide.

On the effective parallel programming of multi-core processors

NARCIS (Netherlands)

Varbanescu, A.L.

2010-01-01

Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

Safety-critical Java for low-end embedded platforms

DEFF Research Database (Denmark)

Søndergaard, Hans; Korsholm, Stephan E.; Ravn, Anders Peter

2012-01-01

We present an implementation of the Safety-Critical Java profile (SCJ), targeted for low-end embedded platforms with as little as 16 kB RAM and 256 kB flash. The distinctive features of the implementation are a combination of a lean Java virtual machine (HVM), with a bare metal kernel implementing...... hardware objects, first level interrupt handlers, and native variables, and an infrastructure written in Java which is minimized through program specialization. The HVM allows the implementation to be easily ported to embedded platforms which have a C compiler as part of the development environment...

High voltage generator circuit with low power and high efficiency applied in EEPROM

International Nuclear Information System (INIS)

Liu Yan; Zhang Shilin; Zhao Yiqiang

2012-01-01

This paper presents a low power and high efficiency high voltage generator circuit embedded in electrically erasable programmable read-only memory (EEPROM). The low power is minimized by a capacitance divider circuit and a regulator circuit using the controlling clock switch technique. The high efficiency is dependent on the zero threshold voltage (V th ) MOSFET and the charge transfer switch (CTS) charge pump. The proposed high voltage generator circuit has been implemented in a 0.35 μm EEPROM CMOS process. Measured results show that the proposed high voltage generator circuit has a low power consumption of about 150.48 μW and a higher pumping efficiency (83.3%) than previously reported circuits. This high voltage generator circuit can also be widely used in low-power flash devices due to its high efficiency and low power dissipation. (semiconductor integrated circuits)

STFTP: Secure TFTP Protocol for Embedded Multi-Agent Systems Communication

Directory of Open Access Journals (Sweden)

ZAGAR, D.

2013-05-01

Full Text Available Today's embedded systems have evolved into multipurpose devices moving towards an embedded multi-agent system (MAS infrastructure. With the involvement of MAS in embedded systems, one remaining issues is establishing communication between agents in low computational power and low memory embedded systems without present Embedded Operating System (EOS. One solution is the extension of an outdated Trivial File Transfer Protocol (TFTP. The main advantage of using TFTP in embedded systems is the easy implementation. However, the problem at hand is the overall lack of security mechanisms in TFTP. This paper proposes an extension to the existing TFTP in a form of added security mechanisms: STFTP. The authentication is proposed using Digest Access Authentication process whereas the data encryption can be performed by various cryptographic algorithms. The proposal is experimentally tested using two embedded systems based on micro-controller architecture. Communication is analyzed for authentication, data rate and transfer time versus various data encryption ciphers and files sizes. STFTP results in an expected drop in performance, which is in the range of similar encryption algorithms. The system could be improved by using embedded systems of higher computational power or by the use of hardware encryption modules.

A Power Efficient Exaflop Computer Design for Global Cloud System Resolving Climate Models.

Science.gov (United States)

Wehner, M. F.; Oliker, L.; Shalf, J.

2008-12-01

Exascale computers would allow routine ensemble modeling of the global climate system at the cloud system resolving scale. Power and cost requirements of traditional architecture systems are likely to delay such capability for many years. We present an alternative route to the exascale using embedded processor technology to design a system optimized for ultra high resolution climate modeling. These power efficient processors, used in consumer electronic devices such as mobile phones, portable music players, cameras, etc., can be tailored to the specific needs of scientific computing. We project that a system capable of integrating a kilometer scale climate model a thousand times faster than real time could be designed and built in a five year time scale for US$75M with a power consumption of 3MW. This is cheaper, more power efficient and sooner than any other existing technology.

Tools for Embedded Computing Systems Software

Science.gov (United States)

1978-01-01

A workshop was held to assess the state of tools for embedded systems software and to determine directions for tool development. A synopsis of the talk and the key figures of each workshop presentation, together with chairmen summaries, are presented. The presentations covered four major areas: (1) tools and the software environment (development and testing); (2) tools and software requirements, design, and specification; (3) tools and language processors; and (4) tools and verification and validation (analysis and testing). The utility and contribution of existing tools and research results for the development and testing of embedded computing systems software are described and assessed.

Self-powered information measuring wireless networks using the distribution of tasks within multicore processors

Science.gov (United States)

Zhuravska, Iryna M.; Koretska, Oleksandra O.; Musiyenko, Maksym P.; Surtel, Wojciech; Assembay, Azat; Kovalev, Vladimir; Tleshova, Akmaral

2017-08-01

The article contains basic approaches to develop the self-powered information measuring wireless networks (SPIM-WN) using the distribution of tasks within multicore processors critical applying based on the interaction of movable components - as in the direction of data transmission as wireless transfer of energy coming from polymetric sensors. Base mathematic model of scheduling tasks within multiprocessor systems was modernized to schedule and allocate tasks between cores of one-crystal computer (SoC) to increase energy efficiency SPIM-WN objects.

Design of an Elliptic Curve Cryptography processor for RFID tag chips.

Science.gov (United States)

Liu, Zilong; Liu, Dongsheng; Zou, Xuecheng; Lin, Hui; Cheng, Jian

2014-09-26

Radio Frequency Identification (RFID) is an important technique for wireless sensor networks and the Internet of Things. Recently, considerable research has been performed in the combination of public key cryptography and RFID. In this paper, an efficient architecture of Elliptic Curve Cryptography (ECC) Processor for RFID tag chip is presented. We adopt a new inversion algorithm which requires fewer registers to store variables than the traditional schemes. A new method for coordinate swapping is proposed, which can reduce the complexity of the controller and shorten the time of iterative calculation effectively. A modified circular shift register architecture is presented in this paper, which is an effective way to reduce the area of register files. Clock gating and asynchronous counter are exploited to reduce the power consumption. The simulation and synthesis results show that the time needed for one elliptic curve scalar point multiplication over GF(2163) is 176.7 K clock cycles and the gate area is 13.8 K with UMC 0.13 μm Complementary Metal Oxide Semiconductor (CMOS) technology. Moreover, the low power and low cost consumption make the Elliptic Curve Cryptography Processor (ECP) a prospective candidate for application in the RFID tag chip.

The Associative Memory Boards for the FTK Processor at ATLAS

CERN Document Server

Calabro, D; The ATLAS collaboration; Citraro, S; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

2013-01-01

The Associative Memory (AM) system, the main part of the FastTracker (FTK) processor, is designed to perform pattern matching using the information of the silicon tracking detectors. It finds track candidates at low resolution that are seeds for the following step performing precise track fitting. The system has to support challenging data traffic, handled by a group of modern low cost FPGAs, the Xilinx Spartan6 chips, which have Low-Power Gigabit Transceivers (GTP). Each GTP transceiver is a combined transmitter and receiver capable of operating at data rates up to 3.2 Gb/s. \

Quality-driven model-based design of multi-processor accelerators : an application to LDPC decoders

NARCIS (Netherlands)

Jan, Y.

2012-01-01

The recent spectacular progress in nano-electronic technology has enabled the implementation of very complex multi-processor systems on single chips (MPSoCs). However in parallel, new highly demanding complex embedded applications are emerging, in fields like communication and networking,

A basic design of microcontroller based data processor and local display for digital logarithmic power channel

International Nuclear Information System (INIS)

Nur Khasan; Syahrudin Yusuf

2009-01-01

A data processor and its local display for a digital logarithmic power channel, which will be used as a complement and diversification of nuclear reactor instrument, has been designed using micro controller base circuit. This power channel has been designed using TTL device and microcontroller. The roll of the microcontroller will be as data acquisition, data processing for the measurement of percentage reactor power, period and the trip decision. In this design has beer; created display of numerical value will be display on the local display in on-line mode for 1 nV to 10 10 nV neutron flux measurement range. This logarithmic power channel is expected to support the existing instrument which uses analog system in Instrumentation and Control System of nuclear reactor. (author)

Embedded Leverage

DEFF Research Database (Denmark)

Frazzini, Andrea; Heje Pedersen, Lasse

find that asset classes with embedded leverage offer low risk-adjusted returns and, in the cross-section, higher embedded leverage is associated with lower returns. A portfolio which is long low-embedded-leverage securities and short high-embedded-leverage securities earns large abnormal returns...

Performance of Distributed CFAR Processors in Pearson Distributed Clutter

OpenAIRE

Messali Zoubeida; Soltani Faouzi

2007-01-01

This paper deals with the distributed constant false alarm rate (CFAR) radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA), order statistics (OS), and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S) random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating ...

Embedded Hyperchaotic Generators: A Comparative Analysis

Science.gov (United States)

Sadoudi, Said; Tanougast, Camel; Azzaz, Mohamad Salah; Dandache, Abbas

In this paper, we present a comparative analysis of FPGA implementation performances, in terms of throughput and resources cost, of five well known autonomous continuous hyperchaotic systems. The goal of this analysis is to identify the embedded hyperchaotic generator which leads to designs with small logic area cost, satisfactory throughput rates, low power consumption and low latency required for embedded applications such as secure digital communications between embedded systems. To implement the four-dimensional (4D) chaotic systems, we use a new structural hardware architecture based on direct VHDL description of the forth order Runge-Kutta method (RK-4). The comparative analysis shows that the hyperchaotic Lorenz generator provides attractive performances compared to that of others. In fact, its hardware implementation requires only 2067 CLB-slices, 36 multipliers and no block RAMs, and achieves a throughput rate of 101.6 Mbps, at the output of the FPGA circuit, at a clock frequency of 25.315 MHz with a low latency time of 316 ns. Consequently, these good implementation performances offer to the embedded hyperchaotic Lorenz generator the advantage of being the best candidate for embedded communications applications.

Diaper-Embedded Urinary Tract Infection Monitoring Sensor Module Powered by Urine-Activated Batteries.

Science.gov (United States)

Seo, Weeseong; Yu, Wuyang; Tan, Tianlin; Ziaie, Babak; Jung, Byunghoo

2017-06-01

Urinary tract infection (UTI) is one of the most common infections in humans. UTI is easily treatable using antibiotics if identified in early stage. However, without early identification and treatment, UTI can be a major source of serious complications in geriatric patients, in particular, those suffering from neurodegenerative diseases. Also, for infants who have difficulty in describing their symptoms, UTI may lead to serious development of the disease making early identification of UTI crucial. In this paper, we present a diaper-embedded, wireless, self-powered, and autonomous UTI monitoring sensor module that allows an early detection of UTI with minimal effort. The sensor module consists of a paper-based colorimetric nitrite sensor, urine-activated batteries, a boost dc-dc converter, a low-power sensor interface utilizing pulse width modulation, and a Bluetooth low energy module for wireless transmission. Experimental results show a better detection of nitrite, a surrogate of UTI, than that of conventional dipstick testing. The proposed sensor module achieves a sensitivity of 1.35 ms/(mg/L) and a detection limit of 4 mg/L for nitrite.

Real time processor for array speckle interferometry

Science.gov (United States)

Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

1989-02-01

The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

Practical, redundant, failure-tolerant, self-reconfiguring embedded system architecture

Science.gov (United States)

Klarer, Paul R.; Hayward, David R.; Amai, Wendy A.

2006-10-03

This invention relates to system architectures, specifically failure-tolerant and self-reconfiguring embedded system architectures. The invention provides both a method and architecture for redundancy. There can be redundancy in both software and hardware for multiple levels of redundancy. The invention provides a self-reconfiguring architecture for activating redundant modules whenever other modules fail. The architecture comprises: a communication backbone connected to two or more processors and software modules running on each of the processors. Each software module runs on one processor and resides on one or more of the other processors to be available as a backup module in the event of failure. Each module and backup module reports its status over the communication backbone. If a primary module does not report, its backup module takes over its function. If the primary module becomes available again, the backup module returns to its backup status.

The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

International Nuclear Information System (INIS)

Maenner, R.; Deluigi, B.

1981-01-01

The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

ACP/R3000 processors in data acquisition systems

International Nuclear Information System (INIS)

Deppe, J.; Areti, H.; Atac, R.

1989-02-01

We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

Dynamic Voltage-Frequency and Workload Joint Scaling Power Management for Energy Harvesting Multi-Core WSN Node SoC

Directory of Open Access Journals (Sweden)

Xiangyu Li

2017-02-01

Full Text Available This paper proposes a scheduling and power management solution for energy harvesting heterogeneous multi-core WSN node SoC such that the system continues to operate perennially and uses the harvested energy efficiently. The solution consists of a heterogeneous multi-core system oriented task scheduling algorithm and a low-complexity dynamic workload scaling and configuration optimization algorithm suitable for light-weight platforms. Moreover, considering the power consumption of most WSN applications have the characteristic of data dependent behavior, we introduce branches handling mechanism into the solution as well. The experimental result shows that the proposed algorithm can operate in real-time on a lightweight embedded processor (MSP430, and that it can make a system do more valuable works and make more than 99.9% use of the power budget.

Numeric processor and text manipulator for the ''MASTER CONTROL'' data-base-management system

International Nuclear Information System (INIS)

Kuhn, R.W.

1976-01-01

The numeric and text processor of the MASTER CONTROL (MCP) data-base-management system permits the user to define fields and arrays that are functionally dependent on the data retained in a data base. This allows the storage of only the essential and unique information and data, and the calculation of derivable quantities as required. The derived quantity can be expressed as an arithmetic expression, that is, a functional relationship. Functions can be multiply subscripted and can be embedded within other functions at up to 58 levels. They can be stored either semi-permanently in a repertoire of functional relations, or they can be defined interactively from a terminal and used immediately for searching on the derived value. The processor also permits the conversion of literal strings into numbers, and vice versa. In addition, the user can define dictionaries that allow the expansion of keyed sentinels associated with records in the data base into fully descriptive expressions. This option can be used for cost-effective searching and data compaction. The functional definitions are reduced to Polish notation and stored in a disk file from which they are either retrieved on demand and evaluated according to the data of records specified or used in any given MASTER CONTROL command. The language used for the definitions of the numeric processor is essentially FORTRAN; most of the standard functions and over two dozen special functions are thus available. The functional processor provides a powerful technique for the integration of text and data for energy research and for scientific and technological work in general. MASTER CONTROL is operational at the Lawrence Livermore Laboratory (LLL) and at the Los Alamos Scientific Laboratory (LASL). 6 figures, 1 table

Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

Science.gov (United States)

Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

2009-01-30

Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

Development of ultrasonic testing technique to inspect containment liners embedded in concrete on nuclear power plants

Energy Technology Data Exchange (ETDEWEB)

Ishida, H.; Kurozumi, Y. [Inst. of Nuclear Safety System, Incorporated, Mihama, Fukui (Japan); Kaneshima, Y. [The Kansai Electric Power Company, Inc., Mihama, Fukui (Japan)

2004-07-01

The purpose of this study is development of ultrasonic testing technique to inspect containment liners embedded in concrete on nuclear power plants. Integrity of containment liners on nuclear power plants can be secured by suitable present operation and maintenance. Furthermore, non-destructive testing technique to inspect embedded liners will ensure the integrity of the containment further. In order to develop the non-destructive testing technique, ultrasonic transducers were made newly and ultrasonic testing data acquisition and evaluation were carried out by using a mock-up. We adopted the surface shear horizontal (SH) wave, low frequency (0.3-0.5MHz), to be able to detect an echo from a defect against attenuation of ultrasonic waves due to long propagation in the liners and dispersion into concrete. We made transducers with three large active elements (40mm x 40mm) in a line which were equivalent to a 120mm width active element. Artificial hollows, {phi}200mm - 19mm depth (1/2thickness) and {phi}200mm - 9.5mm depth (1/4thickness), were made on a surface of a mock-up: carbon steel plate, 38mm thickness, 2,000mm length, 1000mm width. The surfaces of the plate were covered with concrete in order to simulate liners embedded in concrete. As a result of the examinations, the surface SH transducers could detect clearly the echo from the hollows at a distance of 1500mm. We evaluate that the newly made surface SH transducers with three elements have ability of detection of defects such as corrosion on the liners embedded in concrete. (author)

Low-Energy Real-Time OS Using Voltage Scheduling Algorithm for Variable Voltage Processors

OpenAIRE

Okuma, Takanori; Yasuura, Hiroto

2001-01-01

This paper presents a real-time OS based on $ mu $ITRON using proposed voltage scheduling algorithm for variable voltage processors which can vary supply voltage dynamically. The proposed voltage scheduling algorithms assign voltage level for each task dynamically in order to minimize energy consumption under timing constraints. Using the presented real-time OS, running tasks with low supply voltage leads to drastic energy reduction. In addition, the presented voltage scheduling algorithm is ...

A heterogeneous multi-core platform for low power signal processing in systems-on-chip

DEFF Research Database (Denmark)

Paker, Ozgun; Sparsø, Jens; Haandbæk, Niels

2002-01-01

is based on message passing. The mini-cores are designed as parameterized soft macros intended for a synthesis based design flow. A 520.000 transistor 0.25µm CMOS prototype chip containing 6 mini-cores has been fabricated and tested. Its power consumption is only 50% higher than a hardwired ASIC and more......This paper presents a low-power and programmable DSP architecture - a heterogeneous multiprocessor platform consisting of standard CPU/DSP cores, and a set of simple instruction set processors called mini-cores each optimized for a particular class of algorithm (FIR, IIR, LMS, etc.). Communication...

Development of level 2 processor for the readout of TMC

International Nuclear Information System (INIS)

Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

1995-01-01

We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

Compact lidar system using laser diode, binary continuous wave power modulation, and an avalanche photodiode-based receiver controlled by a digital signal processor

Science.gov (United States)

Ardanuy, Antoni; Comerón, Adolfo

2018-04-01

We analyze the practical limits of a lidar system based on the use of a laser diode, random binary continuous wave power modulation, and an avalanche photodiode (APD)-based photereceiver, combined with the control and computing power of the digital signal processors (DSP) currently available. The target is to design a compact portable lidar system made all in semiconductor technology, with a low-power demand and an easy configuration of the system, allowing change in some of its features through software. Unlike many prior works, we emphasize the use of APDs instead of photomultiplier tubes to detect the return signal and the application of the system to measure not only hard targets, but also medium-range aerosols and clouds. We have developed an experimental prototype to evaluate the behavior of the system under different environmental conditions. Experimental results provided by the prototype are presented and discussed.

Embedded and real-time operating systems

CERN Document Server

Wang, K C

2017-01-01

This book covers the basic concepts and principles of operating systems, showing how to apply them to the design and implementation of complete operating systems for embedded and real-time systems. It includes all the foundational and background information on ARM architecture, ARM instructions and programming, toolchain for developing programs, virtual machines for software implementation and testing, program execution image, function call conventions, run-time stack usage and link C programs with assembly code. It describes the design and implementation of a complete OS for embedded systems in incremental steps, explaining the design principles and implementation techniques. For Symmetric Multiprocessing (SMP) embedded systems, the author examines the ARM MPcore processors, which include the SCU and GIC for interrupts routing and interprocessor communication and synchronization by Software Generated Interrupts (SGIs). Throughout the book, complete working sample systems demonstrate the design principles and...

Design of Networks-on-Chip for Real-Time Multi-Processor Systems-on-Chip

DEFF Research Database (Denmark)

Sparsø, Jens

2012-01-01

This paper addresses the design of networks-on-chips for use in multi-processor systems-on-chips - the hardware platforms used in embedded systems. These platforms typically have to guarantee real-time properties, and as the network is a shared resource, it has to provide service guarantees...... (bandwidth and/or latency) to different communication flows. The paper reviews some past work in this field and the lessons learned, and the paper discusses ongoing research conducted as part of the project "Time-predictable Multi-Core Architecture for Embedded Systems" (T-CREST), supported by the European...

Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

Science.gov (United States)

Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

2003-04-01

This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

Embedded Hardware

CERN Document Server

Ganssle, Jack G; Eady, Fred; Edwards, Lewin; Katz, David J; Gentile, Rick

2007-01-01

The Newnes Know It All Series takes the best of what our authors have written to create hard-working desk references that will be an engineer's first port of call for key information, design techniques and rules of thumb. Guaranteed not to gather dust on a shelf!. Circuit design using microcontrollers is both a science and an art. This book covers it all. It details all of the essential theory and facts to help an engineer design a robust embedded system. Processors, memory, and the hot topic of interconnects (I/O) are completely covered. Our authors bring a wealth of experience and ideas; thi

Performance of Distributed CFAR Processors in Pearson Distributed Clutter

Directory of Open Access Journals (Sweden)

Messali Zoubeida

2007-01-01

Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the "OR" fusion rule.

Performance of Distributed CFAR Processors in Pearson Distributed Clutter

Directory of Open Access Journals (Sweden)

Faouzi Soltani

2007-01-01

Full Text Available This paper deals with the distributed constant false alarm rate (CFAR radar detection of targets embedded in heavy-tailed Pearson distributed clutter. In particular, we extend the results obtained for the cell averaging (CA, order statistics (OS, and censored mean level CMLD CFAR processors operating in positive alpha-stable (P&S random variables to more general situations, specifically to the presence of interfering targets and distributed CFAR detectors. The receiver operating characteristics of the greatest of (GO and the smallest of (SO CFAR processors are also determined. The performance characteristics of distributed systems are presented and compared in both homogeneous and in presence of interfering targets. We demonstrate, via simulation results, that the distributed systems when the clutter is modelled as positive alpha-stable distribution offer robustness properties against multiple target situations especially when using the “OR” fusion rule.

GR712RC- Dual-Core Processor- Product Status

Science.gov (United States)

Sturesson, Fredrik; Habinc, Sandi; Gaisler, Jiri

2012-08-01

The GR712RC System-on-Chip (SoC) is a dual core LEON3FT system suitable for advanced high reliability space avionics. Fault tolerance features from Aeroflex Gaisler’s GRLIB IP library and an implementation using Ramon Chips RadSafe cell library enables superior radiation hardness.The GR712RC device has been designed to provide high processing power by including two LEON3FT 32- bit SPARC V8 processors, each with its own high- performance IEEE754 compliant floating-point-unit and SPARC reference memory management unit.This high processing power is combined with a large number of serial interfaces, ranging from high-speed links for data transfers to low-speed control buses for commanding and status acquisition.

Power harvesting using PZT ceramics embedded in orthopedic implants.

Science.gov (United States)

Chen, Hong; Liu, Ming; Jia, Chen; Wang, Zihua

2009-09-01

Battery lifetime has been the stumbling block for many power-critical or maintenance-free real-time embedded applications, such as wireless sensors and orthopedic implants. Thus a piezoelectric material that could convert human motion into electrical energy provides a very attractive solution for clinical implants. In this work, we analyze the power generation characteristics of stiff lead zirconate titanate (PZT) ceramics and the equivalent circuit through extensive experiments. Our experimental framework allows us to explore many important design considerations of such a PZT-based power generator. Overall we can achieve a PZT element volume of 0.5 x 0.5 x 1.8 cm, which is considerably smaller than the results reported so far. Finally, we outline the application of our PZT elements in a total knee replacement (TKR) implant.

Real-Time Operating Systems for Multicore Embedded Systems

OpenAIRE

Tomiyama, Hiroyuki; Honda, Shinya; Takada, Hiroaki

2008-01-01

Multicore systems-on-chip have become popular inthe design of embedded systems in order to simultaneously achieve high performance and low power consumption. On the software side, real-time operating systems are necessary in orderto handle growing complexity of embedded software. This paper describes requirements, design principles and implementation techniques for real-time operating systems to be used inasymmetric multicore systems.

Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

Directory of Open Access Journals (Sweden)

Xie Yiwei

2017-12-01

Full Text Available Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

Run-time Adaptable VLIW Processors : Resources, Performance, Power Consumption, and Reliability Trade-offs

NARCIS (Netherlands)

Anjam, F.

2013-01-01

In this dissertation, we propose to combine programmability with reconfigurability by implementing an adaptable programmable VLIW processor in a reconfigurable hardware. The approach allows applications to be developed at high-level (C language level), while at the same time, the processor

Research on numerical control system based on S3C2410 and MCX314AL

Science.gov (United States)

Ren, Qiang; Jiang, Tingbiao

2008-10-01

With the rapid development of micro-computer technology, embedded system, CNC technology and integrated circuits, numerical control system with powerful functions can be realized by several high-speed CPU chips and RISC (Reduced Instruction Set Computing) chips which have small size and strong stability. In addition, the real-time operating system also makes the attainment of embedded system possible. Developing the NC system based on embedded technology can overcome some shortcomings of common PC-based CNC system, such as the waste of resources, low control precision, low frequency and low integration. This paper discusses a hardware platform of ENC (Embedded Numerical Control) system based on embedded processor chip ARM (Advanced RISC Machines)-S3C2410 and DSP (Digital Signal Processor)-MCX314AL and introduces the process of developing ENC system software. Finally write the MCX314AL's driver under the embedded Linux operating system. The embedded Linux operating system can deal with multitask well moreover satisfy the real-time and reliability of movement control. NC system has the advantages of best using resources and compact system with embedded technology. It provides a wealth of functions and superior performance with a lower cost. It can be sure that ENC is the direction of the future development.

Fault tolerant embedded computers and power electronics for nuclear robotics

International Nuclear Information System (INIS)

Giraud, A.; Robiolle, M.

1995-01-01

For requirements of nuclear industries, it is necessary to use embedded rad-tolerant electronics and high-level safety. In this paper, we first describe a computer architecture called MICADO designed for French nuclear industry. We then present outgoing projects on our industry. A special point is made on power electronics for remote-operated and legged robots. (authors). 7 refs., 2 figs

Fault tolerant embedded computers and power electronics for nuclear robotics

Energy Technology Data Exchange (ETDEWEB)

Giraud, A.; Robiolle, M.

1995-12-31

For requirements of nuclear industries, it is necessary to use embedded rad-tolerant electronics and high-level safety. In this paper, we first describe a computer architecture called MICADO designed for French nuclear industry. We then present outgoing projects on our industry. A special point is made on power electronics for remote-operated and legged robots. (authors). 7 refs., 2 figs.

A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors

Directory of Open Access Journals (Sweden)

Ricardo Acevedo-Avila

2016-05-01

Full Text Available Blob detection is a common task in vision-based applications. Most existing algorithms are aimed at execution on general purpose computers; while very few can be adapted to the computing restrictions present in embedded platforms. This paper focuses on the design of an algorithm capable of real-time blob detection that minimizes system memory consumption. The proposed algorithm detects objects in one image scan; it is based on a linked-list data structure tree used to label blobs depending on their shape and node information. An example application showing the results of a blob detection co-processor has been built on a low-powered field programmable gate array hardware as a step towards developing a smart video surveillance system. The detection method is intended for general purpose application. As such, several test cases focused on character recognition are also examined. The results obtained present a fair trade-off between accuracy and memory requirements; and prove the validity of the proposed approach for real-time implementation on resource-constrained computing platforms.

A Linked List-Based Algorithm for Blob Detection on Embedded Vision-Based Sensors.

Science.gov (United States)

Acevedo-Avila, Ricardo; Gonzalez-Mendoza, Miguel; Garcia-Garcia, Andres

2016-05-28

Blob detection is a common task in vision-based applications. Most existing algorithms are aimed at execution on general purpose computers; while very few can be adapted to the computing restrictions present in embedded platforms. This paper focuses on the design of an algorithm capable of real-time blob detection that minimizes system memory consumption. The proposed algorithm detects objects in one image scan; it is based on a linked-list data structure tree used to label blobs depending on their shape and node information. An example application showing the results of a blob detection co-processor has been built on a low-powered field programmable gate array hardware as a step towards developing a smart video surveillance system. The detection method is intended for general purpose application. As such, several test cases focused on character recognition are also examined. The results obtained present a fair trade-off between accuracy and memory requirements; and prove the validity of the proposed approach for real-time implementation on resource-constrained computing platforms.

Low power signal processing research at Stanford

Science.gov (United States)

Burr, J.; Williamson, P. R.; Peterson, A.

1991-01-01

This paper gives an overview of the research being conducted at Stanford University's Space, Telecommunications, and Radioscience Laboratory in the area of low energy computation. It discusses the work we are doing in large scale digital VLSI neural networks, interleaved processor and pipelined memory architectures, energy estimation and optimization, multichip module packaging, and low voltage digital logic.

Introduction to Embedded Systems Using ANSI C and the Arduino Development Environment

CERN Document Server

Russell, David

2010-01-01

Many electrical and computer engineering projects involve some kind of embedded system in which a microcontroller sits at the center as the primary source of control. The recently-developed Arduino development platform includes an inexpensive hardware development board hosting an eight-bit ATMEL ATmega-family processor and a Java-based software-development environment. These features allow an embedded systems beginner the ability to focus their attention on learning how to write embedded software instead of wasting time overcoming the engineering CAD tools learning curve. The goal of this text

Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors

OpenAIRE

Catalán, Sandra; Igual, Francisco D.; Mayo, Rafael; Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

2015-01-01

Asymmetric multicore processors (AMPs) have recently emerged as an appealing technology for severely energy-constrained environments, especially in mobile appliances where heterogeneity in applications is mainstream. In addition, given the growing interest for low-power high performance computing, this type of architectures is also being investigated as a means to improve the throughput-per-Watt of complex scientific applications. In this paper, we design and embed several architecture-aware ...

BWR thermohydraulics simulation on the AD-10 peripheral processor

International Nuclear Information System (INIS)

Wulff, W.; Cheng, H.S.; Lekach, S.V.; Mallen, A.N.

1983-01-01

This presentation demonstrates the feasibility of simulating plant transients and severe abnormal transients in nuclear power plants at much faster than real-time computing speeds in a low-cost, dedicated, interactive minicomputer. This is achieved by implementing advanced modeling techniques in modern, special-purpose peripheral processors for high-speed system simulation. The results of this demonstration will impact safety analyses and parametric studies, studies on operator responses and control system failures and it will make possible the continuous on-line monitoring of plant performance and the detection and diagnosis of system or component failures

Drag Measurements over Embedded Cavities in a Low Reynolds Number Couette Flow

Science.gov (United States)

Gilmer, Caleb; Lang, Amy; Jones, Robert

2010-11-01

Recent research has revealed that thin-walled, embedded cavities in low Reynolds number flow have the potential to reduce the net viscous drag force acting on the surface. This reduction is due to the formation of embedded vortices allowing the outer flow to pass over the surface via a roller bearing effect. It is also hypothesized that the scales found on butterfly wings may act in a similar manner to cause a net increase in flying efficiency. In this experimental study, rectangular embedded cavities were designed as a means of successfully reducing the net drag across surfaces in a low Reynolds number flow. A Couette flow was generated via a rotating conveyor belt immersed in a tank of high viscosity mineral oil above which the plates with embedded cavities were placed. Drag induced on the plate models was measured using a force gauge and compared directly to measurements acquired over a flat plate. Various cavity aspect ratios and gap heights were tested in order to determine the conditions under which the greatest drag reductions occurred.

Ultra-Low Power Optical Transistor Using a Single Quantum Dot Embedded in a Photonic Wire

DEFF Research Database (Denmark)

Nguyen, H.A.; Grange, T.; Malik, N.S.

2017-01-01

Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons.......Using a single InAs quantum dot embedded in a GaAs photonic wire, we realize a giant non-linearity between two optical modes to experimentally demonstrate an all-optical transistor triggered by 10 photons....

Efficient and Secure Fingerprint Verification for Embedded Devices

Directory of Open Access Journals (Sweden)

Sakiyama Kazuo

2006-01-01

Full Text Available This paper describes a secure and memory-efficient embedded fingerprint verification system. It shows how a fingerprint verification module originally developed to run on a workstation can be transformed and optimized in a systematic way to run real-time on an embedded device with limited memory and computation power. A complete fingerprint recognition module is a complex application that requires in the order of 1000 M unoptimized floating-point instruction cycles. The goal is to run both the minutiae extraction and the matching engines on a small embedded processor, in our case a 50 MHz LEON-2 softcore. It does require optimization and acceleration techniques at each design step. In order to speed up the fingerprint signal processing phase, we propose acceleration techniques at the algorithm level, at the software level to reduce the execution cycle number, and at the hardware level to distribute the system work load. Thirdly, a memory trace map-based memory reduction strategy is used for lowering the system memory requirement. Lastly, at the hardware level, it requires the development of specialized coprocessors. As results of these optimizations, we achieve a 65% reduction on the execution time and a 67% reduction on the memory storage requirement for the minutiae extraction process, compared against the reference implementation. The complete operation, that is, fingerprint capture, feature extraction, and matching, can be done in real-time of less than 4 seconds

Toward an Ultralow-Power Onboard Processor for Tongue Drive System.

Science.gov (United States)

Viseh, Sina; Ghovanloo, Maysam; Mohsenin, Tinoosh

2015-02-01

The Tongue Drive System (TDS) is a new unobtrusive, wireless, and wearable assistive device that allows for real-time tracking of the voluntary tongue motion in the oral space for communication, control, and navigation applications. The latest TDS prototype appears as a wireless headphone and has been tested in human subject trials. However, the robustness of the external TDS (eTDS) in real-life outdoor conditions may not meet safety regulations because of the limited mechanical stability of the headset. The intraoral TDS (iTDS), which is in the shape of a dental retainer, firmly clasps to the upper teeth and resists sensor misplacement. However, the iTDS has more restrictions on its dimensions, limiting the battery size and consequently requiring a considerable reduction in its power consumption to operate over an extended period of two days on a single charge. In this brief, we propose an ultralow-power local processor for the TDS that performs all signal processing on the transmitter side, following the sensors. Assuming the TDS user on average issuing one command/s, implementing the computational engine reduces the data volume that needs to be wirelessly transmitted to a PC or smartphone by a factor of 1500×, from 12 kb/s to ~8 b/s. The proposed design is implemented on an ultralow-power IGLOO nano field-programmable gate array (FPGA) and is tested on AGLN250 prototype board. According to our post-place-and-route results, implementing the engine on the FPGA significantly drops the required data transmission, while an application-specific integrated circuit (ASIC) implementation in a 65-nm CMOS results in a 15× power saving compared to the FPGA solution and occupies a 0.02-mm 2 footprint. As a result, the power consumption and size of the iTDS will be significantly reduced through the use of a much smaller rechargeable battery. Moreover, the system can operate longer following every recharge, improving the iTDS usability.

Hardware trigger processor for the MDT system

CERN Document Server

AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

2017-01-01

We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

Embedded multiprocessors scheduling and synchronization

CERN Document Server

Sriram, Sundararajan

2009-01-01

Techniques for Optimizing Multiprocessor Implementations of Signal Processing ApplicationsAn indispensable component of the information age, signal processing is embedded in a variety of consumer devices, including cell phones and digital television, as well as in communication infrastructure, such as media servers and cellular base stations. Multiple programmable processors, along with custom hardware running in parallel, are needed to achieve the computation throughput required of such applications. Reviews important research in key areas related to the multiprocessor implementation of multi

Study of low insertion loss and miniaturization wavelet transform and inverse transform processor using SAW devices.

Science.gov (United States)

Jiang, Hua; Lu, Wenke; Zhang, Guoan

2013-07-01

In this paper, we propose a low insertion loss and miniaturization wavelet transform and inverse transform processor using surface acoustic wave (SAW) devices. The new SAW wavelet transform devices (WTDs) use the structure with two electrode-widths-controlled (EWC) single phase unidirectional transducers (SPUDT-SPUDT). This structure consists of the input withdrawal weighting interdigital transducer (IDT) and the output overlap weighting IDT. Three experimental devices for different scales 2(-1), 2(-2), and 2(-3) are designed and measured. The minimum insertion loss of the three devices reaches 5.49dB, 4.81dB, and 5.38dB respectively which are lower than the early results. Both the electrode width and the number of electrode pairs are reduced, thus making the three devices much smaller than the early devices. Therefore, the method described in this paper is suitable for implementing an arbitrary multi-scale low insertion loss and miniaturization wavelet transform and inverse transform processor using SAW devices. Copyright © 2013 Elsevier B.V. All rights reserved.

Real time processor for array speckle interferometry

International Nuclear Information System (INIS)

Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

1989-01-01

With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

Java Processor Optimized for RTSJ

Directory of Open Access Journals (Sweden)

Tu Shiliang

2007-01-01

Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

The Inertial Stellar Compass (ISC): A Multifunction, Low Power, Attitude Determination Technology Breakthrough

Science.gov (United States)

Bauer, Frank H. (Technical Monitor); Dennehy, Neil; Gambino, Joel; Maynard, Andrew; Brady, T.; Buckley, S.; Zinchuk, J.

2003-01-01

The Inertial Stellar Compass (ISC) is a miniature, low power, stellar inertial attitude determination system with an accuracy of better than 0.1 degree (1 sigma) in three axes. The ISC consumes only 3.5 Watts of power and is contained in a 2.5 kg package. With its embedded on-board processor, the ISC provides attitude quaternion information and has Lost-in-Space (LIS) initialization capability. The attitude accuracy and LIS capability are provided by combining a wide field of view Active Pixel Sensor (APS) star camera and Micro- ElectroMechanical System (MEMS) inertial sensor information in an integrated sensor system. The performance and small form factor make the ISC a useful sensor for a wide range of missions. In particular, the ISC represents an enabling, fully integrated, micro-satellite attitude determination system. Other applications include using the ISC as a single sensor solution for attitude determination on medium performance spacecraft and as a bolt on independent safe-hold sensor or coarse acquisition sensor for many other spacecraft. NASA's New Millennium Program (NMP) has selected the ISC technology for a Space Technology 6 (ST6) flight validation experiment scheduled for 2004. NMP missions, such a s ST6, are intended to validate advanced technologies that have not flown in space in order to reduce the risk associated with their infusion into future NASA missions. This paper describes the design, operation, and performance of the ISC and outlines the technology validation plan. A number of mission applications for the ISC technology are highlighted, both for the baseline ST6 ISC configuration and more ambitious applications where ISC hardware and software modifications would be required. These applications demonstrate the wide range of Space and Earth Science missions that would benefit from infusion of the ISC technology.

Computing trends using graphic processor in high energy physics

CERN Document Server

Niculescu, Mihai

2011-01-01

One of the main challenges in Heavy Energy Physics is to make fast analysis of high amount of experimental and simulated data. At LHC-CERN one p-p event is approximate 1 Mb in size. The time taken to analyze the data and obtain fast results depends on high computational power. The main advantage of using GPU(Graphic Processor Unit) programming over traditional CPU one is that graphical cards bring a lot of computing power at a very low price. Today a huge number of application(scientific, financial etc) began to be ported or developed for GPU, including Monte Carlo tools or data analysis tools for High Energy Physics. In this paper, we'll present current status and trends in HEP using GPU.

Compact gasoline fuel processor for passenger vehicle APU

Science.gov (United States)

Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

Checkpointing for graceful degradation in distributed embedded systems

Science.gov (United States)

Sababha, Belal Hussein

Graceful degradation is an approach to developing dependable safety-critical embedded applications, where redundant active or standby resources are used to cope with faults through a system reconfiguration at run-time. Compared to traditional hardware and software redundancy, it is a promising technique that may achieve dependability with a significant reduction in cost, size, weight, and power requirements. Reconfiguration at run-time necessitates using proper checkpointing protocols to support state reservation to ensure correct task restarts after a system reconfiguration. One of the most common checkpointing protocols are communication induced checkpointing (CIC) protocols, which are well developed and understood for large parallel and information systems, but not much has been done for resource limited embedded systems. This work implements and evaluates some of the most common CIC protocols in a periodic resource constrained distributed embedded system for graceful degradation purposes. A test-bed has been developed and used for the evaluation of the various protocols. The implemented protocols are thoroughly studied and performances are contrasted. Specifically the periodicity property and how it benefits checkpointing in embedded systems is investigated. This work introduces a unique effort of CIC protocol implementation and evaluation in the field of distributed embedded systems. Other than providing a test-bed for graceful degradation support, this work shows that some checkpointing protocols that are not efficient in large information systems and supercomputers perform well in embedded systems. We show that a simple index-based CIC protocol, such as the BCS protocol, is more appropriate in embedded system applications compared to other protocols that piggyback a significant amount of information to reduce the number of forced checkpoints. Finally, this work proposes a whole graceful degradation approach to achieve fault tolerance in resource constrained

Composable local memory organisation for streaming applications on embedded MPSoCs

NARCIS (Netherlands)

Ambrose, J.; Molnos, A.; Nelson, A.; Cotofana, S.; Goossens, K.G.W.; Juurlink, B.

2011-01-01

Multi-Processor Systems on a Chip (MPSoCs) are suitable platforms for the implementation of complex embedded applications. An MPSoC is composable if the functional and temporal behaviour of each application is independent of the absence or presence of other applications. Composability is required

Rational calculation accuracy in acousto-optical matrix-vector processor

Science.gov (United States)

Oparin, V. V.; Tigin, Dmitry V.

1994-01-01

The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

Seismic response analysis for a deeply embedded nuclear power plant

International Nuclear Information System (INIS)

Chen, W.W.H.; Chatterjee, M.; Day, S.M.

1979-01-01

One of the important aspect of the aseimic design of nuclear power plants is the evaluation of the seismic soil-structure interaction effect due to design earthquakes. The soil-structure interaction effect can initiate rocking and result in different soil motions compared to the free field motions, thus significantly affecting the structural response. Two methods are generally used to solve the seismic soil-structure interaction problems: the direct finite element method (FLUSH) and the substructure or impedance approach. This paper presents the results of the horizontal seismic soil-structure interaction analysis using the impedance aproach and the direct finite element method for a deeply embedded nuclear power plant. (orig.)

Embedded Systems

Indian Academy of Sciences (India)

Embedded system, micro-con- troller ... Embedded systems differ from general purpose computers in many ... Low cost: As embedded systems are extensively used in con- .... operating systems for the desktop computers where scheduling.

Upside to downsizing : Acceleware's graphic processor technology propels seismic data processing revolution

Energy Technology Data Exchange (ETDEWEB)

Smith, M.

2009-11-15

Accelware has developed a graphic processor technology (GPU) that is transforming the petroleum industry. The benefits of the technology are its small-footprint, low-wattage, and high speed. The software brings supercomputing speed to the desktop by leveraging the massive parallel processing capacity to the very latest in GPU technology. This article discussed the GPU technology and its emergence as a powerful supercomputing tool. Accelware's partnering with California-based NVIDIA was also outlined. The advantages of the technology were also discussed including its smaller footprint. Accelware's hardware takes up a fraction of the space and uses up to 70 per cent less power than a traditional central processing unit. By combining Accelware's core knowledge in making complex algorithms run in parallel with an in-house team of seismic industry experts, the company provides software solutions for seismic data processors that access the massively parallel processing capabilities of GPUs. 1 fig.

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

Energy Technology Data Exchange (ETDEWEB)

Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

International Nuclear Information System (INIS)

Barhen, Jacob; Kerekes, Ryan A.; St Charles, Jesse Lee; Buckner, Mark A.

2008-01-01

High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

Real-time simulation of MHD/steam power plants by digital parallel processors

International Nuclear Information System (INIS)

Johnson, R.M.; Rudberg, D.A.

1981-01-01

Attention is given to a large FORTRAN coded program which simulates the dynamic response of the MHD/steam plant on either a SEL 32/55 or VAX 11/780 computer. The code realizes a detailed first-principle model of the plant. Quite recently, in addition to the VAX 11/780, an AD-10 has been installed for usage as a real-time simulation facility. The parallel processor AD-10 is capable of simulating the MHD/steam plant at several times real-time rates. This is desirable in order to develop rapidly a large data base of varied plant operating conditions. The combined-cycle MHD/steam plant model is discussed, taking into account a number of disadvantages. The disadvantages can be overcome with the aid of an array processor used as an adjunct to the unit processor. The conversion of some computations for real-time simulation is considered

A prediction method for job runtimes on shared processors: Survey, statistical analysis and new avenues

NARCIS (Netherlands)

Dobber, A.M.; van der Mei, R.D.; Koole, G.M.

2007-01-01

Grid computing is an emerging technology by which huge numbers of processors over the world create a global source of processing power. Their collaboration makes it possible to perform computations that are too extensive to perform on a single processor. On a grid, processors may connect and

Design of Processors with Reconfigurable Microarchitecture

Directory of Open Access Journals (Sweden)

Andrey Mokhov

2014-01-01

Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

Coordinated Energy Management in Heterogeneous Processors

Directory of Open Access Journals (Sweden)

Indrani Paul

2014-01-01

Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

Array processors: an introduction to their architecture, software, and applications in nuclear medicine

International Nuclear Information System (INIS)

King, M.A.; Doherty, P.W.; Rosenberg, R.J.; Cool, S.L.

1983-01-01

Array processors are ''number crunchers'' that dramatically enhance the processing power of nuclear medicine computer systems for applicatons dealing with the repetitive operations involved in digital image processing of large segments of data. The general architecture and the programming of array processors are introduced, along with some applications of array processors to the reconstruction of emission tomographic images, digital image enhancement, and functional image formation

A Modular Low-Complexity ECG Delineation Algorithm for Real-Time Embedded Systems.

Science.gov (United States)

Bote, Jose Manuel; Recas, Joaquin; Rincon, Francisco; Atienza, David; Hermida, Roman

2018-03-01

This work presents a new modular and low-complexity algorithm for the delineation of the different ECG waves (QRS, P and T peaks, onsets, and end). Involving a reduced number of operations per second and having a small memory footprint, this algorithm is intended to perform real-time delineation on resource-constrained embedded systems. The modular design allows the algorithm to automatically adjust the delineation quality in runtime to a wide range of modes and sampling rates, from a ultralow-power mode when no arrhythmia is detected, in which the ECG is sampled at low frequency, to a complete high-accuracy delineation mode, in which the ECG is sampled at high frequency and all the ECG fiducial points are detected, in the case of arrhythmia. The delineation algorithm has been adjusted using the QT database, providing very high sensitivity and positive predictivity, and validated with the MIT database. The errors in the delineation of all the fiducial points are below the tolerances given by the Common Standards for Electrocardiography Committee in the high-accuracy mode, except for the P wave onset, for which the algorithm is above the agreed tolerances by only a fraction of the sample duration. The computational load for the ultralow-power 8-MHz TI MSP430 series microcontroller ranges from 0.2% to 8.5% according to the mode used.

A new paradigm on battery powered embedded system design based on User-Experience-Oriented method

International Nuclear Information System (INIS)

Wang, Zhuoran; Wu, Yue

2014-01-01

The battery sustainable time has been an active research topic recently for the development of battery powered embedded products such as tablets and smart phones, which are determined by the battery capacity and power consumption. Despite numerous efforts on the improvement of battery capacity in the field of material engineering, the power consumption also plays an important role and easier to ameliorate in delivering a desirable user-experience, especially considering the moderate advancement on batteries for decades. In this study, a new Top-Down modelling method, User-Experience-Oriented Battery Powered Embedded System Design Paradigm, is proposed to estimate the target average power consumption, to guide the hardware and software design, and eventually to approach the theoretical lowest power consumption that the application is still able to provide the full functionality. Starting from the 10-hour sustainable time standard, average working current is defined with battery design capacity and set as a target. Then an implementation is illustrated from both hardware perspective, which is summarized as Auto-Gating power management, and from software perspective, which introduces a new algorithm, SleepVote, to guide the system task design and scheduling

A new paradigm on battery powered embedded system design based on User-Experience-Oriented method

Science.gov (United States)

Wang, Zhuoran; Wu, Yue

2014-03-01

The battery sustainable time has been an active research topic recently for the development of battery powered embedded products such as tablets and smart phones, which are determined by the battery capacity and power consumption. Despite numerous efforts on the improvement of battery capacity in the field of material engineering, the power consumption also plays an important role and easier to ameliorate in delivering a desirable user-experience, especially considering the moderate advancement on batteries for decades. In this study, a new Top-Down modelling method, User-Experience-Oriented Battery Powered Embedded System Design Paradigm, is proposed to estimate the target average power consumption, to guide the hardware and software design, and eventually to approach the theoretical lowest power consumption that the application is still able to provide the full functionality. Starting from the 10-hour sustainable time standard, average working current is defined with battery design capacity and set as a target. Then an implementation is illustrated from both hardware perspective, which is summarized as Auto-Gating power management, and from software perspective, which introduces a new algorithm, SleepVote, to guide the system task design and scheduling.

A Heterogeneous Multi-core Architecture with a Hardware Kernel for Control Systems

DEFF Research Database (Denmark)

Li, Gang; Guan, Wei; Sierszecki, Krzysztof

2012-01-01

Rapid industrialisation has resulted in a demand for improved embedded control systems with features such as predictability, high processing performance and low power consumption. Software kernel implementation on a single processor is becoming more difficult to satisfy those constraints. This pa......Rapid industrialisation has resulted in a demand for improved embedded control systems with features such as predictability, high processing performance and low power consumption. Software kernel implementation on a single processor is becoming more difficult to satisfy those constraints......). Second, a heterogeneous multi-core architecture is investigated, focusing on its performance in relation to hard real-time constraints and predictable behavior. Third, the hardware implementation of HARTEX is designated to support the heterogeneous multi-core architecture. This hardware kernel has...... several advantages over a similar kernel implemented in software: higher-speed processing capability, parallel computation, and separation between the kernel itself and the applications being run. A microbenchmark has been used to compare the hardware kernel with the software kernel, and compare...

Efficient Implementation of Solvers for Linear Model Predictive Control on Embedded Devices

DEFF Research Database (Denmark)

Frison, Gianluca; Kwame Minde Kufoalor, D.; Imsland, Lars

2014-01-01

This paper proposes a novel approach for the efficient implementation of solvers for linear MPC on embedded devices. The main focus is to explain in detail the approach used to optimize the linear algebra for selected low-power embedded devices, and to show how the high-performance implementation...

Soft electron processor for surface sterilization of food material

International Nuclear Information System (INIS)

Baba, Takashi; Kaneko, Hiromi; Taniguchi, Shuichi

2004-01-01

As frozen or chilled foods have become popular nowadays, it has become very important to provide raw materials with lower level microbial contamination to food processing companies. Consequently, the sterilization of food material is one of the major topics for food processing. Dried materials like grains, beans and spices, etc., are not typically deeply contaminated by microorganisms, which reside on the surfaces of materials, so it is very useful to take low energetic, lower than 300 keV, electrons with small penetration power (Soft-Electrons), as a sterilization method for such materials. Soft-Electrons is researched and named by Dr. Hayashi et al. This is a non-thermal method, so one can keep foods hygienic without serious deterioration. It is also a physical method, so is free from residues of chemicals in foods. Recently, Nissin-High Voltage Co., Ltd. have developed and manufactured equipment for commercial use of Soft-Electrons (Soft Electron Processor), which can process 500 kg/h of grains. This report introduces the Soft Electron Processor and shows the results of sterilization of wheat and brown rice by the equipment

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2014-01-01

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology. PMID:24379047

A FPGA embedded web server for remote monitoring and control of smart sensors networks.

Science.gov (United States)

Magdaleno, Eduardo; Rodríguez, Manuel; Pérez, Fernando; Hernández, David; García, Enrique

2013-12-27

This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI). The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A). Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

A FPGA Embedded Web Server for Remote Monitoring and Control of Smart Sensors Networks

Directory of Open Access Journals (Sweden)

Eduardo Magdaleno

2013-12-01

Full Text Available This article describes the implementation of a web server using an embedded Altera NIOS II IP core, a general purpose and configurable RISC processor which is embedded in a Cyclone FPGA. The processor uses the μCLinux operating system to support a Boa web server of dynamic pages using Common Gateway Interface (CGI. The FPGA is configured to act like the master node of a network, and also to control and monitor a network of smart sensors or instruments. In order to develop a totally functional system, the FPGA also includes an implementation of the time-triggered protocol (TTP/A. Thus, the implemented master node has two interfaces, the webserver that acts as an Internet interface and the other to control the network. This protocol is widely used to connecting smart sensors and actuators and microsystems in embedded real-time systems in different application domains, e.g., industrial, automotive, domotic, etc., although this protocol can be easily replaced by any other because of the inherent characteristics of the FPGA-based technology.

Energy efficient HPC on embedded SoCs : optimization techniques for mali GPU

OpenAIRE

Grasso, Ivan; Radojkovic, Petar; Rajovic, Nikola; Gelado Fernandez, Isaac; Ramírez Bellido, Alejandro

2014-01-01

A lot of effort from academia and industry has been invested in exploring the suitability of low-power embedded technologies for HPC. Although state-of-the-art embedded systems-on-chip (SoCs) inherently contain GPUs that could be used for HPC, their performance and energy capabilities have never been evaluated. Two reasons contribute to the above. Primarily, embedded GPUs until now, have not supported 64-bit floating point arithmetic - a requirement for HPC. Secondly, embedded GPUs did not pr...

observations of hot molecular gas emission from embedded low-mass protostars

DEFF Research Database (Denmark)

Visser, R.; Kristensen, L. E.; Bruderer, S.

2012-01-01

Aims. Young stars interact vigorously with their surroundings, as evident from the highly rotationally excited CO (up to Eu/k = 4000 K) and H2O emission (up to 600 K) detected by the Herschel Space Observatory in embedded low-mass protostars. Our aim is to construct a model that reproduces...... the observations quantitatively, to investigate the origin of the emission, and to use the lines as probes of the various heating mechanisms. Methods. The model consists of a spherical envelope with a power-law density structure and a bipolar outflow cavity. Three heating mechanisms are considered: passive heating...... such as luminosity and envelope mass. Results. The bulk of the gas in the envelope, heated by the protostellar luminosity, accounts for 3–10% of the CO luminosity summed over all rotational lines up to J = 40–39; it is best probed by low-J CO isotopologue lines such as C18O 2–1 and 3–2. The UV-heated gas and the C...

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Baird, S.A.; Biddulph, P.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

The UA1 upgrade calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

1990-01-01

The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

Scheduling Driven Partitioning of Heterogeneous Embedded Systems

DEFF Research Database (Denmark)

Pop, Paul; Eles, Petru; Peng, Zebo

1998-01-01

In this paper we present an algorithm for system level hardware/software partitioning of heterogeneous embedded systems. The system is represented as an abstract graph which captures both data-flow and the flow of control. Given an architecture consisting of several processors, ASICs and shared...... busses, our partitioning algorithm finds the partitioning with the smallest hardware cost and is able to predict and guarantee the performance of the system in terms of worst case delay....

Safety-critical Java for embedded systems

DEFF Research Database (Denmark)

Schoeberl, Martin; Dalsgaard, Andreas Engelbredt; Hansen, René Rydhof

2016-01-01

This paper presents the motivation for and outcomes of an engineering research project on certifiable Javafor embedded systems. The project supports the upcoming standard for safety-critical Java, which defines asubset of Java and libraries aiming for development of high criticality systems....... The outcome of this projectinclude prototype safety-critical Java implementations, a time-predictable Java processor, analysis tools formemory safety, and example applications to explore the usability of safety-critical Java for this applicationarea. The text summarizes developments and key contributions...

The research and application of multi-biometric acquisition embedded system

Science.gov (United States)

Deng, Shichao; Liu, Tiegen; Guo, Jingjing; Li, Xiuyan

2009-11-01

The identification technology based on multi-biometric can greatly improve the applicability, reliability and antifalsification. This paper presents a multi-biometric system bases on embedded system, which includes: three capture daughter boards are applied to obtain different biometric: one each for fingerprint, iris and vein of the back of hand; FPGA (Field Programmable Gate Array) is designed as coprocessor, which uses to configure three daughter boards on request and provides data path between DSP (digital signal processor) and daughter boards; DSP is the master processor and its functions include: control the biometric information acquisition, extracts feature as required and responsible for compare the results with the local database or data server through network communication. The advantages of this system were it can acquire three different biometric in real time, extracts complexity feature flexibly in different biometrics' raw data according to different purposes and arithmetic and network interface on the core-board will be the solution of big data scale. Because this embedded system has high stability, reliability, flexibility and fit for different data scale, it can satisfy the demand of multi-biometric recognition.

Embedded fiber optic ultrasonic sensors and generators

Science.gov (United States)

Dorighi, John F.; Krishnaswamy, Sridhar; Achenbach, Jan D.

1995-04-01

Ultrasonic sensors and generators based on fiber-optic systems are described. It is shown that intrinsic fiber optic Fabry-Perot ultrasound sensors that are embedded in a structure can be stabilized by actively tuning the laser frequency. The need for this method of stabilization is demonstrated by detecting piezoelectric transducer-generated ultrasonic pulses in the presence of low frequency dynamic strains that are intentionally induced to cause sensor drift. The actively stabilized embedded fiber optic Fabry-Perot sensor is also shown to have sufficient sensitivity to detect ultrasound that is generated in the interior of a structure by means of a high-power optical fiber that pipes energy from a pulsed laser to an embedded generator of ultrasound.

[Development of Bluetooth wireless sensors].

Science.gov (United States)

Moor, C; Schwaibold, M; Roth, H; Schöchlin, J; Bolz, A

2002-01-01

Wireless communication could help to overcome current obstacles in medical devices and could enable medical services to offer completely new scenarios in health care. The Bluetooth technology which is the upcoming global market leader in wireless communication turned out to be perfectly suited not only for consumer market products but also in the medical environment [1]. It offers a low power, low cost connection in the medium range of 1-100 m with a bandwidth of currently 723.2 kbaud. This paper describes the development of a wireless ECG device and a Pulse Oximeter. Equipped with a Bluetooth port, the measurement devices are enabled to transmit data between the sensor and a Bluetooth-monitor. Therefore, CSR's Bluetooth protocol embedded two-processor and embedded single-processor architecture has been used.

Abelian embedding formulation of the Stueckelberg model and its power-counting renormalizable extension

International Nuclear Information System (INIS)

Quadri, Andrea

2006-01-01

We elucidate the geometry of the polynomial formulation of the non-Abelian Stueckelberg mechanism. We show that a natural off-shell nilpotent Becchi-Rouet-Stora-Tyutin (BRST) differential exists allowing to implement the constraint on the σ field by means of BRST techniques. This is achieved by extending the ghost sector by an additional U(1) factor (Abelian embedding). An important consequence is that a further BRST-invariant but not gauge-invariant mass term can be written for the non-Abelian gauge fields. As all versions of the Stueckelberg theory, also the Abelian embedding formulation yields a nonpower-counting renormalizable theory in D=4. We then derive its natural power-counting renormalizable extension and show that the physical spectrum contains a physical massive scalar particle. Physical unitarity is also established. This model implements the spontaneous symmetry breaking in the Abelian embedding formalism

A 4-kbit low-cost antifuse one-time programmable memory macro for embedded applications

International Nuclear Information System (INIS)

Li Xian; Zhong Huicai; Jia Cheng; Li Xin

2014-01-01

A 4-kbit low-cost one-time programmable (OTP) memory macro for embedded applications is designed and implemented in a 0.18-μm standard CMOS process. The area of the proposed 1.5 transistor (1.5T) OTP cell is 2.13 μm 2 , which is a 49.3% size reduction compared to the previously reported cells. The 1.5T cell is fabricated and measured and shows a large programming window without any disturbance. A novel high voltage switch (HVSW) circuit is also proposed to make sure the OTP macro, implemented in a standard CMOS process, works reliably with the high program voltage. The OTP macro is embedded in negative radio frequency identification (RFID) tags. The full chip size, including the analog front-end, digital controller and the 4-kbit OTP macro, is 600 × 600 μm 2 . The 4-kbit OTP macro only consumes 200 × 260 μm 2 . The measurement shows a 100% program yield by adjusting the program time and has obvious advantages in the core area and power consumption compared to the reported 3T and 2T OTP cores. (semiconductor integrated circuits)

Research on applications of ARM-LINUX embedded systems in manufacturing the nuclear equipment

International Nuclear Information System (INIS)

Nguyen Van Sy; Phan Luong Tuan; Nguyen Xuan Vinh; Dang Quang Bao

2016-01-01

A new microprocessor system that is ARM processor with open source Linux operating system is studied with the objective to apply ARM-Linux embedded systems in manufacturing the nuclear equipment. We use the development board of the company to learn and to build the workflow for an embedded system, then basing on the knowledge we design a motherboard embedded systems interface with the peripherals is buttons, LEDs through GPIO interface and connected with GM counting system via RS232 interface. The results of this study are: i) The procedures for working with embedded systems: process customization, installation embedded operating system and installation process, configure the development tools on the host computer; ii) ARM-Linux motherboard embedded systems interface with the peripherals and GM counting system, indicating the counts from GM counting system on the touch screen. (author)

Embedded parallel processing based ground control systems for small satellite telemetry

Science.gov (United States)

Forman, Michael L.; Hazra, Tushar K.; Troendly, Gregory M.; Nickum, William G.

1994-01-01

The use of networked terminals which utilize embedded processing techniques results in totally integrated, flexible, high speed, reliable, and scalable systems suitable for telemetry and data processing applications such as mission operations centers (MOC). Synergies of these terminals, coupled with the capability of terminal to receive incoming data, allow the viewing of any defined display by any terminal from the start of data acquisition. There is no single point of failure (other than with network input) such as exists with configurations where all input data goes through a single front end processor and then to a serial string of workstations. Missions dedicated to NASA's ozone measurements program utilize the methodologies which are discussed, and result in a multimission configuration of low cost, scalable hardware and software which can be run by one flight operations team with low risk.

A Real-Time Sound Field Rendering Processor

Directory of Open Access Journals (Sweden)

Tan Yiyu

2017-12-01

Full Text Available Real-time sound field renderings are computationally intensive and memory-intensive. Traditional rendering systems based on computer simulations suffer from memory bandwidth and arithmetic units. The computation is time-consuming, and the sample rate of the output sound is low because of the long computation time at each time step. In this work, a processor with a hybrid architecture is proposed to speed up computation and improve the sample rate of the output sound, and an interface is developed for system scalability through simply cascading many chips to enlarge the simulated area. To render a three-minute Beethoven wave sound in a small shoe-box room with dimensions of 1.28 m × 1.28 m × 0.64 m, the field programming gate array (FPGA-based prototype machine with the proposed architecture carries out the sound rendering at run-time while the software simulation with the OpenMP parallelization takes about 12.70 min on a personal computer (PC with 32 GB random access memory (RAM and an Intel i7-6800K six-core processor running at 3.4 GHz. The throughput in the software simulation is about 194 M grids/s while it is 51.2 G grids/s in the prototype machine even if the clock frequency of the prototype machine is much lower than that of the PC. The rendering processor with a processing element (PE and interfaces consumes about 238,515 gates after fabricated by the 0.18 µm processing technology from the ROHM semiconductor Co., Ltd. (Kyoto Japan, and the power consumption is about 143.8 mW.

Microwave de-embedding from theory to applications

CERN Document Server

Crupi, Giovanni

2013-01-01

This groundbreaking book is the first to give an introduction to microwave de-embedding, showing how it is the cornerstone for waveform engineering. The authors of each chapter clearly explain the theoretical concepts, providing a foundation that supports linear and non-linear measurements, modelling and circuit design. Recent developments and future trends in the field are covered throughout, including successful strategies for low-noise and power amplifier design. This book is a must-have for those wishing to understand the full potential of the microwave de-embedding concept to achieve suc

An Evaluation of an Ada Implementation of the Rete Algorithm for Embedded Flight Processors

Science.gov (United States)

1990-12-01

computers was desired. The VAX VMS operating system has many built-in methods for determining program performance (including VAX PCA), but these methods... overviev , of the target environment-- the MIL-STD-1750A VHSIC Avionic Modular Processor ( VA.IP, running under the Ada Avionics Real-Time Software (AARTS... computers . Mil-STD-1750A, the Air Force’s standard flight computer architecture, however, places severe constraints on applications software processing

Embedded 32-bit Differential Pulse Voltammetry (DPV) Technique for 3-electrode Cell Sensing

Science.gov (United States)

N, Aqmar N. Z.; Abdullah, W. F. H.; Zain, Z. M.; Rani, S.

2018-03-01

This paper addresses the development of differential pulse voltammetry (DPV) embedded algorithm using an ARM cortex processor with new developed potentiostat circuit design for in-situ 3-electrode cell sensing. This project is mainly to design a low cost potentiostat for the researchers in laboratories. It is required to develop an embedded algorithm for analytical technique to be used with the designed potentiostat. DPV is one of the most familiar pulse technique method used with 3-electrode cell sensing in chemical studies. Experiment was conducted on 10mM solution of Ferricyanide using the designed potentiostat and the developed DPV algorithm. As a result, the device can generate an excitation signal of DPV from 0.4V to 1.2V and produced a peaked voltammogram with relatively small error compared to the commercial potentiostat; which is only 6.25% difference in peak potential reading. The design of potentiostat device and its DPV algorithm is verified.

Low-loss saturable absorbers based on tapered fibers embedded in carbon nanotube/polymer composites

Science.gov (United States)

Martinez, Amos; Al Araimi, Mohammed; Dmitriev, Artemiy; Lutsyk, Petro; Li, Shen; Mou, Chengbo; Rozhin, Alexey; Sumetsky, Misha; Turitsyn, Sergei

2017-12-01

The emergence of low-dimensional materials has opened new opportunities in the fabrication of compact nonlinear photonic devices. Single-walled carbon nanotubes were among the first of those materials to attract the attention of the photonics community owing to their high third order susceptibility, broadband operation, and ultrafast response. Saturable absorption, in particular, has become a widespread application for nanotubes in the mode-locking of a fiber laser where they are used as nonlinear passive amplitude modulators to initiate pulsed operation. Numerous approaches have been proposed for the integration of nanotubes in fiber systems; these can be divided into those that rely on direct interaction (where the nanotubes are sandwiched between fiber connectors) and those that rely on lateral interaction with the evanescence field of the propagating wave. Tapered fibers, in particular, offer excellent flexibility to adjust the nonlinearity of nanotube-based devices but suffer from high losses (typically exceeding 50%) and poor saturable to non-saturable absorption ratios (typically above 1:5). In this paper, we propose a method to fabricate carbon nanotube saturable absorbers with controllable saturation power, low-losses (as low as 15%), and large saturable to non-saturable loss ratios approaching 1:1. This is achieved by optimizing the procedure of embedding tapered fibers in low-refractive index polymers. In addition, this study sheds light in the operation of these devices, highlighting a trade-off between losses and saturation power and providing guidelines for the design of saturable absorbers according to their application.

Monitoring the performance of off-site processors

International Nuclear Information System (INIS)

Miller, C.C.

1995-01-01

Commercial nuclear power plants have been able to utilize the latest technologies and achieve large volume reduction by obtaining off-site waste processor services. Although the use of such services reduce the burden of waste processing it also reduces the utility's control over the process. Monitoring the performance of off-site processors is important so that the utility is cognizant of the waste disposition for required regulatory reporting. In addition to obtaining data for Reg Guide 1.21 reporting, Performance monitoring is important to determine which vendor and which services to utilize. Off-site processor services were initially offered for the decontamination of metallic waste. Since that time the list of services has expanded to include supercompaction, survey for release, incineration and metal melting. The number of vendors offering off-site services has increased and the services they offer vary. processing rates vary between vendors and have different charge bases. Determining which vendor to use for what service can be complicated and confusing

Array processor architecture

Science.gov (United States)

Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

1983-01-01

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Probabilistic programmable quantum processors

International Nuclear Information System (INIS)

Buzek, V.; Ziman, M.; Hillery, M.

2004-01-01

We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

A Hybrid Scheme Based on Pipelining and Multitasking in Mobile Application Processors for Advanced Video Coding

Directory of Open Access Journals (Sweden)

Muhammad Asif

2015-01-01

Full Text Available One of the key requirements for mobile devices is to provide high-performance computing at lower power consumption. The processors used in these devices provide specific hardware resources to handle computationally intensive video processing and interactive graphical applications. Moreover, processors designed for low-power applications may introduce limitations on the availability and usage of resources, which present additional challenges to the system designers. Owing to the specific design of the JZ47x series of mobile application processors, a hybrid software-hardware implementation scheme for H.264/AVC encoder is proposed in this work. The proposed scheme distributes the encoding tasks among hardware and software modules. A series of optimization techniques are developed to speed up the memory access and data transferring among memories. Moreover, an efficient data reusage design is proposed for the deblock filter video processing unit to reduce the memory accesses. Furthermore, fine grained macroblock (MB level parallelism is effectively exploited and a pipelined approach is proposed for efficient utilization of hardware processing cores. Finally, based on parallelism in the proposed design, encoding tasks are distributed between two processing cores. Experiments show that the hybrid encoder is 12 times faster than a highly optimized sequential encoder due to proposed techniques.

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

OpenAIRE

Abdul Kareem PARCHUR; Ram Asaray SINGH

2012-01-01

High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

The LASS hardware processor

International Nuclear Information System (INIS)

Kunz, P.F.

1976-01-01

The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

A Score Function for Optimizing the Cycle-Life of Battery-Powered Embedded Systems

NARCIS (Netherlands)

Wognsen, Erik Ramsgaard; Haverkort, Boudewijn R.H.M.; Jongerden, M.R.; Hansen, René Rydhof; Larsen, K.G.; Sankaranarayanan, Sriram; Vicario, Enrico

An ever increasing share of embedded systems is powered by rechargeable batteries. These batteries deteriorate with the number of charge/discharge cycles they are subjected to, the so-called cycle life. In this paper, we propose the wear score function to compare and evaluate the relative impact of

Active and passive component embedding into low-cost plastic substrates aimed at smart system applications

NARCIS (Netherlands)

Cauwe, M.; Vandecasteele, B.; Baets, J. de; Brand, J. van den; Kusters, R.; Sridhar, A.

2013-01-01

The technology development for a low-cost, roll-to-roll compatible chip embedding process is described in this paper. Target applications are intelligent labels and disposable sensor patches. Two generations of the technology are depicted. In the first version of the embedding technology, the chips

Development of an Ion Thruster and Power Processor for New Millennium's Deep Space 1 Mission

Science.gov (United States)

Sovey, James S.; Hamley, John A.; Haag, Thomas W.; Patterson, Michael J.; Pencil, Eric J.; Peterson, Todd T.; Pinero, Luis R.; Power, John L.; Rawlin, Vincent K.; Sarmiento, Charles J.;

Invasive tightly coupled processor arrays

CERN Document Server

LARI, VAHID

2016-01-01

This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

The readout performance evaluation of PowerPC

International Nuclear Information System (INIS)

Chu Yuanping; Zhang Hongyu; Zhao Jingwei; Ye Mei; Tao Ning; Zhu Kejun; Tang Suqiu; Guo Yanan

2003-01-01

PowerPC, as a powerful low-cost embedded computer, is one of the very important research objects in recent years in the project of BESIII data acquisition system. The researches on the embedded system and embedded computer have achieved many important results in the field of High Energy Physics especially in the data acquisition system. The one of the key points to design an acquisition system using PowerPC is to evaluate the readout ability of PowerPC correctly. The paper introduce some tests for the PowerPC readout performance. (authors)

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Science.gov (United States)

DeGregorio, Kelly; Wilson, Dale G.

2009-01-01

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand

UA1 upgrade first-level calorimeter trigger processor

International Nuclear Information System (INIS)

Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

1989-01-01

A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

Integrated electrochromic iris device for low power and space-limited applications

International Nuclear Information System (INIS)

Deutschmann, T; Oesterschulze, E

2014-01-01

We present a micro-electrooptical iris based on the electrochromic polymer poly(3,4-ethylenedioxythiophene). Two ring-shaped concentric polymer-segments embedded in a transparent electrochemical cell form the micro iris. The polymer layers change their absorption when an external voltage is applied. This iris device benefits from the absence of any mechanically moving part. This renders a very slim design possible, which is suited for small integrated camera systems. During operation the polymer maintains its absorbing state without power consumption. Its low driving voltage of maximum 1.5 V is beneficial for battery powered applications. The impact of the iris on the depth of focus and transmission control as well as its dynamical behavior will be addressed. (paper)

Low-loss saturable absorbers based on tapered fibers embedded in carbon nanotube/polymer composites

Directory of Open Access Journals (Sweden)

Amos Martinez

2017-12-01

Full Text Available The emergence of low-dimensional materials has opened new opportunities in the fabrication of compact nonlinear photonic devices. Single-walled carbon nanotubes were among the first of those materials to attract the attention of the photonics community owing to their high third order susceptibility, broadband operation, and ultrafast response. Saturable absorption, in particular, has become a widespread application for nanotubes in the mode-locking of a fiber laser where they are used as nonlinear passive amplitude modulators to initiate pulsed operation. Numerous approaches have been proposed for the integration of nanotubes in fiber systems; these can be divided into those that rely on direct interaction (where the nanotubes are sandwiched between fiber connectors and those that rely on lateral interaction with the evanescence field of the propagating wave. Tapered fibers, in particular, offer excellent flexibility to adjust the nonlinearity of nanotube-based devices but suffer from high losses (typically exceeding 50% and poor saturable to non-saturable absorption ratios (typically above 1:5. In this paper, we propose a method to fabricate carbon nanotube saturable absorbers with controllable saturation power, low-losses (as low as 15%, and large saturable to non-saturable loss ratios approaching 1:1. This is achieved by optimizing the procedure of embedding tapered fibers in low-refractive index polymers. In addition, this study sheds light in the operation of these devices, highlighting a trade-off between losses and saturation power and providing guidelines for the design of saturable absorbers according to their application.

Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

Directory of Open Access Journals (Sweden)

Abdul Kareem PARCHUR

2012-08-01

Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

Mixed-Signal Architectures for High-Efficiency and Low-Distortion Digital Audio Processing and Power Amplification

Directory of Open Access Journals (Sweden)

Pierangelo Terreni

2010-01-01

Full Text Available The paper addresses the algorithmic and architectural design of digital input power audio amplifiers. A modelling platform, based on a meet-in-the-middle approach between top-down and bottom-up design strategies, allows a fast but still accurate exploration of the mixed-signal design space. Different amplifier architectures are configured and compared to find optimal trade-offs among different cost-functions: low distortion, high efficiency, low circuit complexity and low sensitivity to parameter changes. A novel amplifier architecture is derived; its prototype implements digital processing IP macrocells (oversampler, interpolating filter, PWM cross-point deriver, noise shaper, multilevel PWM modulator, dead time compensator on a single low-complexity FPGA while off-chip components are used only for the power output stage (LC filter and power MOS bridge; no heatsink is required. The resulting digital input amplifier features a power efficiency higher than 90% and a total harmonic distortion down to 0.13% at power levels of tens of Watts. Discussions towards the full-silicon integration of the mixed-signal amplifier in embedded devices, using BCD technology and targeting power levels of few Watts, are also reported.

Metal membrane-type 25-kW methanol fuel processor for fuel-cell hybrid vehicle

Science.gov (United States)

Han, Jaesung; Lee, Seok-Min; Chang, Hyuksang

A 25-kW on-board methanol fuel processor has been developed. It consists of a methanol steam reformer, which converts methanol to hydrogen-rich gas mixture, and two metal membrane modules, which clean-up the gas mixture to high-purity hydrogen. It produces hydrogen at rates up to 25 N m 3/h and the purity of the product hydrogen is over 99.9995% with a CO content of less than 1 ppm. In this fuel processor, the operating condition of the reformer and the metal membrane modules is nearly the same, so that operation is simple and the overall system construction is compact by eliminating the extensive temperature control of the intermediate gas streams. The recovery of hydrogen in the metal membrane units is maintained at 70-75% by the control of the pressure in the system, and the remaining 25-30% hydrogen is recycled to a catalytic combustion zone to supply heat for the methanol steam-reforming reaction. The thermal efficiency of the fuel processor is about 75% and the inlet air pressure is as low as 4 psi. The fuel processor is currently being integrated with 25-kW polymer electrolyte membrane fuel-cell (PEMFC) stack developed by the Hyundai Motor Company. The stack exhibits the same performance as those with pure hydrogen, which proves that the maximum power output as well as the minimum stack degradation is possible with this fuel processor. This fuel-cell 'engine' is to be installed in a hybrid passenger vehicle for road testing.

Low-temperature thermoelectric power factor enhancement by controlling nanoparticle size distribution.

Science.gov (United States)

Zebarjadi, Mona; Esfarjani, Keivan; Bian, Zhixi; Shakouri, Ali

2011-01-12

Coherent potential approximation is used to study the effect of adding doped spherical nanoparticles inside a host matrix on the thermoelectric properties. This takes into account electron multiple scatterings that are important in samples with relatively high volume fraction of nanoparticles (>1%). We show that with large fraction of uniform small size nanoparticles (∼1 nm), the power factor can be enhanced significantly. The improvement could be large (up to 450% for GaAs) especially at low temperatures when the mobility is limited by impurity or nanoparticle scattering. The advantage of doping via embedded nanoparticles compared to the conventional shallow impurities is quantified. At the optimum thermoelectric power factor, the electrical conductivity of the nanoparticle-doped material is larger than that of impurity-doped one at the studied temperature range (50-500 K) whereas the Seebeck coefficient of the nanoparticle doped material is enhanced only at low temperatures (∼50 K).

An intercomparison of Canadian external dosimetry processors for radiation protection

International Nuclear Information System (INIS)

1989-10-01

The five Canadian external dosimetry processors have participated in a two-stage intercomparison. The first stage involved dosimeters to known radiation fields under controlled laboratory conditions. The second stage involved exposing dosimeters to radiation fields in power reactor working environments. The results for each stage indicated the dose reported by each processor relative to an independently determined dose and relative to the others. The results of the intercomparisons confirm the original supposition: namely that the average differences in reported dose among five processors are much less than the uncertainty limits recommended by the ICRP. This report provides a description of the experimental methods as well as a discussion of the results for each stage. The report also includes a set of recommendations

Engineering embedded systems physics, programs, circuits

CERN Document Server

Hintenaus, Peter

2015-01-01

This is a textbook for graduate and final-year-undergraduate computer-science and electrical-engineering students interested in the hardware and software aspects of embedded and cyberphysical systems design. It is comprehensive and self-contained, covering everything from the basics to case-study implementation. Emphasis is placed on the physical nature of the problem domain and of the devices used. The reader is assumed to be familiar on a theoretical level with mathematical tools like ordinary differential equation and Fourier transforms. In this book these tools will be put to practical use. Engineering Embedded Systems begins by addressing basic material on signals and systems, before introducing to electronics. Treatment of digital electronics accentuating synchronous circuits and including high-speed effects proceeds to micro-controllers, digital signal processors and programmable logic. Peripheral units and decentralized networks are given due weight. The properties of analog circuits and devices like ...

Run control communication for the upgrade of the ATLAS Muon-to-Central Trigger Processor Interface (MUCTPI)

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00223859; The ATLAS collaboration; Armbruster, Aaron James; Carrillo-Montoya, German D.; Chelstowska, Magda Anna; Czodrowski, Patrick; Deviveiros, Pier-Olivier; Eifert, Till; Ellis, Nicolas; Farthouat, Philippe; Galster, Gorm Aske Gram Krohn; Haas, Stefan; Helary, Louis; Lagkas Nikolos, Orestis; Marzin, Antoine; Pauly, Thilo; Ryjov, Vladimir; Schmieden, Kristof; Silva Oliveira, Marcos Vinicius; Stelzer, Harald Joerg; Vichoudis, Paschalis; Wengler, Thorsten

The Muon-to-Central-Trigger-Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3, starting in 2021. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used a SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the framework of the Yocto Project. This approa...

Introduction to co-simulation of software and hardware in embedded processor systems

Energy Technology Data Exchange (ETDEWEB)

Dreike, P.L.; McCoy, J.A.

1996-09-01

From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

Evaluation of the Intel iWarp parallel processor for space flight applications

Science.gov (United States)

Hine, Butler P., III; Fong, Terrence W.

1993-01-01

The potential of a DARPA-sponsored advanced processor, the Intel iWarp, for use in future SSF Data Management Systems (DMS) upgrades is evaluated through integration into the Ames DMS testbed and applications testing. The iWarp is a distributed, parallel computing system well suited for high performance computing applications such as matrix operations and image processing. The system architecture is modular, supports systolic and message-based computation, and is capable of providing massive computational power in a low-cost, low-power package. As a consequence, the iWarp offers significant potential for advanced space-based computing. This research seeks to determine the iWarp's suitability as a processing device for space missions. In particular, the project focuses on evaluating the ease of integrating the iWarp into the SSF DMS baseline architecture and the iWarp's ability to support computationally stressing applications representative of SSF tasks.

Discrete Fourier transformation processor based on complex radix (−1 + j number system

Directory of Open Access Journals (Sweden)

Anidaphi Shadap

2017-02-01

Full Text Available Complex radix (−1 + j allows the arithmetic operations of complex numbers to be done without treating the divide and conquer rules, which offers the significant speed improvement of complex numbers computation circuitry. Design and hardware implementation of complex radix (−1 + j converter has been introduced in this paper. Extensive simulation results have been incorporated and an application of this converter towards the implementation of discrete Fourier transformation (DFT processor has been presented. The functionality of the DFT processor have been verified in Xilinx ISE design suite version 14.7 and performance parameters like propagation delay and dynamic switching power consumption have been calculated by Virtuoso platform in Cadence. The proposed DFT processor has been implemented through conversion, multiplication and addition. The performance parameter matrix in terms of delay and power consumption offered a significant improvement over other traditional implementation of DFT processor.

Power Optimization of Multimode Mobile Embedded Systems with Workload-Delay Dependency

Directory of Open Access Journals (Sweden)

Hoeseok Yang

2016-01-01

Full Text Available This paper proposes to take the relationship between delay and workload into account in the power optimization of microprocessors in mobile embedded systems. Since the components outside a device continuously change their values or properties, the workload to be handled by the systems becomes dynamic and variable. This variable workload is formulated as a staircase function of the delay taken at the previous iteration in this paper and applied to the power optimization of DVFS (dynamic voltage-frequency scaling. In doing so, a graph representation of all possible workload/mode changes during the lifetime of a device, Workload Transition Graph (WTG, is proposed. Then, the power optimization problem is transformed into finding a cycle (closed walk in WTG which minimizes the average power consumption over it. Out of the obtained optimal cycle of WTG, one can derive the optimal power management policy of the target device. It is shown that the proposed policy is valid for both continuous and discrete DVFS models. The effectiveness of the proposed power optimization policy is demonstrated with the simulation results of synthetic and real-life examples.

Functional unit for a processor

NARCIS (Netherlands)

Rohani, A.; Kerkhoff, Hans G.

2013-01-01

The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

The design and realization of general high-speed RAIN100B DAQ module based on powerPC MPC5200B processor

International Nuclear Information System (INIS)

Xue Tao; Gong Guanghua; Shao Beibei

2010-01-01

In order to deal with the DAQ function of nuclear electronics, department of engineering physics of Tsinghua University design and realize a general, high-speed RAIN100B DAQ module based on Freescale's PowerPC MPC5200B processor.And the RAIN100B was used on GEM detector DAQ, it can reach up to 90Mbps data speed. The result is also presented and discussed. (authors)

[Design of an embedded stroke rehabilitation apparatus system based on Linux computer engineering].

Science.gov (United States)

Zhuang, Pengfei; Tian, XueLong; Zhu, Lin

2014-04-01

A realizaton project of electrical stimulator aimed at motor dysfunction of stroke is proposed in this paper. Based on neurophysiological biofeedback, this system, using an ARM9 S3C2440 as the core processor, integrates collection and display of surface electromyography (sEMG) signal, as well as neuromuscular electrical stimulation (NMES) into one system. By embedding Linux system, the project is able to use Qt/Embedded as a graphical interface design tool to accomplish the design of stroke rehabilitation apparatus. Experiments showed that this system worked well.

IF-MANET: Interoperable framework for heterogeneous mobile ad hoc networks

OpenAIRE

Hassan, H.

2015-01-01

The advances in low power micro-processors, wireless networks and embedded systems have raised the need to utilize the significant resources of mobile devices. These devices for example, smart phones, tablets, laptops, wearables, and sensors are gaining enormous processing power, storage capacity and wireless bandwidth. In addition, the advancement in wireless mobile technology has created a new communication paradigm via which a wireless network can be created without any priori infrastructu...

Reactor power distribution monitor

International Nuclear Information System (INIS)

Sekimizu, Koichi

1980-01-01

Purpose: To improve the performance and secure the safety of a nuclear reactor by rapidly computing and display the power density in the nuclear reactor by using a plurality of processors. Constitution: Plant data for a nuclear reactor containing the measured values from a local power monitor LPRM are sent and recorded in a magnetic disc. They are also sent to a core performance computer in which burn-up degree distribution and the like are computed, and the results are sent and recorded in the magnetic disc. A central processors loads programs to each of the processors and applies data recorded in the magnetic disc to each of the processors. Each of the processors computes the corresponding power distribution in four fuel assemblies surrounding the LPRM string by the above information. The central processor compiles the computation results and displays them on a display. In this way, power distribution in the fuel assemblies can rapidly be computed to thereby secure the improvement of the performance and safety of the reactor. (Seki, T.)

Adaptive signal processor

Energy Technology Data Exchange (ETDEWEB)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

Adaptive signal processor

International Nuclear Information System (INIS)

Walz, H.V.

1980-07-01

An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

Multithreading in vector processors

Science.gov (United States)

Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

2018-01-16

In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

Digital control card based on digital signal processor

International Nuclear Information System (INIS)

Hou Shigang; Yin Zhiguo; Xia Le

2008-01-01

A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

When Power Shapes Interpersonal Behavior: Low Relationship Power Predicts Men’s Aggressive Responses to Low Situational Power

Science.gov (United States)

Overall, Nickola C.; Hammond, Matthew D.; McNulty, James K.; Finkel, Eli J.

2016-01-01

When does power in intimate relationships shape important interpersonal behaviors, such as psychological aggression? Five studies tested whether possessing low relationship power was associated with aggressive responses, but (1) only within power-relevant relationship interactions when situational power was low, and (2) only by men because masculinity (but not femininity) involves the possession and demonstration of power. In Studies 1 and 2, men lower in relationship power exhibited greater aggressive communication during couples’ observed conflict discussions, but only when they experienced low situational power because they were unable to influence their partner. In Study 3, men lower in relationship power reported greater daily aggressive responses toward their partner, but only on days when they experienced low situational power because they were either (a) unable to influence their partner or (b) dependent on their partner for support. In Study 4, men who possessed lower relationship power exhibited greater aggressive responses during couples’ support-relevant discussions, but only when they had low situational power because they needed high levels of support. Study 5 provided evidence for the theoretical mechanism underlying men’s aggressive responses to low relationship power. Men who possessed lower relationship power felt less manly on days they faced low situational power because their partner was unwilling to change to resolve relationship problems, which in turn predicted greater aggressive responses to their partner. These results demonstrate that fully understanding when and why power is associated with interpersonal behavior requires differentiating between relationship and situational power. PMID:27442766

VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture

NARCIS (Netherlands)

Gruian, Flavius; Westmijze, M.

2008-01-01

This paper compares two hardware design flows, based on the classic VHDL on one side and the relatively new Blue-spec System Verilog (BSV) on the other side. The comparison is based on a case study of a Java embedded architecture, comprising a Java native processor and a memory management unit. The

Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

Science.gov (United States)

Brooks, Geoffrey W.

1996-03-01

Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

Design and development of embedded control system for high power RF test facility

International Nuclear Information System (INIS)

Nageswara Rao, J.; Badapanda, M.K.; Upadhyay, Rinki; Tripathi, Akhilesh; Hannurkar, P.R.

2013-01-01

Design and development of an embedded control system for the control, interlock and operation of 1MW, 352.2 MHz TH2089 klystron based RF test facility. The key components of the control system are NI compact Re configurable Input Output (cRIO) system and Windows based PC. The cRIO system's rugged hardware architecture includes a 1.06 GHz Dual-Core embedded controller with Real Time (RT) Operating System, a reconfigurable Field Programmable Gate Array (FPGA) chassis for custom I/O timing, control and processing; and I/O modules. Windows based Graphical User Interface (GUI) has been developed to guide the user through start-up procedure, to set the operating parameters and also to display the status information of all the signals. The application software for data logging and publishing of the acquired data namely set, read back and status signals of auxiliary power supplies and machine safety interlocks has been developed in LabVIEW RT module and is running on embedded controller. Machine safety interlock logic has been implemented in FPGA to meet the time criticality. (author)

Powerful conveyer belt real-time online detection system based on x-ray

Science.gov (United States)

Rong, Feng; Miao, Chang-yun; Meng, Wei

2009-07-01

The powerful conveyer belt is widely used in the mine, dock, and so on. After used for a long time, internal steel rope of the conveyor belt may fracture, rust, joints moving, and so on .This would bring potential safety problems. A kind of detection system based on x-ray is designed in this paper. Linear array detector (LDA) is used. LDA cost is low, response fast; technology mature .Output charge of LDA is transformed into differential voltage signal by amplifier. This kind of signal have great ability of anti-noise, is suitable for long-distance transmission. The processor is FPGA. A IP core control 4-channel A/D convertor, achieve parallel output data collection. Soft-core processor MicroBlaze which process tcp/ip protocol is embedded in FPGA. Sampling data are transferred to a computer via Ethernet. In order to improve the image quality, algorithm of getting rid of noise from the measurement result and taking gain normalization for pixel value is studied and designed. Experiments show that this system work well, can real-time online detect conveyor belt of width of 2.0m and speed of 5 m/s, does not affect the production. Image is clear, visual and can easily judge the situation of conveyor belt.

Simulation and Embedded Smart Control

DEFF Research Database (Denmark)

Conrad, Finn; Fan, Zhun; Sørensen, Torben

2006-01-01

The paper presents results obtained from a Danish mechatronic research program focusing on intelligent motion control, simulation and embedded smart controllers for hydraulic actuators and robots as well as results from the EU projects. A mechatronic test facility with digital controllers...... for a hydraulic robot was implemented. The controllers apply digital signal processors (DSPs), and Field Programmable Gate Array, short named as FPGA, respectively. The DSP controller utilizes the dSPACE System that is suitable for real-time experimentation, evaluation and validation of control laws...... and algorithms. Furthermore, a developed IT-tool concept for controller and system design utilizing the ISO 10303 STEP Standard is proposed....

Integrating an embedded system in a microwave moisture meter

Science.gov (United States)

The conversion of a PC- or laptop-controlled microwave moisture meter to a stand-alone meter hosting its own embedded system is discussed. The moisture meter measures the attenuation and phase shift of low power microwaves traversing the sample, from which the dielectric properties are calculated. T...

Design and development of a diesel and JP-8 logistic fuel processor

Science.gov (United States)

Roychoudhury, Subir; Lyubovsky, Maxim; Walsh, D.; Chu, Deryn; Kallio, Erik

The paper describes the design and performance of a breadboard prototype for a 5 kW fuel-processor for powering a solid oxide fuel cell (SOFC) stack. The system was based on a small, modular catalytic Microlith auto-thermal (ATR) reactor with the versatility of operating on diesel, Jet-A or JP-8 fuels. The reforming reactor utilized Microlith substrates and catalyst technology (patented and trademarked). These reactors have demonstrated the capability of efficiently reforming liquid and gaseous hydrocarbon fuels at exceptionally high power densities. The performance characteristics of the auto-thermal reactor (ATR) have been presented along with durability data. The fuel processor integrates fuel preparation, steam generation, sulfur removal, pumps, blowers and controls. The system design was developed via ASPEN ® Engineering Suite process simulation software and was analyzed with reference to system balance requirements. Since the fuel processor has not been integrated with a fuel cell, aspects of thermal integration with the stack have not been specifically addressed.

Low power multi-camera system and algorithms for automated threat detection

Science.gov (United States)

Huber, David J.; Khosla, Deepak; Chen, Yang; Van Buer, Darrel J.; Martin, Kevin

2013-05-01

A key to any robust automated surveillance system is continuous, wide field-of-view sensor coverage and high accuracy target detection algorithms. Newer systems typically employ an array of multiple fixed cameras that provide individual data streams, each of which is managed by its own processor. This array can continuously capture the entire field of view, but collecting all the data and back-end detection algorithm consumes additional power and increases the size, weight, and power (SWaP) of the package. This is often unacceptable, as many potential surveillance applications have strict system SWaP requirements. This paper describes a wide field-of-view video system that employs multiple fixed cameras and exhibits low SWaP without compromising the target detection rate. We cycle through the sensors, fetch a fixed number of frames, and process them through a modified target detection algorithm. During this time, the other sensors remain powered-down, which reduces the required hardware and power consumption of the system. We show that the resulting gaps in coverage and irregular frame rate do not affect the detection accuracy of the underlying algorithms. This reduces the power of an N-camera system by up to approximately N-fold compared to the baseline normal operation. This work was applied to Phase 2 of DARPA Cognitive Technology Threat Warning System (CT2WS) program and used during field testing.

Design of Low Power Algorithms for Automatic Embedded Analysis of Patch ECG Signals

DEFF Research Database (Denmark)

Saadi, Dorthe Bodholt

, several different cable-free wireless patch-type ECG recorders have recently reached the market. One of these recorders is the ePatch designed by the Danish company DELTA. The extended monitoring period available with the patch recorders has demonstrated to increase the diagnostic yield of outpatient ECG....... Such algorithms could allow the real-time transmission of clinically relevant information to a central monitoring station. The first step in embedded ECG interpretation is the automatic detection of each individual heartbeat. An important part of this project was therefore to design a novel algorithm...

Benchmarking NWP Kernels on Multi- and Many-core Processors

Science.gov (United States)

Michalakes, J.; Vachharajani, M.

2008-12-01

Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

The selection of embedded computer using in the nuclear physics instruments

International Nuclear Information System (INIS)

Zhang Jianchuan; Nan Gangyang; Wang Yanyu; Su Hong

2010-01-01

It introduces the requirement for embedded PC and the benefits of using it in the experimental nuclear physics instrument developing and improving project. A cording to the specific requirements in the project of improving laboratory instruments. several kinds of embedded computer are compared and specifically tested. Thus, a x86 architecture embedded computer, which have ultra-low-power consumption and a small in size, is selected to be the main component of the controller using in the nuclear physics instrument, and this will be used in the high-speed data acquisition and electronic control system. (authors)

Design and implementation of embedded un-interruptible power supply system (EUPSS) for web-based mobile application

Science.gov (United States)

Zhang, De-gan; Zhang, Xiao-dan

2012-11-01

With the growth of the amount of information manipulated by embedded application systems, which are embedded into devices and offer access to the devices on the internet, the requirements of saving the information systemically is necessary so as to fulfil access from the client and the local processing more efficiently. For supporting mobile applications, a design and implementation solution of embedded un-interruptible power supply (UPS) system (in brief, EUPSS) is brought forward for long-distance monitoring and controlling of UPS based on Web. The implementation of system is based on ATmega161, RTL8019AS and Arm chips with TCP/IP protocol suite for communication. In the embedded UPS system, an embedded file system is designed and implemented which saves the data and index information on a serial EEPROM chip in a structured way and communicates with a microcontroller unit through I2C bus. By embedding the file system into UPS system or other information appliances, users can access and manipulate local data on the web client side. Embedded file system on chips will play a major role in the growth of IP networking. Based on our experiment tests, the mobile users can easily monitor and control UPS in different places of long-distance. The performance of EUPSS has satisfied the requirements of all kinds of Web-based mobile applications.

The definitive guide to ARM Cortex-M3 and Cortex-M4 processors

CERN Document Server

Yiu, Joseph

2013-01-01

This book presents the background of the ARM architecture and outlines the features of the processors such as the instruction set, interrupt-handling and also demonstrates how to program and utilize the advanced features available such as the Memory Protection Unit (MPU). Chapters on getting started with IAR, Keil, gcc and CooCox CoIDE tools help beginners develop program codes.  Coverage also includes the important areas of software development such as using the low power features, handling information input/output, mixed language projects with assembly and C, and other advanced topics. Tw

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

Institute of Scientific and Technical Information of China (English)

Lou Wenfeng; Feng Peng; Wang Haiyong; Wu Nanjian

2012-01-01

A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed.The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer.An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application.This PLL is implemented in a 0.18μm technology.The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5μs over the entire frequency range.The LC-VCO with the stacked divide-by-2 has a good figure of merit of-193.5 dBc/Hz.The measured phase noise of frequency synthesizer is about -115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than -52 dBc.The whole frequency synthesizer consumes only 4.35 mA @ 1.8 V.

Initial explorations of ARM processors for scientific computing

International Nuclear Information System (INIS)

Abdurachmanov, David; Elmer, Peter; Eulisse, Giulio; Muzaffar, Shahzad

2014-01-01

Power efficiency is becoming an ever more important metric for both high performance and high throughput computing. Over the course of next decade it is expected that flops/watt will be a major driver for the evolution of computer architecture. Servers with large numbers of ARM processors, already ubiquitous in mobile computing, are a promising alternative to traditional x86-64 computing. We present the results of our initial investigations into the use of ARM processors for scientific computing applications. In particular we report the results from our work with a current generation ARMv7 development board to explore ARM-specific issues regarding the software development environment, operating system, performance benchmarks and issues for porting High Energy Physics software

Integrated fuel processor development

International Nuclear Information System (INIS)

Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

2001-01-01

The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

Embedded Control in Wearable Medical Devices: Application to the Artificial Pancreas

Directory of Open Access Journals (Sweden)

Stamatina Zavitsanou

2016-09-01

Full Text Available Significant increases in processing power, coupled with the miniaturization of processing units operating at low power levels, has motivated the embedding of modern control systems into medical devices. The design of such embedded decision-making strategies for medical applications is driven by multiple crucial factors, such as: (i guaranteed safety in the presence of exogenous disturbances and unexpected system failures; (ii constraints on computing resources; (iii portability and longevity in terms of size and power consumption; and (iv constraints on manufacturing and maintenance costs. Embedded control systems are especially compelling in the context of modern artificial pancreas systems (AP used in glucose regulation for patients with type 1 diabetes mellitus (T1DM. Herein, a review of potential embedded control strategies that can be leveraged in a fully-automated and portable AP is presented. Amongst competing controllers, emphasis is provided on model predictive control (MPC, since it has been established as a very promising control strategy for glucose regulation using the AP. Challenges involved in the design, implementation and validation of safety-critical embedded model predictive controllers for the AP application are discussed in detail. Additionally, the computational expenditure inherent to MPC strategies is investigated, and a comparative study of runtime performances and storage requirements among modern quadratic programming solvers is reported for a desktop environment and a prototype hardware platform.

Intra-Minute Cloud Passing Forecasting Based on a Low Cost IoT Sensor—A Solution for Smoothing the Output Power of PV Power Plants

Science.gov (United States)

Sukič, Primož; Štumberger, Gorazd

2017-01-01

Clouds moving at a high speed in front of the Sun can cause step changes in the output power of photovoltaic (PV) power plants, which can lead to voltage fluctuations and stability problems in the connected electricity networks. These effects can be reduced effectively by proper short-term cloud passing forecasting and suitable PV power plant output power control. This paper proposes a low-cost Internet of Things (IoT)-based solution for intra-minute cloud passing forecasting. The hardware consists of a Raspberry PI Model B 3 with a WiFi connection and an OmniVision OV5647 sensor with a mounted wide-angle lens, a circular polarizing (CPL) filter and a natural density (ND) filter. The completely new algorithm for cloud passing forecasting uses the green and blue colors in the photo to determine the position of the Sun, to recognize the clouds, and to predict their movement. The image processing is performed in several stages, considering selectively only a small part of the photo relevant to the movement of the clouds in the vicinity of the Sun in the next minute. The proposed algorithm is compact, fast and suitable for implementation on low cost processors with low computation power. The speed of the cloud parts closest to the Sun is used to predict when the clouds will cover the Sun. WiFi communication is used to transmit this data to the PV power plant control system in order to decrease the output power slowly and smoothly. PMID:28505078

Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems

Directory of Open Access Journals (Sweden)

Josu Etxaniz

2017-04-01

Full Text Available Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks.

Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems

Science.gov (United States)

Etxaniz, Josu; Aranguren, Gerardo

2017-01-01

Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS) metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks. PMID:28468294

Bluetooth Low Power Modes Applied to the Data Transportation Network in Home Automation Systems.

Science.gov (United States)

Etxaniz, Josu; Aranguren, Gerardo

2017-04-30

Even though home automation is a well-known research and development area, recent technological improvements in different areas such as context recognition, sensing, wireless communications or embedded systems have boosted wireless smart homes. This paper focuses on some of those areas related to home automation. The paper draws attention to wireless communications issues on embedded systems. Specifically, the paper discusses the multi-hop networking together with Bluetooth technology and latency, as a quality of service (QoS) metric. Bluetooth is a worldwide standard that provides low power multi-hop networking. It is a radio license free technology and establishes point-to-point and point-to-multipoint links, known as piconets, or multi-hop networks, known as scatternets. This way, many Bluetooth nodes can be interconnected to deploy ambient intelligent networks. This paper introduces the research on multi-hop latency done with park and sniff low power modes of Bluetooth over the test platform developed. Besides, an empirical model is obtained to calculate the latency of Bluetooth multi-hop communications over asynchronous links when links in scatternets are always in sniff or the park mode. Smart home devices and networks designers would take advantage of the models and the estimation of the delay they provide in communications along Bluetooth multi-hop networks.

Review of trigger and on-line processors at SLAC

International Nuclear Information System (INIS)

Lankford, A.J.

1984-07-01

The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

Integrating an Embedded System within a Microwave Moisture Meter

Science.gov (United States)

In this paper, the conversion of a PC or laptop-controlled microwave moisture meter to a stand-alone meter hosting its own embedded system is discussed. The moisture meter uses low-power microwaves to measure the attenuation and phase shift of the sample, from which the dielectric properties are cal...

Evaluation of the Intel Westmere-EX server processor

CERN Document Server

Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

2011-01-01

One year after the arrival of the Intel Xeon 7500 systems (“Nehalem-EX”), CERN openlab is presenting a set of benchmark results obtained when running on the new Xeon E7-4870 Processors, representing the “Westmere-EX” family. A modern 4-socket, 40-core system is confronted with the previous generation of expandable (“EX”) platforms, represented by a 4-socket, 32-core Intel Xeon X7560 based system – both being “top of the line” systems. Benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Symmetric MultiThreading (SMT), the cache sizes available, the configured memory topology, as well as the power configuration if throughput per watt is to be measured. As in previous activities, we have tried to do a good job of comparing like with like. In a “top of the line” comparison based on the HEPSPEC06 benchmark, the “We...

3081/E processor and its on-line use

International Nuclear Information System (INIS)

Rankin, P.; Bricaud, B.; Gravina, M.

1985-05-01

The 3081/E is a second generation emulator of a mainframe IBM. One of it's applications will be to form part of the data acquisition system of the upgraded Mark II detector for data taking at the SLAC linear collider. Since the processor does not have direct connections to I/O devices a FASTBUS interface will be provided to allow communication with both SLAC Scanner Processors (which are responsible for the accumulation of data at a crate level) and the experiment's VAX 8600 mainframe. The 3081/E's will supply a significant amount of on-line computing power to the experiment (a single 3081/E is equivalent to 4 to 5 VAX 11/780's). A major advantage of the 3081/E is that program development can be done on an IBM mainframe (such as the one used for off-line analysis) which gives the programmer access to a full range of debugging tools. The processor's performance can be continually monitored by comparison of the results obtained using it to those given when the same program is run on an IBM computer. 9 refs

Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

Science.gov (United States)

Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

2017-11-01

Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

The Serial Link Processor for the Fast TracKer (FTK) at ATLAS

CERN Document Server

Annovi, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Biesuz, N; Billereau, W; Combe, J M; Citterio, M; Citraro, S; Crescioli, F; Dimas, D; Donati, S; Gentsos, C; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Rossi, E; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A; Vulliez, P

2014-01-01

The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problem inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report also on the performance of a first prototype based on the use of a min@sic AM chip, a small but complete version ...

The Molen Polymorphic Media Processor

NARCIS (Netherlands)

Kuzmanov, G.K.

2004-01-01

In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks

Directory of Open Access Journals (Sweden)

Luis Parrilla

2018-01-01

Full Text Available Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks

Science.gov (United States)

Castillo, Encarnación; López-Ramos, Juan A.; Morales, Diego P.

2018-01-01

Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature. PMID:29337921

Unified Compact ECC-AES Co-Processor with Group-Key Support for IoT Devices in Wireless Sensor Networks.

Science.gov (United States)

Parrilla, Luis; Castillo, Encarnación; López-Ramos, Juan A; Álvarez-Bermejo, José A; García, Antonio; Morales, Diego P

2018-01-16

Security is a critical challenge for the effective expansion of all new emerging applications in the Internet of Things paradigm. Therefore, it is necessary to define and implement different mechanisms for guaranteeing security and privacy of data interchanged within the multiple wireless sensor networks being part of the Internet of Things. However, in this context, low power and low area are required, limiting the resources available for security and thus hindering the implementation of adequate security protocols. Group keys can save resources and communications bandwidth, but should be combined with public key cryptography to be really secure. In this paper, a compact and unified co-processor for enabling Elliptic Curve Cryptography along to Advanced Encryption Standard with low area requirements and Group-Key support is presented. The designed co-processor allows securing wireless sensor networks with independence of the communications protocols used. With an area occupancy of only 2101 LUTs over Spartan 6 devices from Xilinx, it requires 15% less area while achieving near 490% better performance when compared to cryptoprocessors with similar features in the literature.

Adaptive Motion Estimation Processor for Autonomous Video Devices

Directory of Open Access Journals (Sweden)

Dias T

2007-01-01

Full Text Available Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. As a consequence, with the proliferation of autonomous and portable handheld devices that support digital video coding, data-adaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an application-specific instruction set processor (ASIP to implement data-adaptive motion estimation algorithms that is characterized by a specialized datapath and a minimum and optimized instruction set. Due to its low-power nature, this architecture is highly suitable to develop motion estimators for portable, mobile, and battery-supplied devices. Based on the proposed architecture and the considered adaptive algorithms, several motion estimators were synthesized both for a Virtex-II Pro XC2VP30 FPGA from Xilinx, integrated within an ML310 development platform, and using a StdCell library based on a 0.18 μm CMOS process. Experimental results show that the proposed architecture is able to estimate motion vectors in real time for QCIF and CIF video sequences with a very low-power consumption. Moreover, it is also able to adapt the operation to the available energy level in runtime. By adjusting the search pattern and setting up a more convenient operating frequency, it can change the power consumption in the interval between 1.6 mW and 15 mW.

Multi-processor developments in the United States for future high energy physics experiments and accelerators

International Nuclear Information System (INIS)

Gaines, I.

1988-03-01

The use of multi-processors for analysis and high-level triggering in High Energy Physics experiments, pioneered by the early emulator systems, has reached maturity, in particular with the multiple microprocessor systems in use at Fermilab. It is widely acknowledged that such systems will fulfill the major portion of the computing needs of future large experiments. Recent developments at Fermilab's Advanced Computer Program will make such systems even more powerful, cost-effective, and easier to use than they are at present. The next generation of microprocessors, already available, will provide CPU power of about one VAX 780 equivalent/$300, while supporting most VMS FORTRAN extensions and large (>8MB) amounts of memory. Low cost high density mass storage devices (based on video tape cartridge technology) will allow parallel I/O to remove potential I/O bottlenecks in systems of over 1000 VAX equipment processors. New interconnection schemes and system software will allow more flexible topologies and extremely high data bandwidth, especially for on-line systems. This talk will summarize the work at the Advanced Computer Program and the rest of the US in this field. 3 refs., 4 figs

Error detection and prevention in Embedded Systems Software

DEFF Research Database (Denmark)

Kamel, Hani Fouad

1996-01-01

Despite many efforts to structure the development and design processes of embedded systems, errors are discovered at the final stages of production and sometimes after the delivery of the products. The cost of such errors can be prohibitive.Different design techniques to detect such errors...... systems, a formal model for such systems is introduced. The main characteristics of embedded systems design and the interaction of these properties are described. A taxonomy for the structure of the software developed for such systems based on the amount of processes and processors involved is presented.......The second part includes methods and techniques to detect software design errors.The third part deals with error prevention. It starts with a presentation of different models of the development processes used in industry and taught at universities. This leads us to deduce the major causes of errors...

A low-power bidirectional telemetry device with a near-field charging feature for a cardiac microstimulator.

Science.gov (United States)

Shuenn-Yuh Lee; Chih-Jen Cheng; Ming-Chun Liang

2011-08-01

In this paper, wireless telemetry using the near-field coupling technique with round-wire coils for an implanted cardiac microstimulator is presented. The proposed system possesses an external powering amplifier and an internal bidirectional microstimulator. The energy of the microstimulator is provided by a rectifier that can efficiently charge a rechargeable device. A fully integrated regulator and a charge pump circuit are included to generate a stable, low-voltage, and high-potential supply voltage, respectively. A miniature digital processor includes a phase-shift-keying (PSK) demodulator to decode the transmission data and a self-protective system controller to operate the entire system. To acquire the cardiac signal, a low-voltage and low-power monitoring analog front end (MAFE) performs immediate threshold detection and data conversion. In addition, the pacing circuit, which consists of a pulse generator (PG) and its digital-to-analog (D/A) controller, is responsible for stimulating heart tissue. The chip was fabricated by Taiwan Semiconductor Manufacturing Company (TSMC) with 0.35-μm complementary metal-oxide semiconductor technology to perform the monitoring and pacing functions with inductively powered communication. Using a model with lead and heart tissue on measurement, a -5-V pulse at a stimulating frequency of 60 beats per minute (bpm) is delivered while only consuming 31.5 μW of power.

Biological Water Processor and Forward Osmosis Secondary Treatment

Science.gov (United States)

Shull, Sarah; Meyer, Caitlin

2014-01-01

The goal of the Biological Water Processor (BWP) is to remove 90% organic carbon and 75% ammonium from an exploration-based wastewater stream for four crew members. The innovative design saves on space, power and consumables as compared to the ISS Urine Processor Assembly (UPA) by utilizing microbes in a biofilm. The attached-growth system utilizes simultaneous nitrification and denitrification to mineralize organic carbon and ammonium to carbon dioxide and nitrogen gas, which can be scrubbed in a cabin air revitalization system. The BWP uses a four-crew wastewater comprised of urine and humidity condensate, as on the ISS, but also includes hygiene (shower, shave, hand washing and oral hygiene) and laundry. The BWP team donates 58L per day of this wastewater processed in Building 7.

The associative memory system for the FTK processor at ATLAS

CERN Document Server

Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

2014-01-01

In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

Field tests on partial embedment effects (embedment effect tests on soil-structure interaction)

International Nuclear Information System (INIS)

Kurimoto, O.; Tsunoda, T.; Inoue, T.; Izumi, M.; Kusakabe, K.; Akino, K.

1993-01-01

A series of Model Tests of Embedment Effect on Reactor Buildings has been carried out by the Nuclear Power Engineering Corporation (NUPEC), under the sponsorship of the Ministry of International Trade and lndustry (MITI) of Japan. The nuclear reactor buildings are partially embedded due to conditions for the construction or building arrangement in Japan. It is necessary to verify the partial embedment effects by experiments and analytical studies in order to incorporate the effects in the seismic design. Forced vibration tests, therefore, were performed using a model with several types of embedment. Correlated simulation analyses were also performed and the characteristics of partial embedment effects on soil-structure interaction were evaluated. (author)

Analysis and optimization of fault-tolerant embedded systems with hardened processors

DEFF Research Database (Denmark)

Izosimov, Viacheslav; Polian, Ilia; Pop, Paul

2009-01-01

In this paper we propose an approach to the design optimization of fault-tolerant hard real-time embedded systems, which combines hardware and software fault tolerance techniques. We trade-off between selective hardening in hardware and process reexecution in software to provide the required levels...... of fault tolerance against transient faults with the lowest-possible system costs. We propose a system failure probability (SFP) analysis that connects the hardening level with the maximum number of reexecutions in software. We present design optimization heuristics, to select the fault......-tolerant architecture and decide process mapping such that the system cost is minimized, deadlines are satisfied, and the reliability requirements are fulfilled....

Real-time multiple objects tracking on Raspberry-Pi-based smart embedded camera

Science.gov (United States)

Dziri, Aziz; Duranton, Marc; Chapuis, Roland

2016-07-01

Multiple-object tracking constitutes a major step in several computer vision applications, such as surveillance, advanced driver assistance systems, and automatic traffic monitoring. Because of the number of cameras used to cover a large area, these applications are constrained by the cost of each node, the power consumption, the robustness of the tracking, the processing time, and the ease of deployment of the system. To meet these challenges, the use of low-power and low-cost embedded vision platforms to achieve reliable tracking becomes essential in networks of cameras. We propose a tracking pipeline that is designed for fixed smart cameras and which can handle occlusions between objects. We show that the proposed pipeline reaches real-time processing on a low-cost embedded smart camera composed of a Raspberry-Pi board and a RaspiCam camera. The tracking quality and the processing speed obtained with the proposed pipeline are evaluated on publicly available datasets and compared to the state-of-the-art methods.

Wireless powering for low-power distributed sensors

Directory of Open Access Journals (Sweden)

Popović Zoya B.

2006-01-01

Full Text Available In this paper, an overview of the field of wireless powering is presented with an emphasis on low-power applications. Several rectenna elements and arrays are discussed in more detail: (1 a 10-GHz array for powering sensors in aircraft wings; (2 a single antenna in the 2.4-GHz ISM band for low-power assisted-living sensors; and (3 a broadband array for power harvesting in the 2-18GHz frequency range.

Protein extraction from methanol fixed paraffin embedded tissue blocks: A new possibility using cell blocks

Science.gov (United States)

Kokkat, Theresa J.; McGarvey, Diane; Patel, Miral S.; Tieniber, Andrew D.; LiVolsi, Virginia A.; Baloch, Zubair W.

2013-01-01

Background: Methanol fixed and paraffin embedded (MFPE) cellblocks are an essential cytology preparation. However, MFPE cellblocks often contain limited material and their relatively small size has caused them to be overlooked in biomarker discovery. Advances in the field of molecular biotechnology have made it possible to extract proteins from formalin fixed and paraffin embedded (FFPE) tissue blocks. In contrast, there are no established methods for extracting proteins from MFPE cellblocks. We investigated commonly available CHAPS (3-[(3-cholamidopropyl) dimethylammonio]-1-propanesulfonate) buffer, as well as two commercially available Qiagen® kits and compared their effectiveness on MFPE tissue for protein yields. Materials and Methods: MFPE blocks were made by Cellient™ automated system using human tissue specimens from normal and malignant specimens collected in ThinPrep™ Vials. Protein was extracted from Cellient-methanol fixed and paraffin embedded blocks with CHAPS buffer method as well as FFPE and Mammalian Qiagen® kits. Results: Comparison of protein yields demonstrated the effectiveness of various protein extraction methods on MFPE cellblocks. Conclusion: In the current era of minimally invasive techniques to obtain minimal amount of tissue for diagnostic and prognostic purposes, the use of commercial and lab made buffer on low weight MFPE scrapings obtained by Cellient® processor opens new possibilities for protein biomarker research. PMID:24403950

35-We polymer electrolyte membrane fuel cell system for notebook computer using a compact fuel processor

Science.gov (United States)

Son, In-Hyuk; Shin, Woo-Cheol; Lee, Yong-Kul; Lee, Sung-Chul; Ahn, Jin-Gu; Han, Sang-Il; kweon, Ho-Jin; Kim, Ju-Yong; Kim, Moon-Chan; Park, Jun-Yong

A polymer electrolyte membrane fuel cell (PEMFC) system is developed to power a notebook computer. The system consists of a compact methanol-reforming system with a CO preferential oxidation unit, a 16-cell PEMFC stack, and a control unit for the management of the system with a d.c.-d.c. converter. The compact fuel-processor system (260 cm 3) generates about 1.2 L min -1 of reformate, which corresponds to 35 We, with a low CO concentration (notebook computers.

JPP: A Java Pre-Processor

OpenAIRE

Kiniry, Joseph R.; Cheong, Elaine

1998-01-01

The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer

International Nuclear Information System (INIS)

Lou Wenfeng; Feng Peng; Wang Haiyong; Wu Nanjian

2012-01-01

A low power fast settling multi-standard CMOS fractional-N frequency synthesizer is proposed. The current reusing and frequency presetting techniques are adopted to realize the low power fast settling multi-standard fractional-N frequency synthesizer. An auxiliary non-volatile memory (NVM) is embedded to avoid the repetitive calibration process and to save power in practical application. This PLL is implemented in a 0.18 μm technology. The frequency range is 0.3 to 2.54 GHz and the settling time is less than 5 μs over the entire frequency range. The LC-VCO with the stacked divide-by-2 has a good figure of merit of −193.5 dBc/Hz. The measured phase noise of frequency synthesizer is about −115 dBc/Hz at 1 MHz offset when the carrier frequency is 2.4 GHz and the reference spurs are less than −52 dBc. The whole frequency synthesizer consumes only 4.35 mA and 1.8 V. (semiconductor integrated circuits)

Parallel processors and nonlinear structural dynamics algorithms and software

Science.gov (United States)

Belytschko, Ted

1989-01-01

A nonlinear structural dynamics finite element program was developed to run on a shared memory multiprocessor with pipeline processors. The program, WHAMS, was used as a framework for this work. The program employs explicit time integration and has the capability to handle both the nonlinear material behavior and large displacement response of 3-D structures. The elasto-plastic material model uses an isotropic strain hardening law which is input as a piecewise linear function. Geometric nonlinearities are handled by a corotational formulation in which a coordinate system is embedded at the integration point of each element. Currently, the program has an element library consisting of a beam element based on Euler-Bernoulli theory and trianglar and quadrilateral plate element based on Mindlin theory.

Efficient Algorithm and Architecture of Critical-Band Transform for Low-Power Speech Applications

Directory of Open Access Journals (Sweden)

Gan Woon-Seng

2007-01-01

Full Text Available An efficient algorithm and its corresponding VLSI architecture for the critical-band transform (CBT are developed to approximate the critical-band filtering of the human ear. The CBT consists of a constant-bandwidth transform in the lower frequency range and a Brown constant- transform (CQT in the higher frequency range. The corresponding VLSI architecture is proposed to achieve significant power efficiency by reducing the computational complexity, using pipeline and parallel processing, and applying the supply voltage scaling technique. A 21-band Bark scale CBT processor with a sampling rate of 16 kHz is designed and simulated. Simulation results verify its suitability for performing short-time spectral analysis on speech. It has a better fitting on the human ear critical-band analysis, significantly fewer computations, and therefore is more energy-efficient than other methods. With a 0.35 m CMOS technology, it calculates a 160-point speech in 4.99 milliseconds at 234 kHz. The power dissipation is 15.6 W at 1.1 V. It achieves 82.1 power reduction as compared to a benchmark 256-point FFT processor.

Producing chopped firewood with firewood processors

International Nuclear Information System (INIS)

Kaerhae, K.; Jouhiaho, A.

2009-01-01

The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

Green computing: power optimisation of vfi-based real-time multiprocessor dataflow applications

NARCIS (Netherlands)

Ahmad, W.; Holzenspies, P.K.F.; Stoelinga, Mariëlle Ida Antoinette; van de Pol, Jan Cornelis

2015-01-01

Execution time is no longer the only performance metric for computer systems. In fact, a trend is emerging to trade raw performance for energy savings. Techniques like Dynamic Power Management (DPM, switching to low power state) and Dynamic Voltage and Frequency Scaling (DVFS, throttling processor

Piezoelectric energy harvesting for powering low power electronics

Energy Technology Data Exchange (ETDEWEB)

Leinonen, M.; Palosaari, J.; Hannu, J.; Juuti, J.; Jantunen, H. (Univ. of Oulu, Dept. of Electrical and Information Engineering (Finland)). email: jajuu@ee.oulu.fi

2009-07-01

Although wireless data transmission techniques are commonly used in electronic devices, they still suffer from wires for the power supply or from batteries which require charging, replacement and other maintenance. The vision for the portable electronics and industrial measurement systems of the future is that they are intelligent and independent on their energy supply. The major obstacle in this path is the energy source which enables all other functions and 'smartness' of the systems as the computing power is also restricted by the available energy. The development of long-life energy harvesters would reduce the need for batteries and wires thus enabling cost-effective and environment friendlier solutions for various applications such as autonomous wireless sensor networks, powering of portable electronics and other maintenance-free systems. One of the most promising techniques is mechanical energy harvesting e.g. by piezoelectric components where deformations produced by different means is directly converted to electrical charge via direct piezoelectric effect. Subsequently the electrical energy can be regulated or stored for further use. The total mechanical energy in vibration of machines can be very large and usually only a fraction of it can be transformed to electrical energy. Recently, piezoelectric vibration based energy harvesters have been developed widely for different energy consumption and application areas. As an example for low energy device an piezoelectric energy harvester based on impulse type excitations has been developed for active RFID identification. Moreover, piezoharvester with externally leveraged mechanism for force amplification was reported to be able to generate mean power of 0.4 mW from backpack movement. Significantly higher power levels are expected from larger scale testing in Israel, where piezoelectric material is embedded under active walking street, road, airport or railroad. The energy is harvested from human or

The processor farm for online triggering and full event reconstruction of the HERA-B experiment at HERA

International Nuclear Information System (INIS)

Gellrich, A.; Dippel, R.; Gensch, U.; Kowallik, R.; Legrand, I.C.; Leich, H.; Sun, F.; Wegner, P.

1996-01-01

The main goal of the HERA-B experiment which start taking data in 1988 is to study CP violation in B decays. This article describes the concept and the planned implementation of a multi-processor system, called processor farm,as the last part of the data acquisition and trigger system of the HERA B experiment. The third level trigger task and a full online event reconstruction will be performed on this processor farm, consisting of more then 100 powerful RISC processors which are based on commercial hardware boards. The controlling will be done by a real-time operating system which provides a software development environment, including FORTRAN and C compilers. (author)

Real-time data exchange of power supply digital adjustor of HIRFL-CSR

International Nuclear Information System (INIS)

Zeng Xianqiang; Jing Lan; Guo Yuhui; Yao Ze'en; Long Yindong

2012-01-01

In order to solve the communications blockage problem of the power supply digital adjustors in Lanzhou Heavy Ion Accelerator CSR, a new system architecture is adopted, P2P technology is embedded to the core processor ARM of the digital adjustor. Based on the technology of UDP holing, a direct communication connect is established between the adjustors, thus the data are no longer forwarded by the main Oracle database system acting as a server. This method decentralizes the communication responsibility of Oracle database system, the risk of network block is reduced, and the effectiveness and reliability of communication is improved. (authors)

Low power constant fraction discriminator

International Nuclear Information System (INIS)

Krishnan, Shanti; Raut, S.M.; Mukhopadhyay, P.K.

2001-01-01

This paper describes the design of a low power ultrafast constant fraction discriminator, which significantly reduces the power consumption. A conventional fast discriminator consumes about 1250 MW of power whereas this low power version consumes about 440 MW. In a multi detector system, where the number of discriminators is very large, reduction of power is of utmost importance. This low power discriminator is being designed for GRACE (Gamma Ray Atmospheric Cerenkov Experiments) telescope where 1000 channels of discriminators are required. A novel method of decreasing power consumption has been described. (author)

Optical Associative Processors For Visual Perception"

Science.gov (United States)

Casasent, David; Telfer, Brian

1988-05-01

We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

OSCAR API for Real-Time Low-Power Multicores and Its Performance on Multicores and SMP Servers

Science.gov (United States)

Kimura, Keiji; Mase, Masayoshi; Mikami, Hiroki; Miyamoto, Takamichi; Shirako, Jun; Kasahara, Hironori

OSCAR (Optimally Scheduled Advanced Multiprocessor) API has been designed for real-time embedded low-power multicores to generate parallel programs for various multicores from different vendors by using the OSCAR parallelizing compiler. The OSCAR API has been developed by Waseda University in collaboration with Fujitsu Laboratory, Hitachi, NEC, Panasonic, Renesas Technology, and Toshiba in an METI/NEDO project entitled "Multicore Technology for Realtime Consumer Electronics." By using the OSCAR API as an interface between the OSCAR compiler and backend compilers, the OSCAR compiler enables hierarchical multigrain parallel processing with memory optimization under capacity restriction for cache memory, local memory, distributed shared memory, and on-chip/off-chip shared memory; data transfer using a DMA controller; and power reduction control using DVFS (Dynamic Voltage and Frequency Scaling), clock gating, and power gating for various embedded multicores. In addition, a parallelized program automatically generated by the OSCAR compiler with OSCAR API can be compiled by the ordinary OpenMP compilers since the OSCAR API is designed on a subset of the OpenMP. This paper describes the OSCAR API and its compatibility with the OSCAR compiler by showing code examples. Performance evaluations of the OSCAR compiler and the OSCAR API are carried out using an IBM Power5+ workstation, an IBM Power6 high-end SMP server, and a newly developed consumer electronics multicore chip RP2 by Renesas, Hitachi and Waseda. From the results of scalability evaluation, it is found that on an average, the OSCAR compiler with the OSCAR API can exploit 5.8 times speedup over the sequential execution on the Power5+ workstation with eight cores and 2.9 times speedup on RP2 with four cores, respectively. In addition, the OSCAR compiler can accelerate an IBM XL Fortran compiler up to 3.3 times on the Power6 SMP server. Due to low-power optimization on RP2, the OSCAR compiler with the OSCAR API

AMD's 64-bit Opteron processor

CERN Multimedia

CERN. Geneva

2003-01-01

This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

Improving RF Transmit Power and Received Signal Strength in 2.4 GHz ZigBee Based Active RFID System with Embedded Method

Science.gov (United States)

Po'ad, F. A.; Ismail, W.; Jusoh, J. F.

2017-08-01

This paper describes the experiments and analysis conducted on 2.4 GHz embedded active Radio Frequency Identification (RFID) - Wireless Sensor Network (WSN) based system that has been developed for the purposes of location tracking and monitoring in indoor and outdoor environments. Several experiments are conducted to test the effectiveness and performance of the developed system and two of them is by measuring the Radio Frequency (RF) transmitting power and Received Signal Strength (RSS) to prove that the embedded active RFID tag is capable to generate higher transmit power during data transmission and able to provide better RSS reading compared to standalone RFID tag. Experiments are carried out on two RFID tags which are active RFID tag embedded with GPS and GSM (ER2G); and standalone RFID tag communicating with the same active RFID reader. The developed ER2G contributes 12.26 % transmit power and 6.47 % RSS reading higher than standalone RFID tag. The results conclude that the ER2G gives better performance compared to standalone RFID tag and can be used as guidelines for future design improvements.

The micro-processor controlled process radiation monitoring system for reactor safety systems

International Nuclear Information System (INIS)

Mizuno, K.; Noguchi, A.; Kumagami, S.; Gotoh, Y.; Kumahara, T.; Arita, S.

1986-01-01

Digital computers are soon expected to be applied to various real-time safety and safety-related systems in nuclear power plants. Hitachi is now engaged in the development of a micro-processor controlled process radiation monitoring system, which operates on digital processing methods employed with a log ratemeter. A newly defined methodology of design and test procedures is being applied as a means of software program verification for these safety systems. Recently implemented micro-processor technology will help to achieve an advanced man-machine interface and highly reliable performance. (author)

Design of signal reception and processing system of embedded ultrasonic endoscope

Science.gov (United States)

Li, Ming; Yu, Feng; Zhang, Ruiqiang; Li, Yan; Chen, Xiaodong; Yu, Daoyin

2009-11-01

Embedded Ultrasonic Endoscope, based on embedded microprocessor and embedded real-time operating system, sends a micro ultrasonic probe into coelom through the biopsy channel of the Electronic Endoscope to get the fault histology features of digestive organs by rotary scanning, and acquires the pictures of the alimentary canal mucosal surface. At the same time, ultrasonic signals are processed by signal reception and processing system, forming images of the full histology of the digestive organs. Signal Reception and Processing System is an important component of Embedded Ultrasonic Endoscope. However, the traditional design, using multi-level amplifiers and special digital processing circuits to implement signal reception and processing, is no longer satisfying the standards of high-performance, miniaturization and low power requirements that embedded system requires, and as a result of the high noise that multi-level amplifier brought, the extraction of small signal becomes hard. Therefore, this paper presents a method of signal reception and processing based on double variable gain amplifier and FPGA, increasing the flexibility and dynamic range of the Signal Reception and Processing System, improving system noise level, and reducing power consumption. Finally, we set up the embedded experiment system, using a transducer with the center frequency of 8MHz to scan membrane samples, and display the image of ultrasonic echo reflected by each layer of membrane, with a frame rate of 5Hz, verifying the correctness of the system.

Color sensor and neural processor on one chip

Science.gov (United States)

Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

1998-10-01

Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

SVM classifier on chip for melanoma detection.

Science.gov (United States)

Afifi, Shereen; GholamHosseini, Hamid; Sinha, Roopak

2017-07-01

Support Vector Machine (SVM) is a common classifier used for efficient classification with high accuracy. SVM shows high accuracy for classifying melanoma (skin cancer) clinical images within computer-aided diagnosis systems used by skin cancer specialists to detect melanoma early and save lives. We aim to develop a medical low-cost handheld device that runs a real-time embedded SVM-based diagnosis system for use in primary care for early detection of melanoma. In this paper, an optimized SVM classifier is implemented onto a recent FPGA platform using the latest design methodology to be embedded into the proposed device for realizing online efficient melanoma detection on a single system on chip/device. The hardware implementation results demonstrate a high classification accuracy of 97.9% and a significant acceleration factor of 26 from equivalent software implementation on an embedded processor, with 34% of resources utilization and 2 watts for power consumption. Consequently, the implemented system meets crucial embedded systems constraints of high performance and low cost, resources utilization and power consumption, while achieving high classification accuracy.

Deterministic chaos in the processor load

International Nuclear Information System (INIS)

Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

2007-01-01

In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

Efficacy of Code Optimization on Cache-Based Processors

Science.gov (United States)

VanderWijngaart, Rob F.; Saphir, William C.; Chancellor, Marisa K. (Technical Monitor)

1997-01-01

In this paper a number of techniques for improving the cache performance of a representative piece of numerical software is presented. Target machines are popular processors from several vendors: MIPS R5000 (SGI Indy), MIPS R8000 (SGI PowerChallenge), MIPS R10000 (SGI Origin), DEC Alpha EV4 + EV5 (Cray T3D & T3E), IBM RS6000 (SP Wide-node), Intel PentiumPro (Ames' Whitney), Sun UltraSparc (NERSC's NOW). The optimizations all attempt to increase the locality of memory accesses. But they meet with rather varied and often counterintuitive success on the different computing platforms. We conclude that it may be genuinely impossible to obtain portable performance on the current generation of cache-based machines. At the least, it appears that the performance of modern commodity processors cannot be described with parameters defining the cache alone.

Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade

International Nuclear Information System (INIS)

Alberti, F; Citterio, M; Liberali, V; Meroni, C; Andreani, A; Stabile, A; Annovi, A; Beretta, M; Crescioli, F; Dell'Orso, M; Piendibene, M; Volpi, G; Giannetti, P; Lanza, A; Magalotti, D; Sacco, I

2013-01-01

Modern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04.

Thermal Dissipation Efficiency in a Micro-Processor Using Carbon Nanotubes Based Composite

Science.gov (United States)

Thang, Bui Hung; Van Quang, Cao; Nghia, Van Trong; Hong, Phan Ngoc; Van Chuc, Nguyen; Tam, Ngo Thi Thanh; Quang, Le Dinh; Khang, Dao Duc; Khoi, Phan Hong; Minh, Phan Ngoc

2009-09-01

Modern electronic and optoelectronic devices such as μ-processor, light emitting diode, semiconductor laser issued a challenge in the thermal dissipation problem. Finding an effective way for thermal dissipation therefore becomes a very important issue. It is known that carbon nanotubes (CNTs) is one of the most valuable materials with high thermal conductivity (2000 W/m.K compared to thermal conductivity of Ag 419 W/m.K). This suggested an approach in applying the CNTs as an essential component for thermal dissipation media to improve the performance of computer processor and other high power electronic devices. In this work multi walled carbon nanotubes (MWCNTs) based composites were utilized as the thermal dissipation media in a micro processor of a personal computer. The MWCNTs of different concentrations were added into polyaniline, commercial silicon thermal paste and commercial silver thermal paste by mechanical methods. A personal computer with configuration: Intel Pentium IV 3.066 GHz, 512 MB of RAM and Windows XP Service Pack 2 Operating System was employed. The thermal dissipation efficiency of the system was evaluated by directly measure the temperature of the μ-processor during the operation of the computer in different CPU speeds. The measured results showed that the CNTs based composite could reduce the temperature of the u-processor more than 5° C, and the time for increasing the temperature of the μ-processor was three times longer than that when using commercial thermal paste.

Optimal design of distributed control and embedded systems

CERN Document Server

Çela, Arben; Li, Xu-Guang; Niculescu, Silviu-Iulian

2014-01-01

Optimal Design of Distributed Control and Embedded Systems focuses on the design of special control and scheduling algorithms based on system structural properties as well as on analysis of the influence of induced time-delay on systems performances. It treats the optimal design of distributed and embedded control systems (DCESs) with respect to communication and calculation-resource constraints, quantization aspects, and potential time-delays induced by the associated  communication and calculation model. Particular emphasis is put on optimal control signal scheduling based on the system state. In order to render  this complex optimization problem feasible in real time, a time decomposition is based on periodicity induced by the static scheduling is operated. The authors present a co-design approach which subsumes the synthesis of the optimal control laws and the generation of an optimal schedule of control signals on real-time networks as well as the execution of control tasks on a single processor. The a...

EOS: A project to investigate the design and construction of real-time distributed Embedded Operating Systems

Science.gov (United States)

Campbell, R. H.; Essick, Ray B.; Johnston, Gary; Kenny, Kevin; Russo, Vince

1987-01-01

Project EOS is studying the problems of building adaptable real-time embedded operating systems for the scientific missions of NASA. Choices (A Class Hierarchical Open Interface for Custom Embedded Systems) is an operating system designed and built by Project EOS to address the following specific issues: the software architecture for adaptable embedded parallel operating systems, the achievement of high-performance and real-time operation, the simplification of interprocess communications, the isolation of operating system mechanisms from one another, and the separation of mechanisms from policy decisions. Choices is written in C++ and runs on a ten processor Encore Multimax. The system is intended for use in constructing specialized computer applications and research on advanced operating system features including fault tolerance and parallelism.

Fabrication of silicon-embedded low resistance high-aspect ratio planar copper microcoils

Science.gov (United States)

Syed Mohammed, Zishan Ali; Puiu, Poenar Daniel; Aditya, Sheel

2018-01-01

Low resistance is an important requirement for microcoils which act as a signal receiver to ensure low thermal noise during signal detection. High-aspect ratio (HAR) planar microcoils entrenched in blind silicon trenches have features that make them more attractive than their traditional counterparts employing electroplating through a patterned thick polymer or achieved through silicon vias. However, challenges met in fabrication of such coils have not been discussed in detail until now. This paper reports the realization of such HAR microcoils embedded in Si blind trenches, fabricated with a single lithography step by first etching blind trenches in the silicon substrate with an aspect ratio of almost 3∶1 and then filling them up using copper electroplating. The electroplating was followed by chemical wet etching as a faster way of removing excess copper than traditional chemical mechanical polishing. Electrical resistance was further reduced by annealing the microcoils. The process steps and challenges faced in the realization of such structures are reported here followed by their electrical characterization. The obtained electrical resistances are then compared with those of other similar microcoils embedded in blind vias.

Local Buyer Market Power and Horizontally Differentiated Manufacturers

OpenAIRE

Wang, Shinn-Shyr; Rojas, Christian; Lavoie, Nathalie

2010-01-01

In this paper we study a farmer-processor relationship, where market power is bidirectional: processors have buyer as well as seller market power. Farmers supply a homogeneous raw input to the processors, which, in turn, process it into a horizontally differentiated product. The analysis shows that the spread between prices that both parties receive can be decomposed into two components: one due to buyer market power in the agricultural input market and one due to seller market power in the d...

Neurovision processor for designing intelligent sensors

Science.gov (United States)

Gupta, Madan M.; Knopf, George K.

1992-03-01

A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

Ultra-low power high precision magnetotelluric receiver array based customized computer and wireless sensor network

Science.gov (United States)

Chen, R.; Xi, X.; Zhao, X.; He, L.; Yao, H.; Shen, R.

2016-12-01

Dense 3D magnetotelluric (MT) data acquisition owns the benefit of suppressing the static shift and topography effect, can achieve high precision and high resolution inversion for underground structure. This method may play an important role in mineral exploration, geothermal resources exploration, and hydrocarbon exploration. It's necessary to reduce the power consumption greatly of a MT signal receiver for large-scale 3D MT data acquisition while using sensor network to monitor data quality of deployed MT receivers. We adopted a series of technologies to realized above goal. At first, we designed an low-power embedded computer which can couple with other parts of MT receiver tightly and support wireless sensor network. The power consumption of our embedded computer is less than 1 watt. Then we designed 4-channel data acquisition subsystem which supports 24-bit analog-digital conversion, GPS synchronization, and real-time digital signal processing. Furthermore, we developed the power supply and power management subsystem for MT receiver. At last, a series of software, which support data acquisition, calibration, wireless sensor network, and testing, were developed. The software which runs on personal computer can monitor and control over 100 MT receivers on the field for data acquisition and quality control. The total power consumption of the receiver is about 2 watts at full operation. The standby power consumption is less than 0.1 watt. Our testing showed that the MT receiver can acquire good quality data at ground with electrical dipole length as 3 m. Over 100 MT receivers were made and used for large-scale geothermal exploration in China with great success.

Four-body correlation embedded in antisymmetrized geminal power wave function.

Science.gov (United States)

Kawasaki, Airi; Sugino, Osamu

2016-12-28

We extend the Coleman's antisymmetrized geminal power (AGP) to develop a wave function theory that can incorporate up to four-body correlation in a region of strong correlation. To facilitate the variational determination of the wave function, the total energy is rewritten in terms of the traces of geminals. This novel trace formula is applied to a simple model system consisting of one dimensional Hubbard ring with a site of strong correlation. Our scheme significantly improves the result obtained by the AGP-configuration interaction scheme of Uemura et al. and also achieves more efficient compression of the degrees of freedom of the wave function. We regard the result as a step toward a first-principles wave function theory for a strongly correlated point defect or adsorbate embedded in an AGP-based mean-field medium.

Scalable and near-optimal design space exploration for embedded systems

CERN Document Server

Kritikakou, Angeliki; Goutis, Costas

2014-01-01

This book describes scalable and near-optimal, processor-level design space exploration (DSE) methodologies.  The authors present design methodologies for data storage and processing in real-time, cost-sensitive data-dominated embedded systems.  Readers will be enabled to reduce time-to-market, while satisfying system requirements for performance, area, and energy consumption, thereby minimizing the overall cost of the final design.   • Describes design space exploration (DSE) methodologies for data storage and processing in embedded systems, which achieve near-optimal solutions with scalable exploration time; • Presents a set of principles and the processes which support the development of the proposed scalable and near-optimal methodologies; • Enables readers to apply scalable and near-optimal methodologies to the intra-signal in-place optimization step for both regular and irregular memory accesses.

Green computing: power optimisation of VFI-based real-time multiprocessor dataflow applications (extended version)

NARCIS (Netherlands)

Ahmad, W.; Holzenspies, P.K.F.; Stoelinga, Mariëlle Ida Antoinette; van de Pol, Jan Cornelis

2015-01-01

Execution time is no longer the only performance metric for computer systems. In fact, a trend is emerging to trade raw performance for energy savings. Techniques like Dynamic Power Management (DPM, switching to low power state) and Dynamic Voltage and Frequency Scaling (DVFS, throttling processor

Low-complex energy-aware image communication in visual sensor networks

Science.gov (United States)

Phamila, Yesudhas Asnath Victy; Amutha, Ramachandran

2013-10-01

A low-complex, low bit rate, energy-efficient image compression algorithm explicitly designed for resource-constrained visual sensor networks applied for surveillance, battle field, habitat monitoring, etc. is presented, where voluminous amount of image data has to be communicated over a bandwidth-limited wireless medium. The proposed method overcomes the energy limitation of individual nodes and is investigated in terms of image quality, entropy, processing time, overall energy consumption, and system lifetime. This algorithm is highly energy efficient and extremely fast since it applies energy-aware zonal binary discrete cosine transform (DCT) that computes only the few required significant coefficients and codes them using enhanced complementary Golomb Rice code without using any floating point operations. Experiments are performed using the Atmel Atmega128 and MSP430 processors to measure the resultant energy savings. Simulation results show that the proposed energy-aware fast zonal transform consumes only 0.3% of energy needed by conventional DCT. This algorithm consumes only 6% of energy needed by Independent JPEG Group (fast) version, and it suits for embedded systems requiring low power consumption. The proposed scheme is unique since it significantly enhances the lifetime of the camera sensor node and the network without any need for distributed processing as was traditionally required in existing algorithms.

XOP: A second generation fast processor for on-line use in high energy physics experiments

International Nuclear Information System (INIS)

Lingjaerde, T.

1981-01-01

Processors for trigger calculations and data compression in high energy physics are characterized by a high data input capability combined with fas execution of relatively simple routines. In order to achieve the required performance it is advantageous to replace the classical computer instruction-set by microcoded instructions, the various fields of which control the internal subunits in parallel. The fast processor called ESOP is based on such a principle: the different operations are handled step by step by dedicated optimized modules under control of a central instruction unit. Thus, the arithmetic operations, address calculations, conditional checking, loop counts and next instruction evaluation all overlap in time. Based upon the experience from ESOP the architecture of a new processor 'XOP' is beginning to take shape which will be faster and easier to use. In this context the most important innovations are: easy handling of operands in the arithmetic unit by means of three data buses and large data files, a powerful data addressing unit for easy handling of vectors, as well as single operands, and a very flexible logic for conditional branching. Input/output will be made transparent through the introduction of internal fast processors which will be used in conjunction with powerful firmware as a software debugging aid. (orig.)

An Overview of Reconfigurable Hardware in Embedded Systems

Directory of Open Access Journals (Sweden)

Wenyin Fu

2006-09-01

Full Text Available Over the past few years, the realm of embedded systems has expanded to include a wide variety of products, ranging from digital cameras, to sensor networks, to medical imaging systems. Consequently, engineers strive to create ever smaller and faster products, many of which have stringent power requirements. Coupled with increasing pressure to decrease costs and time-to-market, the design constraints of embedded systems pose a serious challenge to embedded systems designers. Reconfigurable hardware can provide a flexible and efficient platform for satisfying the area, performance, cost, and power requirements of many embedded systems. This article presents an overview of reconfigurable computing in embedded systems, in terms of benefits it can provide, how it has already been used, design issues, and hurdles that have slowed its adoption.

VIRTUS: a multi-processor system in FASTBUS

International Nuclear Information System (INIS)

Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

1986-01-01

VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

Encoded low swing for ultra low power interconnect

NARCIS (Netherlands)

Krishnan, R.; Pineda de Gyvez, J.

2003-01-01

We present a novel encoded-low swing technique for ultra low power interconnect. Using this technique and an efficient circuit implementation, we achieve an average of 45.7% improvement in the power-delay product over the schemes utilizing low swing techniques alone, for random bit streams. Also, we

Embedded XML DOM Parser: An Approach for XML Data Processing on Networked Embedded Systems with Real-Time Requirements

Directory of Open Access Journals (Sweden)

Cavia Soto MAngeles

2008-01-01

Full Text Available Abstract Trends in control and automation show an increase in data processing and communication in embedded automation controllers. The eXtensible Markup Language (XML is emerging as a dominant data syntax, fostering interoperability, yet little is still known about how to provide predictable real-time performance in XML processing, as required in the domain of industrial automation. This paper presents an XML processor that is designed with such real-time performance in mind. The publication attempts to disclose insight gained in applying techniques such as object pooling and reuse, and other methods targeted at avoiding dynamic memory allocation and its consequent memory fragmentation. Benchmarking tests are reported in order to illustrate the benefits of the approach.

A lock circuit for a multi-core processor

DEFF Research Database (Denmark)

2015-01-01

An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

Embedded Thermal Control for Subsystems for Next Generation Spacecraft Applications

Science.gov (United States)

Didion, Jeffrey R.

2015-01-01

Thermal Fluids and Analysis Workshop, Silver Spring MD NCTS 21070-15. NASA, the Defense Department and commercial interests are actively engaged in developing miniaturized spacecraft systems and scientific instruments to leverage smaller cheaper spacecraft form factors such as CubeSats. This paper outlines research and development efforts among Goddard Space Flight Center personnel and its several partners to develop innovative embedded thermal control subsystems. Embedded thermal control subsystems is a cross cutting enabling technology integrating advanced manufacturing techniques to develop multifunctional intelligent structures to reduce Size, Weight and Power (SWaP) consumption of both the thermal control subsystem and overall spacecraft. Embedded thermal control subsystems permit heat acquisition and rejection at higher temperatures than state of the art systems by employing both advanced heat transfer equipment (integrated heat exchangers) and high heat transfer phenomena. The Goddard Space Flight Center Thermal Engineering Branch has active investigations seeking to characterize advanced thermal control systems for near term spacecraft missions. The embedded thermal control subsystem development effort consists of fundamental research as well as development of breadboard and prototype hardware and spaceflight validation efforts. This paper will outline relevant fundamental investigations of micro-scale heat transfer and electrically driven liquid film boiling. The hardware development efforts focus upon silicon based high heat flux applications (electronic chips, power electronics etc.) and multifunctional structures. Flight validation efforts include variable gravity campaigns and a proposed CubeSat based flight demonstration of a breadboard embedded thermal control system. The CubeSat investigation is technology demonstration will characterize in long-term low earth orbit a breadboard embedded thermal subsystem and its individual components to develop

Indirect adaptive soft computing based wavelet-embedded control paradigms for WT/PV/SOFC in a grid/charging station connected hybrid power system.

Directory of Open Access Journals (Sweden)

Sidra Mumtaz

Full Text Available This paper focuses on the indirect adaptive tracking control of renewable energy sources in a grid-connected hybrid power system. The renewable energy systems have low efficiency and intermittent nature due to unpredictable meteorological conditions. The domestic load and the conventional charging stations behave in an uncertain manner. To operate the renewable energy sources efficiently for harvesting maximum power, instantaneous nonlinear dynamics should be captured online. A Chebyshev-wavelet embedded NeuroFuzzy indirect adaptive MPPT (maximum power point tracking control paradigm is proposed for variable speed wind turbine-permanent synchronous generator (VSWT-PMSG. A Hermite-wavelet incorporated NeuroFuzzy indirect adaptive MPPT control strategy for photovoltaic (PV system to extract maximum power and indirect adaptive tracking control scheme for Solid Oxide Fuel Cell (SOFC is developed. A comprehensive simulation test-bed for a grid-connected hybrid power system is developed in Matlab/Simulink. The robustness of the suggested indirect adaptive control paradigms are evaluated through simulation results in a grid-connected hybrid power system test-bed by comparison with conventional and intelligent control techniques. The simulation results validate the effectiveness of the proposed control paradigms.

Indirect adaptive soft computing based wavelet-embedded control paradigms for WT/PV/SOFC in a grid/charging station connected hybrid power system.

Science.gov (United States)

Mumtaz, Sidra; Khan, Laiq; Ahmed, Saghir; Bader, Rabiah

2017-01-01

This paper focuses on the indirect adaptive tracking control of renewable energy sources in a grid-connected hybrid power system. The renewable energy systems have low efficiency and intermittent nature due to unpredictable meteorological conditions. The domestic load and the conventional charging stations behave in an uncertain manner. To operate the renewable energy sources efficiently for harvesting maximum power, instantaneous nonlinear dynamics should be captured online. A Chebyshev-wavelet embedded NeuroFuzzy indirect adaptive MPPT (maximum power point tracking) control paradigm is proposed for variable speed wind turbine-permanent synchronous generator (VSWT-PMSG). A Hermite-wavelet incorporated NeuroFuzzy indirect adaptive MPPT control strategy for photovoltaic (PV) system to extract maximum power and indirect adaptive tracking control scheme for Solid Oxide Fuel Cell (SOFC) is developed. A comprehensive simulation test-bed for a grid-connected hybrid power system is developed in Matlab/Simulink. The robustness of the suggested indirect adaptive control paradigms are evaluated through simulation results in a grid-connected hybrid power system test-bed by comparison with conventional and intelligent control techniques. The simulation results validate the effectiveness of the proposed control paradigms.

Indirect adaptive soft computing based wavelet-embedded control paradigms for WT/PV/SOFC in a grid/charging station connected hybrid power system

Science.gov (United States)

Khan, Laiq; Ahmed, Saghir; Bader, Rabiah

2017-01-01

This paper focuses on the indirect adaptive tracking control of renewable energy sources in a grid-connected hybrid power system. The renewable energy systems have low efficiency and intermittent nature due to unpredictable meteorological conditions. The domestic load and the conventional charging stations behave in an uncertain manner. To operate the renewable energy sources efficiently for harvesting maximum power, instantaneous nonlinear dynamics should be captured online. A Chebyshev-wavelet embedded NeuroFuzzy indirect adaptive MPPT (maximum power point tracking) control paradigm is proposed for variable speed wind turbine-permanent synchronous generator (VSWT-PMSG). A Hermite-wavelet incorporated NeuroFuzzy indirect adaptive MPPT control strategy for photovoltaic (PV) system to extract maximum power and indirect adaptive tracking control scheme for Solid Oxide Fuel Cell (SOFC) is developed. A comprehensive simulation test-bed for a grid-connected hybrid power system is developed in Matlab/Simulink. The robustness of the suggested indirect adaptive control paradigms are evaluated through simulation results in a grid-connected hybrid power system test-bed by comparison with conventional and intelligent control techniques. The simulation results validate the effectiveness of the proposed control paradigms. PMID:28877191

Agent-Oriented Embedded Control System Design and Development of a Vision-Based Automated Guided Vehicle

Directory of Open Access Journals (Sweden)

Wu Xing

2012-07-01

Full Text Available This paper presents a control system design and development approach for a vision-based automated guided vehicle (AGV based on the multi-agent system (MAS methodology and embedded system resources. A three-phase agent-oriented design methodology Prometheus is used to analyse system functions, construct operation scenarios, define agent types and design the MAS coordination mechanism. The control system is then developed in an embedded implementation containing a digital signal processor (DSP and an advanced RISC machine (ARM by using the multitasking processing capacity of multiple microprocessors and system services of a real-time operating system (RTOS. As a paradigm, an onboard embedded controller is designed and developed for the AGV with a camera detecting guiding landmarks, and the entire procedure has a high efficiency and a clear hierarchy. A vision guidance experiment for our AGV is carried out in a space-limited laboratory environment to verify the perception capacity and the onboard intelligence of the agent-oriented embedded control system.

Power distribution monitor for nuclear reactor

International Nuclear Information System (INIS)

Nishizawa, Yasuo; Kiguchi, Takashi.

1974-01-01

Object: To compare the measured local power region monitor (LPRM) index with the result of a primary calculation to correct the threshold condition for the primary calculation thereby to rapidly grasp and monitor the existing power distribution. Structure: The index of an LPRM disposed in a nuclear reactor is processed in a data processor to remove therefrom a noise, and transmitted to a threshold condition processor to be stored therein. The LPRM index measured by the threshold condition processor is compared with the calculated LPRM value transmitted from the primary processor, whereby the threshold condition is corrected and transmitted to the primary processor. After the completion of calculation, the traversing incore probe (TIP) indexing value is converted to a thermal output distribution or a linear output density distribution and transmitted to an output indicator or an output typewriter. The operator may monitor the existing power distribution by monitoring the output indicator. (Kamimura, M.)

Circuit for Communication Over Power Lines

Science.gov (United States)

Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

2011-01-01

Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

Configuring a fuel cell based residential combined heat and power system

Science.gov (United States)

Ahmed, Shabbir; Papadias, Dionissios D.; Ahluwalia, Rajesh K.

2013-11-01

The design and performance of a fuel cell based residential combined heat and power (CHP) system operating on natural gas has been analyzed. The natural gas is first converted to a hydrogen-rich reformate in a steam reformer based fuel processor, and the hydrogen is then electrochemically oxidized in a low temperature polymer electrolyte fuel cell to generate electric power. The heat generated in the fuel cell and the available heat in the exhaust gas is recovered to meet residential needs for hot water and space heating. Two fuel processor configurations have been studied. One of the configurations was explored to quantify the effects of design and operating parameters, which include pressure, temperature, and steam-to-carbon ratio in the fuel processor, and fuel utilization in the fuel cell. The second configuration applied the lessons from the study of the first configuration to increase the CHP efficiency. Results from the two configurations allow a quantitative comparison of the design alternatives. The analyses showed that these systems can operate at electrical efficiencies of ∼46% and combined heat and power efficiencies of ∼90%.

Feasibility Study on the Development of 2-channel Embedded Infrared Fiber-optic Sensor for Thermometry of Secondary Water System in Nuclear Power Plant

International Nuclear Information System (INIS)

Yoo, W. J.; Jang, K. W.; Seo, J. K.; Moon, J.; Han, K. T.; Lee, B.; Park, B. G.

2011-01-01

Any warm object by measuring the emitted infrared (IR) radiation. The radiometers using infrared optical fibers are based on the relationship between the temperature of a heat source and the quality and the quantity of an IR radiation. To measure physical properties including a temperature, optical fiber-based sensor has many advantages, such as small size, low cost, high resolution, remote sensing and immunity to electromagnetic radiation over conventional electrical sensors. In this study, we carried out the feasibility study on the development of an embedded IR fiber-optic sensor for thermometry of the secondary water system in a nuclear power plant. The 2-channel embedded fiberoptic temperature sensor was fabricated using two identical IR optical fibers for accurate thermometry without complicated calibration processes. To decide accurate temperature of the water, we measured the difference between the IR radiations emitted from the two temperature sensing probes according to the temperature variation of the water

Sensitometric control of roentgen film processors

International Nuclear Information System (INIS)

Forsberg, H.; Karolinska Sjukhuset, Stockholm

1987-01-01

Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

Trends in languages for embedded systems

International Nuclear Information System (INIS)

Boasson, M.

1986-01-01

Characteristics of embedded systems are discussed. In particular, the role of the computer in such systems is highlighted. Special emphasis is placed on the different requirements different kinds of systems may place on program execution. From such requirements necessary programming constructs are derived and in an overview of currently used languages it is shown how evolution led to modern languages like Ada and CHILL. With the advent of cheap, fast and small processing units, exploitation of parallelism for enhancing system performance is becoming increasingly tempting. However, few languages support the design of such multi-processor systems. Some methods for dealing with this problem are discussed. Finally, systems architectures and associated languages for the use of techniques originally developed for AI research are adumbrated. (Auth.)

Parallel Processor for 3D Recovery from Optical Flow

Directory of Open Access Journals (Sweden)

Jose Hugo Barron-Zambrano

2009-01-01

Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

Special purpose processors for high energy physics applications

International Nuclear Information System (INIS)

Verkerk, C.

1978-01-01

The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

Directory of Open Access Journals (Sweden)

Jen-Chih Kuo

2003-12-01

Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

The Central Trigger Processor (CTP)

CERN Multimedia

Franchini, Matteo

2016-01-01

The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

Fuel processor integrated H{sub 2}S catalytic partial oxidation technology for sulfur removal in fuel cell power plants

Energy Technology Data Exchange (ETDEWEB)

Gardner, T.H.; Berry, D.A.; Lyons, K.D.; Beer, S.K.; Freed, A.D. [U.S. Department of Energy, Morgantown, WV (USA). National Energy Technology Laboratory

2002-12-01

H{sub 2}S catalytic partial oxidation technology with an activated carbon catalyst was found to be a promising method for the removal of hydrogen sulfide from fuel cell hydrocarbon feedstocks. Three different fuel cell feedstocks were considered for analysis: sour natural gas, sour effluent from a liquid middle distillate fuel processor and a Texaco O{sub 2}-blown coal-derived synthesis gas. The H{sub 2}S catalytic partial oxidation reaction, its integratability into fuel cell power plants with different hydrocarbon feedstocks and its salient features are discussed. Experimental results indicate that H{sub 2}S concentration can be removed down to the part-per-million level in these plants. Additionally, a power law rate expression was developed and reaction kinetics compared to prior literature. The activation energy for this reaction was determined to be 34.4 kJ/g mol with the reaction being first order in H{sub 2}S and 0.3 order in O{sub 2}. 18 refs., 14 figs., 3 tabs.

Design And Implementation of Low Area/Power Elliptic Curve Digital Signature Hardware Core

Directory of Open Access Journals (Sweden)

Anissa Sghaier

2017-06-01

Full Text Available The Elliptic Curve Digital Signature Algorithm(ECDSA is the analog to the Digital Signature Algorithm(DSA. Based on the elliptic curve, which uses a small key compared to the others public-key algorithms, ECDSA is the most suitable scheme for environments where processor power and storage are limited. This paper focuses on the hardware implementation of the ECDSA over elliptic curveswith the 163-bit key length recommended by the NIST (National Institute of Standards and Technology. It offers two services: signature generation and signature verification. The proposed processor integrates an ECC IP, a Secure Hash Standard 2 IP (SHA-2 Ip and Random Number Generator IP (RNG IP. Thus, all IPs will be optimized, and different types of RNG will be implemented in order to choose the most appropriate one. A co-simulation was done to verify the ECDSA processor using MATLAB Software. All modules were implemented on a Xilinx Virtex 5 ML 50 FPGA platform; they require respectively 9670 slices, 2530 slices and 18,504 slices. FPGA implementations represent generally the first step for obtaining faster ASIC implementations. Further, the proposed design was also implemented on an ASIC CMOS 45-nm technology; it requires a 0.257 mm2 area cell achieving a maximum frequency of 532 MHz and consumes 63.444 (mW. Furthermore, in this paper, we analyze the security of our proposed ECDSA processor against the no correctness check for input points and restart attacks.

A High-Efficiency Wind Energy Harvester for Autonomous Embedded Systems.

Science.gov (United States)

Brunelli, Davide

2016-03-04

Energy harvesting is currently a hot research topic, mainly as a consequence of the increasing attractiveness of computing and sensing solutions based on small, low-power distributed embedded systems. Harvesting may enable systems to operate in a deploy-and-forget mode, particularly when power grid is absent and the use of rechargeable batteries is unattractive due to their limited lifetime and maintenance requirements. This paper focuses on wind flow as an energy source feasible to meet the energy needs of a small autonomous embedded system. In particular the contribution is on the electrical converter and system integration. We characterize the micro-wind turbine, we define a detailed model of its behaviour, and then we focused on a highly efficient circuit to convert wind energy into electrical energy. The optimized design features an overall volume smaller than 64 cm³. The core of the harvester is a high efficiency buck-boost converter which performs an optimal power point tracking. Experimental results show that the wind generator boosts efficiency over a wide range of operating conditions.

A High-Efficiency Wind Energy Harvester for Autonomous Embedded Systems

Science.gov (United States)

Brunelli, Davide

2016-01-01

Energy harvesting is currently a hot research topic, mainly as a consequence of the increasing attractiveness of computing and sensing solutions based on small, low-power distributed embedded systems. Harvesting may enable systems to operate in a deploy-and-forget mode, particularly when power grid is absent and the use of rechargeable batteries is unattractive due to their limited lifetime and maintenance requirements. This paper focuses on wind flow as an energy source feasible to meet the energy needs of a small autonomous embedded system. In particular the contribution is on the electrical converter and system integration. We characterize the micro-wind turbine, we define a detailed model of its behaviour, and then we focused on a highly efficient circuit to convert wind energy into electrical energy. The optimized design features an overall volume smaller than 64 cm3. The core of the harvester is a high efficiency buck-boost converter which performs an optimal power point tracking. Experimental results show that the wind generator boosts efficiency over a wide range of operating conditions. PMID:26959018

A High-Efficiency Wind Energy Harvester for Autonomous Embedded Systems

Directory of Open Access Journals (Sweden)

Davide Brunelli

2016-03-01

Full Text Available Energy harvesting is currently a hot research topic, mainly as a consequence of the increasing attractiveness of computing and sensing solutions based on small, low-power distributed embedded systems. Harvesting may enable systems to operate in a deploy-and-forget mode, particularly when power grid is absent and the use of rechargeable batteries is unattractive due to their limited lifetime and maintenance requirements. This paper focuses on wind flow as an energy source feasible to meet the energy needs of a small autonomous embedded system. In particular the contribution is on the electrical converter and system integration. We characterize the micro-wind turbine, we define a detailed model of its behaviour, and then we focused on a highly efficient circuit to convert wind energy into electrical energy. The optimized design features an overall volume smaller than 64 cm3. The core of the harvester is a high efficiency buck-boost converter which performs an optimal power point tracking. Experimental results show that the wind generator boosts efficiency over a wide range of operating conditions.

Low-Power Smart Imagers for Vision-Enabled Sensor Networks

CERN Document Server

Fernández-Berni, Jorge; Rodríguez-Vázquez, Ángel

2012-01-01

This book presents a comprehensive, systematic approach to the development of vision system architectures that employ sensory-processing concurrency and parallel processing to meet the autonomy challenges posed by a variety of safety and surveillance applications.  Coverage includes a thorough analysis of resistive diffusion networks embedded within an image sensor array. This analysis supports a systematic approach to the design of spatial image filters and their implementation as vision chips in CMOS technology. The book also addresses system-level considerations pertaining to the embedding of these vision chips into vision-enabled wireless sensor networks.  Describes a system-level approach for designing of vision devices and  embedding them into vision-enabled, wireless sensor networks; Surveys state-of-the-art, vision-enabled WSN nodes; Includes details of specifications and challenges of vision-enabled WSNs; Explains architectures for low-energy CMOS vision chips with embedded, programmable spatial f...

Network Communication for Low Level RF Control

International Nuclear Information System (INIS)

Liu Weiqing; Yin Chengke; Zhang Tongxuan; Fu Zechuan; Liu Jianfei

2009-01-01

Low Level RF (LLRF) control system for storage ring of Shanghai Synchrotron Radiation Facility (SSRF) has been built by digital technology. The settings of parameters and the feedback loop status are carried out through the network communication interface, and the local oscillation and clock, which is the important component of the digital LLRF control system, are also configured through network communication. NIOS II processor was employed as a core to build the embedded system with a real-time operating system MicroC/OS-II, finally Lightweight TCP/IP (LwIP) was used to achieve the communication interface. The communication network is stable after a long-term operation. (authors)

Low-Power Wireless Sensor Network Infrastructures

DEFF Research Database (Denmark)

Hansen, Morten Tranberg

Advancements in wireless communication and electronics improving form factor and hardware capabilities has expanded the applicability of wireless sensor networks. Despite these advancements, devices are still limited in terms of energy which creates the need for duty-cycling and low-power protocols...... peripherals need to by duty-cycled and the low-power wireless radios are severely influenced by the environmental effects causing bursty and unreliable wireless channels. This dissertation presents a communication stack providing services for low-power communication, secure communication, data collection......, and network management which enables construction of low-power wireless sensor network applications. More specifically, these services are designed with the extreme low-power scenarios of the SensoByg project in mind and are implemented as follows. First, low-power communication is implemented with Auto...

Experimental testing of the noise-canceling processor.

Science.gov (United States)

Collins, Michael D; Baer, Ralph N; Simpson, Harry J

2011-09-01

Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

Photonic Low Cost Micro-Sensor for in-Line Wear Particle Detection in Flowing Lube Oils

Directory of Open Access Journals (Sweden)

Jon Mabe

2017-03-01

Full Text Available The presence of microscopic particles in suspension in industrial fluids is often an early warning of latent or imminent failures in the equipment or processes where they are being used. This manuscript describes work undertaken to integrate different photonic principles with a micro- mechanical fluidic structure and an embedded processor to develop a fully autonomous wear debris sensor for in-line monitoring of industrial fluids. Lens-less microscopy, stroboscopic illumination, a CMOS imager and embedded machine vision technologies have been merged to develop a sensor solution that is able to detect and quantify the number and size of micrometric particles suspended in a continuous flow of a fluid. A laboratory test-bench has been arranged for setting up the configuration of the optical components targeting a static oil sample and then a sensor prototype has been developed for migrating the measurement principles to real conditions in terms of operating pressure and flow rate of the oil. Imaging performance is quantified using micro calibrated samples, as well as by measuring real used lubricated oils. Sampling a large fluid volume with a decent 2D spatial resolution, this photonic micro sensor offers a powerful tool at very low cost and compacted size for in-line wear debris monitoring.

Development of An Embedded FPGA-Based Data Acquisition System Dedicated to Zero Power Reactor Noise Experiments

Directory of Open Access Journals (Sweden)

Arkani Mohammad

2014-08-01

Full Text Available An embedded time interval data acquisition system (DAS is developed for zero power reactor (ZPR noise experiments. The system is capable of measuring the correlation or probability distribution of a random process. The design is totally implemented on a single Field Programmable Gate Array (FPGA. The architecture is tested on different FPGA platforms with different speed grades and hardware resources. Generic experimental values for time resolution and inter-event dead time of the system are 2.22 ns and 6.67 ns respectively. The DAS can record around 48-bit x 790 kS/s utilizing its built-in fast memory. The system can measure very long time intervals due to its 48-bit timing structure design. As the architecture can work on a typical FPGA, this is a low cost experimental tool and needs little time to be established. In addition, revisions are easily possible through its reprogramming capability. The performance of the system is checked and verified experimentally.

Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors

OpenAIRE

Natvig, Lasse; Follan, Torbjørn; Støa, Simen; Magnussen, Sindre; Guirado, Antonio Garcia

2015-01-01

Climbing Mont Blanc (CMB) is an open online judge used for training in energy efficient programming of state-of-the-art heterogeneous multicores. It uses an Odroid-XU3 board from Hardkernel with an Exynos Octa processor and integrated power sensors. This processor is three-way heterogeneous containing 14 different cores of three different types. The board currently accepts C and C++ programs, with support for OpenCL v1.1, OpenMP 4.0 and Pthreads. Programs submitted using the graphical user in...

Scalable Motion Estimation Processor Core for Multimedia System-on-Chip Applications

Science.gov (United States)

Lai, Yeong-Kang; Hsieh, Tian-En; Chen, Lien-Fei

2007-04-01

In this paper, we describe a high-throughput and scalable motion estimation processor architecture for multimedia system-on-chip applications. The number of processing elements (PEs) is scalable according to the variable algorithm parameters and the performance required for different applications. Using the PE rings efficiently and an intelligent memory-interleaving organization, the efficiency of the architecture can be increased. Moreover, using efficient on-chip memories and a data management technique can effectively decrease the power consumption and memory bandwidth. Techniques for reducing the number of interconnections and external memory accesses are also presented. Our results demonstrate that the proposed scalable PE-ringed architecture is a flexible and high-performance processor core in multimedia system-on-chip applications.

Study on the analytical methods to evaluate the interaction effects of embedded nuclear power plants

International Nuclear Information System (INIS)

Fukuzawa, R.; Chiba, O.; Tohdo, M.; Hatori, T.

1987-01-01

For the seismic response analyses of nuclear power plants which are more or less embedded into soil medium, it is very important to evaluate the interactive effects on the interface between soil and foundation wall, such as wave propagation to infinity radiated from the side wall. The methods generally used in these analyses can be classified into the two basic procedures. One is the direct procedure in which a structure and soil are medeled together into finite elements or beam elements having the quiet boundary; transmitting boundary, non-reflecting boundary. The other is the substructure procedure in which the computational procedure is divided into two steps. In the first step the behavior of massless foundation due to an external force and seismic motion under the assumption as rigid foundation is analyzed, and the results are represented by impedance functions and foundation input motions. Using the results, the structural response analyses are performed. Taking the substructure procedure for seismic response analyses of embedded nuclear power plants, it is the purpose of this paper to present the features of solutions on impedance functions and foundation input motions obtained by various methods such as 3- or 2-dimensional approach, and their influences on structural responses

35-We polymer electrolyte membrane fuel cell system for notebook computer using a compact fuel processor

Energy Technology Data Exchange (ETDEWEB)

Son, In-Hyuk; Shin, Woo-Cheol; Lee, Sung-Chul; Ahn, Jin-Gu; Han, Sang-Il; kweon, Ho-Jin; Kim, Ju-Yong; Park, Jun-Yong [Energy 1 Group, Energy Laboratory at Corporate R and D Center in Samsung SDI Co., Ltd., 575, Shin-dong, Yeongtong-gu, Suwon-si, Gyeonggi-do 443-731 (Korea); Lee, Yong-Kul [Department of Chemical Engineering, Dankook University, Youngin 448-701 (Korea); Kim, Moon-Chan [Department of Environmental Engineering, Chongju University, Chongju 360-764 (Korea)

2008-10-15

A polymer electrolyte membrane fuel cell (PEMFC) system is developed to power a notebook computer. The system consists of a compact methanol-reforming system with a CO preferential oxidation unit, a 16-cell PEMFC stack, and a control unit for the management of the system with a d.c.-d.c. converter. The compact fuel-processor system (260 cm{sup 3}) generates about 1.2 L min{sup -1} of reformate, which corresponds to 35 We, with a low CO concentration (<30 ppm, typically 0 ppm), and is thus proven to be capable of being targetted at notebook computers. (author)

Development of a highly reliable CRT processor

International Nuclear Information System (INIS)

Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

1996-01-01

Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

Computer Generated Inputs for NMIS Processor Verification

International Nuclear Information System (INIS)

J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

2001-01-01

Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

A Score Function for Optimizing the Cycle-Life of Battery-Powered Embedded Systems

DEFF Research Database (Denmark)

Wognsen, Erik Ramsgaard; Haverkort, Boudewijn; Jongerden, Marijn

2015-01-01

An ever increasing share of embedded systems is powered by rechargeable batteries. These batteries deteriorate with the number of charge/discharge cycles they are subjected to, the so-called cycle life. In this paper, we propose the wear score function to compare and evaluate the relative impact...... of usage (charge and discharge) profiles on cycle life. The wear score function can not only be used to rank different usage profiles, these rankings can also be used as a criterion for optimizing the overall lifetime of a battery-powered system. We perform such an optimization on a nano-satellite case...... checking and reinforcement learning to synthesize near-optimal scheduling strategies subject to possible hard timing-constaints. We use this to study the trade-off between optimal short-term dynamic payload selection and the operational life of the satellite....