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Sample records for low-latency trigger processor

  1. A Track Reconstructing Low-latency Trigger Processor for High-energy Physics

    CERN Document Server

    AUTHOR|(CDS)2067518

    2009-01-01

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 µs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbps via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's dr...

  2. A track reconstructing low-latency trigger processor for high-energy physics

    International Nuclear Information System (INIS)

    Cuveland, Jan de

    2009-01-01

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 μs to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 μs with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  3. A track reconstructing low-latency trigger processor for high-energy physics

    Energy Technology Data Exchange (ETDEWEB)

    Cuveland, Jan de

    2009-09-17

    The detection and analysis of the large number of particles emerging from high-energy collisions between atomic nuclei is a major challenge in experimental heavy-ion physics. Efficient trigger systems help to focus the analysis on relevant events. A primary objective of the Transition Radiation Detector of the ALICE experiment at the LHC is to trigger on high-momentum electrons. In this thesis, a trigger processor is presented that employs massive parallelism to perform the required online event reconstruction within 2 {mu}s to contribute to the Level-1 trigger decision. Its three-stage hierarchical architecture comprises 109 nodes based on FPGA technology. Ninety processing nodes receive data from the detector front-end at an aggregate net bandwidth of 2.16 Tbit/s via 1080 optical links. Using specifically developed components and interconnections, the system combines high bandwidth with minimum latency. The employed tracking algorithm three-dimensionally reassembles the track segments found in the detector's drift chambers based on explicit value comparisons, calculates the momentum of the originating particles from the course of the reconstructed tracks, and finally leads to a trigger decision. The architecture is capable of processing up to 20 000 track segments in less than 2 {mu}s with high detection efficiency and reconstruction precision for high-momentum particles. As a result, this thesis shows how a trigger processor performing complex online track reconstruction within tight real-time requirements can be realized. The presented hardware has been built and is in continuous data taking operation in the ALICE experiment. (orig.)

  4. Low-Latency Embedded Vision Processor (LLEVS)

    Science.gov (United States)

    2016-03-01

    algorithms, low-latency video processing, embedded image processor, wearable electronics, helmet-mounted systems, alternative night / day imaging...external subsystems and data sources with the device. The establishment of data interfaces in terms of data transfer rates, formats and types are...video signals from Near-visible Infrared (NVIR) sensor, Shortwave IR (SWIR) and Longwave IR (LWIR) is the main processing for Night Vision (NI) system

  5. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  6. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  7. Trigger and decision processors

    International Nuclear Information System (INIS)

    Franke, G.

    1980-11-01

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  8. Fast response electromagnetic follow-ups from low latency GW triggers

    International Nuclear Information System (INIS)

    Howell, E J; Chu, Q; Rowlinson, A; Wen, L; Gao, H; Zhang, B; Tingay, S J; Boër, M

    2016-01-01

    We investigate joint low-latency gravitational wave (GW) detection and prompt electromagnetic (EM) follow-up observations of coalescing binary neutron stars (BNSs). Assuming that BNS mergers are associated with short duration gamma ray bursts (SGRBs), we evaluate if rapid EM follow-ups can capture the prompt emission, early engine activity or reveal any potential by-products such as magnetars or fast radio bursts. To examine the expected performance of extreme low-latency search pipelines, we simulate a population of coalescing BNSs and use these to estimate the detectability and localisation efficiency at different times before merger. Using observational SGRB flux data corrected to the range of the advanced GW interferometric detectors, we determine what EM observations could be achieved from low-frequency radio up to high energy γ-ray. We show that while challenging, breakthrough multi-messenger science is possible through low latency pipelines. (paper)

  9. The ALICE Central Trigger Processor (CTP) upgrade

    International Nuclear Information System (INIS)

    Krivda, M.; Alexandre, D.; Barnby, L.S.; Evans, D.; Jones, P.G.; Jusko, A.; Lietava, R.; Baillie, O. Villalobos; Pospíšil, J.

    2016-01-01

    The ALICE Central Trigger Processor (CTP) at the CERN LHC has been upgraded for LHC Run 2, to improve the Transition Radiation Detector (TRD) data-taking efficiency and to improve the physics performance of ALICE. There is a new additional CTP interaction record sent using a new second Detector Data Link (DDL), a 2 GB DDR3 memory and an extension of functionality for classes. The CTP switch has been incorporated directly onto the new LM0 board. A design proposal for an ALICE CTP upgrade for LHC Run 3 is also presented. Part of the development is a low latency high bandwidth interface whose purpose is to minimize an overall trigger latency

  10. A low-latency, low-overhead encoder for data transmission in the ATLAS Liquid Argon Calorimeter trigger upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Xiao, Le [Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Li, Xiaoting [Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Gong, Datao, E-mail: dgong@mail.smu.edu [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Chen, Jinghong [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Deng, Binwei [School of Electric and Electronic Information Engineering, Hubei Polytechnic University, Huangshi, Hubei 435003 (China); Fan, Qingjun; Feng, Yulang [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Guo, Di [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei, Anhui 230026 (China); He, Huiqin [Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Shenzhen Polytechnic, Shenzhen 518055 (China); Hou, Suen [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Huang, Guangming, E-mail: gmhuang@phy.ccnu.edu.cn [Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Liu, Chonghan; Liu, Tiankuan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Sun, Xiangming [Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Tang, Yuxuan [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Teng, Ping-Kun [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); and others

    2016-09-21

    In this paper, we present the design and test results of an encoder integrated circuit for the ATLAS Liquid Argon Calorimeter trigger upgrade. The encoder implements a low-latency and low-overhead line code called LOCic. The encoder operates at 320 MHz with a latency of no greater than 21 ns. The overhead of the encoder is 14.3%. The encoder is an important block of the transmitter ASIC LOCx2, which is prototyped with a commercial 0.25 μm Silicon-on-Sapphire CMOS technology and packaged in a 100-pin QFN package. - Highlights: • We present the design and test results of an encoder integrated circuit for the ATLAS Liquid Argon Calorimeter trigger upgrade. • The encoder implements a low-latency and low-overhead line code called LOCic. The encoder operates at 320 MHz with a latency of no greater than 21 ns. The overhead of the encoder is 14.3%. • The encoder is an important block of the transmitter ASIC LOCx2, which is prototyped with a commercial 0.25 μm Silicon-on-Sapphire CMOS technology for radiation-tolerance and packaged in a 100-pin QFN package.

  11. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

    International Nuclear Information System (INIS)

    Ammendola, R; Biagioni, A; Frezza, O; Lonardo, A; Cicero, F Lo; Paolucci, P S; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P; Lamanna, G; Pantaleo, F; Sozzi, M

    2014-01-01

    NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities

  12. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

    CERN Document Server

    INSPIRE-00646837; Biagioni, A.; Frezza, O.; Lamanna, G.; Lonardo, A.; Lo Cicero, F.; Paolucci, P.S.; Pantaleo, F.; Rossetti, D.; Simula, F.; Sozzi, M.; Tosoratto, L.; Vicini, P.

    2014-02-21

    NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34~Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.

  13. NaNet: a flexible and configurable low-latency NIC for real-time trigger systems based on GPUs

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R [INFN Sezione di Roma Tor Vergata, Via della Ricerca Scientifica, 1 - 00133 Roma (Italy); Biagioni, A; Frezza, O; Lonardo, A; Cicero, F Lo; Paolucci, P S; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, P.le Aldo Moro, 2 - 00185 Roma (Italy); Lamanna, G; Pantaleo, F; Sozzi, M [INFN Sezione di Pisa, Via F. Buonarroti 2 - 56127 Pisa (Italy)

    2014-02-01

    NaNet is an FPGA-based PCIe X8 Gen2 NIC supporting 1/10 GbE links and the custom 34 Gbps APElink channel. The design has GPUDirect RDMA capabilities and features a network stack protocol offloading module, making it suitable for building low-latency, real-time GPU-based computing systems. We provide a detailed description of the NaNet hardware modular architecture. Benchmarks for latency and bandwidth for GbE and APElink channels are presented, followed by a performance analysis on the case study of the GPU-based low level trigger for the RICH detector in the NA62 CERN experiment, using either the NaNet GbE and APElink channels. Finally, we give an outline of project future activities.

  14. Fast processor for dilepton triggers

    International Nuclear Information System (INIS)

    Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

    1983-01-01

    We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

  15. NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

    International Nuclear Information System (INIS)

    Ammendola, Roberto; Biagioni, Andrea; Frezza, Ottorino; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Rossetti, Davide; Simula, Francesco; Tosoratto, Laura; Vicini, Piero; Fantechi, Riccardo; Lamanna, Gianluca; Pantaleo, Felice; Piandani, Roberto; Sozzi, Marco; Pontisso, Luca

    2014-01-01

    We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  16. NaNet: a low-latency NIC enabling GPU-based, real-time low level trigger systems

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, Roberto [INFN, Rome – Tor Vergata (Italy); Biagioni, Andrea; Frezza, Ottorino; Cicero, Francesca Lo; Lonardo, Alessandro; Paolucci, Pier Stanislao; Rossetti, Davide; Simula, Francesco; Tosoratto, Laura; Vicini, Piero [INFN, Rome – Sapienza (Italy); Fantechi, Riccardo [CERN, Geneve (Switzerland); Lamanna, Gianluca; Pantaleo, Felice; Piandani, Roberto; Sozzi, Marco [INFN, Pisa (Italy); Pontisso, Luca [University, Rome (Italy)

    2014-06-11

    We implemented the NaNet FPGA-based PCIe Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  17. NaNet:a low-latency NIC enabling GPU-based, real-time low level trigger systems

    CERN Document Server

    INSPIRE-00646837; Biagioni, Andrea; Fantechi, Riccardo; Frezza, Ottorino; Lamanna, Gianluca; Lo Cicero, Francesca; Lonardo, Alessandro; Paolucci, Pier Stanislao; Pantaleo, Felice; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Tosoratto, Laura; Vicini, Piero

    2014-01-01

    We implemented the NaNet FPGA-based PCI2 Gen2 GbE/APElink NIC, featuring GPUDirect RDMA capabilities and UDP protocol management offloading. NaNet is able to receive a UDP input data stream from its GbE interface and redirect it, without any intermediate buffering or CPU intervention, to the memory of a Fermi/Kepler GPU hosted on the same PCIe bus, provided that the two devices share the same upstream root complex. Synthetic benchmarks for latency and bandwidth are presented. We describe how NaNet can be employed in the prototype of the GPU-based RICH low-level trigger processor of the NA62 CERN experiment, to implement the data link between the TEL62 readout boards and the low level trigger processor. Results for the throughput and latency of the integrated system are presented and discussed.

  18. The UA1 trigger processor

    International Nuclear Information System (INIS)

    Grayer, G.H.

    1981-01-01

    Experiment UA1 is a large multi-purpose spectrometer at the CERN proton-antiproton collider, scheduled for late 1981. The principal trigger is formed on the basis of the energy deposition in calorimeters. A trigger decision taken in under 2.4 microseconds can avoid dead time losses due to the bunched nature of the beam. To achieve this we have built fast 8-bit charge to digital converters followed by two identical digital processors tailored to the experiment. The outputs of groups of the 2440 photomultipliers in the calorimeters are summed to form a total of 288 input channels to the ADCs. A look-up table in RAM is used to convert the digitised photomultiplier signals to energy in one processor, combinations of input channels, and also counts the number of clusters with electromagnetic or hadronic energy above pre-determined levels. Up to twelve combinations of these conditions, together with external information, may be combined in coincidence or in veto to form the final trigger. Provision has been made for testing using simulated data in an off-line mode, and sampling real data when on-line. (orig.)

  19. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

  20. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Baird, S.A.; Biddulph, P.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  1. Intelligent trigger processor for the crystal box

    International Nuclear Information System (INIS)

    Sanders, G.H.; Butler, H.S.; Cooper, M.D.

    1981-01-01

    A large solid angle modular NaI(Tl) detector with 432 phototubes and 88 trigger scintillators is being used to search simultaneously for three lepton flavor changing decays of muon. A beam of up to 10 6 muons stopping per second with a 6% duty factor would yield up to 1000 triggers per second from random triple coincidences. A reduction of the trigger rate to 10 Hz is required from a hardwired primary trigger processor described in this paper. Further reduction to < 1 Hz is achieved by a microprocessor based secondary trigger processor. The primary trigger hardware imposes voter coincidence logic, stringent timing requirements, and a non-adjacency requirement in the trigger scintillators defined by hardwired circuits. Sophisticated geometric requirements are imposed by a PROM-based matrix logic, and energy and vector-momentum cuts are imposed by a hardwired processor using LSI flash ADC's and digital arithmetic loci. The secondary trigger employs four satellite microprocessors to do a sparse data scan, multiplex the data acquisition channels and apply additional event filtering

  2. The TIGER trigger processor for the CAMERA detector at COMPASS-II

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut der Universitaet Freiburg, Freiburg im Breisgau (Germany)

    2013-07-01

    In today's nuclear and high-energy physics experiments the background-induced occupancy of the detector channels can be quite high; therefore it is important to have sophisticated trigger subsystems which process the data in real-time to generate trigger objects for the global trigger decision. In this work we present a FPGA based low-latency trigger processor for the COMPASS-II experiment. TIGER is a high-performance trigger processor that was developed to fit perfectly in the GANDALF framework and extend its versatility. It is designed as a VXS module and is allocated to the central VXS switch slot, which has a direct link from every payload slot. The synchronous transfer protocol was optimized for low latencies and offers a bandwidth of up to 8 Gbit/s per link. The centerpiece of the board is a Xilinx Virtex-6 SX315T FPGA, offering vast programmable logic, embedded memory and DSP resources. It is accompanied by DDR3 memory, a COM Express CPU and a MXM GPU. Besides the VXS backplane ports, the board features two SFP+ transceivers, 32 LVDS inputs and 32 LVDS outputs to interface with the global trigger system and a Gigabit Ethernet port for configuration and monitoring.

  3. UA1 upgrade first-level calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Charlton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Eisenhandler, E.; Fensome, I.; Landon, M.

    1989-01-01

    A new first-level trigger processor has been built for the UA1 experiment on the Cern SppS Collider. The processor exploits the fine granularity of the new UA1 uranium-TMP calorimeter to improve the selectivity of the trigger. The new electron trigger has improved hadron jet rejection, achieved by requiring low energy deposition around the electromagnetic cluster. A missing transverse energy trigger and a total energy trigger have also been implemented. (orig.)

  4. The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Lazovich, Tomo; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

  5. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  6. A programmable systolic trigger processor for FERA bus data

    International Nuclear Information System (INIS)

    Appelquist, G.; Hovander, B.; Sellden, B.; Bohm, C.

    1992-09-01

    A generic CAMAC based trigger processor module for fast processing of large amounts of ADC data, has been designed. This module has been realised using complex programmable gate arrays (LCAs from XILINX). The gate arrays have been connected to memories and multipliers in such a way that different gate array configurations can cover a wide range of module applications. Using this module, it is possible to construct complex trigger processors. The module uses both the fast ECL FERA bus and the CAMAC bus for inputs and outputs. The latter, however, is primarily used for set-up and control but may also be used for data output. Large numbers of ADCs can be served by a hierarchical arrangement of trigger processor modules, processing ADC data with pipe-line arithmetics producing the final result at the apex of the pyramid. The trigger decision will be transmitted to the data acquisition system via a logic signal while numeric results may be extracted by the CAMAC controller. The trigger processor was originally developed for the proposed neutral particle search experiment at CERN, NUMASS. There it was designed to serve as a second level trigger processor. It was required to correct all ADC raw data for efficiency and pedestal, calculate the total calorimeter energy, obtain the optimal time of flight data and calculate the particle mass. A suitable mass cut would then deliver the trigger decision. More complex triggers were also considered. (au)

  7. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  8. Fast track trigger processor for the OPAL detector at LEP

    Energy Technology Data Exchange (ETDEWEB)

    Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

    1986-09-20

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

  9. The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units

    CERN Document Server

    Tavares Delgado, Ademar; The ATLAS collaboration

    2016-01-01

    The ATLAS Trigger Algorithms for General Purpose Graphics Processor Units Type: Talk Abstract: We present the ATLAS Trigger algorithms developed to exploit General­ Purpose Graphics Processor Units. ATLAS is a particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system has two levels, hardware-­based Level 1 and the High Level Trigger implemented in software running on a farm of commodity CPU. Performing the trigger event selection within the available farm resources presents a significant challenge that will increase future LHC upgrades. are being evaluated as a potential solution for trigger algorithms acceleration. Key factors determining the potential benefit of this new technology are the relative execution speedup, the number of GPUs required and the relative financial cost of the selected GPU. We have developed a trigger demonstrator which includes algorithms for reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Cal...

  10. First level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

  11. First-level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

  12. The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

    CERN Document Server

    INSPIRE-00226165

    2014-01-01

    The ATLAS detector at LHC will require a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3 x 10^34 cm-2s-1, this represents an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from a physics point of view, a new element will be included in the Level-1 Trigger scheme after 2015: the Topological Processor (L1Topo). The L1Topo system, currently developed at CERN, will consist initially of an ATCA crate and two L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up to 1.6 Tb/s of data from the calorimeter and muon detectors into two high-end FPGA (Virtex7-690), to be processed in about 200 ns. The design has been optimized to guarantee excellent signal in- tegrity of the high-speed links and low latency data transmission on the Real Time Data Path (RTDP). The L1Topo receives data in a standa...

  13. Graphical processors for HEP trigger systems

    International Nuclear Information System (INIS)

    Ammendola, R.; Biagioni, A.; Chiozzi, S.; Cotta Ramusino, A.; Di Lorenzo, S.; Fantechi, R.; Fiorini, M.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P.S.; Pastorelli, E.; Piandani, R.; Pontisso, L.; Rossetti, D.; Simula, F.; Sozzi, M.

    2017-01-01

    General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.

  14. Graphical processors for HEP trigger systems

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R. [INFN Sezione di Roma Tor Vergata, Via della Ricerca Scientifica, 1, 00133 Roma (Italy); Biagioni, A. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Chiozzi, S.; Cotta Ramusino, A. [INFN Sezione di Ferrara, Via Saragat, 1, 44122 Ferrara (Italy); Di Lorenzo, S. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Università di Pisa, Lungarno Pacinotti 43, 56126 Pisa (Italy); Fantechi, R. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Fiorini, M. [INFN Sezione di Ferrara, Via Saragat, 1, 44122 Ferrara (Italy); Università di Ferrara, Via Ludovico Ariosto 35, 44121 Ferrara (Italy); Frezza, O. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Lamanna, G. [INFN, Laboratori Nazionali di Frascati (Italy); Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Neri, I.; Paolucci, P.S.; Pastorelli, E. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Piandani, R. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Pontisso, L., E-mail: luca.pontisso@cern.ch [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Rossetti, D. [NVIDIA Corp., Santa Clara, CA (United States); Simula, F. [INFN Sezione di Roma, P.le Aldo Moro, 2, 00185 Roma (Italy); Sozzi, M. [INFN Sezione di Pisa, L. Bruno Pontecorvo, 3, 56127 Pisa (Italy); Università di Pisa, Lungarno Pacinotti 43, 56126 Pisa (Italy); and others

    2017-02-11

    General-purpose computing on GPUs is emerging as a new paradigm in several fields of science, although so far applications have been tailored to employ GPUs as accelerators in offline computations. With the steady decrease of GPU latencies and the increase in link and memory throughputs, time is ripe for real-time applications using GPUs in high-energy physics data acquisition and trigger systems. We will discuss the use of online parallel computing on GPUs for synchronous low level trigger systems, focusing on tests performed on the trigger of the CERN NA62 experiment. Latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Moreover, we discuss how specific trigger algorithms can be parallelised and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen LHC luminosity upgrade where highly selective algorithms will be crucial to maintain sustainable trigger rates with very high pileup.

  15. A fast processor for di-lepton triggers

    CERN Document Server

    Kostarakis, P; Barsotti, E; Conetti, S; Cox, B; Enagonio, J; Haldeman, M; Haynes, W; Katsanevas, S; Kerns, C; Lebrun, P; Smith, H; Soszyniski, T; Stoffel, J; Treptow, K; Turkot, F; Wagner, R

    1981-01-01

    As a new application of the Fermilab ECL-CAMAC logic modules a fast trigger processor was developed for Fermilab experiment E-537, aiming to measure the higher mass di-muon production by antiprotons. The processor matches the hit information received from drift chambers and scintillation counters, to find candidate muon tracks and determine their directions and momenta. The tracks are then paired to compute an invariant mass: when the computed mass falls within the desired range, the event is accepted. The process is accomplished in times of 5 to 10 microseconds, while achieving a trigger rate reduction of up to a factor of ten. (5 refs).

  16. The Level 0 Trigger Processor for the NA62 experiment

    International Nuclear Information System (INIS)

    Chiozzi, S.; Gamberini, E.; Gianoli, A.; Mila, G.; Neri, I.; Petrucci, F.; Soldi, D.

    2016-01-01

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  17. The Level 0 Trigger Processor for the NA62 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Chiozzi, S. [INFN, Ferrara (Italy); Gamberini, E. [University of Ferrara and INFN, Ferrara (Italy); Gianoli, A. [INFN, Ferrara (Italy); Mila, G. [University of Turin and INFN, Turin (Italy); Neri, I., E-mail: neri@fe.infn.it [University of Ferrara and INFN, Ferrara (Italy); Petrucci, F. [University of Ferrara and INFN, Ferrara (Italy); Soldi, D. [University of Turin and INFN, Turin (Italy)

    2016-07-11

    In the NA62 experiment at CERN, the intense flux of particles requires a high-performance trigger for the data acquisition system. A Level 0 Trigger Processor (L0TP) was realized, performing the event selection based on trigger primitives coming from sub-detectors and reducing the trigger rate from 10 to 1 MHz. The L0TP is based on a commercial FPGA device and has been implemented in two different solutions. The performance of the two systems are highlighted and compared.

  18. A general-purpose trigger processor system and its application to fast vertex trigger

    International Nuclear Information System (INIS)

    Hazumi, M.; Banas, E.; Natkaniec, Z.; Ostrowicz, W.

    1997-12-01

    A general-purpose hardware trigger system has been developed. The system comprises programmable trigger processors and pattern generator/samplers. The hardware design of the system is described. An application as a prototype of the very fast vertex trigger in an asymmetric B-factory at KEK is also explained. (author)

  19. The ATLAS Level-1 Muon to Central Trigger Processor Interface

    CERN Document Server

    Berge, D; Farthouat, P; Haas, S; Klofver, P; Krasznahorkay, A; Messina, A; Pauly, T; Schuler, G; Spiwoks, R; Wengler, T; PH-EP

    2007-01-01

    The Muon to Central Trigger Processor Interface (MUCTPI) is part of the ATLAS Level-1 trigger system and connects the output of muon trigger system to the Central Trigger Processor (CTP). At every bunch crossing (BC), the MUCTPI receives information on muon candidates from each of the 208 muon trigger sectors and calculates the total multiplicity for each of six transverse momentum (pT) thresholds. This multiplicity value is then sent to the CTP, where it is used together with the input from the Calorimeter trigger to make the final Level-1 Accept (L1A) decision. In addition the MUCTPI provides summary information to the Level-2 trigger and to the data acquisition (DAQ) system for events selected at Level-1. This information is used to define the regions of interest (RoIs) that drive the Level-2 muontrigger processing. The MUCTPI system consists of a 9U VME chassis with a dedicated active backplane and 18 custom designed modules. The design of the modules is based on state-of-the-art FPGA devices and special ...

  20. The Topological Processor for the future ATLAS Level-1 Trigger

    CERN Document Server

    Kahra, C; The ATLAS collaboration

    2014-01-01

    ATLAS is an experiment on the Large Hadron Collider (LHC), located at the European Organization for Nuclear Research (CERN) in Switzerland. By 2015 the LHC instantaneous luminosity will be increased from $10^{34}$ up to $3\\cdot 10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events that contain interesting physics events. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than $2.5 \\mu \\mathrm{s}$. It is composed of the Calorimeter Trigger, the Muon Trigger and the Central Trigger Processor (CTP). In 2014, there will be a new electronics module: the Topological Processor (L1Topo). The L1Topo will make it possible, for the first time, to use detailed information from subdetectors in a single Level-1 module. This allows the determi...

  1. The fast tracker processor for hadron collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, E; Pietri, M; Varotto, G

    2001-01-01

    Perspectives for precise and fast track reconstruction in future hadron collider experiments are addressed. We discuss the feasibility of a pipelined highly parallel processor dedicated to the implementation of a very fast tracking algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points, called patterns, for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at an input rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution tracks with transverse momentum above a few GeV and search for secondary vertices within typical level-2 times. (15 refs).

  2. The fast tracker processor for hadronic collider triggers

    CERN Document Server

    Annovi, A; Bardi, A; Carosi, R; Dell'Orso, Mauro; D'Onofrio, M; Giannetti, P; Iannaccone, G; Morsani, F; Pietri, M; Varotto, G

    2000-01-01

    Perspective for precise and fast track reconstruction in future hadronic collider experiments are addressed. We discuss the feasibility of a pipelined highly parallelized processor dedicated to the implementation of a very fast algorithm. The algorithm is based on the use of a large bank of pre-stored combinations of trajectory points (patterns) for extremely complex tracking systems. The CMS experiment at LHC is used as a benchmark. Tracking data from the events selected by the level-1 trigger are sorted and filtered by the Fast Tracker processor at a rate of 100 kHz. This data organization allows the level-2 trigger logic to reconstruct full resolution traces with transverse momentum above few GeV and search secondary vertexes within typical level-2 times. 15 Refs.

  3. Eight-Channel Digital Signal Processor and Universal Trigger Module

    Science.gov (United States)

    Skulski, Wojtek; Wolfs, Frank

    2003-04-01

    A 10-bit, 8-channel, 40 megasamples per second digital signal processor and waveform digitizer DDC-8 (nicknamed Universal Trigger Module) is presented. The digitizer features 8 analog inputs, 1 analog output for a reconstructed analog waveform, 16 NIM logic inputs, 8 NIM logic outputs, and a pool of 16 TTL logic lines which can be individually configured as either inputs or outputs. The first application of this device is to enhance the present trigger electronics for PHOBOS at RHIC. The status of the development and the first results are presented. Possible applications of the new device are discussed. Supported by the NSF grant PHY-0072204.

  4. Level Zero Trigger Processor for the NA62 experiment

    Science.gov (United States)

    Soldi, D.; Chiozzi, S.

    2018-05-01

    The NA62 experiment is designed to measure the ultra-rare decay K+ arrow π+ ν bar nu branching ratio with a precision of ~ 10% at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three different levels designed to select events of physics interest in a high beam rate environment. The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the NA62 L0TP system is a new approach compared to existing systems used in high-energy physics experiments. It is fully digital, based on a standard gigabit Ethernet communication between detectors and the L0TP Board. The L0TP Board is a commercial development board, mounting a programmable logic device (FPGA). The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period. The L0TP realigns in time the primitives coming from seven different sources and performs a data selection based on the characteristics of the event such as energy, multiplicity and topology of hits in the sub-detectors. It guarantees a maximum latency of 1 ms. The maximum input rate is about 10 MHz for each sub-detector, while the design maximum output trigger rate is 1 MHz. A description of the trigger algorithm is presented here.

  5. Advanced LIGO low-latency searches

    Science.gov (United States)

    Kanner, Jonah; LIGO Scientific Collaboration, Virgo Collaboration

    2016-06-01

    Advanced LIGO recently made the first detection of gravitational waves from merging binary black holes. The signal was first identified by a low-latency analysis, which identifies gravitational-wave transients within a few minutes of data collection. More generally, Advanced LIGO transients are sought with a suite of automated tools, which collectively identify events, evaluate statistical significance, estimate source position, and attempt to characterize source properties. This low-latency effort is enabling a broad multi-messenger approach to the science of compact object mergers and other transients. This talk will give an overview of the low-latency methodology and recent results.

  6. Operation of the upgraded ATLAS Central Trigger Processor during the LHC Run 2

    DEFF Research Database (Denmark)

    Bertelsen, H.; Montoya, G. Carrillo; Deviveiros, P. O.

    2016-01-01

    The ATLAS Central Trigger Processor (CTP) is responsible for forming the Level-1 trigger decision based on the information from the calorimeter and muon trigger processors. In order to cope with the increase of luminosity and physics cross-sections in Run 2, several components of this system have...

  7. M7--a high speed digital processor for second level trigger selections

    International Nuclear Information System (INIS)

    Droege, T.F.; Gaines, I.; Turner, K.J.

    1978-01-01

    A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

  8. Data driven processor 'Vertex Trigger' for B experiments

    International Nuclear Information System (INIS)

    Hartouni, E.P.

    1993-01-01

    Data Driven Processors (DDP's) are specialized computation engines configured to solve specific numerical problems, such as vertex reconstruction. The architecture of the DDP which is the subject of this talk was designed and implemented by W. Sippach and B.C. Knapp at Nevis Lab. in the early 1980's. This particular implementation allows multiple parallel streams of data to provide input to a heterogenous collection of simple operators whose interconnection form an algorithm. The local data flow control allows this device to execute algorithms extremely quickly provided that care is taken in the layout of the algorithm. I/O rates of several hundred megabytes/second are routinely achieved thus making DDP's attractive candidates for complex online calculations. The original question was open-quote can a DDP reconstruct tracks in a Silicon Vertex Detector, find events with a separated vertex and do it fast enough to be used as an online trigger?close-quote Restating this inquiry as three questions and describing the answers to the questions will be the subject of this talk. The three specific questions are: (1) Can an algorithm be found which reconstructs tracks in a planar geometry and no magnetic field; (2) Can separated vertices be recognized in some way; (3) Can the algorithm be implemented in the Nevis-UMass and DDP and execute in 10-20 μs?

  9. On-line trigger processor in PETRA/DORIS experiments at DESY

    CERN Document Server

    ölschläger, R

    1981-01-01

    Data, presented at a poster session, on on-line trigger processing are given. Brief details of trigger processors at the detectors CELLO, TASSO and ARAUS are shown, including: general working method; IC technology; power consumption; logic elements for trigger decision; number of chambers; number of input wires; execution time; parameter variation; links to host computer; cost; test features. (0 refs).

  10. A fast track trigger processor for the OPAL detector at LEP

    International Nuclear Information System (INIS)

    Carter, A.A.; Jaroslawski, S.; Wagner, A.

    1986-01-01

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented. (orig.)

  11. Mobile Low Latency Services in 5G

    DEFF Research Database (Denmark)

    Cattoni, Andrea Fabio; Chandramouli, Devaki; Sartori, Cinzia

    2015-01-01

    Networks beyond 2020 will experience 10000-fold increase in wireless traffic, connect 10-100 times more devices and support the most diverse use cases. Thus, the 5G architecture needs to be flexible and cater for both traffic volumes and diversity of service requirements. Among the set of new use...... cases, support of delay sensitive "mobile" applications, such as vehicular communications (V2X, where X stands for either Vehicle or Infrastructure), require architecture enhancements to natively offer low latency and high mobility. In this paper we propose the necessary technology enablers...

  12. A fast filter processor as a part of the trigger logic in an elastic scattering experiment

    International Nuclear Information System (INIS)

    Kenyon Gjerpe, I.

    1981-01-01

    A fast special purpose processor as a part of the trigger logic in an elastic scattering experiment is described. The decision to incorporate such a processor was taken because the trigger rate was estimated to be an order of magnitude higher than the date taking capability of the on-line minicomputer, a NORD 10. The processor is capable of checking the coplanarity and the opening angle of the two outgoing tracks within about 100 μs. This is done with a spatial resolution of 1 mm by using two points each track given by 3 MWPCs. For comparison this is two orders of magnitude faster than the same algorithm coded in assembly language on a PDP 11/40. The main contribution to this increased speed is due to extensive use of pipelining and parallelism. When running with the processor in the trigger, 75% more elastic events per incoming beam particle were collected, and 3 times as many elastic events per trigger were recorded on to tape for further in-depth analysis, than previously. Due to major improvements in the primary trigger logic this was less than the gain initially anticipated. A first version of the processor was designed and constructed in the CERN DD division by J. Joosten, M. Letheren and B. Martin under the supervision of C. Verkerk. The author was involved in the final design, construction and testing, and subsequently was responsible for the intergration, programming and running of the processor in the experiment. (orig.)

  13. Trigger processing using reconfigurable logic in the CMS calorimeter trigger

    Energy Technology Data Exchange (ETDEWEB)

    Brooke, J J; Cussans, D G; Heath, G P; Maddox, A J; Newbold, D M; Rabbetts, P D

    2001-04-01

    We present the design of the Global Calorimeter Trigger processor for the CMS detector at LHC. This is a fully pipelined processor system which collects data from all the CMS calorimeters and produces summary information used in forming the Level-1 trigger decision for each event. The design in based on the use of state-of-the-art reconfigurable logic devices (FPGAs) and fast data links. We present the results of device testing using a low-latency pipelined sort algorithm, which demonstrate that an FPGA can be used to perform processing previously foreseen to require custom ASICs. Our design approach results in a powerful, flexible and compact processor system.

  14. Level Zero Trigger processor for the ultra rare kaon decay experiment—NA62

    CERN Document Server

    Chiozzi, S; Gianoli, A; Mila, G; Neri, I; Petrucci, F; Soldi, D

    2016-01-01

    n the NA62 experiment at CERN-SPS the communication between detectors and the Lowest Level (L0) trigger processor is performed via Ethernet packets, using the UDP protocol. The L0 Trigger Processor handles the signals from sub-detectors that take part to the trigger generation. In order to choose the best solution for its realization, two different approaches have been implemented. The first approach is fully based on a FPGA device while the second one joins an off-the-shelf PC to the FPGA. The performance of the two systems will be discussed and compared.

  15. Graphics Processors in HEP Low-Level Trigger Systems

    International Nuclear Information System (INIS)

    Ammendola, Roberto; Biagioni, Andrea; Chiozzi, Stefano; Ramusino, Angelo Cotta; Cretaro, Paolo; Lorenzo, Stefano Di; Fantechi, Riccardo; Fiorini, Massimiliano; Frezza, Ottorino; Lamanna, Gianluca; Cicero, Francesca Lo; Lonardo, Alessandro; Martinelli, Michele; Neri, Ilaria; Paolucci, Pier Stanislao; Pastorelli, Elena; Piandani, Roberto; Pontisso, Luca; Rossetti, Davide; Simula, Francesco; Sozzi, Marco; Vicini, Piero

    2016-01-01

    Usage of Graphics Processing Units (GPUs) in the so called general-purpose computing is emerging as an effective approach in several fields of science, although so far applications have been employing GPUs typically for offline computations. Taking into account the steady performance increase of GPU architectures in terms of computing power and I/O capacity, the real-time applications of these devices can thrive in high-energy physics data acquisition and trigger systems. We will examine the use of online parallel computing on GPUs for the synchronous low-level trigger, focusing on tests performed on the trigger system of the CERN NA62 experiment. To successfully integrate GPUs in such an online environment, latencies of all components need analysing, networking being the most critical. To keep it under control, we envisioned NaNet, an FPGA-based PCIe Network Interface Card (NIC) enabling GPUDirect connection. Furthermore, it is assessed how specific trigger algorithms can be parallelized and thus benefit from a GPU implementation, in terms of increased execution speed. Such improvements are particularly relevant for the foreseen Large Hadron Collider (LHC) luminosity upgrade where highly selective algorithms will be essential to maintain sustainable trigger rates with very high pileup

  16. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; Buscher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; Mattig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Schafer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nuclear Research (CERN) in Switzerland. It is designed to observe phenomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4 10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 micro seconds. It is primarily composed of the Calori...

  17. Topological and Central Trigger Processor for 2014 LHC luminosities

    CERN Document Server

    Simioni, E; The ATLAS collaboration; Bauss, B; Berge, D; B\\"{u}scher, V; Childers, T; Degele, R; Dobson, E; Ebling, A; Ellis, N; Farthouat, P; Gabaldon, C; Gorini, B; Haas, S; Ji, W; Kaneda, M; M\\"{a}ttig, S; Messina, A; Meyer, C; Moritz, S; Pauly, T; Pottgen, R; Sch\\"{a}fer, U; Spiwoks, R; Tapprogge, S; Wengler, T; Wenzel, V

    2012-01-01

    The ATLAS experiment is located at the European Center for Nu- clear Research (CERN) in Switzerland. It is designed to observe phe- nomena that involve highly massive particles produced in the collisions at the Large Hadron Collider (LHC): the world’s largest and highest-energy particle accelerator. Event triggering and Data Acquisition is one of the extraordinary challenges faced by the detectors at the high luminosity LHC collider. During 2011, the LHC reached instantaneous luminosities of 4×10^33 cm−1 s−1 and produced events with up to 24 interactions per colliding proton bunch. This places stringent operational and physical requirements on the AT- LAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 400Hz and, at the same time, selecting those events considered interesting. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5μs. It is primarily composed of the Calorimete...

  18. FPGA Co-processor for the ALICE High Level Trigger

    CERN Document Server

    Grastveit, G.; Lindenstruth, V.; Loizides, C.; Roehrich, D.; Skaali, B.; Steinbeck, T.; Stock, R.; Tilsner, H.; Ullaland, K.; Vestbo, A.; Vik, T.

    2003-01-01

    The High Level Trigger (HLT) of the ALICE experiment requires massive parallel computing. One of the main tasks of the HLT system is two-dimensional cluster finding on raw data of the Time Projection Chamber (TPC), which is the main data source of ALICE. To reduce the number of computing nodes needed in the HLT farm, FPGAs, which are an intrinsic part of the system, will be utilized for this task. VHDL code implementing the Fast Cluster Finder algorithm, has been written, a testbed for functional verification of the code has been developed, and the code has been synthesized

  19. Continuously live image processor for drift chamber track segment triggering

    International Nuclear Information System (INIS)

    Berenyi, A.; Chen, H.K.; Dao, K.

    1999-01-01

    The first portion of the BaBar experiment Level 1 Drift Chamber Trigger pipeline is the Track Segment Finder (TSF). Using a novel method incorporating both occupancy and drift-time information, the TSF system continually searches for segments in the supercells of the full 7104-wire Drift Chamber hit image at 3.7 MHz. The TSF was constructed to operate in a potentially high beam-background environment while achieving high segment-finding efficiency, deadtime-free operation, a spatial resolution of 5 simulated physics events

  20. The ATLAS Muon to Central Trigger Processor Interface Upgrade for the Run 3 of the LHC

    CERN Document Server

    Armbruster, Aaron James; The ATLAS collaboration; Chelstowska, Magda Anna

    2017-01-01

    To cope with the higher luminosity and physics cross-sections for the third run of the Large Hadron Collider (LHC) and beyond, the Trigger and Data Acquisition (TDAQ) system of ATLAS experiment at CERN is being upgraded. Part of the TDAQ system, the Muon to Central Trigger Processor Interface (MUCTPI) receives muon candidates information from each of the 208 barrel and endcap muon trigger sectors, counts muon candidates for each transverse momentum threshold and sends the result to the Central Trigger Processor (CTP). The MUCTPI takes into account the possible overlap between trigger sectors in order to avoid double counting of muon candidates. A full redesign and replacement of the existing MUCTPI is required in order to provide full-granularity muon position information at the bunch crossing rate to the Topological Trigger processor (L1Topo) and to be able to interface with the new sector logic modules. State-of-the-art FPGA technology and high-density ribbon fiber-optic transmitters and receivers is being...

  1. Upgrade of the ATLAS Level‐1 trigger with an FPGA based Topological Processor

    CERN Document Server

    Caputo, R; The ATLAS collaboration; Buescher, V; Degele, R; Kiese, P; Maldaner, S; Reiss, A; Schaefer, U; Simioni, E; Tapprogge, S; Urejola, P

    2013-01-01

    The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). LHC proton collision at a frequency of 40 MHz, requires a trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\\mu$s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3$\\times$10$^{34}$cm$^{−2}$s$^{−1}$ in 2015, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receive data in a dedicated format from the calorimeters ...

  2. The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

    CERN Document Server

    Simioni, E; The ATLAS collaboration

    2014-01-01

    The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of highly energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a beam collision frequency of 40 MHz, and thus requires a trigger system to efficiently select events, thereby reducing the storage rate to a manageable level of about 400 Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5 s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up 3 x 10^34/cm2 s from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a specialized format from the ...

  3. Upgrade of the ATLAS Level-1 trigger with an FPGA based Topological Processor

    CERN Document Server

    Caputo, R; The ATLAS collaboration; Buescher, V; Degele, R; Kiese, P; Maldaner, S; Reiss, A; Schaefer, U; Simioni, E; Tapprogge, S; Urrejola, P

    2013-01-01

    The ATLAS experiment is located at the European Centre for Nuclear Research (CERN) in Switzerland. It is designed to measure decay properties of high energetic particles produced in the protons collisions at the Large Hadron Collider (LHC). The LHC has a proton collision at a frequency of 40 MHz, and thus requires a trigger system to efficiently select events down to a manageable event storage rate of about 400Hz. Event triggering is therefore one of the extraordinary challenges faced by the ATLAS detector. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 75kHz and decision latency of less than 2.5$\\mu$s. It is primarily composed of the Calorimeter Trigger, Muon Trigger, the Central Trigger Processor (CTP). Due to the increase in the LHC instantaneous luminosity up to 3$\\times$10$^{34}$ cm$^{−2}$ s$^{−1}$ from 2015 onwards, a new element will be included in the Level-1 Trigger scheme: the Topological Processor (L1Topo). The L1Topo receives data in a dedicate...

  4. Development of the new trigger processor board for the ATLAS Level-1 endcap muon trigger for Run-3

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00525035; The ATLAS collaboration

    2017-01-01

    The instantaneous luminosity of the LHC will be increased by up to a factor of three with respect to the original design value at Run-3 (starting 2021). The ATLAS Level-1 end-cap muon trigger in LHC Run-3 will identify muons by combining data from the Thin-Gap Chamber detector (TGC) and the New Small Wheel (NSW), which is a new detector and will be able to operate in a high background hit rate at Run-3, to suppress the Level-1 trigger rate. In order to handle data from both TGC and NSW, a new trigger processor board has been developed. The board has a modern FPGA to make use of Multi-Gigabit transceiver technology. The readout system for trigger data has also been designed with TCP/IP instead of a dedicated ASIC. This letter presents the electronics and its firmware of the ATLAS Level-1 end-cap muon trigger processor board for LHC Run-3.

  5. ATLAS Level-1 Calorimeter Trigger Subsystem Tests of a Prototype Cluster Processor Module

    CERN Document Server

    Garvey, J; Apostologlou, P; Ay, C; Barnett, B M; Bauss, B; Brawn, I P; Bohm, C; Dahlhoff, A; Davis, A O; Edwards, J; Eisenhandler, E F; Gee, C N P; Gillman, A R; Hanke, P; Hellman, S; Hidévgi, A; Hillier, S J; Jakobs, K; Kluge, E E; Landon, M; Mahboubi, K; Mahout, G; Meier, K; Meshkov, P; Moye, T H; Mills, D; Moyse, E; Nix, O; Penno, K; Perera, V J O; Qian, W; Schmitt, K; Schäfer, U; Silverstein, S; Staley, R J; Thomas, J; Trefzger, T M; Watkins, P M; Watson, A; 9th Workshop On Electronics For LHC Experiments - LECC 2003

    2003-01-01

    The Level-1 Calorimeter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce trigger multiplicity and Region-of-Interest (RoI) information. The trigger will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes by using Readout Driver (ROD) Modules. The CP Modules (CPM) are designed to find isolated electron/photon and hadron/tau clusters in overlapping windows of trigger towers. Each pipelined CPM processes 8-bit data from a total of 128 trigger towers at each LHC crossing. Four full-specification prototypes of CPMs have been built and results of complete tests on individual boards will be presented. These modules were then integrated with other modules to build an ATLAS Level-1 Calorimeter Trigger subsystem test bench. Realtime data were exchanged between modules, and time-slice readout data were tagged and transferr...

  6. Upgrade of the PreProcessor System for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Khomich, A

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5\\,us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serialisers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

  7. Upgrade of the PreProcessor System for the ATLAS LVL1 Calorimeter Trigger

    CERN Document Server

    Khomich, A; The ATLAS collaboration

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger is a hardware-based pipelined system designed to identify high-pT objects in the ATLAS calorimeters within a fixed latency of 2.5us. It consists of three subsystems: the PreProcessor which conditions and digitizes analogue signals and two digital processors. The majority of the PreProcessor's tasks are performed on a dense Multi-Chip Module(MCM) consisting of FADCs, a time-adjustment and digital processing ASICs, and LVDS serializers designed and implemented in ten years old technologies. An MCM substitute, based on today's components (dual channel FADCs and FPGA), is being developed to profit from state-of-the-art electronics and to enhance the flexibility of the digital processing. Development and first test results are presented.

  8. Fast track-finding trigger processor for the SLAC/LBL Mark II Detector

    International Nuclear Information System (INIS)

    Brafman, H.; Breidenbach, M.; Hettel, R.; Himel, T.; Horelick, D.

    1977-10-01

    The SLAC/LBL Mark II Magnetic Detector consists of various particle detectors arranged in cylindrical symmetry located in and around an axial magnetic field. A versatile, programmable secondary trigger processor was designed and built to find curved tracks in the detector. The system operates at a 10 MHz clock rate with a total processing time of 34 μsec and is used to ''trigger'' the data processing computer, thereby rejecting background and greatly improving the data acquisition aspects of the detector-computer combination

  9. The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Silverstein, S

    2010-01-01

    The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

  10. The Digital Algorithm Processors for the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Silverstein, S; The ATLAS collaboration

    2009-01-01

    The ATLAS Level-1 Calorimeter Trigger identifies high-ET jets, electrons/photons and hadrons and measures total and missing transverse energy in proton-proton collisions at the Large Hadron Collider. Two subsystems – the Jet/Energy-sum Processor (JEP) and the Cluster Processor(CP) – process data from every crossing, and report feature multiplicities and energy sums to the ATLAS Central Trigger Processor, which produces a Level-1 Accept decision. Locations and types of identified features are read out to the Level-2 Trigger as regions-of-interest, and quality-monitoring information is read out to the ATLAS data acquisition system. The JEP and CP subsystems share a great deal of common infrastructure, including a custom backplane, several common hardware modules, and readout hardware. Some of the common modules use FPGAs with selectable firmware configurations based on the location in the system. This approach saved substantial development effort and provided a uniform model for software development. We pre...

  11. Firmware implementation of algorithms for the new topological processor in the ATLAS first level trigger

    Energy Technology Data Exchange (ETDEWEB)

    Maldaner, Stephan; Caputo, Regina; Schaefer, Ulrich; Tapprogge, Stefan [Universitaet Mainz, Staudingerweg 7, 55128 Mainz (Germany)

    2013-07-01

    After the upgrade of the Large Hadron Collider in 2013/2014 proton-proton collisions will be provided at a center-of-mass energy of up to 14 TeV with an instantaneous luminosity of at least 1 . 10{sup 34} cm{sup -2}s{sup -1}. During this upgrade a new FPGA based electronics system (Topological Processor) will be included in the ATLAS trigger chain to keep up with the increased rate of events. To reduce rates while maintaining high signal efficiency of the trigger the processor will make its decisions based upon topological criteria like angular cuts and mass calculations. As a hardware based trigger, it will have to fit into the tight first level trigger latency budget of 2.5 μs and thus provides the challenge of making decisions within very short time. Beside the latency, the main constraints on the algorithms are the required amount of logic resources of the FPGA which will be implemented as firmware. Therefore to be able to use as much information as possible, each module will be equipped with 2 state-of-the-art Xilinx Virtex 7 FPGAs to process the incoming data. This talk will present some of the topological algorithms and discuss properties of their implementation in firmware.

  12. Programmable level-1 trigger with 3D-Flow processor array

    International Nuclear Information System (INIS)

    Crosetto, D.

    1994-01-01

    The 3D-Flow parallel processing system is a new concept in processor architecture, system architecture, and assembly architecture. Compared to the electronics used in present systems, this approach reduces the cost and complexity of the hardware and allows easy assembly, disassembly, incremental upgrading, and maintenance of different interconnection topologies. The 3D-Flow parallel-processing system benefits high energy physics (HEP) by allowing: (1) common less costly hardware to be used in different experiments. (2) new uses of existing installations. (3) tuning of trigger based on the first analyzed data, and (4) selection of desired events directly from raw data. The goal of this parallel-processing architecture is to acquire multiple data in parallel (up to 100 million frames per second) and to process them at high speed, accomplishing digital filtering on the input data, pattern recognition (particle identification), data moving, and data formatting. The main features of the system are its programmability, scalability, high-speed communication, and low cost. The compactness of the 3D-Flow parallel-processing system in concert with the processor architecture allows processor interconnections to be mapped into the geometry of sensors (detectors in HEP) without large interconnection signal delay, enabling real-time pattern recognition. The overall 3D-Flow project has passed a major design review at Fermilab (Reviewers included experts in computers, triggering, system assembly, and electronics)

  13. Smart Trigger Pre-Processor Custom Electronics for the PHENIX Experiment

    International Nuclear Information System (INIS)

    Nagle, James L.

    2003-01-01

    OAK-B135 The document provides a final technical report on activities and accomplishments of the experimental relativistic heavy ion physics group at the University of Colorado at Boulder as supported by the Outstanding Junior Investigator Program, Division of Nuclear Physics at the Department of Energy. All of the goals of the grant proposal were achieved during this last year of the Outstanding Junior Investigator funding period. The development of a Smart Trigger Pre-Processor module for fast trigger primitive calculations in the PHENIX experiment has been completed. We finalized the board design, constructed and tested two prototype modules, and with additional funding from the PHENIX project, we fabricated a full set of 15 modules for the Muon Tracking system. During Run-4 at RHIC:, we have begun the process of integrating these modules into the PHENIX data acquisition system, Additionally, we put a large Effort into developing new trigger and fast-track analysis methods for J j J data filtering and reconstruction. These algorithms make use of the trigger primitivE∼s generated via the new electronics

  14. Design and performance of a high resolution, low latency stripline beam position monitor system

    Science.gov (United States)

    Apsimon, R. J.; Bett, D. R.; Blaskovic Kraljevic, N.; Burrows, P. N.; Christian, G. B.; Clarke, C. I.; Constance, B. D.; Dabiri Khah, H.; Davis, M. R.; Perry, C.; Resta López, J.; Swinson, C. J.

    2015-03-01

    A high-resolution, low-latency beam position monitor (BPM) system has been developed for use in particle accelerators and beam lines that operate with trains of particle bunches with bunch separations as low as several tens of nanoseconds, such as future linear electron-positron colliders and free-electron lasers. The system was tested with electron beams in the extraction line of the Accelerator Test Facility at the High Energy Accelerator Research Organization (KEK) in Japan. It consists of three stripline BPMs instrumented with analogue signal-processing electronics and a custom digitizer for logging the data. The design of the analogue processor units is presented in detail, along with measurements of the system performance. The processor latency is 15.6 ±0.1 ns . A single-pass beam position resolution of 291 ±10 nm has been achieved, using a beam with a bunch charge of approximately 1 nC.

  15. The processor farm for online triggering and full event reconstruction of the HERA-B experiment at HERA

    International Nuclear Information System (INIS)

    Gellrich, A.; Dippel, R.; Gensch, U.; Kowallik, R.; Legrand, I.C.; Leich, H.; Sun, F.; Wegner, P.

    1996-01-01

    The main goal of the HERA-B experiment which start taking data in 1988 is to study CP violation in B decays. This article describes the concept and the planned implementation of a multi-processor system, called processor farm,as the last part of the data acquisition and trigger system of the HERA B experiment. The third level trigger task and a full online event reconstruction will be performed on this processor farm, consisting of more then 100 powerful RISC processors which are based on commercial hardware boards. The controlling will be done by a real-time operating system which provides a software development environment, including FORTRAN and C compilers. (author)

  16. Scalla: Structured Cluster Architecture for Low Latency Access

    Energy Technology Data Exchange (ETDEWEB)

    Hanushevsky, Andrew; Wang, Daniel L.; /SLAC

    2012-03-20

    Scalla is a distributed low-latency file access system that incorporates novel techniques that minimize latency and maximize scalability over a large distributed system with a distributed namespace. Scalla's techniques have shown to be effective in nearly a decade of service for the high-energy physics community using commodity hardware and interconnects. We describe the two components used in Scalla that are instrumental in its ability to provide low-latency, fault-tolerant name resolution and load distribution, and enable its use as a high-throughput, low-latency communication layer in the Qserv system, the Large Synoptic Survey Telescope's (LSST's) prototype astronomical query system. Scalla arguably exceeded its three main design objectives: low latency, scaling, and recoverability. In retrospect, these objectives were met using a simple but effective design. Low latency was met by uniformly using linear or constant time algorithms in all high-use paths, avoiding locks whenever possible, and using compact data structures to maximize the memory caching efficiency. Scaling was achieved by architecting the system as a 64-ary tree. Nodes can be added easily and as the number of nodes increases, search performance increases at an exponential rate. Recoverability is inherent in that no permanent state information is maintained and whatever state information is needed it can be quickly constructed or reconstructed in real time. This allows dynamic changes in a cluster of servers with little impact on over-all performance or usability. Today, Scalla is being deployed in environments and for uses that were never conceived in 2001. This speaks well for the systems adaptability but the underlying reason is that the system can meet its three fundamental objectives at the same time.

  17. Low-latency data analysis for the spherical detector Mario Schenberg

    International Nuclear Information System (INIS)

    Costa, Carlos Filipe Da Silva; Costa, César Augusto; Aguiar, Odylio Denys

    2014-01-01

    The confrontation of gravitational waves (GWs) with their electromagnetic (EM) counterparts will be rich with information about astrophysical events. Initially, this confrontation will corroborate GW detections; afterwards, when GW detections become more recurrent, it will allow astrophysics to combine information from different channels (GW, EM and also neutrinos). A low-latency data analysis which provides the direction of an incoming GW candidate is required to confront it with fast follow-up EM observations. Until now, no low-latency data analysis has been developed for spherical detectors. One spherical detector alone is capable of determining both the GW direction and polarization. By using this capability, we have developed a low-latency data analysis pipeline for the Mario Schenberg detector. This pipeline is able to retrieve the direction of GW triggers with an average angular resolution from δs ∼ 8° at SNR ∼ 12 to δs ∼ 1° at SNR ∼ 80, in a timespan of a 4 s for 32 s of data being analyzed. We apply a veto which reduces fake events up to 90% when maintaining the GW efficiency above 90% for high SNRs. We provide here a description of the method and its efficiency: resolution on the direction, false alarm rate and computational time. (paper)

  18. arXiv Level Zero Trigger Processor for the NA62 experiment

    CERN Document Server

    INSPIRE-00584493; Chiozzi, Stefano

    2018-05-02

    The NA62 experiment is designed to measure the ultra-rare decay K+ arrow π+ ν  branching ratio with a precision of ~ 10% at the CERN Super Proton Synchrotron (SPS). The trigger system of NA62 consists in three different levels designed to select events of physics interest in a high beam rate environment. The L0 Trigger Processor (L0TP) is the lowest level system of the trigger chain. It is hardware implemented using programmable logic. The architecture of the NA62 L0TP system is a new approach compared to existing systems used in high-energy physics experiments. It is fully digital, based on a standard gigabit Ethernet communication between detectors and the L0TP Board. The L0TP Board is a commercial development board, mounting a programmable logic device (FPGA). The primitives generated by sub-detectors are sent asynchronously using the UDP protocol to the L0TP during the entire beam spill period. The L0TP realigns in time the primitives coming from seven different sources and performs a data selectio...

  19. The Topological Processor for the future ATLAS Level-1 Trigger: from design to commissioning

    CERN Document Server

    Simioni, E; The ATLAS collaboration

    2014-01-01

    The ATLAS detector at the Large Hadron Collider (LHC) is designed to measure decay properties of high energetic particles produced in the proton-proton collisions. During its first run, the LHC collided proton bunches at a frequency of 20 MHz, and therefore the detector required a Trigger system to efficiently select events down to a manageable event storage rate of about 400 Hz. By 2015 the LHC instantaneous luminosity will be increased up to 3$\\times$$10^{34}cm^{-2}s^{-1}$: this represent an unprecedented challenge faced by the ATLAS Trigger system. To cope with the higher event rate and efficiently select relevant events from physics point of view, a new element will be included in the Level-1 Trigger scheme after 2015: the Topological Processor (L1Topo).\\\\ The L1Topo system, currently developed at CERN, will consist initially of an ATCA crate and two L1Topo modules. A high density opto-electroconverter (AVAGO miniPOD) drives up to 1.6 Tb/s of data from the calorimeter and muon detectors into two high end ...

  20. A Fastbus module for trigger applications based on a digital signal processor and on programmable gate arrays

    International Nuclear Information System (INIS)

    Battaiotto, P.; Colavita, A.; Fratnik, F.; Lanceri, L.; Udine Univ.

    1991-01-01

    The new generation of DSP microprocessors based on RISC and Harvard-like architectures can conveniently take the place of specially built processors in fast trigger circuits for high-energy physics experiments. Presently available programmable gate arrays are well matched to them in speed and contribute to simplify the design of trigger circuits. Using these components, we designed and constructed a Fastbus module. We describe an application for the total-energy trigger of DELPHI, performing the readout of digitized calorimeter trigger data and some simple computations in less than 3 μs. (orig.)

  1. Low-latency situational awareness for UxV platforms

    Science.gov (United States)

    Berends, David C.

    2012-06-01

    Providing high quality, low latency video from unmanned vehicles through bandwidth-limited communications channels remains a formidable challenge for modern vision system designers. SRI has developed a number of enabling technologies to address this, including the use of SWaP-optimized Systems-on-a-Chip which provide Multispectral Fusion and Contrast Enhancement as well as H.264 video compression. Further, the use of salience-based image prefiltering prior to image compression greatly reduces output video bandwidth by selectively blurring non-important scene regions. Combined with our customization of the VLC open source video viewer for low latency video decoding, SRI developed a prototype high performance, high quality vision system for UxV application in support of very demanding system latency requirements and user CONOPS.

  2. HyspIRI Low Latency Concept and Benchmarks

    Science.gov (United States)

    Mandl, Dan

    2010-01-01

    Topics include HyspIRI low latency data ops concept, HyspIRI data flow, ongoing efforts, experiment with Web Coverage Processing Service (WCPS) approach to injecting new algorithms into SensorWeb, low fidelity HyspIRI IPM testbed, compute cloud testbed, open cloud testbed environment, Global Lambda Integrated Facility (GLIF) and OCC collaboration with Starlight, delay tolerant network (DTN) protocol benchmarking, and EO-1 configuration for preliminary DTN prototype.

  3. The ATLAS Muon-to-Central Trigger Processor Interface Upgrade for the Run 3 of the LHC

    CERN Document Server

    Armbruster, Aaron James; The ATLAS collaboration

    2017-01-01

    To cope with the higher luminosity and physics cross-sections for the third run of the Large Hadron Collider (LHC) and beyond, the Trigger and Data Acquisition (TDAQ) system of ATLAS experiment at CERN is being upgraded. Part of the TDAQ system, the Muon to Central Trigger Processor Interface (MUCTPI) receives muon candidates information from each of the 208 barrel and endcap muon trigger sectors, counts muon candidates for each transverse momentum threshold and sends the result to the Central Trigger Processor (CTP). The MUCTPI takes into account the possible overlap between trigger sectors in order to avoid double counting of muon candidates. A full redesign and replacement of the existing MUCTPI is required in order to provide full-granularity muon position information at the bunch crossing rate to the Topological Trigger processor (L1Topo) and to be able to interface with the new sector logic modules. State-of-the-art FPGA technology and high-density ribbon fiber-optic transmitters and receivers is being...

  4. 3D-LIN: A Configurable Low-Latency Interconnect for Multi-Core Clusters with 3D Stacked L1 Memory

    OpenAIRE

    Beanato, Giulia; Loi, Igor; De Micheli, Giovanni; Leblebici, Yusuf; Benini, Luca

    2012-01-01

    Shared L1 memories are of interest for tightly- coupled processor clusters in programmable accelerators as they provide a convenient shared memory abstraction while avoiding cache coherence overheads. The performance of a shared-L1 memory critically depends on the architecture of the low-latency interconnect between processors and memory banks, which needs to provide ultra-fast access to the largest possible L1 working set. The advent of 3D technology provides new opportunities to improve the...

  5. An FPGA based demonstrator for a topological processor in the future ATLAS L1-Calo trigger “GOLD”

    CERN Document Server

    Ebling, A; Büscher, V; Degele, R; Ji, W; Meyer, C; Moritz, S; Schäfer, U; Simioni, E; Tapprogge, S; Wenzel, V

    2012-01-01

    Abstract: The existing ATLAS trigger consists of three levels. The level 1 (L1) is an FPGAs based custom designed trigger, while the second and third levels are software based. The LHC machine plans to bring the beam energy to the maximum value of 7 TeV and to increase the luminosity in the coming years. The current L1 trigger system is therefore seriously challenged. To cope with the resulting higher event rate, as part of the ATLAS trigger upgrade, a new electronics module is foreseen to be added in the ATLAS Level-1 Calorimeter Trigger electronics chain: the Topological Processor (TP). Such a processor needs fast optical I/O and large aggregate bandwidth to use the information on trigger object position in space (e.g. jets in the calorimeters or muons measured in the muon detectors) to improve the purity of the L1 triggers streams by applying topological cuts within the L1 latency budget. In this paper, an overview of the adopted technological solutions and the R&D activities on the demonstrator for th...

  6. Track recognition in 4 μs by a systolic trigger processor using a parallel Hough transform

    International Nuclear Information System (INIS)

    Klefenz, F.; Noffz, K.H.; Conen, W.; Zoz, R.; Kugel, A.; Maenner, R.; Univ. Heidelberg

    1993-01-01

    A parallel Hough transform processor has been developed that identifies circular particle tracks in a 2D projection of the OPAL jet chamber. The high-speed requirements imposed by the 8 bunch crossing mode of LEP could be fulfilled by computing the starting angle and the radius of curvature for each well defined track in less than 4 μs. The system consists of a Hough transform processor that determines well defined tracks, and a Euler processor that counts their number by applying the Euler relation to the thresholded result of the Hough transform. A prototype of a systolic processor has been built that handles one sector of the jet chamber. It consists of 35 x 32 processing elements that were loaded into 21 programmable gate arrays (XILINX). This processor runs at a clock rate of 40 MHz. It has been tested offline with about 1,000 original OPAL events. No deviations from the off-line simulation have been found. A trigger efficiency of 93% has been obtained. The prototype together with the associated drift time measurement unit has been installed at the OPAL detector at LEP and 100k events have been sampled to evaluate the system under detector conditions

  7. Design and performance of a high resolution, low latency stripline beam position monitor system

    Directory of Open Access Journals (Sweden)

    R. J. Apsimon

    2015-03-01

    Full Text Available A high-resolution, low-latency beam position monitor (BPM system has been developed for use in particle accelerators and beam lines that operate with trains of particle bunches with bunch separations as low as several tens of nanoseconds, such as future linear electron-positron colliders and free-electron lasers. The system was tested with electron beams in the extraction line of the Accelerator Test Facility at the High Energy Accelerator Research Organization (KEK in Japan. It consists of three stripline BPMs instrumented with analogue signal-processing electronics and a custom digitizer for logging the data. The design of the analogue processor units is presented in detail, along with measurements of the system performance. The processor latency is 15.6±0.1  ns. A single-pass beam position resolution of 291±10  nm has been achieved, using a beam with a bunch charge of approximately 1 nC.

  8. 3D-Flow processor for a programmable Level-1 trigger (feasibility study)

    International Nuclear Information System (INIS)

    Crosetto, D.

    1992-10-01

    A feasibility study has been made to use the 3D-Flow processor in a pipelined programmable parallel processing architecture to identify particles such as electrons, jets, muons, etc., in high-energy physics experiments

  9. Multi­-Threaded Algorithms for General purpose Graphics Processor Units in the ATLAS High Level Trigger

    CERN Document Server

    Conde Mui\\~no, Patricia; The ATLAS collaboration

    2016-01-01

    General purpose Graphics Processor Units (GPGPU) are being evaluated for possible future inclusion in an upgraded ATLAS High Level Trigger farm. We have developed a demonstrator including GPGPU implementations of Inner Detector and Muon tracking and Calorimeter clustering within the ATLAS software framework. ATLAS is a general purpose particle physics experiment located on the LHC collider at CERN. The ATLAS Trigger system consists of two levels, with level 1 implemented in hardware and the High Level Trigger implemented in software running on a farm of commodity CPU. The High Level Trigger reduces the trigger rate from the 100 kHz level 1 acceptance rate to 1 kHz for recording, requiring an average per­-event processing time of ~250 ms for this task. The selection in the high level trigger is based on reconstructing tracks in the Inner Detector and Muon Spectrometer and clusters of energy deposited in the Calorimeter. Performing this reconstruction within the available farm resources presents a significant ...

  10. SDN Low Latency for Medical Big Data Using Wavelets

    Directory of Open Access Journals (Sweden)

    Fadia Shah

    2017-06-01

    Full Text Available New era is the age of 5G. The network has moved from the simple internet connection towards advanced LTE connections and transmission. The information and communication technology has reshaped telecommunication. For this, among many types of big data, Medical Big Data is one of the most sensitive forms of data. Wavelet is a technical tool to reduce the size of this data to make it available for the user for more time. It is also responsible for low latency and high speed data transmission over the network. The key concern is the Medical Big Data should be accurate and reliable enough so that the recommended treatment should be the concerned one. This paper proposed the scheme to support the concept of data availability without losing crucial information, via Wavelet the Medical Data compression and through SDN supportive architecture by making data availability over the wireless network. Such scheme is in favor of the efficient use of technology for the benefit of human beings in the support of medical treatments.

  11. Integer-valued Lévy processes and low latency financial econometrics

    DEFF Research Database (Denmark)

    Barndorff-Nielsen, Ole; Pollard, David G.; Shephard, Neil

    Motivated by features of low latency data in financial econometrics we study in detail integervalued Lévy processes as the basis of price processes for high frequency econometrics. We propose using models built out of the difference of two subordinators. We apply these models in practice to low...... latency data for a variety of different types of futures contracts.futures markets, high frequency econometrics, low latency data, negative binomial, Skellam, tempered stable...

  12. Trigger Algorithms and Electronics for the ATLAS Muon NSW Upgrade

    CERN Document Server

    Guan, Liang; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW), comprising MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), will upgrade the ATLAS muon system for a high background environment. Particularly, the NSW trigger will reduce the rate of fake triggers coming from background tracks in the endcap. We will present an overview of the FPGA-based trigger processor for NSW and trigger algorithms for sTGC and Micromegas detector sub systems. In additional, we will present development of NSW trigger electronics, in particular, the sTGC Trigger Data Serializer (TDS) ASIC, sTGC Pad Trigger board, the sTGC data packet router and L1 Data Driver Card. Finally, we will detail the challenges of meeting the low latency requirements of the trigger system and coping with the high background rates of the HL-LHC.

  13. Tap Arduino: An Arduino microcontroller for low-latency auditory feedback in sensorimotor synchronization experiments.

    Science.gov (United States)

    Schultz, Benjamin G; van Vugt, Floris T

    2016-12-01

    Timing abilities are often measured by having participants tap their finger along with a metronome and presenting tap-triggered auditory feedback. These experiments predominantly use electronic percussion pads combined with software (e.g., FTAP or Max/MSP) that records responses and delivers auditory feedback. However, these setups involve unknown latencies between tap onset and auditory feedback and can sometimes miss responses or record multiple, superfluous responses for a single tap. These issues may distort measurements of tapping performance or affect the performance of the individual. We present an alternative setup using an Arduino microcontroller that addresses these issues and delivers low-latency auditory feedback. We validated our setup by having participants (N = 6) tap on a force-sensitive resistor pad connected to the Arduino and on an electronic percussion pad with various levels of force and tempi. The Arduino delivered auditory feedback through a pulse-width modulation (PWM) pin connected to a headphone jack or a wave shield component. The Arduino's PWM (M = 0.6 ms, SD = 0.3) and wave shield (M = 2.6 ms, SD = 0.3) demonstrated significantly lower auditory feedback latencies than the percussion pad (M = 9.1 ms, SD = 2.0), FTAP (M = 14.6 ms, SD = 2.8), and Max/MSP (M = 15.8 ms, SD = 3.4). The PWM and wave shield latencies were also significantly less variable than those from FTAP and Max/MSP. The Arduino missed significantly fewer taps, and recorded fewer superfluous responses, than the percussion pad. The Arduino captured all responses, whereas at lower tapping forces, the percussion pad missed more taps. Regardless of tapping force, the Arduino outperformed the percussion pad. Overall, the Arduino is a high-precision, low-latency, portable, and affordable tool for auditory experiments.

  14. An FPGA-based trigger processor for a measurement of deeply virtual Compton scattering at the COMPASS-II experiment

    Energy Technology Data Exchange (ETDEWEB)

    Schopferer, Sebastian

    2013-12-16

    The COMPASS-II experiment at CERN is focusing on a measurement of the deeply virtual Compton scattering. Several upgrades of the experimental setup have been performed in 2012, namely the construction of a long liquid hydrogen target and a surrounding recoil proton detector called CAMERA. Based on a time-of-flight measurement between two barrels of scintillators, the CAMERA detector allows to detect protons with a kinetic energy down to 35 MeV, which leave the target under large polar angles. At the same time, protons can be distinguished from other particles resulting from background processes by means of an energy loss measurement in the scintillating material. In order to extend the existing COMPASS trigger scheme, a digital trigger system has been developed, which is detailed in the thesis at hand. The trigger system is able to select events with a recoil proton in the final state while suppressing background events, using the particle identification capabilities of the CAMERA detector. Challenging selection criteria based on both the time-of-flight and the energy loss measurement call for a powerful programmable logic board. At the same time, the integration into the existing COMPASS trigger system poses strict constraints on the latency of the trigger decision. For the implementation of the proton trigger system, a new FPGA-based trigger and DAQ hardware called TIGER has been built. The module is operated in two firmware configurations, serving two distinct purposes. Firstly, the trigger processor is responsible for the generation of a trigger signal based on recoil particles, which is included in the global first-level trigger decision. Secondly, a readout concentrator allows to multiplex the data streams of up to 18 readout modules into one link to the DAQ. The CAMERA detector and the corresponding readout and trigger electronics was commissioned during a test run in autumn 2012. This thesis contains details about the trigger concept, the development of the

  15. Run Control Communication for the Upgrade of the ATLAS Muon-to-Central-Trigger-Processor Interface (MUCTPI)

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00223859; The ATLAS collaboration; Armbruster, Aaron James; Carrillo-Montoya, German D.; Chelstowska, Magda Anna; Czodrowski, Patrick; Deviveiros, Pier-Olivier; Eifert, Till; Ellis, Nicolas; Galster, Gorm Aske Gram Krohn; Haas, Stefan; Helary, Louis; Lagkas Nikolos, Orestis; Marzin, Antoine; Pauly, Thilo; Ryjov, Vladimir; Schmieden, Kristof; Silva Oliveira, Marcos Vinicius; Stelzer, Harald Joerg; Vichoudis, Paschalis; Wengler, Thorsten; Farthouat, Philippe

    2018-01-01

    The Muon-to-Central Trigger Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used the SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the Yocto/OpenEmbedded framework. This approach was successfully...

  16. Run control communication for the upgrade of the ATLAS Muon-to-Central Trigger Processor Interface (MUCTPI)

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00223859; The ATLAS collaboration; Armbruster, Aaron James; Carrillo-Montoya, German D.; Chelstowska, Magda Anna; Czodrowski, Patrick; Deviveiros, Pier-Olivier; Eifert, Till; Ellis, Nicolas; Farthouat, Philippe; Galster, Gorm Aske Gram Krohn; Haas, Stefan; Helary, Louis; Lagkas Nikolos, Orestis; Marzin, Antoine; Pauly, Thilo; Ryjov, Vladimir; Schmieden, Kristof; Silva Oliveira, Marcos Vinicius; Stelzer, Harald Joerg; Vichoudis, Paschalis; Wengler, Thorsten

    The Muon-to-Central-Trigger-Processor Interface (MUCTPI) of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN will be upgraded to an ATCA blade system for Run 3, starting in 2021. The new design requires development of new communication models for control, configuration and monitoring. A System-on-Chip (SoC) with a programmable logic part and a processor part will be used for communication to the run control system and to the MUCTPI processing FPGAs. Different approaches have been compared. First, we tried an available UDP-based implementation in firmware for the programmable logic. Although this approach works as expected, it does not provide any flexibility to extend the functionality to more complex operations, e.g. for serial protocols. Second, we used a SoC processor with an embedded Linux operating system and an application-specific software written in C++ using a TCP remote-procedure-call approach. The software is built and maintained using the framework of the Yocto Project. This approa...

  17. Low Latency DESDynI Data Products for Disaster Response, Resource Management and Other Applications

    Science.gov (United States)

    Doubleday, Joshua R.; Chien, Steve A.; Lou, Yunling

    2011-01-01

    We are developing onboard processor technology targeted at the L-band SAR instrument onboard the planned DESDynI mission to enable formation of SAR images onboard opening possibilities for near-real-time data products to augment full data streams. Several image processing and/or interpretation techniques are being explored as possible direct-broadcast products for use by agencies in need of low-latency data, responsible for disaster mitigation and assessment, resource management, agricultural development, shipping, etc. Data collected through UAVSAR (L-band) serves as surrogate to the future DESDynI instrument. We have explored surface water extent as a tool for flooding response, and disturbance images on polarimetric backscatter of repeat pass imagery potentially useful for structural collapse (earthquake), mud/land/debris-slides etc. We have also explored building vegetation and snow/ice classifiers, via support vector machines utilizing quad-pol backscatter, cross-pol phase, and a number of derivatives (radar vegetation index, dielectric estimates, etc.). We share our qualitative and quantitative results thus far.

  18. Commodity multi-processor systems in the ATLAS level-2 trigger

    International Nuclear Information System (INIS)

    Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

    2000-01-01

    Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

  19. Commodity multi-processor systems in the ATLAS level-2 trigger

    CERN Document Server

    Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

    2000-01-01

    Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

  20. A line code with quick-resynchronization capability and low latency for the optical data links of LHC experiments

    International Nuclear Information System (INIS)

    Deng, B; He, M; Chen, J; Guo, D; Hou, S; Teng, P-K; Li, X; Liu, C; Xiang, A C; Ye, J; Gong, D; Liu, T; You, Y

    2014-01-01

    We propose a line code that has fast resynchronization capability and low latency. Both the encoder and decoder have been implemented in FPGAs. The encoder has also been implemented in an ASIC. The latency of the whole optical link (not including the optical fiber) is estimated to be less than 73.9 ns. In the case of radiation-induced link synchronization loss, the decoder can recover the synchronization in 25 ns. The line code will be used in the ATLAS liquid argon calorimeter Phase-I trigger upgrade and can also be potentially used in other LHC experiments

  1. Low Latency Audio Video: Potentials for Collaborative Music Making through Distance Learning

    Science.gov (United States)

    Riley, Holly; MacLeod, Rebecca B.; Libera, Matthew

    2016-01-01

    The primary purpose of this study was to examine the potential of LOw LAtency (LOLA), a low latency audio visual technology designed to allow simultaneous music performance, as a distance learning tool for musical styles in which synchronous playing is an integral aspect of the learning process (e.g., jazz, folk styles). The secondary purpose was…

  2. A programmable systolic array correlator as a trigger processor for electron pairs in rich (ring image Cherenkov) counters

    Science.gov (United States)

    Männer, R.

    1989-12-01

    This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128 x 128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8 x 8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology.

  3. A programmable systolic array correlator as a trigger processor for electron pairs in RICH (ring image Cherenkov) counters

    International Nuclear Information System (INIS)

    Maenner, R.

    1989-01-01

    This paper describes a systolic array processor for a ring image Cherenkov counter which is capable of identifying pairs of electron circles with a known radius and a certain minimum distance within 15 μs. The processor is a very flexible and fast device. It consists of 128x128 processing elements (PEs), where one PE is assigned to each pixel of the image. All PEs run synchronously at 40 MHz. The identification of electron circles is done by correlating the detector image with the proper circle circumference. Circle centers are found by peak detection in the correlation result. A second correlation with a circle disc allows circles of closed electron pairs to be rejected. The trigger decision is generated if a pseudo adder detects at least two remaining circles. The device is controlled by a freely programmable sequencer. A VLSI chip containing 8x8 PEs is being developed using a VENUS design system and will be produced in 2μ CMOS technology. (orig.)

  4. Reconfigurable PCI Express cards for low-latency data transport in HEP experiments

    International Nuclear Information System (INIS)

    Ammendola, R.; Biagioni, A.; Cretaro, P.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P.S.; Pastorelli, E.; Simula, F.; Vicini, P.; Lamanna, G.; Pontisso, L.

    2017-01-01

    State-of-the-art technology supports the High Energy Physics community in addressing the problem of managing an overwhelming amount of experimental data. From the point of view of communication between the detectors’ readout system and computing nodes, the critical issues are the following: latency, moving data in a deterministic and low amount of time; bandwidth, guaranteeing the maximum capability of the link and communication protocol adopted; endpoint consolidation, tight aggregation of channels on a single board. This contribution describes the status and performances of the NaNet project, whose goal is the design of a family of FPGA-based PCIe network interface cards. The efforts of the team are focused on implementing a low-latency, real-time data transport mechanism between the board network multi-channel system and CPU and GPU accelerators memories on the host. Several opportunities concerning technical solutions and scientific applications have been explored: NaNet-1 with a single GbE I/O interface, and NaNet-10, offering four 10GbE ports, for activities related to the GPU-based real-time trigger of NA62 experiment at CERN; NaNet"3, with four 2.5 Gbit optical channels, developed for the KM3NeT-ITALIA underwater neutrino telescope.

  5. Reconfigurable PCI Express cards for low-latency data transport in HEP experiments

    Science.gov (United States)

    Ammendola, R.; Biagioni, A.; Cretaro, P.; Frezza, O.; Lamanna, G.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Pontisso, L.; Simula, F.; Vicini, P.

    2017-01-01

    State-of-the-art technology supports the High Energy Physics community in addressing the problem of managing an overwhelming amount of experimental data. From the point of view of communication between the detectors' readout system and computing nodes, the critical issues are the following: latency, moving data in a deterministic and low amount of time; bandwidth, guaranteeing the maximum capability of the link and communication protocol adopted; endpoint consolidation, tight aggregation of channels on a single board. This contribution describes the status and performances of the NaNet project, whose goal is the design of a family of FPGA-based PCIe network interface cards. The efforts of the team are focused on implementing a low-latency, real-time data transport mechanism between the board network multi-channel system and CPU and GPU accelerators memories on the host. Several opportunities concerning technical solutions and scientific applications have been explored: NaNet-1 with a single GbE I/O interface, and NaNet-10, offering four 10GbE ports, for activities related to the GPU-based real-time trigger of NA62 experiment at CERN; NaNet ^3 , with four 2.5Gbit optical channels, developed for the KM3NeT-ITALIA underwater neutrino telescope.

  6. Status of the NA62 liquid krypton electromagnetic calorimeter Level 0 trigger processor

    CERN Document Server

    Bonaiuto, V; Fucci, A; Paoluzzi, G; Salamon, A; Salina, G; Santovetti, E; Sargeni, F; Venditti, S

    2013-01-01

    The NA62 experiment at the CERN SPS aims to measure the Branching Ratio of the very rare kaon decay K(+)→π(+)νbar nu collecting O(100) events with a 10% background in two years of data taking. To reject the K(+)→π(+)π(0) background the NA48 liquid krypton calorimeter will be used in the 1-10 mrad angular region. The status of the Liquid Krypton Electromagnetic Calorimeter Level 0 Trigger is presented.

  7. A compact pre-processor system for the ATLAS level-1 calorimeter trigger

    CERN Document Server

    Pfeiffer, U

    1999-01-01

    This thesis describ es the researc h whose aim is to dev elop a compact Pre-Pro cessor system for the A TLAS Lev el-1 Calorimeter T rigger. Con tributions to the p erformance and the arc hitecture of the Pre-Pro cessor w ere made. A demonstrator Multi-Chip Mo dule (PPrD- MCM) w as dev elop ed and assem bled whic h p erforms most of the prepro cessing of four analogue trigger-to w er signals. The prepro cessing includes digitisation to 8-bit precision, iden ti cation of the corresp onding bunc h-crossing in time (BCID), calibration of the transv erse energy , readout of ra w trigger data, and high-sp eed serial data transmission to the trigger pro cessors. The demonstrator Multi-Chip Mo dule has a size of 15.9 cm 2 and it consists of 9 dies. The MCM w as designed with a smallest feature size of 100 m and it w as fabricated in a laminated MCM-L pro cess o ered b yW urth Elektronik. A Flip-Chip in terconnection ASIC (Finco) w as dev elop ed for the PPrD-MCM and fabricated in a 0.8 m BiCMOS- pro cess o ered b ...

  8. Optimization on fixed low latency implementation of the GBT core in FPGA

    Science.gov (United States)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-07-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  9. Optimization on fixed low latency implementation of the GBT core in FPGA

    International Nuclear Information System (INIS)

    Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

    2017-01-01

    In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

  10. Use of GPUs in Trigger Systems

    Science.gov (United States)

    Lamanna, Gianluca

    In recent years the interest for using graphics processor (GPU) in general purpose high performance computing is constantly rising. In this paper we discuss the possible use of GPUs to construct a fast and effective real time trigger system, both in software and hardware levels. In particular, we study the integration of such a system in the NA62 trigger. The first application of GPUs for rings pattern recognition in the RICH will be presented. The results obtained show that there are not showstoppers in trigger systems with relatively low latency. Thanks to the use of off-the-shelf technology, in continous development for purposes related to video game and image processing market, the architecture described would be easily exported to other experiments, to build a versatile and fully customizable online selection.

  11. Low-Latency Science Exploration of Planetary Bodies: How ISS Might Be Used as Part of a Low-Latency Analog Campaign for Human Exploration

    Science.gov (United States)

    Thronson, Harley; Valinia, Azita; Bleacher, Jacob; Eigenbrode, Jennifer; Garvin, Jim; Petro, Noah

    2014-01-01

    We suggest that the International Space Station be used to examine the application and validation of low-latency telepresence for surface exploration from space as an alternative, precursor, or potentially as an adjunct to astronaut "boots on the ground." To this end, controlled experiments that build upon and complement ground-based analog field studies will be critical for assessing the effects of different latencies (0 to 500 milliseconds), task complexity, and alternate forms of feedback to the operator. These experiments serve as an example of a pathfinder for NASA's roadmap of missions to Mars with low-latency telerobotic exploration as a precursor to astronaut's landing on the surface to conduct geological tasks.

  12. ATLAS Level-1 Topological Trigger

    CERN Document Server

    Zheng, Daniel; The ATLAS collaboration

    2018-01-01

    The ATLAS experiment has introduced and recently commissioned a completely new hardware sub-system of its first-level trigger: the topological processor (L1Topo). L1Topo consist of two AdvancedTCA blades mounting state-of-the-art FPGA processors, providing high input bandwidth (up to 4 Gb/s) and low latency data processing (200 ns). L1Topo is able to select collision events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Results from data recorded using the L1Topo trigger will be presented. These results demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-pT leptons, including H->tau tau and J/Psi->mu mu. In addition to describing the L1Topo trigger system, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize...

  13. An Ultra-Low-Latency Geo-Routing Scheme for Team-Based Unmanned Vehicular Applications

    KAUST Repository

    Bader, Ahmed; Alouini, Mohamed-Slim

    2016-01-01

    Results and lessons learned from the implementation of a novel ultra low-latency geo-routing scheme are presented in this paper. The geo-routing scheme is intended for team-based mobile systems whereby a cluster of unmanned autonomous vehicles

  14. Scalable optical packet switch architecture for low latency and high load computer communication networks

    NARCIS (Netherlands)

    Calabretta, N.; Di Lucente, S.; Nazarathy, Y.; Raz, O.; Dorren, H.J.S.

    2011-01-01

    High performance computer and data-centers require PetaFlop/s processing speed and Petabyte storage capacity with thousands of low-latency short link interconnections between computers nodes. Switch matrices that operate transparently in the optical domain are a potential way to efficiently

  15. Controllable thousand-port low-latency optical packet switch architecture for short link applications

    NARCIS (Netherlands)

    Di Lucente, S.; Nazarathy, J.; Raz, O.; Calabretta, N.; Dorren, H.J.S.; Bienstman, P.; Morthier, G.; Roelkens, G.; et al., xx

    2011-01-01

    The implementation of a low-latency optical packet switch architecture that is controllable while scaling to over thousand ports is investigated in this paper. Optical packet switches with thousand of input/output ports are promising devices to improve the performance of short link applications in

  16. Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project

    Science.gov (United States)

    Ammendola, R.; Biagioni, A.; Cretaro, P.; Frezza, O.; Lo Cicero, F.; Lonardo, A.; Martinelli, M.; Paolucci, P. S.; Pastorelli, E.; Pisani, F.; Simula, F.; Vicini, P.; Navaridas, J.; Chaix, F.; Chrysos, N.; Katevenis, M.; Papaeustathiou, V.

    2017-10-01

    With processor architecture evolution, the HPC market has undergone a paradigm shift. The adoption of low-cost, Linux-based clusters extended the reach of HPC from its roots in modelling and simulation of complex physical systems to a broader range of industries, from biotechnology, cloud computing, computer analytics and big data challenges to manufacturing sectors. In this perspective, the near future HPC systems can be envisioned as composed of millions of low-power computing cores, densely packed — meaning cooling by appropriate technology — with a tightly interconnected, low latency and high performance network and equipped with a distributed storage architecture. Each of these features — dense packing, distributed storage and high performance interconnect — represents a challenge, made all the harder by the need to solve them at the same time. These challenges lie as stumbling blocks along the road towards Exascale-class systems; the ExaNeSt project acknowledges them and tasks itself with investigating ways around them.

  17. Declaratively programmable ultra-low latency audio effects processing on FPGA

    NARCIS (Netherlands)

    Verstraelen, Martinus Johannes Wilhelmina; Kuper, Jan; Smit, Gerardus Johannes Maria

    2014-01-01

    WaveCore is a coarse-grained reconfigurable processor architecture, based on data-flow principles. The processor architecture consists of a scalable and interconnected cluster of Processing Units (PU), where each PU embodies a small floating-point RISC processor. The processor has been designed in

  18. Low Latency Workflow Scheduling and an Application of Hyperspectral Brightness Temperatures

    Science.gov (United States)

    Nguyen, P. T.; Chapman, D. R.; Halem, M.

    2012-12-01

    the Nino 4 region, as well as a 1.9 Kelvin decadal Arctic warming in the 4u and 12u spectral regions. Additionally, we will present the frequency of extreme global warming events by the use of a normalized maximum BT in a grid cell relative to its local standard deviation. A low-latency Hadoop scheduling environment maintains data integrity and fault tolerance in a MapReduce data intensive Cloud environment while improving the "time to solution" metric by 35% when compared to a more traditional parallel processing system for the same dataset. Our next step will be to improve the usability of our Hadoop task scheduling system, to enable rapid prototyping of data intensive experiments by means of processing "kernels". We will report on the performance and experience of implementing these experiments on the NEX testbed, and propose the use of a graphical directed acyclic graph (DAG) interface to help us develop on-demand scientific experiments. Our workflow system works within Hadoop infrastructure as a replacement for the FIFO or FairScheduler, thus the use of Apache "Pig" latin or other Apache tools may also be worth investigating on the NEX system to improve the usability of our workflow scheduling infrastructure for rapid experimentation.

  19. A low-latency pipeline for GRB light curve and spectrum using Fermi/GBM near real-time data

    Science.gov (United States)

    Zhao, Yi; Zhang, Bin-Bin; Xiong, Shao-Lin; Long, Xi; Zhang, Qiang; Song, Li-Ming; Sun, Jian-Chao; Wang, Yuan-Hao; Li, Han-Cheng; Bu, Qing-Cui; Feng, Min-Zi; Li, Zheng-Heng; Wen, Xing; Wu, Bo-Bing; Zhang, Lai-Yu; Zhang, Yong-Jie; Zhang, Shuang-Nan; Shao, Jian-Xiong

    2018-05-01

    Rapid response and short time latency are very important for Time Domain Astronomy, such as the observations of Gamma-ray Bursts (GRBs) and electromagnetic (EM) counterparts of gravitational waves (GWs). Based on near real-time Fermi/GBM data, we developed a low-latency pipeline to automatically calculate the temporal and spectral properties of GRBs. With this pipeline, some important parameters can be obtained, such as T 90 and fluence, within ∼ 20 min after the GRB trigger. For ∼ 90% of GRBs, T 90 and fluence are consistent with the GBM catalog results within 2σ errors. This pipeline has been used by the Gamma-ray Bursts Polarimeter (POLAR) and the Insight Hard X-ray Modulation Telescope (Insight-HXMT) to follow up the bursts of interest. For GRB 170817A, the first EM counterpart of GW events detected by Fermi/GBM and INTEGRAL/SPI-ACS, the pipeline gave T 90 and spectral information 21 min after the GBM trigger, providing important information for POLAR and Insight-HXMT observations.

  20. Low-Latency Teleoperations for Human Exploration and Evolvable Mars Campaign

    Science.gov (United States)

    Lupisella, Mark; Wright, Michael; Arney, Dale; Gershman, Bob; Stillwagen, Fred; Bobskill, Marianne; Johnson, James; Shyface, Hilary; Larman, Kevin; Lewis, Ruthan; hide

    2015-01-01

    NASA has been analyzing a number of mission concepts and activities that involve low-latency telerobotic (LLT) operations. One mission concept that will be covered in this presentation is Crew-Assisted Sample Return which involves the crew acquiring samples (1) that have already been delivered to space, and or acquiring samples via LLT from orbit to a planetary surface and then launching the samples to space to be captured in space and then returned to the earth with the crew. Both versions of have key roles for low-latency teleoperations. More broadly, the NASA Evolvable Mars Campaign is exploring a number of other activities that involve LLT, such as: (a) human asteroid missions, (b) PhobosDeimos missions, (c) Mars human landing site reconnaissance and site preparation, and (d) Mars sample handling and analysis. Many of these activities could be conducted from Mars orbit and also with the crew on the Mars surface remotely operating assets elsewhere on the surface, e.g. for exploring Mars special regions and or teleoperating a sample analysis laboratory both of which may help address planetary protection concerns. The operational and technology implications of low-latency teleoperations will be explored, including discussion of relevant items in the NASA Technology Roadmap and also how previously deployed robotic assets from any source could subsequently be used by astronauts via LLT.

  1. Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC operations

    CERN Document Server

    Acosta, D; Furic, I; Gartner, J; Di Giovanni, G P; Hammar, A; Kotov, K; Madorsky, A; Matveev, M; Padley, P; Uvarov, L; Wang, D

    2009-01-01

    The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60° azimuthal sector. This would dramatically improve the efficiency of the track reconstruction in a high occupancy environment over the current design. However, such an improvement would require significantly higher bandwidth and logic resources. We propose to use the fastest available serial links, running asynchronously to the machine clock to use their full bandwidth. The work of creating a firmware model f...

  2. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The hardware of the trigger components has been mostly finished. The ECAL Endcap Trigger Concentrator Cards (TCC) are in production while Barrel TCC firmware has been upgraded, and the Trigger Primitives can now be stored by the Data Concentrator Card for readout by the DAQ. The Regional Calorimeter Trigger (RCT) system is complete, and the timing is being finalized. All 502 HCAL trigger links to RCT run without error. The HCAL muon trigger timing has been equalized with DT, RPC, CSC and ECAL. The hardware and firmware for the Global Calorimeter Trigger (GCT) jet triggers are being commissioned and data from these triggers is available for readout. The GCT energy sums from rings of trigger towers around the beam pipe beam have been changed to include two rings from both sides. The firmware for Drift Tube Track Finder, Barrel Sorter and Wedge Sorter has been upgraded, and the synchronization of the DT trigger is satisfactory. The CSC local trigger has operated flawlessly u...

  3. TRIGGER

    CERN Multimedia

    Roberta Arcidiacono

    2013-01-01

    Trigger Studies Group (TSG) The Trigger Studies Group has just concluded its third 2013 workshop, where all POGs presented the improvements to the physics object reconstruction, and all PAGs have shown their plans for Trigger development aimed at the 2015 High Level Trigger (HLT) menu. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger menu development, path timing, Trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – this last task in collaboration with PdmV (Physics Data and Monte Carlo Validation group). In the last months the group has delivered several HLT rate estimates and comparisons, using the available data and Monte Carlo samples. The studies were presented at the Trigger workshops in September and December, and STEAM has contacted POGs and PAGs to understand the origin of the discrepancies observed between 8 TeV data and Monte Carlo simulations. The most recent results show what the...

  4. Development of the Plate Boundary Observatory GPS Low Latency Salton Trough Radio Network

    Science.gov (United States)

    Walls, C.; Miller, S.; Wilson, B.; Lawrence, S.; Arnitz, E.

    2008-05-01

    UNAVCO is developing a 20 GPS station low latency radio network that spans the San Andreas and San Jacinto faults in the region of highest strain in southern California and the narrowest part of the North America-Pacific plate boundary. The Salton Trough Radio Network (STRN) is instrumented with Ethernet bridge Intuicom EB6+ (900 MHz) radios to transmit a high rate low latency data stream from each permanent GPS site for the purpose of the following: 1) telemeter 15 second data (1 MB/day/station) to the Plate Boundary Observatory archive, 2) accommodate the timely download of 1 and 5 sample per second data following large earthquakes (4 MB/hour/station), and 3) test the UStream of 1Hz BINEX and RTCM data. Three of four phases have been completed. Office radio testing yielded transfer rates of 30-50 KB/s with subsecond latency while streaming 1 Hz data. Latency climbed to ~1.8 seconds while simultaneously streaming 1 Hz and downloading hourly 1 and 5 sample per second data files. Field testing demonstrated rates on the order of 30 KB/s. At present the radios are installed and have transfer rates of 10-40 KB/s between sites that span 10-32 km. The final phase will be the installation of the main telemetry relay where master radios will be connected to a high speed ISP near the town of Brawley. The high-rate low latency UStream data will be available to researchers who are developing prototype earthquake early warning systems in Southern California. A goal of the STRN is to make the data available rapidly enough for GPS-derived coseismic and dynamic displacements to be integrated into early warning system earthquake models. The improved earthquake models will better assist emergency response. UStream data will also aid surveyors who wish to use PBO GPS stations as permanent, high-quality base stations in real-time kinematic surveys.

  5. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The trigger synchronization procedures for running with cosmic muons and operating with the LHC were reviewed during the May electronics week. Firmware maintenance issues were also reviewed. Link tests between the new ECAL endcap trigger concentrator cards (TCC48) and the Regional Calorimeter Trigger have been performed. Firmware for the energy sum triggers and an upgraded tau trigger of the Global Calorimeter Triggers has been developed and is under test. The optical fiber receiver boards for the Track-Finder trigger theta links of the DT chambers are now all installed. The RPC trigger is being made more robust by additional chamber and cable shielding and also by firmware upgrades. For the CSC’s the front-end and trigger motherboard firmware have been updated. New RPC patterns and DT/CSC lookup tables taking into account phi asymmetries in the magnetic field configuration are under study. The motherboard for the new pipeline synchronizer of the Global Trigg...

  6. TRIGGER

    CERN Multimedia

    W. Smith

    2012-01-01

      Level-1 Trigger The Level-1 Trigger group is ready to deploy improvements to the L1 Trigger algorithms for 2012. These include new high-PT patterns for the RPC endcap, an improved CSC PT assignment, a new PT-matching algorithm for the Global Muon Trigger, and new calibrations for ECAL, HCAL, and the Regional Calorimeter Trigger. These should improve the efficiency, rate, and stability of the L1 Trigger. The L1 Trigger group also is migrating the online systems to SLC5. To make the data transfer from the Global Calorimeter Trigger to the Global Trigger more reliable and also to allow checking the data integrity online, a new optical link system has been developed by the GCT and GT groups and successfully tested at the CMS electronics integration facility in building 904. This new system is now undergoing further tests at Point 5 before being deployed for data-taking this year. New L1 trigger menus have recently been studied and proposed by Emmanuelle Perez and the L1 Detector Performance Group...

  7. Optimized Interface Diversity for Ultra-Reliable Low Latency Communication (URLLC)

    DEFF Research Database (Denmark)

    Nielsen, Jimmy Jessen; Liu, Rongkuan; Popovski, Petar

    2017-01-01

    An important ingredient of the future 5G systems will be Ultra-Reliable Low-Latency Communication (URLLC). A way to offer URLLC without intervention in the baseband/PHY layer design is to use interface diversity and integrate multiple communication interfaces, each interface based on a different...... technology. Our approach is to use rateless codes to seamlessly distribute coded payload and redundancy data across multiple available communication interfaces. We formulate an optimization problem to find the payload allocation weights that maximize the reliability at specific target latency values...

  8. Toward Massive, Ultrareliable, and Low-Latency Wireless Communication With Short Packets

    DEFF Research Database (Denmark)

    Durisi, Giuseppe; Koch, Tobias; Popovski, Petar

    2016-01-01

    Most of the recent advances in the design of high-speed wireless systems are based on information-theoretic principles that demonstrate how to efficiently transmit long data packets. However, the upcoming wireless systems, notably the fifth-generation (5G) system, will need to support novel traffic...... that should be received with low latency and ultrahigh reliability. Current wireless systems are not designed to support short-packet transmissions. For example, the design of current systems relies on the assumption that the metadata (control information) is of negligible size compared to the actual...

  9. An Ultra-Low-Latency Geo-Routing Scheme for Team-Based Unmanned Vehicular Applications

    KAUST Repository

    Bader, Ahmed

    2016-02-26

    Results and lessons learned from the implementation of a novel ultra low-latency geo-routing scheme are presented in this paper. The geo-routing scheme is intended for team-based mobile systems whereby a cluster of unmanned autonomous vehicles are deployed to accomplish a critical mission under human supervision. The contention-free nature of the developed scheme lends itself to jointly achieve lower latency and higher throughput. Implementation challenges are presented and corresponding resolutions are discussed herewith. © 2015 IEEE.

  10. TRIGGER

    CERN Multimedia

    W. Smith

    At the March meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, the program of trigger pattern tests and vertical slice tests and planning for the Global Runs starting this summer. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and integration testing is in full swing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. After full checkout, trigger subsystems will be then operated in the CMS Global Runs. Continuous...

  11. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The production of the trigger hardware is now basically finished, and in time for the turn-on of the LHC. The last boards produced are the Trigger Concentrator Cards for the ECAL Endcaps (TCC-EE). After the recent installation of the four EE Dees, the TCC-EE prototypes were used for their commissioning. Production boards are arriving and are being tested continuously, with the last ones expected in November. The Regional Calorimeter Trigger hardware is fully integrated after installation of the last EE cables. Pattern tests from the HCAL up to the GCT have been performed successfully. The HCAL triggers are fully operational, including the connection of the HCAL-outer and forward-HCAL (HO/HF) technical triggers to the Global Trigger. The HCAL Trigger and Readout (HTR) board firmware has been updated to permit recording of the tower “feature bit” in the data. The Global Calorimeter Trigger hardware is installed, but some firmware developments are still n...

  12. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The overall status of the L1 trigger has been excellent and the running efficiency has been high during physics fills. The timing is good to about 1%. The fine-tuning of the time synchronization of muon triggers is ongoing and will be completed after more than 10 nb-1 of data have been recorded. The CSC trigger primitive and RPC trigger timing have been refined. A new configuration for the CSC Track Finder featured modified beam halo cuts and improved ghost cancellation logic. More direct control was provided for the DT opto-receivers. New RPC Cosmic Trigger (RBC/TTU) trigger algorithms were enabled for collision runs. There is further work planned during the next technical stop to investigate a few of the links from the ECAL to the Regional Calorimeter Trigger (RCT). New firmware and a new configuration to handle trigger rate spikes in the ECAL barrel are also being tested. A board newly developed by the tracker group (ReTRI) has been installed and activated to block re...

  13. Advances in High-Throughput Speed, Low-Latency Communication for Embedded Instrumentation (7th Annual SFAF Meeting, 2012)

    Energy Technology Data Exchange (ETDEWEB)

    Jordan, Scott

    2012-06-01

    Scott Jordan on "Advances in high-throughput speed, low-latency communication for embedded instrumentation" at the 2012 Sequencing, Finishing, Analysis in the Future Meeting held June 5-7, 2012 in Santa Fe, New Mexico.

  14. TRIGGER

    CERN Multimedia

    W. Smith

    2010-01-01

    Level-1 Trigger Hardware and Software The Level-1 Trigger hardware has performed well during both the recent proton-proton and heavy ion running. Efforts were made to improve the visibility and handling of alarms and warnings. The tracker ReTRI boards that prevent fixed frequencies of Level-1 Triggers are now configured through the Trigger Supervisor. The Global Calorimeter Trigger (GCT) team has introduced a buffer cleanup procedure at stops and a reset of the QPLL during configuring to ensure recalibration in case of a switch from the LHC clock to the local clock. A device to test the cables between the Regional Calorimeter Trigger and the GCT has been manufactured. A wrong charge bit was fixed in the CSC Trigger. The ECAL group is improving crystal masking and spike suppression in the trigger primitives. New firmware for the Drift Tube Track Finder (DTTF) sorters was developed to improve fake track tagging and sorting. Zero suppression was implemented in the DT Sector Collector readout. The track finder b...

  15. TRIGGER

    CERN Multimedia

    Wesley Smith

    Trigger Hardware The status of the trigger components was presented during the September CMS Week and Annual Review and at the monthly trigger meetings in October and November. Procedures for cold and warm starts (e.g. refreshing of trigger parameters stored in registers) of the trigger subsystems have been studied. Reviews of parts of the Global Calorimeter Trigger (GCT) and the Global Trigger (GT) have taken place in October and November. The CERN group summarized the status of the Trigger Timing and Control (TTC) system. All TTC crates and boards are installed in the underground counting room, USC55. The central clock system will be upgraded in December (after the Global Run at the end of November GREN) to the new RF2TTC LHC machine interface timing module. Migration of subsystem's TTC PCs to SLC4/ XDAQ 3.12 is being prepared. Work is on going to unify the access to Local Timing Control (LTC) and TTC CMS interface module (TTCci) via SOAP (Simple Object Access Protocol, a lightweight XML-based messaging ...

  16. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos

    2010-01-01

    Level-1 Trigger Hardware and Software Since nearly all of the Level-1 (L1) Trigger hardware at Point 5 has been commissioned, activities during the past months focused on the fine-tuning of synchronization, particularly for the ECAL and the CSC systems, on firmware upgrades and on improving trigger operation and monitoring. Periodic resynchronizations or hard resets and a shortened luminosity section interval of 23 seconds were implemented. For the DT sector collectors, an automatic power-off was installed in case of high temperatures, and the monitoring capabilities of the opto-receivers and the mini-crates were enhanced. The DTTF and the CSCTF now have improved memory lookup tables. The HCAL trigger primitive logic implemented a new algorithm providing better stability of the energy measurement in the presence of any phase misalignment. For the Global Calorimeter Trigger, additional Source Cards have been manufactured and tested. Testing of the new tau, missing ET and missing HT algorithms is underw...

  17. TRIGGER

    CERN Multimedia

    Wesley Smith

    Level-1 Trigger Hardware and Software The final parts of the Level-1 trigger hardware are now being put in place. For the ECAL endcaps, more than half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are now available at CERN, such that one complete endcap can be covered. The Global Trigger now correctly handles ECAL calibration sequences, without being influenced by backpressure. The Regional Calorimeter Trigger (RCT) hardware is complete and working in USC55. Intra-crate tests of all 18 RCT crates and the Global Calorimeter Trigger (GCT) are regularly taking place. Pattern tests have successfully captured data from HCAL through RCT to the GCT Source Cards. HB/HE trigger data are being compared with emulator results to track down the very few remaining hardware problems. The treatment of hot and dead cells, including their recording in the database, has been defined. For the GCT, excellent agreement between the emulator and data has been achieved for jets and HF ET sums. There is still som...

  18. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The trigger system has been constantly in use in cosmic and commissioning data taking periods. During CRAFT running it delivered 300 million muon and calorimeter triggers to CMS. It has performed stably and reliably. During the abort gaps it has also provided laser and other calibration triggers. Timing issues, namely synchronization and latency issues, have been solved. About half of the Trigger Concentrator Cards for the ECAL Endcap (TCC-EE) are installed, and the firmware is being worked on. The production of the other half has started. The HCAL Trigger and Readout (HTR) card firmware has been updated, and new features such as fast parallel zero-suppression have been included. Repairs of drift tube (DT) trigger mini-crates, optical links and receivers of sector collectors are under way and have been completed on YB0. New firmware for the optical receivers of the theta links to the drift tube track finder is being installed. In parallel, tests with new eta track finde...

  19. TRIGGER

    CERN Multimedia

    R. Carlin with contributions from D. Acosta

    2012-01-01

    Level-1 Trigger Data-taking continues at cruising speed, with high availability of all components of the Level-1 trigger. We have operated the trigger up to a luminosity of 7.6E33, where we approached 100 kHz using the 7E33 prescale column.  Recently, the pause without triggers in case of an automatic "RESYNC" signal (the "settle" and "recover" time) was reduced in order to minimise the overall dead-time. This may become very important when the LHC comes back with higher energy and luminosity after LS1. We are also preparing for data-taking in the proton-lead run in early 2013. The CASTOR detector will make its comeback into CMS and triggering capabilities are being prepared for this. Steps to be taken include improved cooperation with the TOTEM trigger system and using the LHC clock during the injection and ramp phases of LHC. Studies are being finalised that will have a bearing on the Trigger Technical Design Report (TDR), which is to be rea...

  20. TRIGGER

    CERN Multimedia

    W. Smith

    At the December meeting, the CMS trigger group reported on progress in production, tests in the Electronics Integration Center (EIC) in Prevessin 904, progress on trigger installation in the underground counting room at point 5, USC55, and results from the Magnet Test and Cosmic Challenge (MTCC) phase II. The trigger group is engaged in the final stages of production testing, systems integration, and software and firmware development. Most systems are delivering final tested electronics to CERN. The installation in USC55 is underway and moving towards integration testing. A program of orderly connection and checkout with subsystems and central systems has been developed. This program includes a series of vertical subsystem slice tests providing validation of a portion of each subsystem from front-end electronics through the trigger and DAQ to data captured and stored. This is combined with operations and testing without beam that will continue until startup. The plans for start-up, pilot and early running tri...

  1. TRIGGER

    CERN Multimedia

    Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software New Forward Scintillating Counters (FSC) for rapidity gap measurements have been installed and integrated into the Trigger recently. For the Global Muon Trigger, tuning of quality criteria has led to improvements in muon trigger efficiencies. Several subsystems have started campaigns to increase spares by recovering boards or producing new ones. The barrel muon sector collector test system has been reactivated, new η track finder boards are in production, and φ track finder boards are under revision. In the CSC track finder, an η asymmetry problem has been corrected. New pT look-up tables have also improved efficiency. RPC patterns were changed from four out of six coincident layers to three out of six in the barrel, which led to a significant increase in efficiency. A new PAC firmware to trigger on heavy stable charged particles allows looking for chamber hit coincidences in two consecutive bunch-crossings. The redesign of the L1 Trigger Emulator...

  2. TRIGGER

    CERN Multimedia

    W. Smith, from contributions of D. Acosta

    2012-01-01

      The L1 Trigger group deployed several major improvements this year. Compared to 2011, the single-muon trigger rate has been reduced by a factor of 2 and the η coverage has been restored to 2.4, with high efficiency. During the current technical stop, a higher jet seed threshold will be applied in the Global Calorimeter Trigger in order to significantly reduce the strong pile-up dependence of the HT and multi-jet triggers. The currently deployed L1 menu, with the “6E33” prescales, has a total rate of less than 100 kHz and operates with detector readout dead time of less than 3% for luminosities up to 6.5 × 1033 cm–2s–1. Further prescale sets have been created for 7 and 8 × 1033 cm–2s–1 luminosities. The L1 DPG is evaluating the performance of the Trigger for upcoming conferences and publication. Progress on the Trigger upgrade was reviewed during the May Upgrade Week. We are investigating scenarios for stagin...

  3. TRIGGER

    CERN Multimedia

    W. Smith from contributions of C. Leonidopoulos, I. Mikulec, J. Varela and C. Wulz.

    Level-1 Trigger Hardware and Software Over the past few months, the Level-1 trigger has successfully recorded data with cosmic rays over long continuous stretches as well as LHC splash events, beam halo, and collision events. The L1 trigger hardware, firmware, synchronization, performance and readiness for beam operation were reviewed in October. All L1 trigger hardware is now installed at Point 5, and most of it is completely commissioned. While the barrel ECAL Trigger Concentrator Cards are fully operational, the recently delivered endcap ECAL TCC system is still being commissioned. For most systems there is a sufficient number of spares available, but for a few systems additional reserve modules are needed. It was decided to increase the overall L1 latency by three bunch crossings to increase the safety margin for trigger timing adjustments. In order for CMS to continue data taking during LHC frequency ramps, the clock distribution tree needs to be reset. The procedures for this have been tested. A repl...

  4. TRIGGER

    CERN Multimedia

    R. Arcidiacono

    2013-01-01

      In 2013 the Trigger Studies Group (TSG) has been restructured in three sub-groups: STEAM, for the development of new HLT menus and monitoring their performance; STORM, for the development of HLT tools, code and actual configurations; and FOG, responsible for the online operations of the High Level Trigger. The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for Trigger Menu development, path timing, trigger performance studies coordination, HLT offline DQM as well as HLT release, menu and conditions validation – in collaboration and with the technical support of the PdmV group. Since the end of proton-proton data taking, the group has started preparing for 2015 data taking, with collisions at 13 TeV and 25 ns bunch spacing. The reliability of the extrapolation to higher energy is being evaluated comparing the trigger rates on 7 and 8 TeV Monte Carlo samples with the data taken in the past two years. The effect of 25 ns bunch spacing is being studied on the d...

  5. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware and Software The road map for the final commissioning of the level-1 trigger system has been set. The software for the trigger subsystems is being upgraded to run under CERN Scientific Linux 4 (SLC4). There is also a new release for the Trigger Supervisor (TS 1.4), which implies upgrade work by the subsystems. As reported by the CERN group, a campaign to tidy the Trigger Timing and Control (TTC) racks has begun. The machine interface was upgraded by installing the new RF2TTC module, which receives RF signals from LHC Point 4. Two Beam Synchronous Timing (BST) signals, one for each beam, can now be received in CMS. The machine group will define the exact format of the information content shortly. The margin on the locking range of the CMS QPLL is planned for study for different subsystems in the next Global Runs, using a function generator. The TTC software has been successfully tested on SLC4. Some TTC subsystems have already been upgraded to SLC4. The TTCci Trigger Supervisor ...

  6. Low Latency MAC Protocol in Wireless Sensor Networks Using Timing Offset

    Science.gov (United States)

    Choi, Seung Sik

    This paper proposes a low latency MAC protocol that can be used in sensor networks. To extend the lifetime of sensor nodes, the conventional solution is to synchronize active/sleep periods of all sensor nodes. However, due to these synchronized sensor nodes, packets in the intermediate nodes must wait until the next node wakes up before it can forward a packet. This induces a large delay in sensor nodes. To solve this latency problem, a clustered sensor network which uses two types of sensor nodes and layered architecture is considered. Clustered heads in each cluster are synchronized with different timing offsets to reduce the sleep delay. Using this concept, the latency problem can be solved and more efficient power usage can be obtained.

  7. On the Impact of Multi-User Traffic Dynamics on Low Latency Communications

    DEFF Research Database (Denmark)

    Gerardino, Guillermo Andrés Pocovi; Pedersen, Klaus I.; Alvarez, Beatriz Soret

    2016-01-01

    In this paper we study the downlink latency performance in a multi-user cellular network. We use a flexible 5G radio frame structure, where the TTI size is configurable on a per-user basis according to their specific service requirements. Results show that at low system loads using a short TTI (e.......g. 0.25 ms) is an attractive solution to achieve low latency communications (LLC). The main benefits come from the low transmission delay required to transmit the payloads. However, as the load increases, longer TTI configurations with lower relative control overhead (and therefore higher spectral...... efficiency) provide better performance as these better cope with the non-negligible queuing delay. The presented results allow to conclude that support for scheduling with different TTI sizes is important for LLC and should be included in the future 5G....

  8. Multi-User Preemptive Scheduling For Critical Low Latency Communications in 5G Networks

    DEFF Research Database (Denmark)

    Abdul-Mawgood Ali Ali Esswie, Ali; Pedersen, Klaus

    2018-01-01

    5G new radio is envisioned to support three major service classes: enhanced mobile broadband (eMBB), ultrareliable low-latency communications (URLLC), and massive machine type communications. Emerging URLLC services require up to one millisecond of communication latency with 99.999% success...... probability. Though, there is a fundamental trade-off between system spectral efficiency (SE) and achievable latency. This calls for novel scheduling protocols which cross-optimize system performance on user-centric; instead of network-centric basis. In this paper, we develop a joint multi-user preemptive...... scheduling strategy to simultaneously cross-optimize system SE and URLLC latency. At each scheduling opportunity, available URLLC traffic is always given higher priority. When sporadic URLLC traffic appears during a transmission time interval (TTI), proposed scheduler seeks for fitting the URLLC-eMBB traffic...

  9. A Type of Low-Latency Data Gathering Method with Multi-Sink for Sensor Networks

    Science.gov (United States)

    Sha, Chao; Qiu, Jian-mei; Li, Shu-yan; Qiang, Meng-ye; Wang, Ru-chuan

    2016-01-01

    To balance energy consumption and reduce latency on data transmission in Wireless Sensor Networks (WSNs), a type of low-latency data gathering method with multi-Sink (LDGM for short) is proposed in this paper. The network is divided into several virtual regions consisting of three or less data gathering units and the leader of each region is selected according to its residual energy as well as distance to all of the other nodes. Only the leaders in each region need to communicate with the mobile Sinks which have effectively reduced energy consumption and the end-to-end delay. Moreover, with the help of the sleep scheduling and the sensing radius adjustment strategies, redundancy in network coverage could also be effectively reduced. Simulation results show that LDGM is energy efficient in comparison with MST as well as MWST and its time efficiency on data collection is higher than one Sink based data gathering methods. PMID:27338401

  10. A Type of Low-Latency Data Gathering Method with Multi-Sink for Sensor Networks

    Directory of Open Access Journals (Sweden)

    Chao Sha

    2016-06-01

    Full Text Available To balance energy consumption and reduce latency on data transmission in Wireless Sensor Networks (WSNs, a type of low-latency data gathering method with multi-Sink (LDGM for short is proposed in this paper. The network is divided into several virtual regions consisting of three or less data gathering units and the leader of each region is selected according to its residual energy as well as distance to all of the other nodes. Only the leaders in each region need to communicate with the mobile Sinks which have effectively reduced energy consumption and the end-to-end delay. Moreover, with the help of the sleep scheduling and the sensing radius adjustment strategies, redundancy in network coverage could also be effectively reduced. Simulation results show that LDGM is energy efficient in comparison with MST as well as MWST and its time efficiency on data collection is higher than one Sink based data gathering methods.

  11. A Fault Tolerant, Dynamic and Low Latency BDII Architecture for Grids

    CERN Document Server

    Osman, Asif; Batool, Naheed; McClatchey, Richard

    2012-01-01

    The current BDII model relies on information gathering from agents that run on each core node of a Grid. This information is then published into a Grid wide information resource known as Top BDII. The Top level BDIIs are updated typically in cycles of a few minutes each. A new BDDI architecture is proposed and described in this paper based on the hypothesis that only a few attribute values change in each BDDI information cycle and consequently it may not be necessary to update each parameter in a cycle. It has been demonstrated that significant performance gains can be achieved by exchanging only the information about records that changed during a cycle. Our investigations have led us to implement a low latency and fault tolerant BDII system that involves only minimal data transfer and facilitates secure transactions in a Grid environment.

  12. Low-latency analysis pipeline for compact binary coalescences in the advanced gravitational wave detector era

    International Nuclear Information System (INIS)

    Adams, T; Buskulic, D; Germain, V; Marion, F; Mours, B; Guidi, G M; Montani, M; Piergiovanni, F; Wang, G

    2016-01-01

    The multi-band template analysis (MBTA) pipeline is a low-latency coincident analysis pipeline for the detection of gravitational waves (GWs) from compact binary coalescences. MBTA runs with a low computational cost, and can identify candidate GW events online with a sub-minute latency. The low computational running cost of MBTA also makes it useful for data quality studies. Events detected by MBTA online can be used to alert astronomical partners for electromagnetic follow-up. We outline the current status of MBTA and give details of recent pipeline upgrades and validation tests that were performed in preparation for the first advanced detector observing period. The MBTA pipeline is ready for the outset of the advanced detector era and the exciting prospects it will bring. (paper)

  13. TRIGGER

    CERN Multimedia

    by Wesley Smith

    2011-01-01

    Level-1 Trigger Hardware and Software After the winter shutdown minor hardware problems in several subsystems appeared and were corrected. A reassessment of the overall latency has been made. In the TTC system shorter cables between TTCci and TTCex have been installed, which saved one bunch crossing, but which may have required an adjustment of the RPC timing. In order to tackle Pixel out-of-syncs without influencing other subsystems, a special hardware/firmware re-sync protocol has been introduced in the Global Trigger. The link between the Global Calorimeter Trigger and the Global Trigger with the new optical Global Trigger Interface and optical receiver daughterboards has been successfully tested in the Electronics Integration Centre in building 904. New firmware in the GCT now allows a setting to remove the HF towers from energy sums. The HF sleeves have been replaced, which should lead to reduced rates of anomalous signals, which may allow their inclusion after this is validated. For ECAL, improvements i...

  14. TRIGGER

    CERN Multimedia

    W. Smith

    2011-01-01

    Level-1 Trigger Hardware and Software Overall the L1 trigger hardware has been running very smoothly during the last months of proton running. Modifications for the heavy-ion run have been made where necessary. The maximal design rate of 100 kHz can be sustained without problems. All L1 latencies have been rechecked. The recently installed Forward Scintillating Counters (FSC) are being used in the heavy ion run. The ZDC scintillators have been dismantled, but the calorimeter itself remains. We now send the L1 accept signal and other control signals to TOTEM. Trigger cables from TOTEM to CMS will be installed during the Christmas shutdown, so that the TOTEM data can be fully integrated within the CMS readout. New beam gas triggers have been developed, since the BSC-based trigger is no longer usable at high luminosities. In particular, a special BPTX signal is used after a quiet period with no collisions. There is an ongoing campaign to provide enough spare modules for the different subsystems. For example...

  15. TRIGGER

    CERN Multimedia

    J. Alimena

    2013-01-01

    Trigger Strategy Group The Strategy for Trigger Evolution And Monitoring (STEAM) group is responsible for the development of future High-Level Trigger menus, as well as of its DQM and validation, in collaboration and with the technical support of the PdmV group. Taking into account the beam energy and luminosity expected in 2015, a rough estimate of the trigger rates indicates a factor four increase with respect to 2012 conditions. Assuming that a factor two can be tolerated thanks to the increase in offline storage and processing capabilities, a toy menu has been developed using the new OpenHLT workflow to estimate the transverse energy/momentum thresholds that would halve the current trigger rates. The CPU time needed to run the HLT has been compared between data taken with 25 ns and 50 ns bunch spacing, for equivalent pile-up: no significant difference was observed on the global time per event distribution at the only available data point, corresponding to a pile-up of about 10 interactions. Using th...

  16. Design Considerations for an Upgraded Track-Finding Processor in the Level-1 Endcap Muon Trigger of CMS for SLHC Operations

    CERN Document Server

    Madorsky, Alexander

    2009-01-01

    D. Acosta, M. Fisher, I. Furic, J. Gartner, G.P. Di Giovanni, A. Hammar, K. Kotov, A. Madorsky, D. Wang University of Florida/Physics, POB 118440, Gainesville, FL, USA, 32611 L. Uvarov Petersburg Nuclear Physics Institute, Gatchina, Russia M. Matveev, P. Padley Rice University, MS 61, 6100 Main Street, Houston, TX, USA, 77005 The conceptual design for a Level-1 muon track-finder trigger for the CMS endcap muon system is proposed that can accommodate the increased particle occupancy and system constraints of the proposed SLHC accelerator upgrade and the CMS detector upgrades. A brief review of the architecture of the current track-finder for LHC trigger operation is given, with potential bottlenecks indicated for SLHC operation. The upgraded track-finding processors described here would receive as many as two track segments detected from every cathode strip chamber comprising the endcap muon system, up to a total of 18 per 60 degree azimuthal sector. This would dramatically improve the efficiency of the ...

  17. TRIGGER

    CERN Multimedia

    W. Smith

    Level-1 Trigger Hardware The CERN group is working on the TTC system. Seven out of nine sub-detector TTC VME crates with all fibers cabled are installed in USC55. 17 Local Trigger Controller (LTC) boards have been received from production and are in the process of being tested. The RF2TTC module replacing the TTCmi machine interface has been delivered and will replace the TTCci module used to mimic the LHC clock. 11 out of 12 crates housing the barrel ECAL off-detector electronics have been installed in USC55 after commissioning at the Electronics Integration Centre in building 904. The cabling to the Regional Calorimeter Trigger (RCT) is terminated. The Lisbon group has completed the Synchronization and Link mezzanine board (SLB) production. The Palaiseau group has fully tested and installed 33 out of 40 Trigger Concentrator Cards (TCC). The seven remaining boards are being remade. The barrel TCC boards have been tested at the H4 test beam, and good agreement with emulator predictions were found. The cons...

  18. Efficient Architectures for Low Latency and High Throughput Trading Systems on the JVM

    Directory of Open Access Journals (Sweden)

    Alexandru LIXANDRU

    2013-01-01

    Full Text Available The motivation for our research starts from the common belief that the Java platform is not suitable for implementing ultra-high performance applications. Java is one of the most widely used software development platform in the world, and it provides the means for rapid development of robust and complex applications that are easy to extend, ensuring short time-to-market of initial deliveries and throughout the lifetime of the system. The Java runtime environment, and especially the Java Virtual Machine, on top of which applications are executed, is the principal source of concerns in regards to its suitability in the electronic trading environment, mainly because of its implicit memory management. In this paper, we intend to identify some of the most common measures that can be taken, both at the Java runtime environment level and at the application architecture level, which can help Java applications achieve ultra-high performance. We also propose two efficient architectures for exchange trading systems that allow for ultra-low latencies and high throughput.

  19. JPEG XS, a new standard for visually lossless low-latency lightweight image compression

    Science.gov (United States)

    Descampe, Antonin; Keinert, Joachim; Richter, Thomas; Fößel, Siegfried; Rouvroy, Gaël.

    2017-09-01

    JPEG XS is an upcoming standard from the JPEG Committee (formally known as ISO/IEC SC29 WG1). It aims to provide an interoperable visually lossless low-latency lightweight codec for a wide range of applications including mezzanine compression in broadcast and Pro-AV markets. This requires optimal support of a wide range of implementation technologies such as FPGAs, CPUs and GPUs. Targeted use cases are professional video links, IP transport, Ethernet transport, real-time video storage, video memory buffers, and omnidirectional video capture and rendering. In addition to the evaluation of the visual transparency of the selected technologies, a detailed analysis of the hardware and software complexity as well as the latency has been done to make sure that the new codec meets the requirements of the above-mentioned use cases. In particular, the end-to-end latency has been constrained to a maximum of 32 lines. Concerning the hardware complexity, neither encoder nor decoder should require more than 50% of an FPGA similar to Xilinx Artix 7 or 25% of an FPGA similar to Altera Cyclon 5. This process resulted in a coding scheme made of an optional color transform, a wavelet transform, the entropy coding of the highest magnitude level of groups of coefficients, and the raw inclusion of the truncated wavelet coefficients. This paper presents the details and status of the standardization process, a technical description of the future standard, and the latest performance evaluation results.

  20. Low-power low-latency MAC protocol for aeronautical applications

    Science.gov (United States)

    Sabater, Jordi; Kluge, Martin; Bovelli, Sergio; Schalk, Josef

    2007-05-01

    This paper describes asynchronous MAC (Medium Access Control) strategies based on the IEEE 802.15.4 physical layer for wireless aeronautical applications where low power and low latency are important requirements as well as security and data integrity. Sensor data is acquired and collected on request, by means of a mobile device, and later stored in a centralized database. In order to have the smallest power consumption the wireless sensor has to remain in deep sleep mode as long as possible and wake up and listen periodically for RF activity. If its unique ID is mentioned in the destination address field, the complete frame is received, processed and replied if necessary. If the detected packet is addressed to another sensor the reception will stop immediately and the wireless sensor will go into deep sleep mode again. Listening instead of sending actively does not 'pollute' the already crowded 2.45GHz spectrum, reduces collisions and increases security. The mobile data concentrator can not be synchronized with all the sensors installed in a distributed environment, therefore smart asynchronous data transmission strategies are needed to reduce latencies and increase throughput. For the considered application, sensors are independent of each other, simply share the medium and together with the data concentrator are organized in a star network topology. The centre of the star is the concentrator which is rarely in range. It coordinates and activates the wireless sensor nodes to collect the measured data.

  1. High-throughput and low-latency network communication with NetIO

    CERN Document Server

    AUTHOR|(CDS)2088631; The ATLAS collaboration

    2017-01-01

    HPC network technologies like Infiniband, TrueScale or OmniPath provide low-latency and high-throughput communication between hosts, which makes them attractive options for data-acquisition systems in large-scale high-energy physics experiments. Like HPC networks, DAQ networks are local and include a well specified number of systems. Unfortunately traditional network communication APIs for HPC clusters like MPI or PGAS target exclusively the HPC community and are not suited well for DAQ applications. It is possible to build distributed DAQ applications using low-level system APIs like Infiniband Verbs, but it requires a non-negligible effort and expert knowledge. At the same time, message services like ZeroMQ have gained popularity in the HEP community. They allow building distributed applications with a high-level approach and provide good performance. Unfortunately their usage usually limits developers to TCP/IP-based networks. While it is possible to operate a TCP/IP stack on top of Infiniband and OmniPath...

  2. Design and Analysis of a Low Latency Deterministic Network MAC for Wireless Sensor Networks.

    Science.gov (United States)

    Sahoo, Prasan Kumar; Pattanaik, Sudhir Ranjan; Wu, Shih-Lin

    2017-09-22

    The IEEE 802.15.4e standard has four different superframe structures for different applications. Use of a low latency deterministic network (LLDN) superframe for the wireless sensor network is one of them, which can operate in a star topology. In this paper, a new channel access mechanism for IEEE 802.15.4e-based LLDN shared slots is proposed, and analytical models are designed based on this channel access mechanism. A prediction model is designed to estimate the possible number of retransmission slots based on the number of failed transmissions. Performance analysis in terms of data transmission reliability, delay, throughput and energy consumption are provided based on our proposed designs. Our designs are validated for simulation and analytical results, and it is observed that the simulation results well match with the analytical ones. Besides, our designs are compared with the IEEE 802.15.4 MAC mechanism, and it is shown that ours outperforms in terms of throughput, energy consumption, delay and reliability.

  3. Analisa Perbandingan Quality of Service Voice Over IP dengan Pengujian Codec Menggunakan Algoritma Low Latency Queuing

    Directory of Open Access Journals (Sweden)

    Darmawan Darmawan

    2017-09-01

    Full Text Available Voice over IP (VoIP adalah solusi komunikasi suara yang murah karena menggunakan jaringan IP dibanding penggunaan telephone analog yang banyak memakan biaya. Dalam penerapannya, VoIP mengalami permasalahan karena menggunakan teknologi packet switching yang mana penggunaannya bersamaan dengan paket data sehingga timbul delay, jitter, dan packet loss.  Pada penelitian ini, algoritma Low Latency Queuing (LLQ diterapkan pada router cisco. Algoritma LLQ merupakan gabungan dari algoritma Priority Queuing (PQ dan Class Based Weight Fair Queuing (CBWFQ sehingga dapat memprioritaskan paket suara disamping paket data. Algoritma LLQ ini diujikan menggunakan codec GSM FR, G722, dan G711 A-law. Hasil pengujian didapatkan nilai parameter yang tidak jauh berbeda dan memenuhi standar ITU-T.G1010. Nilai delay rata - rata terendah yaitu ketika menggunakan codec G722 sebesar 20,019 ms tetapi G722 memiliki rata - rata jitter yang terbesar yaitu 0,986 ms.  Codec dengan jitter rata – rata terkecil adalah G711 A-law sebesar 0,838 ms. Packet loss untuk semua codec yang diujikan adalah 0%.  Throughput pada paket data terbesar saat menggunakan codec GSM FR yaitu 18,139 kbps. Codec yang direkomendasikan adalah G711 A-law karena lebih stabil dari segi jitter dan codec GSM FR cocok diimplementasikan pada jaringan yang memiliki bandwitdh kecil.

  4. Implementing a low-latency parallel graphic equalizer with heterogeneous computing

    NARCIS (Netherlands)

    Norilo, Vesa; Verstraelen, Martinus Johannes Wilhelmina; Valimaki, Vesa; Svensson, Peter; Kristiansen, Ulf

    2015-01-01

    This paper describes the implementation of a recently introduced parallel graphic equalizer (PGE) in a heterogeneous way. The control and audio signal processing parts of the PGE are distributed to a PC and to a signal processor, of WaveCore architecture, respectively. This arrangement is

  5. Construction and Evaluation of an Ultra Low Latency Frameless Renderer for VR.

    Science.gov (United States)

    Friston, Sebastian; Steed, Anthony; Tilbury, Simon; Gaydadjiev, Georgi

    2016-04-01

    Latency - the delay between a user's action and the response to this action - is known to be detrimental to virtual reality. Latency is typically considered to be a discrete value characterising a delay, constant in time and space - but this characterisation is incomplete. Latency changes across the display during scan-out, and how it does so is dependent on the rendering approach used. In this study, we present an ultra-low latency real-time ray-casting renderer for virtual reality, implemented on an FPGA. Our renderer has a latency of ~1 ms from 'tracker to pixel'. Its frameless nature means that the region of the display with the lowest latency immediately follows the scan-beam. This is in contrast to frame-based systems such as those using typical GPUs, for which the latency increases as scan-out proceeds. Using a series of high and low speed videos of our system in use, we confirm its latency of ~1 ms. We examine how the renderer performs when driving a traditional sequential scan-out display on a readily available HMO, the Oculus Rift OK2. We contrast this with an equivalent apparatus built using a GPU. Using captured human head motion and a set of image quality measures, we assess the ability of these systems to faithfully recreate the stimuli of an ideal virtual reality system - one with a zero latency tracker, renderer and display running at 1 kHz. Finally, we examine the results of these quality measures, and how each rendering approach is affected by velocity of movement and display persistence. We find that our system, with a lower average latency, can more faithfully draw what the ideal virtual reality system would. Further, we find that with low display persistence, the sensitivity to velocity of both systems is lowered, but that it is much lower for ours.

  6. Overview and performance of the ATLAS Level-1 Topological Trigger

    CERN Document Server

    Damp, Johannes Frederic; The ATLAS collaboration

    2018-01-01

    In 2017 the LHC provided proton-proton collisions to the ATLAS experiment with high luminosity (up to 2.06x10^34), placing stringent operational and physical requirements on the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency of less than 2.5 μs. An important role is played by its newly commissioned component: the L1 topological trigger (L1Topo). This innovative system consists of two blades designed in AdvancedTCA form factor, mounting four individual state-of-the-art processors, and providing high input bandwidth and low latency data processing. Up to 128 topological trigger algorithms can be implemented to select interesting events by applying kinematic and angular requirements on electromagnetic clusters, jets, muons and total energy. This results in a significantly...

  7. High-Throughput and Low-Latency Network Communication with NetIO

    Science.gov (United States)

    Schumacher, Jörn; Plessl, Christian; Vandelli, Wainer

    2017-10-01

    HPC network technologies like Infiniband, TrueScale or OmniPath provide low- latency and high-throughput communication between hosts, which makes them attractive options for data-acquisition systems in large-scale high-energy physics experiments. Like HPC networks, DAQ networks are local and include a well specified number of systems. Unfortunately traditional network communication APIs for HPC clusters like MPI or PGAS exclusively target the HPC community and are not suited well for DAQ applications. It is possible to build distributed DAQ applications using low-level system APIs like Infiniband Verbs, but it requires a non-negligible effort and expert knowledge. At the same time, message services like ZeroMQ have gained popularity in the HEP community. They make it possible to build distributed applications with a high-level approach and provide good performance. Unfortunately, their usage usually limits developers to TCP/IP- based networks. While it is possible to operate a TCP/IP stack on top of Infiniband and OmniPath, this approach may not be very efficient compared to a direct use of native APIs. NetIO is a simple, novel asynchronous message service that can operate on Ethernet, Infiniband and similar network fabrics. In this paper the design and implementation of NetIO is presented and described, and its use is evaluated in comparison to other approaches. NetIO supports different high-level programming models and typical workloads of HEP applications. The ATLAS FELIX project [1] successfully uses NetIO as its central communication platform. The architecture of NetIO is described in this paper, including the user-level API and the internal data-flow design. The paper includes a performance evaluation of NetIO including throughput and latency measurements. The performance is compared against the state-of-the- art ZeroMQ message service. Performance measurements are performed in a lab environment with Ethernet and FDR Infiniband networks.

  8. Coexistence of enhanced mobile broadband communications and ultra-reliable low-latency communications in mobile front-haul

    Science.gov (United States)

    Ying, Kai; Kowalski, John M.; Nogami, Toshizo; Yin, Zhanping; Sheng, Jia

    2018-01-01

    5G systems are supposed to support coexistence of multiple services such as ultra reliable low latency communications (URLLC) and enhanced mobile broadband (eMBB) communications. The target of eMBB communications is to meet the high-throughput requirement while URLLC are used for some high priority services. Due to the sporadic nature and low latency requirement, URLLC transmission may pre-empt the resource of eMBB transmission. Our work is to analyze the URLLC impact on eMBB transmission in mobile front-haul. Then, some solutions are proposed to guarantee the reliability/latency requirements for URLLC services and minimize the impact to eMBB services at the same time.

  9. Low-latency Science Exploration of Planetary Bodies: a Demonstration Using ISS in Support of Mars Human Exploration

    Science.gov (United States)

    Thronson, Harley A.; Valinia, Azita; Bleacher, Jacob; Eigenbrode, Jennifer; Garvin, Jim; Petro, Noah

    2014-01-01

    We summarize a proposed experiment to use the International Space Station to formally examine the application and validation of low-latency telepresence for surface exploration from space as an alternative, precursor, or potentially as an adjunct to astronaut "boots on the ground." The approach is to develop and propose controlled experiments, which build upon previous field studies and which will assess the effects of different latencies (0 to 500 msec), task complexity, and alternate forms of feedback to the operator. These experiments serve as an example of a pathfinder for NASA's roadmap of missions to Mars with low-latency telerobotic exploration as a precursor to astronaut's landing on the surface to conduct geological tasks.

  10. Configurable Crossbar Switch for Deterministic, Low-latency Inter-blade Communications in a MicroTCA Platform

    Energy Technology Data Exchange (ETDEWEB)

    Karamooz, Saeed [Vadatech Inc. (United States); Breeding, John Eric [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States); Justice, T Alan [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2017-08-01

    As MicroTCA expands into applications beyond the telecommunications industry from which it originated, it faces new challenges in the area of inter-blade communications. The ability to achieve deterministic, low-latency communications between blades is critical to realizing a scalable architecture. In the past, legacy bus architectures accomplished inter-blade communications using dedicated parallel buses across the backplane. Because of limited fabric resources on its backplane, MicroTCA uses the carrier hub (MCH) for this purpose. Unfortunately, MCH products from commercial vendors are limited to standard bus protocols such as PCI Express, Serial Rapid IO and 10/40GbE. While these protocols have exceptional throughput capability, they are neither deterministic nor necessarily low-latency. To overcome this limitation, an MCH has been developed based on the Xilinx Virtex-7 690T FPGA. This MCH provides the system architect/developer complete flexibility in both the interface protocol and routing of information between blades. In this paper, we present the application of this configurable MCH concept to the Machine Protection System under development for the Spallation Neutron Sources's proton accelerator. Specifically, we demonstrate the use of the configurable MCH as a 12x4-lane crossbar switch using the Aurora protocol to achieve a deterministic, low-latency data link. In this configuration, the crossbar has an aggregate bandwidth of 48 GB/s.

  11. Low-Latency Digital Signal Processing for Feedback and Feedforward in Quantum Computing and Communication

    Science.gov (United States)

    Salathé, Yves; Kurpiers, Philipp; Karg, Thomas; Lang, Christian; Andersen, Christian Kraglund; Akin, Abdulkadir; Krinner, Sebastian; Eichler, Christopher; Wallraff, Andreas

    2018-03-01

    Quantum computing architectures rely on classical electronics for control and readout. Employing classical electronics in a feedback loop with the quantum system allows us to stabilize states, correct errors, and realize specific feedforward-based quantum computing and communication schemes such as deterministic quantum teleportation. These feedback and feedforward operations are required to be fast compared to the coherence time of the quantum system to minimize the probability of errors. We present a field-programmable-gate-array-based digital signal processing system capable of real-time quadrature demodulation, a determination of the qubit state, and a generation of state-dependent feedback trigger signals. The feedback trigger is generated with a latency of 110 ns with respect to the timing of the analog input signal. We characterize the performance of the system for an active qubit initialization protocol based on the dispersive readout of a superconducting qubit and discuss potential applications in feedback and feedforward algorithms.

  12. Implementation of a Low-Latency Contention-Free Geographical Routing Scheme for Mobile Cyber-Physical Systems

    KAUST Repository

    Bader, Ahmed

    2015-07-09

    Results and lessons learned from the implementation of a novel ultra low-latency geo-routing scheme are presented in this paper. The geo-routing scheme is intended for team-based mobile cyber-physical systems whereby a cluster of unmanned vehicles (robots) are deployed to accomplish a critical mission under human supervision. The contention-free nature of the developed scheme lends itself to jointly achieve lower latency and higher throughput. Implementation challenges are presented and corresponding resolutions are discussed herewith.

  13. Alert: An Adaptive Low-Latency Event-Driven MAC Protocol for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Vinod Namboodiri

    2011-01-01

    Full Text Available Collection of rare but delay-critical messages from a group of sensor nodes is a key process in many wireless sensor network applications. This is particularly important for security-related applications like intrusion detection and fire alarm systems. An event sensed by multiple sensor nodes in the network can trigger many messages to be sent simultaneously. We present Alert, a MAC protocol for collecting event-triggered urgent messages from a group of sensor nodes with minimum latency and without requiring any cooperation or prescheduling among the senders or between senders and receiver during protocol execution. Alert is designed to handle multiple simultaneous messages from different nodes efficiently and reliably, minimizing the overall delay to collect all messages along with the delay to get the first message. Moreover, the ability of the network to handle a large number of simultaneous messages does not come at the cost of excessive delays when only a few messages need to be handled. We analyze Alert and evaluate its feasibility and performance with an implementation on commodity hardware. We further compare Alert with existing approaches through simulations and show the performance improvement possible through Alert.

  14. Complexity optimization and high-throughput low-latency hardware implementation of a multi-electrode spike-sorting algorithm.

    Science.gov (United States)

    Dragas, Jelena; Jackel, David; Hierlemann, Andreas; Franke, Felix

    2015-03-01

    Reliable real-time low-latency spike sorting with large data throughput is essential for studies of neural network dynamics and for brain-machine interfaces (BMIs), in which the stimulation of neural networks is based on the networks' most recent activity. However, the majority of existing multi-electrode spike-sorting algorithms are unsuited for processing high quantities of simultaneously recorded data. Recording from large neuronal networks using large high-density electrode sets (thousands of electrodes) imposes high demands on the data-processing hardware regarding computational complexity and data transmission bandwidth; this, in turn, entails demanding requirements in terms of chip area, memory resources and processing latency. This paper presents computational complexity optimization techniques, which facilitate the use of spike-sorting algorithms in large multi-electrode-based recording systems. The techniques are then applied to a previously published algorithm, on its own, unsuited for large electrode set recordings. Further, a real-time low-latency high-performance VLSI hardware architecture of the modified algorithm is presented, featuring a folded structure capable of processing the activity of hundreds of neurons simultaneously. The hardware is reconfigurable “on-the-fly” and adaptable to the nonstationarities of neuronal recordings. By transmitting exclusively spike time stamps and/or spike waveforms, its real-time processing offers the possibility of data bandwidth and data storage reduction.

  15. Reducing the PAPR in FBMC-OQAM systems with low-latency trellis-based SLM technique

    Science.gov (United States)

    Bulusu, S. S. Krishna Chaitanya; Shaiek, Hmaied; Roviras, Daniel

    2016-12-01

    Filter-bank multi-carrier (FBMC) modulations, and more specifically FBMC-offset quadrature amplitude modulation (OQAM), are seen as an interesting alternative to orthogonal frequency division multiplexing (OFDM) for the 5th generation radio access technology. In this paper, we investigate the problem of peak-to-average power ratio (PAPR) reduction for FBMC-OQAM signals. Recently, it has been shown that FBMC-OQAM with trellis-based selected mapping (TSLM) scheme not only is superior to any scheme based on symbol-by-symbol approach but also outperforms that of the OFDM with classical SLM scheme. This paper is an extension of that work, where we analyze the TSLM in terms of computational complexity, required hardware memory, and latency issues. We have proposed an improvement to the TSLM, which requires very less hardware memory, compared to the originally proposed TSLM, and also have low latency. Additionally, the impact of the time duration of partial PAPR on the performance of TSLM is studied, and its lower bound has been identified by proposing a suitable time duration. Also, a thorough and fair comparison of performance has been done with an existing trellis-based scheme proposed in literature. The simulation results show that the proposed low-latency TSLM yields better PAPR reduction performance with relatively less hardware memory requirements.

  16. Commissioning and Validation of the ATLAS Level-1 Topological Trigger in Run 2

    CERN Document Server

    Zheng, Daniel; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment has introduced and recently commissioned a completely new hardware sub-system of its first-level trigger: the topological processor (L1Topo). L1Topo consist of two AdvancedTCA blades mounting state-of-the-art FPGA processors, providing high input bandwidth (up to 4 Gb/s) and low latency data processing (200 ns). L1Topo is able to select collision events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Results from data recorded using the L1Topo trigger will be presented. These results demonstrate a significantly improved background event rejection, thus allowing for rate reduction with minimal efficiency loss. This improvement has been shown for several physics processes leading to low-$p_T$ leptons, including $H\\rightarrow\\tau \\tau$ and $J/\\psi \\rightarrow \\mu \\mu$. In addition to describing the L1Topo trigger system, we will discuss the use of an accurate L1Topo simulation as a pow...

  17. Near real time/low latency data collection for climate warming manipulations and an elevated CO2 SPRUCE experiment

    Science.gov (United States)

    Krassovski, M.; Hanson, P. J.; Riggs, J. S.; Nettles, W. R., IV

    2017-12-01

    Climate change studies are one of the most important aspects of modern science and related experiments are getting bigger and more complex. One such experiment is the Spruce and Peatland Responses Under Climatic and Environmental Change experiment (SPRUCE, http://mnspruce.ornl.gov) conducted in in northern Minnesota, 40 km north of Grand Rapids, in the USDA Forest Service Marcell Experimental Forest (MEF). The SPRUCE experimental mission is to assess ecosystem-level biological responses of vulnerable, high carbon terrestrial ecosystems to a range of climate warming manipulations and an elevated CO2 atmosphere. This manipulation experiment generates a lot of observational data and requires a reliable onsite data collection system, dependable methods to transfer data to a robust scientific facility, and real-time monitoring capabilities. This presentation shares our experience of establishing near real time/low latency data collection and monitoring system using satellite communication.

  18. High-throughput and low-latency 60GHz small-cell network architectures over radio-over-fiber technologies

    Science.gov (United States)

    Pleros, N.; Kalfas, G.; Mitsolidou, C.; Vagionas, C.; Tsiokos, D.; Miliou, A.

    2017-01-01

    Future broadband access networks in the 5G framework will need to be bilateral, exploiting both optical and wireless technologies. This paper deals with new approaches and synergies on radio-over-fiber (RoF) technologies and how those can be leveraged to seamlessly converge wireless technology for agility and mobility with passive optical networks (PON)-based backhauling. The proposed convergence paradigm is based upon a holistic network architecture mixing mm-wave wireless access with photonic integration, dynamic capacity allocation and network coding schemes to enable high bandwidth and low-latency fixed and 60GHz wireless personal area communications for gigabit rate per user, proposing and deploying on top a Medium-Transparent MAC (MT-MAC) protocol as a low-latency bandwidth allocation mechanism. We have evaluated alternative network topologies between the central office (CO) and the access point module (APM) for data rates up to 2.5 Gb/s and SC frequencies up to 60 GHz. Optical network coding is demonstrated for SCM-based signaling to enhance bandwidth utilization and facilitate optical-wireless convergence in 5G applications, reporting medium-transparent network coding directly at the physical layer between end-users communicating over a RoF infrastructure. Towards equipping the physical layer with the appropriate agility to support MT-MAC protocols, a monolithic InP-based Remote Antenna Unit optoelectronic PIC interface is shown that ensures control over the optical resource allocation assisting at the same time broadband wireless service. Finally, the MT-MAC protocol is analysed and simulation and analytical theoretical results are presented that are found to be in good agreement confirming latency values lower than 1msec for small- to mid-load conditions.

  19. A 96-channel FPGA-based Time-to-Digital Converter (TDC) and fast trigger processor module with multi-hit capability and pipeline

    International Nuclear Information System (INIS)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-01-01

    We describe an field-programmable gate arrays based (FPGA), 96-channel, Time-to-Digital converter (TDC) and trigger logic board intended for use with the Central Outer Tracker (COT) [T. Affolder et al., Nucl. Instr. and Meth. A 526 (2004) 249] in the CDF Experiment [The CDF-II detector is described in the CDF Technical Design Report (TDR), FERMILAB-Pub-96/390-E. The TDC described here is intended as a further upgrade beyond that described in the TDR] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGAs. The special capabilities of this device are the availability of 840MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2ns, a minimum input pulse width of 4.8ns and a minimum separation of 4.8ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47Mbytes/s. The TDC module also produces prompt trigger data every Tevatron crossing via a deadtimeless fast logic path that can be easily reprogrammed. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and

  20. Distributed metadata servers for cluster file systems using shared low latency persistent key-value metadata store

    Science.gov (United States)

    Bent, John M.; Faibish, Sorin; Pedone, Jr., James M.; Tzelnic, Percy; Ting, Dennis P. J.; Ionkov, Latchesar A.; Grider, Gary

    2017-12-26

    A cluster file system is provided having a plurality of distributed metadata servers with shared access to one or more shared low latency persistent key-value metadata stores. A metadata server comprises an abstract storage interface comprising a software interface module that communicates with at least one shared persistent key-value metadata store providing a key-value interface for persistent storage of key-value metadata. The software interface module provides the key-value metadata to the at least one shared persistent key-value metadata store in a key-value format. The shared persistent key-value metadata store is accessed by a plurality of metadata servers. A metadata request can be processed by a given metadata server independently of other metadata servers in the cluster file system. A distributed metadata storage environment is also disclosed that comprises a plurality of metadata servers having an abstract storage interface to at least one shared persistent key-value metadata store.

  1. 12-bit 32 channel 500 MS/s low-latency ADC for particle accelerators real-time control

    Science.gov (United States)

    Karnitski, Anton; Baranauskas, Dalius; Zelenin, Denis; Baranauskas, Gytis; Zhankevich, Alexander; Gill, Chris

    2017-09-01

    Particle beam control systems require real-time low latency digital feedback with high linearity and dynamic range. Densely packed electronic systems employ high performance multichannel digitizers causing excessive heat dissipation. Therefore, low power dissipation is another critical requirement for these digitizers. A described 12-bit 500 MS/s ADC employs a sub-ranging architecture based on a merged sample & hold circuit, a residue C-DAC and a shared 6-bit flash core ADC. The core ADC provides a sequential coarse and fine digitization featuring a latency of two clock cycles. The ADC is implemented in a 28 nm CMOS process and consumes 4 mW of power per channel from a 0.9 V supply (interfacing and peripheral circuits are excluded). Reduced power consumption and small on-chip area permits the implementation of 32 ADC channels on a 10.7 mm2 chip. The ADC includes a JESD204B standard compliant output data interface operated at the 7.5 Gbps/ch rate. To minimize the data interface related time latency, a special feature permitting to bypass the JESD204B interface is built in. DoE Phase I Award Number: DE-SC0017213.

  2. GPU-accelerated low-latency real-time searches for gravitational waves from compact binary coalescence

    International Nuclear Information System (INIS)

    Liu Yuan; Du Zhihui; Chung, Shin Kee; Hooper, Shaun; Blair, David; Wen Linqing

    2012-01-01

    We present a graphics processing unit (GPU)-accelerated time-domain low-latency algorithm to search for gravitational waves (GWs) from coalescing binaries of compact objects based on the summed parallel infinite impulse response (SPIIR) filtering technique. The aim is to facilitate fast detection of GWs with a minimum delay to allow prompt electromagnetic follow-up observations. To maximize the GPU acceleration, we apply an efficient batched parallel computing model that significantly reduces the number of synchronizations in SPIIR and optimizes the usage of the memory and hardware resource. Our code is tested on the CUDA ‘Fermi’ architecture in a GTX 480 graphics card and its performance is compared with a single core of Intel Core i7 920 (2.67 GHz). A 58-fold speedup is achieved while giving results in close agreement with the CPU implementation. Our result indicates that it is possible to conduct a full search for GWs from compact binary coalescence in real time with only one desktop computer equipped with a Fermi GPU card for the initial LIGO detectors which in the past required more than 100 CPUs. (paper)

  3. Low latency protocol for transmission of measurement data from FPGA to Linux computer via 10 Gbps Ethernet link

    International Nuclear Information System (INIS)

    Zabolotny, W.M.

    2015-01-01

    This paper presents FADE-10G—an integrated solution for modern multichannel measurement systems. Its main aim is a low latency, reliable transmission of measurement data from FPGA-based front-end electronic boards (FEBs) to a computer-based node in the Data Acquisition System (DAQ), using a standard Ethernet 1 Gbps or 10 Gbps link. In addition to transmission of data, the system allows the user to send reliably simple control commands from DAQ to FEB and to receive responses. The aim of the work is to provide a possible simple base solution, which can be adapted by the end user to his or her particular needs. Therefore, the emphasis is put on the minimal consumption of FPGA resources in FEB and the minimal CPU load in the DAQ computer. The open source implementation of the FPGA IP core and the Linux kernel driver published under permissive license facilitates modifications and reuse of the solution. The system has been successfully tested in real hardware, both with 1 Gbps and 10 Gbps links

  4. Low latency adaptive streaming of HD H.264 video over 802.11 wireless networks with cross-layer feedback

    Science.gov (United States)

    Patti, Andrew; Tan, Wai-tian; Shen, Bo

    2007-09-01

    Streaming video in consumer homes over wireless IEEE 802.11 networks is becoming commonplace. Wireless 802.11 networks pose unique difficulties for streaming high definition (HD), low latency video due to their error-prone physical layer and media access procedures which were not designed for real-time traffic. HD video streaming, even with sophisticated H.264 encoding, is particularly challenging due to the large number of packet fragments per slice. Cross-layer design strategies have been proposed to address the issues of video streaming over 802.11. These designs increase streaming robustness by imposing some degree of monitoring and control over 802.11 parameters from application level, or by making the 802.11 layer media-aware. Important contributions are made, but none of the existing approaches directly take the 802.11 queuing into account. In this paper we take a different approach and propose a cross-layer design allowing direct, expedient control over the wireless packet queue, while obtaining timely feedback on transmission status for each packet in a media flow. This method can be fully implemented on a media sender with no explicit support or changes required to the media client. We assume that due to congestion or deteriorating signal-to-noise levels, the available throughput may drop substantially for extended periods of time, and thus propose video source adaptation methods that allow matching the bit-rate to available throughput. A particular H.264 slice encoding is presented to enable seamless stream switching between streams at multiple bit-rates, and we explore using new computationally efficient transcoding methods when only a high bit-rate stream is available.

  5. A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

    Science.gov (United States)

    Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, T.; Vyrsokinos, K.; Pleros, N.

    2018-02-01

    The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

  6. High-Precision and Low Latency RT-GNSS Processed Data for Diverse Geophysical and Natural Hazard Communities.

    Science.gov (United States)

    Mencin, David; Hodgkinson, Kathleen; Sievers, Charlie; David, Phillips; Charles, Meertens; Glen, Mattioli

    2017-04-01

    UNAVCO has been providing infrastructure and support for solid-earth sciences and earthquake natural hazards for the past two decades. Recent advances in GNSS technology and data processing are now providing position solutions with centimeter-level precision at high-rate (>1 Hz) and low latency (i.e. the time required for data to arrive for analysis, in this case less than 1 second). These data have the potential to improve our understanding in diverse areas of geophysics including properties of seismic, volcanic, magmatic and tsunami sources, and thus profoundly transform rapid event characterization and warning. Scientific and operational applications also include glacier and ice sheet motions; tropospheric modeling; and space weather. These areas of geophysics represent a spectrum of research fields, including geodesy, seismology, tropospheric weather, space weather and natural hazards. Processed Real-Time GNSS (RT-GNSS) data will require formats and standards that allow this broad and diverse community to use these data and associated meta-data in existing research infrastructure. These advances have critically highlighted the difficulties associated with merging data and metadata between scientific disciplines. Even seemingly very closely related fields such as geodesy and seismology, which both have rich histories of handling large volumes of data and metadata, do not go together well in any automated way. Community analysis strategies, or lack thereof, such as treatment of error prove difficult to address and are reflected in the data and metadata. In addition, these communities have differing security, accessibility and reliability requirements. We propose some solutions to the particular problem of making RT-GNSS processed solution data and metadata accessible to multiply scientific and natural hazard communities. Importantly, we discuss the roadblocks encounter and solved and those that remain to be addressed.

  7. Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC Upgrades Summary

    CERN Document Server

    Madorsky, Alexander

    2017-01-01

    To accommodate high-luminosity LHC operation at 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide the best track reconstruction, the trigger system must now import all available trigger primitives generated by Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources.To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup Table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The µTCA architecture (ado...

  8. The Maia Spectroscopy Detector System: Engineering for Integrated Pulse Capture, Low-Latency Scanning and Real-Time Processing

    International Nuclear Information System (INIS)

    Kirkham, R.; Siddons, D.; Dunn, P.A.; Kuczewski, A.J.; Dodanwela, R.; Moorhead, G.F.; Ryan, C.G.; De Geronimo, G.; Beuttenmuller, R.; Pinelli, D.; Pfeffer, M.; Davey, P.; Jensen, M.; de Jonge, M.D.; Howard, D.L.; Kusel, M.; McKinlay, J.

    2010-01-01

    The Maia detector system is engineered for energy dispersive x-ray fluorescence spectroscopy and elemental imaging at photon rates exceeding 10 7 /s, integrated scanning of samples for pixel transit times as small as 50 (micro)s and high definition images of 10 8 pixels and real-time processing of detected events for spectral deconvolution and online display of pure elemental images. The system developed by CSIRO and BNL combines a planar silicon 384 detector array, application-specific integrated circuits for pulse shaping and peak detection and sampling and optical data transmission to an FPGA-based pipelined, parallel processor. This paper describes the system and the underpinning engineering solutions.

  9. L1Track: A fast Level 1 track trigger for the ATLAS high luminosity upgrade

    International Nuclear Information System (INIS)

    Cerri, Alessandro

    2016-01-01

    With the planned high-luminosity upgrade of the LHC (HL-LHC), the ATLAS detector will see its collision rate increase by approximately a factor of 5 with respect to the current LHC operation. The earliest hardware-based ATLAS trigger stage (“Level 1”) will have to provide a higher rejection factor in a more difficult environment: a new improved Level 1 trigger architecture is under study, which includes the possibility of extracting with low latency and high accuracy tracking information in time for the decision taking process. In this context, the feasibility of potential approaches aimed at providing low-latency high-quality tracking at Level 1 is discussed. - Highlights: • HL-LH requires highly performing event selection. • ATLAS is studying the implementation of tracking at the very first trigger level. • Low latency and high-quality seem to be achievable with dedicated hardware and adequate detector readout architecture.

  10. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  11. Online track processor for the CDF upgrade

    International Nuclear Information System (INIS)

    Thomson, E. J.

    2002-01-01

    A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

  12. VIRTUS: a multi-processor system in FASTBUS

    International Nuclear Information System (INIS)

    Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

    1986-01-01

    VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

  13. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  14. Triggers in UA2 and UA1

    International Nuclear Information System (INIS)

    Dorenbosch, J.

    1985-01-01

    The UA2 and UA1 trigger systems are described as they will be used after the upgrade of the CERN SPPS. The luminosity of the collider will increase to 3x10 30 . The bunch spacing is 4 microseconds, comparable to the time available for a second level trigger at the SSC. The first level triggers are very powerful and deliver trigger rates of about 100 Hz. The UA1 second level trigger operates on the final digitizings with a combination of special and general purpose processors. At the highest trigger levels a small farm of processors performs the final reduction. (orig.)

  15. A dedicated line-processor as used at the SHF

    International Nuclear Information System (INIS)

    Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

    1985-01-01

    A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

  16. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  17. Multithreading in vector processors

    Science.gov (United States)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  18. Low latency asynchronous interface circuits

    Science.gov (United States)

    Sadowski, Greg

    2017-06-20

    In one form, a logic circuit includes an asynchronous logic circuit, a synchronous logic circuit, and an interface circuit coupled between the asynchronous logic circuit and the synchronous logic circuit. The asynchronous logic circuit has a plurality of asynchronous outputs for providing a corresponding plurality of asynchronous signals. The synchronous logic circuit has a plurality of synchronous inputs corresponding to the plurality of asynchronous outputs, a stretch input for receiving a stretch signal, and a clock output for providing a clock signal. The synchronous logic circuit provides the clock signal as a periodic signal but prolongs a predetermined state of the clock signal while the stretch signal is active. The asynchronous interface detects whether metastability could occur when latching any of the plurality of the asynchronous outputs of the asynchronous logic circuit using said clock signal, and activates the stretch signal while the metastability could occur.

  19. The EarthScope Array Network Facility: application-driven low-latency web-based tools for accessing high-resolution multi-channel waveform data

    Science.gov (United States)

    Newman, R. L.; Lindquist, K. G.; Clemesha, A.; Vernon, F. L.

    2008-12-01

    Since April 2004 the EarthScope USArray seismic network has grown to over 400 broadband stations that stream multi-channel data in near real-time to the Array Network Facility in San Diego. Providing secure, yet open, access to real-time and archived data for a broad range of audiences is best served by a series of platform agnostic low-latency web-based applications. We present a framework of tools that interface between the world wide web and Boulder Real Time Technologies Antelope Environmental Monitoring System data acquisition and archival software. These tools provide audiences ranging from network operators and geoscience researchers, to funding agencies and the general public, with comprehensive information about the experiment. This ranges from network-wide to station-specific metadata, state-of-health metrics, event detection rates, archival data and dynamic report generation over a stations two year life span. Leveraging open source web-site development frameworks for both the server side (Perl, Python and PHP) and client-side (Flickr, Google Maps/Earth and jQuery) facilitates the development of a robust extensible architecture that can be tailored on a per-user basis, with rapid prototyping and development that adheres to web-standards.

  20. Integrated fuel processor development

    International Nuclear Information System (INIS)

    Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

    2001-01-01

    The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

  1. The ARGUS vertex trigger

    International Nuclear Information System (INIS)

    Koch, N.; Kolander, M.; Kolanoski, H.; Siegmund, T.; Bergter, J.; Eckstein, P.; Schubert, K.R.; Waldi, R.; Imhof, M.; Ressing, D.; Weiss, U.; Weseler, S.

    1995-09-01

    A fast second level trigger has been developed for the ARGUS experiment which recognizes tracks originating from the interaction region. The processor compares the hits in the ARGUS Micro Vertex Drift Chamber to 245760 masks stored in random access memories. The masks which are fully defined in three dimensions are able to reject tracks originating in the wall of the narrow beampipe of 10.5 mm radius. (orig.)

  2. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  3. 3081/E processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.

    1984-04-01

    The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

  4. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  5. Adaptive signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

  6. Adaptive signal processor

    International Nuclear Information System (INIS)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  7. The new UA1 calorimeter trigger

    International Nuclear Information System (INIS)

    Eisenhandler, E.

    1988-01-01

    The new UA1 first-level calorimeter trigger processor is described, with emphasis on the fast two-dimensional electromagnetic cluster-finding that is its most novel feature. This processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. (author)

  8. Electronics for CMS Endcap Muon Level-1 Trigger System Phase-1 and HL LHC upgrades

    Science.gov (United States)

    Madorsky, A.

    2017-07-01

    To accommodate high-luminosity LHC operation at a 13 TeV collision energy, the CMS Endcap Muon Level-1 Trigger system had to be significantly modified. To provide robust track reconstruction, the trigger system must now import all available trigger primitives generated by the Cathode Strip Chambers and by certain other subsystems, such as Resistive Plate Chambers (RPC). In addition to massive input bandwidth, this also required significant increase in logic and memory resources. To satisfy these requirements, a new Sector Processor unit has been designed. It consists of three modules. The Core Logic module houses the large FPGA that contains the track-finding logic and multi-gigabit serial links for data exchange. The Optical module contains optical receivers and transmitters; it communicates with the Core Logic module via a custom backplane section. The Pt Lookup table (PTLUT) module contains 1 GB of low-latency memory that is used to assign the final Pt to reconstructed muon tracks. The μ TCA architecture (adopted by CMS) was used for this design. The talk presents the details of the hardware and firmware design of the production system based on Xilinx Virtex-7 FPGA family. The next round of LHC and CMS upgrades starts in 2019, followed by a major High-Luminosity (HL) LHC upgrade starting in 2024. In the course of these upgrades, new Gas Electron Multiplier (GEM) detectors and more RPC chambers will be added to the Endcap Muon system. In order to keep up with all these changes, a new Advanced Processor unit is being designed. This device will be based on Xilinx UltraScale+ FPGAs. It will be able to accommodate up to 100 serial links with bit rates of up to 25 Gb/s, and provide up to 2.5 times more logic resources than the device used currently. The amount of PTLUT memory will be significantly increased to provide more flexibility for the Pt assignment algorithm. The talk presents preliminary details of the hardware design program.

  9. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  10. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  11. High-level trigger system for the LHC ALICE experiment

    CERN Document Server

    Bramm, R; Lien, J A; Lindenstruth, V; Loizides, C; Röhrich, D; Skaali, B; Steinbeck, T M; Stock, Reinhard; Ullaland, K; Vestbø, A S; Wiebalck, A

    2003-01-01

    The central detectors of the ALICE experiment at LHC will produce a data size of up to 75 MB/event at an event rate less than approximately equals 200 Hz resulting in a data rate of similar to 15 GB/s. Online processing of the data is necessary in order to select interesting (sub)events ("High Level Trigger"), or to compress data efficiently by modeling techniques. Processing this data requires a massive parallel computing system (High Level Trigger System). The system will consist of a farm of clustered SMP-nodes based on off- the-shelf PCs connected with a high bandwidth low latency network.

  12. 3081//sub E/ processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

    1983-03-01

    Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

  13. Progress on the Level-1 Calorimeter Trigger

    CERN Multimedia

    Eric Eisenhandler

    The Level-1 Calorimeter Trigger (L1Calo) has recently passed a number of major hurdles. The various electronic modules that make up the trigger are either in full production or are about to be, and preparations in the ATLAS pit are well advanced. L1Calo has three main subsystems. The PreProcessor converts analogue calorimeter signals to digital, associates the rather broad trigger pulses with the correct proton-proton bunch crossing, and does a final calibration in transverse energy before sending digital data streams to the two algorithmic trigger processors. The Cluster Processor identifies and counts electrons, photons and taus, and the Jet/Energy-sum Processor looks for jets and also sums missing and total transverse energy. Readout drivers allow the performance of the trigger to be monitored online and offline, and also send region-of-interest information to the Level-2 Trigger. The PreProcessor (Heidelberg) is the L1Calo subsystem with the largest number of electronic modules (124), and most of its fu...

  14. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

  15. The Molen Polymorphic Media Processor

    NARCIS (Netherlands)

    Kuzmanov, G.K.

    2004-01-01

    In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

  16. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  17. The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

    International Nuclear Information System (INIS)

    Maenner, R.; Deluigi, B.

    1981-01-01

    The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

  18. The STAR Level-3 trigger system

    International Nuclear Information System (INIS)

    Adler, C.; Berger, J.; Demello, M.; Dietel, T.; Flierl, D.; Landgraf, J.; Lange, J.S.; LeVine, M.J.; Ljubicic, A.; Nelson, J.; Roehrich, D.; Stock, R.; Struck, C.; Yepes, P.

    2003-01-01

    The STAR Level-3 trigger issues a trigger decision upon a complete online reconstruction of Au+Au collisions at relativistic heavy ion collider energies. Central interactions are processed up to a rate of 50 s -1 including a simple analysis of physics observables. The setup of the processor farm and the event reconstruction as well as experiences and the proposed trigger algorithms are described

  19. A trigger simulation framework for the ALICE experiment

    International Nuclear Information System (INIS)

    Antinori, F; Carminati, F; Gheata, A; Gheata, M

    2011-01-01

    A realistic simulation of the trigger system in a complex HEP experiment is essential for performing detailed trigger efficiency studies. The ALICE trigger simulation is evolving towards a framework capable of replaying the full trigger chain starting from the input to the individual trigger processors and ending with the decision mechanisms of the ALICE central trigger processor. This paper describes the new ALICE trigger simulation framework that is being tested and deployed. The framework handles details like trigger levels, signal delays and busy signals, implementing the trigger logic via customizable trigger device objects managed by a robust scheduling mechanism. A big advantage is the high flexibility of the framework, which is able to mix together components described with very different levels of detail. The framework is being gradually integrated within the ALICE simulation and reconstruction frameworks.

  20. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  1. Triggering with the ALICE TRD. Results and prospects

    Energy Technology Data Exchange (ETDEWEB)

    Klein, Jochen; Pachmayer, Yvonne [Physikalisches Institut, University of Heidelberg (Germany); Westerhoff, Uwe [Institut fuer Kernphysik, Universitaet Muenster (Germany); Collaboration: ALICE-Collaboration

    2015-07-01

    The ALICE Transition Radiation Detector provides multiple level-1 trigger contributions. The signatures are based on tracks which are reconstructed in an FPGA array from chamber-wise track segments. The latter are calculated on the detector-mounted frontend electronics. The massive parallelization allows for the low latency trigger 8 us after the interaction. We show the performance of the triggers on electrons and jets during LHC Run 1. Further, we discuss improvements and prospects for Run 2. In particular, an online calculation of the distance of closest approach to the primary vertex shall be used to reject the dominant background from the conversion of photons at large radii. The combination of tracks over stack and sector boundaries will help to improve the efficiency of the jet trigger.

  2. High level trigger system for the ALICE experiment

    International Nuclear Information System (INIS)

    Frankenfeld, U.; Roehrich, D.; Ullaland, K.; Vestabo, A.; Helstrup, H.; Lien, J.; Lindenstruth, V.; Schulz, M.; Steinbeck, T.; Wiebalck, A.; Skaali, B.

    2001-01-01

    The ALICE experiment at the Large Hadron Collider (LHC) at CERN will detect up to 20,000 particles in a single Pb-Pb event resulting in a data rate of ∼75 MByte/event. The event rate is limited by the bandwidth of the data storage system. Higher rates are possible by selecting interesting events and subevents (High Level trigger) or compressing the data efficiently with modeling techniques. Both require a fast parallel pattern recognition. One possible solution to process the detector data at such rates is a farm of clustered SMP nodes, based on off-the-shelf PCs, and connected by a high bandwidth, low latency network

  3. Video frame processor

    International Nuclear Information System (INIS)

    Joshi, V.M.; Agashe, Alok; Bairi, B.R.

    1993-01-01

    This report provides technical description regarding the Video Frame Processor (VFP) developed at Bhabha Atomic Research Centre. The instrument provides capture of video images available in CCIR format. Two memory planes each with a capacity of 512 x 512 x 8 bit data enable storage of two video image frames. The stored image can be processed on-line and on-line image subtraction can also be carried out for image comparisons. The VFP is a PC Add-on board and is I/O mapped within the host IBM PC/AT compatible computer. (author). 9 refs., 4 figs., 19 photographs

  4. Optical Finite Element Processor

    Science.gov (United States)

    Casasent, David; Taylor, Bradley K.

    1986-01-01

    A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

  5. The ATLAS Level-1 Trigger Timing Setup

    CERN Document Server

    Spiwoks, R; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS detector at CERN's LHC will be exposed to proton-proton collisions at a bunch-crossing rate of 40 MHz. In order to reduce the data rate, a three-level trigger system selects potentially interesting physics. The first trigger level is implemented in electronics and firmware. It aims at reducing the output rate to less than 100 kHz. The Central Trigger Processor combines information from the calorimeter and muon trigger processors and makes the final Level-1-Accept decision. It is a central element in the timing setup of the experiment. Three aspects are considered in this article: the timing setup with respect to the Level-1 trigger, with respect to the expriment, and with respect to the world.

  6. Trigger finger

    Science.gov (United States)

    ... digit; Trigger finger release; Locked finger; Digital flexor tenosynovitis ... cut or hand Yellow or green drainage from the cut Hand pain or discomfort Fever If your trigger finger returns, call your surgeon. You may need another surgery.

  7. High-performance parallel processors based on star-coupled wavelength division multiplexing optical interconnects

    Science.gov (United States)

    Deri, Robert J.; DeGroot, Anthony J.; Haigh, Ronald E.

    2002-01-01

    As the performance of individual elements within parallel processing systems increases, increased communication capability between distributed processor and memory elements is required. There is great interest in using fiber optics to improve interconnect communication beyond that attainable using electronic technology. Several groups have considered WDM, star-coupled optical interconnects. The invention uses a fiber optic transceiver to provide low latency, high bandwidth channels for such interconnects using a robust multimode fiber technology. Instruction-level simulation is used to quantify the bandwidth, latency, and concurrency required for such interconnects to scale to 256 nodes, each operating at 1 GFLOPS performance. Performance scales have been shown to .apprxeq.100 GFLOPS for scientific application kernels using a small number of wavelengths (8 to 32), only one wavelength received per node, and achievable optoelectronic bandwidth and latency.

  8. The ATLAS Level-1 Topological Trigger Performance

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371751; The ATLAS collaboration

    2016-01-01

    The LHC will collide protons in the ATLAS detector with increasing luminosity through 2016, placing stringent operational and physical requirements to the ATLAS trigger system in order to reduce the 40 MHz collision rate to a manageable event storage rate of 1 kHz, while not rejecting interesting physics events. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. During the LHC shutdown after the Run 1 finished in 2013, the Level-1 trigger system was upgraded including hardware, firmware and software updates. In particular, new electronics modules were introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which...

  9. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  10. The associative memory system for the FTK processor at ATLAS

    CERN Document Server

    Magalotti, D; The ATLAS collaboration; Donati, S; Luciano, P; Piendibene, M; Giannetti, P; Lanza, A; Verzellesi, G; Sakellariou, Andreas; Billereau, W; Combe, J M

    2014-01-01

    In high energy physics experiments, the most interesting processes are very rare and hidden in an extremely large level of background. As the experiment complexity, accelerator backgrounds, and instantaneous luminosity increase, more effective and accurate data selection techniques are needed. The Fast TracKer processor (FTK) is a real time tracking processor designed for the ATLAS trigger upgrade. The FTK core is the Associative Memory system. It provides massive computing power to minimize the processing time of complex tracking algorithms executed online. This paper reports on the results and performance of a new prototype of Associative Memory system.

  11. Use of a track and vertex processor in a fixed-target charm experiment

    International Nuclear Information System (INIS)

    Schub, M.H.; Carey, T.A.; Hsiung, Y.B.; Kaplan, D.M.; Lee, C.; Miller, G.; Sa, J.; Teng, P.K.

    1996-01-01

    We have constructed and operated a high-speed parallel-pipelined track and vertex processor and used it to trigger data acquisition in a high-rate charm and beauty experiment at Fermilab. The processor uses information from hodoscopes and wire chambers to reconstruct tracks in the bend view of a magnetic spectrometer, and uses these tracks to find the corresponding tracks in a set of silicon-strip detectors. The processor then forms vertices and triggers the experiment if at least one vertex is downstream of the target. Under typical charm running conditions, with an interaction rate of ∼5 MHz, the processor rejects 80-90% of lower-level triggers while maintaining efficiency of ∼70% for two-prong D-meson decays. (orig.)

  12. ATLAS FTK Fast Track Trigger

    CERN Document Server

    Iizawa, T; The ATLAS collaboration

    2014-01-01

    The Fast TracKer (FTK) will perform global track reconstruction after each Level-1 trigger accept signal to enable the software-based higher level trigger to have early access to tracking information. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGAs) form an important part of the system architecture, and the large level of computing power required for pattern recognition is provided by incorporating standard-cell ASICs named Associative Memory (AM). Motivation and the architecture of the FTK system will be presented, and the status of hardware and simulation will be following.

  13. The CDF level-3 trigger

    International Nuclear Information System (INIS)

    Devlin, T.

    1993-01-01

    The Collider Detector at Fermilab (CDF) has been operating at the Tevatron and collecting data on proton-antiproton interactions with collision rates above 250,000 Hz. Three levels of filtering select events for data logging at a rate of about 4 Hz. The Level 3 trigger provides most of the capabilities of the offline production programs for event reconstruction and physics analysis. The type of physics triggers, application of cuts, and combinations of logical requirements for event selection are controlled at run time by a trigger table using a syntax fully integrated with the Level 1 and Level 2 hardware triggers. The level 3 software operates in 48 RISC/UNIX processors (over 1000 mips) served by four 20-MByte/sec data buses for input, output and control. The system architecture, debugging, code validation, error reporting, analysis capabilities and performance will be described

  14. ATLAS FTK: Fast Track Trigger

    CERN Document Server

    Volpi, Guido; The ATLAS collaboration

    2015-01-01

    An overview of the ATLAS Fast Tracker processor is presented, reporting the design of the system, its expected performance, and the integration status. The next LHC runs, with a significant increase in instantaneous luminosity, will provide a big challenge to the trigger and data acquisition systems of all the experiments. An intensive use of the tracking information at the trigger level will be important to keep high efficiency in interesting events, despite the increase in multiple p-p collisions per bunch crossing (pile-up). In order to increase the use of tracks within the High Level Trigger (HLT), the ATLAS experiment planned the installation of an hardware processor dedicated to tracking: the Fast TracKer (FTK) processor. The FTK is designed to perform full scan track reconstruction at every Level-1 accept. To achieve this goal, the FTK uses a fully parallel architecture, with algorithms designed to exploit the computing power of custom VLSI chips, the Associative Memory, as well as modern FPGAs. The FT...

  15. Flexible trigger menu implementation on the Global Trigger for the CMS Level-1 trigger upgrade

    Science.gov (United States)

    MATSUSHITA, Takashi; CMS Collaboration

    2017-10-01

    The CMS experiment at the Large Hadron Collider (LHC) has continued to explore physics at the high-energy frontier in 2016. The integrated luminosity delivered by the LHC in 2016 was 41 fb-1 with a peak luminosity of 1.5 × 1034 cm-2s-1 and peak mean pile-up of about 50, all exceeding the initial estimations for 2016. The CMS experiment has upgraded its hardware-based Level-1 trigger system to maintain its performance for new physics searches and precision measurements at high luminosities. The Global Trigger is the final step of the CMS Level-1 trigger and implements a trigger menu, a set of selection requirements applied to the final list of objects from calorimeter and muon triggers, for reducing the 40 MHz collision rate to 100 kHz. The Global Trigger has been upgraded with state-of-the-art FPGA processors on Advanced Mezzanine Cards with optical links running at 10 GHz in a MicroTCA crate. The powerful processing resources of the upgraded system enable implementation of more algorithms at a time than previously possible, allowing CMS to be more flexible in how it handles the available trigger bandwidth. Algorithms for a trigger menu, including topological requirements on multi-objects, can be realised in the Global Trigger using the newly developed trigger menu specification grammar. Analysis-like trigger algorithms can be represented in an intuitive manner and the algorithms are translated to corresponding VHDL code blocks to build a firmware. The grammar can be extended in future as the needs arise. The experience of implementing trigger menus on the upgraded Global Trigger system will be presented.

  16. SDN-controlled topology-reconfigurable optical mobile fronthaul architecture for bidirectional CoMP and low latency inter-cell D2D in the 5G mobile era.

    Science.gov (United States)

    Cvijetic, Neda; Tanaka, Akihiro; Kanonakis, Konstantinos; Wang, Ting

    2014-08-25

    We demonstrate the first SDN-controlled optical topology-reconfigurable mobile fronthaul (MFH) architecture for bidirectional coordinated multipoint (CoMP) and low latency inter-cell device-to-device (D2D) connectivity in the 5G mobile networking era. SDN-based OpenFlow control is used to dynamically instantiate the CoMP and inter-cell D2D features as match/action combinations in control plane flow tables of software-defined optical and electrical switching elements. Dynamic re-configurability is thereby introduced into the optical MFH topology, while maintaining back-compatibility with legacy fiber deployments. 10 Gb/s peak rates with <7 μs back-to-back transmission latency and 29.6 dB total power budget are experimentally demonstrated, confirming the attractiveness of the new approach for optical MFH of future 5G mobile systems.

  17. Composable processor virtualization for embedded systems

    NARCIS (Netherlands)

    Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

    2010-01-01

    Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

  18. An Upgraded ATLAS Central Trigger for 2015 Luminosities

    International Nuclear Information System (INIS)

    Poettgen, Ruth; Gutenberg, Johannes

    2013-06-01

    The Central Trigger Processor (CTP) is a core unit of the first of three levels that constitute the ATLAS trigger system. Based on information from calorimeter and muon trigger processors as well as from some additional systems it produces the level-1 trigger decision and prompts the read-out of the sub-detectors. The increase in luminosity at the LHC has pushed the CTP operation to its design limits. In order to still satisfy the physics goals of the experiment after the shutdown of the LHC of 2013/2014 the CTP will be upgraded during this period. This article discusses the current Central Trigger Processor, the motivation for the upgrade, and the changes foreseen to meet the requirements of the post-2014 physics runs at the LHC. (authors)

  19. Distributed processor systems

    International Nuclear Information System (INIS)

    Zacharov, B.

    1976-01-01

    In recent years, there has been a growing tendency in high-energy physics and in other fields to solve computational problems by distributing tasks among the resources of inter-coupled processing devices and associated system elements. This trend has gained further momentum more recently with the increased availability of low-cost processors and with the development of the means of data distribution. In two lectures, the broad question of distributed computing systems is examined and the historical development of such systems reviewed. An attempt is made to examine the reasons for the existence of these systems and to discern the main trends for the future. The components of distributed systems are discussed in some detail and particular emphasis is placed on the importance of standards and conventions in certain key system components. The ideas and principles of distributed systems are discussed in general terms, but these are illustrated by a number of concrete examples drawn from the context of the high-energy physics environment. (Auth.)

  20. The ATLAS fast tracker processor design

    CERN Document Server

    Volpi, Guido; Albicocco, Pietro; Alison, John; Ancu, Lucian Stefan; Anderson, James; Andari, Nansi; Andreani, Alessandro; Andreazza, Attilio; Annovi, Alberto; Antonelli, Mario; Asbah, Needa; Atkinson, Markus; Baines, J; Barberio, Elisabetta; Beccherle, Roberto; Beretta, Matteo; Biesuz, Nicolo Vladi; Blair, R E; Bogdan, Mircea; Boveia, Antonio; Britzger, Daniel; Bryant, Partick; Burghgrave, Blake; Calderini, Giovanni; Camplani, Alessandra; Cavaliere, Viviana; Cavasinni, Vincenzo; Chakraborty, Dhiman; Chang, Philip; Cheng, Yangyang; Citraro, Saverio; Citterio, Mauro; Crescioli, Francesco; Dawe, Noel; Dell'Orso, Mauro; Donati, Simone; Dondero, Paolo; Drake, G; Gadomski, Szymon; Gatta, Mauro; Gentsos, Christos; Giannetti, Paola; Gkaitatzis, Stamatios; Gramling, Johanna; Howarth, James William; Iizawa, Tomoya; Ilic, Nikolina; Jiang, Zihao; Kaji, Toshiaki; Kasten, Michael; Kawaguchi, Yoshimasa; Kim, Young Kee; Kimura, Naoki; Klimkovich, Tatsiana; Kolb, Mathis; Kordas, K; Krizka, Karol; Kubota, T; Lanza, Agostino; Li, Ho Ling; Liberali, Valentino; Lisovyi, Mykhailo; Liu, Lulu; Love, Jeremy; Luciano, Pierluigi; Luongo, Carmela; Magalotti, Daniel; Maznas, Ioannis; Meroni, Chiara; Mitani, Takashi; Nasimi, Hikmat; Negri, Andrea; Neroutsos, Panos; Neubauer, Mark; Nikolaidis, Spiridon; Okumura, Y; Pandini, Carlo; Petridou, Chariclia; Piendibene, Marco; Proudfoot, James; Rados, Petar Kevin; Roda, Chiara; Rossi, Enrico; Sakurai, Yuki; Sampsonidis, Dimitrios; Saxon, James; Schmitt, Stefan; Schoening, Andre; Shochet, Mel; Shoijaii, Jafar; Soltveit, Hans Kristian; Sotiropoulou, Calliope-Louisa; Stabile, Alberto; Swiatlowski, Maximilian J; Tang, Fukun; Taylor, Pierre Thor Elliot; Testa, Marianna; Tompkins, Lauren; Vercesi, V; Wang, Rui; Watari, Ryutaro; Zhang, Jianhong; Zeng, Jian Cong; Zou, Rui; Bertolucci, Federico

    2015-01-01

    The extended use of tracking information at the trigger level in the LHC is crucial for the trigger and data acquisition (TDAQ) system to fulfill its task. Precise and fast tracking is important to identify specific decay products of the Higgs boson or new phenomena, as well as to distinguish the contributions coming from the many collisions that occur at every bunch crossing. However, track reconstruction is among the most demanding tasks performed by the TDAQ computing farm; in fact, complete reconstruction at full Level-1 trigger accept rate (100 kHz) is not possible. In order to overcome this limitation, the ATLAS experiment is planning the installation of a dedicated processor, the Fast Tracker (FTK), which is aimed at achieving this goal. The FTK is a pipeline of high performance electronics, based on custom and commercial devices, which is expected to reconstruct, with high resolution, the trajectories of charged-particle tracks with a transverse momentum above 1 GeV, using the ATLAS inner tracker info...

  1. Level-1 Calorimeter Trigger starts firing

    CERN Multimedia

    Stephen Hillier

    2007-01-01

    L1Calo is one of the major components of ATLAS First Level trigger, along with the Muon Trigger and Central Trigger Processor. It forms all of the first-level calorimeter-based triggers, including electron, jet, tau and missing ET. The final system consists of over 250 custom designed 9U VME boards, most containing a dense array of FPGAs or ASICs. It is subdivided into a PreProcessor, which digitises the incoming trigger signals from the Liquid Argon and Tile calorimeters, and two separate processor systems, which perform the physics algorithms. All of these are highly flexible, allowing the possibility to adapt to beam conditions and luminosity. All parts of the system are read out through Read-Out Drivers, which provide monitoring data and Region of Interest (RoI) information for the Level-2 trigger. Production of the modules is now essentially complete, and enough modules exist to populate the full scale system in USA15. Installation is proceeding rapidly - approximately 90% of the final modules are insta...

  2. Green Secure Processors: Towards Power-Efficient Secure Processor Design

    Science.gov (United States)

    Chhabra, Siddhartha; Solihin, Yan

    With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

  3. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    International Nuclear Information System (INIS)

    Foehlisch, F.

    2007-01-01

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  4. Calibration for the ATLAS Level-1 Calorimeter-Trigger

    Energy Technology Data Exchange (ETDEWEB)

    Foehlisch, F.

    2007-12-19

    This thesis describes developments and tests that are necessary to operate the Pre-Processor of the ATLAS Level-1 Calorimeter Trigger for data acquisition. The major tasks of Pre-Processor comprise the digitizing, time-alignment and the calibration of signals that come from the ATLAS calorimeter. Dedicated hardware has been developed that must be configured in order to fulfill these tasks. Software has been developed that implements the register-model of the Pre-Processor Modules and allows to set up the Pre-Processor. In order to configure the Pre-Processor in the context of an ATLAS run, user-settings and the results of calibration measurements are used to derive adequate settings for registers of the Pre-Processor. The procedures that allow to perform the required measurements and store the results into a database are demonstrated. Furthermore, tests that go along with the ATLAS installation are presented and results are shown. (orig.)

  5. Processors and systems (picture processing)

    Energy Technology Data Exchange (ETDEWEB)

    Gemmar, P

    1983-01-01

    Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

  6. Seismometer array station processors

    International Nuclear Information System (INIS)

    Key, F.A.; Lea, T.G.; Douglas, A.

    1977-01-01

    A description is given of the design, construction and initial testing of two types of Seismometer Array Station Processor (SASP), one to work with data stored on magnetic tape in analogue form, the other with data in digital form. The purpose of a SASP is to detect the short period P waves recorded by a UK-type array of 20 seismometers and to edit these on to a a digital library tape or disc. The edited data are then processed to obtain a rough location for the source and to produce seismograms (after optimum processing) for analysis by a seismologist. SASPs are an important component in the scheme for monitoring underground explosions advocated by the UK in the Conference of the Committee on Disarmament. With digital input a SASP can operate at 30 times real time using a linear detection process and at 20 times real time using the log detector of Weichert. Although the log detector is slower, it has the advantage over the linear detector that signals with lower signal-to-noise ratio can be detected and spurious large amplitudes are less likely to produce a detection. It is recommended, therefore, that where possible array data should be recorded in digital form for input to a SASP and that the log detector of Weichert be used. Trial runs show that a SASP is capable of detecting signals down to signal-to-noise ratios of about two with very few false detections, and at mid-continental array sites it should be capable of detecting most, if not all, the signals with magnitude above msub(b) 4.5; the UK argues that, given a suitable network, it is realistic to hope that sources of this magnitude and above can be detected and identified by seismological means alone. (author)

  7. Trigger Finger

    Science.gov (United States)

    ... in a bent position. People whose work or hobbies require repetitive gripping actions are at higher risk ... developing trigger finger include: Repeated gripping. Occupations and hobbies that involve repetitive hand use and prolonged gripping ...

  8. Smart trigger logic for focal plane arrays

    Science.gov (United States)

    Levy, James E; Campbell, David V; Holmes, Michael L; Lovejoy, Robert; Wojciechowski, Kenneth; Kay, Randolph R; Cavanaugh, William S; Gurrieri, Thomas M

    2014-03-25

    An electronic device includes a memory configured to receive data representing light intensity values from pixels in a focal plane array and a processor that analyzes the received data to determine which light values correspond to triggered pixels, where the triggered pixels are those pixels that meet a predefined set of criteria, and determines, for each triggered pixel, a set of neighbor pixels for which light intensity values are to be stored. The electronic device also includes a buffer that temporarily stores light intensity values for at least one previously processed row of pixels, so that when a triggered pixel is identified in a current row, light intensity values for the neighbor pixels in the previously processed row and for the triggered pixel are persistently stored, as well as a data transmitter that transmits the persistently stored light intensity values for the triggered and neighbor pixels to a data receiver.

  9. Arbitration in crossbar interconnect for low latency

    Science.gov (United States)

    Ohmacht, Martin; Sugavanam, Krishnan

    2013-02-05

    A system and method and computer program product for reducing the latency of signals communicated through a crossbar switch, the method including using at slave arbitration logic devices associated with Slave devices for which access is requested from one or more Master devices, two or more priority vector signals cycled among their use every clock cycle for selecting one of the requesting Master devices and updates the respective priority vector signal used every clock cycle. Similarly, each Master for which access is requested from one or more Slave devices, can have two or more priority vectors and can cycle among their use every clock cycle to further reduce latency and increase throughput performance via the crossbar.

  10. Natrium: Use of FPGA embedded processors for real-time data compression

    Energy Technology Data Exchange (ETDEWEB)

    Ammendola, R; Salamon, A; Salina, G [INFN Sezione di Roma Tor Vergata, Rome (Italy); Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P [INFN Sezione di Roma, Rome (Italy)

    2011-12-15

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  11. Natrium: Use of FPGA embedded processors for real-time data compression

    International Nuclear Information System (INIS)

    Ammendola, R; Salamon, A; Salina, G; Biagioni, A; Frezza, O; Cicero, F Lo; Lonardo, A; Rossetti, D; Simula, F; Tosoratto, L; Vicini, P

    2011-01-01

    We present test results and characterization of a data compression system for the readout of the NA62 liquid krypton calorimeter trigger processor. The Level-0 electromagnetic calorimeter trigger processor of the NA62 experiment at CERN receives digitized data from the calorimeter main readout board. These data are stored on an on-board DDR2 RAM memory and read out upon reception of a Level-0 accept signal. The maximum raw data throughput from the trigger front-end cards is 2.6 Gbps. To readout these data over two Gbit Ethernet interfaces we investigated different implementations of a data compression system based on the Rice-Golomb coding: one is implemented in the FPGA as a custom block and one is implemented on the FPGA embedded processor running a C code. The two implementations are tested on a set of sample events and compared with respect to achievable readout bandwidth.

  12. Flexible trigger menu implementation on the Global Trigger for the CMS Level-1 trigger upgrade

    CERN Document Server

    Matsushita, Takashi

    2017-01-01

    The CMS experiment at the Large Hadron Collider (LHC) has continued to explore physics at the high-energy frontier in 2016. The integrated luminosity delivered by the LHC in 2016 was 41~fb$^{-1}$ with a peak luminosity of 1.5 $\\times$ 10$^{34}$ cm$^{-2}$s$^{-1}$ and peak mean pile-up of about 50, all exceeding the initial estimations for 2016. The CMS experiment has upgraded its hardware-based Level-1 trigger system to maintain its performance for new physics searches and precision measurements at high luminosities. The Global Trigger is the final step of the CMS \\mbox{Level-1} trigger and implements a trigger menu, a set of selection requirements applied to the final list of objects from calorimeter and muon triggers, for reducing the 40 MHz collision rate to 100 kHz. The Global Trigger has been upgraded with state-of-the-art FPGA processors on Advanced Mezzanine Cards with optical links running at 10 GHz in a MicroTCA crate. The powerful processing resources of the upgraded system enable implemen...

  13. A Time-Multiplexed Track-Trigger architecture for CMS

    CERN Document Server

    Hall, Geoffrey; Pesaresi, Mark Franco; Rose, A

    2014-01-01

    The CMS Tracker under development for the High Luminosity LHC includes an outer tracker based on ``PT-modules'' which will provide track stubs based on coincident clusters in two closely spaced sensor layers, aiming to reject low transverse momentum track hits before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data is still an open question. One attractive option is to explore a Time Multiplexed design similar to one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The Time Multiplexed Trigger concept is explained, the potential benefits of applying it for processing future tracker data are described and a possible design based on cur...

  14. XL-100S microprogrammable processor

    International Nuclear Information System (INIS)

    Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

    1983-01-01

    The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

  15. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  16. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  17. Beam Test of the ATLAS Level-1 Calorimeter Trigger System

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Thomas, J P; Typaldos, D; Watkins, P M; Watson, A; Achenbach, R; Föhlisch, F; Geweniger, C; Hanke, P; Kluge, E E; Mahboubi, K; Meier, K; Meshkov, P; Rühr, F; Schmitt, K; Schultz-Coulon, H C; Ay, C; Bauss, B; Belkin, A; Rieke, S; Schäfer, U; Tapprogge, T; Trefzger, T; Weber, GA; Eisenhandler, E F; Landon, M; Apostologlou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Mirea, A; Perera, V J O; Qian, W; Sankey, D P C; Bohm, C; Hellman, S; Hidvegi, A; Silverstein, S

    2005-01-01

    The Level-1 Calorimter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce Region-of-Interest (RoIs) and trigger multiplicities. The latter are sent in real time to the Central Trigger Processor (CTP) where the Level-1 decision is made. On receipt of a Level-1 Accept, Readout Driver Modules (RODs), provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purpose. RoI information is sent to the RoI builder (RoIB) to help reduce the amount of data required for the Level-2 Trigger The Level-1 Calorimeter Trigger System at the test beam consisted of 1 Preprocessor module, 1 Cluster Processor Module, 1 Jet/Energy Module and 2 Common Merger Modules. Calorimeter energies were sucessfully handled thourghout the chain and trigger object sent to the CTP. Level-1 Accepts were sucessfully produced and used to drive the readout path. Online diagno...

  18. Optical Array Processor: Laboratory Results

    Science.gov (United States)

    Casasent, David; Jackson, James; Vaerewyck, Gerard

    1987-01-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

  19. The D OE software trigger

    International Nuclear Information System (INIS)

    Linnemann, J.T.; Michigan State Univ., East Lansing, MI

    1992-10-01

    In the D OE experiment, the software filter operates in a processor farm with each node processing a single event. Processing is data-driven: the filter does local processing to verify the candidates from the hardware trigger. The filter code consists of independent pieces called ''tools''; processing for a given hardware bit is a ''script'' invoking one or more ''tools'' sequentially. An offline simulator drives the same code with the same configuration files, running on real or simulated data. Online tests use farm nodes parasiting on the data stream. We discuss the performance of the system and how we attempt to verify its correctness

  20. Triggering Artefacts

    DEFF Research Database (Denmark)

    Mogensen, Preben Holst; Robinson, Mike

    1995-01-01

    and adapting them to specific situations need not be ad hoc.Triggering artefacts are a way of systematically challenging both designers' preunderstandings and the conservatism of work practice. Experiences from the Great Belt tunnel and bridge project are used to illustrate howtriggering artefacts change...

  1. Simulation of the ATLAS New Small Wheel Trigger Sysmtem

    CERN Document Server

    Saito, Tomoyuki; The ATLAS collaboration

    2017-01-01

    The instantaneous luminosity of the Large Hadron Collider (LHC) at CERN will be increased up to a factor of five with respect to the original design value to explore higher energy scale. In order to benefit from the expected high luminosity performance, the first station of the ATLAS muon end-cap Small Wheel system will be replaced by a New Small Wheel (NSW) detector. The NSW provide precise track segment information to the muon Level-1 trigger to reduce fake triggers. This contribution will summarize a detail of the NSW trigger decision system, track reconstruction algorithm implemented into the trigger processor and results of performance studies on the trigger system.

  2. The DOe Silicon Track Trigger

    International Nuclear Information System (INIS)

    Steinbrueck, Georg

    2003-01-01

    We describe a trigger preprocessor to be used by the DOe experiment for selecting events with tracks from the decay of long-lived particles. This Level 2 impact parameter trigger utilizes information from the Silicon Microstrip Tracker to reconstruct tracks with improved spatial and momentum resolutions compared to those obtained by the Level 1 tracking trigger. It is constructed of VME boards with much of the logic existing in programmable processors. A common motherboard provides the I/O infrastructure and three different daughter boards perform the tasks of identifying the roads from the tracking trigger data, finding the clusters in the roads in the silicon detector, and fitting tracks to the clusters. This approach provides flexibility for the design, testing and maintenance phases of the project. The track parameters are provided to the trigger framework in 25 μs. The effective impact parameter resolution for high-momentum tracks is 35 μm, dominated by the size of the Tevatron beam

  3. Programmable trigger for electron pairs in ring image Cherenkov counters

    International Nuclear Information System (INIS)

    Glab, J.; Baur, R.; Manner, R.

    1990-01-01

    This paper describes a programmable trigger processor for the recognition of Cherenkov rings in a RICH counter. It identifies open electron pairs and suppresses close conversion and Dalitz pairs within 20 μs. More generally, the system can be used for correlating pixel images with pattern masks in order to locate all relatively well defined patterns of a certain type. The trigger processor consists of a systolic processor array of 160 x 176, i.e., 28,160 identical processing elements (PEs) that filter out open electron pairs, and a pseudo adder array that determines whether there was at least one such pair. The processor array is assembled of 20 x 22 VLSI chips containing 8 x 8 PEs each. The semi-custom chip has been developed in 2 μ CMOS standard cell technology

  4. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Explicitly Parallel Instruction Computing (EPIC) is an instruction processing paradigm that has been in the spot- light due to its adoption by the next generation of Intel. Processors starting with the IA-64. The EPIC processing paradigm is an evolution of the Very Long Instruction. Word (VLIW) paradigm. This article gives an ...

  5. VON WISPR Family Processors: Volume 1

    National Research Council Canada - National Science Library

    Wagstaff, Ronald

    1997-01-01

    ...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

  6. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

  7. Deterministic chaos in the processor load

    International Nuclear Information System (INIS)

    Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

    2007-01-01

    In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

  8. Calorimeter trigger system for the ISR axial-field spectrometer

    International Nuclear Information System (INIS)

    1981-01-01

    A fast and flexible trigger processor system designed to run in parallel up to 51 different types of trigger is used in a large hadron calorimeter experiment at CERN-ISR. A very fast data bus connected to 255 10 bit address ECL memory chips allows programmable selection of events according to their topology and energy pattern in less than 150 ns. In addition this system can interrogate two programmable processors (ESOP) to isolate events characterized by a large energy flow in the central drift chamber (< 500 μs). All functions of the trigger processor can be checked externally by a computer through injecting in parallel simulated input signals into various stages of the system. Salient features and performances will be discussed

  9. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  10. The ATLAS Muon and Tau Trigger

    CERN Document Server

    Dell'Asta, L; The ATLAS collaboration

    2013-01-01

    [Muon] The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-levels processing scheme for the trigger system. The level-1 muon trigger system gets its input from fast muon trigger detectors. Fast sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a level-2 (L2) trigger followed by an event filter (EF) for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. Trigger-specific algorithms were developed and are used for the L2 to increase processing speed for instance by making use of look-up tables and simpler algorithms, while the EF muon triggers mostly benefit from offline reconstruction software to obtain most precise determination of the track parameters. There are two algorithms with different approaches, namely inside-out and outside-in...

  11. Online Fastbus processor for LEP

    International Nuclear Information System (INIS)

    Mueller, H.

    1986-01-01

    The author describes the online computing aspects of Fastbus systems using a processor module which has been developed at CERN and is now available commercially. These General Purpose Master/Slaves (GPMS) are based on 68000/10 (or optionally 68020/68881) processors. Applications include use as event-filters (DELPHI), supervisory controllers, Fastbus stand-alone diagnostic tools, and multiprocessor array components. The direct mapping of single, 32-bit assembly instructions to execute Fastbus protocols makes the use of a GPM both simple and flexible. Loosely coupled processing in Fastbus networks is possible between GPM's as they support access semaphores and use a two port memory as I/O buffer for Fastbus. Both master and slave-ports support block transfers up to 20 Mbytes/s. The CERN standard Fastbus software and the MoniCa symbolic debugging monitor are available on the GPM with real time, multiprocessing support. (Auth.)

  12. Invasive tightly coupled processor arrays

    CERN Document Server

    LARI, VAHID

    2016-01-01

    This book introduces new massively parallel computer (MPSoC) architectures called invasive tightly coupled processor arrays. It proposes strategies, architecture designs, and programming interfaces for invasive TCPAs that allow invading and subsequently executing loop programs with strict requirements or guarantees of non-functional execution qualities such as performance, power consumption, and reliability. For the first time, such a configurable processor array architecture consisting of locally interconnected VLIW processing elements can be claimed by programs, either in full or in part, using the principle of invasive computing. Invasive TCPAs provide unprecedented energy efficiency for the parallel execution of nested loop programs by avoiding any global memory access such as GPUs and may even support loops with complex dependencies such as loop-carried dependencies that are not amenable to parallel execution on GPUs. For this purpose, the book proposes different invasion strategies for claiming a desire...

  13. Pixel DAQ and trigger for HL-LHC

    International Nuclear Information System (INIS)

    Morettini, P.

    2017-01-01

    The read-out is one of the challenges in the design of a pixel detector for the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), that is expected to operate from 2026 at a leveled luminosity of 5 × 10 34  cm −2  s −1 . This is especially true if tracking information is needed in a low latency trigger system. The difficulties of a fast read-out will be reviewed, and possible strategies explained. The solutions that are being evaluated by the ATLAS and CMS collaborations for the upgrade of their trackers will be outlined and ideas on possible development beyond HL-LHC will be presented.

  14. The ATLAS high level trigger region of interest builder

    International Nuclear Information System (INIS)

    Blair, R.; Dawson, J.; Drake, G.; Haberichter, W.; Schlereth, J.; Zhang, J.; Ermoline, Y.; Pope, B.; Aboline, M.; High Energy Physics; Michigan State Univ.

    2008-01-01

    This article describes the design, testing and production of the ATLAS Region of Interest Builder (RoIB). This device acts as an interface between the Level 1 trigger and the high level trigger (HLT) farm for the ATLAS LHC detector. It distributes all of the Level 1 data for a subset of events to a small number of (16 or less) individual commodity processors. These processors in turn provide this information to the HLT. This allows the HLT to use the Level 1 information to narrow data requests to areas of the detector where Level 1 has identified interesting objects

  15. Speculative segmented sum for sparse matrix-vector multiplication on heterogeneous processors

    DEFF Research Database (Denmark)

    Liu, Weifeng; Vinter, Brian

    2015-01-01

    of the same chip is triggered to re-arrange the predicted partial sums for a correct resulting vector. On three heterogeneous processors from Intel, AMD and nVidia, using 20 sparse matrices as a benchmark suite, the experimental results show that our method obtains significant performance improvement over...

  16. Use of Digital Signal Processors (DSP) in high energy physics experiments

    International Nuclear Information System (INIS)

    Crosetto, D.

    1988-01-01

    The FDDP - Fast Digital Data Processor - is a modular system for executing parallel digital processing algorithms to perform programmable trigger decisions or programmable on-line data reduction. Typical application involve zero suppression and pulse shape analysis. The characteristics of the system are: modularity, expandability and flexibility. (author). 4 refs, 5 figs

  17. The CMS High-Level Trigger

    International Nuclear Information System (INIS)

    Covarelli, R.

    2009-01-01

    At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the 'High-Level Trigger'(HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, τ leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

  18. The CMS High-Level Trigger

    CERN Document Server

    Covarelli, Roberto

    2009-01-01

    At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the "High-Level Trigger" (HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, tau leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

  19. The CMS High-Level Trigger

    Science.gov (United States)

    Covarelli, R.

    2009-12-01

    At the startup of the LHC, the CMS data acquisition is expected to be able to sustain an event readout rate of up to 100 kHz from the Level-1 trigger. These events will be read into a large processor farm which will run the "High-Level Trigger" (HLT) selection algorithms and will output a rate of about 150 Hz for permanent data storage. In this report HLT performances are shown for selections based on muons, electrons, photons, jets, missing transverse energy, τ leptons and b quarks: expected efficiencies, background rates and CPU time consumption are reported as well as relaxation criteria foreseen for a LHC startup instantaneous luminosity.

  20. The D-Zero Run II Trigger

    International Nuclear Information System (INIS)

    Blazey, G. C.

    1997-01-01

    The general purpose D0 collider detector, located at Fermi National Accelerator Laboratory, requires significantly enhanced data acquisition and triggering to operate in the high luminosity (L = 2 x 10 32 cm -2 s -1 ), high rate environment (7 MHz or 132 ns beam crossings) of the upgraded TeVatron proton anti-proton accelerator. This article describes the three major levels and frameworks of the new trigger. Information from the first trigger stage (L1) which includes scintillating, tracking and calorimeter detectors will provide a deadtimeless, 4.2 (micro)s trigger decision with an accept rate of 10 kHz. The second stage (L2), comprised of hardware engines associated with specific detectors and a single global processor will test for correlations between L1 triggers. L2 will have an accept rate of 1 kHz at a maximum deadtime of 5% and require a 100 (micro)s decision time. The third and final stage (L3) will reconstruct events in a farm of processors for a final instantaneous accept rate of 50 Hz

  1. The ATLAS Level-1 Topological Trigger Design and Operation in Run-2

    CERN Document Server

    Igonkina, Olga; The ATLAS collaboration

    2018-01-01

    The ATLAS Level-1 Trigger system performs initial event selection using data from calorimeters and the muon spectrometer to reduce the LHC collision event rate down to about 100 kHz. Trigger decisions from the different sub-systems are combined in the Central Trigger Processor for the final Level-1 decision. A new FPGAs-based AdvancedTCA sub-system was introduced to calculate in real time complex kinematic observables: the Topological Processor System. It was installed during the shutdown and commissioning started in 2015 and continued during 2016. The design and operation of the Level-1 Topological Trigger in Run-2 will be illustrated.

  2. ATLAS Trigger and Data Acquisition Upgrades for High Luminosity LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00439268; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment at CERN is planning a second phase of upgrades to prepare for the "High Luminosity LHC", a 4th major run due to start in 2026. In order to deliver an order of magnitude more data than previous runs, 14 TeV protons will collide with an instantaneous luminosity of 7.5 × 1034 cm−2s−1, resulting in much higher pileup and data rates than the current experiment was designed to handle. While this extreme scenario is essential to realise the physics programme, it is a huge challenge for the detector, trigger, data acquisition and computing. The detector upgrades themselves also present new requirements and opportunities for the trigger and data acquisition system. Initial upgrade designs for the trigger and data acquisition system are shown, including the real time low latency hardware trigger, hardware-based tracking, the high throughput data acquisition system and the commodity hardware and software-based data handling and event filtering. The motivation, overall architecture and expected ...

  3. ATLAS Trigger and Data Acquisition Upgrades for High Luminosity LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00421104; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment at CERN is planning a second phase of upgrades to prepare for the "High Luminosity LHC", a 4th major run due to start in 2026. In order to deliver an order of magnitude more data than previous runs, 14 TeV protons will collide with an instantaneous luminosity of $7.5 \\times 10^{34} cm^{-2}s^{-1}$, resulting in much higher pileup and data rates than the current experiment was designed to handle. While this extreme scenario is essential to realise the physics programme, it is a huge challenge for the detector, trigger, data acquisition and computing. The detector upgrades themselves also present new requirements and opportunities for the trigger and data acquisition system. Initial upgrade designs for the trigger and data acquisition system are shown, including the real time low latency hardware trigger, hardware-based tracking, the high throughput data acquisition system and the commodity hardware and software-based data handling and event filtering. The motivation, overall architecture an...

  4. ATLAS Trigger and Data Acquisition Upgrades for High Luminosity LHC

    CERN Document Server

    George, Simon; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment at CERN is planning a second phase of upgrades to prepare for the "High Luminosity LHC", a 4th major run due to start in 2026. In order to deliver an order of magnitude more data than previous runs, 14 TeV protons will collide with an instantaneous luminosity of 7.5 × 10^{34} cm^{−2}s^{−1}, resulting in much higher pileup and data rates than the current experiment was designed to handle. While this extreme scenario is essential to realise the physics programme, it is a huge challenge for the detector, trigger, data acquisition and computing. The detector upgrades themselves also present new requirements and opportunities for the trigger and data acquisition system. Initial upgrade designs for the trigger and data acquisition system are shown, including the real time low latency hardware trigger, hardware-based tracking, the high throughput data acquisition system and the commodity hardware and software-based data handling and event filtering. The motivation, overall architecture and ...

  5. ATLAS Trigger and Data Acquisition Upgrades for High Luminosity LHC

    CERN Document Server

    Balunas, William Keaton; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment at CERN is planning a second phase of upgrades to prepare for the "High Luminosity LHC", a 4th major run due to start in 2026. In order to deliver an order of magnitude more data than previous runs, 14 TeV protons will collide with an instantaneous luminosity of $7.5 × 10^{34}$ cm$^{−2}$s$^{−1}$, resulting in much higher pileup and data rates than the current experiment was designed to handle. While this extreme scenario is essential to realise the physics programme, it is a huge challenge for the detector, trigger, data acquisition and computing. The detector upgrades themselves also present new requirements and opportunities for the trigger and data acquisition system. Initial upgrade designs for the trigger and data acquisition system are shown, including the real time low latency hardware trigger, hardware-based tracking, the high throughput data acquisition system and the commodity hardware and software-based data handling and event filtering. The motivation, overall architectur...

  6. The Hardware Topological Trigger of ATLAS: Commissioning and Operations

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226165; The ATLAS collaboration

    2018-01-01

    The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system with an output rate of 100 kHz and decision latency smaller than 2.5 μs. It consists of a calorimeter trigger, muon trigger and a central trigger processor. To improve the physics potential reach in ATLAS, during the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software level. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Topological Processor System (L1Topo). It consists of a single AdvancedCTA shelf equipped with two Level-1 topological processor blades. For individual blades, real-time information from calorimeter and muon Level-1 trigger systems, is processed by four individual state-of-the-art FPGAs. It needs to deal with a large input bandwidth of up to 6 Tb/s, optical connectivity and low processing latency on the real-time data path. The L1Topo firmware apply measurements of angles between jets and/or leptons and several...

  7. Vertex trigger implementation using shared memory technology

    CERN Document Server

    Müller, H

    1998-01-01

    The implementation of a 1 st level vertex trigger for LHC-B is particularly difficult due to the high ( 1 MHz ) input data rate. With ca. 350 silicon hits per event, both the R strips and Phi strips of the detectors produce a total of ca 2 Gbyte/s zero-suppressed da ta.1 note succeeds to the ideas to use R-phi coordinates for fast integer linefinding in programmable hardware, as described in LHB note 97-006. For an implementation we propose a FPGA preprocessing stage operating at 1 MHz with the benefit to substantially reduce the amount of data to be transmitted to the CPUs and to liberate a large fraction of CPU time. Interconnected via 4 Gbit/s SCI technol-ogy 2 , a shared memory system can be built which allows to perform data driven eventbuilding with, or without preprocessing. A fully data driven architecture between source modules and destination memories provides a highly reliable memory-to-memory transfer mechanism of very low latency. The eventbuilding is performed via associating events at the sourc...

  8. Some questions of using the algebraic coding theory for construction of special-purpose processors in high energy physics spectrometers

    International Nuclear Information System (INIS)

    Nikityuk, N.M.

    1989-01-01

    The results of investigations of using the algebraic coding theory for the creation of parallel encoders, majority coincidence schemes and coordinate processors for the first and second trigger levels are described. Concrete examples of calculation and structure of special-purpose processor using the table arithmetic method are given for multiplicity t ≤ 5. The question of using parallel and sequential syndrome coding methods for the registration of events with clusters is discussed. 30 refs.; 10 figs

  9. The multilevel trigger system of the DIRAC experiment

    International Nuclear Information System (INIS)

    Afanas'ev, L.; Gallas, M.; Goldin, D.

    2002-01-01

    The multilevel trigger system of the DIRAC experiment at CERN is presented. It includes a fast first level trigger as well as various trigger processors to select events with a pair of pions having a low relative momentum typical of the physical process under study. One of these processors employs the drift chamber data, another one is based on a neural network algorithm and the others use various hit-map detector correlations. Two versions of the trigger system used at different stages of the experiment are described. The complete system reduces the event rate by a factor of 1000, with efficiency ≥ 95 % of detecting the events in the relative momentum range of interest

  10. Optical computing - an alternate approach to trigger processing

    International Nuclear Information System (INIS)

    Cleland, W.E.

    1981-01-01

    The enormous rate reduction factors required by most ISABELLE experiments suggest that we should examine every conceivable approach to trigger processing. One approach that has not received much attention by high energy physicists is optical data processing. The past few years have seen rapid advances in optoelectronic technology, stimulated mainly by the military and the communications industry. An intriguing question is whether one can utilize this technology together with the optical computing techniques that have been developed over the past two decades to develop a rapid trigger processor for high energy physics experiments. Optical data processing is a method for performing a few very specialized operations on data which is inherently two dimensional. Typical operations are the formation of convolution or correlation integrals between the input data and information stored in the processor in the form of an optical filter. Optical processors are classed as coherent or incoherent, according to the spatial coherence of the input wavefront. Typically, in a coherent processor a laser beam is modulated with a photographic transparency which represents the input data. In an incoherent processor, the input may be an incoherently illuminated transparency, but self-luminous objects, such as an oscilloscope trace, have also been used. We consider here an incoherent processor in which the input data is converted into an optical wavefront through the excitation of an array of point sources - either light emitting diodes or injection lasers

  11. Commissioning the ATLAS Level-1 Central Trigger System

    CERN Document Server

    Sherman, Daniel

    2010-01-01

    The ATLAS Level-1 central trigger is a critical part of ATLAS operation. It receives the 40 MHz bunch clock from the LHC and distributes it to all sub-detectors. It initiates their read-out by forming the Level-1 Accept decision, which is based on information from the calorimeter and muon trigger processors and a variety of additional trigger inputs from detectors in the forward region. It also provides trigger summary information to the data acquisition system and the Level-2 trigger system. In this paper, we present the completion of the installed central trigger system, its performance during cosmic-ray data taking and the experience gained with triggering on the first LHC beams.

  12. Real-time machine vision system using FPGA and soft-core processor

    Science.gov (United States)

    Malik, Abdul Waheed; Thörnberg, Benny; Meng, Xiaozhou; Imran, Muhammad

    2012-06-01

    This paper presents a machine vision system for real-time computation of distance and angle of a camera from reference points in the environment. Image pre-processing, component labeling and feature extraction modules were modeled at Register Transfer (RT) level and synthesized for implementation on field programmable gate arrays (FPGA). The extracted image component features were sent from the hardware modules to a soft-core processor, MicroBlaze, for computation of distance and angle. A CMOS imaging sensor operating at a clock frequency of 27MHz was used in our experiments to produce a video stream at the rate of 75 frames per second. Image component labeling and feature extraction modules were running in parallel having a total latency of 13ms. The MicroBlaze was interfaced with the component labeling and feature extraction modules through Fast Simplex Link (FSL). The latency for computing distance and angle of camera from the reference points was measured to be 2ms on the MicroBlaze, running at 100 MHz clock frequency. In this paper, we present the performance analysis, device utilization and power consumption for the designed system. The FPGA based machine vision system that we propose has high frame speed, low latency and a power consumption that is much lower compared to commercially available smart camera solutions.

  13. Trigger circuit

    International Nuclear Information System (INIS)

    Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.

    1984-01-01

    A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)

  14. Accuracies Of Optical Processors For Adaptive Optics

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1992-01-01

    Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

  15. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  16. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  17. Data register and processor for multiwire chambers

    International Nuclear Information System (INIS)

    Karpukhin, V.V.

    1985-01-01

    A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

  18. Many - body simulations using an array processor

    International Nuclear Information System (INIS)

    Rapaport, D.C.

    1985-01-01

    Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

  19. Sensitometric control of roentgen film processors

    International Nuclear Information System (INIS)

    Forsberg, H.; Karolinska Sjukhuset, Stockholm

    1987-01-01

    Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

  20. Physics performances with the new ATLAS Level-1 Topological trigger in Run 2

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00414333; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aims at reducing the 40 MHz proton-proton collision event rate to a manageable event storage rate of 1 kHz, preserving events valuable for physics analysis. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: The Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. More than one hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. This information will be essential to improve background reject...

  1. ATLAS calorimeter and topological trigger upgrades for Phase 1

    CERN Document Server

    Silverstein, S

    2011-01-01

    The ATLAS Level-1 Calorimeter Trigger (L1Calo) collaboration is pursuing two hardware upgrade programs for Phase 1 of the LHC upgrade. The first of these is development of a new mixed-signal multi-chip module (MCM) for the PreProcessor system. based on faster FADCs and a modern FPGA. Designed as a drop-in replacement for the existing MCM, the FPGA also enables future upgrades to the PreProcessor algorithms, including enhanced digital filtering and compensation for time-variation of pedestals. It is also planned to augment the current multiplicity-based trigger by adding topology-based algorithms. This is made possible by adding jet and EM/hadron Regions of Interest (ROIs) to the L1Calo real time data path. A synchronous, pipelined topological processor (TP) based on high-density FPGAs and multi-Gbit optical links gathers all ROI information and performs topological algorithms.

  2. Upgrade of the CMS Global Muon Trigger

    CERN Document Server

    Lingemann, Joschka; Sakulin, Hannes; Jeitler, Manfred; Stahl, Achim

    2015-01-01

    The increase in center-of-mass energy and luminosity for Run 2 of the Large Hadron Collider pose new challenges for the trigger systems of the experiments. To keep triggering with a similar performance as in Run 1, the CMS muon trigger is currently being upgraded. The new algorithms will provide higher resolution, especially for the muon transverse momentum and will make use of isolation criteria that combine calorimeter with muon information already in the level-1 trigger. The demands of the new algorithms can only be met by upgrading the level-1 trigger system to new powerful FPGAs with high bandwidth I/O. The processing boards will be based on the new microTCA standard. We report on the planned algorithms for the upgraded Global Muon Trigger (GMT) which combines information from the muon trigger sub-systems and assigns the isolation variable. The upgraded GMT will be implemented using a Master Processor 7 card, built by Imperial College, that features a large Xilinx Virtex 7 FPGA. Up to 72 optical links at...

  3. Design and Test Space Exploration of Transport-Triggered Architectures

    NARCIS (Netherlands)

    Zivkovic, V.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.

    2000-01-01

    This paper describes a new approach in the high level design and test of transport-triggered architectures (TTA), a special type of application specific instruction processors (ASIP). The proposed method introduces the test as an additional constraint, besides throughput and circuit area. The

  4. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    Kaerhae, K.; Jouhiaho, A.

    2009-01-01

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  5. Trigger region unit for the ALICE PHOS calorimeter

    CERN Document Server

    Müller, Hans; Li Qing Xia; Pimenta, Rui; Röhrich, Dieter; Skaali, Bernhard; Oltean, Alexandra

    2005-01-01

    The Photon Spectrometer (PHOS) of ALICE measures electromagnetic showers of up to 100 GeV via a large matrix of PWO crystals, each read out by an APD. Trigger regions consist of 28*16 crystals, inter-connected via analogue signals generated on front-end cards and transmitted to Trigger Region Units (TRU) which digitize and process the analogue hit information. Eight TRU cards are embedded inside each PHOS module in water-cooled cassettes, each inserted between a block 14 FEE readout cards. Analogue sums are generated by fast summing shapers, with their outputs connected to the TRU via equal-length differential cables. The TRU receives analogue sums on 112 inputs and digitizes these via 12 bit ADCs which are inter-connected with a central FPGA via serial LVDS links. The level-0 and level-1 trigger algorithms are based on pipelined charge summing over 4 consecutive samples and over 4*4 crystal windows. Low latency level-0 decisions and more refined level-1 decisions are generated as a 40 MHz Yes/No sequence whi...

  6. The BTeV trigger system

    International Nuclear Information System (INIS)

    Kaplan, D.M.

    2000-01-01

    BTeV is a dedicated beauty and charm experiment proposed for the Fermilab Tevatron. The broad physics program envisaged for BTeV requires a trigger that is efficient for a wide variety of heavy-quark decays, including those to all-hadronic final states. To achieve this, we plan to trigger on evidence of detached vertices at the very first trigger level, taking advantage of fast-readout pixel detectors to facilitate fast pattern recognition. Simulations show that 100-to-1 rejection of light-quark background events can be achieved at Level 1 using specialized trackfinding hardware, and that an additional factor of 10-100 in data reduction can be achieved using general purpose processor farms at Levels 2 and 3. This is adequate to allow data taking at luminosities in excess of 2x10 32 cm -2 s -1

  7. Micro processors for plant protection

    International Nuclear Information System (INIS)

    McAffer, N.T.C.

    1976-01-01

    Micro computers can be used satisfactorily in general protection duties with economic advantages over hardwired systems. The reliability of such protection functions can be enhanced by keeping the task performed by each protection micro processor simple and by avoiding such a task being dependent on others in any substantial way. This implies that vital work done for any task is kept within it and that any communications from it to outside or to it from outside are restricted to those for controlling data transfer. Also that the amount of this data should be the minimum consistent with satisfactory task execution. Technology is changing rapidly and devices may become obsolete and be supplanted by new ones before their theoretical reliability can be confirmed or otherwise by field service. This emphasises the need for users to pool device performance data so that effective reliability judgements can be made within the lifetime of the devices. (orig.) [de

  8. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  9. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

  10. The communication processor of TUMULT-64

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Jansen, P.G.

    1988-01-01

    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

  11. An interactive parallel processor for data analysis

    International Nuclear Information System (INIS)

    Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

    1984-01-01

    A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

  12. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  13. The ZEUS second level calorimeter trigger

    International Nuclear Information System (INIS)

    Jong, S.J. de.

    1990-01-01

    ZEUS is a detector for the HERA ep collider, consisting of several large components. The most important being the inner tracking detectors, which are positioned nearest to the interaction point, the calorimeter surrounding the inner tracking detectors and the muon detectors on the outside of the experimental setup. Each component will deliver a vast amount of information. In order to keep this information manageable, data is preprocessed and condensed per component and then combined to obtain the final global trigger result. The main subject of this thesis is the second level calorimeter trigger processor of the ZEUS detector. In order to be able to reject the unwanted events passing the first level, the topological event signature will have to be used at the second level. The most demanding task of the second level is the recognition of local energy depositions corresponding to isolated electrons and hadron jets. Also part of the work performed by the first level will be repeated with a higher level of accuracy. Additional information not available to the first level trigger will be processed and will be made available to the global second level trigger decision module. For the second level calorimeter trigger processor a special VME module, containing two transputers, has been developed. The second level calorimeter trigger algorithm described in this thesis was tested with simulated events, that were tracked through a computer simulation of the ZEUS detector. A part of this thesis is therefore devoted to the description of the various Monte Carlo models and the justification of the way in which they were used. (author). 132 refs.; 76 figs.; 18 tabs

  14. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  15. Development of a highly reliable CRT processor

    International Nuclear Information System (INIS)

    Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

    1996-01-01

    Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

  16. Computer Generated Inputs for NMIS Processor Verification

    International Nuclear Information System (INIS)

    J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

    2001-01-01

    Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

  17. Simulation of the ATLAS New Small Wheel trigger

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00399900; The ATLAS collaboration

    2018-01-01

    The instantaneous luminosity of the LHC will increase up to a factor of seven with respect to the original design value to explore physics at higher energy scale. The inner station of the ATLAS muon end-cap system (Small Wheel) will be replaced by the New Small Wheel (NSW) to benefit from the high luminosity. The NSW will provide precise track-segment information to the Level-1 trigger system in order to suppress the trigger rate from fake muon tracks. This article summarizes the NSW trigger decision system and track-segment finding algorithm implemented in the trigger processor, and discusses results of performance studies on the trigger system. The results demonstrate that the NSW trigger system is capable of working with good performance satisfying the requirements.

  18. Simulation and Validation of the ATLAS Level-1 Topological Trigger

    CERN Document Server

    Bakker, Pepijn Johannes; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment has recently commissioned a new component of its first-level trigger: the L1 topological trigger. This system, using state-of-the-art FPGA processors, makes it possible to reject events by applying topological requirements, such as kinematic criteria involving clusters, jets, muons, and total transverse energy. The data recorded using the L1Topological trigger demonstrates that this innovative trigger strategy allows for an improved rejection rate without efficiency loss. This improvement has been shown for several relevant physics processes leading to low-$p_T$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, an accurate simulation of the L1Topological trigger is used to validate and optimize the performance of this trigger. To reach such an accuracy, this simulation must take into account the fact that the firmware algorithms are executed on a FPGA architecture, while the simulation is executed on a floating point architecture.

  19. Analytical Bounds on the Threads in IXP1200 Network Processor

    OpenAIRE

    Ramakrishna, STGS; Jamadagni, HS

    2003-01-01

    Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

  20. Effect of processor temperature on film dosimetry

    International Nuclear Information System (INIS)

    Srivastava, Shiv P.; Das, Indra J.

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

  1. Optical Associative Processors For Visual Perception"

    Science.gov (United States)

    Casasent, David; Telfer, Brian

    1988-05-01

    We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

  2. Using the automata processor for fast pattern recognition in high energy physics experiments—A proof of concept

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Michael H.L.S., E-mail: mwang@fnal.gov [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States); Cancelo, Gustavo; Green, Christopher [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States); Guo, Deyuan; Wang, Ke [University of Virginia, Charlottesville, VA 22904 (United States); Zmuda, Ted [Fermi National Accelerator Laboratory, Batavia, IL 60510 (United States)

    2016-10-01

    We explore the Micron Automata Processor (AP) as a suitable commodity technology that can address the growing computational needs of pattern recognition in High Energy Physics (HEP) experiments. A toy detector model is developed for which an electron track confirmation trigger based on the Micron AP serves as a test case. Although primarily meant for high speed text-based searches, we demonstrate a proof of concept for the use of the Micron AP in a HEP trigger application.

  3. An R&D programme on alternative technologies for the ATLAS level-1 calorimeter trigger

    CERN Document Server

    Appelquist, G; Bohm, C; Engström, M; Hellman, S; Holmgren, S O; Johansson, E; Yamdagni, N; Zhao, X; Sundblad, R; Ödmark, A; Bodo, P; Elderstig, H; Hentzell, H; Lindgren, S; Tober, M; Johansson, H; Svensson, C; Yuan, J R; Mohktari, M; Ellis, Nick

    1995-01-16

    This note describes a first-level calorimeter trigger processor designed to take advantage of new possibilities that arise as a consequence of modern design techniques and components such as optical interconnections, application specific integrated circuits (ASICs) and multi-chip modules (MCMs). The design is homogeneous down to the trigger cell level. This means that no boundary effects occur due to the system partitioning. The construction presented relies mainly on two different types of highly complex ASICs for processing and an MCM for opto-electrical conversion of input data. The trigger processor performs electron/photon identification, jet detection and missing ET calculations for the central first-level trigger and region of interest (RoI) selection for the second-level trigger. Exploring the possibilities given by advanced technologies leads to a first-level trigger architecture with advantages over more traditional designs, allowing, for example, higher precision calculations. Remaining degrees of ...

  4. Development of Innovative Design Processor

    International Nuclear Information System (INIS)

    Park, Y.S.; Park, C.O.

    2004-01-01

    The nuclear design analysis requires time-consuming and erroneous model-input preparation, code run, output analysis and quality assurance process. To reduce human effort and improve design quality and productivity, Innovative Design Processor (IDP) is being developed. Two basic principles of IDP are the document-oriented design and the web-based design. The document-oriented design is that, if the designer writes a design document called active document and feeds it to a special program, the final document with complete analysis, table and plots is made automatically. The active documents can be written with ordinary HTML editors or created automatically on the web, which is another framework of IDP. Using the proper mix-up of server side and client side programming under the LAMP (Linux/Apache/MySQL/PHP) environment, the design process on the web is modeled as a design wizard style so that even a novice designer makes the design document easily. This automation using the IDP is now being implemented for all the reload design of Korea Standard Nuclear Power Plant (KSNP) type PWRs. The introduction of this process will allow large reduction in all reload design efforts of KSNP and provide a platform for design and R and D tasks of KNFC. (authors)

  5. Onboard spectral imager data processor

    Science.gov (United States)

    Otten, Leonard J.; Meigs, Andrew D.; Franklin, Abraham J.; Sears, Robert D.; Robison, Mark W.; Rafert, J. Bruce; Fronterhouse, Donald C.; Grotbeck, Ronald L.

    1999-10-01

    Previous papers have described the concept behind the MightySat II.1 program, the satellite's Fourier Transform imaging spectrometer's optical design, the design for the spectral imaging payload, and its initial qualification testing. This paper discusses the on board data processing designed to reduce the amount of downloaded data by an order of magnitude and provide a demonstration of a smart spaceborne spectral imaging sensor. Two custom components, a spectral imager interface 6U VME card that moves data at over 30 MByte/sec, and four TI C-40 processors mounted to a second 6U VME and daughter card, are used to adapt the sensor to the spacecraft and provide the necessary high speed processing. A system architecture that offers both on board real time image processing and high-speed post data collection analysis of the spectral data has been developed. In addition to the on board processing of the raw data into a usable spectral data volume, one feature extraction technique has been incorporated. This algorithm operates on the basic interferometric data. The algorithm is integrated within the data compression process to search for uploadable feature descriptions.

  6. A data base processor semantics specification package

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

  7. The CMS Level-1 Calorimeter Trigger for LHC Run II

    CERN Document Server

    Zabi, Alexandre; Cadamuro, Luca; Davignon, Olivier; Romanteau, Thierry; Strebler, Thomas; Cepeda, Maria Luisa; Sauvan, Jean-baptiste; Wardle, Nicholas; Aggleton, Robin Cameron; Ball, Fionn Amhairghen; Brooke, James John; Newbold, David; Paramesvaran, Sudarshan; Smith, D; Taylor, Joseph Ross; Fountas, Konstantinos; Baber, Mark David John; Bundock, Aaron; Breeze, Shane Davy; Citron, Matthew; Elwood, Adam Christopher; Hall, Geoffrey; Iles, Gregory Michiel; Laner Ogilvy, Christian; Penning, Bjorn; Rose, A; Shtipliyski, Antoni; Tapper, Alexander; Durkin, Timothy John; Harder, Kristian; Harper, Sam; Shepherd-Themistocleous, Claire; Thea, Alessandro; Williams, Thomas Stephen; Dasu, Sridhara Rao; Dodd, Laura Margaret; Klabbers, Pamela Renee; Levine, Aaron; Ojalvo, Isabel Rose; Ruggles, Tyler Henry; Smith, Nicholas Charles; Smith, Wesley; Svetek, Ales; Forbes, R; Tikalsky, Jesra Lilah; Vicente, Marcelo

    2017-01-01

    Results from the completed Phase 1 Upgrade of the Compact Muon Solenoid (CMS) Level-1 Calorimeter Trigger are presented. The upgrade was completed in two stages, with the first running in 2015 for proton and Heavy Ion collisions and the final stage for 2016 data taking. The Level-1 trigger has been fully commissioned and has been used by CMS to collect over 43 fb-1 of data since the start of the Large Hadron Collider (LHC) Run II. The new trigger has been designed to improve the performance at high luminosity and large number of simultaneous inelastic collisions per crossing (pile-up). For this purpose it uses a novel design, the Time Multiplexed Trigger (TMT), which enables the data from an event to be processed by a single trigger processor at full granularity over several bunch crossings. The TMT design is a modular design based on the uTCA standard. The trigger processors are instrumented with Xilinx Virtex-7 690 FPGAs and 10 Gbps optical links. The TMT architecture is flexible and the number of trigger p...

  8. The LHCb trigger

    International Nuclear Information System (INIS)

    Korolko, I.

    1998-01-01

    This paper describes progress in the development of the LHCb trigger system since the letter of intent. The trigger philosophy has significantly changed, resulting in an increase of trigger efficiency for signal B events. It is proposed to implement a level-1 vertex topology trigger in specialised hardware. (orig.)

  9. PERFORMANCE EVALUATION OF OR1200 PROCESSOR WITH EVOLUTIONARY PARALLEL HPRC USING GEP

    Directory of Open Access Journals (Sweden)

    R. Maheswari

    2012-04-01

    Full Text Available In this fast computing era, most of the embedded system requires more computing power to complete the complex function/ task at the lesser amount of time. One way to achieve this is by boosting up the processor performance which allows processor core to run faster. This paper presents a novel technique of increasing the performance by parallel HPRC (High Performance Reconfigurable Computing in the CPU/DSP (Digital Signal Processor unit of OR1200 (Open Reduced Instruction Set Computer (RISC 1200 using Gene Expression Programming (GEP an evolutionary programming model. OR1200 is a soft-core RISC processor of the Intellectual Property cores that can efficiently run any modern operating system. In the manufacturing process of OR1200 a parallel HPRC is placed internally in the Integer Execution Pipeline unit of the CPU/DSP core to increase the performance. The GEP Parallel HPRC is activated /deactivated by triggering the signals i HPRC_Gene_Start ii HPRC_Gene_End. A Verilog HDL(Hardware Description language functional code for Gene Expression Programming parallel HPRC is developed and synthesised using XILINX ISE in the former part of the work and a CoreMark processor core benchmark is used to test the performance of the OR1200 soft core in the later part of the work. The result of the implementation ensures the overall speed-up increased to 20.59% by GEP based parallel HPRC in the execution unit of OR1200.

  10. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  11. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  12. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2014-01-01

    Modern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present results and performances of a new prototype of Associative Memory system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the Atlas experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. The problem is solved by the time data are loaded into the AM devices. We report on the tests of the integrate...

  13. The Associative Memory system for the FTK processor at ATLAS

    CERN Document Server

    Cipriani, R; The ATLAS collaboration; Donati, S; Giannetti, P; Lanza, A; Luciano, P; Magalotti, D; Piendibene, M

    2013-01-01

    Experiments at the LHC hadron collider search for extremely rare processes hidden in much larger background levels. As the experiment complexity, the accelerator backgrounds and instantaneus luminosity increase, increasingly complex and exclusive selections are necessary. We present results and performances of a new prototype of Associative Memory (AM) system, the core of the Fast Tracker processor (FTK). FTK is a real time tracking device for the ATLAS experiment trigger upgrade. The AM system provides massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the "combinatorial challenge", is beat by the AM technology exploiting parallelism to the maximum level. The Associative Memory compares the event to pre-calculated "expectations" or "patterns" (pattern matching) at once and look for candidate tracks called "roads". The problem is solved by the time data are loaded into the AM devices. We report ...

  14. Should a reliable information processor be chaotic (brain models)

    Energy Technology Data Exchange (ETDEWEB)

    Nicolis, J S

    1982-01-01

    Brain-like structures have evolved by performing signal processing initially by minimizing tracking errors on a competitive basis. Such systems are highly complex and at the same time notoriously disordered. The functional trace of the cerebral cortex of the human brain is a good example. The electroencephalogram (EEG) appears particularly fragmented during the execution of mental tasks, as well as during the recurrent episodes of rem sleep. A stochastically regular or a highly synchronized EEG on the other hand, characterises a drowsy (relaxing) or epileptic subject respectively and indicates-in both cases-a very incompetent information processor. The author suggests that such behavioral changeovers are produced via bifurcations which trigger the thalamocortical nonlinear pacemaking oscillator to switch from an unstable limit cycle to a strange attractor regime (i.e. to chaos), or vice versa. This analysis aims to show that the EEGs characteristics are not accidental but inevitable and even necessary and, therefore, functionally significant. 25 references.

  15. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  16. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

    1995-01-01

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  17. Accuracy Limitations in Optical Linear Algebra Processors

    Science.gov (United States)

    Batsell, Stephen Gordon

    1990-01-01

    One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

  18. The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

    International Nuclear Information System (INIS)

    Becam, C.; Bernaudin, P.; Delanghe, J.; Mencik, M.; Merkel, B.; Plothow, H.; Fest, H.M.; Lecoq, J.; Martin, H.; Meyer, J.M.

    1981-01-01

    The bit slice micro-processor GESPRO, as it is proposed for use in the UA 2 data acquisition chain and trigger system, is a CAMAC module plugged into a standard Elliott System crate via which it communicates as a slave with its host computer (ND, DEC). It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine (150 ns effective cycle time) with multi-mode memory addressing capacity of 64 K words. The micro-processor structure uses 5 busses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2 K (RAM) words of 48 bits each. A special hardwired module allows floating point (as well as integer) multiplication of 24 x 24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: a) online data reduction, i.e. to read DURANDAL (fast ADC's = the hardware trigger in the experiment), process the information (effective mass calculation, etc.) resulting in accepting or rejecting the event. b) read out and analysis of the accepted data (collect statistical information). c) preprocess the data (calculation of pointers, address decoding, etc.). The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hardware and software will be tested with simulated data. First results are expected in about one year from now. (orig.)

  19. The new Global Muon Trigger of the CMS experiment

    CERN Document Server

    Fulcher, Jonathan Richard; Rabady, Dinyar Sebastian; Reis, Thomas; Sakulin, Hannes

    2016-01-01

    For the 2016 physics data runs the L1 trigger system of the Compact Muon Solenoid (CMS) experiment underwent a major upgrade to cope with the increasing instantaneous luminosity of the CERN LHC whilst maintaining a high event selection efficiency for the CMS physics program. Most subsystem specific trigger processor boards were replaced with powerful general purpose processor boards, conforming to the MicroTCA standard, whose tasks are performed by firmware on an FPGA of the Xilinx Virtex 7 family. Furthermore, the muon trigger system moved from a subsystem centered approach, where each of the three muon detector systems provides muon candidates to the Global Muon Trigger (GMT), to a region based system, where muon track finders (TFs) combine information from the subsystems to generate muon candidates in three detector regions, that are then sent to the upgraded GMT. The upgraded GMT receives up to 108 muons from the processors of the muon TFs in the barrel, overlap, and endcap detector regions. The muons are...

  20. Physics performances with the new ATLAS Level-1 Topological trigger in the LHC High-Luminosity Era

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00414333; The ATLAS collaboration

    2016-01-01

    The ATLAS trigger system aim at reducing the 40 MHz protons collision event rate to a manageable event storage rate of 1 kHz, preserving events with valuable physics meaning. The Level-1 trigger is the first rate-reducing step in the ATLAS trigger system, with an output rate of 100 kHz and decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. During the last upgrade, a new electronics element was introduced to Level-1: L1Topo, the Topological Processor System. It will make it possible to use detailed realtime information from the Level-1 calorimeter and muon triggers, processed in individual state of the art FPGA processors to determine angles between jets and/or leptons and calculate kinematic variables based on lists of selected/sorted objects. Over hundred VHDL algorithms are producing trigger outputs to be incorporated into the central trigger processor. Such information will be essential to improve background rejection and ...

  1. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

  2. The Phase-1 Upgrade for the Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC

    CERN Document Server

    Izzo, Vincenzo; The ATLAS collaboration

    2018-01-01

    The Level-1 Muon Barrel Trigger of the ATLAS Experiment at LHC makes use of Resistive Plate Chamber (RPC) detectors. The on-detector trigger electronics modules are able to identify muons with predefined transverse momentum values (pT) by executing a coincidence logic on signals coming from the various detector layers. On-detector trigger boards then transfer trigger data to the off-detector electronics. A complex trigger system processes the incoming data by combining trigger information from the barrel and the endcap regions, and providing the combined muon candidate to the Central Trigger Processor (CTP). For almost a decade, the Level-1 Trigger system operated very well, despite the challenging requirements on trigger efficiency and performance, and the continuously increasing LHC luminosity. In order to cope with these constraints, various upgrades for the full trigger system were already deployed, and others have been designed to be installed in the next years. Most of the upgrades to the trigger system...

  3. A first-level calorimeter trigger for the ATLAS experiment

    International Nuclear Information System (INIS)

    Perera, V.; Edwards, J.; Gee, N.

    1995-01-01

    In the RD27 collaboration the authors have carried out system studies on the implementation of the first level calorimeter trigger processor system for the ATLAS experiment to be mounted at the Large Hadron Collider (LHC) at CERN. A demonstrator trigger system operated successfully with the RD3 and RD33 calorimeters at the full 40 MHz LHC bunch crossing (BC) rate. The prototype application-specific integrated circuits (ASICs) in this system each processed data from only a single trigger cell and its environment, which would lead to an extremely large system for ATLAS. Using eight-bit parallel data even the use of ASICs, processing multiple trigger cells would demand unacceptably large numbers of input pins and module connections. Initial studies of this I/O problem produced a solution based on asynchronous transmission of zero-suppressed and BC-tagged data on 160 Mbit/s serial links. This approach appeared to be feasible but would have introduced additional latency of about 20 BCs. Further studies have led to the design of a fully-synchronous calorimeter trigger processor system using commercial high-speed optical links. The links will terminate in multi-chip modules (MCMs) incorporating custom-designed integrated optics, and the trigger algorithms will be implemented in ASICs

  4. Architectural design and analysis of a programmable image processor

    International Nuclear Information System (INIS)

    Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

    2003-01-01

    In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

  5. A Time-Multiplexed Track-Trigger for the CMS HL-LHC upgrade

    CERN Document Server

    Hall, Geoffrey

    2016-01-01

    A new CMS Tracker is under development for operation at the High Luminosity LHC from 2025. It includes an outer tracker based on special modules of two different types which will construct track stubs using spatially coincident clusters in two closely spaced sensor layers, to reject low transverse momentum track hits and reduce the data volume before data transmission to the Level-1 trigger. The tracker data will be used to reconstruct track segments in dedicated processors before onward transmission to other trigger processors which will combine tracker information with data originating from the calorimeter and muon detectors, to make the final L1 trigger decision. The architecture for processing the tracker data outside the detector is under study, using several alternative approaches. One attractive possibility is to exploit a Time Multiplexed design similar to the one which is currently being implemented in the CMS calorimeter trigger as part of the Phase I trigger upgrade. The novel Time Multiplexed Trig...

  6. XOP, a fast versatile processor, as a building block for parallel processing in high energy physics experiments

    International Nuclear Information System (INIS)

    Baehler, P.; Bosco, N.; Lingjaerde, T.; Ljuslin, C.; Van Praag, A.; Werner, P.

    1986-01-01

    The XOP processor has been designed for trigger calculation and data compression in high energy physics experiments. Therefore, emphasis has been placed upon fast execution and high input/output rate. The fast execution is achieved by a wide instruction word holding operations which are executed concurrently. Thus, the arithmetic operations, data address calculations, data accessing, condition checking, loop count checking and next instruction evaluation all overlap in time. In conventional micro-processors these operations are performed sequentially. In addition, the instruction set comprises not only the classical computer instructions, but also specialized instructions suitable for trigger calculations, such as bit search, population count, loose compare and vector instructions. In order to achieve a high input/output rate, each XOP ECLine interface board is equipped with an input and an output port which fulfil the LeCroy ECLine specifications. The autonomous input port allows a data rate of 40 Mbytes/sec, while the program controlled output port allows 20 Mbytes/sec. For Fastbus based systems a dual Fastbus master interface is under design which allows to build up a Fastbus multi-processor system. This design is being done in collaboration with LAPP Annecy for the CERN Lep L3 experiment. Their scheme comprises 4-5 XOP processors, each of them with a master interface on a data input segment and a master interface on a data output segment. This paper describes the structure of the XOP processor, the interface capabilities and the software development and debugging tools. (Auth.)

  7. The ATLAS Level-1 Calorimeter Trigger Architecture

    CERN Document Server

    Garvey, J; Mahout, G; Moye, T H; Staley, R J; Watkins, P M; Watson, A T; Achenbach, R; Hanke, P; Kluge, E E; Meier, K; Meshkov, P; Nix, O; Penno, K; Schmitt, K; Ay, Cc; Bauss, B; Dahlhoff, A; Jakobs, K; Mahboubi, K; Schäfer, U; Trefzger, T M; Eisenhandler, E F; Landon, M; Moyse, E; Thomas, J; Apostoglou, P; Barnett, B M; Brawn, I P; Davis, A O; Edwards, J; Gee, C N P; Gillman, A R; Perera, V J O; Qian, W; Bohm, C; Hellman, S; Hidvégi, A; Silverstein, S; RT 2003 13th IEEE-NPSS Real Time Conference

    2004-01-01

    The architecture of the ATLAS Level-1 Calorimeter Trigger system (L1Calo) is presented. Common approaches have been adopted for data distribution, result merging, readout, and slow control across the three different subsystems. A significant amount of common hardware is utilized, yielding substantial savings in cost, spares, and development effort. A custom, high-density backplane has been developed with data paths suitable for both the em/tt cluster processor (CP) and jet/energy-summation processor (JEP) subsystems. Common modules also provide interfaces to VME, CANbus and the LHC Timing, Trigger and Control system (TTC). A common data merger module (CMM) uses FPGAs with multiple configurations for summing electron/photon and tau/hadron cluster multiplicities, jet multiplicities, or total and missing transverse energy. The CMM performs both crate- and system-level merging. A common, FPGA-based readout driver (ROD) is used by all of the subsystems to send input, intermediate and output data to the data acquis...

  8. ATLAS calorimetry: Trigger, simulation and jet calibration

    CERN Document Server

    Weber, Pavel

    2008-01-01

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle phi and in pseud...

  9. ATLAS calorimetry. Trigger, simulation and jet calibration

    Energy Technology Data Exchange (ETDEWEB)

    Weber, P

    2007-02-06

    The Pre-Processor system of the ATLAS Level-1 Calorimeter Trigger performs complex processing of analog trigger tower signals from electromagnetic and hadronic calorimeters. The main processing block of the Pre-Processor System is the Multi-Chip Module (MCM). The first part of this thesis describes MCM quality assurance tests that have been developed, their use in the MCM large scale production and the results that have been obtained. In the second part of the thesis a validation of a shower parametrisation model for the ATLAS fast simulation package ATLFAST based on QCD dijet events is performed. A detailed comparison of jet response and jet energy resolution between the fast and the full simulation is presented. The uniformity of the calorimeter response has a significant impact on the accuracy of the jet energy measurement. A study of the calorimeter intercalibration using QCD dijet events is presented in the last part of the thesis. The intercalibration study is performed in azimuth angle {phi} and in pseudorapidity {eta}. The performance of the calibration methods including possible systematic and statistical effects is described. (orig.)

  10. Proceedings of the workshop on triggering and data acquisition for experiments at the Supercollider

    Energy Technology Data Exchange (ETDEWEB)

    Donaldson, R. [ed.

    1989-04-01

    This meeting covered the following subjects: triggering requirements for SSC physics; CDF level 3 trigger; D0 trigger design; AMY trigger systems; Zeus calorimeter first level trigger; data acquisition for the Zeus Central Tracking Detector; trigger and data acquisition aspects for SSC tracking; data acquisition systems for the SSC; validating triggers in CDF level 3; optical data transmission at SSC; time measurement system at SSC; SSC/BCD data acquisition system; microprocessors and other processors for triggering and filtering at the SSC; data acquisition, event building, and on-line processing; LAA real-time benchmarks; object-oriented system building at SSC; and software and project management. Selected papers are indexed separately for inclusion in the Energy Science and Technology Database.

  11. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  12. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-02-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  13. Embedded processor extensions for image processing

    Science.gov (United States)

    Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

    2008-04-01

    The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

  14. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  15. HLS4ML: deploying deep learning on FPGAs for L1 trigger and Data Acquisition

    CERN Multimedia

    CERN. Geneva

    2018-01-01

    Machine learning is becoming ubiquitous across HEP. There is great potential to improve trigger and DAQ performances with it. However, the exploration of such techniques within the field in low latency/power FPGAs has just begun. We present HLS4ML, a user-friendly software, based on High-Level Synthesis (HLS), designed to deploy network architectures on FPGAs. As a case study, we use HLS4ML for boosted-jet tagging with deep networks at the LHC. We show how neural networks can be made fit the resources available on modern FPGAs, thanks to network pruning and quantization. We map out resource usage and latency versus network architectures, to identify the typical problem complexity that HLS4ML could deal with. We discuss possible applications in current and future HEP experiments.

  16. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  17. Parallel processor for fast event analysis

    International Nuclear Information System (INIS)

    Hensley, D.C.

    1983-01-01

    Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

  18. Time Manager Software for a Flight Processor

    Science.gov (United States)

    Zoerne, Roger

    2012-01-01

    Data analysis is a process of inspecting, cleaning, transforming, and modeling data to highlight useful information and suggest conclusions. Accurate timestamps and a timeline of vehicle events are needed to analyze flight data. By moving the timekeeping to the flight processor, there is no longer a need for a redundant time source. If each flight processor is initially synchronized to GPS, they can freewheel and maintain a fairly accurate time throughout the flight with no additional GPS time messages received. How ever, additional GPS time messages will ensure an even greater accuracy. When a timestamp is required, a gettime function is called that immediately reads the time-base register.

  19. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  20. Simulation of a parallel processor on a serial processor: The neutron diffusion equation

    International Nuclear Information System (INIS)

    Honeck, H.C.

    1981-01-01

    Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

  1. Special purpose processors for high energy physics applications

    International Nuclear Information System (INIS)

    Verkerk, C.

    1978-01-01

    The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

  2. The Level 0 Pixel Trigger system for the ALICE experiment

    International Nuclear Information System (INIS)

    Rinella, G Aglieri; Kluge, A; Krivda, M

    2007-01-01

    The ALICE Silicon Pixel Detector contains 1200 readout chips. Fast-OR signals indicate the presence of at least one hit in the 8192 pixel matrix of each chip. The 1200 bits are transmitted every 100 ns on 120 data readout optical links using the G-Link protocol. The Pixel Trigger System extracts and processes them to deliver an input signal to the Level 0 trigger processor targeting a latency of 800 ns. The system is compact, modular and based on FPGA devices. The architecture allows the user to define and implement various trigger algorithms. The system uses advanced 12-channel parallel optical fiber modules operating at 1310 nm as optical receivers and 12 deserializer chips closely packed in small area receiver boards. Alternative solutions with multi-channel G-Link deserializers implemented directly in programmable hardware devices were investigated. The design of the system and the progress of the ALICE Pixel Trigger project are described in this paper

  3. XOP: A second generation fast processor for on-line use in high energy physics experiments

    International Nuclear Information System (INIS)

    Lingjaerde, T.

    1981-01-01

    Processors for trigger calculations and data compression in high energy physics are characterized by a high data input capability combined with fas execution of relatively simple routines. In order to achieve the required performance it is advantageous to replace the classical computer instruction-set by microcoded instructions, the various fields of which control the internal subunits in parallel. The fast processor called ESOP is based on such a principle: the different operations are handled step by step by dedicated optimized modules under control of a central instruction unit. Thus, the arithmetic operations, address calculations, conditional checking, loop counts and next instruction evaluation all overlap in time. Based upon the experience from ESOP the architecture of a new processor 'XOP' is beginning to take shape which will be faster and easier to use. In this context the most important innovations are: easy handling of operands in the arithmetic unit by means of three data buses and large data files, a powerful data addressing unit for easy handling of vectors, as well as single operands, and a very flexible logic for conditional branching. Input/output will be made transparent through the introduction of internal fast processors which will be used in conjunction with powerful firmware as a software debugging aid. (orig.)

  4. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2016-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  5. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  6. Development of a processor embedded timing unit for the synchronized operation in KSTAR

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Woongryol, E-mail: wrlee@nfri.re.kr; Lee, Taegu; Hong, Jaesic

    2016-11-15

    Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

  7. Development of a processor embedded timing unit for the synchronized operation in KSTAR

    International Nuclear Information System (INIS)

    Lee, Woongryol; Lee, Taegu; Hong, Jaesic

    2016-01-01

    Highlights: • Timing board for the synchronized tokamak operation. • Processor embedded distributed control system. • Single clock source and multiple trigger signal for the plasma diagnostics. • Delay compensation among the distributed timing boards. - Abstract: The Local Timing Unit (LTU) in KSTAR provides a single clock source and multiple trigger signals with flexible configuration. Over the past seven years, the LTU had a mechanical redesign and several firmware updates for the purpose of provision of a robust operation and precision timing signal. Now we have developed a third version of a local timing unit which has a standalone operation capability. The LTU is built in a cabinet mountable 1U PIZZA box and provides twelve signal output ports, a packet mirroring interface, and an LCD interface panel. The core functions of the LTU are implemented in a Field Programmable Gate Array (FPGA) which has an internal hardcore processor. The internal processor allows the use of Linux Operating System (OS) and the Experimental Physics and Industrial Control System (EPICS). All user level application functions are controllable through the EPICS, however the time critical internal functions are performed by the FPGA logic blocks same as the previous version. The new LTU provides pluggable output module so that we can easily extend the signal output port. The easy installation and effective replacement reduce the efforts of maintenance. This paper describes design, development, and commissioning results of the new KSTAR LTU.

  8. The ATLAS online High Level Trigger framework: Experience reusing offline software components in the ATLAS trigger

    International Nuclear Information System (INIS)

    Wiedenmann, Werner

    2010-01-01

    Event selection in the ATLAS High Level Trigger is accomplished to a large extent by reusing software components and event selection algorithms developed and tested in an offline environment. Many of these offline software modules are not specifically designed to run in a heavily multi-threaded online data flow environment. The ATLAS High Level Trigger (HLT) framework based on the GAUDI and ATLAS ATHENA frameworks, forms the interface layer, which allows the execution of the HLT selection and monitoring code within the online run control and data flow software. While such an approach provides a unified environment for trigger event selection across all of ATLAS, it also poses strict requirements on the reused software components in terms of performance, memory usage and stability. Experience of running the HLT selection software in the different environments and especially on large multi-node trigger farms has been gained in several commissioning periods using preloaded Monte Carlo events, in data taking periods with cosmic events and in a short period with proton beams from LHC. The contribution discusses the architectural aspects of the HLT framework, its performance and its software environment within the ATLAS computing, trigger and data flow projects. Emphasis is also put on the architectural implications for the software by the use of multi-core processors in the computing farms and the experiences gained with multi-threading and multi-process technologies.

  9. BAT Triggering Performance

    Science.gov (United States)

    McLean, Kassandra M.; Fenimore, E. E.; Palmer, D. M.; BAT Team

    2006-09-01

    The Burst Alert Telescope (BAT) onboard Swift has detected and located about 160 gamma-ray bursts (GRBs) in its first twenty months of operation. BAT employs two triggering systems to find GRBs: image triggering, which looks for a new point source in the field of view, and rate triggering, which looks for a significant increase in the observed counts. The image triggering system looks at 1 minute, 5 minute, and full pointing accumulations of counts in the detector plane in the energy range of 15-50 keV, with about 50 evaluations per pointing (about 40 minutes). The rate triggering system looks through 13 different time scales (from 4ms to 32s), 4 overlapping energy bins (covering 15-350 keV), 9 regions of the detector plane (from the full plane to individual quarters), and two background sampling models to search for GRBs. It evaluates 27000 trigger criteria in a second, for close to 1000 criteria. The image triggering system looks at 1, 5, and 40 minute accumulations of counts in the detector plane in the energy range of 15-50 keV. Both triggering systems are working very well with the settings from before launch and after we turned on BAT. However, we now have more than a year and a half of data to evaluate these triggering systems and tweak them for optimal performance, as well as lessons learned from these triggering systems.

  10. The new Level-1 Topological Trigger for the ATLAS experiment at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00047907; The ATLAS collaboration

    2017-01-01

    At the CERN Large Hadron Collider, the world’s most powerful particle accelerator, the ATLAS experiment records high-energy proton collision to investigate the properties of fundamental particles. These collisions take place at a 40 MHz, and the ATLAS trigger system selects the interesting ones, reducing the rate to 1 kHz, allowing for their storage and subsequent offline analysis. The ATLAS trigger system is organized in two levels, with increasing degree of details and of accuracy. The first level trigger reduces the event rate to 100 kHz with a decision latency of less than 2.5 micro seconds. It is composed of the calorimeter trigger, muon trigger and central trigger processor. A new component of the first-level trigger was introduced in 2015: the Topological Processor (L1Topo). It allows to use detailed real-time information from the Level-1 calorimeter and muon systems, to compute advanced kinematic quantities using state of the art FPGA processors, and to select interesting events based on several com...

  11. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  12. Cassava processors' awareness of occupational and environmental ...

    African Journals Online (AJOL)

    A larger percentage (74.5%) of the respondents indicated that the Agricultural Development Programme (ADP) is their source of information. The result also showed that processor's awareness of occupational hazards associated with the different stages of cassava processing vary because their involvement in these stages

  13. A high-speed analog neural processor

    NARCIS (Netherlands)

    Masa, P.; Masa, Peter; Hoen, Klaas; Hoen, Klaas; Wallinga, Hans

    1994-01-01

    Targeted at high-energy physics research applications, our special-purpose analog neural processor can classify up to 70 dimensional vectors within 50 nanoseconds. The decision-making process of the implemented feedforward neural network enables this type of computation to tolerate weight

  14. Beeldverwerking met de Micron Automatic Processor

    OpenAIRE

    Goyens, Frank

    2017-01-01

    Deze thesis is een onderzoek naar toepassingen binnen beeldverwerking op de Micron Automata Processor hardware. De hardware wordt vergeleken met populaire hedendaagse hardware. Ook bevat dit onderzoek nuttige informatie en strategieën voor het ontwikkelen van nieuwe toepassingen. Bevindingen in dit onderzoek omvatten proof of concept algoritmes en een praktische toepassing.

  15. 7 CFR 1215.14 - Processor.

    Science.gov (United States)

    2010-01-01

    ... 7 Agriculture 10 2010-01-01 2010-01-01 false Processor. 1215.14 Section 1215.14 Agriculture Regulations of the Department of Agriculture (Continued) AGRICULTURAL MARKETING SERVICE (MARKETING AGREEMENTS... CONSUMER INFORMATION Popcorn Promotion, Research, and Consumer Information Order Definitions § 1215.14...

  16. Simplifying cochlear implant speech processor fitting

    NARCIS (Netherlands)

    Willeboer, C.

    2008-01-01

    Conventional fittings of the speech processor of a cochlear implant (CI) rely to a large extent on the implant recipient's subjective responses. For each of the 22 intracochlear electrodes the recipient has to indicate the threshold level (T-level) and comfortable loudness level (C-level) while

  17. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    This book presents the papers given at a conference which reviewed the new developments in parallel and vector processing. Topics considered at the conference included hardware (array processors, supercomputers), programming languages, software aids, numerical methods (e.g., Monte Carlo algorithms, iterative methods, finite elements, optimization), and applications (e.g., neutron transport theory, meteorology, image processing)

  18. Space Station Water Processor Process Pump

    Science.gov (United States)

    Parker, David

    1995-01-01

    This report presents the results of the development program conducted under contract NAS8-38250-12 related to the International Space Station (ISS) Water Processor (WP) Process Pump. The results of the Process Pumps evaluation conducted on this program indicates that further development is required in order to achieve the performance and life requirements for the ISSWP.

  19. Interleaved Subtask Scheduling on Multi Processor SOC

    NARCIS (Netherlands)

    Zhe, M.

    2006-01-01

    The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

  20. User manual Dieka PreProcessor

    NARCIS (Netherlands)

    Valkering, Kasper

    2000-01-01

    This is the user manual belonging to the Dieka-PreProcessor. This application was written by Wenhua Cao and revised and expanded by Kasper Valkering. The aim of this preproccesor is to be able to draw and mesh extrusion dies in ProEngineer, and do the FE-calculation in Dieka. The preprocessor makes

  1. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  2. Event analysis using a massively parallel processor

    International Nuclear Information System (INIS)

    Bale, A.; Gerelle, E.; Messersmith, J.; Warren, R.; Hoek, J.

    1990-01-01

    This paper describes a system for performing histogramming of n-tuple data at interactive rates using a commercial SIMD processor array connected to a work-station running the well-known Physics Analysis Workstation software (PAW). Results indicate that an order of magnitude performance improvement over current RISC technology is easily achievable

  3. The second level trigger of the L3 experiment. Pt. 2

    International Nuclear Information System (INIS)

    Beingessner, S.P.; Blaising, J.J.; Chollet-Le Flour, F.; Degre, A.; Dromby, G.; Goy, C.; Lecoq, J.; Morand, R.; Moynot, M.; Perrot, G.; Rosier-Lees, S.; Forconi, G.

    1993-07-01

    The events recorded by the L3 Data Acquisition System are selected by three levels of trigger. The event filtering performed by software at the second trigger level is described. First coded offline in FORTRAN, the filtering software is microcoded for online execution in a farm of 3 XOP processors operating in a round robin mode. It identifies and rejects background events. Depending on running conditions and trigger type, rejection factors ranging from 45% to 80% are obtained on first level energy, muon and tec triggers. Selection efficiencies greater than 99.95% are achieved. (authors). 14 refs., 3 figs., 2 tabs

  4. Stay away from asthma triggers

    Science.gov (United States)

    Asthma triggers - stay away from; Asthma triggers - avoiding; Reactive airway disease - triggers; Bronchial asthma - triggers ... clothes. They should leave the coat outside or away from your child. Ask people who work at ...

  5. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  6. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

    1983-01-01

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  7. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  8. The design and performance of the ATLAS Inner Detector trigger for Run 2

    CERN Document Server

    Penc, Ondrej; The ATLAS collaboration

    2016-01-01

    The design and performance of the ATLAS Inner Detector (ID) trigger algorithms running online on the high level trigger (HLT) processor farm with the early LHC Run 2 data are discussed. The redesign of the ID trigger, which took place during the 2013-15 long shutdown, in order to satisfy the demands of the higher energy LHC Run 2 operation is described. The ID trigger HLT algorithms are essential for nearly all trigger signatures within the ATLAS trigger. The detailed performance of the tracking algorithms with the early Run 2 data for the different trigger signatures is presented, including the detailed timing performance for the algorithms running on the redesigned single stage ATLAS HLT Farm. Comparison with the Run 1 strategy are made and demonstrate the superior performance of the strategy adopted for Run 2.

  9. Trigger algorithms and electronics for the ATLAS muon new small wheel upgrade

    International Nuclear Information System (INIS)

    Guan, L.

    2016-01-01

    The New Small Wheel Upgrade for the ATLAS experiment will replace the innermost station of the Muon Spectrometer in the forward region in order to maintain its current performance during high luminosity data-taking after the LHC Phase-I upgrade. The New Small Wheel, comprising Micromegas and small Thin Gap Chambers, will reduce the rate of fake triggers coming from backgrounds in the forward region and significantly improve the Level-1 muon trigger selectivity by providing precise on-line segment measurements with ∼ 1 mrad angular resolution. Such demanding precision, together with the short time (∼ 1 μs) to prepare trigger data and perform on-line reconstruction, implies very stringent requirements on the design of trigger system and trigger electronics. This paper presents an overview of the design of the New Small Wheel trigger system, trigger algorithms and processor hardware

  10. The Level-1 Tile-Muon Trigger in the Tile Calorimeter upgrade program

    International Nuclear Information System (INIS)

    Ryzhov, A.

    2016-01-01

    The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal provides highly-segmented energy measurements for incident particles. Information from TileCal's outermost radial layer can assist in muon tagging in the Level-1 Muon Trigger by rejecting fake muon triggers due to slow charged particles (typically protons) without degrading the efficiency of the trigger. The main activity of the Tile-Muon Trigger in the ATLAS Phase-0 upgrade program was to install and to activate the TileCal signal processor module for providing trigger inputs to the Level-1 Muon Trigger. This report describes the Tile-Muon Trigger, focusing on the new detector electronics such as the Tile Muon Digitizer Board (TMDB) that receives, digitizes and then provides the signal from eight TileCal modules to three Level-1 muon endcap Sector-Logic Boards.

  11. Lipsi: Probably the Smallest Processor in the World

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

  12. Lessons from (triggered) tremor

    Science.gov (United States)

    Gomberg, Joan

    2010-01-01

    I test a “clock-advance” model that implies triggered tremor is ambient tremor that occurs at a sped-up rate as a result of loading from passing seismic waves. This proposed model predicts that triggering probability is proportional to the product of the ambient tremor rate and a function describing the efficacy of the triggering wave to initiate a tremor event. Using data mostly from Cascadia, I have compared qualitatively a suite of teleseismic waves that did and did not trigger tremor with ambient tremor rates. Many of the observations are consistent with the model if the efficacy of the triggering wave depends on wave amplitude. One triggered tremor observation clearly violates the clock-advance model. The model prediction that larger triggering waves result in larger triggered tremor signals also appears inconsistent with the measurements. I conclude that the tremor source process is a more complex system than that described by the clock-advance model predictions tested. Results of this and previous studies also demonstrate that (1) conditions suitable for tremor generation exist in many tectonic environments, but, within each, only occur at particular spots whose locations change with time; (2) any fluid flow must be restricted to less than a meter; (3) the degree to which delayed failure and secondary triggering occurs is likely insignificant; and 4) both shear and dilatational deformations may trigger tremor. Triggered and ambient tremor rates correlate more strongly with stress than stressing rate, suggesting tremor sources result from time-dependent weakening processes rather than simple Coulomb failure.

  13. Triggering trigeminal neuralgia

    DEFF Research Database (Denmark)

    Di Stefano, Giulia; Maarbjerg, Stine; Nurmikko, Turo

    2018-01-01

    Introduction Although it is widely accepted that facial pain paroxysms triggered by innocuous stimuli constitute a hallmark sign of trigeminal neuralgia, very few studies to date have systematically investigated the role of the triggers involved. In the recently published diagnostic classification...

  14. Triggering the GRANDE array

    International Nuclear Information System (INIS)

    Wilson, C.L.; Bratton, C.B.; Gurr, J.; Kropp, W.; Nelson, M.; Sobel, H.; Svoboda, R.; Yodh, G.; Burnett, T.; Chaloupka, V.; Wilkes, R.J.; Cherry, M.; Ellison, S.B.; Guzik, T.G.; Wefel, J.; Gaidos, J.; Loeffler, F.; Sembroski, G.; Goodman, J.; Haines, T.J.; Kielczewska, D.; Lane, C.; Steinberg, R.; Lieber, M.; Nagle, D.; Potter, M.; Tripp, R.

    1990-01-01

    A brief description of the Gamma Ray And Neutrino Detector Experiment (GRANDE) is presented. The detector elements and electronics are described. The trigger logic for the array is then examined. The triggers for the Gamma Ray and the Neutrino portions of the array are treated separately. (orig.)

  15. Trigger Menu in 2017

    CERN Document Server

    The ATLAS collaboration

    2018-01-01

    This document summarises the trigger menu deployed by the ATLAS experiment during 2017 data taking at proton-proton collision centre-of-mass energies of $\\sqrt{s}=13$ TeV and $\\sqrt{s}=5$ TeV at the LHC and describes the improvements with respect to the trigger system and menu used in 2016 data taking.

  16. Causality and headache triggers

    Science.gov (United States)

    Turner, Dana P.; Smitherman, Todd A.; Martin, Vincent T.; Penzien, Donald B.; Houle, Timothy T.

    2013-01-01

    Objective The objective of this study was to explore the conditions necessary to assign causal status to headache triggers. Background The term “headache trigger” is commonly used to label any stimulus that is assumed to cause headaches. However, the assumptions required for determining if a given stimulus in fact has a causal-type relationship in eliciting headaches have not been explicated. Methods A synthesis and application of Rubin’s Causal Model is applied to the context of headache causes. From this application the conditions necessary to infer that one event (trigger) causes another (headache) are outlined using basic assumptions and examples from relevant literature. Results Although many conditions must be satisfied for a causal attribution, three basic assumptions are identified for determining causality in headache triggers: 1) constancy of the sufferer; 2) constancy of the trigger effect; and 3) constancy of the trigger presentation. A valid evaluation of a potential trigger’s effect can only be undertaken once these three basic assumptions are satisfied during formal or informal studies of headache triggers. Conclusions Evaluating these assumptions is extremely difficult or infeasible in clinical practice, and satisfying them during natural experimentation is unlikely. Researchers, practitioners, and headache sufferers are encouraged to avoid natural experimentation to determine the causal effects of headache triggers. Instead, formal experimental designs or retrospective diary studies using advanced statistical modeling techniques provide the best approaches to satisfy the required assumptions and inform causal statements about headache triggers. PMID:23534872

  17. The LHCb trigger

    CERN Document Server

    Hernando Morata, Jose Angel

    2006-01-01

    The LHCb experiment relies on an efficient trigger to select a rate up to 2 kHz of events useful for physics analysis from an initial rate of 10 MHz of visible collisions. In this contribution, we describe the different LHCb trigger algorithms and present their expected performance.

  18. The NA27 trigger

    International Nuclear Information System (INIS)

    Bizzarri, R.; Di Capua, E.; Falciano, S.; Iori, M.; Marel, G.; Piredda, G.; Zanello, L.; Haupt, L.; Hellman, S.; Holmgren, S.O.; Johansson, K.E.

    1985-05-01

    We have designed and implemented a minimum bias trigger together with a fiducial volume trigger for the experiment NA27, performed at the CERN SPS. A total of more than 3 million bubble chamber pictures have been taken with a triggered cross section smaller than 75% of the total inelastic cross section. Events containing charm particles were triggered with an efficiency of 98 +2 sub(-3)%. With the fiducial volume trigger, the probability for a picture to contain an interaction in the visible hydrogen increased from 47.3% to 59.5%, reducing film cost and processing effort with about 20%. The improvement in data taking rate is shown to be negligible. (author)

  19. Bulk-memory processor for data acquisition

    International Nuclear Information System (INIS)

    Nelson, R.O.; McMillan, D.E.; Sunier, J.W.; Meier, M.; Poore, R.V.

    1981-01-01

    To meet the diverse needs and data rate requirements at the Van de Graaff and Weapons Neutron Research (WNR) facilities, a bulk memory system has been implemented which includes a fast and flexible processor. This bulk memory processor (BMP) utilizes bit slice and microcode techniques and features a 24 bit wide internal architecture allowing direct addressing of up to 16 megawords of memory and histogramming up to 16 million counts per channel without overflow. The BMP is interfaced to the MOSTEK MK 8000 bulk memory system and to the standard MODCOMP computer I/O bus. Coding for the BMP both at the microcode level and with macro instructions is supported. The generalized data acquisition system has been extended to support the BMP in a manner transparent to the user

  20. Design of Processors with Reconfigurable Microarchitecture

    Directory of Open Access Journals (Sweden)

    Andrey Mokhov

    2014-01-01

    Full Text Available Energy becomes a dominating factor for a wide spectrum of computations: from intensive data processing in “big data” companies resulting in large electricity bills, to infrastructure monitoring with wireless sensors relying on energy harvesting. In this context it is essential for a computation system to be adaptable to the power supply and the service demand, which often vary dramatically during runtime. In this paper we present an approach to building processors with reconfigurable microarchitecture capable of changing the way they fetch and execute instructions depending on energy availability and application requirements. We show how to use Conditional Partial Order Graphs to formally specify the microarchitecture of such a processor, explore the design possibilities for its instruction set, and synthesise the instruction decoder using correct-by-construction techniques. The paper is focused on the design methodology, which is evaluated by implementing a power-proportional version of Intel 8051 microprocessor.

  1. Real time processor for array speckle interferometry

    International Nuclear Information System (INIS)

    Chin, G.; Florez, J.; Borelli, R.; Fong, W.; Miko, J.; Trujillo, C.

    1989-01-01

    With the construction of several new large aperture telescopes and the development of large format array detectors in the near IR, the ability to obtain diffraction limited seeing via IR array speckle interferometry offers a powerful tool. We are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element 2D complex FFT, and to average the power spectrum all within the 25 msec coherence time for speckles at near IR wavelength. The processor is a compact unit controlled by a PC with real time display and data storage capability. It provides the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with off-line methods

  2. Parallel processor programs in the Federal Government

    Science.gov (United States)

    Schneck, P. B.; Austin, D.; Squires, S. L.; Lehmann, J.; Mizell, D.; Wallgren, K.

    1985-01-01

    In 1982, a report dealing with the nation's research needs in high-speed computing called for increased access to supercomputing resources for the research community, research in computational mathematics, and increased research in the technology base needed for the next generation of supercomputers. Since that time a number of programs addressing future generations of computers, particularly parallel processors, have been started by U.S. government agencies. The present paper provides a description of the largest government programs in parallel processing. Established in fiscal year 1985 by the Institute for Defense Analyses for the National Security Agency, the Supercomputing Research Center will pursue research to advance the state of the art in supercomputing. Attention is also given to the DOE applied mathematical sciences research program, the NYU Ultracomputer project, the DARPA multiprocessor system architectures program, NSF research on multiprocessor systems, ONR activities in parallel computing, and NASA parallel processor projects.

  3. RISC Processors and High Performance Computing

    Science.gov (United States)

    Bailey, David H.; Saini, Subhash; Craw, James M. (Technical Monitor)

    1995-01-01

    This tutorial will discuss the top five RISC microprocessors and the parallel systems in which they are used. It will provide a unique cross-machine comparison not available elsewhere. The effective performance of these processors will be compared by citing standard benchmarks in the context of real applications. The latest NAS Parallel Benchmarks, both absolute performance and performance per dollar, will be listed. The next generation of the NPB will be described. The tutorial will conclude with a discussion of future directions in the field. Technology Transfer Considerations: All of these computer systems are commercially available internationally. Information about these processors is available in the public domain, mostly from the vendors themselves. The NAS Parallel Benchmarks and their results have been previously approved numerous times for public release, beginning back in 1991.

  4. Commissioning and validation of the ATLAS Level-1 topological trigger

    CERN Document Server

    AUTHOR|(SzGeCERN)788741; The ATLAS collaboration; Hong, Tae Min

    2017-01-01

    The ATLAS experiment has recently commissioned a new hardware component of its first-level trigger: the topological processor (L1Topo). This innovative system, using state-of-the-art FPGA processors, selects events by applying kinematic and topological requirements on candidate objects (energy clusters, jets, and muons) measured by calorimeters and muon sub-detectors. Since the first-level trigger is a synchronous pipelined system, such requirements are applied within a latency of 200ns. We will present the first results from data recorded using the L1Topo trigger; these demonstrate a significantly improved background event rejection, thus allowing for a rate reduction without efficiency loss. This improvement has been shown for several physics processes leading to low-$P_{T}$ leptons, including $H\\to{}\\tau{}\\tau{}$ and $J/\\Psi\\to{}\\mu{}\\mu{}$. In addition, we will discuss the use of an accurate L1Topo simulation as a powerful tool to validate and optimize the performance of this new trigger system. To reach ...

  5. Upgrade of the ATLAS Level-1 Trigger with event topology information

    CERN Document Server

    Simioni, Eduard; The ATLAS collaboration; Bauss, B; Büscher, V; Jakobi, K; Kaluza, A; Kahra, C; Reiss, A; Schäffer, J; Schulte, A; Simon, M; Tapprogge, S; Vogel, A; Zinser, M; Palka, M

    2015-01-01

    The Large Hadron Collider (LHC) in 2015 will collide proton beams with increased luminosity from \\unit{10^{34}} up to \\unit{3 \\times 10^{34}cm^{-2}s^{-1}}. ATLAS is an LHC experiment designed to measure decay properties of high energetic particles produced in the protons collisions. The higher luminosity places stringent operational and physical requirements on the ATLAS Trigger in order to reduce the 40MHz collision rate to a manageable event storage rate of 1kHz while at the same time, selecting those events with valuable physics meaning. The Level-1 Trigger is the first rate-reducing step in the ATLAS Trigger, with an output rate of 100kHz and decision latency of less than 2.5$\\mu s$. It is composed of the Calorimeter Trigger (L1Calo), the Muon Trigger (L1Muon) and the Central Trigger Processor (CTP). In 2014, there will be a new electronics element in the chain: the Topological Processor System (L1Topo system).\\\\ The L1Topo system consist of a single AdvancedTCA shelf equipped with three L1Topo processor ...

  6. The ATLAS Level-1 Topological Trigger performance in Run 2

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00120419; The ATLAS collaboration

    2017-01-01

    The Level-1 trigger is the first event rate reducing step in the ATLAS detector trigger system, with an output rate of up to 100 kHz and decision latency smaller than 2.5 μs. During the LHC shutdown after Run 1, the Level-1 trigger system was upgraded at hardware, firmware and software levels. In particular, a new electronics sub-system was introduced in the real-time data processing path: the Level-1 Topological trigger system. It consists of a single electronics shelf equipped with two Level-1 Topological processor blades. They receive real-time information from the Level-1 calorimeter and muon triggers, which is processed to measure angles between trigger objects, invariant masses or other kinematic variables. Complementary to other requirements, these measurements are taken into account in the final Level-1 trigger decision. The system was installed and commissioning started in 2015 and continued during 2016. As part of the commissioning, the decisions from individual algorithms were simulated and compar...

  7. Operation of the Upgraded ATLAS Level-1 Central Trigger System

    CERN Document Server

    Glatzer, Julian Maximilian Volker; The ATLAS collaboration

    2015-01-01

    The ATLAS Level-1 Central Trigger (L1CT) system is a central part of ATLAS data-taking and has undergone a major upgrade for Run 2 of the LHC, in order to cope with the expected increase of instantaneous luminosity of a factor of 2 with respect to Run 1. The upgraded hardware offers more flexibility in the trigger decisions due to the double amount of trigger inputs and usable trigger channels. It also provides an interface to the new topological trigger system. Operationally - particularly useful for commissioning, calibration and test runs - it allows concurrent running of up to 3 different sub-detector combinations. In this contribution, we give an overview of the operational software framework of the L1CT system with particular emphasis of the configuration, controls and monitoring aspects. The software framework allows a consistent configuration with respect to the ATLAS experiment and the LHC machine, upstream and downstream trigger processors, and the data acquisition. Trigger and dead-time rates are m...

  8. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  9. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  10. Silicon Processors Using Organically Reconfigurable Techniques (SPORT)

    Science.gov (United States)

    2014-05-19

    AFRL-OSR-VA-TR-2014-0132 SILICON PROCESSORS USING ORGANICALLY RECONFIGURABLE TECHNIQUES ( SPORT ) Dennis Prather UNIVERSITY OF DELAWARE Final Report 05...5a. CONTRACT NUMBER Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) 5b. GRANT NUMBER FA9550-10-1-0363 5c...Contract: Silicon Processes for Organically Reconfigurable Techniques ( SPORT ) Contract #: FA9550-10-1-0363 Reporting Period: 1 July 2010 – 31 December

  11. Quantum chemistry on a superconducting quantum processor

    Energy Technology Data Exchange (ETDEWEB)

    Kaicher, Michael P.; Wilhelm, Frank K. [Theoretical Physics, Saarland University, 66123 Saarbruecken (Germany); Love, Peter J. [Department of Physics and Astronomy, Tufts University, Medford, MA 02155 (United States)

    2016-07-01

    Quantum chemistry is the most promising civilian application for quantum processors to date. We study its adaptation to superconducting (sc) quantum systems, computing the ground state energy of LiH through a variational hybrid quantum classical algorithm. We demonstrate how interactions native to sc qubits further reduce the amount of quantum resources needed, pushing sc architectures as a near-term candidate for simulations of more complex atoms/molecules.

  12. Debugging in a multi-processor environment

    International Nuclear Information System (INIS)

    Spann, J.M.

    1981-01-01

    The Supervisory Control and Diagnostic System (SCDS) for the Mirror Fusion Test Facility (MFTF) consists of nine 32-bit minicomputers arranged in a tightly coupled distributed computer system utilizing a share memory as the data exchange medium. Debugging of more than one program in the multi-processor environment is a difficult process. This paper describes what new tools were developed and how the testing of software is performed in the SCDS for the MFTF project

  13. The design of the ZEUS tracking trigger and studies of b quark fragmentation

    Energy Technology Data Exchange (ETDEWEB)

    Silvester, I M

    1989-01-01

    This thesis consists of two parts, describing two very different aspects of experimental elementary particle physics. The first part describes, in detail, the design and estimated performance of a hardware track finding trigger processor. This processor is being built as part of the trigger for the ZEUS experiment, one of the two experiments being built to take data at the HERA electron-proton collider, currently under construction at the DESY laboratories in Hamburg. By using information from the main tracking chamber, the CTD, to reject data from events taking place outside the interaction region, this processor should be able to reduce the event rate from a beam crossing rate of 10{sup 6} s{sup -1} to approximately 9500 s{sup -1}. Used in conjunction with a trigger processor processing calorimeter data it should be able to achieve the desired first level trigger rate of 1 kHz. The second part describes two measurements of the fragmentation variable z for b quarks, made using a b enriched sample of 381 jets taken from the 31000 hadronic events with a centre of mass energy of 35 GeV observed with the TASSO detector during 1986. These measurements, obtained from the mean charged multiplicity and the rapidity distribution, have largely independent systematic uncertainties. The values obtained for (z{sub b}) were combined to give a value of 0.87{+-}0.02{+-}0.04. (author).

  14. Multibus-based parallel processor for simulation

    Science.gov (United States)

    Ogrady, E. P.; Wang, C.-H.

    1983-01-01

    A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

  15. Code compression for VLIW embedded processors

    Science.gov (United States)

    Piccinelli, Emiliano; Sannino, Roberto

    2004-04-01

    The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

  16. Techniques for optimizing inerting in electron processors

    International Nuclear Information System (INIS)

    Rangwalla, I.J.; Korn, D.J.; Nablo, S.V.

    1993-01-01

    The design of an ''inert gas'' distribution system in an electron processor must satisfy a number of requirements. The first of these is the elimination or control of beam produced ozone and NO x which can be transported from the process zone by the product into the work area. Since the tolerable levels for O 3 in occupied areas around the processor are 3 in the beam heated process zone, or exhausting and dilution of the gas at the processor exit. The second requirement of the inerting system is to provide a suitable environment for completing efficient, free radical initiated addition polymerization. The competition between radical loss through de-excitation and that from O 2 quenching must be understood. This group has used gas chromatographic analysis of electron cured coatings to study the trade-offs of delivered dose, dose rate and O 2 concentrations in the process zone to determine the tolerable ranges of parameter excursions for production quality control purposes. These techniques are described for an ink coating system on paperboard, where a broad range of process parameters have been studied (D, D radical, O 2 ). It is then shown how the technique is used to optimize the use of higher purity (10-100 ppm O 2 ) nitrogen gas for inerting, in combination with lower purity (2-20,000 ppm O 2 ) non-cryogenically produced gas, as from a membrane or pressure swing adsorption generators. (author)

  17. Treecode with a Special-Purpose Processor

    Science.gov (United States)

    Makino, Junichiro

    1991-08-01

    We describe an implementation of the modified Barnes-Hut tree algorithm for a gravitational N-body calculation on a GRAPE (GRAvity PipE) backend processor. GRAPE is a special-purpose computer for N-body calculations. It receives the positions and masses of particles from a host computer and then calculates the gravitational force at each coordinate specified by the host. To use this GRAPE processor with the hierarchical tree algorithm, the host computer must maintain a list of all nodes that exert force on a particle. If we create this list for each particle of the system at each timestep, the number of floating-point operations on the host and that on GRAPE would become comparable, and the increased speed obtained by using GRAPE would be small. In our modified algorithm, we create a list of nodes for many particles. Thus, the amount of the work required of the host is significantly reduced. This algorithm was originally developed by Barnes in order to vectorize the force calculation on a Cyber 205. With this algorithm, the computing time of the force calculation becomes comparable to that of the tree construction, if the GRAPE backend processor is sufficiently fast. The obtained speed-up factor is 30 to 50 for a RISC-based host computer and GRAPE-1A with a peak speed of 240 Mflops.

  18. Multi-processor network implementations in Multibus II and VME

    International Nuclear Information System (INIS)

    Briegel, C.

    1992-01-01

    ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

  19. LHCb Topological Trigger Reoptimization

    International Nuclear Information System (INIS)

    Likhomanenko, Tatiana; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Ilten, Philip; Williams, Michael

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so- called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all ’interesting” decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. Methods studied include cascading, ensembling and blending techniques. Furthermore, novel boosting techniques have been implemented that will help reduce systematic uncertainties in Run 2 measurements. We demonstrate that the reoptimized topological trigger is expected to significantly improve on the Run 1 performance for a wide range of b-hadron decays. (paper)

  20. NOMAD Trigger Studies

    International Nuclear Information System (INIS)

    Varvell, K.

    1995-01-01

    The author reports on the status of an offline study of the NOMAD triggers, which has several motivations. Of primary importance is to demonstrate, using offline information recorded by the individual subdetectors comprising NOMAD, that the online trigger system is functioning as expected. Such an investigation serves to complement the extensive monitoring which is already carried out online. More specific to the needs of the offline software and analysis, the reconstruction of tracks and vertices in the detector requires some knowledge of the time at which the trigger has occurred, in order to locate relevant hits in the drift chambers and muon chambers in particular. The fact that the different triggers allowed by the MIOTRINO board take varying times to form complicates this task. An offline trigger algorithm may serve as a tool to shed light on situations where the online trigger status bits have not been recorded correctly, as happens in a small number of cases, or as an aid to studies with the aim of further refinement of the online triggers themselves

  1. Boosted decision trees in the CMS Level-1 endcap muon trigger

    CERN Document Server

    Low, Jia Fu; Busch, Elena Laura; Carnes, Andrew Mathew; Furic, Ivan-Kresimir; Gleyzer, Sergei; Kotov, Khristian; Madorsky, Alexander; Rorie, Jamal Tildon; Scurlock, Bobby; Shi, Wei; Acosta, Darin Edward

    2017-01-01

    The first implementation of Boosted Decision Trees (BDTs) inside a Level-1 trigger system at the LHC is presented. The Endcap Muon Track Finder (EMTF) at CMS uses BDTs to infer the momentum of muons in the forward region of the detector, based on 25 different variables. Combinations of these variables are evaluated offline using regression BDTs, whose output is stored in 1.2 GB look-up tables (LUTs) in the EMTF hardware. These BDTs take advantage of complex correlations between variables, the inhomogeneous magnetic field, and non-linear effects such as inelastic scattering to distinguish high-momentum signal muons from the overwhelming low-momentum background. The LUTs are used to turn the complex BDT evaluation into a simple look-up operation in fixed low latency. The new momentum assignment algorithm has reduced the trigger rate by a factor of 3 at the 25 GeV trigger threshold with respect to the legacy system, with further improvements foreseen in the coming year.

  2. Merged ozone profiles from four MIPAS processors

    Science.gov (United States)

    Laeng, Alexandra; von Clarmann, Thomas; Stiller, Gabriele; Dinelli, Bianca Maria; Dudhia, Anu; Raspollini, Piera; Glatthor, Norbert; Grabowski, Udo; Sofieva, Viktoria; Froidevaux, Lucien; Walker, Kaley A.; Zehner, Claus

    2017-04-01

    The Michelson Interferometer for Passive Atmospheric Sounding (MIPAS) was an infrared (IR) limb emission spectrometer on the Envisat platform. Currently, there are four MIPAS ozone data products, including the operational Level-2 ozone product processed at ESA, with the scientific prototype processor being operated at IFAC Florence, and three independent research products developed by the Istituto di Fisica Applicata Nello Carrara (ISAC-CNR)/University of Bologna, Oxford University, and the Karlsruhe Institute of Technology-Institute of Meteorology and Climate Research/Instituto de Astrofísica de Andalucía (KIT-IMK/IAA). Here we present a dataset of ozone vertical profiles obtained by merging ozone retrievals from four independent Level-2 MIPAS processors. We also discuss the advantages and the shortcomings of this merged product. As the four processors retrieve ozone in different parts of the spectra (microwindows), the source measurements can be considered as nearly independent with respect to measurement noise. Hence, the information content of the merged product is greater and the precision is better than those of any parent (source) dataset. The merging is performed on a profile per profile basis. Parent ozone profiles are weighted based on the corresponding error covariance matrices; the error correlations between different profile levels are taken into account. The intercorrelations between the processors' errors are evaluated statistically and are used in the merging. The height range of the merged product is 20-55 km, and error covariance matrices are provided as diagnostics. Validation of the merged dataset is performed by comparison with ozone profiles from ACE-FTS (Atmospheric Chemistry Experiment-Fourier Transform Spectrometer) and MLS (Microwave Limb Sounder). Even though the merging is not supposed to remove the biases of the parent datasets, around the ozone volume mixing ratio peak the merged product is found to have a smaller (up to 0.1 ppmv

  3. Bringing High Rate, Low Latency Data From Unimak Island, Alaska

    Science.gov (United States)

    Feaux, K.; Jackson, M.; Mencin, D.; Gallaher, W.; Smith, S.; Bohnenstiehl, K.; Borsa, A.; Enders, M.; Coyle, B.; Paskievitch, J.; Read, C.

    2009-05-01

    The Plate Boundary Observatory (PBO), part of the NSF-funded EarthScope project, completed the installation of a fourteen GPS stations, eight tiltmeters, one webcam, and one digital broadband seismometer on Unimak Island, Alaska in August, 2008. PBO collaborated with the USGS, who provided engineering support for this project. Combined with the USGS operated seismic network, the Unimak Island network is a state of the art scientific network. The primary data communications goal of the project was to design and implement a robust data communications network capable of downloading 15-sec daily GPS files and to test the streaming of 1- Hz GPS data at a select set of GPS stations on Unimak Island. As part of the permitting agreement with the landowner, PBO co-located the GPS stations with existing USGS seismic stations. The high-speed radio link deployed allowed the USGS to test the feasibility of broadband seismometer installations on Unimak Island. This collaboration with the USGS was another successful joint operation between PBO and the USGS. The technical and logistical challenges involved in the project as well as some preliminary results of the data communications system will be presented. These challenges include complicated logistics, bad weather, complex network geometries with multiple radio repeaters, long distance RF transmission over water, hardware bandwidth limitations, power limitations, space limitations, as well as working in bear country on an incredibly remote and active volcano.

  4. Preventing Active Timing Attacks in Low-Latency Anonymous Communication

    Science.gov (United States)

    2010-04-26

    measured routers with the modifiers “Exit”, “Fast”, “Running”, “Stable”, and “Valid”. The routers also had to be non- hibernating and could not have exit...Tor client was a custom client written in Java . Packet traces were recorded using tcpdump. The timestamps on these were used to determine the timing of

  5. Low-latency wireless data transfer for motion control

    NARCIS (Netherlands)

    Boeij, de J.; Haazen, M.H.; Smulders, P.F.M.; Lomonova, E.A.

    2009-01-01

    This paper discusses a new approach for wireless motion control. Existing wireless techniques suffer from large closed loop delays of several milliseconds, which is unacceptable in precision motion systems. These large delays are mainly caused by the protocol used, since these are optimized for

  6. Reliability in Warehouse-Scale Computing: Why Low Latency Matters

    DEFF Research Database (Denmark)

    Nannarelli, Alberto

    2015-01-01

    , the limiting factor of these warehouse-scale data centers is the power dissipation. Power is dissipated not only in the computation itself, but also in heat removal (fans, air conditioning, etc.) to keep the temperature of the devices within the operating ranges. The need to keep the temperature low within......Warehouse sized buildings are nowadays hosting several types of large computing systems: from supercomputers to large clusters of servers to provide the infrastructure to the cloud. Although the main target, especially for high-performance computing, is still to achieve high throughput...

  7. Robust Throughput Boosting for Low Latency Dynamic Partial Reconfiguration

    DEFF Research Database (Denmark)

    Nannarelli, Alberto; Re, M.; Cardarilli, Gian Carlo

    2017-01-01

    Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over-clocking th......Reducing the configuration time of portions of an FPGA at run time is crucial in contemporary FPGA-based accelerators. In this work, we propose a method to increase the throughput for FPGA dynamic partial reconfiguration by using standard IP blocks. The throughput is increased by over...

  8. System and Analysis for Low Latency Video Processing using Microservices

    OpenAIRE

    VASUKI BALASUBRAMANIAM, KARTHIKEYAN

    2017-01-01

    The evolution of big data processing and analysis has led to data-parallel frameworks such as Hadoop, MapReduce, Spark, and Hive, which are capable of analyzing large streams of data such as server logs, web transactions, and user reviews. Videos are one of the biggest sources of data and dominate the Internet traffic. Video processing on a large scale is critical and challenging as videos possess spatial and temporal features, which are not taken into account by the existing data-parallel fr...

  9. Timing, Trigger and Control Systems for LHC Detectors

    CERN Multimedia

    2002-01-01

    \\\\ \\\\At the LHC, precise bunch-crossing clock and machine orbit signals must be broadcast over distances of several km from the Prevessin Control Room to the four experiment areas and other destinations. At the LHC experiments themselves, quite extensive distribution systems are also required for the transmission of timing, trigger and control (TTC) signals to large numbers of front-end electronics controllers from a single location in the vicinity of the central trigger processor. The systems must control the detector synchronization and deliver the necessary fast signals and messages that are phased with the LHC clock, orbit or bunch structure. These include the bunch-crossing clock, level-1 trigger decisions, bunch and event numbers, as well as test signals and broadcast commands. A common solution to this TTC system requirement is expected to result in important economies of scale and permit a rationalization of the development, operational and support efforts required. LHC Common Project RD12 is developi...

  10. Supervision of the ATLAS High Level Trigger System

    CERN Document Server

    Wheeler, S.; Meessen, C.; Qian, Z.; Touchard, F.; Negri, France A.; Zobernig, H.; CHEP 2003 Computing in High Energy Physics; Negri, France A.

    2003-01-01

    The ATLAS High Level Trigger (HLT) system provides software-based event selection after the initial LVL1 hardware trigger. It is composed of two stages, the LVL2 trigger and the Event Filter. The HLT is implemented as software tasks running on large processor farms. An essential part of the HLT is the supervision system, which is responsible for configuring, coordinating, controlling and monitoring the many hundreds of processes running in the HLT. A prototype implementation of the supervision system, using tools from the ATLAS Online Software system is presented. Results from scalability tests are also presented where the supervision system was shown to be capable of controlling over 1000 HLT processes running on 230 nodes.

  11. A Muon Trigger with high pT-resolution for Phase-II of the LHC Upgrade, based on the ATLAS Muon Drift Tube Chambers

    CERN Document Server

    Nowak, S; The ATLAS collaboration

    2014-01-01

    The ATLAS Muon Trigger in the ATLAS end-cap region is based on Thin Gap Chambers (TGC) which have an excellent time resolution but a moderate spatial resolution. The Muon Trigger efficiency curves show that for a transverse momentum ($p_{t}$) threshold of 20 GeVc$^{-1}$ the trigger rate is mainly dominated by muons with a $p_{t}$ between 10 GeVc$^{-1}$ and 20 GeVc$^{-1}$. To cope with the expected Muon Trigger rate at HL-LHC luminosities, we propose to include the precision tracking chambers (MDT) in the Muon Trigger. According to a potential study based on ATLAS data and assuming the HL-LHC scenario, this leads to a dramatical reduction of the Muon Trigger rate below the nominal threshold. As the already existing MDT chamber read-out chain is not capable of reading out the MDT fast enough to be used for the Muon Trigger, an additional fast read-out (FRO) chain with moderate spatial resolution but low latency is necessary. To conduct fast track reconstruction and muon $p_{t}$ determination with the data acqui...

  12. Intelligent trigger by massively parallel processors for high energy physics experiments

    International Nuclear Information System (INIS)

    Rohrbach, F.; Vesztergombi, G.

    1992-01-01

    The CERN-MPPC collaboration concentrates its effort on the development of machines based on massive parallelism with thousands of integrated processing elements, arranged in a string. Seven applications are under detailed studies within the collaboration: three for LHC, one for SSC, two for fixed target high energy physics at CERN and one for HDTV. Preliminary results are presented. They show that the objectives should be reached with the use of the ASP architecture. (author)

  13. Calo trigger acquisition system

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    Calo trigger acquisition system - Evolution of the acquisition system from a multiple boards system (upper, orange cables) to a single board one (below, light blue cables) where all the channels are collected in a single board.

  14. Calorimetry triggering in ATLAS

    CERN Document Server

    Igonkina, O; Adragna, P; Aharrouche, M; Alexandre, G; Andrei, V; Anduaga, X; Aracena, I; Backlund, S; Baines, J; Barnett, B M; Bauss, B; Bee, C; Behera, P; Bell, P; Bendel, M; Benslama, K; Berry, T; Bogaerts, A; Bohm, C; Bold, T; Booth, J R A; Bosman, M; Boyd, J; Bracinik, J; Brawn, I, P; Brelier, B; Brooks, W; Brunet, S; Bucci, F; Casadei, D; Casado, P; Cerri, A; Charlton, D G; Childers, J T; Collins, N J; Conde Muino, P; Coura Torres, R; Cranmer, K; Curtis, C J; Czyczula, Z; Dam, M; Damazio, D; Davis, A O; De Santo, A; Degenhardt, J; Delsart, P A; Demers, S; Demirkoz, B; Di Mattia, A; Diaz, M; Djilkibaev, R; Dobson, E; Dova, M, T; Dufour, M A; Eckweiler, S; Ehrenfeld, W; Eifert, T; Eisenhandler, E; Ellis, N; Emeliyanov, D; Enoque Ferreira de Lima, D; Faulkner, P J W; Ferland, J; Flacher, H; Fleckner, J E; Flowerdew, M; Fonseca-Martin, T; Fratina, S; Fhlisch, F; Gadomski, S; Gallacher, M P; Garitaonandia Elejabarrieta, H; Gee, C N P; George, S; Gillman, A R; Goncalo, R; Grabowska-Bold, I; Groll, M; Gringer, C; Hadley, D R; Haller, J; Hamilton, A; Hanke, P; Hauser, R; Hellman, S; Hidvgi, A; Hillier, S J; Hryn'ova, T; Idarraga, J; Johansen, M; Johns, K; Kalinowski, A; Khoriauli, G; Kirk, J; Klous, S; Kluge, E-E; Koeneke, K; Konoplich, R; Konstantinidis, N; Kwee, R; Landon, M; LeCompte, T; Ledroit, F; Lei, X; Lendermann, V; Lilley, J N; Losada, M; Maettig, S; Mahboubi, K; Mahout, G; Maltrana, D; Marino, C; Masik, J; Meier, K; Middleton, R P; Mincer, A; Moa, T; Monticelli, F; Moreno, D; Morris, J D; Mller, F; Navarro, G A; Negri, A; Nemethy, P; Neusiedl, A; Oltmann, B; Olvito, D; Osuna, C; Padilla, C; Panes, B; Parodi, F; Perera, V J O; Perez, E; Perez Reale, V; Petersen, B; Pinzon, G; Potter, C; Prieur, D P F; Prokishin, F; Qian, W; Quinonez, F; Rajagopalan, S; Reinsch, A; Rieke, S; Riu, I; Robertson, S; Rodriguez, D; Rogriquez, Y; Rhr, F; Saavedra, A; Sankey, D P C; Santamarina, C; Santamarina Rios, C; Scannicchio, D; Schiavi, C; Schmitt, K; Schultz-Coulon, H C; Schfer, U; Segura, E; Silverstein, D; Silverstein, S; Sivoklokov, S; Sjlin, J; Staley, R J; Stamen, R; Stelzer, J; Stockton, M C; Straessner, A; Strom, D; Sushkov, S; Sutton, M; Tamsett, M; Tan, C L A; Tapprogge, S; Thomas, J P; Thompson, P D; Torrence, E; Tripiana, M; Urquijo, P; Urrejola, P; Vachon, B; Vercesi, V; Vorwerk, V; Wang, M; Watkins, P M; Watson, A; Weber, P; Weidberg, T; Werner, P; Wessels, M; Wheeler-Ellis, S; Whiteson, D; Wiedenmann, W; Wielers, M; Wildt, M; Winklmeier, F; Wu, X; Xella, S; Zhao, L; Zobernig, H; de Seixas, J M; dos Anjos, A; Asman, B; Özcan, E

    2009-01-01

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2 105 to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  15. BTeV Trigger

    International Nuclear Information System (INIS)

    Gottschalk, Erik E.

    2006-01-01

    BTeV was designed to conduct precision studies of CP violation in BB-bar events using a forward-geometry detector in a hadron collider. The detector was optimized for high-rate detection of beauty and charm particles produced in collisions between protons and antiprotons. The trigger was designed to take advantage of the main difference between events with beauty and charm particles and more typical hadronic events-the presence of detached beauty and charm decay vertices. The first stage of the BTeV trigger was to receive data from a pixel vertex detector, reconstruct tracks and vertices for every beam crossing, reject at least 98% of beam crossings in which neither beauty nor charm particles were produced, and trigger on beauty events with high efficiency. An overview of the trigger design and its evolution to include commodity networking and computing components is presented

  16. Calorimetry triggering in ATLAS

    International Nuclear Information System (INIS)

    Igonkina, O; Achenbach, R; Andrei, V; Adragna, P; Aharrouche, M; Bauss, B; Bendel, M; Alexandre, G; Anduaga, X; Aracena, I; Backlund, S; Bogaerts, A; Baines, J; Barnett, B M; Bee, C; P, Behera; Bell, P; Benslama, K; Berry, T; Bohm, C

    2009-01-01

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2 | 10 5 to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  17. Calorimetry Triggering in ATLAS

    International Nuclear Information System (INIS)

    Igonkina, O.; Achenbach, R.; Adragna, P.; Aharrouche, M.; Alexandre, G.; Andrei, V.; Anduaga, X.; Aracena, I.; Backlund, S.; Baines, J.; Barnett, B.M.; Bauss, B.; Bee, C.; Behera, P.; Bell, P.; Bendel, M.; Benslama, K.; Berry, T.; Bogaerts, A.; Bohm, C.; Bold, T.; Booth, J.R.A.; Bosman, M.; Boyd, J.; Bracinik, J.; Brawn, I.P.; Brelier, B.; Brooks, W.; Brunet, S.; Bucci, F.; Casadei, D.; Casado, P.; Cerri, A.; Charlton, D.G.; Childers, J.T.; Collins, N.J.; Conde Muino, P.; Coura Torres, R.; Cranmer, K.; Curtis, C.J.; Czyczula, Z.; Dam, M.; Damazio, D.; Davis, A.O.; De Santo, A.; Degenhardt, J.

    2011-01-01

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2/10 5 to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  18. Calorimetry triggering in ATLAS

    Energy Technology Data Exchange (ETDEWEB)

    Igonkina, O [Nikhef National Institute for Subatomic Physics, Amsterdam (Netherlands); Achenbach, R; Andrei, V [Kirchhoff Institut fuer Physik, Universitaet Heidelberg, Heidelberg (Germany); Adragna, P [Physics Department, Queen Mary, University of London, London (United Kingdom); Aharrouche, M; Bauss, B; Bendel, M [Institut fr Physik, Universitt Mainz, Mainz (Germany); Alexandre, G [Section de Physique, Universite de Geneve, Geneva (Switzerland); Anduaga, X [Universidad Nacional de La Plata, La Plata (Argentina); Aracena, I [Stanford Linear Accelerator Center (SLAC), Stanford (United States); Backlund, S; Bogaerts, A [European Laboratory for Particle Physics (CERN), Geneva (Switzerland); Baines, J; Barnett, B M [STFC Rutherford Appleton Laboratory, Harwell Science and Innovation Campus, Didcot, Oxon (United Kingdom); Bee, C [Centre de Physique des Particules de Marseille, IN2P3-CNRS, Marseille (France); P, Behera [Iowa State University, Ames, Iowa (United States); Bell, P [School of Physics and Astronomy, University of Manchester, Manchester (United Kingdom); Benslama, K [University of Regina, Regina (Canada); Berry, T [Department of Physics, Royal Holloway and Bedford New College, Egham (United Kingdom); Bohm, C [Fysikum, Stockholm University, Stockholm (Sweden)

    2009-04-01

    The ATLAS experiment is preparing for data taking at 14 TeV collision energy. A rich discovery physics program is being prepared in addition to the detailed study of Standard Model processes which will be produced in abundance. The ATLAS multi-level trigger system is designed to accept one event in 2 | 10{sup 5} to enable the selection of rare and unusual physics events. The ATLAS calorimeter system is a precise instrument, which includes liquid Argon electro-magnetic and hadronic components as well as a scintillator-tile hadronic calorimeter. All these components are used in the various levels of the trigger system. A wide physics coverage is ensured by inclusively selecting events with candidate electrons, photons, taus, jets or those with large missing transverse energy. The commissioning of the trigger system is being performed with cosmic ray events and by replaying simulated Monte Carlo events through the trigger and data acquisition system.

  19. LHCb Topological Trigger Reoptimization

    CERN Document Server

    INSPIRE-00400931; Ilten, Philip; Khairullin, Egor; Rogozhnikov, Alex; Ustyuzhanin, Andrey; Williams, Michael

    2015-12-23

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger, which utilized a custom boosted decision tree algorithm, selected a nearly 100% pure sample of b-hadrons with a typical efficiency of 60-70%; its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and neural networks. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. ...

  20. Topological Trigger Developments

    CERN Multimedia

    Likhomanenko, Tatiana

    2015-01-01

    The main b-physics trigger algorithm used by the LHCb experiment is the so-called topological trigger. The topological trigger selects vertices which are a) detached from the primary proton-proton collision and b) compatible with coming from the decay of a b-hadron. In the LHC Run 1, this trigger utilized a custom boosted decision tree algorithm, selected an almost 100% pure sample of b-hadrons with a typical efficiency of 60-70%, and its output was used in about 60% of LHCb papers. This talk presents studies carried out to optimize the topological trigger for LHC Run 2. In particular, we have carried out a detailed comparison of various machine learning classifier algorithms, e.g., AdaBoost, MatrixNet and uBoost. The topological trigger algorithm is designed to select all "interesting" decays of b-hadrons, but cannot be trained on every such decay. Studies have therefore been performed to determine how to optimize the performance of the classification algorithm on decays not used in the training. These inclu...

  1. Architecture of a Level 1 Track Trigger for the CMS Experiment

    CERN Document Server

    Heintz, Ulrich

    2010-01-01

    The luminosity goal for the Super-LHC is 1035/cm2/s. At this luminosity the number of proton-proton interactions in each beam crossing will be in the hundreds. This will stress many components of the CMS detector. One system that has to be upgraded is the trigger system. To keep the rate at which the level 1 trigger fires manageable, information from the tracker has to be integrated into the level 1 trigger. Current design proposals foresee tracking detectors that perform on-detector filtering to reject hits from low-momentum particles. In order to build a trigger system, the filtered hit data from different layers and sectors of the tracker will have to be transmitted off the detector and brought together in a logic processor that generates trigger tracks within the time window allowed by the level 1 trigger latency. I will describe a possible architecture for the off-detector logic that accomplishes this goal.

  2. Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

    Science.gov (United States)

    Cerati, Giuseppe; Elmer, Peter; Krutelyov, Slava; Lantz, Steven; Lefebvre, Matthieu; Masciovecchio, Mario; McDermott, Kevin; Riley, Daniel; Tadel, Matevž; Wittich, Peter; Würthwein, Frank; Yagil, Avi

    2017-08-01

    For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

  3. Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

    Directory of Open Access Journals (Sweden)

    Cerati Giuseppe

    2017-01-01

    Full Text Available For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU, ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC, for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

  4. Parallelized Kalman-Filter-Based Reconstruction of Particle Tracks on Many-Core Processors and GPUs

    Energy Technology Data Exchange (ETDEWEB)

    Cerati, Giuseppe [Fermilab; Elmer, Peter [Princeton U.; Krutelyov, Slava [UC, San Diego; Lantz, Steven [Cornell U.; Lefebvre, Matthieu [Princeton U.; Masciovecchio, Mario [UC, San Diego; McDermott, Kevin [Cornell U.; Riley, Daniel [Cornell U., LNS; Tadel, Matevž [UC, San Diego; Wittich, Peter [Cornell U.; Würthwein, Frank [UC, San Diego; Yagil, Avi [UC, San Diego

    2017-01-01

    For over a decade now, physical and energy constraints have limited clock speed improvements in commodity microprocessors. Instead, chipmakers have been pushed into producing lower-power, multi-core processors such as Graphical Processing Units (GPU), ARM CPUs, and Intel MICs. Broad-based efforts from manufacturers and developers have been devoted to making these processors user-friendly enough to perform general computations. However, extracting performance from a larger number of cores, as well as specialized vector or SIMD units, requires special care in algorithm design and code optimization. One of the most computationally challenging problems in high-energy particle experiments is finding and fitting the charged-particle tracks during event reconstruction. This is expected to become by far the dominant problem at the High-Luminosity Large Hadron Collider (HL-LHC), for example. Today the most common track finding methods are those based on the Kalman filter. Experience with Kalman techniques on real tracking detector systems has shown that they are robust and provide high physics performance. This is why they are currently in use at the LHC, both in the trigger and offine. Previously we reported on the significant parallel speedups that resulted from our investigations to adapt Kalman filters to track fitting and track building on Intel Xeon and Xeon Phi. Here, we discuss our progresses toward the understanding of these processors and the new developments to port the Kalman filter to NVIDIA GPUs.

  5. The bit slice micro-processor 'GESPRO' as a project in the UA2 experiment

    CERN Document Server

    Becam, C; Delanghe, J; Fest, H M; Lecoq, J; Martin, H; Mencik, M; MerkeI, B; Meyer, J M; Perrin, M; Plothow, H; Rampazzo, J P; Schittly, A

    1981-01-01

    The bit slice micro-processor GESPRO is a CAMAC module plugged into a standard Elliot system crate via which it communicates as a slave with its host computer. It has full control of CAMAC as a master unit. GESPRO is a 24 bit machine with multi-mode memory addressing capacity of 64K words. The micro-processor structure uses 5 buses including pipe-line registers to mask access time and 16 interrupt levels. The micro-program memory capacity is 2K (RAM) words of 48 bits each. A special hardwired module allows floating point, as well as integer, multiplication of 24*24 bits, result in 48 bits, in about 200 ns. This micro-processor could be used in the UA2 data acquisition chain and trigger system for the following tasks: (a) online data reduction, i.e. to read DURANDAL, process the information resulting in accepting or rejecting the event; (b) readout and analysis of the accepted data; (c) preprocess the data. The UA2 version of GESPRO is under construction, programs and micro-programs are under development. Hard...

  6. Modcomp MAX IV System Processors reference guide

    Energy Technology Data Exchange (ETDEWEB)

    Cummings, J.

    1990-10-01

    A user almost always faces a big problem when having to learn to use a new computer system. The information necessary to use the system is often scattered throughout many different manuals. The user also faces the problem of extracting the information really needed from each manual. Very few computer vendors supply a single Users Guide or even a manual to help the new user locate the necessary manuals. Modcomp is no exception to this, Modcomp MAX IV requires that the user be familiar with the system file usage which adds to the problem. At General Atomics there is an ever increasing need for new users to learn how to use the Modcomp computers. This paper was written to provide a condensed Users Reference Guide'' for Modcomp computer users. This manual should be of value not only to new users but any users that are not Modcomp computer systems experts. This Users Reference Guide'' is intended to provided the basic information for the use of the various Modcomp System Processors necessary to, create, compile, link-edit, and catalog a program. Only the information necessary to provide the user with a basic understanding of the Systems Processors is included. This document provides enough information for the majority of programmers to use the Modcomp computers without having to refer to any other manuals. A lot of emphasis has been placed on the file description and usage for each of the System Processors. This allows the user to understand how Modcomp MAX IV does things rather than just learning the system commands.

  7. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  8. The design of a graphics processor

    International Nuclear Information System (INIS)

    Holmes, M.; Thorne, A.R.

    1975-12-01

    The design of a graphics processor is described which takes into account known and anticipated user requirements, the availability of cheap minicomputers, the state of integrated circuit technology, and the overall need to minimise cost for a given performance. The main user needs are the ability to display large high resolution pictures, and to dynamically change the user's view in real time by means of fast coordinate processing hardware. The transformations that can be applied to 2D or 3D coordinates either singly or in combination are: translation, scaling, mirror imaging, rotation, and the ability to map the transformation origin on to any point on the screen. (author)

  9. Dual-scale topology optoelectronic processor.

    Science.gov (United States)

    Marsden, G C; Krishnamoorthy, A V; Esener, S C; Lee, S H

    1991-12-15

    The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.

  10. Nuclear interactive evaluations on distributed processors

    International Nuclear Information System (INIS)

    Dix, G.E.; Congdon, S.P.

    1988-01-01

    BWR [boiling water reactor] nuclear design is a complicated process, involving trade-offs among a variety of conflicting objectives. Complex computer calculations and usually required for each design iteration. GE Nuclear Energy has implemented a system where the evaluations are performed interactively on a large number of small microcomputers. This approach minimizes the time it takes to carry out design iterations even through the processor speeds are low compared with modern super computers. All of the desktop microcomputers are linked to a common data base via an ethernet communications system so that design data can be shared and data quality can be maintained

  11. Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    Levinskas, D.

    1993-01-01

    This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves

  12. Lattice gauge theory using parallel processors

    International Nuclear Information System (INIS)

    Lee, T.D.; Chou, K.C.; Zichichi, A.

    1987-01-01

    The book's contents include: Lattice Gauge Theory Lectures: Introduction and Current Fermion Simulations; Monte Carlo Algorithms for Lattice Gauge Theory; Specialized Computers for Lattice Gauge Theory; Lattice Gauge Theory at Finite Temperature: A Monte Carlo Study; Computational Method - An Elementary Introduction to the Langevin Equation, Present Status of Numerical Quantum Chromodynamics; Random Lattice Field Theory; The GF11 Processor and Compiler; and The APE Computer and First Physics Results; Columbia Supercomputer Project: Parallel Supercomputer for Lattice QCD; Statistical and Systematic Errors in Numerical Simulations; Monte Carlo Simulation for LGT and Programming Techniques on the Columbia Supercomputer; Food for Thought: Five Lectures on Lattice Gauge Theory

  13. Introduction to programming multiple-processor computers

    International Nuclear Information System (INIS)

    Hicks, H.R.; Lynch, V.E.

    1985-04-01

    FORTRAN applications programs can be executed on multiprocessor computers in either a unitasking (traditional) or multitasking form. The latter allows a single job to use more than one processor simultaneously, with a consequent reduction in wall-clock time and, perhaps, the cost of the calculation. An introduction to programming in this environment is presented. The concepts of synchronization and data sharing using EVENTS and LOCKS are illustrated with examples. The strategy of strong synchronization and the use of synchronization templates are proposed. We emphasize that incorrect multitasking programs can produce irreproducible results, which makes debugging more difficult

  14. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Andrei, George Victor

    2010-10-27

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  15. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    International Nuclear Information System (INIS)

    Andrei, George Victor

    2010-01-01

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  16. The data path of the ATLAS level-1 calorimeter trigger preprocessor

    Energy Technology Data Exchange (ETDEWEB)

    Andrei, George Victor

    2010-10-27

    The PreProcessor of the ATLAS Level-1 Calorimeter Trigger provides digital values of transverse energy in real-time to the subsequent object-finding processors. The input comprises more than 7000 analogue signals of reduced granularity from the calorimeters of the ATLAS detector. The Level-1 trigger decision must be verified. For this, the PreProcessor transmits copies of the real-time digital data to the Data Acquisition (DAQ) system. In addition, the PreProcessor system provides a standard VMEbus interface to the computing infrastructure of the experiment, on which configuration data is loaded and control or monitoring data are read out. A dedicated system that ensures both the transfer of event data to storage in ATLAS and the data transfer over the VME was implemented on the 124 modules of the PreProcessor system in the form of a ''Readout Manager''. The ''Field Programmable Gate Array'' (FPGA) is located on each module. The rst part of this work describes the algorithms developed to meet the functionality of the Readout Manager. The second part deals with the tests that were carried out to ensure the proper functionality of the modules before they were installed at CERN in the ATLAS cavern. (orig.)

  17. Recommending the heterogeneous cluster type multi-processor system computing

    International Nuclear Information System (INIS)

    Iijima, Nobukazu

    2010-01-01

    Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

  18. Implementation of a level 1 trigger system using high speed serial (VXS) techniques for the 12GeV high luminosity experimental programs at Thomas Jefferson National Accelerator Facility

    International Nuclear Information System (INIS)

    Cuevas, C.; Raydo, B.; Dong, H.; Gupta, A.; Barbosa, F.J.; Wilson, J.; Taylor, W.M.; Jastrzembski, E.; Abbott, D.

    2009-01-01

    We will demonstrate a hardware and firmware solution for a complete fully pipelined multi-crate trigger system that takes advantage of the elegant high speed VXS serial extensions for VME. This trigger system includes three sections starting with the front end crate trigger processor (CTP), a global Sub-System Processor (SSP) and a Trigger Supervisor that manages the timing, synchronization and front end event readout. Within a front end crate, trigger information is gathered from each 16 Channel, 12 bit Flash ADC module at 4 nS intervals via the VXS backplane, to a Crate Trigger Processor (CTP). Each Crate Trigger Processor receives these 500 MB/S VXS links from the 16 FADC-250 modules, aligns skewed data inherent of Aurora protocol, and performs real time crate level trigger algorithms. The algorithm results are encoded using a Reed-Solomon technique and transmission of this Level 1 trigger data is sent to the SSP using a multi-fiber link. The multi-fiber link achieves an aggregate trigger data transfer rate to the global trigger at 8 Gb/s. The SSP receives and decodes Reed-Solomon error correcting transmission from each crate, aligns the data, and performs the global level trigger algorithms. The entire trigger system is synchronous and operates at 250 MHz with the Trigger Supervisor managing not only the front end event readout, but also the distribution of the critical timing clocks, synchronization signals, and the global trigger signals to each front end readout crate. These signals are distributed to the front end crates on a separate fiber link and each crate is synchronized using a unique encoding scheme to guarantee that each front end crate is synchronous with a fixed latency, independent of the distance between each crate. The overall trigger signal latency is <3 uS, and the proposed 12GeV experiments at Jefferson Lab require up to 200KHz Level 1 trigger rate.

  19. SSC 254 Screen-Based Word Processors: Production Tests. The Lanier Word Processor.

    Science.gov (United States)

    Moyer, Ruth A.

    Designed for use in Trident Technical College's Secretarial Lab, this series of 12 production tests focuses on the use of the Lanier Word Processor for a variety of tasks. In tests 1 and 2, students are required to type and print out letters. Tests 3 through 8 require students to reformat a text; make corrections on a letter; divide and combine…

  20. CMS Trigger Performance

    CERN Document Server

    Donato, Silvio

    2017-01-01

    During its second run of operation (Run 2) which started in 2015, the LHC will deliver a peak instantaneous luminosity that may reach $2 \\cdot 10^{34}$ cm$^{-2}$s$^{-1}$ with an average pile-up of about 55, far larger than the design value. Under these conditions, the online event selection is a very challenging task. In CMS, it is realized by a two-level trigger system the Level-1 (L1) Trigger, implemented in custom-designed electronics, and the High Level Trigger (HLT), a streamlined version of the offline reconstruction software running on a computer farm. In order to face this challenge, the L1 trigger has been through a major upgrade compared to Run 1, whereby all electronic boards of the system have been replaced, allowing more sophisticated algorithms to be run online. Its last stage, the global trigger, is now able to perform complex selections and to compute high-level quantities, like invariant masses. Likewise, the algorithms that run in the HLT go through big improvements; in particular, new appr...

  1. Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

    OpenAIRE

    Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

    2016-01-01

    International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

  2. Upgrade of the ATLAS Level-1 Calorimeter Trigger

    CERN Document Server

    Wessels, M; The ATLAS collaboration

    2014-01-01

    The Level-1 Calorimeter Trigger (L1Calo) of the ATLAS experiment has been operating well since the start of LHC data taking, and played a major role in the Higgs boson discovery. To face the new challenges posed by the upcoming increases of the LHC proton beam energy and luminosity, a series of upgrades is planned for L1Calo. The initial upgrade phase in 2013-14 includes substantial improvements to the analogue and digital signal processing to allow more sophisticated digital filters for energy and timing measurement, as well as compensate for pile-up and baseline shifting effects. Two existing digital algorithm processor subsystems will receive substantial hardware and firmware upgrades to increase the real-time data path bandwidth, allowing topological information to be transmitted and processed at Level-1. An entirely new subsystem, the Level-1 Topological Processor, will receive real-time data from both the upgraded L1Calo and Level-1 Muon Trigger to perform trigger algorithms based on entire event topolo...

  3. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  4. Associative Memory Design for the Fast TracKer Processor (FTK)at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beretta, M; Bossini, E; Crescioli, F; Dell'Orso, M; Giannetti, P; Hoff, J; Liu, T; Liberali, V; Sacco, I; Schoening, A; Soltveit, H K; Stabile, A; Tripiccione, R

    2011-01-01

    We describe a VLSI processor for pattern recognition based on Content Addressable Memory (CAM) architecture, optimized for on-line track finding in high-energy physics experiments. A large CAM bank stores all trajectories of interest and extracts the ones compatible with a given event. This task is naturally parallelized by a CAM architecture able to output identified trajectories, recognized among a huge amount of possible combinations, in just a few 100 MHz clock cycles. We have developed this device (called the AMchip03 processor), using 180 nm technology, for the Silicon Vertex Trigger (SVT) upgrade at CDF [1] using a standard-cell VLSI design methodology. We propose a new design that introduces a full custom CAM cell and takes advantage of 65 nm technology. The customized design maximizes the pattern density, minimizes the power consumption and implements the functionalities needed for the planned Fast Tracker (FTK) [2], an ATLAS trigger upgrade project at LHC. We introduce a new variable resolution patt...

  5. Expert System Constant False Alarm Rate (CFAR) Processor

    National Research Council Canada - National Science Library

    Wicks, Michael C

    2006-01-01

    An artificial intelligence system improves radar signal processor performance by increasing target probability of detection and reducing probability of false alarm in a severe radar clutter environment...

  6. Special processor for in-core control systems

    International Nuclear Information System (INIS)

    Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

    1978-01-01

    The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

  7. Development of level 2 processor for the readout of TMC

    International Nuclear Information System (INIS)

    Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

    1995-01-01

    We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

  8. The ATLAS muon trigger: Experience and performance in the first 3 years of LHC pp runs

    International Nuclear Information System (INIS)

    Ventura, Andrea

    2013-01-01

    The ATLAS experiment at CERN's Large Hadron Collider (LHC) deploys a three-level processing scheme for the trigger system. The Level-1 muon trigger system gets its input from fast muon trigger detectors. Sector logic boards select muon candidates, which are passed via an interface board to the central trigger processor and then to the High Level Trigger (HLT). The muon HLT is purely software based and encompasses a Level-2 trigger followed by an event filter for a staged trigger approach. It has access to the data of the precision muon detectors and other detector elements to refine the muon hypothesis. The ATLAS experiment has taken data with high efficiency continuously over entire running periods from 2010 to 2012, for which sophisticated triggers to guard the highest physics output while reducing effectively the event rate were mandatory. The ATLAS muon trigger has successfully adapted to this challenging environment. The selection strategy has been optimized for the various physics analyses involving muons in the final state. This work briefly summarizes these three years of experience in the ATLAS muon trigger and reports about efficiency, resolution, and general performance of the muon trigger

  9. The ATLAS Tau Trigger

    CERN Document Server

    Dam, M; The ATLAS collaboration

    2009-01-01

    The ATLAS experiment at CERN’s LHC has implemented a dedicated tau trigger system to select hadronically decaying tau leptons from the enormous background of QCD jets. This promises a significant increase in the discovery potential to the Higgs boson and in searches for physics beyond the Standard Model. The three level trigger system has been optimised for effciency and good background rejection. The first level uses information from the calorimeters only, while the two higher levels include also information from the tracking detectors. Shower shape variables and the track multiplicity are important variables to distinguish taus from QCD jets. At the initial lumonosity of 10^31 cm^−2 s^−1, single tau triggers with a transverse energy threshold of 50 GeV or higher can be run standalone. Below this level, the tau signatures will be combined with other event signature

  10. The ATLAS Tau Trigger

    CERN Document Server

    Rados, PK; The ATLAS collaboration

    2014-01-01

    Physics processes involving tau leptons play a crucial role in understanding particle physics at the high energy frontier. The ability to efficiently trigger on events containing hadronic tau decays is therefore of particular importance to the ATLAS experiment. During the 2012 run, the Large Hadronic Collder (LHC) reached instantaneous luminosities of nearly $10^{34} cm^{-2}s^{-1}$ with bunch crossings occurring every $50 ns$. This resulted in a huge event rate and a high probability of overlapping interactions per bunch crossing (pile-up). With this in mind it was necessary to design an ATLAS tau trigger system that could reduce the event rate to a manageable level, while efficiently extracting the most interesting physics events in a pile-up robust manner. In this poster the ATLAS tau trigger is described, its performance during 2012 is presented, and the outlook for the LHC Run II is briefly summarized.

  11. ALICE High Level Trigger

    CERN Multimedia

    Alt, T

    2013-01-01

    The ALICE High Level Trigger (HLT) is a computing farm designed and build for the real-time, online processing of the raw data produced by the ALICE detectors. Events are fully reconstructed from the raw data, analyzed and compressed. The analysis summary together with the compressed data and a trigger decision is sent to the DAQ. In addition the reconstruction of the events allows for on-line monitoring of physical observables and this information is provided to the Data Quality Monitor (DQM). The HLT can process event rates of up to 2 kHz for proton-proton and 200 Hz for Pb-Pb central collisions.

  12. The charged particle trigger of the CELLO-detector

    International Nuclear Information System (INIS)

    Schroeder, V.

    1981-01-01

    The fast charged particle trigger of the CELLO-detector at the PETRA e + e - storage ring (DESY) is a fast software programmable hardware processor. It is using multiwire chamber signals as inputs and takes a decision on charged tracks coming from the interaction region in less than 1 μsec. The input signals are addressing Random Access Memory devices in which the mask schemes of all meaningful physical tracks are stored. The RAM output signals give information about the numbers and shapes of the valid masks found. This information is used for fast event acquisition and online data analysis done by a PDP 11 computer. (orig.)

  13. The JET fast central acquisition and trigger system

    International Nuclear Information System (INIS)

    Blackler, K.; Edwards, A.W.

    1994-01-01

    This paper describes a new data acquisition system at JET which uses Texas TMS320C40 parallel digital signal processors and the HELIOS parallel operating system to reduce the large amounts of experimental data produced by fast diagnostics. This unified system features a two level trigger system which performs real-time activity detection together with asynchronous event classification and selection. This provides automated data reduction during an experiment. The system's application to future fusion machines which have almost continuous operation is discussed

  14. The STAR trigger

    International Nuclear Information System (INIS)

    Bieser, F.S.; Crawford, H.J.; Engelage, J.; Eppley, G.; Greiner, L.C.; Judd, E.G.; Klein, S.R.; Meissner, F.; Minor, R.; Milosevich, Z.; Mutchler, G.; Nelson, J.M.; Schambach, J.; VanderMolen, A.S.; Ward, H.; Yepes, P.

    2003-01-01

    We describe the trigger system that we designed and implemented for the STAR detector at RHIC. This is a 10 MHz pipelined system based on fast detector output that controls the event selection for the much slower tracking detectors. Results from the first run are presented and new detectors for the 2001 run are discussed

  15. Asthma Triggers: Gain Control

    Science.gov (United States)

    ... harm people too. Try to use pest management methods that pose less of a risk. Keep counters, sinks, tables and floors clean and ... with pest challenges in your home and other environments. [EPA ... pests while reducing pesticide risks; roaches are often asthma triggers and shouldn’t ...

  16. Physics issues on triggering

    Indian Academy of Sciences (India)

    The detectors at the ILC are planned to run without hardware trigger. The ... as not coming from the interaction point and not matching to the silicon detectors ... electrons so that additional dE/dx cuts can help, making also here a factor 10 or.

  17. AIDS radio triggers.

    Science.gov (United States)

    Elias, A M

    1991-07-01

    In April 1991, the Ethnic Communities' Council of NSW was granted funding under the Community AIDS Prevention and Education Program through the Department of Community Services and Health, to produce a series of 6x50 second AIDS radio triggers with a 10-second tag line for further information. The triggers are designed to disseminate culturally-sensitive information about HIV/AIDS in English, Italian, Greek, Spanish, Khmer, Turkish, Macedonian, Serbo-Croatian, Arabic, Cantonese, and Vietnamese, with the goal of increasing awareness and decreasing the degree of misinformation about HIV/AIDS among people of non-English-speaking backgrounds through radio and sound. The 6 triggers cover the denial that AIDS exists in the community, beliefs that words and feelings do not protect one from catching HIV, encouraging friends to be compassionate, compassion within the family, AIDS information for a young audience, and the provision of accurate and honest information on HIV/AIDS. The triggers are slated to be completed by the end of July 1991 and will be broadcast on all possible community, ethnic, and commercial radio networks across Australia. They will be available upon request in composite form with an information kit for use by health care professionals and community workers.

  18. Dealing with Asthma Triggers

    Science.gov (United States)

    ... one trigger that you shouldn't avoid because exercise is important for your health. Your doctor will want you to be active, so talk with him or her about what to do before playing ... or 15 minutes before you exercise or play sports. And, of course, you'll ...

  19. Trigger Finger (Stenosing Tenosynovitis)

    Science.gov (United States)

    ... All Topics A-Z Videos Infographics Symptom Picker Anatomy Bones Joints Muscles Nerves Vessels Tendons About Hand Surgery What is a Hand Surgeon? What is a Hand Therapist? Media Find a Hand Surgeon Home Anatomy Trigger Finger Email to a friend * required fields ...

  20. The Fast Tracker Real Time Processor

    CERN Document Server

    Annovi, A; The ATLAS collaboration

    2011-01-01

    As the LHC luminosity is ramped up to the SLHC Phase I level and beyond, the high rates, multiplicities, and energies of particles seen by the detectors will pose a unique challenge. Only a tiny fraction of the produced collisions can be stored on tape and immense real-time data reduction is needed. An effective trigger system must maintain high trigger efficiencies for the physics we are most interested in, and at the same time suppress the enormous QCD backgrounds. This requires massive computing power to minimize the online execution time of complex algorithms. A multi-level trigger is an effective solution for an otherwise impossible problem. The Fast Tracker (FTK)[1], is a proposed upgrade to the current ATLAS trigger system that will operate at full Level-1 output rates and provide high quality tracks reconstructed over the entire detector by the start of processing in Level-2. FTK solves the combinatorial challenge inherent to tracking by exploiting massive parallelism of associative memories [2] that ...

  1. Aspects of computation on asynchronous parallel processors

    International Nuclear Information System (INIS)

    Wright, M.

    1989-01-01

    The increasing availability of asynchronous parallel processors has provided opportunities for original and useful work in scientific computing. However, the field of parallel computing is still in a highly volatile state, and researchers display a wide range of opinion about many fundamental questions such as models of parallelism, approaches for detecting and analyzing parallelism of algorithms, and tools that allow software developers and users to make effective use of diverse forms of complex hardware. This volume collects the work of researchers specializing in different aspects of parallel computing, who met to discuss the framework and the mechanics of numerical computing. The far-reaching impact of high-performance asynchronous systems is reflected in the wide variety of topics, which include scientific applications (e.g. linear algebra, lattice gauge simulation, ordinary and partial differential equations), models of parallelism, parallel language features, task scheduling, automatic parallelization techniques, tools for algorithm development in parallel environments, and system design issues

  2. Efficient quantum walk on a quantum processor

    Science.gov (United States)

    Qiang, Xiaogang; Loke, Thomas; Montanaro, Ashley; Aungskunsiri, Kanin; Zhou, Xiaoqi; O'Brien, Jeremy L.; Wang, Jingbo B.; Matthews, Jonathan C. F.

    2016-01-01

    The random walk formalism is used across a wide range of applications, from modelling share prices to predicting population genetics. Likewise, quantum walks have shown much potential as a framework for developing new quantum algorithms. Here we present explicit efficient quantum circuits for implementing continuous-time quantum walks on the circulant class of graphs. These circuits allow us to sample from the output probability distributions of quantum walks on circulant graphs efficiently. We also show that solving the same sampling problem for arbitrary circulant quantum circuits is intractable for a classical computer, assuming conjectures from computational complexity theory. This is a new link between continuous-time quantum walks and computational complexity theory and it indicates a family of tasks that could ultimately demonstrate quantum supremacy over classical computers. As a proof of principle, we experimentally implement the proposed quantum circuit on an example circulant graph using a two-qubit photonics quantum processor. PMID:27146471

  3. Processor-in-memory-and-storage architecture

    Science.gov (United States)

    DeBenedictis, Erik

    2018-01-02

    A method and apparatus for performing reliable general-purpose computing. Each sub-core of a plurality of sub-cores of a processor core processes a same instruction at a same time. A code analyzer receives a plurality of residues that represents a code word corresponding to the same instruction and an indication of whether the code word is a memory address code or a data code from the plurality of sub-cores. The code analyzer determines whether the plurality of residues are consistent or inconsistent. The code analyzer and the plurality of sub-cores perform a set of operations based on whether the code word is a memory address code or a data code and a determination of whether the plurality of residues are consistent or inconsistent.

  4. Optimal processor for malfunction detection in operating nuclear reactor

    International Nuclear Information System (INIS)

    Ciftcioglu, O.

    1990-01-01

    An optimal processor for diagnosing operational transients in a nuclear reactor is described. Basic design of the processor involves real-time processing of noise signal obtained from a particular in core sensor and the optimality is based on minimum alarm failure in contrast to minimum false alarm criterion from the safe and reliable plant operation viewpoint

  5. Sojourn time tails in processor-sharing systems

    NARCIS (Netherlands)

    Egorova, R.R.

    2009-01-01

    The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

  6. ACP/R3000 processors in data acquisition systems

    International Nuclear Information System (INIS)

    Deppe, J.; Areti, H.; Atac, R.

    1989-02-01

    We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

  7. On the effective parallel programming of multi-core processors

    NARCIS (Netherlands)

    Varbanescu, A.L.

    2010-01-01

    Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

  8. Bank switched memory interface for an image processor

    International Nuclear Information System (INIS)

    Barron, M.; Downward, J.

    1980-09-01

    A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

  9. Digital image processing software system using an array processor

    International Nuclear Information System (INIS)

    Sherwood, R.J.; Portnoff, M.R.; Journeay, C.H.; Twogood, R.E.

    1981-01-01

    A versatile array processor-based system for general-purpose image processing was developed. At the heart of this system is an extensive, flexible software package that incorporates the array processor for effective interactive image processing. The software system is described in detail, and its application to a diverse set of applications at LLNL is briefly discussed. 4 figures, 1 table

  10. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  11. Biomass is beginning to threaten the wood-processors

    International Nuclear Information System (INIS)

    Beer, G.; Sobinkovic, B.

    2004-01-01

    In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

  12. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  13. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  14. Recursive Matrix Inverse Update On An Optical Processor

    Science.gov (United States)

    Casasent, David P.; Baranoski, Edward J.

    1988-02-01

    A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

  15. Performance of the ATLAS first-level Trigger with first LHC Data

    CERN Document Server

    Lundberg, J; The ATLAS collaboration

    2010-01-01

    ATLAS is one of the two general-purpose detectors at the Large Hadron Collider (LHC). Its trigger system must reduce the anticipated proton collision rate of up to 40 MHz to a recordable event rate of 100-200 Hz. This is realized through a multi-level trigger system. The first-level trigger is implemented with custom-built electronics and makes an initial selection which reduces the rate to less than 100 kHz. The subsequent trigger selection is done in software run on PC farms. The first-level trigger decision is made by the central-trigger processor using information from coarse grained calorimeter information, dedicated muon-trigger detectors, and a variety of additional trigger inputs from detectors in the forward regions. We present the performance of the first-level trigger during the commissioning of the ATLAS detector during early LHC running. We cover the trigger strategies used during the different machine commissioning phases from first circulating beams and splash events to collisions. It is descri...

  16. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  17. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  18. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  19. Experimental testing of the noise-canceling processor.

    Science.gov (United States)

    Collins, Michael D; Baer, Ralph N; Simpson, Harry J

    2011-09-01

    Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

  20. Simulation of a processor switching circuit with APLSV

    International Nuclear Information System (INIS)

    Dilcher, H.

    1979-01-01

    The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de