Precise linear gating circuit on integrated microcircuits
Energy Technology Data Exchange (ETDEWEB)
Butskii, V.V.; Vetokhin, S.S.; Reznikov, I.V.
Precise linear gating circuit on four microcircuits is described. A basic flowsheet of the gating circuit is given. The gating circuit consists of two input differential cascades total load of which is two current followers possessing low input and high output resistances. Follower outlets are connected to high ohmic dynamic load formed with a current source which permits to get high amplification (>1000) at one cascade. Nonlinearity amounts to <0.1% in the range of input signal amplitudes of -10-+10 V. Front duration for an output signal with 10 V amplitude amounts to 100 ns. Attenuation of input signal with a closed gating circuit is 60 db. The gating circuits described is used in the device intended for processing of scintillation sensor signals.
International Nuclear Information System (INIS)
Suwono.
1978-01-01
A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)
Linear gate with prescaled window
Energy Technology Data Exchange (ETDEWEB)
Koch, J; Bissem, H H; Krause, H; Scobel, W [Hamburg Univ. (Germany, F.R.). 1. Inst. fuer Experimentalphysik
1978-07-15
An electronic circuit is described that combines the features of a linear gate, a single channel analyzer and a prescaler. It allows selection of a pulse height region between two adjustable thresholds and scales the intensity of the spectrum within this window down by a factor 2sup(N) (0<=N<=9), whereas the complementary part of the spectrum is transmitted without being affected.
Carr, Joseph
1996-01-01
The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa
Bradley, William; Bird, Ross; Eldred, Dennis; Zook, Jon; Knowles, Gareth
2013-01-01
This work involved developing spacequalifiable switch mode DC/DC power supplies that improve performance with fewer components, and result in elimination of digital components and reduction in magnetics. This design is for missions where systems may be operating under extreme conditions, especially at elevated temperature levels from 200 to 300 degC. Prior art for radiation-tolerant DC/DC converters has been accomplished utilizing classical magnetic-based switch mode converter topologies; however, this requires specific shielding and component de-rating to meet the high-reliability specifications. It requires complex measurement and feedback components, and will not enable automatic re-optimization for larger changes in voltage supply or electrical loading condition. The innovation is a switch mode DC/DC power supply that eliminates the need for processors and most magnetics. It can provide a well-regulated voltage supply with a gain of 1:100 step-up to 8:1 step down, tolerating an up to 30% fluctuation of the voltage supply parameters. The circuit incorporates a ceramic core transformer in a manner that enables it to provide a well-regulated voltage output without use of any processor components or magnetic transformers. The circuit adjusts its internal parameters to re-optimize its performance for changes in supply voltage, environmental conditions, or electrical loading at the output
Four-gate transistor analog multiplier circuit
Mojarradi, Mohammad M. (Inventor); Blalock, Benjamin (Inventor); Cristoloveanu, Sorin (Inventor); Chen, Suheng (Inventor); Akarvardar, Kerem (Inventor)
2011-01-01
A differential output analog multiplier circuit utilizing four G.sup.4-FETs, each source connected to a current source. The four G.sup.4-FETs may be grouped into two pairs of two G.sup.4-FETs each, where one pair has its drains connected to a load, and the other par has its drains connected to another load. The differential output voltage is taken at the two loads. In one embodiment, for each G.sup.4-FET, the first and second junction gates are each connected together, where a first input voltage is applied to the front gates of each pair, and a second input voltage is applied to the first junction gates of each pair. Other embodiments are described and claimed.
Synthesis of multivalued quantum logic circuits by elementary gates
Di, Yao-Min; Wei, Hai-Rui
2013-01-01
We propose the generalized controlled X (gcx) gate as the two-qudit elementary gate, and based on Cartan decomposition, we also give the one-qudit elementary gates. Then we discuss the physical implementation of these elementary gates and show that it is feasible with current technology. With these elementary gates many important qudit quantum gates can be synthesized conveniently. We provide efficient methods for the synthesis of various kinds of controlled qudit gates and greatly simplify the synthesis of existing generic multi-valued quantum circuits. Moreover, we generalize the quantum Shannon decomposition (QSD), the most powerful technique for the synthesis of generic qubit circuits, to the qudit case. A comparison of ququart (d=4) circuits and qubit circuits reveals that using ququart circuits may have an advantage over the qubit circuits in the synthesis of quantum circuits.
A gate drive circuit for gate-turn-off (GTO) devices in series stack
International Nuclear Information System (INIS)
Despe, O.
1999-01-01
A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements
Voltage linear transformation circuit design
Sanchez, Lucas R. W.; Jin, Moon-Seob; Scott, R. Phillip; Luder, Ryan J.; Hart, Michael
2017-09-01
Many engineering projects require automated control of analog voltages over a specified range. We have developed a computer interface comprising custom hardware and MATLAB code to provide real-time control of a Thorlabs adaptive optics (AO) kit. The hardware interface includes an op amp cascade to linearly shift and scale a voltage range. With easy modifications, any linear transformation can be accommodated. In AO applications, the design is suitable to drive a range of different types of deformable and fast steering mirrors (FSM's). Our original motivation and application was to control an Optics in Motion (OIM) FSM which requires the customer to devise a unique interface to supply voltages to the mirror controller to set the mirror's angular deflection. The FSM is in an optical servo loop with a wave front sensor (WFS), which controls the dynamic behavior of the mirror's deflection. The code acquires wavefront data from the WFS and fits a plane, which is subsequently converted into its corresponding angular deflection. The FSM provides +/-3° optical angular deflection for a +/-10 V voltage swing. Voltages are applied to the mirror via a National Instruments digital-to-analog converter (DAC) followed by an op amp cascade circuit. This system has been integrated into our Thorlabs AO testbed which currently runs at 11 Hz, but with planned software upgrades, the system update rate is expected to improve to 500 Hz. To show that the FSM subsystem is ready for this speed, we conducted two different PID tuning runs at different step commands. Once 500 Hz is achieved, we plan to make the code and method for our interface solution freely available to the community.
Enhancement of Linear Circuit Program
DEFF Research Database (Denmark)
Gaunholt, Hans; Dabu, Mihaela; Beldiman, Octavian
1996-01-01
In this report a preliminary user friendly interface has been added to the LCP2 program making it possible to describe an electronic circuit by actually drawing the circuit on the screen. Component values and other options and parameters can easily be set by the aid of the interface. The interface...
The analysis and design of linear circuits
Thomas, Roland E; Toussaint, Gregory J
2009-01-01
The Analysis and Design of Linear Circuits, 6e gives the reader the opportunity to not only analyze, but also design and evaluate linear circuits as early as possible. The text's abundance of problems, applications, pedagogical tools, and realistic examples helps engineers develop the skills needed to solve problems, design practical alternatives, and choose the best design from several competing solutions. Engineers searching for an accessible introduction to resistance circuits will benefit from this book that emphasizes the early development of engineering judgment.
Reconfigurable chaotic logic gates based on novel chaotic circuit
International Nuclear Information System (INIS)
Behnia, S.; Pazhotan, Z.; Ezzati, N.; Akhshani, A.
2014-01-01
Highlights: • A novel method for implementing logic gates based on chaotic maps is introduced. • The logic gates can be implemented without any changes in the threshold voltage. • The chaos-based logic gates may serve as basic components of future computing devices. - Abstract: The logical operations are one of the key issues in today’s computer architecture. Nowadays, there is a great interest in developing alternative ways to get the logic operations by chaos computing. In this paper, a novel implementation method of reconfigurable logic gates based on one-parameter families of chaotic maps is introduced. The special behavior of these chaotic maps can be utilized to provide same threshold voltage for all logic gates. However, there is a wide interval for choosing a control parameter for all reconfigurable logic gates. Furthermore, an experimental implementation of this nonlinear system is presented to demonstrate the robustness of computing capability of chaotic circuits
Logic-type Schmitt circuit using multi-valued gates
Wakui, M.; Tanaka, M.
Logic-type Schmitt circuits (LTSCs) proposed in this paper by author's proposal are a new detector for a multi-valued multi-threshold logic circuit, and it realizes the high resolution with a little hysteresis or the high noise margin. The detector consists of the combinations of the multi-valued gates (MVGs) and a positive reaction device (PRD), and each circuit can be realized by the conventional elements. This paper shows their practical circuits, and describes the regions and the conditions for their operation.
Modeling digital switching circuits with linear algebra
Thornton, Mitchell A
2014-01-01
Modeling Digital Switching Circuits with Linear Algebra describes an approach for modeling digital information and circuitry that is an alternative to Boolean algebra. While the Boolean algebraic model has been wildly successful and is responsible for many advances in modern information technology, the approach described in this book offers new insight and different ways of solving problems. Modeling the bit as a vector instead of a scalar value in the set {0, 1} allows digital circuits to be characterized with transfer functions in the form of a linear transformation matrix. The use of transf
Experimental investigation of a four-qubit linear-optical quantum logic circuit.
Stárek, R; Mičuda, M; Miková, M; Straka, I; Dušek, M; Ježek, M; Fiurášek, J
2016-09-20
We experimentally demonstrate and characterize a four-qubit linear-optical quantum logic circuit. Our robust and versatile scheme exploits encoding of two qubits into polarization and path degrees of single photons and involves two crossed inherently stable interferometers. This approach allows us to design a complex quantum logic circuit that combines a genuine four-qubit C(3)Z gate and several two-qubit and single-qubit gates. The C(3)Z gate introduces a sign flip if and only if all four qubits are in the computational state |1〉. We verify high-fidelity performance of this central four-qubit gate using Hofmann bounds on quantum gate fidelity and Monte Carlo fidelity sampling. We also experimentally demonstrate that the quantum logic circuit can generate genuine multipartite entanglement and we certify the entanglement with the use of suitably tailored entanglement witnesses.
International Nuclear Information System (INIS)
Ji, In-Hwan; Choi, Young-Hwan; Ha, Min-Woo; Han, Min-Koo; Choi, Yearn-Ik
2006-01-01
A new protection circuit employing the collector to emitter voltage (V CE ) sensing scheme for short-circuit withstanding capability of the insulated gate bipolar transistor (IGBT) is proposed and verified by experimental results. Because the current path between the gate and collector can be successfully eliminated in the proposed protection circuit, the power consumption can be reduced and the gate input impedance can be increased. Previous study is limited to dc characteristics. However, experimental results show that the proposed protection circuit successfully reduces the over-current of main IGBT by 80.4% under the short-circuit condition
A logic circuit for solving linear function by digital method
International Nuclear Information System (INIS)
Ma Yonghe
1986-01-01
A mathematical method for determining the linear relation of physical quantity with rediation intensity is described. A logic circuit has been designed for solving linear function by digital method. Some applications and the circuit function are discussed
Effective dark count rate reduction by modified SPAD gating circuit
Energy Technology Data Exchange (ETDEWEB)
Prochazka, Ivan; Blazej, Josef, E-mail: blazej@fjfi.cvut.cz; Kodet, Jan
2015-07-01
For our main application of single photon counting avalanche detectors in focus – laser ranging of space objects and laser time transfer – the ultimate requirements are relatively large and homogeneous active area having a diameter of 100 to 200 µm and a sub-picosecond stability of timing. The detector dark count rate and after-pulsing probability are parameters of relatively lower, but not negligible importance. In presented paper we will focused on them. We have developed a new active quenching and gating scheme which can reduce afterpulsing effect and hence also effective dark count rate at lower temperature. In satellite laser ranging system the effective dark count rate was reduced more than 35 times. This improvement will contribute in increasing the data yield and hence to increase precision and productivity. - Highlights: • Signal and quenching path in a control circuit stayed unaffected by gating. • The detector package optimized for laser time transfer systems is considered. • After-pulsing effect is reduced by a modification of the use of gate signal. • The dark count rate is reduced for gate rates of the order of units of kHz.
Substitution of cobalt alloying in PWR primary circuit gate valves
International Nuclear Information System (INIS)
Cachon, L.; Sudreau, F.; Brunel, L.
1995-01-01
The object of this study is qualify cobalt-free alternative alloys for valve applications. This paper focus on tribological characterization of numerous coatings is done by using the first one, of a classical type. Then tests are performed with the second one which simulates solicitations supported by gate valves in primary circuit of PWR. 35% Ni-Cr - 65% Cr 3 C 2 coating, deposited by detonation gun technology, gives us hope to find a substitute of Stelite 6. (author). 5 refs., 16 figs., 2 tabs
A circuit design for multi-inputs stateful OR gate
Energy Technology Data Exchange (ETDEWEB)
Chen, Qiao; Wang, Xiaoping, E-mail: wangxiaoping@hust.edu.cn; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-09-07
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
A circuit design for multi-inputs stateful OR gate
International Nuclear Information System (INIS)
Chen, Qiao; Wang, Xiaoping; Wan, Haibo; Yang, Ran; Zheng, Jian
2016-01-01
The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.
Visual construction of characteristic equations of linear electric circuits
Directory of Open Access Journals (Sweden)
V.V. Kostyukov
2013-12-01
Full Text Available A visual identification method with application of partial circuits is developed for characteristic equation coefficients of transients in linear electric circuits. The method is based on interrelationship between the roots of algebraic polynomial and its coefficients. The method is illustrated with an example of a third-order linear electric circuit.
On Multiplicative Linear Logic, Modality and Quantum Circuits
Directory of Open Access Journals (Sweden)
Ugo Dal Lago
2012-10-01
Full Text Available A logical system derived from linear logic and called QMLL is introduced and shown able to capture all unitary quantum circuits. Conversely, any proof is shown to compute, through a concrete GoI interpretation, some quantum circuits. The system QMLL, which enjoys cut-elimination, is obtained by endowing multiplicative linear logic with a quantum modality.
Entangling efficiency of linear-optical quantum gates
Czech Academy of Sciences Publication Activity Database
Lemr, Karel; Černoch, Antonín; Soubusta, Jan; Dušek, M.
2012-01-01
Roč. 86, č. 3 (2012), "032321-1"-"032321-5" ISSN 1050-2947 R&D Projects: GA ČR GAP205/12/0382 Institutional research plan: CEZ:AV0Z10100522 Keywords : linear-optical quantum gates * quantum physics Subject RIV: BH - Optics, Masers, Lasers Impact factor: 3.042, year: 2012 http://pra.aps.org/pdf/PRA/v86/i3/e032321
Linear circuit transfer functions an introduction to fast analytical techniques
Basso, Christophe P
2016-01-01
Linear Circuit Transfer Functions: An introduction to Fast Analytical Techniques teaches readers how to determine transfer functions of linear passive and active circuits by applying Fast Analytical Circuits Techniques. Building on their existing knowledge of classical loop/nodal analysis, the book improves and expands their skills to unveil transfer functions in a swift and efficient manner. Starting with simple examples, the author explains step-by-step how expressing circuits time constants in different configurations leads to writing transfer functions in a compact and insightful way. By learning how to organize numerators and denominators in the fastest possible way, readers will speed-up analysis and predict the frequency resp nse of simple to complex circuits. In some cases, they will be able to derive the final expression by inspection, without writing a line of algebra. Key features: * Emphasizes analysis through employing time constant-based methods discussed in other text books but not widely us...
Lower Bounds for Circuits with Few Modular Gates using Exponential Sums
DEFF Research Database (Denmark)
Hansen, Kristoffer Arnsfelt
2006-01-01
We prove that any AC0 circuit augmented with {epsilon log2 n} MODm gates and with a MAJORITY gate at the output, require size nOmega(log n) to compute MODl, when l has a prime factor not dividing m and epsilon is sufficiently small. We also obtain that the MOD2 function is hard on the average for...... gates. Our results are based on recent bounds of exponential sums that were previously introduced for proving lower bounds for MAJ o MODm o ANDd circuits....
Zhang, Lina; Zhang, Hui; Liu, Mei; Dong, Bin
2016-06-22
In this paper, we report a polymer-based raspberry-like micromotor. Interestingly, the resulting micromotor exhibits multistimuli-responsive motion behavior. Its on-off-on motion can be regulated by the application of stimuli such as H2O2, near-infrared light, NH3, or their combinations. Because of the versatility in motion control, the current micromotor has great potential in the application field of logic gate and logic circuit. With use of different stimuli as the inputs and the micromotor motion as the output, reprogrammable OR and INHIBIT logic gates or logic circuit consisting of OR, NOT, and AND logic gates can be achieved.
Robustness of MW-Level IGBT modules against gate oscillations under short circuit events
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Wu, Rui; Iannuzzo, Francesco
2015-01-01
The susceptibility of MW-level IGBT power modules to critical gate voltage oscillations during short circuit events has been evidenced experimentally. This paper proposes a sensitivity analysis method to better understand the oscillating behavior dependence on different operating conditions (i...... the oscillation phenomenon, as well as to further improve the device performance during short circuit....
Behavioral modeling of the dominant dynamics in input-output transfer of linear(ized) circuits
Beelen, T.G.J.; Maten, ter E.J.W.; Sihaloho, H.J.; Eijndhoven, van S.J.L.
2010-01-01
We present a powerful procedure for determining both the dominant dynamics of the inputoutput transfer and the corresponding most influential circuit parameters of a linear(ized) circuit. The procedure consists of several steps in which a specific (sub)problem is solved and its solution is used in
Linear circuit theory matrices in computer applications
Vlach, Jiri
2014-01-01
Basic ConceptsNodal and Mesh AnalysisMatrix MethodsDependent SourcesNetwork TransformationsCapacitors and InductorsNetworks with Capacitors and InductorsFrequency DomainLaplace TransformationTime DomainNetwork FunctionsActive NetworksTwo-PortsTransformersModeling and Numerical MethodsSensitivitiesModified Nodal FormulationFourier Series and TransformationAppendix: Scaling of Linear Networks.
Configurable unitary transformations and linear logic gates using quantum memories.
Campbell, G T; Pinel, O; Hosseini, M; Ralph, T C; Buchler, B C; Lam, P K
2014-08-08
We show that a set of optical memories can act as a configurable linear optical network operating on frequency-multiplexed optical states. Our protocol is applicable to any quantum memories that employ off-resonant Raman transitions to store optical information in atomic spins. In addition to the configurability, the protocol also offers favorable scaling with an increasing number of modes where N memories can be configured to implement arbitrary N-mode unitary operations during storage and readout. We demonstrate the versatility of this protocol by showing an example where cascaded memories are used to implement a conditional cz gate.
Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng
2017-09-01
Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.
Ripple gate drive circuit for fast operation of series connected IGBTs
Rockot, Joseph H.; Murray, Thomas W.; Bass, Kevin C.
2005-09-20
A ripple gate drive circuit includes a plurality of transistors having their power terminals connected in series across an electrical potential. A plurality of control circuits, each associated with one of the transistors, is provided. Each control circuit is responsive to a control signal and an optical signal received from at least one other control circuit for controlling the conduction of electrical current through the power terminals of the associated transistor. The control circuits are responsive to a first state of the control circuit for causing each transistor in series to turn on sequentially and responsive to a second state of the control signal for causing each transistor in series to turn off sequentially.
All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits
International Nuclear Information System (INIS)
Renteria, J.; Jiang, C.; Yan, Z.; Samnakay, R.; Goli, P.; Pope, T. R.; Salguero, T. T.; Wickramaratne, D.; Lake, R. K.; Khitun, A. G.; Balandin, A. A.
2014-01-01
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe 2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe 2 –Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials
All-metallic electrically gated 2H-TaSe2 thin-film switches and logic circuits
Renteria, J.; Samnakay, R.; Jiang, C.; Pope, T. R.; Goli, P.; Yan, Z.; Wickramaratne, D.; Salguero, T. T.; Khitun, A. G.; Lake, R. K.; Balandin, A. A.
2014-01-01
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe2 were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe2-Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.
All-metallic electrically gated 2H-TaSe{sub 2} thin-film switches and logic circuits
Energy Technology Data Exchange (ETDEWEB)
Renteria, J.; Jiang, C.; Yan, Z. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Samnakay, R.; Goli, P. [Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Pope, T. R.; Salguero, T. T. [Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States); Wickramaratne, D.; Lake, R. K. [Laboratory for Terascale and Terahertz Electronics, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Khitun, A. G. [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Materials Science and Engineering Program, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Balandin, A. A., E-mail: balandin@ee.ucr.edu [Nano-Device Laboratory, Department of Electrical Engineering, Bourns College of Engineering, University of California–Riverside, Riverside, California 92521 (United States); Department of Chemistry, University of Georgia, Athens, Georgia 30602 (United States)
2014-01-21
We report the fabrication and performance of all-metallic three-terminal devices with tantalum diselenide thin-film conducting channels. For this proof-of-concept demonstration, the layers of 2H-TaSe{sub 2} were exfoliated mechanically from single crystals grown by the chemical vapor transport method. Devices with nanometer-scale thicknesses exhibit strongly non-linear current-voltage characteristics, unusual optical response, and electrical gating at room temperature. We have found that the drain-source current in thin-film 2H-TaSe{sub 2}–Ti/Au devices reproducibly shows an abrupt transition from a highly resistive to a conductive state, with the threshold tunable via the gate voltage. Such current-voltage characteristics can be used, in principle, for implementing radiation-hard all-metallic logic circuits. These results may open new application space for thin films of van der Waals materials.
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.
2011-01-01
-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result
Single-flux-quantum logic circuits exploiting collision-based fusion gates
International Nuclear Information System (INIS)
Asai, T.; Yamada, K.; Amemiya, Y.
2008-01-01
We propose a single-flux-quantum (SFQ) logic circuit based on the fusion computing systems--collision-based and reaction-diffusion fusion computers. A fusion computing system consists of regularly arrayed unit cells (fusion gates), where each unit has two input arms and two output arms and is connected to its neighboring cells with the arms. We designed functional SFQ circuits that implemented the fusion computation. The unit cell was able to be made with ten Josephson junctions. Circuit simulation with standard Nb/Al-AlOx/Nb 2.5-kA/cm 2 process parameters showed that the SFQ fusion computing systems could operate at 10 GHz clock
Exact synthesis of three-qubit quantum circuits from non-binary quantum gates
Yang, Guowu; Hung, William N. N.; Song, Xiaoyu; Perkowski, Marek A.
2010-04-01
Because of recent nano-technological advances, nano-structured systems have become highly ordered, making it quantum computing schemas possible. We propose an approach to optimally synthesise quantum circuits from non-permutative quantum gates such as controlled-square-root-of-not (i.e., controlled-V). Our approach reduces the synthesis problem to multiple-valued optimisation and uses group theory. We devise a novel technique that transforms the quantum logic synthesis problem from a multi-valued constrained optimisation problem to a permutable representation. The transformation enables us to use group theory to exploit the symmetric properties of the synthesis problem. Assuming a cost of one for each two-qubit gate, we found all reversible circuits with quantum costs of 4, 5, 6, etc., and give another algorithm to realise these reversible circuits with quantum gates. The approach can be used for both binary permutative deterministic circuits and probabilistic circuits such as controlled random-number generators and hidden Markov models.
Single OR molecule and OR atomic circuit logic gates interconnected on a Si(100)H surface
International Nuclear Information System (INIS)
Ample, F; Joachim, C; Duchemin, I; Hliwa, M
2011-01-01
Electron transport calculations were carried out for three terminal OR logic gates constructed either with a single molecule or with a surface dangling bond circuit interconnected on a Si(100)H surface. The corresponding multi-electrode multi-channel scattering matrix (where the central three terminal junction OR gate is the scattering center) was calculated, taking into account the electronic structure of the supporting Si(100)H surface, the metallic interconnection nano-pads, the surface atomic wires and the molecule. Well interconnected, an optimized OR molecule can only run at a maximum of 10 nA output current intensity for a 0.5 V bias voltage. For the same voltage and with no molecule in the circuit, the output current of an OR surface atomic scale circuit can reach 4 μA.
Electrostatic Discharge Current Linear Approach and Circuit Design Method
Directory of Open Access Journals (Sweden)
Pavlos K. Katsivelis
2010-11-01
Full Text Available The Electrostatic Discharge phenomenon is a great threat to all electronic devices and ICs. An electric charge passing rapidly from a charged body to another can seriously harm the last one. However, there is a lack in a linear mathematical approach which will make it possible to design a circuit capable of producing such a sophisticated current waveform. The commonly accepted Electrostatic Discharge current waveform is the one set by the IEC 61000-4-2. However, the over-simplified circuit included in the same standard is incapable of producing such a waveform. Treating the Electrostatic Discharge current waveform of the IEC 61000-4-2 as reference, an approximation method, based on Prony’s method, is developed and applied in order to obtain a linear system’s response. Considering a known input, a method to design a circuit, able to generate this ESD current waveform in presented. The circuit synthesis assumes ideal active elements. A simulation is carried out using the PSpice software.
Instantaneous Switching Processes in Quasi-Linear Circuits
Directory of Open Access Journals (Sweden)
Rositsa Angelova
2004-01-01
Full Text Available The paper considers instantaneous processes in electrical circuits produced by the stepwise change of the capacitance of the capacitor and the inductance of the inductor and by the switching on and switching off of the circuit. In order to determine the set of electrical circuits, for which it is possible to explicitly obtain the values of the currents and the voltages at the end of the instantaneous process, a classification of the networks with nonlinear elements is introduced in the paper. The instantaneous switching process in the moment t0 is approximated when T->t0 with a sequence of processes in the interval [t0, T]. For quasi-linear inductive and capacitive circuits; we present the type of the system satisfied by the currents and the voltages, the charges, as well as the fluxes in the interval [t0, T]. From this system, after passage to the limit T->t0, we obtain the formulas for the values of the circuits at the end of the instantaneous process. The obtained results are applied for the analysis of particular processes.
Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications
International Nuclear Information System (INIS)
Zhuge, Jing; Huang, Ru; Wang, Yangyuan; Verhulst, Anne S; Vandenberghe, William G; Dehaene, Wim; Groeseneken, Guido
2011-01-01
This paper investigates the potential of tunnel field-effect transistors (TFETs), with emphasis on short-gate TFETs, by simulation for low-power digital applications having a supply voltage lower than 0.5 V. A transient study shows that the tunneling current has a negligible contribution in charging and discharging the gate capacitance of TFETs. In spite of a higher resistance region in the short-gate TFET, the gate (dis)charging speed still meets low-voltage application requirements. A circuit analysis is performed on short-gate TFETs with different materials, such as Si, Ge and heterostructures in terms of voltage overshoot, delay, static power, energy consumption and energy delay product (EDP). These results are compared to MOSFET and full-gate TFET performance. It is concluded that short-gate heterostructure TFETs (Ge–source for nTFET, In 0.6 Ga 0.4 As–source for pTFET) are promising candidates to extend the supply voltage to lower than 0.5 V because they combine the advantage of a low Miller capacitance, due to the short-gate structures, and strong drive current in TFETs, due to the narrow bandgap material in the source. At a supply voltage of 0.4 V and for an EOT and channel length of 0.6 nm and 40 nm, respectively, a three-stage inverter chain based on short-gate heterostructure TFETs saves 40% energy consumption per cycle at the same delay and shows 60%–75% improvement of EDP at the same static power, compared to its full-gate counterpart. When compared to the MOSFET, better EDP can be achieved in the heterostructure TFET especially at low static power consumption
Modeling and simulation of floating gate nanocrystal FET devices and circuits
Hasaneen, El-Sayed A. M.
The nonvolatile memory market has been growing very fast during the last decade, especially for mobile communication systems. The Semiconductor Industry Association International Technology Roadmap for Semiconductors states that the difficult challenge for nonvolatile semiconductor memories is to achieve reliable, low power, low voltage performance and high-speed write/erase. This can be achieved by aggressive scaling of the nonvolatile memory cells. Unfortunately, scaling down of conventional nonvolatile memory will further degrade the retention time due to the charge loss between the floating gate and drain/source contacts and substrate which makes conventional nonvolatile memory unattractive. Using nanocrystals as charge storage sites reduces dramatically the charge leakage through oxide defects and drain/source contacts. Floating gate nanocrystal nonvolatile memory, FG-NCNVM, is a candidate for future memory because it is advantageous in terms of high-speed write/erase, small size, good scalability, low-voltage, low-power applications, and the capability to store multiple bits per cell. Many studies regarding FG-NCNVMs have been published. Most of them have dealt with fabrication improvements of the devices and device characterizations. Due to the promising FG-NCNVM applications in integrated circuits, there is a need for circuit a simulation model to simulate the electrical characteristics of the floating gate devices. In this thesis, a FG-NCNVM circuit simulation model has been proposed. It is based on the SPICE BSIM simulation model. This model simulates the cell behavior during normal operation. Model validation results have been presented. The SPICE model shows good agreement with experimental results. Current-voltage characteristics, transconductance and unity gain frequency (fT) have been studied showing the effect of the threshold voltage shift (DeltaVth) due to nanocrystal charge on the device characteristics. The threshold voltage shift due to
Directory of Open Access Journals (Sweden)
Shikha Panwar
2014-01-01
Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.
Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits
Russinoff, David M.
1995-01-01
We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.
A low-cost universal cumulative gating circuit for small and large animal clinical imaging
Gioux, Sylvain; Frangioni, John V.
2008-02-01
Image-assisted diagnosis and therapy is becoming more commonplace in medicine. However, most imaging techniques suffer from voluntary or involuntary motion artifacts, especially cardiac and respiratory motions, which degrade image quality. Current software solutions either induce computational overhead or reject out-of-focus images after acquisition. In this study we demonstrate a hardware-only gating circuit that accepts multiple, pseudo-periodic signals and produces a single TTL (0-5 V) imaging window of accurate phase and period. The electronic circuit Gerber files described in this article and the list of components are available online at www.frangionilab.org.
Critical Gates Identification for Fault-Tolerant Design in Math Circuits
Directory of Open Access Journals (Sweden)
Tian Ban
2017-01-01
Full Text Available Hardware redundancy at different levels of design is a common fault mitigation technique, which is well known for its efficiency to the detriment of area overhead. In order to reduce this drawback, several fault-tolerant techniques have been proposed in literature to find a good trade-off. In this paper, critical constituent gates in math circuits are detected and graded based on the impact of an error in the output of a circuit. These critical gates should be hardened first under the area constraint of design criteria. Indeed, output bits considered crucial to a system receive higher priorities to be protected, reducing the occurrence of critical errors. The 74283 fast adder is used as an example to illustrate the feasibility and efficiency of the proposed approach.
T-gate aligned nanotube radio frequency transistors and circuits with superior performance.
Che, Yuchi; Lin, Yung-Chen; Kim, Pyojae; Zhou, Chongwu
2013-05-28
In this paper, we applied self-aligned T-gate design to aligned carbon nanotube array transistors and achieved an extrinsic current-gain cutoff frequency (ft) of 25 GHz, which is the best on-chip performance for nanotube radio frequency (RF) transistors reported to date. Meanwhile, an intrinsic current-gain cutoff frequency up to 102 GHz is obtained, comparable to the best value reported for nanotube RF transistors. Armed with the excellent extrinsic RF performance, we performed both single-tone and two-tone measurements for aligned nanotube transistors at a frequency up to 8 GHz. Furthermore, we utilized T-gate aligned nanotube transistors to construct mixing and frequency doubling analog circuits operated in gigahertz frequency regime. Our results confirm the great potential of nanotube-based circuit applications and indicate that nanotube transistors are promising building blocks in high-frequency electronics.
Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates
DEFF Research Database (Denmark)
Gal, A.; Hansen, Kristoffer Arnsfelt; Koucky, Michal
2013-01-01
We bound the minimum number w of wires needed to compute any (asymptotically good) error-correcting code C:{0,1}Ω(n)→{0,1}n with minimum distance Ω(n), using unbounded fan-in circuits of depth d with arbitrary gates. Our main results are: 1) if d=2, then w=Θ(n (lgn/lglgn)2); 2) if d=3, then w...
Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates
DEFF Research Database (Denmark)
Gál, Anna; Hansen, Kristoffer Arnsfelt; Koucký, Michal
2012-01-01
We bound the minimum number w of wires needed to compute any (asymptotically good) error-correcting code C:{0,1}Ω(n) -> {0,1}n with minimum distance Ω(n), using unbounded fan-in circuits of depth d with arbitrary gates. Our main results are: (1) If d=2 then w = Θ(n ({log n/ log log n})2). (2) If d...
Zhang, Tianhe C; Janik, John J; Peters, Ryan V; Chen, Gang; Ji, Ru-Rong; Grill, Warren M
2015-07-01
Spinal cord stimulation (SCS) is a therapy used to treat intractable pain with a putative mechanism of action based on the Gate Control Theory. We hypothesized that sensory projection neuron responses to SCS would follow a single stereotyped response curve as a function of SCS frequency, as predicted by the Gate Control circuit. We recorded the responses of antidromically identified sensory projection neurons in the lumbar spinal cord during 1- to 150-Hz SCS in both healthy rats and neuropathic rats following chronic constriction injury (CCI). The relationship between SCS frequency and projection neuron activity predicted by the Gate Control circuit accounted for a subset of neuronal responses to SCS but could not account for the full range of observed responses. Heterogeneous responses were classifiable into three additional groups and were reproduced using computational models of spinal microcircuits representing other interactions between nociceptive and nonnociceptive sensory inputs. Intrathecal administration of bicuculline, a GABAA receptor antagonist, increased spontaneous and evoked activity in projection neurons, enhanced excitatory responses to SCS, and reduced inhibitory responses to SCS, suggesting that GABAA neurotransmission plays a broad role in regulating projection neuron activity. These in vivo and computational results challenge the Gate Control Theory as the only mechanism underlying SCS and refine our understanding of the effects of SCS on spinal sensory neurons within the framework of contemporary understanding of dorsal horn circuitry. Copyright © 2015 the American Physiological Society.
International Nuclear Information System (INIS)
Kumar, Rohit; Ghosh, Bahniman; Gupta, Shoubhik
2015-01-01
This paper proposes a novel design paradigm for circuits designed in quantum dot cellular automata (QCA) technology. Previously reported QCA circuits in the literature have generally been designed in a single layer which is the main logical block in which the inverter and majority gate are on the base layer, except for the parts where multilayer wire crossing was used. In this paper the concept of multilayer wire crossing has been extended to design logic gates in multilayers. Using a 5-input majority gate in a multilayer, a 1-bit and 2-bit adder have been designed in the proposed multilayer gate design paradigm. A comparison has been made with some adders reported previously in the literature and it has been shown that circuits designed in the proposed design paradigm are much more efficient in terms of area, the requirement of QCA cells in the design and the input–output delay of the circuit. Over all, the availability of one additional spatial dimension makes the design process much more flexible and there is scope for the customizability of logic gate designs to make the circuit compact. (paper)
Experimental implementation of optimal linear-optical controlled-unitary gates
Czech Academy of Sciences Publication Activity Database
Lemr, K.; Bartkiewicz, K.; Černoch, Antonín; Dušek, M.; Soubusta, Jan
2015-01-01
Roč. 114, č. 15 (2015), "153602-1"-"153602-5" ISSN 0031-9007 R&D Projects: GA ČR GAP205/12/0382 Institutional support: RVO:68378271 Keywords : two-qubit gates * optimal linear-optical controlled-unitary gates * quantum computing Subject RIV: BH - Optics, Masers, Lasers Impact factor: 7.645, year: 2015
Azerbaijan Technical University’s Experience in Teaching Linear Electrical Circuit Theory
Directory of Open Access Journals (Sweden)
G. A. Mamedov
2006-01-01
Full Text Available An experience in teaching linear electrical circuit theory at the Azerbaijan Technical University is presented in the paper. The paper describes structure of the Linear Electrical Circuit Theory course worked out by the authors that contains a section on electrical calculation of track circuits, information on electro-magnetic compatibility and typical tests for better understanding of the studied subject.
From neurons to circuits: linear estimation of local field potentials
Rasch, Malte; Logthetis, Nikos K.; Kreiman, Gabriel
2010-01-01
Extracellular physiological recordings are typically separated into two frequency bands: local field potentials (LFPs, a circuit property) and spiking multi-unit activity (MUA). There has been increased interest in LFPs due to their correlation with fMRI measurements and the possibility of studying local processing and neuronal synchrony. To further understand the biophysical origin of LFPs, we asked whether it is possible to estimate their time course based on the spiking activity from the same or nearby electrodes. We used Signal Estimation Theory to show that a linear filter operation on the activity of one/few neurons can explain a significant fraction of the LFP time course in the macaque primary visual cortex. The linear filter used to estimate the LFPs had a stereotypical shape characterized by a sharp downstroke at negative time lags and a slower positive upstroke for positve time lags. The filter was similar across neocortical regions and behavioral conditions including spontaneous activity and visual stimulation. The estimations had a spatial resolution of ~1 mm and a temporal resolution of ~200 ms. By considering a causal filter, we observed a temporal asymmetry such that the positive time lags in the filter contributed more to the LFP estimation than negative time lags. Additionally, we showed that spikes occurring within ~10 ms of spikes from nearby neurons yielded better estimation accuracies than nonsynchronous spikes. In sum, our results suggest that at least some circuit-level local properties of the field potentials can be predicted from the activity of one or a few neurons. PMID:19889990
Experimental realization of linear-optical partial SWAP gates
Czech Academy of Sciences Publication Activity Database
Černoch, Antonín; Soubusta, Jan; Bartůšková, L.; Dušek, M.; Fiurášek, J.
2008-01-01
Roč. 100, č. 18 (2008), 180501/1-180501/4 ISSN 0031-9007 R&D Projects: GA MŠk(CZ) 1M06002 Institutional research plan: CEZ:AV0Z10100522 Keywords : two-qubit gates * Mach-Zehnder interferomeret * quantum information processing Subject RIV: BH - Optics, Masers, Lasers Impact factor: 7.180, year: 2008
Power gating of VLSI circuits using MEMS switches in low power applications
Shobak, Hosam
2011-12-01
Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.
Acousto-optic modulation and opto-acoustic gating in piezo-optomechanical circuits
Balram, Krishna C.; Davanço, Marcelo I.; Ilic, B. Robert; Kyhm, Ji-Hoon; Song, Jin Dong; Srinivasan, Kartik
2017-01-01
Acoustic wave devices provide a promising chip-scale platform for efficiently coupling radio frequency (RF) and optical fields. Here, we use an integrated piezo-optomechanical circuit platform that exploits both the piezoelectric and photoelastic coupling mechanisms to link 2.4 GHz RF waves to 194 THz (1550 nm) optical waves, through coupling to propagating and localized 2.4 GHz acoustic waves. We demonstrate acousto-optic modulation, resonant in both the optical and mechanical domains, in which waveforms encoded on the RF carrier are mapped to the optical field. We also show opto-acoustic gating, in which the application of modulated optical pulses interferometrically gates the transmission of propagating acoustic pulses. The time-domain characteristics of this system under both pulsed RF and pulsed optical excitation are considered in the context of the different physical pathways involved in driving the acoustic waves, and modelled through the coupled mode equations of cavity optomechanics. PMID:28580373
Cell-to-Cell Communication Circuits: Quantitative Analysis of Synthetic Logic Gates
Hoffman-Sommer, Marta; Supady, Adriana; Klipp, Edda
2012-01-01
One of the goals in the field of synthetic biology is the construction of cellular computation devices that could function in a manner similar to electronic circuits. To this end, attempts are made to create biological systems that function as logic gates. In this work we present a theoretical quantitative analysis of a synthetic cellular logic-gates system, which has been implemented in cells of the yeast Saccharomyces cerevisiae (Regot et al., 2011). It exploits endogenous MAP kinase signaling pathways. The novelty of the system lies in the compartmentalization of the circuit where all basic logic gates are implemented in independent single cells that can then be cultured together to perform complex logic functions. We have constructed kinetic models of the multicellular IDENTITY, NOT, OR, and IMPLIES logic gates, using both deterministic and stochastic frameworks. All necessary model parameters are taken from literature or estimated based on published kinetic data, in such a way that the resulting models correctly capture important dynamic features of the included mitogen-activated protein kinase pathways. We analyze the models in terms of parameter sensitivity and we discuss possible ways of optimizing the system, e.g., by tuning the culture density. We apply a stochastic modeling approach, which simulates the behavior of whole populations of cells and allows us to investigate the noise generated in the system; we find that the gene expression units are the major sources of noise. Finally, the model is used for the design of system modifications: we show how the current system could be transformed to operate on three discrete values. PMID:22934039
Multi-strategy based quantum cost reduction of linear nearest-neighbor quantum circuit
Tan, Ying-ying; Cheng, Xue-yun; Guan, Zhi-jin; Liu, Yang; Ma, Haiying
2018-03-01
With the development of reversible and quantum computing, study of reversible and quantum circuits has also developed rapidly. Due to physical constraints, most quantum circuits require quantum gates to interact on adjacent quantum bits. However, many existing quantum circuits nearest-neighbor have large quantum cost. Therefore, how to effectively reduce quantum cost is becoming a popular research topic. In this paper, we proposed multiple optimization strategies to reduce the quantum cost of the circuit, that is, we reduce quantum cost from MCT gates decomposition, nearest neighbor and circuit simplification, respectively. The experimental results show that the proposed strategies can effectively reduce the quantum cost, and the maximum optimization rate is 30.61% compared to the corresponding results.
Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator
Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok
2016-01-01
The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416
Rana, K. P. S.; Kumar, Vineet; Prasad, Tapan
2018-02-01
Temperature to Frequency Converters (TFCs) are potential signal conditioning circuits (SCCs) usually employed in temperature measurements using thermistors. A NE/SE-566 based SCC has been recently used in several reported works as TFC. Application of NE/SE-566 based SCC requires a mechanism for finding the optimal values of SCC parameters yielding the optimal linearity and desired sensitivity performances. Two classical methods, namely, inflection point and three point have been employed for this task. In this work, the application of these two methods, on NE/SE-566 based SCC in TFC, is investigated in detail and the conditions for its effective usage are developed. Further, since these classical methods offer an approximate linearization of temperature and frequency relationship an application of a linear search based technique is proposed to further enhance the linearity. The implemented linear search method used results obtained from the above mentioned classical methods. The presented simulation studies, for three different industrial grade thermistors, revealed that the linearity enhancements of 21.7, 18.3 and 17.8% can be achieved over the inflection point method and 4.9, 4.7 and 4.7% over the three point method, for an input temperature range of 0-100 °C.
Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.
Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao
2016-07-26
A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.
Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors
Directory of Open Access Journals (Sweden)
Zhen Li
2015-09-01
Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.
Prospects of luminescence based molecular scale logic gates and logic circuits
Energy Technology Data Exchange (ETDEWEB)
Speiser, Shammai, E-mail: speiser@technion.ac.il
2016-01-15
In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder.
Prospects of luminescence based molecular scale logic gates and logic circuits
International Nuclear Information System (INIS)
Speiser, Shammai
2016-01-01
In recent years molecular electronics has emerged as a rapidly growing research field. The aim of this review is to introduce this subject as a whole with special emphasis on molecular scale potential devices and applications. As a particular example we will discuss all optical molecular scale logic gates and logic circuits based on molecular fluorescence and electronic excitation transfer processes. Charge and electronic energy transfers (ET and EET) are well-studied examples whereby different molecules can signal their state from one (the donor, D) to the other (the acceptor, A). We show how a half-adder logic circuit can be implemented on one molecule that can communicate its logic output as input to another half-adder molecule. This is achieved as an electronic energy transfer from a donor to an acceptor, thus implementing a molecular full adder. We discuss a specific pair, the rhodamine–azulene, for which there is considerable spectroscopic data, but the scheme is general enough to allow a wide choice of D and A pairs. We present results based on this pair, in which, for the first time, an all optical half-adder and full-adder logic circuits are implemented. - Highlights: • Molecular scale logic • Photoquenching • Full adder
Shin, SeungJun; Yu, YunSeop; Choi, JungBum
2008-10-01
New multi-valued logic (MVL) families using the hybrid circuits consisting of three gates single-electron transistors (TG-SETs) and a metal-oxide-semiconductor field-effect transistor (MOSFET) are proposed. The use of SETs offers periodic literal characteristics due to Coulomb oscillation of SET, which allows a realization of binary logic (BL) circuits as well as multi-valued logic (MVL) circuits. The basic operations of the proposed MVL families are successfully confirmed through SPICE circuit simulation based on the physical device model of a TG-SET. The proposed MVL circuits are found to be much faster, but much larger power consumption than a previously reported MVL, and they have a trade-off between speed and power consumption. As an example to apply the newly developed MVL families, a half-adder is introduced.
International Nuclear Information System (INIS)
Laws, W.R.; Potter, D.W.; Sutherland, J.C.
1984-01-01
We have constructed a circuit that permits conventional timing electronics to be used in single photon-counting fluorimeters with high repetition rate excitation sources (synchrotrons and mode-locked lasers). Most commercial time-to-amplitude and time-to-digital converters introduce errors when processing very short time intervals and when subjected to high-frequency signals. This circuit reduces the frequency of signals representing the pulsed light source (stops) to the rate of detected fluorescence events (starts). Precise timing between the start/stop pair is accomplished by using the second stop pulse after a start pulse. Important features of our design are that the circuit is insensitive to the simultaneous occurrence of start and stop signals and that the reduction in the stop frequency allows the start/stop time interval to be placed in linear regions of the response functions of commercial timing electronics
Wide operating window spin-torque majority gate towards large-scale integration of logic circuits
Vaysset, Adrien; Zografos, Odysseas; Manfrini, Mauricio; Mocuta, Dan; Radu, Iuliana P.
2018-05-01
Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields.
International Nuclear Information System (INIS)
Zhu Chang-Hua; Cao Xin; Quan Dong-Xiao; Pei Chang-Xing
2014-01-01
Linear optical quantum Fredkin gate can be applied to quantum computing and quantum multi-user communication networks. In the existing linear optical scheme, two single photon detectors (SPDs) are used to herald the success of the quantum Fredkin gate while they have no photon count. But analysis results show that for non-perfect SPD, the lower the detector efficiency, the higher the heralded success rate by this scheme is. We propose an improved linear optical quantum Fredkin gate by designing a new heralding scheme with an auxiliary qubit and only one SPD, in which the higher the detection efficiency of the heralding detector, the higher the success rate of the gate is. The new heralding scheme can also work efficiently under a non-ideal single photon source. Based on this quantum Fredkin gate, large-scale quantum switching networks can be built. As an example, a quantum Beneš network is shown in which only one SPD is used. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)
Hek, A.P. de; Busking, E.B.
2006-01-01
In this paper the design and performance of an on-chip active gate bias circuit for application in MMIC amplifiers, which gives 100% compensation for threshold variation and at the same time is insensitive to supply voltage variations, is discussed. Design equations have been given. In addition, the
Passive linear-optics 640 Gbit/s logic NOT gate
DEFF Research Database (Denmark)
Maram, Reza; Kong, Deming; Galili, Michael
2015-01-01
We experimentally demonstrate a 640 Gbit/s all-optical NOT gate for high-speed telecommunication on-off-keying (OOK) data signals. We employ linear optical signal processing based on spectral phase-only (all-pass) optical filtering to perform the target logic NOT operation....
Towards MRI-guided linear accelerator control: gating on an MRI accelerator.
Crijns, S P M; Kok, J G M; Lagendijk, J J W; Raaymakers, B W
2011-08-07
To boost the possibilities of image guidance in radiotherapy by providing images with superior soft-tissue contrast during treatment, we pursue diagnostic quality MRI functionality integrated with a linear accelerator. Large respiration-induced semi-periodic target excursions hamper treatment of cancer of the abdominal organs. Methods to compensate in real time for such motion are gating and tracking. These strategies are most effective in cases where anatomic motion can be visualized directly, which supports the use of an integrated MRI accelerator. We establish here an infrastructure needed to realize gated radiation delivery based on MR feedback and demonstrate its potential as a first step towards more advanced image guidance techniques. The position of a phantom subjected to one-dimensional periodic translation is tracked with the MR scanner. Real-time communication with the MR scanner and control of the radiation beam are established. Based on the time-resolved position of the phantom, gated radiation delivery to the phantom is realized. Dose distributions for dynamic delivery conditions with varying gating windows are recorded on gafchromic film. The similarity between dynamically and statically obtained dose profiles gradually increases as the gating window is decreased. With gating windows of 5 mm, we obtain sharp dose profiles. We validate our gating implementation by comparing measured dose profiles to theoretical profiles calculated using the knowledge of the imposed motion pattern. Excellent correspondence is observed. At the same time, we show that real-time on-line reconstruction of the accumulated dose can be performed using time-resolved target position information. This facilitates plan adaptation not only on a fraction-to-fraction scale but also during one fraction, which is especially valuable in highly accelerated treatment strategies. With the currently established framework and upcoming improvements to our prototype-integrated MRI accelerator
Dadgour, Hamed F.
2010-01-01
Nano-Electro-Mechanical Switches (NEMS) offer the prospect of improved energy-efficiency in digital circuits due to their near-zero subthreshold leakage and extremely low subthreshold swing values. Among the different approaches of implementing NEMS, laterallyactuated double-gate NEMS devices have attracted much attention as they provide unique and exciting circuit design opportunities. For instance, this paper demonstrates that compact XOR/XNOR gates can be implemented using only two such NEMS transistors. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms) are grouped only in horizontal and/or vertical directions; the diagonal (or zig-zag) grouping of adjacent "1s" is not an option due to the absence of compact XOR/XNOR gates. However, this work demonstrates, for the first time ever, that in lateral double-gate NEMS-based circuits, grouping of minterms is possible in horizontal and vertical as well as diagonal fashions. This is because the diagonal groupings of minterms require XOR/XNOR operations, which are available in such NEMS-based circuits at minimal costs. This novel design paradigm facilitates more compact implementations of Boolean functions and thus, considerably improves their energy-efficiency. For example, a lateral NEMS-based full-adder is implemented using less than half the number of transistors, which is required by a CMOS-based full-adder. Furthermore, circuit simulations are performed to evaluate the energy-efficiencies of the NEMS-based 32-bit carry-save adders compared to their standard CMOS-based counterparts. Copyright 2010 ACM.
High linearity 5.2-GHz power amplifier MMIC using CPW structure technology with a linearizer circuit
International Nuclear Information System (INIS)
Wu Chiasong; Lin Tah-Yeong; Wu Hsien-Ming
2010-01-01
A built-in linearizer was applied to improve the linearity in a 5.2-GHz power amplifier microwave monolithic integrated circuit (MMIC), which was undertaken with 0.15-μm AlGaAs/InGaAs D-mode PHEMT technology. The power amplifier (PA) was studied taking into account the linearizer circuit and the coplanar waveguide (CPW) structures. Based on these technologies, the power amplifier, which has a chip size of 1.44 x 1.10 mm 2 , obtained an output power of 13.3 dBm and a power gain of 14 dB in the saturation region. An input third-order intercept point (HP 3 ) of -3 dBm, an output third-order intercept point (OIP 3 ) of 21.1 dBm and a power added efficiency (PAE) of 22% were attained, respectively. Finally, the overall power characterization exhibited high gain and high linearity, which illustrates that the power amplifier has a compact circuit size and exhibits favorable RF characteristics. This power circuit demonstrated high RF characterization and could be used for microwave power circuit applications at 5.2 GHz. (semiconductor integrated circuits)
Majima, Yutaka; Hackenberger, Guillaume; Azuma, Yasuo; Kano, Shinya; Matsuzaki, Kosuke; Susaki, Tomofumi; Sakamoto, Masanori; Teranishi, Toshiharu
2017-01-01
Single-electron transistors (SETs) are sub-10-nm scale electronic devices based on conductive Coulomb islands sandwiched between double-barrier tunneling barriers. Chemically assembled SETs with alkanethiol-protected Au nanoparticles show highly stable Coulomb diamonds and two-input logic operations. The combination of bottom-up and top-down processes used to form the passivation layer is vital for realizing multi-gate chemically assembled SET circuits, as this combination enables us to connect conventional complementary metal oxide semiconductor (CMOS) technologies via planar processes. Here, three-input gate exclusive-OR (XOR) logic operations are demonstrated in passivated chemically assembled SETs. The passivation layer is a hybrid bilayer of self-assembled monolayers (SAMs) and pulsed laser deposited (PLD) aluminum oxide (AlO[Formula: see text]), and top-gate electrodes were prepared on the hybrid passivation layers. Top and two-side-gated SETs showed clear Coulomb oscillation and diamonds for each of the three available gates, and three-input gate XOR logic operation was clearly demonstrated. These results show the potential of chemically assembled SETs to work as logic devices with multi-gate inputs using organic and inorganic hybrid passivation layers.
International Nuclear Information System (INIS)
Memon, A.A.
2013-01-01
This paper presents a gate driver circuit for the switching devices used in the asymmetrical converter for a switched reluctance machine with reduced number of isolated dc/dc converters. Isolation required in the gate driver circuit of switching devices is indispensable. For the purpose of isolation different arrangements may be used such as pulse transformers. The dc/dc converter for isolation and powering the gate drive circuits is suitable, cheaper in cost and simple to implement. It is also significant that required number of isolation converters is much less than the switches used in converter. In addition, a simple logic circuit has been presented for producing the gate signals at correct phase sequence which is compared with the gated signals directly obtained from the encoder of an existing machine. (author)
International Nuclear Information System (INIS)
Su Hong; Li Xiaogang; Zhu Haidong; Ma Xiaoli; Yin Weiwei; Li Zhuyu; Jin Genming; Wu Heyu
2001-01-01
A new kind of logical circuit will be introduced in brief. There are 16 independent channels in the module. The module receives low amplitude signals(≥40 mV), and processes them to amplify, shape, delay, sum and etc. After the processing each channel produces 2 pairs of ECL logical signal to feed the gate of QDC as the gate signal of QDC. The module consists of high-speed preamplifier unit, high-speed discriminate unit, delaying and shaping unit, summing unit and trigger display unit. The module is developed for 64 CH. 12 BIT Multi-event QDC. The impedance of QDC is 110 Ω. Each gate signal of QDC requires a pair of differential ECL level, Min. Gate width 30 ns and Max. Gate width 1 μs. It has showed that the outputs of logical circuit module satisfy the QDC requirements in experiment. The module can be used on data acquisition system to acquire thousands of data at high-speed ,high-density and multi-parameter, in heavy particle nuclear physics experiment. It also can be used to discriminate multi-coincidence events
Kuindersma, P.I.; Leijtens, X.J.M.; Zantvoort, van J.H.C.; Waardt, de H.
2012-01-01
We characterize integrated InP circuits for high speed ‘all-optical’ signal processing. Single chip circuits act as optical transistors. Transmodulation is performed by non-linear gain sections. Integrated tunable filters give signal equalization in time domain.
Implementation of respiratory-gated VMAT on a Versa HD linear accelerator.
Snyder, Jeffrey E; Flynn, Ryan T; Hyer, Daniel E
2017-09-01
The accurate delivery of respiratory-gated volumetric modulated arc therapy (VMAT) treatment plans presents a challenge since the gantry rotation and collimator leaves must be repeatedly stopped and set into motion during each breathing cycle. In this study, we present the commissioning process for an Anzai gating system (AZ-733VI) on an Elekta Versa HD linear accelerator and make recommendations for successful clinical implementation. The commissioning tests include central axis dose consistency, profile consistency, gating beam-on/off delay, and comparison of gated versus nongated gamma pass rates for patient-specific quality assurance using four clinically commissioned photon energies: 6 MV, 6 FFF, 10 MV, and 10 FFF. The central axis dose constancy between gated and nongated deliveries was within 0.6% for all energies and the analysis of open field profiles for gated and nongated deliveries showed an agreement of 97.8% or greater when evaluated with a percent difference criteria of 1%. The measurement of the beam-on/off delay was done by evaluating images of a moving ball-bearing phantom triggered by the gating system and average beam-on delays of 0.22-0.29 s were observed. No measurable beam-off delay was present. Measurements of gated VMAT dose distributions resulted in decrements as high as 9% in the gamma passing rate as compared to nongated deliveries when evaluated against the planned dose distribution at 3%/3 mm. By decreasing the dose rate, which decreases the gantry speed during gated delivery, the gamma passing rates of gated and nongated treatments can be made equivalent. We present an empirically derived formula to limit the maximum dose rate during VMAT deliveries and show that by implementing a reduced dose rate, a gamma passing rate of greater than 95% (3%/3 mm) was obtained for all plan measurements. © 2017 The Authors. Journal of Applied Clinical Medical Physics published by Wiley Periodicals, Inc. on behalf of American Association of
Modal and polarization qubits in Ti:LiNbO3 photonic circuits for a universal quantum logic gate.
Saleh, Mohammed F; Di Giuseppe, Giovanni; Saleh, Bahaa E A; Teich, Malvin Carl
2010-09-13
Lithium niobate photonic circuits have the salutary property of permitting the generation, transmission, and processing of photons to be accommodated on a single chip. Compact photonic circuits such as these, with multiple components integrated on a single chip, are crucial for efficiently implementing quantum information processing schemes.We present a set of basic transformations that are useful for manipulating modal qubits in Ti:LiNbO(3) photonic quantum circuits. These include the mode analyzer, a device that separates the even and odd components of a state into two separate spatial paths; the mode rotator, which rotates the state by an angle in mode space; and modal Pauli spin operators that effect related operations. We also describe the design of a deterministic, two-qubit, single-photon, CNOT gate, a key element in certain sets of universal quantum logic gates. It is implemented as a Ti:LiNbO(3) photonic quantum circuit in which the polarization and mode number of a single photon serve as the control and target qubits, respectively. It is shown that the effects of dispersion in the CNOT circuit can be mitigated by augmenting it with an additional path. The performance of all of these components are confirmed by numerical simulations. The implementation of these transformations relies on selective and controllable power coupling among single- and two-mode waveguides, as well as the polarization sensitivity of the Pockels coefficients in LiNbO(3).
Design of quaternary logic circuit using quantum dot gate-quantum dot channel FET (QDG-QDCFET)
Karmakar, Supriya
2014-10-01
This paper presents the implementation of quaternary logic circuits based on quantum dot gate-quantum dot channel field effect transistor (QDG-QDCFET). The super lattice structure in the quantum dot channel region of QDG-QDCFET and the electron tunnelling from inversion channel to the quantum dot layer in the gate region of a QDG-QDCFET change the threshold voltage of this device which produces two intermediate states between its ON and OFF states. This property of QDG-QDCFET is used to implement multi-valued logic for future multi-valued logic circuit. This paper presents the design of basic quaternary logic operation such as inverter, AND and OR operation based on QDG-QDCFET.
International Nuclear Information System (INIS)
Barbieri, M.
2007-01-01
Bose-Einstein coalescence of independent photons at the surface of a beam splitter is the physical process that allows linear optical quantum gates to be built. When distinct parametric down-conversion events are used as an independent photon source, distinguishability arises form the energy correlation of each photon with its twin. We derive upper bound for the entanglement which can be generated under these conditions
Ahmad, Peer Zahoor; Quadri, S M K; Ahmad, Firdous; Bahar, Ali Newaz; Wani, Ghulam Mohammad; Tantary, Shafiq Maqbool
2017-12-01
Quantum-dot cellular automata, is an extremely small size and a powerless nanotechnology. It is the possible alternative to current CMOS technology. Reversible QCA logic is the most important issue at present time to reduce power losses. This paper presents a novel reversible logic gate called the F-Gate. It is simplest in design and a powerful technique to implement reversible logic. A systematic approach has been used to implement a novel single layer reversible Full-Adder, Full-Subtractor and a Full Adder-Subtractor using the F-Gate. The proposed Full Adder-Subtractor has achieved significant improvements in terms of overall circuit parameters among the most previously cost-efficient designs that exploit the inevitable nano-level issues to perform arithmetic computing. The proposed designs have been authenticated and simulated using QCADesigner tool ver. 2.0.3.
Park, Hyeonwoo; Teramoto, Akinobu; Kuroda, Rihito; Suwa, Tomoyuki; Sugawa, Shigetoshi
2018-04-01
Localized stress-induced leakage current (SILC) has become a major problem in the reliability of flash memories. To reduce it, clarifying the SILC mechanism is important, and statistical measurement and analysis have to be carried out. In this study, we applied an array test circuit that can measure the SILC distribution of more than 80,000 nMOSFETs with various gate areas at a high speed (within 80 s) and a high accuracy (on the 10-17 A current order). The results clarified that the distributions of localized SILC in different gate areas follow a universal distribution assuming the same SILC defect density distribution per unit area, and the current of localized SILC defects does not scale down with the gate area. Moreover, the distribution of SILC defect density and its dependence on the oxide field for measurement (E OX-Measure) were experimentally determined for fabricated devices.
Manzoor, Ali; Rafique, Sajid; Usman Iftikhar, Muhammad; Mahmood Ul Hassan, Khalid; Nasir, Ali
2017-08-01
Piezoelectric vibration energy harvester (PVEH) consists of a cantilever bimorph with piezoelectric layers pasted on its top and bottom, which can harvest power from vibrations and feed to low power wireless sensor nodes through some power conditioning circuit. In this paper, a non-linear conditioning circuit, consisting of a full-bridge rectifier followed by a buck-boost converter, is employed to investigate the issues of electrical side of the energy harvesting system. An integrated mathematical model of complete electromechanical system has been developed. Previously, researchers have studied PVEH with sophisticated piezo-beam models but employed simplistic linear circuits, such as resistor, as electrical load. In contrast, other researchers have worked on more complex non-linear circuits but with over-simplified piezo-beam models. Such models neglect different aspects of the system which result from complex interactions of its electrical and mechanical subsystems. In this work, authors have integrated the distributed parameter-based model of piezo-beam presented in literature with a real world non-linear electrical load. Then, the developed integrated model is employed to analyse the stability of complete energy harvesting system. This work provides a more realistic and useful electromechanical model having realistic non-linear electrical load unlike the simplistic linear circuit elements employed by many researchers.
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Wu, Rui; Iannuzzo, Francesco
2015-01-01
This paper analyzes the evidence of critical gate voltage oscillations in 1.7 kV/1 kA Insulated-Gate Bipolar Transistor (IGBT) power modules under short circuit conditions. A 6 kA/1.1 kV Non-Destructive Test (NDT) set up for repeatable short circuit tests has been built with a 40 nH stray inducta...
Linear circuits, systems and signal processing: theory and application
International Nuclear Information System (INIS)
Byrnes, C.I.; Saeks, R.E.; Martin, C.F.
1988-01-01
In part because of its universal role as a first approximation of more complicated behaviour and in part because of the depth and breadth of its principle paradigms, the study of linear systems continues to play a central role in control theory and its applications. Enhancing more traditional applications to aerospace and electronics, application areas such as econometrics, finance, and speech and signal processing have contributed to a renaissance in areas such as realization theory and classical automatic feedback control. Thus, the last few years have witnessed a remarkable research effort expended in understanding both new algorithms and new paradigms for modeling and realization of linear processes and in the analysis and design of robust control strategies. The papers in this volume reflect these trends in both the theory and applications of linear systems and were selected from the invited and contributed papers presented at the 8th International Symposium on the Mathematical Theory of Networks and Systems held in Phoenix on June 15-19, 1987
Energy Technology Data Exchange (ETDEWEB)
Escane, J.M. [Ecole Superieure d' Electricite, 91 - Gif-sur-Yvette (France)
2005-04-01
The first part of this article defines the different elements of an electrical network and the models to represent them. Each model involves the current and the voltage as a function of time. Models involving time functions are simple but their use is not always easy. The Laplace transformation leads to a more convenient form where the variable is no more directly the time. This transformation leads also to the notion of transfer function which is the object of the second part. The third part aims at defining the fundamental operation rules of linear networks, commonly named 'general theorems': linearity principle and superimposition theorem, duality principle, Thevenin theorem, Norton theorem, Millman theorem, triangle-star and star-triangle transformations. These theorems allow to study complex power networks and to simplify the calculations. They are based on hypotheses, the first one is that all networks considered in this article are linear. (J.S.)
International Nuclear Information System (INIS)
Bandyopadhyay, Supriyo; Cahay, Marc
2009-01-01
In electronics, information has been traditionally stored, processed and communicated using an electron's charge. This paradigm is increasingly turning out to be energy-inefficient, because movement of charge within an information processing device invariably causes current flow and an associated dissipation. Replacing 'charge' with the 'spin' of an electron to encode information may eliminate much of this dissipation and lead to more energy-efficient 'green electronics'. This realization has spurred significant research in spintronic devices and circuits where spin either directly acts as the physical variable for hosting information or augments the role of charge. In this review article, we discuss and elucidate some of these ideas, and highlight their strengths and weaknesses. Many of them can potentially reduce energy dissipation significantly, but unfortunately are error-prone and unreliable. Moreover, there are serious obstacles to their technological implementation that may be difficult to overcome in the near term. This review addresses three constructs: (1) single devices or binary switches that can be constituents of Boolean logic gates for digital information processing, (2) complete gates that are capable of performing specific Boolean logic operations, and (3) combinational circuits or architectures (equivalent to many gates working in unison) that are capable of performing universal computation. (topical review)
Asymmetric split-gate ambipolar transistor and its circuit application to complementary inverter
Yoo, H.; Smits, E.C.P.; van Breemen, A.J.J.M.; van der Steen, J.L.; Torricelli, F.; Ghittorelli, M.; Lee, J.; Gelinck, G.; Kim, J.-J.
2016-01-01
Using a concept of asymmetric side gate and main gate, it is shown that it is possible to realize unipolar transport (both p-type and n-type) in a thin-film transistor with a high-performance ambipolar polymer semiconductor. In a complementary inverter, this results in higher noise margin and DC
Cooke, C. H.
1975-01-01
STICAP (Stiff Circuit Analysis Program) is a FORTRAN 4 computer program written for the CDC-6400-6600 computer series and SCOPE 3.0 operating system. It provides the circuit analyst a tool for automatically computing the transient responses and frequency responses of large linear time invariant networks, both stiff and nonstiff (algorithms and numerical integration techniques are described). The circuit description and user's program input language is engineer-oriented, making simple the task of using the program. Engineering theories underlying STICAP are examined. A user's manual is included which explains user interaction with the program and gives results of typical circuit design applications. Also, the program structure from a systems programmer's viewpoint is depicted and flow charts and other software documentation are given.
Directory of Open Access Journals (Sweden)
H. Vazquez-Leal
2014-01-01
Full Text Available We present a homotopy continuation method (HCM for finding multiple operating points of nonlinear circuits composed of devices modelled by using piecewise linear (PWL representations. We propose an adaptation of the modified spheres path tracking algorithm to trace the homotopy trajectories of PWL circuits. In order to assess the benefits of this proposal, four nonlinear circuits composed of piecewise linear modelled devices are analysed to determine their multiple operating points. The results show that HCM can find multiple solutions within a single homotopy trajectory. Furthermore, we take advantage of the fact that homotopy trajectories are PWL curves meant to replace the multidimensional interpolation and fine tuning stages of the path tracking algorithm with a simple and highly accurate procedure based on the parametric straight line equation.
dRail: a novel physical layout methodology for power gated circuits
Mistry, Jatin N.; Biggs, John; Myers, James; Al-Hashimi, Bashir M.; Flynn, David
2012-01-01
In this paper we present a physical layout methodology, called dRail, to allow power gated and non-power gated cells to be placed next to each other. This is unlike traditional voltage area layout which separates cells to prevent shorting of power supplies leading to impact on area, routing and power. To implement dRail, a modified standard cell architecture and physical layout is proposed. The methodology is validated by implementing power gating on the data engine in an ARM Cortex-A5 proces...
Two-qubit gate operations in superconducting circuits with strong coupling and weak anharmonicity
International Nuclear Information System (INIS)
Lü Xinyou; Ashhab, S; Cui Wei; Wu Rebing; Nori, Franco
2012-01-01
We theoretically study the implementation of two-qubit gates in a system of two coupled superconducting qubits. In particular, we analyze two-qubit gate operations under the condition that the coupling strength is comparable with or even larger than the anharmonicity of the qubits. By numerically solving the time-dependent Schrödinger equation under the assumption of negligible decoherence, we obtain the dependence of the two-qubit gate fidelity on the system parameters in the case of both direct and indirect qubit-qubit coupling. Our numerical results can be used to identify the ‘safe’ parameter regime for experimentally implementing two-qubit gates with high fidelity in these systems. (paper)
Seven channel gated charge to time converter
Energy Technology Data Exchange (ETDEWEB)
Stubbs, R J; Waddoup, W D [Durham Univ. (UK)
1977-11-01
By using a hybrid integrated circuit seven independent gated charge to time converters have been constructed in a single width NIM module. Gate widths from < approximately 10 ns to approximately 300 ns are possible with a resolution of 0.25 pC, linearity is better than +-1 pC over 2.5 decades of input signal height. Together with a multichannel scaling system described in the following paper one has a very powerful multichannel gated ADC system.
Using NCAP to predict RFI effects in linear bipolar integrated circuits
Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.
1980-11-01
Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.
Automatic Design of Synthetic Gene Circuits through Mixed Integer Non-linear Programming
Huynh, Linh; Kececioglu, John; Köppe, Matthias; Tagkopoulos, Ilias
2012-01-01
Automatic design of synthetic gene circuits poses a significant challenge to synthetic biology, primarily due to the complexity of biological systems, and the lack of rigorous optimization methods that can cope with the combinatorial explosion as the number of biological parts increases. Current optimization methods for synthetic gene design rely on heuristic algorithms that are usually not deterministic, deliver sub-optimal solutions, and provide no guaranties on convergence or error bounds. Here, we introduce an optimization framework for the problem of part selection in synthetic gene circuits that is based on mixed integer non-linear programming (MINLP), which is a deterministic method that finds the globally optimal solution and guarantees convergence in finite time. Given a synthetic gene circuit, a library of characterized parts, and user-defined constraints, our method can find the optimal selection of parts that satisfy the constraints and best approximates the objective function given by the user. We evaluated the proposed method in the design of three synthetic circuits (a toggle switch, a transcriptional cascade, and a band detector), with both experimentally constructed and synthetic promoter libraries. Scalability and robustness analysis shows that the proposed framework scales well with the library size and the solution space. The work described here is a step towards a unifying, realistic framework for the automated design of biological circuits. PMID:22536398
International Nuclear Information System (INIS)
Flament, O.; Autran, J.L.; Roche, P.; Leray, J.L.; Musseau, O.
1996-01-01
Enhanced total dose damage of Junction Field-effect Transistors (JFETs) due to low dose rate and/or elevated temperature has been investigated for elementary p-channel structures fabricated on bulk and SOI substrates as well as for related linear integrated circuits. All these devices were fabricated with conventional junction isolation (field oxide). Large increases in damage have been revealed by performing high temperature and/or low dose rate irradiations. These results are consistent with previous studies concerning bipolar field oxides under low-field conditions. They suggest that the transport of radiation-induced holes through the oxide is the underlying mechanism. Such an enhanced degradation must be taken into account for low dose rate effects on linear integrated circuits
Pfaff, Wolfgang; Reagor, Matthew; Heeres, Reinier; Ofek, Nissim; Chou, Kevin; Blumoff, Jacob; Leghtas, Zaki; Touzard, Steven; Sliwa, Katrina; Holland, Eric; Krastanov, Stefan; Frunzio, Luigi; Devoret, Michel; Jiang, Liang; Schoelkopf, Robert
2015-03-01
High-Q microwave resonators show great promise for storing and manipulating quantum states in circuit QED. Using resonator modes as such a resource in quantum information processing applications requires the ability to manipulate the state of a resonator efficiently. Further, one must engineer appropriate coupling channels without spoiling the coherence properties of the resonator. We present an architecture that combines millisecond lifetimes for photonic quantum states stored in a linear resonator with fast measurement provided by a low-Q readout resonator. We demonstrate experimentally how a continuous drive on a transmon can be utilized to generate highly non-classical photonic states inside the high-Q resonator via effective nonlinear resonator mode interactions. Our approach opens new avenues for using modes of long-lived linear resonators in the circuit QED platform for quantum information processing tasks.
CiOpt: a program for optimization of the frequency response of linear circuits
Miró Sans, Joan Maria; Palà Schönwälder, Pere
1991-01-01
An interactive personal-computer program for optimizing the frequency response of linear lumped circuits (CiOpt) is presented. CiOpt has proved to be an efficient tool in improving designs where the inclusion of more accurate device models distorts the desired frequency response, as well as in device modeling. The outputs of CiOpt are the element values which best match the obtained and the desired frequency response. The optimization algorithms used (the Fletcher-Powell and Newton's methods,...
On photonic controlled phase gates
International Nuclear Information System (INIS)
Kieling, K; Eisert, J; O'Brien, J L
2010-01-01
As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.
Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates
Czech Academy of Sciences Publication Activity Database
Gál, A.; Hansen, A. K.; Koucký, Michal; Pudlák, Pavel; Viola, E.
2013-01-01
Roč. 59, č. 10 (2013), s. 6611-6627 ISSN 0018-9448 R&D Projects: GA AV ČR IAA100190902 Institutional support: RVO:67985840 Keywords : bounded-depth circuits * error-correcting codes * hashing Subject RIV: BA - General Mathematics Impact factor: 2.650, year: 2013 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6578188
Tight bounds on computing error-correcting codes by bounded-depth circuits with arbitrary gates
Czech Academy of Sciences Publication Activity Database
Gál, A.; Hansen, A. K.; Koucký, Michal; Pudlák, Pavel; Viola, E.
2013-01-01
Roč. 59, č. 10 (2013), s. 6611-6627 ISSN 0018-9448 R&D Projects: GA AV ČR IAA100190902 Institutional support: RVO:67985840 Keywords : bounded-depth circuits * error -correcting codes * hashing Subject RIV: BA - General Mathematics Impact factor: 2.650, year: 2013 http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6578188
Sporea, R. A.; Trainor, M. J.; Young, N. D.; Shannon, J. M.; Silva, S. R. P.
2014-03-01
Ultra-large-scale integrated (ULSI) circuits have benefited from successive refinements in device architecture for enormous improvements in speed, power efficiency and areal density. In large-area electronics (LAE), however, the basic building-block, the thin-film field-effect transistor (TFT) has largely remained static. Now, a device concept with fundamentally different operation, the source-gated transistor (SGT) opens the possibility of unprecedented functionality in future low-cost LAE. With its simple structure and operational characteristics of low saturation voltage, stability under electrical stress and large intrinsic gain, the SGT is ideally suited for LAE analog applications. Here, we show using measurements on polysilicon devices that these characteristics lead to substantial improvements in gain, noise margin, power-delay product and overall circuit robustness in digital SGT-based designs. These findings have far-reaching consequences, as LAE will form the technological basis for a variety of future developments in the biomedical, civil engineering, remote sensing, artificial skin areas, as well as wearable and ubiquitous computing, or lightweight applications for space exploration.
Multiple atomic scale solid surface interconnects for atom circuits and molecule logic gates
International Nuclear Information System (INIS)
Joachim, C; Martrou, D; Gauthier, S; Rezeq, M; Troadec, C; Jie Deng; Chandrasekhar, N
2010-01-01
The scientific and technical challenges involved in building the planar electrical connection of an atomic scale circuit to N electrodes (N > 2) are discussed. The practical, laboratory scale approach explored today to assemble a multi-access atomic scale precision interconnection machine is presented. Depending on the surface electronic properties of the targeted substrates, two types of machines are considered: on moderate surface band gap materials, scanning tunneling microscopy can be combined with scanning electron microscopy to provide an efficient navigation system, while on wide surface band gap materials, atomic force microscopy can be used in conjunction with optical microscopy. The size of the planar part of the circuit should be minimized on moderate band gap surfaces to avoid current leakage, while this requirement does not apply to wide band gap surfaces. These constraints impose different methods of connection, which are thoroughly discussed, in particular regarding the recent progress in single atom and molecule manipulations on a surface.
A novel mixed-synchronization phenomenon in coupled Chua's circuits via non-fragile linear control
International Nuclear Information System (INIS)
Wang Jun-Wei; Ma Qing-Hua; Zeng Li
2011-01-01
Dynamical variables of coupled nonlinear oscillators can exhibit different synchronization patterns depending on the designed coupling scheme. In this paper, a non-fragile linear feedback control strategy with multiplicative controller gain uncertainties is proposed for realizing the mixed-synchronization of Chua's circuits connected in a drive-response configuration. In particular, in the mixed-synchronization regime, different state variables of the response system can evolve into complete synchronization, anti-synchronization and even amplitude death simultaneously with the drive variables for an appropriate choice of scaling matrix. Using Lyapunov stability theory, we derive some sufficient criteria for achieving global mixed-synchronization. It is shown that the desired non-fragile state feedback controller can be constructed by solving a set of linear matrix inequalities (LMIs). Numerical simulations are also provided to demonstrate the effectiveness of the proposed control approach. (general)
Directory of Open Access Journals (Sweden)
D. V. Rose
2010-09-01
Full Text Available A 3D fully electromagnetic (EM model of the principal pulsed-power components of a high-current linear transformer driver (LTD has been developed. LTD systems are a relatively new modular and compact pulsed-power technology based on high-energy density capacitors and low-inductance switches located within a linear-induction cavity. We model 1-MA, 100-kV, 100-ns rise-time LTD cavities [A. A. Kim et al., Phys. Rev. ST Accel. Beams 12, 050402 (2009PRABFM1098-440210.1103/PhysRevSTAB.12.050402] which can be used to drive z-pinch and material dynamics experiments. The model simulates the generation and propagation of electromagnetic power from individual capacitors and triggered gas switches to a radially symmetric output line. Multiple cavities, combined to provide voltage addition, drive a water-filled coaxial transmission line. A 3D fully EM model of a single 1-MA 100-kV LTD cavity driving a simple resistive load is presented and compared to electrical measurements. A new model of the current loss through the ferromagnetic cores is developed for use both in circuit representations of an LTD cavity and in the 3D EM simulations. Good agreement between the measured core current, a simple circuit model, and the 3D simulation model is obtained. A 3D EM model of an idealized ten-cavity LTD accelerator is also developed. The model results demonstrate efficient voltage addition when driving a matched impedance load, in good agreement with an idealized circuit model.
Sevilla, Galo T.
2016-02-29
Thinned silicon based complementary metal oxide semiconductor(CMOS)electronics can be physically flexible. To overcome challenges of limited thinning and damaging of devices originated from back grinding process, we show sequential reactive ion etching of silicon with the assistance from soft polymeric materials to efficiently achieve thinned (40 μm) and flexible (1.5 cm bending radius) silicon based functional CMOSinverters with high-κ/metal gate transistors. Notable advances through this study shows large area of silicon thinning with pre-fabricated high performance elements with ultra-large-scale-integration density (using 90 nm node technology) and then dicing of such large and thinned (seemingly fragile) pieces into smaller pieces using excimer laser. The impact of various mechanical bending and bending cycles show undeterred high performance of flexible siliconCMOSinverters. Future work will include transfer of diced silicon chips to destination site, interconnects, and packaging to obtain fully flexible electronic systems in CMOS compatible way.
Imperfect linear-optical photonic gates with number-resolving photodetection
International Nuclear Information System (INIS)
Smith, A. Matthew; Uskov, D. B.; Ying, L. H.; Kaplan, L.
2011-01-01
We use the numerical optimization techniques of Uskov et al.[Phys. Rev. A 81, 012303 (2010)] to investigate the behavior of the success rates for Knill-Laflamme-Milburn-style [Knill et al., Nature (London) 409, 46 (2001)] two- and three-qubit entangling gates. The methods are first demonstrated at perfect fidelity and then extended to imperfect gates. We find that as the perfect fidelity condition is relaxed, the maximum attainable success rates increase in a predictable fashion depending on the size of the system, and we compare that rate of increase for several gates.
Robust 2-Qubit Gates in a Linear Ion Crystal Using a Frequency-Modulated Driving Force
Leung, Pak Hong; Landsman, Kevin A.; Figgatt, Caroline; Linke, Norbert M.; Monroe, Christopher; Brown, Kenneth R.
2018-01-01
In an ion trap quantum computer, collective motional modes are used to entangle two or more qubits in order to execute multiqubit logical gates. Any residual entanglement between the internal and motional states of the ions results in loss of fidelity, especially when there are many spectator ions in the crystal. We propose using a frequency-modulated driving force to minimize such errors. In simulation, we obtained an optimized frequency-modulated 2-qubit gate that can suppress errors to less than 0.01% and is robust against frequency drifts over ±1 kHz . Experimentally, we have obtained a 2-qubit gate fidelity of 98.3(4)%, a state-of-the-art result for 2-qubit gates with five ions.
International Nuclear Information System (INIS)
Sah, C.-T.; Jie Binbin
2009-01-01
This paper reports the physical realization of the Bipolar Field-Effect Transistor (BiFET) and its one-transistor basic building block circuits. Examples are given for the one and two MOS gates on thin and thick, pure and impure base, with electron and hole contacts, and the corresponding theoretical current-voltage characteristics previously computed by us, without generation-recombination-trapping-tunneling of electrons and holes. These examples include the one-MOS-gate on semi-infinite thick impure base transistor (the bulk transistor) and the impurethin-base Silicon-on-Insulator (SOI) transistor and the two-MOS-gates on thin base transistors (the FinFET and the Thin Film Transistor TFT). Figures are given with the cross-section views containing the electron and hole concentration and current density distributions and trajectories and the corresponding DC current-voltage characteristics.
Kim, Dae-Hyeong; Song, Jizhou; Choi, Won Mook; Kim, Hoon-Sik; Kim, Rak-Hwan; Liu, Zhuangjian; Huang, Yonggang Y; Hwang, Keh-Chih; Zhang, Yong-wei; Rogers, John A
2008-12-02
Electronic systems that offer elastic mechanical responses to high-strain deformations are of growing interest because of their ability to enable new biomedical devices and other applications whose requirements are impossible to satisfy with conventional wafer-based technologies or even with those that offer simple bendability. This article introduces materials and mechanical design strategies for classes of electronic circuits that offer extremely high stretchability, enabling them to accommodate even demanding configurations such as corkscrew twists with tight pitch (e.g., 90 degrees in approximately 1 cm) and linear stretching to "rubber-band" levels of strain (e.g., up to approximately 140%). The use of single crystalline silicon nanomaterials for the semiconductor provides performance in stretchable complementary metal-oxide-semiconductor (CMOS) integrated circuits approaching that of conventional devices with comparable feature sizes formed on silicon wafers. Comprehensive theoretical studies of the mechanics reveal the way in which the structural designs enable these extreme mechanical properties without fracturing the intrinsically brittle active materials or even inducing significant changes in their electrical properties. The results, as demonstrated through electrical measurements of arrays of transistors, CMOS inverters, ring oscillators, and differential amplifiers, suggest a valuable route to high-performance stretchable electronics.
Directory of Open Access Journals (Sweden)
Tony T. Kim
2011-07-01
Full Text Available Recently, double-gate MOSFETs (DGMOSFETs have been shown to be more optimal for ultra-low power circuit design due to the improved subthreshold slope and the reduced leakage current compared to bulk CMOS. However, DGMOSFETs for subthreshold circuit design have not been much explored in comparison to those for strong inversion-based design. In this paper, various configurations of DGMOSFETs, such as tied/independent gates and symmetric/asymmetric gate oxide thickness are explored for ultra-low power and high efficient radio frequency identification (RFID design. Comparison of bulk CMOS with DGMOSFETs has been conducted in ultra-low power subthreshold digital logic design and rectifier design, emphasizing the scope of the nano-scale DGMOSFET technology for future ultra-low power systems. The DGMOSFET-based subthreshold logic improves energy efficiency by more than 40% compared to the bulk CMOS-based logic at 32 nm. Among the various DGMOSFET configurations for RFID rectifiers, symmetric tied-gate DGMOSFET has the best power conversion efficiency and the lowest power consumption.
Directory of Open Access Journals (Sweden)
A. Daghighi
2013-09-01
Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.
Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto
2018-04-01
Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.
Kengne, J.; Jafari, S.; Njitacke, Z. T.; Yousefi Azar Khanian, M.; Cheukem, A.
2017-11-01
Mathematical models (ODEs) describing the dynamics of almost all continuous time chaotic nonlinear systems (e.g. Lorenz, Rossler, Chua, or Chen system) involve at least a nonlinear term in addition to linear terms. In this contribution, a novel (and singular) 3D autonomous chaotic system without linear terms is introduced. This system has an especial feature of having two twin strange attractors: one ordinary and one symmetric strange attractor when the time is reversed. The complex behavior of the model is investigated in terms of equilibria and stability, bifurcation diagrams, Lyapunov exponent plots, time series and Poincaré sections. Some interesting phenomena are found including for instance, period-doubling bifurcation, antimonotonicity (i.e. the concurrent creation and annihilation of periodic orbits) and chaos while monitoring the system parameters. Compared to the (unique) case previously reported by Xu and Wang (2014) [31], the system considered in this work displays a more 'elegant' mathematical expression and experiences richer dynamical behaviors. A suitable electronic circuit (i.e. the analog simulator) is designed and used for the investigations. Pspice based simulation results show a very good agreement with the theoretical analysis.
Li, Dong; Chen, Mingyuan; Zong, Qijun; Zhang, Zengxing
2017-10-11
The Schottky junction is an important unit in electronics and optoelectronics. However, its properties greatly degrade with device miniaturization. The fast development of circuits has fueled a rapid growth in the study of two-dimensional (2D) crystals, which may lead to breakthroughs in the semiconductor industry. Here we report a floating-gate manipulated nonvolatile ambipolar Schottky junction memory from stacked all-2D layers of graphene-BP/h-BN/graphene (BP, black phosphorus; h-BN, hexagonal boron nitride) in a designed floating-gate field-effect Schottky barrier transistor configuration. By manipulating the voltage pulse applied to the control gate, the device exhibits ambipolar characteristics and can be tuned to act as graphene-p-BP or graphene-n-BP junctions with reverse rectification behavior. Moreover, the junction exhibits good storability properties of more than 10 years and is also programmable. On the basis of these characteristics, we further demonstrate the application of the device to dual-mode nonvolatile Schottky junction memories, memory inverter circuits, and logic rectifiers.
International Nuclear Information System (INIS)
Pease, R.L.; Brown, D.B.; Cohn, L.
1997-01-01
A hardness assurance test approach has been developed for bipolar linear circuits and devices in space. It consists of a screen for dose rate sensitivity and a characterization test method to develop the conditions for a lot acceptance test at high dose rate
Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei
2017-12-01
InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. Gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing module size are important challenges for the design of such detector system. Here we present for the first time an InGaAs/InP SPD with 1.25 GHz sine wave gating using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15 mm * 15 mm and implements the miniaturization of avalanche extraction for high-frequency sine wave gating. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of MIRC, and the SPD exhibits excellent performance with 27.5 % photon detection efficiency, 1.2 kcps dark count rate, and 9.1 % afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.
Zhou, Yu; Pearson, John E; Auerbach, Anthony
2005-12-01
We derive the analytical form of a rate-equilibrium free-energy relationship (with slope Phi) for a bounded, linear chain of coupled reactions having arbitrary connecting rate constants. The results confirm previous simulation studies showing that Phi-values reflect the position of the perturbed reaction within the chain, with reactions occurring earlier in the sequence producing higher Phi-values than those occurring later in the sequence. The derivation includes an expression for the transmission coefficients of the overall reaction based on the rate constants of an arbitrary, discrete, finite Markov chain. The results indicate that experimental Phi-values can be used to calculate the relative heights of the energy barriers between intermediate states of the chain but provide no information about the energies of the wells along the reaction path. Application of the equations to the case of diliganded acetylcholine receptor channel gating suggests that the transition-state ensemble for this reaction is nearly flat. Although this mechanism accounts for many of the basic features of diliganded and unliganded acetylcholine receptor channel gating, the experimental rate-equilibrium free-energy relationships appear to be more linear than those predicted by the theory.
Djordjevic, Ivan B
2010-04-12
The Bell states preparation circuit is a basic circuit required in quantum teleportation. We describe how to implement it in all-fiber technology. The basic building blocks for its implementation are directional couplers and highly nonlinear optical fiber (HNLF). Because the quantum information processing is based on delicate superposition states, it is sensitive to quantum errors. In order to enable fault-tolerant quantum computing the use of quantum error correction is unavoidable. We show how to implement in all-fiber technology encoders and decoders for sparse-graph quantum codes, and provide an illustrative example to demonstrate this implementation. We also show that arbitrary set of universal quantum gates can be implemented based on directional couplers and HNLFs.
Energy Technology Data Exchange (ETDEWEB)
Lee, S; Zheng, Y; Albani, D; Colussi, V; Dorth, J; Sohn, J [Case Western University, Cleveland, OH (United States)
2016-06-15
Purpose: To reduce internal target volume (ITV), respiratory management is a must in imaging and treatment for lung, liver, and breast cancers. We investigated the dosimetric accuracy of VMAT treatment delivery with a Response™ gating system linked to linear accelerator. Methods: The Response™ gating module designed to directly control radiation beam by breath-holding with a ABC system (Elekta AB, Stockholm, Sweden) was tested for VMAT treatments. Seven VMAT plans including three conventional and four stereotactic body radiotherapy (SBRT) cases were evaluated. Each plan was composed of two or four arcs of 6MV radiation beam with prescribed dose ranged from 1.8 to 9 Gy per fraction. Each plan was delivered continuously without gating and delivered with multiple interruptions by the ResponseTM gating module with a 20 or 30 second breath-holding period. MapCheck2 and Gafchromic EBT3 films sandwiched in MapPHAN were used to measure the delivered dose with and without gating. Films were scanned on a flatbed color scanner, and red channel was extracted for film dosimetry. Gamma analysis was performed to analyze the dosimetrical accuracy of the radiation delivery with gating. Results: The measured doses with gating remarkably agree with the planned dose distributions in the results of gamma index passing rate (within 20% isodose; >98% for 3%/3mm and >92% for 2%/2mm in MapCheck2, and >91% for 3%/3mm criteria in EBT3 film except one case which was for large target and highly modulated). No significant difference (student t-test: p-value < 0.0005) was shown between the doses delivered with and without gating. There was no indication of radiation gap or overlapping during deliver interruption in film dosimetry. Conclusion: The Response™ gating system can be safely used during VMAT treatment. The accurate performance of the gating system linked to ABC can contribute to ITV reduction for SBRT using VMAT.
International Nuclear Information System (INIS)
Kobulnicky, K; Pawlak, D; Purwar, A
2015-01-01
Purpose: To examine the beam performance of a Varian TrueBeam linear accelerator under external device-based gated delivery conditions. Methods: Six gating cycles were used to evaluate the gating performance of a standard production TrueBeam system that was not specially tuned in any way. The system was equipped with a factory installed external gating interface (EXGI). An in-house EXGI tester box was used to simulate the input gating signals. The gating cycles were selected based on long beam-on and short beam-off times, short beam-on and long beam-off times, or equal beam on and off times to check linac performance. The beam latencies were measured as the time difference between the logic high gating signal and the first or last target pulses with an oscilloscope. Tissue-Phantom Ratio, beam flatness, and dose distributions from 5 different plans were measured using the 6 different gating durations and the un-gated irradiation. A PTW 729 2-D array was used to compare 5 plans versus the un-gated delivery with a 1%/1mm gamma index passing criteria. Results: The beam latencies of the linac were based off of 20 samples for beam-on and beam-off, for each gating cycle. The average beam-on delays were measured to be between 57 and 66msec, with a maximum of 88 msec. The beam off latencies averaged between 19 and 26msec, with a maximum of 48 msec. TPR20,10 measurements showed beam energy stability within 0.5% of the un-gated delivery. Beam flatness was better than 2.5% for all gated cycles. All but two deliveries, the open field with 4 seconds on, 1 second off, and a five field IMRT plan with 0.5 seconds on, 2.5 seconds off, had >90% passing rate. Conclusion: TrueBeam demonstrates excellent beam stability with minimal beam latencies under external device-based gated operations. Dosimetric measurements show minimal variation in beam energy, flatness, and plan delivery. Authors are employees of Varian Medical Systems, Inc
Energy Technology Data Exchange (ETDEWEB)
Kobulnicky, K; Pawlak, D; Purwar, A [Varian Medical Systems, Inc., Palo Alto, CA (United States)
2015-06-15
Purpose: To examine the beam performance of a Varian TrueBeam linear accelerator under external device-based gated delivery conditions. Methods: Six gating cycles were used to evaluate the gating performance of a standard production TrueBeam system that was not specially tuned in any way. The system was equipped with a factory installed external gating interface (EXGI). An in-house EXGI tester box was used to simulate the input gating signals. The gating cycles were selected based on long beam-on and short beam-off times, short beam-on and long beam-off times, or equal beam on and off times to check linac performance. The beam latencies were measured as the time difference between the logic high gating signal and the first or last target pulses with an oscilloscope. Tissue-Phantom Ratio, beam flatness, and dose distributions from 5 different plans were measured using the 6 different gating durations and the un-gated irradiation. A PTW 729 2-D array was used to compare 5 plans versus the un-gated delivery with a 1%/1mm gamma index passing criteria. Results: The beam latencies of the linac were based off of 20 samples for beam-on and beam-off, for each gating cycle. The average beam-on delays were measured to be between 57 and 66msec, with a maximum of 88 msec. The beam off latencies averaged between 19 and 26msec, with a maximum of 48 msec. TPR20,10 measurements showed beam energy stability within 0.5% of the un-gated delivery. Beam flatness was better than 2.5% for all gated cycles. All but two deliveries, the open field with 4 seconds on, 1 second off, and a five field IMRT plan with 0.5 seconds on, 2.5 seconds off, had >90% passing rate. Conclusion: TrueBeam demonstrates excellent beam stability with minimal beam latencies under external device-based gated operations. Dosimetric measurements show minimal variation in beam energy, flatness, and plan delivery. Authors are employees of Varian Medical Systems, Inc.
Jiang, Wen-Hao; Liu, Jian-Hong; Liu, Yin; Jin, Ge; Zhang, Jun; Pan, Jian-Wei
2017-12-15
InGaAs/InP single-photon detectors (SPDs) are the key devices for applications requiring near-infrared single-photon detection. The gating mode is an effective approach to synchronous single-photon detection. Increasing gating frequency and reducing the module size are important challenges for the design of such a detector system. Here we present for the first time, to the best of our knowledge, an InGaAs/InP SPD with 1.25 GHz sine wave gating (SWG) using a monolithically integrated readout circuit (MIRC). The MIRC has a size of 15 mm×15 mm and implements the miniaturization of avalanche extraction for high-frequency SWG. In the MIRC, low-pass filters and a low-noise radio frequency amplifier are integrated based on the technique of low temperature co-fired ceramic, which can effectively reduce the parasitic capacitance and extract weak avalanche signals. We then characterize the InGaAs/InP SPD to verify the functionality and reliability of the MIRC, and the SPD exhibits excellent performance with 27.5% photon detection efficiency, a 1.2 kcps dark count rate, and 9.1% afterpulse probability at 223 K and 100 ns hold-off time. With this MIRC, one can further design miniaturized high-frequency SPD modules that are highly required for practical applications.
High voltage MOSFET switching circuit
McEwan, Thomas E.
1994-01-01
The problem of source lead inductance in a MOSFET switching circuit is compensated for by adding an inductor to the gate circuit. The gate circuit inductor produces an inductive spike which counters the source lead inductive drop to produce a rectangular drive voltage waveform at the internal gate-source terminals of the MOSFET.
International Nuclear Information System (INIS)
Landen, O.L.; Bell, P.M.; Satariano, J.J.; Oertel, J.A.; Bradley, D.K.
1994-01-01
The pulsed characteristics of gated, stripline configuration microchannel-plate (MCP) detectors used in X-ray framing cameras deployed on laser plasma experiments worldwide are examined in greater detail. The detectors are calibrated using short (20 ps) and long (500 ps) pulse X-ray irradiation and 3--60 ps, deep UV (202 and 213 nm), spatially-smoothed laser irradiation. Two-dimensional unsaturated gain profiles show 5 in irradiation and fitted using a discrete dynode model. Finally, a pump-probe experiment quantifying for the first time long-suspected gain depletion by strong localized irradiation was performed. The mechanism for the extra voltage and hence gain degradation is shown to be associated with intense MCP irradiation in the presence of the voltage pulse, at a fluence at least an order of magnitude above that necessary for saturation. Results obtained for both constant pump area and constant pump fluence are presented. The data are well modeled by calculating the instantaneous electrical energy loss due to the intense charge extraction at the pump site and then recalculating the gain downstream at the probe site given the pump-dependent degradation in voltage amplitude
Quantum gate decomposition algorithms.
Energy Technology Data Exchange (ETDEWEB)
Slepoy, Alexander
2006-07-01
Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.
Investigation of flip-flop effects in a linear analog comparator-with-hysteresis circuit
International Nuclear Information System (INIS)
Roche, N.J.H.; Buchner, S.P.; Warner, J.H.; McMorrow, D.; Roig, F.; Auriel, G.; Dusseau, L.; Boch, J.; Saigne, F.; Azais, B.
2013-01-01
The impact of the positive feedback loop on analog single event transient (ASET) shapes was investigated for a comparator- with-hysteresis circuit. Simulation based on previous developed ASET simulation tool is used to model the impact of the power supply voltage, the input voltage level and the injected energy. Simulation results show that these kinds of circuits are sensitive to flip-flop effects. This phenomenon occurs if the input voltage is in the hysteresis band range. In this case, simulations show that the ASET can latch the output into a non-desired state by changing the state of the circuit on his transfer characteristic curves. Laser experiments were conducted and show that the simulation outputs are in agreement with the experimental collected data. (authors)
Directory of Open Access Journals (Sweden)
Wei Li
2018-04-01
Full Text Available Reliability is one of the critical issues for a modular multilevel converter (MMC since it consists of a large number of series-connected power electronics submodules (SMs. In this paper, a complete control strategy including fault detection, localization, and tolerant operation is proposed for the MMC under an insulated gate bipolar transistor (IGBT open circuit fault. According to the output characteristics of the SM with the open-circuit fault of IGBT, a fault detection method based on the circulating current and output current observation is used. In order to further precisely locate the position of the faulty SM, a fault localization method based on the SM capacitor voltage observation is developed. After the faulty SM is isolated, the continuous operation of the converter is ensured by adopting the fault-tolerant strategy based on the use of redundant modules. To verify the proposed fault detection, fault localization, and fault-tolerant operation strategies, a 900 kVA MMC system under the conditions of an IGBT open circuit is developed in the Matlab/Simulink platform. The capabilities of rapid detection, precise positioning, and fault-tolerant operation of the investigated detection and control algorithms are also demonstrated.
DEFF Research Database (Denmark)
Olsson, Per-Ivar; Fiandaca, Gianluca; Larsen, Jakob Juul
, a logarithmic gate width distribution for optimizing IP data quality and an estimate of gating uncertainty. Additional steps include modelling and cancelling of non-linear background drift and harmonic noise and a technique for efficiently identifying and removing spikes. The cancelling of non-linear background...... drift is based on a Cole-Cole model which effectively handles current induced electrode polarization drift. The model-based cancelling of harmonic noise reconstructs the harmonic noise as a sum of harmonic signals with a common fundamental frequency. After segmentation of the signal and determining....... The processing steps is successfully applied on full field profile data sets. With the model-based cancelling of harmonic noise, the first usable IP gate is moved one decade closer to time zero. Furthermore, with a Cole-Cole background drift model the shape of the response at late times is accurately retrieved...
Study on data acquisition circuit used in SSPA linear array detector X-ray detection
Wei Biao; Che Zhen Ping
2002-01-01
After SSPA used as X-ray array detector is developed, the authors take a research on the data acquisition circuit applied to the detector. The experiment designed has verified the feasibility of application of this array detector and its data acquisition circuit to X-ray computed tomography (X-CT). The preliminary test results indicate that the method of the X-ray detection is feasible for industry X-CT nondestructive testing, which brings about advantage for detecting and measuring with high resolution, good efficiency and low cost
Ultra Linear Low-loss Varactors & Circuits for Adaptive RF Systems
Huang, C.
2010-01-01
With the evolution of wireless communication, varactors can play an important role in enabling adaptive transceivers as well as phase-diversity systems. This thesis presents various varactor diode-based circuit topologies that facilitate RF adaptivity. The proposed varactor configurations can act as
International Nuclear Information System (INIS)
Lee, Min Su; Lee, Hee Chul
2012-01-01
To overcome the total ionizing dose effect on an n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET), we designed a radiation-hardened gate-around n-MOSFET structure and evaluated it through a radiation-exposure experiment. Each test device was fabricated in a commercial 0.35-micron complementary metal-oxide-semiconductor (CMOS) process. The fabricated devices were evaluated under a total dose of 1 Mrad (Si) at a dose rate of 250 krad/h to obtain very high reliability for space electronics. The experimental results showed that the gate-around n-MOSFET structure had very good performance against 1 Mrad (Si) of gamma radiation, while the conventional n-MOSFET experienced a considerable amount of radiation-induced leakage current. Furthermore, a source follower designed with the gate-around transistor worked properly at 1 Mrad (Si) of gamma radiation while a source follower designed with the conventional n-MOSFET lost its functionality.
How linear response shaped models of neural circuits and the quest for alternatives.
Herfurth, Tim; Tchumatchenko, Tatjana
2017-10-01
In the past decades, many mathematical approaches to solve complex nonlinear systems in physics have been successfully applied to neuroscience. One of these tools is the concept of linear response functions. However, phenomena observed in the brain emerge from fundamentally nonlinear interactions and feedback loops rather than from a composition of linear filters. Here, we review the successes achieved by applying the linear response formalism to topics, such as rhythm generation and synchrony and by incorporating it into models that combine linear and nonlinear transformations. We also discuss the challenges encountered in the linear response applications and argue that new theoretical concepts are needed to tackle feedback loops and non-equilibrium dynamics which are experimentally observed in neural networks but are outside of the validity regime of the linear response formalism. Copyright © 2017 Elsevier Ltd. All rights reserved.
Reagor, Matthew; Pfaff, Wolfgang; Heeres, Reinier; Ofek, Nissim; Chou, Kevin; Blumoff, Jacob; Leghtas, Zaki; Touzard, Steven; Sliwa, Katrina; Holland, Eric; Albert, Victor V.; Frunzio, Luigi; Devoret, Michel H.; Jiang, Liang; Schoelkopf, Robert J.
2015-03-01
Recent advances in circuit QED have shown great potential for using microwave resonators as quantum memories. In particular, it is possible to encode the state of a quantum bit in non-classical photonic states inside a high-Q linear resonator. An outstanding challenge is to perform controlled operations on such a photonic state. We demonstrate experimentally how a continuous drive on a transmon qubit coupled to a high-Q storage resonator can be used to induce non-linear dynamics of the resonator. Tailoring the drive properties allows us to cancel or enhance non-linearities in the system such that we can manipulate the state stored in the cavity. This approach can be used to either counteract undesirable evolution due to the bare Hamiltonian of the system or, ultimately, to perform logical operations on the state encoded in the cavity field. Our method provides a promising pathway towards performing universal control for quantum states stored in high-coherence resonators in the circuit QED platform.
Dadgour, Hamed F.; Hussain, Muhammad Mustafa; Banerjee, Kaustav
2010-01-01
. While this in itself is a major improvement, its implications for minimizing Boolean functions using Karnaugh maps (K-maps) are even more significant. In the standard K-map technique, which is used in digital circuit design, adjacent "1s" (minterms
Stanley, A. G.; Gauthier, M. K.
1977-01-01
A successful diagnostic technique was developed using a scanning electron microscope (SEM) as a precision tool to determine ionization effects in integrated circuits. Previous SEM methods radiated the entire semiconductor chip or major areas. The large area exposure methods do not reveal the exact components which are sensitive to radiation. To locate these sensitive components a new method was developed, which consisted in successively irradiating selected components on the device chip with equal doses of electrons /10 to the 6th rad (Si)/, while the whole device was subjected to representative bias conditions. A suitable device parameter was measured in situ after each successive irradiation with the beam off.
Brink, S; Nease, S; Hasler, P
2013-09-01
Results are presented from several spiking network experiments performed on a novel neuromorphic integrated circuit. The networks are discussed in terms of their computational significance, which includes applications such as arbitrary spatiotemporal pattern generation and recognition, winner-take-all competition, stable generation of rhythmic outputs, and volatile memory. Analogies to the behavior of real biological neural systems are also noted. The alternatives for implementing the same computations are discussed and compared from a computational efficiency standpoint, with the conclusion that implementing neural networks on neuromorphic hardware is significantly more power efficient than numerical integration of model equations on traditional digital hardware. Copyright © 2013 Elsevier Ltd. All rights reserved.
Digital linear control theory applied to automatic stepsize control in electrical circuit simulation
Verhoeven, A.; Beelen, T.G.J.; Hautus, M.L.J.; Maten, ter E.J.W.; Di Bucchianico, A.; Mattheij, R.M.M.; Peletier, M.A.
2006-01-01
Adaptive stepsize control is used to control the local errors of the numerical solution. For optimization purposes smoother stepsize controllers are wanted, such that the errors and stepsizes also behave smoothly. We consider approaches from digital linear control theory applied to multistep
Digital linear control theory applied to automatic stepsize control in electrical circuit simulation
Verhoeven, A.; Beelen, T.G.J.; Hautus, M.L.J.; Maten, ter E.J.W.
2005-01-01
Adaptive stepsize control is used to control the local errors of the numerical solution. For optimization purposes smoother stepsize controllers are wanted, such that the errors and stepsizes also behave smoothly. We consider approaches from digital linear control theory applied to multistep
Lee, Dongil; Yoon, Jinsu; Lee, Juhee; Lee, Byung-Hyun; Seol, Myeong-Lok; Bae, Hagyoul; Jeon, Seung-Bae; Seong, Hyejeong; Im, Sung Gap; Choi, Sung-Jin; Choi, Yang-Kyu
2016-05-01
Printing electronics has become increasingly prominent in the field of electronic engineering because this method is highly efficient at producing flexible, low-cost and large-scale thin-film transistors. However, TFTs are typically constructed with rigid insulating layers consisting of oxides and nitrides that are brittle and require high processing temperatures, which can cause a number of problems when used in printed flexible TFTs. In this study, we address these issues and demonstrate a method of producing inkjet-printed TFTs that include an ultra-thin polymeric dielectric layer produced by initiated chemical vapor deposition (iCVD) at room temperature and highly purified 99.9% semiconducting carbon nanotubes. Our integrated approach enables the production of flexible logic circuits consisting of CNT-TFTs on a polyethersulfone (PES) substrate that have a high mobility (up to 9.76 cm2 V-1 sec-1), a low operating voltage (less than 4 V), a high current on/off ratio (3 × 104), and a total device yield of 90%. Thus, it should be emphasized that this study delineates a guideline for the feasibility of producing flexible CNT-TFT logic circuits with high performance based on a low-cost and simple fabrication process.
Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue
2017-06-24
With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.
Directory of Open Access Journals (Sweden)
Chen Yang
2017-06-01
Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.
Energy Technology Data Exchange (ETDEWEB)
Yun, Gil Jung; Yang, Hong Young
2011-03-15
This book is about digital logic circuit test, which lists the digital basic theory, basic gate like and, or And Not gate, NAND/NOR gate such as NAND gate, NOR gate, AND and OR, logic function, EX-OR gate, adder and subtractor, decoder and encoder, multiplexer, demultiplexer, flip-flop, counter such as up/down counter modulus N counter and Reset type counter, shift register, D/A and A/D converter and two supplements list of using components and TTL manual and CMOS manual.
International Nuclear Information System (INIS)
Wang Wei; Li Na; Ren Yuzhou; Li Hao; Zheng Lifen; Li Jin; Jiang Junjie; Chen Xiaoping; Wang Kai; Xia Chunping
2013-01-01
The effects of linear doping profile near the source and drain contacts on the switching and high-frequency characteristics for conventional single-material-gate CNTFET (C-CNTFET) and hetero-material-gate CNTFET (HMG-CNTFET) have been theoretically investigated by using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green's functions (NEGF) solved self-consistently with Poisson's equations. The simulation results show that at a CNT channel length of 20 nm with chirality (7, 0), the intrinsic cutoff frequency of C-CNTFETs reaches up to a few THz. In addition, a comparison study has been performed between C-and HMG-CNTFETs. For the C-CNTFET, results reveal that a longer linear doping length can improve the cutoff frequency and switching speed. However, it has the reverse effect on on/off current ratios. To improve the on/off current ratios performance of CNTFETs and overcome short-channel effects (SCEs) in high-performance device applications, a novel CNTFET structure with a combination of an HMG and linear doping profile has been proposed. It is demonstrated that the HMG structure design with an optimized linear doping length has improved high-frequency and switching performances as compared to C-CNTFETs. The simulation study may be useful for understanding and optimizing high-performance of CNTFETs and assessing the reliability of CNTFETs for prospective applications. (semiconductor devices)
International Nuclear Information System (INIS)
Takano, H.; Hosogi, K.; Kato, T.
1995-01-01
A fully ion-implanted self-aligned T-shaped gate Ga As metal-semiconductor field-effect transistor (MESFET) with high frequency and extremely low-noise performance has been successfully fabricated for super low-noise microwave monolithic integrated circuit (MMIC) amplifiers. A subhalf-micrometer gate structure composed of WSi/Ti/Mo/Au is employed to reduce gate resistance effectively. This multilayer gate structure is formed by newly developed dummy SiON self-alignment technology and a photoresist planarization process. At an operating frequency of 12 GHz, a minimum noise figure of 0.87 dB with an associated gain of 10.62 dB has been obtained. Based on the novel FET process, a low-noise single-stage MMIC amplifier with an excellent low-noise figure of 1.2 dB with an associated gain of 8 dB in the 14 GHz band has been realized. This is the lowest noise figure ever reported at this frequency for low-noise MMICs based on ion-implanted self-aligned gate MESFET technology. 14 refs., 9 figs
Chief of Naval Education and Training Support, Pensacola, FL.
This individualized learning module on linear integrated circuits is one in a series of modules for a course in basic electricity and electronics. The course is one of a number of military-developed curriculum packages selected for adaptation to vocational instructional and curriculum development in a civilian setting. Two lessons are included in…
Directory of Open Access Journals (Sweden)
Qian Hong
2008-05-01
Full Text Available Abstract Background: Several approaches, including metabolic control analysis (MCA, flux balance analysis (FBA, correlation metric construction (CMC, and biochemical circuit theory (BCT, have been developed for the quantitative analysis of complex biochemical networks. Here, we present a comprehensive theory of linear analysis for nonequilibrium steady-state (NESS biochemical reaction networks that unites these disparate approaches in a common mathematical framework and thermodynamic basis. Results: In this theory a number of relationships between key matrices are introduced: the matrix A obtained in the standard, linear-dynamic-stability analysis of the steady-state can be decomposed as A = SRT where R and S are directly related to the elasticity-coefficient matrix for the fluxes and chemical potentials in MCA, respectively; the control-coefficients for the fluxes and chemical potentials can be written in terms of RT BS and ST BS respectively where matrix B is the inverse of A; the matrix S is precisely the stoichiometric matrix in FBA; and the matrix eAt plays a central role in CMC. Conclusion: One key finding that emerges from this analysis is that the well-known summation theorems in MCA take different forms depending on whether metabolic steady-state is maintained by flux injection or concentration clamping. We demonstrate that if rate-limiting steps exist in a biochemical pathway, they are the steps with smallest biochemical conductances and largest flux control-coefficients. We hypothesize that biochemical networks for cellular signaling have a different strategy for minimizing energy waste and being efficient than do biochemical networks for biosynthesis. We also discuss the intimate relationship between MCA and biochemical systems analysis (BSA.
Reversible logic gates on Physarum Polycephalum
International Nuclear Information System (INIS)
Schumann, Andrew
2015-01-01
In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum
Nishiguchi, Kenya; Kaneki, Syota; Ozaki, Shiro; Hashizume, Tamotsu
2017-10-01
To investigate current linearity and operation stability of metal-oxide-semiconductor (MOS) AlGaN/GaN high electron mobility transistors (HEMTs), we have fabricated and characterized the Al2O3-gate MOS-HEMTs without and with a bias annealing in air at 300 °C. Compared with the as-fabricated (unannealed) MOS HEMTs, the bias-annealed devices showed improved linearity of I D-V G curves even in the forward bias regime, resulting in increased maximum drain current. Lower subthreshold slope was also observed after bias annealing. From the precise capacitance-voltage analysis on a MOS diode fabricated on the AlGaN/GaN heterostructure, it was found that the bias annealing effectively reduced the state density at the Al2O3/AlGaN interface. This led to efficient modulation of the AlGaN surface potential close to the conduction band edge, resulting in good gate control of two-dimensional electron gas density even at forward bias. In addition, the bias-annealed MOS HEMT showed small threshold voltage shift after applying forward bias stress and stable operation even at high temperatures.
Logic circuits based on molecular spider systems.
Mo, Dandan; Lakin, Matthew R; Stefanovic, Darko
2016-08-01
Spatial locality brings the advantages of computation speed-up and sequence reuse to molecular computing. In particular, molecular walkers that undergo localized reactions are of interest for implementing logic computations at the nanoscale. We use molecular spider walkers to implement logic circuits. We develop an extended multi-spider model with a dynamic environment wherein signal transmission is triggered via localized reactions, and use this model to implement three basic gates (AND, OR, NOT) and a cascading mechanism. We develop an algorithm to automatically generate the layout of the circuit. We use a kinetic Monte Carlo algorithm to simulate circuit computations, and we analyze circuit complexity: our design scales linearly with formula size and has a logarithmic time complexity. Copyright © 2016 Elsevier Ireland Ltd. All rights reserved.
International Nuclear Information System (INIS)
Kraus, H.G.; Jones, J.L.
1986-01-01
The problem of non-linear superconducting magnet and electrical protection circuit system transients is formulated. To enable studying the effects of coil normalization transients, coil distortion (due to imbalanced magnetic forces), internal coil arcs and shorts, and other normal and off-normal circuit element responses, the following capabilities are included: temporal, voltage and current-dependent voltage sources, current sources, resistors, capacitors and inductors. The concept of self-mutual inductance, and the form of the associated inductance matrix, is discussed for internally shorted coils. This is a Kirchhoff's voltage loop law and Kirchhoff's current node law formulation. The non-linear integrodifferential equation set is solved via a unique hybrid finite difference/integral finite element technique. (author)
Instantons in Self-Organizing Logic Gates
Bearden, Sean R. B.; Manukian, Haik; Traversa, Fabio L.; Di Ventra, Massimiliano
2018-03-01
Self-organizing logic is a recently suggested framework that allows the solution of Boolean truth tables "in reverse"; i.e., it is able to satisfy the logical proposition of gates regardless to which terminal(s) the truth value is assigned ("terminal-agnostic logic"). It can be realized if time nonlocality (memory) is present. A practical realization of self-organizing logic gates (SOLGs) can be done by combining circuit elements with and without memory. By employing one such realization, we show, numerically, that SOLGs exploit elementary instantons to reach equilibrium points. Instantons are classical trajectories of the nonlinear equations of motion describing SOLGs and connect topologically distinct critical points in the phase space. By linear analysis at those points, we show that these instantons connect the initial critical point of the dynamics, with at least one unstable direction, directly to the final fixed point. We also show that the memory content of these gates affects only the relaxation time to reach the logically consistent solution. Finally, we demonstrate, by solving the corresponding stochastic differential equations, that, since instantons connect critical points, noise and perturbations may change the instanton trajectory in the phase space but not the initial and final critical points. Therefore, even for extremely large noise levels, the gates self-organize to the correct solution. Our work provides a physical understanding of, and can serve as an inspiration for, models of bidirectional logic gates that are emerging as important tools in physics-inspired, unconventional computing.
Vawter, G. Allen
2013-11-12
An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.
Multiple Independent Gate FETs: How Many Gates Do We Need?
Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni
2015-01-01
Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...
The design of a semi-custom intergrated circuit for the SLAC SLC timing control system
International Nuclear Information System (INIS)
Linstadt, E.
1985-01-01
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given
Design of a semi-custom integrated circuit for the SLAC SLC timing control system
International Nuclear Information System (INIS)
Linstadt, E.
1984-10-01
A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given
Ferri, Bonni H.; Ferri, Aldo A.; Majerich, David M.; Madden, Amanda G.
2016-01-01
This paper examines the effects of hands-on learning in an undergraduate circuits class that is taught to non-majors; i.e., students outside of electrical and computing engineering. The course, ECE3710, is taught in a blended format facilitated by the video lectures prepared for two Massive Open Online Courses developed for the Coursera Platform.…
Engineering integrated photonics for heralded quantum gates.
Meany, Thomas; Biggerstaff, Devon N; Broome, Matthew A; Fedrizzi, Alessandro; Delanty, Michael; Steel, M J; Gilchrist, Alexei; Marshall, Graham D; White, Andrew G; Withford, Michael J
2016-06-10
Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.
Engineering integrated photonics for heralded quantum gates
Meany, Thomas; Biggerstaff, Devon N.; Broome, Matthew A.; Fedrizzi, Alessandro; Delanty, Michael; Steel, M. J.; Gilchrist, Alexei; Marshall, Graham D.; White, Andrew G.; Withford, Michael J.
2016-06-01
Scaling up linear-optics quantum computing will require multi-photon gates which are compact, phase-stable, exhibit excellent quantum interference, and have success heralded by the detection of ancillary photons. We investigate the design, fabrication and characterisation of the optimal known gate scheme which meets these requirements: the Knill controlled-Z gate, implemented in integrated laser-written waveguide arrays. We show device performance to be less sensitive to phase variations in the circuit than to small deviations in the coupler reflectivity, which are expected given the tolerance values of the fabrication method. The mode fidelity is also shown to be less sensitive to reflectivity and phase errors than the process fidelity. Our best device achieves a fidelity of 0.931 ± 0.001 with the ideal 4 × 4 unitary circuit and a process fidelity of 0.680 ± 0.005 with the ideal computational-basis process.
CMOS gate array characterization procedures
Spratt, James P.
1993-09-01
Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.
Electronic devices and circuits
Pridham, Gordon John
1972-01-01
Electronic Devices and Circuits, Volume 3 provides a comprehensive account on electronic devices and circuits and includes introductory network theory and physics. The physics of semiconductor devices is described, along with field effect transistors, small-signal equivalent circuits of bipolar transistors, and integrated circuits. Linear and non-linear circuits as well as logic circuits are also considered. This volume is comprised of 12 chapters and begins with an analysis of the use of Laplace transforms for analysis of filter networks, followed by a discussion on the physical properties of
Hybdrid integral circuit for proportional chambers
International Nuclear Information System (INIS)
Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.
1978-01-01
Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture
Panda, D. K.; Lenka, T. R.
2017-06-01
An enhancement mode p-GaN gate AlGaN/GaN HEMT is proposed and a physics based virtual source charge model with Landauer approach for electron transport has been developed using Verilog-A and simulated using Cadence Spectre, in order to predict device characteristics such as threshold voltage, drain current and gate capacitance. The drain current model incorporates important physical effects such as velocity saturation, short channel effects like DIBL (drain induced barrier lowering), channel length modulation (CLM), and mobility degradation due to self-heating. The predicted I d-V ds, I d-V gs, and C-V characteristics show an excellent agreement with the experimental data for both drain current and capacitance which validate the model. The developed model was then utilized to design and simulate a single-pole single-throw (SPST) RF switch.
Marston, R M
1995-01-01
CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu
Structured-gate organic field-effect transistors
International Nuclear Information System (INIS)
Aljada, Muhsen; Pandey, Ajay K; Velusamy, Marappan; Burn, Paul L; Meredith, Paul; Namdas, Ebinazar B
2012-01-01
We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO 2 ) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends. (paper)
Structured-gate organic field-effect transistors
Aljada, Muhsen; Pandey, Ajay K.; Velusamy, Marappan; Burn, Paul L.; Meredith, Paul; Namdas, Ebinazar B.
2012-06-01
We report the fabrication and electrical characteristics of structured-gate organic field-effect transistors consisting of a gate electrode patterned with three-dimensional pillars. The pillar gate electrode was over-coated with a gate dielectric (SiO2) and solution processed organic semiconductors producing both unipolar p-type and bipolar behaviour. We show that this new structured-gate architecture delivers higher source-drain currents, higher gate capacitance per unit equivalent linear channel area, and enhanced charge injection (electrons and/or holes) versus the conventional planar structure in all modes of operation. For the bipolar field-effect transistor (FET) the maximum source-drain current enhancements in p- and n-channel mode were >600% and 28%, respectively, leading to p and n charge mobilities with the same order of magnitude. Thus, we have demonstrated that it is possible to use the FET architecture to manipulate and match carrier mobilities of material combinations where one charge carrier is normally dominant. Mobility matching is advantageous for creating organic logic circuit elements such as inverters and amplifiers. Hence, the method represents a facile and generic strategy for improving the performance of standard organic semiconductors as well as new materials and blends.
Nonlinear optics quantum computing with circuit QED.
Adhikari, Prabin; Hafezi, Mohammad; Taylor, J M
2013-02-08
One approach to quantum information processing is to use photons as quantum bits and rely on linear optical elements for most operations. However, some optical nonlinearity is necessary to enable universal quantum computing. Here, we suggest a circuit-QED approach to nonlinear optics quantum computing in the microwave regime, including a deterministic two-photon phase gate. Our specific example uses a hybrid quantum system comprising a LC resonator coupled to a superconducting flux qubit to implement a nonlinear coupling. Compared to the self-Kerr nonlinearity, we find that our approach has improved tolerance to noise in the qubit while maintaining fast operation.
A Low Noise Electronic Circuit
Annema, Anne J.; Leenaerts, Dominicus M.W.; de Vreede, Petrus W.H.
2002-01-01
An electronic circuit, which can be used as a Low Noise Amplifier (LNA), comprises two complementary Field Effect Transistors (M1, M2; M5, M6), each having a gate, a source and a drain. The gates are connected together as a common input terminal, and the drains are connected together as a
International Nuclear Information System (INIS)
Forno, Massimo Dal; Craievich, Paolo; Penco, Giuseppe; Vescovo, Roberto
2013-01-01
The front-end injection systems of the FERMI@Elettra linac produce high brightness electron beams that define the performance of the Free Electron Laser. The photoinjector mainly consists of the radiofrequency (rf) gun and of two S-band rf structures which accelerate the beam. Accelerating structures endowed with a single feed coupler cause deflection and degradation of the electron beam properties, due to the asymmetry of the electromagnetic field. In this paper, a new type of single feed structure with movable short-circuit is proposed. It has the advantage of having only one waveguide input, but we propose a novel design where the dipolar component is reduced. Moreover, the racetrack geometry allows to reduce the quadrupolar component. This paper presents the microwave design and the analysis of the particle motion inside the linac. A prototype has been machined at the Elettra facility to verify the new coupler design and the rf field has been measured by adopting the bead-pull method. The results are here presented, showing good agreement with the expectations
Dal Forno, Massimo; Craievich, Paolo; Penco, Giuseppe; Vescovo, Roberto
2013-11-01
The front-end injection systems of the FERMI@Elettra linac produce high brightness electron beams that define the performance of the Free Electron Laser. The photoinjector mainly consists of the radiofrequency (rf) gun and of two S-band rf structures which accelerate the beam. Accelerating structures endowed with a single feed coupler cause deflection and degradation of the electron beam properties, due to the asymmetry of the electromagnetic field. In this paper, a new type of single feed structure with movable short-circuit is proposed. It has the advantage of having only one waveguide input, but we propose a novel design where the dipolar component is reduced. Moreover, the racetrack geometry allows to reduce the quadrupolar component. This paper presents the microwave design and the analysis of the particle motion inside the linac. A prototype has been machined at the Elettra facility to verify the new coupler design and the rf field has been measured by adopting the bead-pull method. The results are here presented, showing good agreement with the expectations.
Isaak, S.; Bull, S.; Pitter, M. C.; Harrison, Ian.
2011-05-01
This paper reports on the development of a SPAD device and its subsequent use in an actively quenched single photon counting imaging system, and was fabricated in a UMC 0.18 μm CMOS process. A low-doped p- guard ring (t-well layer) encircling the active area to prevent the premature reverse breakdown. The array is a 16×1 parallel output SPAD array, which comprises of an active quenched SPAD circuit in each pixel with the current value being set by an external resistor RRef = 300 kΩ. The SPAD I-V response, ID was found to slowly increase until VBD was reached at excess bias voltage, Ve = 11.03 V, and then rapidly increase due to avalanche multiplication. Digital circuitry to control the SPAD array and perform the necessary data processing was designed in VHDL and implemented on a FPGA chip. At room temperature, the dark count was found to be approximately 13 KHz for most of the 16 SPAD pixels and the dead time was estimated to be 40 ns.
Nanofluidic Transistor Circuits
Chang, Hsueh-Chia; Cheng, Li-Jing; Yan, Yu; Slouka, Zdenek; Senapati, Satyajyoti
2012-02-01
Non-equilibrium ion/fluid transport physics across on-chip membranes/nanopores is used to construct rectifying, hysteretic, oscillatory, excitatory and inhibitory nanofluidic elements. Analogs to linear resistors, capacitors, inductors and constant-phase elements were reported earlier (Chang and Yossifon, BMF 2009). Nonlinear rectifier is designed by introducing intra-membrane conductivity gradient and by asymmetric external depletion with a reverse rectification (Yossifon and Chang, PRL, PRE, Europhys Lett 2009-2011). Gating phenomenon is introduced by functionalizing polyelectrolytes whose conformation is field/pH sensitive (Wang, Chang and Zhu, Macromolecules 2010). Surface ion depletion can drive Rubinstein's microvortex instability (Chang, Yossifon and Demekhin, Annual Rev of Fluid Mech, 2012) or Onsager-Wien's water dissociation phenomenon, leading to two distinct overlimiting I-V features. Bipolar membranes exhibit an S-hysteresis due to water dissociation (Cheng and Chang, BMF 2011). Coupling the hysteretic diode with some linear elements result in autonomous ion current oscillations, which undergo classical transitions to chaos. Our integrated nanofluidic circuits are used for molecular sensing, protein separation/concentration, electrospray etc.
TCAD analysis of short-circuit oscillations in IGBTs
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Iannuzzo, Francesco; Rahimo, Munaf
2017-01-01
Insulated-Gate Bipolar Transistors (IGBTs) exhibit a gate-voltage oscillation phenomenon during short-circuit, which can result in a gate-oxide breakdown. The oscillations have been investigated through device simulations and experimental investigations of a 3.3-kV IGBT. It has been found...... during short circuit....
Benchmarking gate-based quantum computers
Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans
2017-11-01
With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.
Gate Drive For High Speed, High Power IGBTs
Energy Technology Data Exchange (ETDEWEB)
Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; /SLAC
2007-06-18
A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3{micro}S with a rate of current rise of more than 10000A/{micro}S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt.
Gate Drive For High Speed, High Power IGBTs
International Nuclear Information System (INIS)
Nguyen, M.N.; Cassel, R.L.; de Lamare, J.E.; Pappas, G.C.; SLAC
2007-01-01
A new gate drive for high-voltage, high-power IGBTs has been developed for the SLAC NLC (Next Linear Collider) Solid State Induction Modulator. This paper describes the design and implementation of a driver that allows an IGBT module rated at 800A/3300V to switch up to 3000A at 2200V in 3(micro)S with a rate of current rise of more than 10000A/(micro)S, while still being short circuit protected. Issues regarding fast turn on, high de-saturation voltage detection, and low short circuit peak current will be presented. A novel approach is also used to counter the effect of unequal current sharing between parallel chips inside most high-power IGBT modules. It effectively reduces the collector-emitter peak current, and thus protects the IGBT from being destroyed during soft short circuit conditions at high di/dt
Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.
2016-01-01
Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868
Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J
2016-03-01
Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.
Relaxation oscillation logic in Josephson junction circuits
International Nuclear Information System (INIS)
Fulton, T.A.
1981-01-01
A dc powered, self-resetting Josephson junction logic circuit relying on relaxation oscillations is described. A pair of Josephson junction gates are connected in series, a first shunt is connected in parallel with one of the gates, and a second shunt is connected in parallel with the series combination of gates. The resistance of the shunts and the dc bias current bias the gates so that they are capable of undergoing relaxation oscillations. The first shunt forms an output line whereas the second shunt forms a control loop. The bias current is applied to the gates so that, in the quiescent state, the gate in parallel with the second shunt is at V O, and the other gate is undergoing relaxation oscillations. By controlling the state of the first gate with the current in the output loop of another identical circuit, the invert function is performed
Miniaturization of Josephson logic circuits
International Nuclear Information System (INIS)
Ko, H.; Van Duzer, T.
1985-01-01
The performances of Current Injection Logic (CIL) and Resistor Coupled Josephson Logic (RCJL) have been evaluated for minimum features sizes ranging from 5 μm to 0.2 μm. The logic delay is limited to about 10 ps for both the CIL AND gate and the RCJL OR gate biased at 70% of maximum bias current. The maximum circuit count on an 6.35 x 6.35 chip is 13,000 for CIL gates and 20,000 for RCJL gates. Some suggestions are given for further improvements
Analogue Building Blocks Based on Digital CMOS Gates
DEFF Research Database (Denmark)
Mucha, Igor
1996-01-01
Low-performance analogue circuits built of digital MOS gates are presented. Depending on the threshold voltages of the technology used the final circuits can be operated using low supply voltages. The main advantage using the proposed circuits is the simplicity and ultimate compatibility...... with the design of digital circuits....
Upper bounds for reversible circuits based on Young subgroups
DEFF Research Database (Denmark)
Abdessaied, Nabila; Soeken, Mathias; Thomsen, Michael Kirkedal
2014-01-01
We present tighter upper bounds on the number of Toffoli gates needed in reversible circuits. Both multiple controlled Toffoli gates and mixed polarity Toffoli gates have been considered for this purpose. The calculation of the bounds is based on a synthesis approach based on Young subgroups...... that results in circuits using a more generalized gate library. Starting from an upper bound for this library we derive new bounds which improve the existing bound by around 77%....
Characterization of a Common-Gate Amplifier Using Ferroelectric Transistors
Hunt, Mitchell; Sayyah, Rana; MacLeod, Todd C.; Ho, Fat D.
2011-01-01
In this paper, the empirical data collected through experiments performed using a FeFET in the common-gate amplifier circuit is presented. The FeFET common-gate amplifier was characterized by varying all parameters in the circuit, such as load resistance, biasing of the transistor, and input voltages. Due to the polarization of the ferroelectric layer, the particular behavior of the FeFET common-gate amplifier presents interesting results. Furthermore, the differences between a FeFET common-gate amplifier and a MOSFET common-gate amplifier are examined.
Unstable oscillators based hyperchaotic circuit
DEFF Research Database (Denmark)
Murali, K.; Tamasevicius, A.; G. Mykolaitis, A.
1999-01-01
A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations in the circ...... in the circuit. The performance of the circuit is investigated by means of numerical integration of appropriate differential equations, PSPICE simulations, and hardware experiment.......A simple 4th order hyperchaotic circuit with unstable oscillators is described. The circuit contains two negative impedance converters, two inductors, two capacitors, a linear resistor and a diode. The Lyapunov exponents are presented to confirm hyperchaotic nature of the oscillations...
Hickman, Ian
2013-01-01
Analog Circuits Cookbook presents articles about advanced circuit techniques, components and concepts, useful IC for analog signal processing in the audio range, direct digital synthesis, and ingenious video op-amp. The book also includes articles about amplitude measurements on RF signals, linear optical imager, power supplies and devices, and RF circuits and techniques. Professionals and students of electrical engineering will find the book informative and useful.
International Nuclear Information System (INIS)
Khitun, Alexander; Bao Mingqiang; Wang, Kang L
2010-01-01
We describe and analyse possible approaches to magnonic logic circuits and basic elements required for circuit construction. A distinctive feature of the magnonic circuitry is that information is transmitted by spin waves propagating in the magnetic waveguides without the use of electric current. The latter makes it possible to exploit spin wave phenomena for more efficient data transfer and enhanced logic functionality. We describe possible schemes for general computing and special task data processing. The functional throughput of the magnonic logic gates is estimated and compared with the conventional transistor-based approach. Magnonic logic circuits allow scaling down to the deep submicrometre range and THz frequency operation. The scaling is in favour of the magnonic circuits offering a significant functional advantage over the traditional approach. The disadvantages and problems of the spin wave devices are also discussed.
Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi
2016-04-01
Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.
Realistic Realizations Of Threshold Circuits
Razavi, Hassan M.
1987-08-01
Threshold logic, in which each input is weighted, has many theoretical advantages over the standard gate realization, such as reducing the number of gates, interconnections, and power dissipation. However, because of the difficult synthesis procedure and complicated circuit implementation, their use in the design of digital systems is almost nonexistant. In this study, three methods of NMOS realizations are discussed, and their advantages and shortcomings are explored. Also, the possibility of using the methods to realize multi-valued logic is examined.
Sketoe, J. G.; Clark, Anthony
2000-01-01
This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.
A high performance gate drive for large gate turn off thyristors
Energy Technology Data Exchange (ETDEWEB)
Szilagyi, C.P.
1993-01-01
Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing
Graf, Rudolf F
1996-01-01
This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings
Superconducting resonators as beam splitters for linear-optics quantum computation.
Chirolli, Luca; Burkard, Guido; Kumar, Shwetank; Divincenzo, David P
2010-06-11
We propose and analyze a technique for producing a beam-splitting quantum gate between two modes of a ring-resonator superconducting cavity. The cavity has two integrated superconducting quantum interference devices (SQUIDs) that are modulated by applying an external magnetic field. The gate is accomplished by applying a radio frequency pulse to one of the SQUIDs at the difference of the two mode frequencies. Departures from perfect beam splitting only arise from corrections to the rotating wave approximation; an exact calculation gives a fidelity of >0.9992. Our construction completes the toolkit for linear-optics quantum computing in circuit quantum electrodynamics.
Digital Circuit Analysis Using an 8080 Processor.
Greco, John; Stern, Kenneth
1983-01-01
Presents the essentials of a program written in Intel 8080 assembly language for the steady state analysis of a combinatorial logic gate circuit. Program features and potential modifications are considered. For example, the program could also be extended to include clocked/unclocked sequential circuits. (JN)
Solid state circuit controls direction, speed, and braking of dc motor
Hanna, M. F.
1966-01-01
Full-wave bridge rectifier circuit controls the direction, speed, and braking of a dc motor. Gating in the circuit of Silicon Controlled Rectifiers /SCRS/ controls output polarity and braking is provided by an SCR that is gated to short circuit the reverse voltage generated by reversal of motor rotation.
International Nuclear Information System (INIS)
Cui, Wen-Xue; Hu, Shi; Wang, Hong-Fu; Zhu, Ai-Dong; Zhang, Shou
2015-01-01
The direct implementation of multiqubit controlled phase gate of photons is appealing and important for reducing the complexity of the physical realization of linear-optics-based practical quantum computer and quantum algorithms. In this letter we propose a nondestructive scheme for implementing an N-qubit controlled phase gate of photons with a high success probability. The gate can be directly implemented with the self-designed quantum encoder circuits, which are probabilistic optical quantum entangler devices and can be achieved using linear optical elements, single-photon superposition state, and quantum dot coupled to optical microcavity. The calculated results indicate that both the success probabilities of the quantum encoder circuit and the N-qubit controlled phase gate in our scheme are higher than those in the previous schemes. We also consider the effects of the side leakage and cavity loss on the success probability and the fidelity of the quantum encoder circuit for a realistic quantum-dot-microcavity coupled system. (letter)
Nanoeletromechanical switch and logic circuits formed therefrom
Nordquist, Christopher D [Albuquerque, NM; Czaplewski, David A [Albuquerque, NM
2010-05-18
A nanoelectromechanical (NEM) switch is formed on a substrate with a source electrode containing a suspended electrically-conductive beam which is anchored to the substrate at each end. This beam, which can be formed of ruthenium, bows laterally in response to a voltage applied between a pair of gate electrodes and the source electrode to form an electrical connection between the source electrode and a drain electrode located near a midpoint of the beam. Another pair of gate electrodes and another drain electrode can be located on an opposite side of the beam to allow for switching in an opposite direction. The NEM switch can be used to form digital logic circuits including NAND gates, NOR gates, programmable logic gates, and SRAM and DRAM memory cells which can be used in place of conventional CMOS circuits, or in combination therewith.
Logarithmic current-measuring transistor circuits
DEFF Research Database (Denmark)
Højberg, Kristian Søe
1967-01-01
Describes two transistorized circuits for the logarithmic measurement of small currents suitable for nuclear reactor instrumentation. The logarithmic element is applied in the feedback path of an amplifier, and only one dual transistor is used as logarithmic diode and temperature compensating...... transistor. A simple one-amplifier circuit is compared with a two-amplifier system. The circuits presented have been developed in connexion with an amplifier using a dual m.o.s. transistor input stage with diode-protected gates....
Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee
2014-10-01
The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.
International Nuclear Information System (INIS)
Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung
2014-01-01
The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)
International Nuclear Information System (INIS)
Dyukov, L.V.; Fedorov, A.F.; Terekhov, V.F.
1977-01-01
The circuit and design of a modulator at pulse power of 15 MW and average power of 300 kW, intended for supplying a klystron generator, are described. The modulator is designed for operating in a lengthy mode. The capacitance storage-former is made in the form of three parallel sections of artificial shaping lines in order to lower the specific loads on the elements of the shaping line and thyristors. The thyristor spark gaps are made in the form of a unified water-cooled assembly composed of 12 series TD-320 thyristors. An assessment of the modulator reliability has shown that the average time-to-fault is 800 hr. Modulator tests confirm that the choice of the circuit solution is correct. The modulator total efficiency equals to approximately 0.9
Energy Technology Data Exchange (ETDEWEB)
Datta, Deepanjan [Department of Electrical and Computer Engineering, Purdue University, West Lafayette, IN 47906 (United States); Ganguly, Samiran [Department of Electronics Engineering, Indian School of Mines, Dhanbad-826004 (India); Dasgupta, S [Department of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee-247667 (India)
2007-05-30
Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p{sup +} poly-n{sup +} poly-p{sup +} poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime.
International Nuclear Information System (INIS)
Datta, Deepanjan; Ganguly, Samiran; Dasgupta, S
2007-01-01
Large band-to-band tunnelling (BTBT) and gate leakage current can limit scalability of nanoscale devices. In this paper, we have proposed a novel nanoscale parallel connected heteromaterial double gate (PCHEM-DG) architecture with triple metal gate which significantly suppress BTBT leakage, making it efficient for low power design in the sub-10 nm regime. We have also proposed a triple gate device with p + poly-n + poly-p + poly gate which has substantially low gate leakage over symmetric DG MOSFET. Simulations are performed using a 2D Poisson-Schroedinger simulator and verified with a 2D device simulator ATLAS. We conclude that, due to intrinsic body doping, negligible gate leakage, suppressed BTBT over symmetric DG devices, metal gate (MG) PCHEM-DG MOSFET is efficient for low power circuit design in the nanometre regime
Full Digital Short Circuit Protection for Advanced IGBTs
谷村, 拓哉; 湯浅, 一史; 大村, 一郎
2011-01-01
A full digital short circuit protection method for advanced IGBTs has been proposed and experimentally demonstrated for the first time. The method employs combination of digital circuit, the gate charge sense instead of the conventional sense IGBT and analog circuit configuration. Digital protection scheme has significant advantages in thevprotection speed and flexibility.
Hardening Logic Encryption against Key Extraction Attacks with Circuit Camouflage
2017-03-01
camouflage; obfuscation; SAT; key extraction; reverse engineering ; security; trusted electronics Introduction Integrated Circuit (IC) designs are... Circuit camouflage is hardware obfuscation technology that prevents reverse engineering of a fabricated device by utilizing a relatively small...obfuscated with circuit camouflage technology, this type of attack becomes much more difficult because a reverse engineer cannot extract a gate- level
Gate-keeper module for TANSY-KM5
International Nuclear Information System (INIS)
Rydz, R.; Norberg, L.; Urholm, L.; Grosshoeg, G.
1991-01-01
The purpose of the Gate-keeper is the control of the RDCs, the ADCs, and the constant fraction discriminator. The Gate-keeper synchronizes the units and ensures that the data taking is clean and not intermixed with other events. There are six Gate-Keepers in the system, one for each proton detector. All input circuits are designed to accept TTL as well as negative NIM signals. The output is 50 ohm TTL or negative NIM as defined by internal jumpers
Quantum computer gate simulations | Dada | Journal of the Nigerian ...
African Journals Online (AJOL)
A new interactive simulator for Quantum Computation has been developed for simulation of the universal set of quantum gates and for construction of new gates of up to 3 qubits. The simulator also automatically generates an equivalent quantum circuit for any arbitrary unitary transformation on a qubit. Available quantum ...
A low-power, CMOS peak detect and hold circuit for nuclear pulse spectroscopy
International Nuclear Information System (INIS)
Ericson, M.N.; Simpson, M.L.; Britton, C.L.; Allen, M.D.; Kroeger, R.A.; Inderhees, S.E.
1994-01-01
A low-power CMOS peak detecting track and hold circuit optimized for nuclear pulse spectroscopy is presented. The circuit topology eliminates the need for a rectifying diode, reducing the effect of charge injection into the hold capacitor, incorporates a linear gate at the input to prevent pulse pileup, and uses dynamic bias control that minimizes both pedestal and droop. Both positive-going and negative-going pulses are accommodated using a complementary set of track and hold circuits. Full characterization of the design fabricated in 1.2μm CMOS including dynamic range, integral nonlinearity, droop rate, pedestal, and power measurements is presented. Additionally, analysis and design approaches for optimization of operational characteristics are discussed
Designing Novel Quaternary Quantum Reversible Subtractor Circuits
Haghparast, Majid; Monfared, Asma Taheri
2018-01-01
Reversible logic synthesis is an important area of current research because of its ability to reduce energy dissipation. In recent years, multiple valued logic has received great attention due to its ability to reduce the width of the reversible circuit which is a main requirement in quantum technology. Subtractor circuits are between major components used in quantum computers. In this paper, we will discuss the design of a quaternary quantum reversible half subtractor circuit using quaternary 1-qudit, 2-qudit Muthukrishnan-Stroud and 3-qudit controlled gates and a 2-qudit Generalized quaternary gate. Then a design of a quaternary quantum reversible full subtractor circuit based on the quaternary half subtractor will be presenting. The designs shall then be evaluated in terms of quantum cost, constant input, garbage output, and hardware complexity. The proposed quaternary quantum reversible circuits are the first attempt in the designing of the aforementioned subtractor.
Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator
Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro
2018-02-01
The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.
Investigation of Impact of the Gate Circuitry on IGBT Transistor Dynamic Parameters
Directory of Open Access Journals (Sweden)
Vytautas Bleizgys
2011-03-01
Full Text Available The impact of Insulated Gate Bipolar Transistor driver circuit parameters on the rise and fall time of the collector current and voltage collector-emitter was investigated. The influence of transistor driver circuit parameters on heating of Insulated Gate Bipolar Transistors was investigated as well.Article in Lithuanian
Protected gates for topological quantum field theories
International Nuclear Information System (INIS)
Beverland, Michael E.; Pastawski, Fernando; Preskill, John; Buerschaper, Oliver; Koenig, Robert; Sijher, Sumit
2016-01-01
We study restrictions on locality-preserving unitary logical gates for topological quantum codes in two spatial dimensions. A locality-preserving operation is one which maps local operators to local operators — for example, a constant-depth quantum circuit of geometrically local gates, or evolution for a constant time governed by a geometrically local bounded-strength Hamiltonian. Locality-preserving logical gates of topological codes are intrinsically fault tolerant because spatially localized errors remain localized, and hence sufficiently dilute errors remain correctable. By invoking general properties of two-dimensional topological field theories, we find that the locality-preserving logical gates are severely limited for codes which admit non-abelian anyons, in particular, there are no locality-preserving logical gates on the torus or the sphere with M punctures if the braiding of anyons is computationally universal. Furthermore, for Ising anyons on the M-punctured sphere, locality-preserving gates must be elements of the logical Pauli group. We derive these results by relating logical gates of a topological code to automorphisms of the Verlinde algebra of the corresponding anyon model, and by requiring the logical gates to be compatible with basis changes in the logical Hilbert space arising from local F-moves and the mapping class group
Divide and control: split design of multi-input DNA logic gates.
Gerasimova, Yulia V; Kolpashchikov, Dmitry M
2015-01-18
Logic gates made of DNA have received significant attention as biocompatible building blocks for molecular circuits. The majority of DNA logic gates, however, are controlled by the minimum number of inputs: one, two or three. Here we report a strategy to design a multi-input logic gate by splitting a DNA construct.
Linear-Optical Generation of Eigenstates of the Two-Site XY Model
Directory of Open Access Journals (Sweden)
Stefanie Barz
2015-04-01
Full Text Available Much of the anticipation accompanying the development of a quantum computer relates to its application to simulating dynamics of another quantum system of interest. Here, we study the building blocks for simulating quantum spin systems with linear optics. We experimentally generate the eigenstates of the XY Hamiltonian under an external magnetic field. The implemented quantum circuit consists of two cnot gates, which are realized experimentally by harnessing entanglement from a photon source and applying a cphase gate. We tune the ratio of coupling constants and the magnetic field by changing local parameters. This implementation of the XY model using linear quantum optics might open the door to future studies of quenching dynamics using linear optics.
Linearization Method and Linear Complexity
Tanaka, Hidema
We focus on the relationship between the linearization method and linear complexity and show that the linearization method is another effective technique for calculating linear complexity. We analyze its effectiveness by comparing with the logic circuit method. We compare the relevant conditions and necessary computational cost with those of the Berlekamp-Massey algorithm and the Games-Chan algorithm. The significant property of a linearization method is that it needs no output sequence from a pseudo-random number generator (PRNG) because it calculates linear complexity using the algebraic expression of its algorithm. When a PRNG has n [bit] stages (registers or internal states), the necessary computational cost is smaller than O(2n). On the other hand, the Berlekamp-Massey algorithm needs O(N2) where N(≅2n) denotes period. Since existing methods calculate using the output sequence, an initial value of PRNG influences a resultant value of linear complexity. Therefore, a linear complexity is generally given as an estimate value. On the other hand, a linearization method calculates from an algorithm of PRNG, it can determine the lower bound of linear complexity.
A new quantum flux parametron logic gate with large input margin
International Nuclear Information System (INIS)
Hioe, W.; Hosoya, M.; Goto, E.
1991-01-01
This paper reports on the Quantum Flux Parametron (QFP) which is a flux transfer, flux activated Josephson logic device which realizes much lower power dissipation than other Josephson logic devices. Being a two-terminal device its correct operation may be affected by coupling to other QFPs. The problems include backcoupling from active QFPs through inactive QFPs (relay noise), coupling between QFPs activated at different times because of clock skew (homophase noise), and interaction between active QFPs (reaction hazard). Previous QFP circuits worked by wired-majority, which being a linear input logic, has low input margin. A new logic gate (D-gate) using a QFP to perform logic operations has been analyzed and tested by computer simulation. Relay noise, homophase noise and reaction hazard are substantially reduced. Moreover, the input have little interaction hence input margin is greatly improved
CMOS Active-Pixel Image Sensor With Simple Floating Gates
Fossum, Eric R.; Nakamura, Junichi; Kemeny, Sabrina E.
1996-01-01
Experimental complementary metal-oxide/semiconductor (CMOS) active-pixel image sensor integrated circuit features simple floating-gate structure, with metal-oxide/semiconductor field-effect transistor (MOSFET) as active circuit element in each pixel. Provides flexibility of readout modes, no kTC noise, and relatively simple structure suitable for high-density arrays. Features desirable for "smart sensor" applications.
Logic circuits from zero forcing.
Burgarth, Daniel; Giovannetti, Vittorio; Hogben, Leslie; Severini, Simone; Young, Michael
We design logic circuits based on the notion of zero forcing on graphs; each gate of the circuits is a gadget in which zero forcing is performed. We show that such circuits can evaluate every monotone Boolean function. By using two vertices to encode each logical bit, we obtain universal computation. We also highlight a phenomenon of "back forcing" as a property of each function. Such a phenomenon occurs in a circuit when the input of gates which have been already used at a given time step is further modified by a computation actually performed at a later stage. Finally, we show that zero forcing can be also used to implement reversible computation. The model introduced here provides a potentially new tool in the analysis of Boolean functions, with particular attention to monotonicity. Moreover, in the light of applications of zero forcing in quantum mechanics, the link with Boolean functions may suggest a new directions in quantum control theory and in the study of engineered quantum spin systems. It is an open technical problem to verify whether there is a link between zero forcing and computation with contact circuits.
Fermionic models with superconducting circuits
Energy Technology Data Exchange (ETDEWEB)
Las Heras, Urtzi; Garcia-Alvarez, Laura; Mezzacapo, Antonio; Lamata, Lucas [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); Solano, Enrique [University of the Basque Country UPV/EHU, Department of Physical Chemistry, Bilbao (Spain); IKERBASQUE, Basque Foundation for Science, Bilbao (Spain)
2015-12-01
We propose a method for the efficient quantum simulation of fermionic systems with superconducting circuits. It consists in the suitable use of Jordan-Wigner mapping, Trotter decomposition, and multiqubit gates, be with the use of a quantum bus or direct capacitive couplings. We apply our method to the paradigmatic cases of 1D and 2D Fermi-Hubbard models, involving couplings with nearest and next-nearest neighbours. Furthermore, we propose an optimal architecture for this model and discuss the benchmarking of the simulations in realistic circuit quantum electrodynamics setups. (orig.)
Analysis of High Power IGBT Short Circuit Failures
Energy Technology Data Exchange (ETDEWEB)
Pappas, G.
2005-02-11
The Next Linear Collider (NLC) accelerator proposal at SLAC requires a highly efficient and reliable, low cost, pulsed-power modulator to drive the klystrons. A solid-state induction modulator has been developed at SLAC to power the klystrons; this modulator uses commercial high voltage and high current Insulated Gate Bipolar Transistor (IGBT) modules. Testing of these IGBT modules under pulsed conditions was very successful; however, the IGBTs failed when tests were performed into a low inductance short circuit. The internal electrical connections of a commercial IGBT module have been analyzed to extract self and mutual partial inductances for the main current paths as well as for the gate structure. The IGBT module, together with the partial inductances, has been modeled using PSpice. Predictions for electrical paths that carry the highest current correlate with the sites of failed die under short circuit tests. A similar analysis has been carried out for a SLAC proposal for an IGBT module layout. This paper discusses the mathematical model of the IGBT module geometry and presents simulation results.
Resonance circuits for adiabatic circuits
Directory of Open Access Journals (Sweden)
C. Schlachta
2003-01-01
Full Text Available One of the possible techniques to reduces the power consumption in digital CMOS circuits is to slow down the charge transport. This slowdown can be achieved by introducing an inductor in the charging path. Additionally, the inductor can act as an energy storage element, conserving the energy that is normally dissipated during discharging. Together with the parasitic capacitances from the circuit a LCresonant circuit is formed.
A spiking neuron circuit based on a carbon nanotube transistor
International Nuclear Information System (INIS)
Chen, C-L; Kim, K; Truong, Q; Shen, A; Li, Z; Chen, Y
2012-01-01
A spiking neuron circuit based on a carbon nanotube (CNT) transistor is presented in this paper. The spiking neuron circuit has a crossbar architecture in which the transistor gates are connected to its row electrodes and the transistor sources are connected to its column electrodes. An electrochemical cell is incorporated in the gate of the transistor by sandwiching a hydrogen-doped poly(ethylene glycol)methyl ether (PEG) electrolyte between the CNT channel and the top gate electrode. An input spike applied to the gate triggers a dynamic drift of the hydrogen ions in the PEG electrolyte, resulting in a post-synaptic current (PSC) through the CNT channel. Spikes input into the rows trigger PSCs through multiple CNT transistors, and PSCs cumulate in the columns and integrate into a ‘soma’ circuit to trigger output spikes based on an integrate-and-fire mechanism. The spiking neuron circuit can potentially emulate biological neuron networks and their intelligent functions. (paper)
High linearity current communicating passive mixer employing a simple resistor bias
International Nuclear Information System (INIS)
Liu Rongjiang; Guo Guiliang; Yan Yuepeng
2013-01-01
A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier (TIA) is introduced. It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell. The optimum linearity and the maximum symmetric switching operation are obtained at the same time. The mixer is implemented in a 0.25 μm CMOS process. The test shows that it achieves an input third-order intercept point of 13.32 dBm, conversion gain of 5.52 dB, and a single sideband noise figure of 20 dB. (semiconductor integrated circuits)
Hood, John Linsley
2013-01-01
The Art of Linear Electronics presents the principal aspects of linear electronics and techniques in linear electronic circuit design. The book provides a wide range of information on the elucidation of the methods and techniques in the design of linear electronic circuits. The text discusses such topics as electronic component symbols and circuit drawing; passive and active semiconductor components; DC and low frequency amplifiers; and the basic effects of feedback. Subjects on frequency response modifying circuits and filters; audio amplifiers; low frequency oscillators and waveform generato
Qin, Wei; Wang, Xin; Miranowicz, Adam; Zhong, Zhirong; Nori, Franco
2017-07-01
Heralded near-deterministic multiqubit controlled-phase gates with integrated error detection have recently been proposed by Borregaard et al. [Phys. Rev. Lett. 114, 110502 (2015), 10.1103/PhysRevLett.114.110502]. This protocol is based on a single four-level atom (a heralding quartit) and N three-level atoms (operational qutrits) coupled to a single-resonator mode acting as a cavity bus. Here we generalize this method for two distant resonators without the cavity bus between the heralding and operational atoms. Specifically, we analyze the two-qubit controlled-Z gate and its multiqubit-controlled generalization (i.e., a Toffoli-like gate) acting on the two-lowest levels of N qutrits inside one resonator, with their successful actions being heralded by an auxiliary microwave-driven quartit inside the other resonator. Moreover, we propose a circuit-quantum-electrodynamics realization of the protocol with flux and phase qudits in linearly coupled transmission-line resonators with dissipation. These methods offer a quadratic fidelity improvement compared to cavity-assisted deterministic gates.
Energy Technology Data Exchange (ETDEWEB)
Senthilkumar, S [Madurai Medical College ' Govt. Rajaji Hospital, Madurai (India)
2014-06-01
Purpose: The main purpose of this work was to develop an in-house low cost respiratory motion phantom platform for testing the accuracy of the gated radiotherapy system and analyze the dosimetric difference during gated radiotherapy. Methods: An in-house respiratory motion platform(RMP) was designed and constructed for testing the targeting accuracy of respiratory tracking system. The RMP consist of acrylic Chest Wall Platform, 2 DC motors, 4 IR sensors, speed controller circuit, 2 LED and 2 moving rods inside the RMP. The velocity of the movement can be varied from 0 to 30 cycles per minute. The platform mounted to a base using precision linear bearings. The base and platform are made of clear, 15mm thick polycarbonate plastic and the linear ball bearings are oriented to restrict the platform to a movement of approximately 50mm up and down with very little friction. Results: The targeting accuracy of the respiratory tracking system was evaluated using phantom with and without respiratory movement with varied amplitude. We have found the 5% dose difference to the PTV during the movement in comparison with stable PTV. The RMP can perform sinusoidal motion in 1D with fixed peak to peak motion of 5 to 50mm and cycle interval from 2 to 6 seconds. The RMP was designed to be able to simulate the gross anatomical anterior posterior motion attributable to respiration-induced motion of the thoracic region. Conclusion: The unique RMP simulates breathing providing the means to create a comprehensive program for commissioning, training, quality assurance and dose verification of gated radiotherapy treatments. Create the anterior/posterior movement of a target over a 5 to 50 mm distance to replicate tumor movement. The targeting error of the respiratory tracking system is less than 1.0 mm which shows suitable for clinical treatment with highly performance.
International Nuclear Information System (INIS)
Senthilkumar, S
2014-01-01
Purpose: The main purpose of this work was to develop an in-house low cost respiratory motion phantom platform for testing the accuracy of the gated radiotherapy system and analyze the dosimetric difference during gated radiotherapy. Methods: An in-house respiratory motion platform(RMP) was designed and constructed for testing the targeting accuracy of respiratory tracking system. The RMP consist of acrylic Chest Wall Platform, 2 DC motors, 4 IR sensors, speed controller circuit, 2 LED and 2 moving rods inside the RMP. The velocity of the movement can be varied from 0 to 30 cycles per minute. The platform mounted to a base using precision linear bearings. The base and platform are made of clear, 15mm thick polycarbonate plastic and the linear ball bearings are oriented to restrict the platform to a movement of approximately 50mm up and down with very little friction. Results: The targeting accuracy of the respiratory tracking system was evaluated using phantom with and without respiratory movement with varied amplitude. We have found the 5% dose difference to the PTV during the movement in comparison with stable PTV. The RMP can perform sinusoidal motion in 1D with fixed peak to peak motion of 5 to 50mm and cycle interval from 2 to 6 seconds. The RMP was designed to be able to simulate the gross anatomical anterior posterior motion attributable to respiration-induced motion of the thoracic region. Conclusion: The unique RMP simulates breathing providing the means to create a comprehensive program for commissioning, training, quality assurance and dose verification of gated radiotherapy treatments. Create the anterior/posterior movement of a target over a 5 to 50 mm distance to replicate tumor movement. The targeting error of the respiratory tracking system is less than 1.0 mm which shows suitable for clinical treatment with highly performance
Electronic circuit encyclopedia 2
International Nuclear Information System (INIS)
Park, Sun Ho
1992-10-01
This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.
Electronic circuit encyclopedia 2
Energy Technology Data Exchange (ETDEWEB)
Park, Sun Ho
1992-10-15
This book is composed of 15 chapters, which are amplification of weak signal and measurement circuit audio control and power amplification circuit, data transmission and wireless system, forwarding and isolation, signal converting circuit, counter and comparator, discriminator circuit, oscillation circuit and synthesizer, digital and circuit on computer image processing circuit, sensor drive circuit temperature sensor circuit, magnetic control and application circuit, motor driver circuit, measuring instrument and check tool and power control and stability circuit.
Packaging Solutions for Mitigating IGBT Short-Circuit Instabilities
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Iannuzzo, Francesco; Blaabjerg, Frede
2017-01-01
In this paper, the gate voltage oscillations occurring under short-circuit conditions in Insulated-Gate Bipolar Transistors are investigated, together with their dependency with respect to stray inductance variations. By using AnSYS Q3D Extractor, electromagnetic simulations are conducted to extr...
Gate Engineering in SOI LDMOS for Device Reliability
Directory of Open Access Journals (Sweden)
Aanand
2016-01-01
Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..
A parity checker circuit based on microelectromechanical resonator logic elements
Energy Technology Data Exchange (ETDEWEB)
Hafiz, Md Abdullah Al, E-mail: abdullah.hafiz@kaust.edu.sa [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Li, Ren [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Younis, Mohammad I. [PSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia); Fariborzi, Hossein [CEMSE Division, King Abdullah University of Science and Technology, Thuwal (Saudi Arabia)
2017-03-03
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized. - Highlights: • A 4-bit parity checker circuit is proposed and demonstrated based on MEMS resonator based logic elements. • Multiple copies of MEMS resonator based XOR logic gates are used to construct a complex logic circuit. • Functionality and feasibility of micro-resonator based logic platform is demonstrated.
Real-time reconfigurable devices implemented in UV-light programmable floating-gate CMOS
Energy Technology Data Exchange (ETDEWEB)
Aunet, Snorre
2002-06-01
This dissertation describes using theory, computer simulations and laboratory measurements a new class of real time reconfigurable UV-programmable floating-gate circuits operating with current levels typically in the pA to {mu}A range, implemented in a standard double-poly CMOS technology. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I/O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components. Compared to earlier FGUVMOS approaches the number of transistors for implementing the CARRY' of a FULL-ADDER is reduced from 22 to 2. A complete FULL-ADDER can be implemented using only 8 transistors. 2-MOSFET circuits able to implement CARRY', NOR, NAND and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. An 8-transistor FULL-ADDER might use 2500 times less energy than a FULL-ADDER implemented using standard cells in the same 0.6 {mu}m CMOS technology while running at 1 MHz. The circuits are also shown to be a new class of linear threshold elements, which is the basic building blocks of neural networks. Theory is developed as a help in the design of floating-gate circuits.
Circuit arrangement of an electronic component for the design of fail-safe protective circuits
International Nuclear Information System (INIS)
Centmaier, W.; Bernhard, U.; Friederich, B.; Heisecke, I.
1974-01-01
The critical parameters of reactors are controlled by safety circuits. These circuits are controlled designed as logic modules operating by the 'n-out-of-m' selection principle. In most cases, a combination of a '1-out-of-3' circuit with a '2-out-of-3' circuit and separate indication is sufficient for a dynamic fail-safe circuit. The basic logic elements are AND and OR gate circuits, respectively, which are triggered by pulse trains and in which the failure of a pulse train is indicated as an error at the output. The module allows the design of safety circuits offering various degrees of safety. If the indication of an error is made on the modules, faulty components can be exchanged by the maintenance crew right away. (DG) [de
Displacement measurement system for linear array detector
International Nuclear Information System (INIS)
Zhang Pengchong; Chen Ziyu; Shen Ji
2011-01-01
It presents a set of linear displacement measurement system based on encoder. The system includes displacement encoders, optical lens and read out circuit. Displacement read out unit includes linear CCD and its drive circuit, two amplifier circuits, second order Butterworth low-pass filter and the binarization circuit. The coding way is introduced, and various parts of the experimental signal waveforms are given, and finally a linear experimental test results are given. The experimental results are satisfactory. (authors)
GS Department
2009-01-01
Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department
An algebraic approach to linear-optical schemes for deterministic quantum computing
International Nuclear Information System (INIS)
Aniello, Paolo; Cagli, Ruben Coen
2005-01-01
Linear-optical passive (LOP) devices and photon counters are sufficient to implement universal quantum computation with single photons, and particular schemes have already been proposed. In this paper we discuss the link between the algebraic structure of LOP transformations and quantum computing. We first show how to decompose the Fock space of N optical modes in finite-dimensional subspaces that are suitable for encoding strings of qubits and invariant under LOP transformations (these subspaces are related to the spaces of irreducible unitary representations of U (N). Next we show how to design in algorithmic fashion LOP circuits which implement any quantum circuit deterministically. We also present some simple examples, such as the circuits implementing a cNOT gate and a Bell state generator/analyser
Modeling a verification test system for mixed-signal circuits
San Segundo Bello, D.; Tangelder, R.J.W.T.; Kerkhoff, Hans G.
In contrast to the large number of logic gates and storage circuits encountered in digital networks, purely analog networks usually have relatively few circuit primitives (operational amplifiers and so on). The complexity lies not in the number of building blocks but in the complexity of each block
Enabling complex genetic circuits to respond to extrinsic environmental signals.
Hoynes-O'Connor, Allison; Shopera, Tatenda; Hinman, Kristina; Creamer, John Philip; Moon, Tae Seok
2017-07-01
Genetic circuits have the potential to improve a broad range of metabolic engineering processes and address a variety of medical and environmental challenges. However, in order to engineer genetic circuits that can meet the needs of these real-world applications, genetic sensors that respond to relevant extrinsic and intrinsic signals must be implemented in complex genetic circuits. In this work, we construct the first AND and NAND gates that respond to temperature and pH, two signals that have relevance in a variety of real-world applications. A previously identified pH-responsive promoter and a temperature-responsive promoter were extracted from the E. coli genome, characterized, and modified to suit the needs of the genetic circuits. These promoters were combined with components of the type III secretion system in Salmonella typhimurium and used to construct a set of AND gates with up to 23-fold change. Next, an antisense RNA was integrated into the circuit architecture to invert the logic of the AND gate and generate a set of NAND gates with up to 1168-fold change. These circuits provide the first demonstration of complex pH- and temperature-responsive genetic circuits, and lay the groundwork for the use of similar circuits in real-world applications. Biotechnol. Bioeng. 2017;114: 1626-1631. © 2017 Wiley Periodicals, Inc. © 2017 Wiley Periodicals, Inc.
Silicon integrated circuits part A : supplement 2
Kahng, Dawon
1981-01-01
Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public
Comments on the Huang and Taylor model of ion-implanted silicon-gate depletion-mode IGFET
International Nuclear Information System (INIS)
Marciniak, W.; Madura, H.
1985-01-01
Recently the Huang and Taylor model (HT model) of built-in channel MOS transistors has been widely used in the analysis of electronic circuits because of its relative simplicity. Huang and Taylor assumed that the effects of the finite channel thickness may be represented by an average semiconductor capacitance in series with the gate oxide capacitance. The derivation of the current-voltage characteristics is based on a linear equation of surface depleted charge density Qsub(s), which is calculated as the sheet charge of constant capacitance C-bar. This is done instead of using the exact solution of the Poisson equation, which has a rather complex form of nonlinear relationship between the charge Qsub(s) and the gate voltage. The basic equation is given. (author)
Fabrication and simulation of organic transistors and functional circuits
Energy Technology Data Exchange (ETDEWEB)
Taylor, D. Martin, E-mail: d.m.taylor@bangor.ac.uk [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Patchett, Eifion R.; Williams, Aled [School of Electronic Engineering, Bangor University, Dean Street, Bangor, Gwynedd LL57 1UT (United Kingdom); Ding, Ziqian; Assender, Hazel E. [Department of Materials, Oxford University, Parks Road, Oxford OX1 3PH (United Kingdom); Morrison, John J.; Yeates, Stephen G. [School of Chemistry, University of Manchester, Oxford Road, Manchester M13 9PL (United Kingdom)
2015-07-29
Highlights: • Development of roll-to-roll fabrication protocol for organic TFTs and circuits. • Bottom-gate polystyrene/DNTT TFTs much better than top-gate TFTs. • High-yield and high mobility with polystyrene-buffered TPGDA. • Fabrication of functional circuits – ring oscillators and logic gates. • New baseline process allows TFT parameter extraction and circuit simulation. - Abstract: We report the development of a vacuum-evaporation route for the roll-to-roll fabrication of functioning organic circuits. A number of key findings and observations are highlighted which influenced the eventual fabrication protocol adopted. Initially, the role of interface roughness in determining carrier mobility in thin film transistors (TFTs) is investigated. Then it is shown that TFT yield is higher for devices fabricated on a flash-evaporated-plasma-polymerised tri(propyleneglycol) diacrylate (TPGDA) gate dielectric than for TFTs based on a spin-coated polystyrene (PS) dielectric. However, a degradation in mobility is observed which is attributed to the highly polar TPGDA surface. It is shown that high mobility, low gate-leakage currents and excellent stability are restored when the surface of TPGDA was buffered with a thin, spin-coated PS film. The resulting baseline process allowed arrays of functional circuits such as ring oscillators, NOR/NAND logic gates and S–R latches to be fabricated with high yield and their performance to be simulated.
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Hafiz, Md Abdullah Al; Kosuru, Lakshmoji; Younis, Mohammad I.
2016-01-01
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Towards electromechanical computation: An alternative approach to realize complex logic circuits
Hafiz, M. A. A.
2016-08-18
Electromechanical computing based on micro/nano resonators has recently attracted significant attention. However, full implementation of this technology has been hindered by the difficulty in realizing complex logic circuits. We report here an alternative approach to realize complex logic circuits based on multiple MEMS resonators. As case studies, we report the construction of a single-bit binary comparator, a single-bit 4-to-2 encoder, and parallel XOR/XNOR and AND/NOT logic gates. Toward this, several microresonators are electrically connected and their resonance frequencies are tuned through an electrothermal modulation scheme. The microresonators operating in the linear regime do not require large excitation forces, and work at room temperature and at modest air pressure. This study demonstrates that by reconfiguring the same basic building block, tunable resonator, several essential complex logic functions can be achieved.
Design and characterization of integrated components for SiN photonic quantum circuits.
Poot, Menno; Schuck, Carsten; Ma, Xiao-Song; Guo, Xiang; Tang, Hong X
2016-04-04
The design, fabrication, and detailed calibration of essential building blocks towards fully integrated linear-optics quantum computation are discussed. Photonic devices are made from silicon nitride rib waveguides, where measurements on ring resonators show small propagation losses. Directional couplers are designed to be insensitive to fabrication variations. Their offset and coupling lengths are measured, as well as the phase difference between the transmitted and reflected light. With careful calibrations, the insertion loss of the directional couplers is found to be small. Finally, an integrated controlled-NOT circuit is characterized by measuring the transmission through different combinations of inputs and outputs. The gate fidelity for the CNOT operation with this circuit is estimated to be 99.81% after post selection. This high fidelity is due to our robust design, good fabrication reproducibility, and extensive characterizations.
A programming language for composable DNA circuits.
Phillips, Andrew; Cardelli, Luca
2009-08-06
Recently, a range of information-processing circuits have been implemented in DNA by using strand displacement as their main computational mechanism. Examples include digital logic circuits and catalytic signal amplification circuits that function as efficient molecular detectors. As new paradigms for DNA computation emerge, the development of corresponding languages and tools for these paradigms will help to facilitate the design of DNA circuits and their automatic compilation to nucleotide sequences. We present a programming language for designing and simulating DNA circuits in which strand displacement is the main computational mechanism. The language includes basic elements of sequence domains, toeholds and branch migration, and assumes that strands do not possess any secondary structure. The language is used to model and simulate a variety of circuits, including an entropy-driven catalytic gate, a simple gate motif for synthesizing large-scale circuits and a scheme for implementing an arbitrary system of chemical reactions. The language is a first step towards the design of modelling and simulation tools for DNA strand displacement, which complements the emergence of novel implementation strategies for DNA computing.
A parity checker circuit based on microelectromechanical resonator logic elements
Hafiz, Md Abdullah Al
2017-01-11
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
A parity checker circuit based on microelectromechanical resonator logic elements
Hafiz, Md Abdullah Al; Li, Ren; Younis, Mohammad I.; Fariborzi, Hossein
2017-01-01
Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.
Circuit mismatch influence on performance of paralleling silicon carbide MOSFETs
DEFF Research Database (Denmark)
Li, Helong; Munk-Nielsen, Stig; Pham, Cam
2014-01-01
This paper focuses on circuit mismatch influence on performance of paralleling SiC MOSFETs. Power circuit mismatch and gate driver mismatch influences are analyzed in detail. Simulation and experiment results show the influence of circuit mismatch and verify the analysis. This paper aims to give...... suggestions on paralleling discrete SiC MOSFETs and designing layout of power modules with paralleled SiC MOSFETs dies....
DEFF Research Database (Denmark)
2010-01-01
A switch-mode power circuit comprises a controllable element and a control unit. The controllable element is configured to control a current in response to a control signal supplied to the controllable element. The control unit is connected to the controllable element and provides the control...
Nelson, Jane B.
1998-01-01
Describes a research-based activity for high school physics students in which they build an LC circuit and find its resonant frequency of oscillation using an oscilloscope. Includes a diagram of the apparatus and an explanation of the procedures. (DDR)
Low cost design of microprocessor EDAC circuit
International Nuclear Information System (INIS)
Hao Li; Yu Lixin; Peng Heping; Zhuang Wei
2015-01-01
An optimization method of error detection and correction (EDAC) circuit design is proposed. The method involves selecting or constructing EDAC codes of low cost hardware, associated with operation scheduling implementation based on 2-input XOR gates structure, and two actions for reducing hardware cells, which can reduce the delay penalties and area costs of the EDAC circuit effectively. The 32-bit EDAC circuit hardware implementation is selected to make a prototype, based on the 180 nm process. The delay penalties and area costs of the EDAC circuit are evaluated. Results show that the time penalty and area cost of the EDAC circuitries are affected with different parity-check matrices and different hardware implementation for the EDAC codes with the same capability of correction and detection code. This method can be used as a guide for low-cost radiation-hardened microprocessor EDAC circuit design and for more advanced technologies. (paper)
Reconfigurable Complementary Logic Circuits with Ambipolar Organic Transistors.
Yoo, Hocheon; Ghittorelli, Matteo; Smits, Edsger C P; Gelinck, Gerwin H; Lee, Han-Koo; Torricelli, Fabrizio; Kim, Jae-Joon
2016-10-20
Ambipolar organic electronics offer great potential for simple and low-cost fabrication of complementary logic circuits on large-area and mechanically flexible substrates. Ambipolar transistors are ideal candidates for the simple and low-cost development of complementary logic circuits since they can operate as n-type and p-type transistors. Nevertheless, the experimental demonstration of ambipolar organic complementary circuits is limited to inverters. The control of the transistor polarity is crucial for proper circuit operation. Novel gating techniques enable to control the transistor polarity but result in dramatically reduced performances. Here we show high-performance non-planar ambipolar organic transistors with electrical control of the polarity and orders of magnitude higher performances with respect to state-of-art split-gate ambipolar transistors. Electrically reconfigurable complementary logic gates based on ambipolar organic transistors are experimentally demonstrated, thus opening up new opportunities for ambipolar organic complementary electronics.
Three-channel gated nanosecond integrator
International Nuclear Information System (INIS)
Tsirkel', B.I.; Martsinovskij, A.M.
1981-01-01
Structure and principle of operation of three-channel gated integrator for investigating the shape of periodical electric and optical signals at high background noise level are described. The integrator consists of an integrating circuit itself for each channel and a circuit of gating pulse formation. If the noise level doesn't exceed the signal, the value of storage capacity can be equal to 22 nF. The value of storage capacity must be increased in the case of a worse signal-to-noise ratio. The gating pulse formation circuit includes a comparator, a sawtooth voltage generator and a reference voltage generator. An integrator flowsheet is given. The time resolution of the system is about 50 ns, time sweep amounts to 5-2000 μs, electric signal sensitivity is about 70 μV. The pulse signal shape recording is performed with manual or automated time sweep at two-coordinate potentiometer. The light signal detection is made on the base of photomultiplier pulse counting rate record by the dynamic capacitor method, sensitivity limit amounts to about 1 pulse/s
Universal programmable quantum circuit schemes to emulate an operator
Energy Technology Data Exchange (ETDEWEB)
Daskin, Anmer; Grama, Ananth; Kollias, Giorgos [Department of Computer Science, Purdue University, West Lafayette, Indiana 47907 (United States); Kais, Sabre [Department of Chemistry, Department of Physics and Birck Nanotechnology Center, Purdue University, West Lafayette, Indiana 47907 (United States); Qatar Environment and Energy Research Institute, Doha (Qatar)
2012-12-21
Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix-which can be non-unitary-in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e{sup -iHt} for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.
Universal programmable quantum circuit schemes to emulate an operator
International Nuclear Information System (INIS)
Daskin, Anmer; Grama, Ananth; Kollias, Giorgos; Kais, Sabre
2012-01-01
Unlike fixed designs, programmable circuit designs support an infinite number of operators. The functionality of a programmable circuit can be altered by simply changing the angle values of the rotation gates in the circuit. Here, we present a new quantum circuit design technique resulting in two general programmable circuit schemes. The circuit schemes can be used to simulate any given operator by setting the angle values in the circuit. This provides a fixed circuit design whose angles are determined from the elements of the given matrix–which can be non-unitary–in an efficient way. We also give both the classical and quantum complexity analysis for these circuits and show that the circuits require a few classical computations. For the electronic structure simulation on a quantum computer, one has to perform the following steps: prepare the initial wave function of the system; present the evolution operator U=e −iHt for a given atomic and molecular Hamiltonian H in terms of quantum gates array and apply the phase estimation algorithm to find the energy eigenvalues. Thus, in the circuit model of quantum computing for quantum chemistry, a crucial step is presenting the evolution operator for the atomic and molecular Hamiltonians in terms of quantum gate arrays. Since the presented circuit designs are independent from the matrix decomposition techniques and the global optimization processes used to find quantum circuits for a given operator, high accuracy simulations can be done for the unitary propagators of molecular Hamiltonians on quantum computers. As an example, we show how to build the circuit design for the hydrogen molecule.
Scaling of graphene integrated circuits.
Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman
2015-05-07
The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.
Otanps synapse linear relation multiplier circuit
International Nuclear Information System (INIS)
Chible, H.
2008-01-01
In this paper, a four quadrant VLSI analog multiplier will be proposed, in order to be used in the implementation of the neurons and synapses modules of the artificial neural networks. The main characteristics of this multiplier are the small silicon area and the low power consumption and the high value of the weight input voltage. (author)
Hyperchaotic circuit with damped harmonic oscillators
DEFF Research Database (Denmark)
Lindberg, Erik; Murali, K.; Tamasevicius, A.
2001-01-01
A simple fourth-order hyperchaotic circuit with damped harmonic oscillators is described. ANP3 and PSpice simulations including an eigenvalue study of the linearized Jacobian are presented together with a hardware implementation. The circuit contains two inductors with series resistance, two ideal...... capacitors and one nonlinear active conductor. The Lyapunov exponents are presented to confirm the hyperchaotic nature of the oscillations of the circuit. The nonlinear conductor is realized with a diode. A negative impedance converter and a linear resistor. The performance of the circuit is investigated...... by means of numerical integration of the appropriate differential equations....
Electronic circuit for control rod attracting electromagnet
International Nuclear Information System (INIS)
Ito, Koji.
1991-01-01
The present invention provides a discharging circuit for control rod attracting electromagnet used for a reactor which is highly reliable and has high performance. The resistor of the circuit comprises a non-linear resistor element and a blocking rectification element connected in series. The discharging circuit can be prevented from short-circuit by selecting a resistor having a resistance value about ten times as great as the coil resistance, even in a case where the blocking rectification element and the non-linear resistor element are failed. Accordingly, reduction of attracting force and the increase of scream releasing time can be minimized. (I.S.)
Design, Analysis and Test of Logic Circuits Under Uncertainty
Krishnaswamy, Smita; Hayes, John P
2013-01-01
Integrated circuits (ICs) increasingly exhibit uncertain characteristics due to soft errors, inherently probabilistic devices, and manufacturing variability. As device technologies scale, these effects can be detrimental to the reliability of logic circuits. To improve future semiconductor designs, this book describes methods for analyzing, designing, and testing circuits subject to probabilistic effects. The authors first develop techniques to model inherently probabilistic methods in logic circuits and to test circuits for determining their reliability after they are manufactured. Then, they study error-masking mechanisms intrinsic to digital circuits and show how to leverage them to design more reliable circuits. The book describes techniques for: • Modeling and reasoning about probabilistic behavior in logic circuits, including a matrix-based reliability-analysis framework; • Accurate analysis of soft-error rate (SER) based on functional-simulation, sufficiently scalable for use in gate-l...
Introduction of audio gating to further reduce organ motion in breathing synchronized radiotherapy
International Nuclear Information System (INIS)
Kubo, H. Dale; Wang Lili
2002-01-01
With breathing synchronized radiotherapy (BSRT), a voltage signal derived from an organ displacement detector is usually displayed on the vertical axis whereas the elapsed time is shown on the horizontal axis. The voltage gate window is set on the breathing voltage signal. Whenever the breathing signal falls between the two gate levels, a gate pulse is produced to enable the treatment machine. In this paper a new gating mechanism, audio (or time-sequence) gating, is introduced and is integrated into the existing voltage gating system. The audio gating takes advantage of the repetitive nature of the breathing signal when repetitive audio instruction is given to the patient. The audio gating is aimed at removing the regions of sharp rises and falls in the breathing signal that cannot be removed by the voltage gating. When the breathing signal falls between voltage gate levels as well as between audio-gate levels, the voltage- and audio-gated radiotherapy (ART) system will generate an AND gate pulse. When this gate pulse is received by a linear accelerator, the linear accelerator becomes 'enabled' for beam delivery and will deliver the beam when all other interlocks are removed. This paper describes a new gating mechanism and a method of recording beam-on signal, both of which are, configured into a laptop computer. The paper also presents evidence of some clinical advantages achieved with the ART system
Gated x-ray detector for the National Ignition Facility
International Nuclear Information System (INIS)
Oertel, John A.; Aragonez, Robert; Archuleta, Tom; Barnes, Cris; Casper, Larry; Fatherley, Valerie; Heinrichs, Todd; King, Robert; Landers, Doug; Lopez, Frank; Sanchez, Phillip; Sandoval, George; Schrank, Lou; Walsh, Peter; Bell, Perry; Brown, Matt; Costa, Robert; Holder, Joe; Montelongo, Sam; Pederson, Neal
2006-01-01
Two new gated x-ray imaging cameras have recently been designed, constructed, and delivered to the National Ignition Facility in Livermore, CA. These gated x-Ray detectors are each designed to fit within an aluminum airbox with a large capacity cooling plane and are fitted with an array of environmental housekeeping sensors. These instruments are significantly different from earlier generations of gated x-ray images due, in part, to an innovative impedance matching scheme, advanced phosphor screens, pulsed phosphor circuits, precision assembly fixturing, unique system monitoring, and complete remote computer control. Preliminary characterization has shown repeatable uniformity between imaging strips, improved spatial resolution, and no detectable impedance reflections
Accuracy and Consistency of Respiratory Gating in Abdominal Cancer Patients
International Nuclear Information System (INIS)
Ge, Jiajia; Santanam, Lakshmi; Yang, Deshan; Parikh, Parag J.
2013-01-01
Purpose: To evaluate respiratory gating accuracy and intrafractional consistency for abdominal cancer patients treated with respiratory gated treatment on a regular linear accelerator system. Methods and Materials: Twelve abdominal patients implanted with fiducials were treated with amplitude-based respiratory-gated radiation therapy. On the basis of daily orthogonal fluoroscopy, the operator readjusted the couch position and gating window such that the fiducial was within a setup margin (fiducial-planning target volume [f-PTV]) when RPM indicated “beam-ON.” Fifty-five pre- and post-treatment fluoroscopic movie pairs with synchronized respiratory gating signal were recorded. Fiducial motion traces were extracted from the fluoroscopic movies using a template matching algorithm and correlated with f-PTV by registering the digitally reconstructed radiographs with the fluoroscopic movies. Treatment was determined to be “accurate” if 50% of the fiducial area stayed within f-PTV while beam-ON. For movie pairs that lost gating accuracy, a MATLAB program was used to assess whether the gating window was optimized, the external-internal correlation (EIC) changed, or the patient moved between movies. A series of safety margins from 0.5 mm to 3 mm was added to f-PTV for reassessing gating accuracy. Results: A decrease in gating accuracy was observed in 44% of movie pairs from daily fluoroscopic movies of 12 abdominal patients. Three main causes for inaccurate gating were identified as change of global EIC over time (∼43%), suboptimal gating setup (∼37%), and imperfect EIC within movie (∼13%). Conclusions: Inconsistent respiratory gating accuracy may occur within 1 treatment session even with a daily adjusted gating window. To improve or maintain gating accuracy during treatment, we suggest using at least a 2.5-mm safety margin to account for gating and setup uncertainties
Hybrid Toffoli gate on photons and quantum spins.
Luo, Ming-Xing; Ma, Song-Ya; Chen, Xiu-Bo; Wang, Xiaojun
2015-11-16
Quantum computation offers potential advantages in solving a number of interesting and difficult problems. Several controlled logic gates, the elemental building blocks of quantum computer, have been realized with various physical systems. A general technique was recently proposed that significantly reduces the realization complexity of multiple-control logic gates by harnessing multi-level information carriers. We present implementations of a key quantum circuit: the three-qubit Toffoli gate. By exploring the optical selection rules of one-sided optical microcavities, a Toffoli gate may be realized on all combinations of photon and quantum spins in the QD-cavity. The three general controlled-NOT gates are involved using an auxiliary photon with two degrees of freedom. Our results show that photons and quantum spins may be used alternatively in quantum information processing.
Relative ultrasound energy measurement circuit
Gustafsson, E.Martin I.; Johansson, Jonny; Delsing, Jerker
2005-01-01
A relative ultrasound energy estimation circuit has been designed in a standard 0.35-μm CMOS process, to be a part of a thumb size internet connected wireless ultrasound measurement system. This circuit measures the relative energy between received ultrasound pulses, and presents an output signal that is linear to the received energy. Post-layout simulations indicate 7 bit linearity for 500 mV input signals, 5 μsec startup and stop times, 2.6 mW power consumption during active state. The acti...
High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology
DEFF Research Database (Denmark)
Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid
This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared...... with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention...
Sander, K F
1964-01-01
Linear Network Theory covers the significant algebraic aspect of network theory, with minimal reference to practical circuits. The book begins the presentation of network analysis with the exposition of networks containing resistances only, and follows it up with a discussion of networks involving inductance and capacity by way of the differential equations. Classification and description of certain networks, equivalent networks, filter circuits, and network functions are also covered. Electrical engineers, technicians, electronics engineers, electricians, and students learning the intricacies
Superconducting flux flow digital circuits
International Nuclear Information System (INIS)
Martens, J.S.; Zipperian, T.E.; Hietala, V.M.; Ginley, D.S.; Tigges, C.P.; Phillips, J.M.; Siegal, M.P.
1993-01-01
The authors have developed a family of digital logic circuits based on superconducting flux flow transistors that show high speed, reasonable signal levels, large fan-out, and large noise margins. The circuits are made from high-temperature superconductors (HTS) and have been shown to operate at over 90 K. NOR gates have been demonstrated with fan-outs of more than 5 and fully loaded switching times less than a fixture-limited 50 ps. Ring-oscillator data suggest inverter delay times of about 40ps when using a 3-μm linewidths. Simple flip-flops have also been demonstrated showing large noise margins, response times of less than 30 ps, and static power dissipation on the order of 30 nW. Among other uses, this logic family is appropriate as an interface between logic families such as single flux quantum and conventional semiconductor logic
Compiling quantum circuits to realistic hardware architectures using temporal planners
Venturelli, Davide; Do, Minh; Rieffel, Eleanor; Frank, Jeremy
2018-04-01
To run quantum algorithms on emerging gate-model quantum hardware, quantum circuits must be compiled to take into account constraints on the hardware. For near-term hardware, with only limited means to mitigate decoherence, it is critical to minimize the duration of the circuit. We investigate the application of temporal planners to the problem of compiling quantum circuits to newly emerging quantum hardware. While our approach is general, we focus on compiling to superconducting hardware architectures with nearest neighbor constraints. Our initial experiments focus on compiling Quantum Alternating Operator Ansatz (QAOA) circuits whose high number of commuting gates allow great flexibility in the order in which the gates can be applied. That freedom makes it more challenging to find optimal compilations but also means there is a greater potential win from more optimized compilation than for less flexible circuits. We map this quantum circuit compilation problem to a temporal planning problem, and generated a test suite of compilation problems for QAOA circuits of various sizes to a realistic hardware architecture. We report compilation results from several state-of-the-art temporal planners on this test set. This early empirical evaluation demonstrates that temporal planning is a viable approach to quantum circuit compilation.
Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation
International Nuclear Information System (INIS)
Estreich, D.B.
1978-11-01
A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience
Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata.
Bahar, Ali Newaz; Rahman, Mohammad Maksudur; Nahid, Nur Mohammad; Hassan, Md Kamrul
2017-02-01
This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T =2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.
Automatic design of digital synthetic gene circuits.
Directory of Open Access Journals (Sweden)
Mario A Marchisio
2011-02-01
Full Text Available De novo computational design of synthetic gene circuits that achieve well-defined target functions is a hard task. Existing, brute-force approaches run optimization algorithms on the structure and on the kinetic parameter values of the network. However, more direct rational methods for automatic circuit design are lacking. Focusing on digital synthetic gene circuits, we developed a methodology and a corresponding tool for in silico automatic design. For a given truth table that specifies a circuit's input-output relations, our algorithm generates and ranks several possible circuit schemes without the need for any optimization. Logic behavior is reproduced by the action of regulatory factors and chemicals on the promoters and on the ribosome binding sites of biological Boolean gates. Simulations of circuits with up to four inputs show a faithful and unequivocal truth table representation, even under parametric perturbations and stochastic noise. A comparison with already implemented circuits, in addition, reveals the potential for simpler designs with the same function. Therefore, we expect the method to help both in devising new circuits and in simplifying existing solutions.
Strong, G.H.; Faught, M.L.
1963-12-24
A device for safety rod counting in a nuclear reactor is described. A Wheatstone bridge circuit is adapted to prevent de-energizing the hopper coils of a ball backup system if safety rods, sufficient in total control effect, properly enter the reactor core to effect shut down. A plurality of resistances form one arm of the bridge, each resistance being associated with a particular safety rod and weighted in value according to the control effect of the particular safety rod. Switching means are used to switch each of the resistances in and out of the bridge circuit responsive to the presence of a particular safety rod in its effective position in the reactor core and responsive to the attainment of a predetermined velocity by a particular safety rod enroute to its effective position. The bridge is unbalanced in one direction during normal reactor operation prior to the generation of a scram signal and the switching means and resistances are adapted to unbalance the bridge in the opposite direction if the safety rods produce a predetermined amount of control effect in response to the scram signal. The bridge unbalance reversal is then utilized to prevent the actuation of the ball backup system, or, conversely, a failure of the safety rods to produce the predetermined effect produces no unbalance reversal and the ball backup system is actuated. (AEC)
Fast frequency divider circuit using combinational logic
Helinski, Ryan
2017-05-30
The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.
Short- circuit tests of circuit breakers
Chorovský, P.
2015-01-01
This paper deals with short-circuit tests of low voltage electrical devices. In the first part of this paper, there are described basic types of short- circuit tests and their principles. Direct and indirect (synthetic) tests with more details are described in the second part. Each test and principles are explained separately. Oscilogram is obtained from short-circuit tests of circuit breakers at laboratory. The aim of this research work is to propose a test circuit for performing indirect test.
RF Circuit Design in Nanometer CMOS
Nauta, Bram
2007-01-01
With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern
Memristor Circuits and Systems
Zidan, Mohammed A.
2015-05-01
resistive-based memory systems and neural computing. For gateless arrays, we present multiport array structure and readout technique, which for the first time introduces a closed-form solution for the challenging crossbar sneak-paths problem. Moreover, a new adaptive threshold readout methodology is proposed, which employs the memory hierarchy locality property in order to improve the access time to the memristor crossbar. Another fast readout technique based on binary counters is presented for locality-less crossbar systems. On the other hand, for gated arrays, we present new readout technique and circuitry that combines the advantages of the gated and gateless memristor arrays, namely the high-density and low-power consumption. In general, the presented structures and readout methodologies empower much faster and power efficient access to the high-density memristive crossbar, compared to other works presented in the literature. Finally, at the circuit level, we propose novel reactance-less oscillators based on memristor devices, which find promising applications in embedded systems and bio-inspired computing. Altogether, we believe that our contributions to the emerging technology help to push it to the next level, shortening the path towards better futuristic computing systems.
Collective of mechatronics circuit
International Nuclear Information System (INIS)
1987-02-01
This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.
Collective of mechatronics circuit
Energy Technology Data Exchange (ETDEWEB)
NONE
1987-02-15
This book is composed of three parts, which deals with mechatronics system about sensor, circuit and motor. The contents of the first part are photo sensor of collector for output, locating detection circuit with photo interrupts, photo sensor circuit with CdS cell and lamp, interface circuit with logic and LED and temperature sensor circuit. The second part deals with oscillation circuit with crystal, C-R oscillation circuit, F-V converter, timer circuit, stability power circuit, DC amp and DC-DC converter. The last part is comprised of bridge server circuit, deformation bridge server, controlling circuit of DC motor, controlling circuit with IC for PLL and driver circuit of stepping motor and driver circuit of Brushless.
Synthesis of energy-efficient FSMs implemented in PLD circuits
Nawrot, Radosław; Kulisz, Józef; Kania, Dariusz
2017-11-01
The paper presents an outline of a simple synthesis method of energy-efficient FSMs. The idea consists in using local clock gating to selectively block the clock signal, if no transition of a state of a memory element is required. The research was dedicated to logic circuits using Programmable Logic Devices as the implementation platform, but the conclusions can be applied to any synchronous circuit. The experimental section reports a comparison of three methods of implementing sequential circuits in PLDs with respect to clock distribution: the classical fully synchronous structure, the structure exploiting the Enable Clock inputs of memory elements, and the structure using clock gating. The results show that the approach based on clock gating is the most efficient one, and it leads to significant reduction of dynamic power consumed by the FSM.
Signatures of Mechanosensitive Gating.
Morris, Richard G
2017-01-10
The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.
Radiation-hardened CMOS/SOS LSI circuits
International Nuclear Information System (INIS)
Aubuchon, K.G.; Peterson, H.T.; Shumake, D.P.
1976-01-01
The recently developed technology for building radiation-hardened CMOS/SOS devices has now been applied to the fabrication of LSI circuits. This paper describes and presents results on three different circuits: an 8-bit adder/subtractor (Al gate), a 256-bit shift register (Si gate), and a polycode generator (Al gate). The 256-bit shift register shows very little degradation after 1 x 10 6 rads (Si), with an increase from 1.9V to 2.9V in minimum operating voltage, a decrease of about 20% in maximum frequency, and little or no change in quiescent current. The p-channel thresholds increase from -0.9V to -1.3V, while the n-channel thresholds decrease from 1.05 to 0.23V, and the n-channel leakage remains below 1nA/mil. Excellent hardening results were also obtained on the polycode generator circuit. Ten circuits were irradiated to 1 x 10 6 rads (Si), and all continued to function well, with an increase in minimum power supply voltage from 2.85V to 5.85V and an increase in quiescent current by a factor of about 2. Similar hardening results were obtained on the 8-bit adder, with the minimum power supply voltage increasing from 2.2V to 4.6V and the add time increasing from 270 to 350 nsec after 1 x 10 6 rads (Si). These results show that large CMOS/SOS circuits can be hardened to above 1 x 10 6 rads (Si) with either the Si gate or Al gate technology. The paper also discusses the relative advantages of the Si gate versus the Al gate technology
A fast charge integrating and shaping circuit
International Nuclear Information System (INIS)
Kulka, Z.; Szoncso, F.
1990-01-01
The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)
Toward spin-based Magneto Logic Gate in Graphene
Wen, Hua; Dery, Hanan; Amamou, Walid; Zhu, Tiancong; Lin, Zhisheng; Shi, Jing; Zutic, Igor; Krivorotov, Ilya; Sham, Lu; Kawakami, Roland
Graphene has emerged as a leading candidate for spintronic applications due to its long spin diffusion length at room temperature. A universal magnetologic gate (MLG) based on spin transport in graphene has been recently proposed as the building block of a logic circuit which could replace the current CMOS technology. This MLG has five ferromagnetic electrodes contacting a graphene channel and can be considered as two three-terminal XOR logic gates. Here we demonstrate this XOR logic gate operation in such a device. This was achieved by systematically tuning the injection current bias to balance the spin polarization efficiency of the two inputs, and offset voltage in the detection circuit to obtain binary outputs. The output is a current which corresponds to different logic states: zero current is logic `0', and nonzero current is logic `1'. We find improved performance could be achieved by reducing device size and optimizing the contacts.
Guzman, R
2000-03-01
Circuit parties are extended celebrations, lasting from a day to a week, primarily attended by gay and bisexual men in their thirties and forties. These large-scale dance parties move from city to city and draw thousands of participants. The risks for contracting HIV during these parties include recreational drug use and unsafe sex. Limited data exists on the level of risk at these parties, and participants are skeptical of outside help because of past criticism of these events. Health care and HIV advocates can promote risk-reduction strategies with the cooperation of party planners and can counsel individuals to personally reduce their own risk. To convey the message, HIV prevention workers should emphasize positive and community-centered aspects of the parties, such as taking care of friends and avoiding overdose.
New Circuit QED system based on Triple-leg Stripline Resonator.
Kim, Dongmin; Moon, Kyungsun
Conventional circuit QED system consists of a qubit located inside a linear stripline resonator, which has successfully demonstrated a strong coupling between a single photon and a qubit. Here we present a new circuit QED system, where the qubit is coupled to triple-leg stripline resonator (TSR). We have shown that TSR supports two-fold degenerate photon modes among others. By coupling them to a single qubit, we have obtained the dressed states of a coupled system of a single qubit and two-fold degenerate photon modes. By locating two qubits at two legs of TSR, we have studied a potential two-bit gate operation (e.g., CNOT gate) of the system. We will discuss the main advantage of utilizing two-fold degenerate photon modes This work is partially supported by Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (NRF-2016R1D1A1B01013756).
A double-gate double-feedback JFET charge-sensitive preamplifier
International Nuclear Information System (INIS)
Fazzi, A.
1996-01-01
A new charge-sensitive preamplifier (CSP) without a physical resistance in the feedback is presented. The input device has to be a double-gate JFET. In this new preamplifier configuration the feedback capacitor is continuously discharged by means of a second DC current feedback loop closed through the bottom gate of the input JFET. The top gate-channel junction works as usual in reverse bias, the bottom gate-channel is forward biased. A fraction of the current injected by the bottom gate reaches the top gate discharging the feedback capacitor. The n-channel double-gate JFET is considered from the viewpoint of the restoring action as a parasitic p-n-p ''transversal'' bipolar junction transistor. The new preamplifier is also suited for detectors operating at room temperature with leakage current which may vary with time. The DC behaviour and the dynamic behaviour of the circuit is analyzed and new measurements presented. (orig.)
Technology CAD for germanium CMOS circuit
Energy Technology Data Exchange (ETDEWEB)
Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)
2006-12-15
Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.
Technology CAD for germanium CMOS circuit
International Nuclear Information System (INIS)
Saha, A.R.; Maiti, C.K.
2006-01-01
Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted
Linearization of the Lorenz system
International Nuclear Information System (INIS)
Li, Chunbiao; Sprott, Julien Clinton; Thio, Wesley
2015-01-01
A partial and complete piecewise linearized version of the Lorenz system is proposed. The linearized versions have an independent total amplitude control parameter. Additional further linearization leads naturally to a piecewise linear version of the diffusionless Lorenz system. A chaotic circuit with a single amplitude controller is then implemented using a new switch element, producing a chaotic oscillation that agrees with the numerical calculation for the piecewise linear diffusionless Lorenz system. - Highlights: • A partial and complete piecewise linearized version of the Lorenz system are addressed. • The linearized versions have an independent total amplitude control parameter. • A piecewise linear version of the diffusionless Lorenz system is derived by further linearization. • A corresponding chaotic circuit without any multiplier is implemented for the chaotic oscillation
Linearization of the Lorenz system
Energy Technology Data Exchange (ETDEWEB)
Li, Chunbiao, E-mail: goontry@126.com [School of Electronic & Information Engineering, Nanjing University of Information Science & Technology, Nanjing 210044 (China); Engineering Technology Research and Development Center of Jiangsu Circulation Modernization Sensor Network, Jiangsu Institute of Commerce, Nanjing 211168 (China); Sprott, Julien Clinton [Department of Physics, University of Wisconsin–Madison, Madison, WI 53706 (United States); Thio, Wesley [Department of Electrical and Computer Engineering, The Ohio State University, Columbus, OH 43210 (United States)
2015-05-08
A partial and complete piecewise linearized version of the Lorenz system is proposed. The linearized versions have an independent total amplitude control parameter. Additional further linearization leads naturally to a piecewise linear version of the diffusionless Lorenz system. A chaotic circuit with a single amplitude controller is then implemented using a new switch element, producing a chaotic oscillation that agrees with the numerical calculation for the piecewise linear diffusionless Lorenz system. - Highlights: • A partial and complete piecewise linearized version of the Lorenz system are addressed. • The linearized versions have an independent total amplitude control parameter. • A piecewise linear version of the diffusionless Lorenz system is derived by further linearization. • A corresponding chaotic circuit without any multiplier is implemented for the chaotic oscillation.
Few-photon Non-linearities in Nanophotonic Devices for Quantum Information Technology
DEFF Research Database (Denmark)
Nysteen, Anders
In this thesis we investigate few-photon non-linearities in all-optical, on-chip circuits, and we discuss their possible applications in devices of interest for quantum information technology, such as conditional two-photon gates and single-photon sources. In order to propose efficient devices...... the scattered photons. Even though the non-linearity also alters the pulse spectrum due to a four-wave mixing process, we demonstrate that input pulses with a Gaussian spectrum can be mapped to the output with up to 80 % fidelity. Using two identical two-level emitters, we propose a setup for a deterministic...... by the capturing process. Semiconductor quantum dots (QDs) are promising for realizing few-photon non-linearities in solid-state implementations, although coupling to phonon modes in the surrounding lattice have significant influence on the dynamics. By accounting for the commonly neglected asymmetry between...
Finding the Energy Efficient Curve: Gate Sizing for Minimum Power under Delay Constraints
Directory of Open Access Journals (Sweden)
Yoni Aizik
2011-01-01
Full Text Available A design scenario examined in this paper assumes that a circuit has been designed initially for high speed, and it is redesigned for low power by downsizing of the gates. In recent years, as power consumption has become a dominant issue, new optimizations of circuits are required for saving energy. This is done by trading off some speed in exchange for reduced power. For each feasible speed, an optimization problem is solved in this paper, finding new sizes for the gates such that the circuit satisfies the speed goal while dissipating minimal power. Energy/delay gain (EDG is defined as a metric to quantify the most efficient tradeoff. The EDG of the circuit is evaluated for a range of reduced circuit speeds, and the power-optimal gate sizes are compared with the initial sizes. Most of the energy savings occur at the final stages of the circuits, while the largest relative downsizing occurs in middle stages. Typical tapering factors for power efficient circuits are larger than those for speed-optimal circuits. Signal activity and signal probability affect the optimal gate sizes in the combined optimization of speed and power.
Commutation circuit for an HVDC circuit breaker
Premerlani, William J.
1981-01-01
A commutation circuit for a high voltage DC circuit breaker incorporates a resistor capacitor combination and a charging circuit connected to the main breaker, such that a commutating capacitor is discharged in opposition to the load current to force the current in an arc after breaker opening to zero to facilitate arc interruption. In a particular embodiment, a normally open commutating circuit is connected across the contacts of a main DC circuit breaker to absorb the inductive system energy trapped by breaker opening and to limit recovery voltages to a level tolerable by the commutating circuit components.
On automatic synthesis of analog/digital circuits
Energy Technology Data Exchange (ETDEWEB)
Beiu, V.
1998-12-31
The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.
Proposal of unilateral single-flux-quantum logic gate
International Nuclear Information System (INIS)
Mikaye, H.; Fukaya, N.; Okabe, Y.; Sugamo, T.
1985-01-01
A new type of single flux quantum logic gate is proposed, which can perform unilateral propagation of signal without using three-phase clock. This gate is designed to be built with bridge-type Josephson junctions. A basic logic gate consists of two one-junction interferometers coupled by superconducting interconnecting lines, and the logical states are represented by zero or one quantized fluxoid in one of one-junction interferometers. The bias current of the unequal magnitude to each of the two one-junction interferometers results in unilateral signal flow. By adjusting design parameters such as the ratio of the critical current of Josephson junctions and the inductances, circuits with the noise immunity of greater than 50% with respect to the bias current have been designed. Three cascaded gates were modeled and simulated on a computer, and the unilateral signal flow was confirmed. The simulation also shows that a switching delay about 2 picoseconds is feasible
Scherer, Artur; Valiron, Benoît; Mau, Siun-Chuon; Alexander, Scott; van den Berg, Eric; Chapuran, Thomas E.
2017-03-01
We provide a detailed estimate for the logical resource requirements of the quantum linear-system algorithm (Harrow et al. in Phys Rev Lett 103:150502, 2009) including the recently described elaborations and application to computing the electromagnetic scattering cross section of a metallic target (Clader et al. in Phys Rev Lett 110:250504, 2013). Our resource estimates are based on the standard quantum-circuit model of quantum computation; they comprise circuit width (related to parallelism), circuit depth (total number of steps), the number of qubits and ancilla qubits employed, and the overall number of elementary quantum gate operations as well as more specific gate counts for each elementary fault-tolerant gate from the standard set { X, Y, Z, H, S, T, { CNOT } }. In order to perform these estimates, we used an approach that combines manual analysis with automated estimates generated via the Quipper quantum programming language and compiler. Our estimates pertain to the explicit example problem size N=332{,}020{,}680 beyond which, according to a crude big-O complexity comparison, the quantum linear-system algorithm is expected to run faster than the best known classical linear-system solving algorithm. For this problem size, a desired calculation accuracy ɛ =0.01 requires an approximate circuit width 340 and circuit depth of order 10^{25} if oracle costs are excluded, and a circuit width and circuit depth of order 10^8 and 10^{29}, respectively, if the resource requirements of oracles are included, indicating that the commonly ignored oracle resources are considerable. In addition to providing detailed logical resource estimates, it is also the purpose of this paper to demonstrate explicitly (using a fine-grained approach rather than relying on coarse big-O asymptotic approximations) how these impressively large numbers arise with an actual circuit implementation of a quantum algorithm. While our estimates may prove to be conservative as more efficient
Active quenching circuit for a InGaAs single-photon avalanche diode
International Nuclear Information System (INIS)
Zheng Lixia; Wu Jin; Xi Shuiqing; Shi Longxing; Liu Siyang; Sun Weifeng
2014-01-01
We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications. (semiconductor integrated circuits)
Resistors Improve Ramp Linearity
Kleinberg, L. L.
1982-01-01
Simple modification to bootstrap ramp generator gives more linear output over longer sweep times. New circuit adds just two resistors, one of which is adjustable. Modification cancels nonlinearities due to variations in load on charging capacitor and due to changes in charging current as the voltage across capacitor increases.
Analog circuit design designing dynamic circuit response
Feucht, Dennis
2010-01-01
This second volume, Designing Dynamic Circuit Response builds upon the first volume Designing Amplifier Circuits by extending coverage to include reactances and their time- and frequency-related behavioral consequences.
Design of synthetic biological logic circuits based on evolutionary algorithm.
Chuang, Chia-Hua; Lin, Chun-Liang; Chang, Yen-Chang; Jennawasin, Tanagorn; Chen, Po-Kuei
2013-08-01
The construction of an artificial biological logic circuit using systematic strategy is recognised as one of the most important topics for the development of synthetic biology. In this study, a real-structured genetic algorithm (RSGA), which combines general advantages of the traditional real genetic algorithm with those of the structured genetic algorithm, is proposed to deal with the biological logic circuit design problem. A general model with the cis-regulatory input function and appropriate promoter activity functions is proposed to synthesise a wide variety of fundamental logic gates such as NOT, Buffer, AND, OR, NAND, NOR and XOR. The results obtained can be extended to synthesise advanced combinational and sequential logic circuits by topologically distinct connections. The resulting optimal design of these logic gates and circuits are established via the RSGA. The in silico computer-based modelling technology has been verified showing its great advantages in the purpose.
International Nuclear Information System (INIS)
Verity, P.R.; Chaplain, M.D.; Turner, G.D.J.
1984-01-01
A monostable trigger circuit comprises transistors TR2 and TR3 arranged with their collectors and bases interconnected. The collector of the transistor TR2 is connected to the base of transistor TR3 via a capacitor C2 the main current path of a grounded base transistor TR1 and resistive means R2,R3. The collector of transistor TR3 is connected to the base of transistor TR2 via resistive means R6, R7. In the stable state all the transistors are OFF, the capacitor C2 is charged, and the output is LOW. A positive pulse input to the base of TR2 switches it ON, which in turn lowers the voltage at points A and B and so switches TR1 ON so that C2 can discharge via R2, R3, which in turn switches TR3 ON making the output high. Thus all three transistors are latched ON. When C2 has discharged sufficiently TR1 switches OFF, followed by TR3 (making the output low again) and TR2. The components C1, C3 and R4 serve to reduce noise, and the diode D1 is optional. (author)
Wei, Hai-Rui; Lu Long, Gui
2015-01-01
Hybrid quantum gates hold great promise for quantum information processing since they preserve the advantages of different quantum systems. Here we present compact quantum circuits to deterministically implement controlled-NOT, Toffoli, and Fredkin gates between a flying photon qubit and diamond nitrogen-vacancy (NV) centers assisted by microcavities. The target qubits of these universal quantum gates are encoded on the spins of the electrons associated with the diamond NV centers and they have long coherence time for storing information, and the control qubit is encoded on the polarizations of the flying photon and can be easily manipulated. Our quantum circuits are compact, economic, and simple. Moreover, they do not require additional qubits. The complexity of our schemes for universal three-qubit gates is much reduced, compared to the synthesis with two-qubit entangling gates. These schemes have high fidelities and efficiencies, and they are feasible in experiment. PMID:26271899
Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao
2018-04-01
In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.
Online junction temperature measurement via internal gate resistance during turn-on
DEFF Research Database (Denmark)
Baker, Nick; Munk-Nielsen, Stig; Liserre, Marco
2014-01-01
A new method for junction temperature measurement of power semiconductor switches is presented. The measurement exploits the temperature dependent resistance of the temperature sensitive electrical parameter (TSEP): the internal gate resistance. This dependence can be observed during the normal...... switching transitions of an IGBT or MOSFET, and as a result the presented method uses the integral of the gate voltage during the turn-on delay. A measurement circuit can be integrated into a gate driver with no modification to converter or gate driver operation and holds significant advantages over other...
Organizing of delay, input gate and memory of proportional chamber channel basing on D-trigger
International Nuclear Information System (INIS)
Vladimirov, S.V.; Kuzichev, V.F.; Rabin, N.V.
1980-01-01
Economical organization of delay, input gate and proportional chamber (PC) channel memory on the 155 TM2 D trigger basis is described. The channel consists of an amplifier; delay element permitting to synchronize PC signal and recording strobe-signal; input gate, where coincidence of the above signals occurs; memory element, where the data from a wire are recorded and stored; read gate through which the data are transmitted for further processing. Presented is one of the versions of circuit solution for delay element, input gate and momory element. Flowsheet peculiarity is the simplicity of fabrication and tuning as well as low cost of the device
Complexity classifications for different equivalence and audit problems for Boolean circuits
BÃ¶hler, Elmar; Creignou, Nadia; Galota, Matthias; Reith, Steffen; Schnoor, Henning; Vollmer, Heribert
2010-01-01
We study Boolean circuits as a representation of Boolean functions and conskier different equivalence, audit, and enumeration problems. For a number of restricted sets of gate types (bases) we obtain efficient algorithms, while for all other gate types we show these problems are at least NP-hard.
Genetic Spot Optimization for Peak Power Estimation in Large VLSI Circuits
Directory of Open Access Journals (Sweden)
Michael S. Hsiao
2002-01-01
Full Text Available Estimating peak power involves optimization of the circuit's switching function. The switching of a given gate is not only dependent on the output capacitance of the node, but also heavily dependent on the gate delays in the circuit, since multiple switching events can result from uneven circuit delay paths in the circuit. Genetic spot expansion and optimization are proposed in this paper to estimate tight peak power bounds for large sequential circuits. The optimization spot shifts and expands dynamically based on the maximum power potential (MPP of the nodes under optimization. Four genetic spot optimization heuristics are studied for sequential circuits. Experimental results showed an average of 70.7% tighter peak power bounds for large sequential benchmark circuits was achieved in short execution times.
Designable DNA-binding domains enable construction of logic circuits in mammalian cells.
Gaber, Rok; Lebar, Tina; Majerle, Andreja; Šter, Branko; Dobnikar, Andrej; Benčina, Mojca; Jerala, Roman
2014-03-01
Electronic computer circuits consisting of a large number of connected logic gates of the same type, such as NOR, can be easily fabricated and can implement any logic function. In contrast, designed genetic circuits must employ orthogonal information mediators owing to free diffusion within the cell. Combinatorial diversity and orthogonality can be provided by designable DNA- binding domains. Here, we employed the transcription activator-like repressors to optimize the construction of orthogonal functionally complete NOR gates to construct logic circuits. We used transient transfection to implement all 16 two-input logic functions from combinations of the same type of NOR gates within mammalian cells. Additionally, we present a genetic logic circuit where one input is used to select between an AND and OR function to process the data input using the same circuit. This demonstrates the potential of designable modular transcription factors for the construction of complex biological information-processing devices.
Universal programmable logic gate and routing method
Fijany, Amir (Inventor); Vatan, Farrokh (Inventor); Akarvardar, Kerem (Inventor); Blalock, Benjamin (Inventor); Chen, Suheng (Inventor); Cristoloveanu, Sorin (Inventor); Kolawa, Elzbieta (Inventor); Mojarradi, Mohammad M. (Inventor); Toomarian, Nikzad (Inventor)
2009-01-01
An universal and programmable logic gate based on G.sup.4-FET technology is disclosed, leading to the design of more efficient logic circuits. A new full adder design based on the G.sup.4-FET is also presented. The G.sup.4-FET can also function as a unique router device offering coplanar crossing of signal paths that are isolated and perpendicular to one another. This has the potential of overcoming major limitations in VLSI design where complex interconnection schemes have become increasingly problematic.
Nano-CMOS gate dielectric engineering
Wong, Hei
2011-01-01
According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic
All-Digital Time-Domain CMOS Smart Temperature Sensor with On-Chip Linearity Enhancement.
Chen, Chun-Chi; Chen, Chao-Lieh; Lin, Yi
2016-01-30
This paper proposes the first all-digital on-chip linearity enhancement technique for improving the accuracy of the time-domain complementary metal-oxide semiconductor (CMOS) smart temperature sensor. To facilitate on-chip application and intellectual property reuse, an all-digital time-domain smart temperature sensor was implemented using 90 nm Field Programmable Gate Arrays (FPGAs). Although the inverter-based temperature sensor has a smaller circuit area and lower complexity, two-point calibration must be used to achieve an acceptable inaccuracy. With the help of a calibration circuit, the influence of process variations was reduced greatly for one-point calibration support, reducing the test costs and time. However, the sensor response still exhibited a large curvature, which substantially affected the accuracy of the sensor. Thus, an on-chip linearity-enhanced circuit is proposed to linearize the curve and achieve a new linearity-enhanced output. The sensor was implemented on eight different Xilinx FPGA using 118 slices per sensor in each FPGA to demonstrate the benefits of the linearization. Compared with the unlinearized version, the maximal inaccuracy of the linearized version decreased from 5 °C to 2.5 °C after one-point calibration in a range of -20 °C to 100 °C. The sensor consumed 95 μW using 1 kSa/s. The proposed linearity enhancement technique significantly improves temperature sensing accuracy, avoiding costly curvature compensation while it is fully synthesizable for future Very Large Scale Integration (VLSI) system.
Quantum walks, quantum gates, and quantum computers
International Nuclear Information System (INIS)
Hines, Andrew P.; Stamp, P. C. E.
2007-01-01
The physics of quantum walks on graphs is formulated in Hamiltonian language, both for simple quantum walks and for composite walks, where extra discrete degrees of freedom live at each node of the graph. It is shown how to map between quantum walk Hamiltonians and Hamiltonians for qubit systems and quantum circuits; this is done for both single-excitation and multiexcitation encodings. Specific examples of spin chains, as well as static and dynamic systems of qubits, are mapped to quantum walks, and walks on hyperlattices and hypercubes are mapped to various gate systems. We also show how to map a quantum circuit performing the quantum Fourier transform, the key element of Shor's algorithm, to a quantum walk system doing the same. The results herein are an essential preliminary to a Hamiltonian formulation of quantum walks in which coupling to a dynamic quantum environment is included
A single nano cantilever as a reprogrammable universal logic gate
Chappanda, K. N.
2017-02-24
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing.
A single nano cantilever as a reprogrammable universal logic gate
International Nuclear Information System (INIS)
Chappanda, K N; Ilyas, S; Kazmi, S N R; Younis, M I; Holguin-Lerma, J; Batra, N M; Costa, P M F J
2017-01-01
The current transistor-based computing circuits use multiple interconnected transistors to realize a single Boolean logic gate. This leads to higher power requirements and delayed computing. Transistors are not suitable for applications in harsh environments and require complicated thermal management systems due to excessive heat dissipation. Also, transistor circuits lack the ability to dynamically reconfigure their functionality in real time, which is desirable for enhanced computing capability. Further, the miniaturization of transistors to improve computational power is reaching its ultimate physical limits. As a step towards overcoming the limitations of transistor-based computing, here we demonstrate a reprogrammable universal Boolean logic gate based on a nanoelectromechanical cantilever (NC) oscillator. The fundamental XOR, AND, NOR, OR and NOT logic gates are condensed in a single NC, thereby reducing electrical interconnects between devices. The device is dynamically switchable between any logic gates at the same drive frequency without the need for any change in the circuit. It is demonstrated to operate at elevated temperatures minimizing the need for thermal management systems. It has a tunable bandwidth of 5 MHz enabling parallel and dynamically reconfigurable logic device for enhanced computing. (paper)
An integer programming model for gate assignment problem at airline terminals
Chun, Chong Kok; Nordin, Syarifah Zyurina
2015-05-01
In this paper, we concentrate on a gate assignment problem (GAP) at the airlines terminal. Our problem is to assign an arrival plane to a suitable gate. There are two considerations needed to take. One of its is passenger walking distance from arrival gate to departure gate while another consideration is the transport baggage distance from one gate to another. Our objective is to minimize the total distance between the gates that related to assign the arrival plane to the suitable gates. An integer linear programming (ILP) model is proposed to solve this gate assignment problem. We also conduct a computational experiment using CPLEX 12.1 solver in AIMMS 3.10 software to analyze the performance of the model. Results of the computational experiments are presented. The efficiency of flights assignment is depends on the ratio of the weight for both total passenger traveling distances and total baggage transport distances.
Robust quantum gates between trapped ions using shaped pulses
Energy Technology Data Exchange (ETDEWEB)
Zou, Ping, E-mail: zouping@m.scnu.edu.cn; Zhang, Zhi-Ming, E-mail: zmzhang@scnu.edu.cn
2015-12-18
We improve two existing entangling gate schemes between trapped ion qubits immersed in a large linear crystal. Based on the existing two-qubit gate schemes by applying segmented forces on the individually addressed qubits, we present a systematic method to optimize the shapes of the forces to suppress the dominant source of infidelity. The spin-dependent forces in the scheme can be from periodic photon kicks or from continuous optical pulses. The entangling gates are fast, robust, and have high fidelity. They can be used to implement scalable quantum computation and quantum simulation. - Highlights: • We present a systematic method to optimize the shape of the pulses to decouple qubits from intermediary motional modes. • Our optimized scheme can be applied to both the ultrafast gate and fast gate. • Our optimized scheme can suppress the dominant source of infidelity to arbitrary order. • When the number of trapped ions increase, the number of needed segments increases slowly.
Gated integrator with signal baseline subtraction
Energy Technology Data Exchange (ETDEWEB)
Wang, X.
1996-12-17
An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window. 5 figs.
Gated integrator with signal baseline subtraction
Energy Technology Data Exchange (ETDEWEB)
Wang, Xucheng (Lisle, IL)
1996-01-01
An ultrafast, high precision gated integrator includes an opamp having differential inputs. A signal to be integrated is applied to one of the differential inputs through a first input network, and a signal indicative of the DC offset component of the signal to be integrated is applied to the other of the differential inputs through a second input network. A pair of electronic switches in the first and second input networks define an integrating period when they are closed. The first and second input networks are substantially symmetrically constructed of matched components so that error components introduced by the electronic switches appear symmetrically in both input circuits and, hence, are nullified by the common mode rejection of the integrating opamp. The signal indicative of the DC offset component is provided by a sample and hold circuit actuated as the integrating period begins. The symmetrical configuration of the integrating circuit improves accuracy and speed by balancing out common mode errors, by permitting the use of high speed switching elements and high speed opamps and by permitting the use of a small integrating time constant. The sample and hold circuit substantially eliminates the error caused by the input signal baseline offset during a single integrating window.
Pridham, G J
2013-01-01
Solid-State Circuits provides an introduction to the theory and practice underlying solid-state circuits, laying particular emphasis on field effect transistors and integrated circuits. Topics range from construction and characteristics of semiconductor devices to rectification and power supplies, low-frequency amplifiers, sine- and square-wave oscillators, and high-frequency effects and circuits. Black-box equivalent circuits of bipolar transistors, physical equivalent circuits of bipolar transistors, and equivalent circuits of field effect transistors are also covered. This volume is divided
Santiago, John
2013-01-01
Circuits overloaded from electric circuit analysis? Many universities require that students pursuing a degree in electrical or computer engineering take an Electric Circuit Analysis course to determine who will ""make the cut"" and continue in the degree program. Circuit Analysis For Dummies will help these students to better understand electric circuit analysis by presenting the information in an effective and straightforward manner. Circuit Analysis For Dummies gives you clear-cut information about the topics covered in an electric circuit analysis courses to help
A novel method of developing all optical frequency encoded Fredkin gates
Garai, Sisir Kumar
2014-02-01
All optical reversible logic gates have significant applications in the field of optics and optoelectronics for developing different sequential and combinational circuits of optical computing, optical signal processing and in multi-valued logic operations and quantum computing. Here the author proposes a method for developing all optical three-input-output Fredkin gate and modified Fredkin gate using frequency encoded data. For this purpose the author has exploited the properties of efficient frequency conversion and faster switching speed of semiconductor optical amplifiers. Simulation results of the three input-output Fredkin gate testifies to the feasibility of the proposed scheme. These Fredkin gates are universal logic gates, and can be used to develop different all-optical logic and data processors in communication network.
New efficient five-input majority gate for quantum-dot cellular automata
International Nuclear Information System (INIS)
Farazkish, Razieh; Navi, Keivan
2012-01-01
A novel fault-tolerant five-input majority gate for quantum-dot cellular automata is presented. Quantum-dot cellular automata (QCA) is an emerging technology which is considered to be presented in future computers. Two principle logic elements in QCA are “majority gate” and “inverter.” In this paper, we propose a new approach to the design of fault-tolerant five-input majority gate by considering two-dimensional arrays of QCA cells. We analyze fault tolerance properties of such block five-input majority gate in terms of misalignment, missing, and dislocation cells. Some physical proofs are used for verifying five-input majority gate circuit layout and functionality. Our results clearly demonstrate that the redundant version of the block five-input majority gate is more robust than the standard style for this gate.
Current limiter circuit system
Witcher, Joseph Brandon; Bredemann, Michael V.
2017-09-05
An apparatus comprising a steady state sensing circuit, a switching circuit, and a detection circuit. The steady state sensing circuit is connected to a first, a second and a third node. The first node is connected to a first device, the second node is connected to a second device, and the steady state sensing circuit causes a scaled current to flow at the third node. The scaled current is proportional to a voltage difference between the first and second node. The switching circuit limits an amount of current that flows between the first and second device. The detection circuit is connected to the third node and the switching circuit. The detection circuit monitors the scaled current at the third node and controls the switching circuit to limit the amount of the current that flows between the first and second device when the scaled current is greater than a desired level.
On the dynamic analysis of piecewise-linear networks
Heemels, W.P.M.H.; Camlibel, M.K.; Schumacher, J.M.
2002-01-01
Piecewise-linear (PL) modeling is often used to approximate the behavior of nonlinear circuits. One of the possible PL modeling methodologies is based on the linear complementarity problem, and this approach has already been used extensively in the circuits and systems community for static networks. In this paper, the object of study will be dynamic electrical circuits that can be recast as linear complementarity systems, i.e., as interconnections of linear time-invariant differential equatio...
Probabilistic implementation of Hadamard and unitary gates
International Nuclear Information System (INIS)
Song Wei; Yang Ming; Cao Zhuoliang
2004-01-01
We show that the Hadamard and unitary gates could be implemented by a unitary evolution together with a measurement for any unknown state chosen from a set A={ vertical bar Ψi>, vertical bar Ψ-bar i>} (i=1,2) if and only if vertical bar Ψ1>, vertical bar Ψ2>, vertical bar Ψ-bar 1>, vertical bar Ψ-bar 2> are linearly independent. We also derive the best transformation efficiencies
Error-Transparent Quantum Gates for Small Logical Qubit Architectures
Kapit, Eliot
2018-02-01
One of the largest obstacles to building a quantum computer is gate error, where the physical evolution of the state of a qubit or group of qubits during a gate operation does not match the intended unitary transformation. Gate error stems from a combination of control errors and random single qubit errors from interaction with the environment. While great strides have been made in mitigating control errors, intrinsic qubit error remains a serious problem that limits gate fidelity in modern qubit architectures. Simultaneously, recent developments of small error-corrected logical qubit devices promise significant increases in logical state lifetime, but translating those improvements into increases in gate fidelity is a complex challenge. In this Letter, we construct protocols for gates on and between small logical qubit devices which inherit the parent device's tolerance to single qubit errors which occur at any time before or during the gate. We consider two such devices, a passive implementation of the three-qubit bit flip code, and the author's own [E. Kapit, Phys. Rev. Lett. 116, 150501 (2016), 10.1103/PhysRevLett.116.150501] very small logical qubit (VSLQ) design, and propose error-tolerant gate sets for both. The effective logical gate error rate in these models displays superlinear error reduction with linear increases in single qubit lifetime, proving that passive error correction is capable of increasing gate fidelity. Using a standard phenomenological noise model for superconducting qubits, we demonstrate a realistic, universal one- and two-qubit gate set for the VSLQ, with error rates an order of magnitude lower than those for same-duration operations on single qubits or pairs of qubits. These developments further suggest that incorporating small logical qubits into a measurement based code could substantially improve code performance.
Performance analysis of gate all around GaAsP/AlGaSb CP-TFET
Lemtur, Alemienla; Sharma, Dheeraj; Suman, Priyanka; Patel, Jyoti; Yadav, Dharmendra Singh; Sharma, Neeraj
2018-05-01
Illustration of importance of gate all around (GAA) structure and hetero-junction formed by III-V semiconductor compounds has been analysed through GaAsP/AlGaSb CP-TFET (charge plasma tunnel field effect transistor). Charge plasma concept has been incorporated here to make this device more immune towards random dopant fluctuations (RDF). A high driving current of 1.28 ×10-5 A/μm and transconductance (gm) of 96.4 μS at supply voltages VGS = 1V and VDS = 0.5V is achieved. Further, implications of employing this device in analog/RF circuits have been supported with simulated results showing a high cut-off frequency of 34.5 THz and device efficiency of 3.45 MV-1. Apart from this, an insight of the linearity performances has also been included. Simultaneously, all the results are compared with a conventional gate all around charge plasma TFET.
The negative differential resistance characteristics of an RC-IGBT and its equivalent circuit model
International Nuclear Information System (INIS)
Zhang Wenliang; Zhu Yangjun; Tian Xiaoli; Lu Shuojin
2014-01-01
A simple equivalent circuit model is proposed according to the device structure of reverse conducting insulated gate bipolar transistors (RC-IGBT). Mathematical derivation and circuit simulations indicate that this model can explain the snap-back effect (including primary snap-back effect, secondary snap-back effect, and reverse snap-back effect) and hysteresis effect perfectly. (semiconductor devices)
A probabilistic CNOT gate for coherent state qubits
International Nuclear Information System (INIS)
Oliveira, M.S.R.; Vasconcelos, H.M.; Silva, J.B.R.
2013-01-01
We propose a scheme for implementing a probabilistic controlled-NOT (CNOT) gate for coherent state qubits using only linear optics and a particular four-mode state. The proposed optical setup works, as a CNOT gate, near-faithful when |α| 2 ⩾25 and independent of the input state. The key element for realizing the proposed CNOT scheme is the entangled four-mode state.
A probabilistic CNOT gate for coherent state qubits
Energy Technology Data Exchange (ETDEWEB)
Oliveira, M.S.R.; Vasconcelos, H.M.; Silva, J.B.R., E-mail: joaobrs@ufc.br
2013-11-22
We propose a scheme for implementing a probabilistic controlled-NOT (CNOT) gate for coherent state qubits using only linear optics and a particular four-mode state. The proposed optical setup works, as a CNOT gate, near-faithful when |α|{sup 2}⩾25 and independent of the input state. The key element for realizing the proposed CNOT scheme is the entangled four-mode state.
Experimental demonstration of a Hadamard gate for coherent state qubits
Energy Technology Data Exchange (ETDEWEB)
Tipsmark, Anders; Laghaout, Amine; Andersen, Ulrik L. [Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark); Dong, Ruifang [Quantum Frequency Standards Division, National Time Service Center (NTSC), Chinese Academy of Sciences, 710600 Lintong, Shaanxi (China); Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark); Marek, Petr [Department of Optics, Palacky University, 17. listopadu 12, CZ-77146 Olomouc (Czech Republic); Jezek, Miroslav [Department of Optics, Palacky University, 17. listopadu 12, CZ-77146 Olomouc (Czech Republic); Department of Physics, Technical University of Denmark, Fysikvej, DK-2800 Kgs. Lyngby (Denmark)
2011-11-15
We discuss and make an experimental test of a probabilistic Hadamard gate for coherent state qubits. The scheme is based on linear optical components, nonclassical resources, and the joint projective action of a photon counter and a homodyne detector. We experimentally characterize the gate for the coherent states of the computational basis by full tomographic reconstruction of the transformed output states. Based on the parameters of the experiment, we simulate the fidelity for all coherent state qubits on the Bloch sphere.
Experimental demonstration of a Hadamard gate for coherent state qubits
DEFF Research Database (Denmark)
Tipsmark, Anders; Dong, Ruifang; Laghaout, Amine
2011-01-01
We discuss and make an experimental test of a probabilistic Hadamard gate for coherent state qubits. The scheme is based on linear optical components, nonclassical resources, and the joint projective action of a photon counter and a homodyne detector. We experimentally characterize the gate for t...... for the coherent states of the computational basis by full tomographic reconstruction of the transformed output states. Based on the parameters of the experiment, we simulate the fidelity for all coherent state qubits on the Bloch sphere....
Amplifying genetic logic gates.
Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew
2013-05-03
Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.
International Nuclear Information System (INIS)
Hanson, C.W. III; Hoffman, E.A.
1995-01-01
There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart
Integrated circuits for multimedia applications
DEFF Research Database (Denmark)
Vandi, Luca
2007-01-01
, and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt...... the impact of substrate-induced currents. Basic models are derived in the design phase, and the technological limits of the device are considered. Measurement results show that a very compact coil can provide ~1nH inductance up to 20GHz (physical limit for the measurement equipment), with a peak quality...
The role of Snell's law for a magnonic majority gate.
Kanazawa, Naoki; Goto, Taichi; Sekiguchi, Koji; Granovsky, Alexander B; Ross, Caroline A; Takagi, Hiroyuki; Nakamura, Yuichi; Uchida, Hironaga; Inoue, Mitsuteru
2017-08-11
In the fifty years since the postulation of Moore's Law, the increasing energy consumption in silicon electronics has motivated research into emerging devices. An attractive research direction is processing information via the phase of spin waves within magnonic-logic circuits, which function without charge transport and the accompanying heat generation. The functional completeness of magnonic logic circuits based on the majority function was recently proved. However, the performance of such logic circuits was rather poor due to the difficulty of controlling spin waves in the input junction of the waveguides. Here, we show how Snell's law describes the propagation of spin waves in the junction of a Ψ-shaped magnonic majority gate composed of yttrium iron garnet with a partially metallized surface. Based on the analysis, we propose a magnonic counterpart of a core-cladding waveguide to control the wave propagation in the junction. This study has therefore experimentally demonstrated a fundamental building block of a magnonic logic circuit.
Rapidly reconfigurable all-optical universal logic gate
Goddard, Lynford L.; Bond, Tiziana C.; Kallman, Jeffrey S.
2010-09-07
A new reconfigurable cascadable all-optical on-chip device is presented. The gate operates by combining the Vernier effect with a novel effect, the gain-index lever, to help shift the dominant lasing mode from a mode where the laser light is output at one facet to a mode where it is output at the other facet. Since the laser remains above threshold, the speed of the gate for logic operations as well as for reprogramming the function of the gate is primarily limited to the small signal optical modulation speed of the laser, which can be on the order of up to about tens of GHz. The gate can be rapidly and repeatedly reprogrammed to perform any of the basic digital logic operations by using an appropriate analog optical or electrical signal at the gate selection port. Other all-optical functionality includes wavelength conversion, signal duplication, threshold switching, analog to digital conversion, digital to analog conversion, signal routing, and environment sensing. Since each gate can perform different operations, the functionality of such a cascaded circuit grows exponentially.
Investigation on the Short Circuit Safe Operation Area of SiC MOSFET Power Modules
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Luo, Haoze; Iannuzzo, Francesco
2016-01-01
This paper gives a better insight of the short circuit capability of state-of-the-art SiC MOSFET power modules rated at 1.2 kV by highlighting the physical limits under different operating conditions. Two different failure mechanisms have been identiﬁed, both reducing the short-circuit capability...... of SiC power modules in respect to discrete SiC devices. Based on such failure mechanisms, two short circuit criteria (i.e., short circuit current-based criterion and gate voltage-based criterion) are proposed in order to ensure their robustness under short-circuit conditions. A Safe Operation Area (SOA...
A reconfigurable NAND/NOR genetic logic gate.
Goñi-Moreno, Angel; Amos, Martyn
2012-09-18
Engineering genetic Boolean logic circuits is a major research theme of synthetic biology. By altering or introducing connections between genetic components, novel regulatory networks are built in order to mimic the behaviour of electronic devices such as logic gates. While electronics is a highly standardized science, genetic logic is still in its infancy, with few agreed standards. In this paper we focus on the interpretation of logical values in terms of molecular concentrations. We describe the results of computational investigations of a novel circuit that is able to trigger specific differential responses depending on the input standard used. The circuit can therefore be dynamically reconfigured (without modification) to serve as both a NAND/NOR logic gate. This multi-functional behaviour is achieved by a) varying the meanings of inputs, and b) using branch predictions (as in computer science) to display a constrained output. A thorough computational study is performed, which provides valuable insights for the future laboratory validation. The simulations focus on both single-cell and population behaviours. The latter give particular insights into the spatial behaviour of our engineered cells on a surface with a non-homogeneous distribution of inputs. We present a dynamically-reconfigurable NAND/NOR genetic logic circuit that can be switched between modes of operation via a simple shift in input signal concentration. The circuit addresses important issues in genetic logic that will have significance for more complex synthetic biology applications.
Intuitive analog circuit design
Thompson, Marc
2013-01-01
Intuitive Analog Circuit Design outlines ways of thinking about analog circuits and systems that let you develop a feel for what a good, working analog circuit design should be. This book reflects author Marc Thompson's 30 years of experience designing analog and power electronics circuits and teaching graduate-level analog circuit design, and is the ideal reference for anyone who needs a straightforward introduction to the subject. In this book, Dr. Thompson describes intuitive and ""back-of-the-envelope"" techniques for designing and analyzing analog circuits, including transistor amplifi
The circuit designer's companion
Williams, Tim
1991-01-01
The Circuit Designer's Companion covers the theoretical aspects and practices in analogue and digital circuit design. Electronic circuit design involves designing a circuit that will fulfill its specified function and designing the same circuit so that every production model of it will fulfill its specified function, and no other undesired and unspecified function.This book is composed of nine chapters and starts with a review of the concept of grounding, wiring, and printed circuits. The subsequent chapters deal with the passive and active components of circuitry design. These topics are foll
Radiation-hard silicon gate bulk CMOS cell family
International Nuclear Information System (INIS)
Gibbon, C.F.; Habing, D.H.; Flores, R.S.
1980-01-01
A radiation-hardened bulk silicon gate CMOS technology and a topologically simple, high-performance dual-port cell family utilizing this process have been demonstrated. Additional circuits, including a random logic circuit containing 4800 transistors on a 236 x 236 mil die, are presently being designed and processed. Finally, a joint design-process effort is underway to redesign the cell family in reduced design rules; this results in a factor of 2.5 cell size reduction and a factor of 3 decrease in chip interconnect area. Cell performance is correspondingly improved
Analog integrated circuits design for processing physiological signals.
Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting
2010-01-01
Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.
Gate valve performance prediction
International Nuclear Information System (INIS)
Harrison, D.H.; Damerell, P.S.; Wang, J.K.; Kalsi, M.S.; Wolfe, K.J.
1994-01-01
The Electric Power Research Institute is carrying out a program to improve the performance prediction methods for motor-operated valves. As part of this program, an analytical method to predict the stem thrust required to stroke a gate valve has been developed and has been assessed against data from gate valve tests. The method accounts for the loads applied to the disc by fluid flow and for the detailed mechanical interaction of the stem, disc, guides, and seats. To support development of the method, two separate-effects test programs were carried out. One test program determined friction coefficients for contacts between gate valve parts by using material specimens in controlled environments. The other test program investigated the interaction of the stem, disc, guides, and seat using a special fixture with full-sized gate valve parts. The method has been assessed against flow-loop and in-plant test data. These tests include valve sizes from 3 to 18 in. and cover a considerable range of flow, temperature, and differential pressure. Stem thrust predictions for the method bound measured results. In some cases, the bounding predictions are substantially higher than the stem loads required for valve operation, as a result of the bounding nature of the friction coefficients in the method
Stanford, Duke, Rice,... and Gates?
Carey, Kevin
2009-01-01
This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…
Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates
International Nuclear Information System (INIS)
Duce, A Del; Savory, S; Bayvel, P
2006-01-01
In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another
Implementation of a three-qubit refined Deutsch-Jozsa algorithm using SFG quantum logic gates
Energy Technology Data Exchange (ETDEWEB)
Duce, A Del; Savory, S; Bayvel, P [Department of Electronic and Electrical Engineering, University College London, Torrington Place, London WC1E 7JE (United Kingdom)
2006-05-31
In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.
Implementation of a three-qubit refined Deutsch Jozsa algorithm using SFG quantum logic gates
DelDuce, A.; Savory, S.; Bayvel, P.
2006-05-01
In this paper we present a quantum logic circuit which can be used for the experimental demonstration of a three-qubit solid state quantum computer based on a recent proposal of optically driven quantum logic gates. In these gates, the entanglement of randomly placed electron spin qubits is manipulated by optical excitation of control electrons. The circuit we describe solves the Deutsch problem with an improved algorithm called the refined Deutsch-Jozsa algorithm. We show that it is possible to select optical pulses that solve the Deutsch problem correctly, and do so without losing quantum information to the control electrons, even though the gate parameters vary substantially from one gate to another.
Gilbertson, Steve
The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.
A gating grid driver for time projection chambers
Energy Technology Data Exchange (ETDEWEB)
Tangwancharoen, S.; Lynch, W.G.; Barney, J.; Estee, J. [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States); Department of Physics and Astronomy, Michigan State University, East Lansing, MI 48824 (United States); Shane, R. [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States); Tsang, M.B., E-mail: tsang@nscl.msu.edu [National Superconducting Cyclotron Laboratory, Michigan State University, East Lansing, MI 48824 (United States); Department of Physics and Astronomy, Michigan State University, East Lansing, MI 48824 (United States); Zhang, Y. [Department of Physics, Tsinghua University, Beijing 100084 (China); Isobe, T.; Kurata-Nishimura, M. [RIKEN Nishina Center, Hirosawa 2-1, Wako, Saitama 351-0198 (Japan); Murakami, T. [Department of Physics, Kyoto University, Kita-shirakawa, Kyoto 606–8502 (Japan); Xiao, Z.G. [Department of Physics, Tsinghua University, Beijing 100084 (China); Zhang, Y.F. [College of Nuclear Science and Technology, Beijing Normal University, Beijing 100875 (China)
2017-05-01
A simple but novel driver system has been developed to operate the wire gating grid of a Time Projection Chamber (TPC). This system connects the wires of the gating grid to its driver via low impedance transmission lines. When the gating grid is open, all wires have the same voltage allowing drift electrons, produced by the ionization of the detector gas molecules, to pass through to the anode wires. When the grid is closed, the wires have alternating higher and lower voltages causing the drift electrons to terminate at the more positive wires. Rapid opening of the gating grid with low pickup noise is achieved by quickly shorting the positive and negative wires to attain the average bias potential with N-type and P-type MOSFET switches. The circuit analysis and simulation software SPICE shows that the driver restores the gating grid voltage to 90% of the opening voltage in less than 0.20 µs, for small values of the termination resistors. When tested in the experimental environment of a time projection chamber larger termination resistors were chosen so that the driver opens the gating grid in 0.35 µs. In each case, opening time is basically characterized by the RC constant given by the resistance of the switches and terminating resistors and the capacitance of the gating grid and its transmission line. By adding a second pair of N-type and P-type MOSFET switches, the gating grid is closed by restoring 99% of the original charges to the wires within 3 µs.
Chaplin, J C; Russell, N A; Krasnogor, N
2012-07-01
In this paper we detail experimental methods to implement registers, logic gates and logic circuits using populations of photochromic molecules exposed to sequences of light pulses. Photochromic molecules are molecules with two or more stable states that can be switched reversibly between states by illuminating with appropriate wavelengths of radiation. Registers are implemented by using the concentration of molecules in each state in a given sample to represent an integer value. The register's value can then be read using the intensity of a fluorescence signal from the sample. Logic gates have been implemented using a register with inputs in the form of light pulses to implement 1-input/1-output and 2-input/1-output logic gates. A proof of concept logic circuit is also demonstrated; coupled with the software workflow describe the transition from a circuit design to the corresponding sequence of light pulses. Copyright © 2012 Elsevier Ireland Ltd. All rights reserved.
Molecular logic gates: the past, present and future.
Erbas-Cakmak, Sundus; Kolemen, Safacan; Sedgwick, Adam C; Gunnlaugsson, Thorfinnur; James, Tony D; Yoon, Juyoung; Akkaya, Engin U
2018-04-03
The field of molecular logic gates originated 25 years ago, when A. P. de Silva published a seminal article in Nature. Stimulated by this ground breaking research, scientists were inspired to join the race to simulate the workings of the fundamental components of integrated circuits using molecules. The rules of this game of mimicry were flexible, and have evolved and morphed over the years. This tutorial review takes a look back on and provides an overview of the birth and growth of the field of molecular logics. Spinning-off from chemosensor research, molecular logic gates quickly proved themselves to be more than intellectual exercises and are now poised for many potential practical applications. The ultimate goal of this vein of research became clearer only recently - to "boldly go where no silicon-based logic gate has gone before" and seek out a new deeper understanding of life inside tissues and cells.
Methodology for Analysis, Modeling and Simulation of Airport Gate-waiting Delays
Wang, Jianfeng
availability. Analysis of the worst days at six major airports in the summer of 2007 indicates that major gate-waiting delays are primarily due to operational disruptions---specifically, extended gate occupancy time, reduced gate availability and higher-than-scheduled arrival rate (usually due to arrival delay). Major gate-waiting delays are not a result of over-scheduling. The second part of this dissertation presents a simulation model to evaluate the impact of gate operational disruptions and gate-waiting-delay mitigation strategies, including building new gates, implementing common gates, using overnight off-gate parking and adopting self-docking gates. Simulation results show the following effects of disruptions: (i) The impact of arrival delay in a time window (e.g. 7 pm to 9 pm) on gate-waiting delay is bounded. (ii) The impact of longer-than-scheduled gate-occupancy times in a time window on gate-waiting delay can be unbounded and gate-waiting delay can increase linearly as the disruption level increases. (iii) Small reductions in gate availability have a small impact on gate-waiting delay due to slack gate capacity, while larger reductions have a non-linear impact as slack gate capacity is used up. Simulation results show the following effects of mitigation strategies: (i) Implementing common gates is an effective mitigation strategy, especially for airports with a flight schedule not dominated by one carrier, such as LGA. (ii) The overnight off-gate rule is effective in mitigating gate-waiting delay for flights stranded overnight following departure cancellations. This is especially true at airports where the gate utilization is at maximum overnight, such as LGA and DFW. The overnight off-gate rule can also be very effective to mitigate gate-waiting delay due to operational disruptions in evenings. (iii) Self-docking gates are effective in mitigating gate-waiting delay due to reduced gate availability.
Realization of quantum gates with multiple control qubits or multiple target qubits in a cavity
Waseem, Muhammad; Irfan, Muhammad; Qamar, Shahid
2015-06-01
We propose a scheme to realize a three-qubit controlled phase gate and a multi-qubit controlled NOT gate of one qubit simultaneously controlling n-target qubits with a four-level quantum system in a cavity. The implementation time for multi-qubit controlled NOT gate is independent of the number of qubit. Three-qubit phase gate is generalized to n-qubit phase gate with multiple control qubits. The number of steps reduces linearly as compared to conventional gate decomposition method. Our scheme can be applied to various types of physical systems such as superconducting qubits coupled to a resonator and trapped atoms in a cavity. Our scheme does not require adjustment of level spacing during the gate implementation. We also show the implementation of Deutsch-Joza algorithm. Finally, we discuss the imperfections due to cavity decay and the possibility of physical implementation of our scheme.
Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.
2009-01-01
The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.
Electrical Circuits and Water Analogies
Smith, Frederick A.; Wilson, Jerry D.
1974-01-01
Briefly describes water analogies for electrical circuits and presents plans for the construction of apparatus to demonstrate these analogies. Demonstrations include series circuits, parallel circuits, and capacitors. (GS)
Realization of a quantum Hamiltonian Boolean logic gate on the Si(001):H surface.
Kolmer, Marek; Zuzak, Rafal; Dridi, Ghassen; Godlewski, Szymon; Joachim, Christian; Szymonski, Marek
2015-08-07
The design and construction of the first prototypical QHC (Quantum Hamiltonian Computing) atomic scale Boolean logic gate is reported using scanning tunnelling microscope (STM) tip-induced atom manipulation on an Si(001):H surface. The NOR/OR gate truth table was confirmed by dI/dU STS (Scanning Tunnelling Spectroscopy) tracking how the surface states of the QHC quantum circuit on the Si(001):H surface are shifted according to the input logical status.
Energy dissipation dataset for reversible logic gates in quantum dot-cellular automata
Directory of Open Access Journals (Sweden)
Ali Newaz Bahar
2017-02-01
Full Text Available This paper presents an energy dissipation dataset of different reversible logic gates in quantum-dot cellular automata. The proposed circuits have been designed and verified using QCADesigner simulator. Besides, the energy dissipation has been calculated under three different tunneling energy level at temperature T=2 K. For estimating the energy dissipation of proposed gates; QCAPro tool has been employed.
Coarse-Grained Online Monitoring of BTI Aging by Reusing Power-Gating Infrastructure
Tenentes, V.; Rossi, D.; Sheng Yang,; Khursheed, S.; Al-Hashimi, B.M.; Gunn, S.R.
2017-01-01
In this paper, we present a novel coarse-grained technique for monitoring online the Bias Temperature Instability (BTI) aging of circuits by exploiting their power gating infrastructure. The proposed technique relies on monitoring the discharge time of the virtual-power-network during stand-by operations, the value of which depends on the threshold voltage of the CMOS devices in the power-gated design (PGD). It does not require any distributed sensors, because the virtual-power network is alr...
REA, Editors of
2012-01-01
REA's Essentials provide quick and easy access to critical information in a variety of different fields, ranging from the most basic to the most advanced. As its name implies, these concise, comprehensive study guides summarize the essentials of the field covered. Essentials are helpful when preparing for exams, doing homework and will remain a lasting reference source for students, teachers, and professionals. Electric Circuits I includes units, notation, resistive circuits, experimental laws, transient circuits, network theorems, techniques of circuit analysis, sinusoidal analysis, polyph
Bahar, Ali Newaz; Waheed, Sajjad
2016-01-01
The fundamental logical element of a quantum-dot cellular automata (QCA) circuit is majority voter gate (MV). The efficiency of a QCA circuit is depends on the efficiency of the MV. This paper presents an efficient single layer five-input majority voter gate (MV5). The structure of proposed MV5 is very simple and easy to implement in any logical circuit. This proposed MV5 reduce number of cells and use conventional QCA cells. However, using MV5 a multilayer 1-bit full-adder (FA) is designed. The functional accuracy of the proposed MV5 and FA are confirmed by QCADesigner a well-known QCA layout design and verification tools. Furthermore, the power dissipation of proposed circuits are estimated, which shows that those circuits dissipate extremely small amount of energy and suitable for reversible computing. The simulation outcomes demonstrate the superiority of the proposed circuit.
Synchronization circuit for shaping electron beam picosecond pulses
International Nuclear Information System (INIS)
Pavlov, Yu.S.; Solov'ev, N.G.; Tomnikov, A.P.
1985-01-01
A fast response circuit of modulator trigger pulse synchronization of a deflector of the electron linear accelerator at 13 MeV with the given phase of HF-voltage is described. The circuit is constructed using K500 and K100 integrated emitter-coupled logics circuits. Main parameters of a synchropulse are duration of 20-50 ns, pulse rise time of 1-5 ns, pulse amplitude >=10 V, delay instability of a trigger pulse <=+-0.05 ns. A radiopulse with 3 μs duration, 5 V amplitude and 400 Hz frequency enters the circuit input. The circuit can operate at both pulsed operation and continuous modes
Treu, C.A. Jr.
1999-08-31
A piezoelectric motor drive circuit is provided which utilizes the piezoelectric elements as oscillators and a Meacham half-bridge approach to develop feedback from the motor ground circuit to produce a signal to drive amplifiers to power the motor. The circuit automatically compensates for shifts in harmonic frequency of the piezoelectric elements due to pressure and temperature changes. 7 figs.
DEFF Research Database (Denmark)
2009-01-01
A load testing circuit a circuit tests the load impedance of a load connected to an amplifier. The load impedance includes a first terminal and a second terminal, the load testing circuit comprising a signal generator providing a test signal of a defined bandwidth to the first terminal of the load...
Bergstra, J.A.; Ponse, A.
2010-01-01
Short-circuit evaluation denotes the semantics of propositional connectives in which the second argument is only evaluated if the first argument does not suffice to determine the value of the expression. In programming, short-circuit evaluation is widely used. A short-circuit logic is a variant of
Louwsma, S.M.; Vertregt, Maarten
2011-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital
Louwsma, S.M.; Vertregt, Maarten
2010-01-01
A sampling circuit for sampling a signal is disclosed. The sampling circuit comprises a plurality of sampling channels adapted to sample the signal in time-multiplexed fashion, each sampling channel comprising a respective track-and-hold circuit connected to a respective analogue to digital
Energy Technology Data Exchange (ETDEWEB)
Alvey, Christopher; Orphanidou, C.; Coleman, J.; McIntyre, A.; Golding, S.; Kochanski, G. [University of Oxford, Oxford (United Kingdom)
2008-11-15
The use of gated or ECG triggered MR is a well-established technique and developments in coil technology have enabled this approach to be applied to areas other than the heart. However, the image quality of gated (ECG or cine) versus non-gated or real-time has not been extensively evaluated in the mouth. We evaluate two image sequences by developing an automatic image processing technique which compares how well the image represents known anatomy. Four subjects practised experimental poly-syllabic sentences prior to MR scanning. Using a 1.5 T MR unit, we acquired comparable gated (using an artificial trigger) and non-gated sagittal images during speech. We then used an image processing algorithm to model the image grey along lines that cross the airway. Each line involved an eight parameter non-linear equation to model of proton densities, edges, and dimensions. Gated and non-gated images show similar spatial resolution, with non-gated images being slightly sharper (10% better resolution, less than 1 pixel). However, the gated sequences generated images of substantially lower inherent noise, and substantially better discrimination between air and tissue. Additionally, the gated sequences demonstrate a very much greater temporal resolution. Overall, image quality is better with gated imaging techniques, especially given their superior temporal resolution. Gated techniques are limited by the repeatability of the motions involved, and we have shown that speech to a metronome can be sufficiently repeatable to allow high-quality gated magnetic resonance imaging images. We suggest that gated sequences may be useful for evaluating other types of repetitive movement involving the joints and limb motions. (orig.)
International Nuclear Information System (INIS)
Alvey, Christopher; Orphanidou, C.; Coleman, J.; McIntyre, A.; Golding, S.; Kochanski, G.
2008-01-01
The use of gated or ECG triggered MR is a well-established technique and developments in coil technology have enabled this approach to be applied to areas other than the heart. However, the image quality of gated (ECG or cine) versus non-gated or real-time has not been extensively evaluated in the mouth. We evaluate two image sequences by developing an automatic image processing technique which compares how well the image represents known anatomy. Four subjects practised experimental poly-syllabic sentences prior to MR scanning. Using a 1.5 T MR unit, we acquired comparable gated (using an artificial trigger) and non-gated sagittal images during speech. We then used an image processing algorithm to model the image grey along lines that cross the airway. Each line involved an eight parameter non-linear equation to model of proton densities, edges, and dimensions. Gated and non-gated images show similar spatial resolution, with non-gated images being slightly sharper (10% better resolution, less than 1 pixel). However, the gated sequences generated images of substantially lower inherent noise, and substantially better discrimination between air and tissue. Additionally, the gated sequences demonstrate a very much greater temporal resolution. Overall, image quality is better with gated imaging techniques, especially given their superior temporal resolution. Gated techniques are limited by the repeatability of the motions involved, and we have shown that speech to a metronome can be sufficiently repeatable to allow high-quality gated magnetic resonance imaging images. We suggest that gated sequences may be useful for evaluating other types of repetitive movement involving the joints and limb motions. (orig.)
Energy Technology Data Exchange (ETDEWEB)
Reshetov, N.E.
1980-01-01
Relay equipment using semiconductor components (such as those containing gates using planar transformers, and a relay in networks which control the operational time of a relay) are widely used in the automation equipment of electric power systems. A scheme where a gate in the form of an integrated circuit is used is given.
Wei, Hai-Rui; Deng, Fu-Guo
2014-01-13
We present some compact quantum circuits for a deterministic quantum computing on electron-spin qubits assisted by quantum dots inside single-side optical microcavities, including the CNOT, Toffoli, and Fredkin gates. They are constructed by exploiting the giant optical Faraday rotation induced by a single-electron spin in a quantum dot inside a single-side optical microcavity as a result of cavity quantum electrodynamics. Our universal quantum gates have some advantages. First, all the gates are accomplished with a success probability of 100% in principle. Second, our schemes require no additional electron-spin qubits and they are achieved by some input-output processes of a single photon. Third, our circuits for these gates are simple and economic. Moreover, our devices for these gates work in both the weak coupling and the strong coupling regimes, and they are feasible in experiment.
Area efficient digital logic NOT gate using single electron box (SEB
Directory of Open Access Journals (Sweden)
Bahrepour Davoud
2017-01-01
Full Text Available The continuing scaling down of complementary metal oxide semiconductor (CMOS has led researchers to build new devices with nano dimensions, whose behavior will be interpreted based on quantum mechanics. Single-electron devices (SEDs are promising candidates for future VLSI applications, due to their ultra small dimensions and lower power consumption. In most SED based digital logic designs, a single gate is introduced and its performance discussed. While in the SED based circuits the fan out of designed gate circuit should be considered and measured. In the other words, cascaded SED based designs must work properly so that the next stage(s should be driven by the previous stage. In this paper, previously NOT gate based on single electron box (SEB which is an important structure in SED technology, is reviewed in order to obtain correct operation in series connections. The correct operation of the NOT gate is investigated in a buffer circuit which uses two connected NOT gate in series. Then, for achieving better performance the designed buffer circuit is improved by the use of scaling process.
DEFF Research Database (Denmark)
Pandey, Bishwajeet; Pandey, Sujeet; Sharma, Shivani
2016-01-01
In this paper, we are integrating clock gating in design of energy efficient equation solver circuits based on Vedic mathematics. Clock gating is one of the best energy efficient techniques. The Sutra 'SunyamSamyasamuccaye' says thatif sum of numerator and sum of denominator is same then we can e......, 94.54% for 1800MHz, and 94.02% for 2.2GHz, when we use gated clock instead of un gated one on 40nm FPGA and temperature is 329.85K. Power consumption in 28nm FPGA is less than 40nm FPGA....
International Nuclear Information System (INIS)
Rousseau, P.
1968-01-01
In a first part, after a brief recall concerning 'planar' technology we discuss the various parasitic elements associated with integrated circuits components. Mathematical formulae of these elements are derived. In a second part, we present a matrix of 22 transistors and 12 resistors which has been realized. This matrix enables the integration of the major part of nuclear circuits. Some of the obtained circuits are shown, particularly an emitter coupled logic gate which presents good electrical behaviour. (author) [fr
Study on effective MOSFET channel length extracted from gate capacitance
Tsuji, Katsuhiro; Terada, Kazuo; Fujisaka, Hisato
2018-01-01
The effective channel length (L GCM) of metal-oxide-semiconductor field-effect transistors (MOSFETs) is extracted from the gate capacitances of actual-size MOSFETs, which are measured by charge-injection-induced-error-free charge-based capacitance measurement (CIEF CBCM). To accurately evaluate the capacitances between the gate and the channel of test MOSFETs, the parasitic capacitances are removed by using test MOSFETs having various channel sizes and a source/drain reference device. A strong linear relationship between the gate-channel capacitance and the design channel length is obtained, from which L GCM is extracted. It is found that L GCM is slightly less than the effective channel length (L CRM) extracted from the measured MOSFET drain current. The reason for this is discussed, and it is found that the capacitance between the gate electrode and the source and drain regions affects this extraction.
Radiation sensitivity of integrated circuits Pt. 1
International Nuclear Information System (INIS)
Bereczkine Kerenyi, Ilona
1986-01-01
The cosmic ray sensitivity of CMOS integrated circuits are overviewed in three parts. The aim is to analyze the effects of ionizing radiation on the degradation of electronic parameters, the effects of the electric state during irradiation, and the radiation hardening of ICs. In this Part 1 a general introduction of the response of semiconductors to cosmic radiation is given, and the radiation tolerance and hardening of small-scale integrated CMOS ICs is analyzed in detail. The devices include various basic inverters and simple gate ICs. (R.P.)
Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging
Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng
2013-09-01
A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.
DeForest, Craig; Seaton, Daniel B.; Darnell, John A.
2017-08-01
I present and demonstrate a new, general purpose post-processing technique, "3D noise gating", that can reduce image noise by an order of magnitude or more without effective loss of spatial or temporal resolution in typical solar applications.Nearly all scientific images are, ultimately, limited by noise. Noise can be direct Poisson "shot noise" from photon counting effects, or introduced by other means such as detector read noise. Noise is typically represented as a random variable (perhaps with location- or image-dependent characteristics) that is sampled once per pixel or once per resolution element of an image sequence. Noise limits many aspects of image analysis, including photometry, spatiotemporal resolution, feature identification, morphology extraction, and background modeling and separation.Identifying and separating noise from image signal is difficult. The common practice of blurring in space and/or time works because most image "signal" is concentrated in the low Fourier components of an image, while noise is evenly distributed. Blurring in space and/or time attenuates the high spatial and temporal frequencies, reducing noise at the expense of also attenuating image detail. Noise-gating exploits the same property -- "coherence" -- that we use to identify features in images, to separate image features from noise.Processing image sequences through 3-D noise gating results in spectacular (more than 10x) improvements in signal-to-noise ratio, while not blurring bright, resolved features in either space or time. This improves most types of image analysis, including feature identification, time sequence extraction, absolute and relative photometry (including differential emission measure analysis), feature tracking, computer vision, correlation tracking, background modeling, cross-scale analysis, visual display/presentation, and image compression.I will introduce noise gating, describe the method, and show examples from several instruments (including SDO
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
Energy Technology Data Exchange (ETDEWEB)
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S., E-mail: miaoxs@mail.hust.edu.cn [Wuhan National Laboratory for Optoelectronics (WNLO), Huazhong University of Science and Technology (HUST), Wuhan 430074 (China); School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan 430074 (China)
2013-12-21
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices.
Nonvolatile “AND,” “OR,” and “NOT” Boolean logic gates based on phase-change memory
International Nuclear Information System (INIS)
Li, Y.; Zhong, Y. P.; Deng, Y. F.; Zhou, Y. X.; Xu, L.; Miao, X. S.
2013-01-01
Electronic devices or circuits that can implement both logic and memory functions are regarded as the building blocks for future massive parallel computing beyond von Neumann architecture. Here we proposed phase-change memory (PCM)-based nonvolatile logic gates capable of AND, OR, and NOT Boolean logic operations verified in SPICE simulations and circuit experiments. The logic operations are parallel computing and results can be stored directly in the states of the logic gates, facilitating the combination of computing and memory in the same circuit. These results are encouraging for ultralow-power and high-speed nonvolatile logic circuit design based on novel memory devices
Six-Correction Logic (SCL Gates in Quantum-dot Cellular Automata (QCA
Directory of Open Access Journals (Sweden)
Md. Anisur Rahman
2015-11-01
Full Text Available Quantum Dot Cellular Automata (QCA is a promising nanotechnology in Quantum electronics for its ultra low power consumption, faster speed and small size features. It has significant advantages over the Complementary Metal–Oxide–Semiconductor (CMOS technology. This paper present, a novel QCA representation of Six-Correction Logic (SCL gate based on QCA logic gates: the Maj3, Maj AND gate and Maj OR. In order to design and verify the functionality of the proposed layout, QCADesigner a familiar QCA simulator has been employed. The simulation results confirm correctness of the claims and its usefulness in designing a digital circuits.
Ochoa, Agustin
2016-01-01
This book describes a consistent and direct methodology to the analysis and design of analog circuits with particular application to circuits containing feedback. The analysis and design of circuits containing feedback is generally presented by either following a series of examples where each circuit is simplified through the use of insight or experience (someone else’s), or a complete nodal-matrix analysis generating lots of algebra. Neither of these approaches leads to gaining insight into the design process easily. The author develops a systematic approach to circuit analysis, the Driving Point Impedance and Signal Flow Graphs (DPI/SFG) method that does not require a-priori insight to the circuit being considered and results in factored analysis supporting the design function. This approach enables designers to account fully for loading and the bi-directional nature of elements both in the feedback path and in the amplifier itself, properties many times assumed negligible and ignored. Feedback circuits a...
Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate
International Nuclear Information System (INIS)
Razieh Farazkish, R.; Sayedsalehi, S.; Navi, K.
2012-01-01
Quantum-dot Cellular Automata (QCA) is one of the most attractive technologies for computing at nano scale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states) and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.
Instrumentation for Gate Current Noise Measurements on sub-100 nm MOS Transistors
Gaioni, L; Ratti, L; Re, V; Speziali, V; Traversi, G
2008-01-01
This work describes a measuring system that was developed to characterize the gate current noise performances of CMOS devices with minimum feature size in the 100 nm span. These devices play an essential role in the design of present daymixedsignal integrated circuits, because of the advantages associated with the scaling process. The reduction in the gate oxide thickness brought about by CMOS technology downscaling leads to a non-negligible gate current due to direct tunneling phenomena; this current represents a noise source which requires an accurate characterization for optimum analog design. In this paper, two instruments able to perform measurements in two different ranges of gate current values will be discussed. Some of the results of gate current noise characterization will also be presented.
Novel Design for Quantum Dots Cellular Automata to Obtain Fault-Tolerant Majority Gate
Directory of Open Access Journals (Sweden)
Razieh Farazkish
2012-01-01
Full Text Available Quantum-dot Cellular Automata (QCA is one of the most attractive technologies for computing at nanoscale. The principle element in QCA is majority gate. In this paper, fault-tolerance properties of the majority gate is analyzed. This component is suitable for designing fault-tolerant QCA circuits. We analyze fault-tolerance properties of three-input majority gate in terms of misalignment, missing, and dislocation cells. In order to verify the functionality of the proposed component some physical proofs using kink energy (the difference in electrostatic energy between the two polarization states and computer simulations using QCA Designer tool are provided. Our results clearly demonstrate that the redundant version of the majority gate is more robust than the standard style for this gate.
Bilal, Bisma; Ahmed, Suhaib; Kakkar, Vipan
2018-02-01
The challenges which the CMOS technology is facing toward the end of the technology roadmap calls for an investigation of various logical and technological solutions to CMOS at the nano scale. Two such paradigms which are considered in this paper are the reversible logic and the quantum-dot cellular automata (QCA) nanotechnology. Firstly, a new 3 × 3 reversible and universal gate, RG-QCA, is proposed and implemented in QCA technology using conventional 3-input majority voter based logic. Further the gate is optimized by using explicit interaction of cells and this optimized gate is then used to design an optimized modular full adder in QCA. Another configuration of RG-QCA gate, CRG-QCA, is then proposed which is a 4 × 4 gate and includes the fault tolerant characteristics and parity preserving nature. The proposed CRG-QCA gate is then tested to design a fault tolerant full adder circuit. Extensive comparisons of gate and adder circuits are drawn with the existing literature and it is envisaged that our proposed designs perform better and are cost efficient in QCA technology.
G(sup 4)FET Implementations of Some Logic Circuits
Mojarradi, Mohammad; Akarvardar, Kerem; Cristoleveanu, Sorin; Gentil, Paul; Blalock, Benjamin; Chen, Suhan
2009-01-01
Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration
Digitally controlled oscillator design with a variable capacitance XOR gate
International Nuclear Information System (INIS)
Kumar, Manoj; Arya, Sandeep K.; Pandey, Sujata
2011-01-01
A digitally controlled oscillator (DCO) using a three-transistor XOR gate as the variable load has been presented. A delay cell using an inverter and a three-transistor XOR gate as the variable capacitance is also proposed. Three-, five- and seven-stage DCO circuits have been designed using the proposed delay cell. The output frequency is controlled digitally with bits applied to the delay cells. The three-bit DCO shows output frequency and power consumption variation in the range of 3.2486–4.0267 GHz and 0.6121–0.3901 mW, respectively, with a change in the control word 111–000. The five-bit DCO achieves frequency and power of 1.8553–2.3506 GHz and 1.0202–0.6501 mW, respectively, with a change in the control word 11111–00000. Moreover, the seven-bit DCO shows a frequency and power consumption variation of 1.3239–1.6817 GHz and 1.4282–0.9102 mW, respectively, with a varying control word 1111111–0000000. The power consumption and output frequency of the proposed circuits have been compared with earlier reported circuits and the present approaches show significant improvements. (semiconductor integrated circuits)
Shilov, Georgi E
1977-01-01
Covers determinants, linear spaces, systems of linear equations, linear functions of a vector argument, coordinate transformations, the canonical form of the matrix of a linear operator, bilinear and quadratic forms, Euclidean spaces, unitary spaces, quadratic forms in Euclidean and unitary spaces, finite-dimensional space. Problems with hints and answers.
100-nm gate lithography for double-gate transistors
Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.
2001-09-01
The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.
Circuit for Driving Piezoelectric Transducers
Randall, David P.; Chapsky, Jacob
2009-01-01
The figure schematically depicts an oscillator circuit for driving a piezoelectric transducer to excite vibrations in a mechanical structure. The circuit was designed and built to satisfy application-specific requirements to drive a selected one of 16 such transducers at a regulated amplitude and frequency chosen to optimize the amount of work performed by the transducer and to compensate for both (1) temporal variations of the resonance frequency and damping time of each transducer and (2) initially unknown differences among the resonance frequencies and damping times of different transducers. In other words, the circuit is designed to adjust itself to optimize the performance of whichever transducer is selected at any given time. The basic design concept may be adaptable to other applications that involve the use of piezoelectric transducers in ultrasonic cleaners and other apparatuses in which high-frequency mechanical drives are utilized. This circuit includes three resistor-capacitor networks that, together with the selected piezoelectric transducer, constitute a band-pass filter having a peak response at a frequency of about 2 kHz, which is approximately the resonance frequency of the piezoelectric transducers. Gain for generating oscillations is provided by a power hybrid operational amplifier (U1). A junction field-effect transistor (Q1) in combination with a resistor (R4) is used as a voltage-variable resistor to control the magnitude of the oscillation. The voltage-variable resistor is part of a feedback control loop: Part of the output of the oscillator is rectified and filtered for use as a slow negative feedback to the gate of Q1 to keep the output amplitude constant. The response of this control loop is much slower than 2 kHz and, therefore, does not introduce significant distortion of the oscillator output, which is a fairly clean sine wave. The positive AC feedback needed to sustain oscillations is derived from sampling the current through the
International Nuclear Information System (INIS)
Li, X. Allen; Stepaniak, Christopher; Gore, Elizabeth
2006-01-01
This work introduces a gating technique that uses 4DCT to determine gating parameters and to plan gated treatment, and employs a Siemens linear accelerator to deliver the gated treatment. Because of technology incompatibility, the 4DCT scanner (LightSpeed, GE) and the Siemens accelerator require two different motion-monitoring systems. The motion monitoring system (AZ-773V, Anzai Med.) used for the gated delivery utilizes a pressure sensor to detect the external respiratory motion (pressure change) in real time. Another system (RPM, Varian) used for the 4DCT scanner (LightSpeed, GE) is based on an infrared camera to detect motion of external markers. These two motion monitoring systems (RPM and Anzai systems) were found to correlate well with each other. The depth doses and profile measured for gated delivery (with a duty cycle of 25% or 50%) were found to agree within 1.0% with those measured for ungated delivery, indicating that gating did not significantly alter beam characteristics. The measurement verified also that the MU linearity and beam output remained unchanged (within 0.3%). A practical method of using 4DCT to plan a gated treatment was developed. The duty cycle for either phase or amplitude gating can be determined based on 4DCT with consideration of set-up error and delivery efficiency. The close-loop measurement involving the entire gating process (imaging, planning, and delivery) showed that the measured isodose distributions agreed with those intended, validating the accuracy and reliability of the gating technique. Based these observations, we conclude that the gating technique introduced in this work, integrating Siemens linear accelerator and Anzai pressure sensor device with GE/Varian RPM 4DCT, is reliable and effective, and it can be used clinically to account for respiratory motion during radiation therapy
Directory of Open Access Journals (Sweden)
Jason eMarmon
2016-03-01
Full Text Available Modern electronics are developing electronic-optical integrated circuits, while their electronic backbone, e.g. field-effect transistors (FETs, remains the same. However, further FET down scaling is facing physical and technical challenges. A light-effect transistor (LET offers electronic-optical hybridization at the component level, which can continue Moore’s law to quantum region without requiring a FET’s fabrication complexity, e.g. physical gate and doping, by employing optical gating and photoconductivity. Multiple independent gates are therefore readily realized to achieve unique functionalities without increasing chip space. Here we report LET device characteristics and novel digital and analog applications, such as optical logic gates and optical amplification. Prototype CdSe-nanowire-based LETs show output and transfer characteristics resembling advanced FETs, e.g. on/off ratios up to ~1.0x106 with a source-drain voltage of ~1.43 V, gate-power of ~260 nW, and subthreshold swing of ~0.3 nW/decade (excluding losses. Our work offers new electronic-optical integration strategies and electronic and optical computing approaches.
Corticolimbic gating of emotion-driven punishment.
Treadway, Michael T; Buckholtz, Joshua W; Martin, Justin W; Jan, Katharine; Asplund, Christopher L; Ginther, Matthew R; Jones, Owen D; Marois, René
2014-09-01
Determining the appropriate punishment for a norm violation requires consideration of both the perpetrator's state of mind (for example, purposeful or blameless) and the strong emotions elicited by the harm caused by their actions. It has been hypothesized that such affective responses serve as a heuristic that determines appropriate punishment. However, an actor's mental state often trumps the effect of emotions, as unintended harms may go unpunished, regardless of their magnitude. Using fMRI, we found that emotionally graphic descriptions of harmful acts amplify punishment severity, boost amygdala activity and strengthen amygdala connectivity with lateral prefrontal regions involved in punishment decision-making. However, this was only observed when the actor's harm was intentional; when harm was unintended, a temporoparietal-medial-prefrontal circuit suppressed amygdala activity and the effect of graphic descriptions on punishment was abolished. These results reveal the brain mechanisms by which evaluation of a transgressor's mental state gates our emotional urges to punish.
Digital systems from logic gates to processors
Deschamps, Jean-Pierre; Terés, Lluís
2017-01-01
This textbook for a one-semester course in Digital Systems Design describes the basic methods used to develop “traditional” Digital Systems, based on the use of logic gates and flip flops, as well as more advanced techniques that enable the design of very large circuits, based on Hardware Description Languages and Synthesis tools. It was originally designed to accompany a MOOC (Massive Open Online Course) created at the Autonomous University of Barcelona (UAB), currently available on the Coursera platform. Readers will learn what a digital system is and how it can be developed, preparing them for steps toward other technical disciplines, such as Computer Architecture, Robotics, Bionics, Avionics and others. In particular, students will learn to design digital systems of medium complexity, describe digital systems using high level hardware description languages, and understand the operation of computers at their most basic level. All concepts introduced are reinforced by plentiful illustrations, examples, ...
Chemical sensitivity of Mo gate Mos capacitors
Energy Technology Data Exchange (ETDEWEB)
Lombardi, R.M.; Aragon, R. [Laboratorio de Peliculas delgadas, Facultad de Ingenieria, Paseo Colon 850, 1063, Buenos Aires (Argentina)
2006-07-01
Mo gate Mos capacitors exhibit a negative shift of their C-V characteristic by up to 240 mV, at 125 C, in response to 1000 ppm hydrogen, in controlled nitrogen atmospheres. The experimental methods for obtaining capacitance and conductance, as a function of polarisation voltage, as well as the relevant equivalent circuits are reviewed. The single-state interface state density, at the semiconductor-dielectric interface, decreases from 2.66 x 10{sup 11} cm{sup -2} e-v{sup -1}, in pure nitrogen, to 2.5 x 10{sup 11} cm{sup -2} e-v{sup -1} in 1000 ppm hydrogen in nitrogen mixtures, at this temperature. (Author)
DMILL circuits. The hardened electronics decuples its performances
International Nuclear Information System (INIS)
Anon.
1998-01-01
Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)
VLSI scaling methods and low power CMOS buffer circuit
International Nuclear Information System (INIS)
Sharma Vijay Kumar; Pattanaik Manisha
2013-01-01
Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)
Error Mitigation for Short-Depth Quantum Circuits
Temme, Kristan; Bravyi, Sergey; Gambetta, Jay M.
2017-11-01
Two schemes are presented that mitigate the effect of errors and decoherence in short-depth quantum circuits. The size of the circuits for which these techniques can be applied is limited by the rate at which the errors in the computation are introduced. Near-term applications of early quantum devices, such as quantum simulations, rely on accurate estimates of expectation values to become relevant. Decoherence and gate errors lead to wrong estimates of the expectation values of observables used to evaluate the noisy circuit. The two schemes we discuss are deliberately simple and do not require additional qubit resources, so to be as practically relevant in current experiments as possible. The first method, extrapolation to the zero noise limit, subsequently cancels powers of the noise perturbations by an application of Richardson's deferred approach to the limit. The second method cancels errors by resampling randomized circuits according to a quasiprobability distribution.
DEFF Research Database (Denmark)
Nguyen-Duy, Khiem; Petersen, Lars Press; Knott, Arnold
2014-01-01
This paper presents the design of a 300-Watt isolated power supply for MOS gate driver circuit in medium and high voltage applications. The key feature of the developed power supply is having a very low circuit input-to-output parasitic capacitance, thus maximizing its noise immunity. This makes...
Sabah, Nassir H
2007-01-01
Circuit Variables and Elements Overview Learning Objectives Electric Current Voltage Electric Power and Energy Assigned Positive Directions Active and Passive Circuit Elements Voltage and Current Sources The Resistor The Capacitor The Inductor Concluding Remarks Summary of Main Concepts and Results Learning Outcomes Supplementary Topics on CD Problems and Exercises Basic Circuit Connections and Laws Overview Learning Objectives Circuit Terminology Kirchhoff's Laws Voltage Division and Series Connection of Resistors Current Division and Parallel Connection of Resistors D-Y Transformation Source Equivalence and Transformation Reduced-Voltage Supply Summary of Main Concepts and Results Learning Outcomes Supplementary Topics and Examples on CD Problems and Exercises Basic Analysis of Resistive Circuits Overview Learning Objectives Number of Independent Circuit Equations Node-Voltage Analysis Special Considerations in Node-Voltage Analysis Mesh-Current Analysis Special Conside...
Rangel-Abundis, Alberto
2006-01-01
Shunt and short circuit are antonyms. In French, the term shunt has been adopted to denote the alternative pathway of blood flow. However, in French, as well as in Spanish, the word short circuit (court-circuit and cortocircuito) is synonymous with shunt, giving rise to a linguistic and scientific inconsistency. Scientific because shunt and short circuit made reference to a phenomenon that occurs in the field of the physics. Because shunt and short circuit are antonyms, it is necessary to clarify that shunt is an alternative pathway of flow from a net of high resistance to a net of low resistance, maintaining the stream. Short circuit is the interruption of the flow, because a high resistance impeaches the flood. This concept is applied to electrical and cardiovascular physiology, as well as to the metabolic pathways.
Prusinski, Ben; Chung, Richard
2011-01-01
Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica
Analog storage integrated circuit
Walker, J.T.; Larsen, R.S.; Shapiro, S.L.
1989-03-07
A high speed data storage array is defined utilizing a unique cell design for high speed sampling of a rapidly changing signal. Each cell of the array includes two input gates between the signal input and a storage capacitor. The gates are controlled by a high speed row clock and low speed column clock so that the instantaneous analog value of the signal is only sampled and stored by each cell on coincidence of the two clocks. 6 figs.
TOFPET 2: A high-performance circuit for PET time-of-flight
Energy Technology Data Exchange (ETDEWEB)
Di Francesco, Agostino, E-mail: agodifra@lip.pt [LIP, Lisbon (Portugal); Bugalho, Ricardo [LIP, Lisbon (Portugal); PETsys Electronics, Oeiras (Portugal); Oliveira, Luis [CTS-UNINOVA, DEE FCT-UNL, Caparica (Portugal); Rivetti, Angelo [INFN - sez. Torino (Italy); Rolo, Manuel [LIP, Lisbon (Portugal); INFN - sez. Torino (Italy); Silva, Jose C.; Varela, Joao [LIP, Lisbon (Portugal); PETsys Electronics, Oeiras (Portugal)
2016-07-11
We present a readout and digitization ASIC featuring low-noise and low-power for time-of flight (TOF) applications using SiPMs. The circuit is designed in standard CMOS 110 nm technology, has 64 independent channels and is optimized for time-of-flight measurement in Positron Emission Tomography (TOF-PET). The input amplifier is a low impedance current conveyor based on a regulated common-gate topology. Each channel has quad-buffered analogue interpolation TDCs (time binning 20 ps) and charge integration ADCs with linear response at full scale (1500 pC). The signal amplitude can also be derived from the measurement of time-over-threshold (ToT). Simulation results show that for a single photo-electron signal with charge 200 (550) fC generated by a SiPM with (320 pF) capacitance the circuit has 24 (30) dB SNR, 75 (39) ps r.m.s. resolution, and 4 (8) mW power consumption. The event rate is 600 kHz per channel, with up to 2 MHz dark counts rejection.
Dobkin, Bob
2012-01-01
Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <
Regenerative feedback resonant circuit
Jones, A. Mark; Kelly, James F.; McCloy, John S.; McMakin, Douglas L.
2014-09-02
A regenerative feedback resonant circuit for measuring a transient response in a loop is disclosed. The circuit includes an amplifier for generating a signal in the loop. The circuit further includes a resonator having a resonant cavity and a material located within the cavity. The signal sent into the resonator produces a resonant frequency. A variation of the resonant frequency due to perturbations in electromagnetic properties of the material is measured.
The Circuit Ideal of a Vector Configuration
DEFF Research Database (Denmark)
Jensen, Anders Nedergaard; Bogart, Tristram; Thomas, Rekha
$, of $\\A$ which has numerous applications and is nontrivial to compute. Since circuits can be computed using linear algebra and the two ideals often coincide, it is worthwhile to understand when equality occurs. In this paper we study $\\ica$ in relation to $\\ia$ from various algebraic and combinatorial...
State-Space Formulation for Circuit Analysis
Martinez-Marin, T.
2010-01-01
This paper presents a new state-space approach for temporal analysis of electrical circuits. The method systematically obtains the state-space formulation of nondegenerate linear networks without using concepts of topology. It employs nodal/mesh systematic analysis to reduce the number of undesired variables. This approach helps students to…
Monolitic integrated circuit for the strobed charge-to-time converter
International Nuclear Information System (INIS)
Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.
1985-01-01
The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC
Timergenerator circuits manual
Marston, R M
2013-01-01
Timer/Generator Circuits Manual is an 11-chapter text that deals mainly with waveform generator techniques and circuits. Each chapter starts with an explanation of the basic principles of its subject followed by a wide range of practical circuit designs. This work presents a total of over 300 practical circuits, diagrams, and tables.Chapter 1 outlines the basic principles and the different types of generator. Chapters 2 to 9 deal with a specific type of waveform generator, including sine, square, triangular, sawtooth, and special waveform generators pulse. These chapters also include pulse gen
Electronic devices and circuits
Pridham, Gordon John
1968-01-01
Electronic Devices and Circuits, Volume 1 deals with the design and applications of electronic devices and circuits such as passive components, diodes, triodes and transistors, rectification and power supplies, amplifying circuits, electronic instruments, and oscillators. These topics are supported with introductory network theory and physics. This volume is comprised of nine chapters and begins by explaining the operation of resistive, inductive, and capacitive elements in direct and alternating current circuits. The theory for some of the expressions quoted in later chapters is presented. Th
Maximum Acceleration Recording Circuit
Bozeman, Richard J., Jr.
1995-01-01
Coarsely digitized maximum levels recorded in blown fuses. Circuit feeds power to accelerometer and makes nonvolatile record of maximum level to which output of accelerometer rises during measurement interval. In comparison with inertia-type single-preset-trip-point mechanical maximum-acceleration-recording devices, circuit weighs less, occupies less space, and records accelerations within narrower bands of uncertainty. In comparison with prior electronic data-acquisition systems designed for same purpose, circuit simpler, less bulky, consumes less power, costs and analysis of data recorded in magnetic or electronic memory devices. Circuit used, for example, to record accelerations to which commodities subjected during transportation on trucks.
Wolfendale, E
2013-01-01
MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi
Chen, Wai-Kai
2003-01-01
A bestseller in its first edition, The Circuits and Filters Handbook has been thoroughly updated to provide the most current, most comprehensive information available in both the classical and emerging fields of circuits and filters, both analog and digital. This edition contains 29 new chapters, with significant additions in the areas of computer-aided design, circuit simulation, VLSI circuits, design automation, and active and digital filters. It will undoubtedly take its place as the engineer's first choice in looking for solutions to problems encountered in the design, analysis, and behavi
Security electronics circuits manual
MARSTON, R M
1998-01-01
Security Electronics Circuits Manual is an invaluable guide for engineers and technicians in the security industry. It will also prove to be a useful guide for students and experimenters, as well as providing experienced amateurs and DIY enthusiasts with numerous ideas to protect their homes, businesses and properties.As with all Ray Marston's Circuits Manuals, the style is easy-to-read and non-mathematical, with the emphasis firmly on practical applications, circuits and design ideas. The ICs and other devices used in the practical circuits are modestly priced and readily available ty
A novel optical gating method for laser gated imaging
Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer
2013-06-01
For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.
Energy efficient circuit design using nanoelectromechanical relays
Venkatasubramanian, Ramakrishnan
Nano-electromechanical (NEM) relays are a promising class of emerging devices that offer zero off-state leakage and behave like an ideal switch. Recent advances in planar fabrication technology have demonstrated that microelectromechanical (MEMS) scale miniature relays could be manufactured reliably and could be used to build fully functional, complex integrated circuits. The zero leakage operation of relays has renewed the interest in relay based low power logic design. This dissertation explores circuit architectures using NEM relays and NEMS-CMOS heterogeneous integration. Novel circuit topologies for sequential logic, memory, and power management circuits have been proposed taking into consideration the NEM relay device properties and optimizing for energy efficiency and area. In nanoscale electromechanical devices, dispersion forces like Van der Waals' force (vdW) affect the pull-in stability of the relay devices significantly. Verilog-A electromechanical model of the suspended gate relay operating at 1V with a nominal air gap of 5 - 10nm has been developed taking into account all the electrical, mechanical and dispersion effects. This dissertation explores different relay based latch and flip-flop topologies. It has been shown that as few as 4 relay cells could be used to build flip-flops. An integrated voltage doubler based flip flop that improves the performance by 2X by overdriving Vgb has been proposed. Three NEM relay based parallel readout memory bitcell architectures have been proposed that have faster access time, and remove the reliability issues associated with previously reported serial readout architectures. A paradigm shift in design of power switches using NEM relays is proposed. An interesting property of the relay device is that the ON state resistance (Ron) of the NEM relay switch is constant and is insensitive to the gate slew rate. This coupled with infinite OFF state resistance (Roff ) offers significant area and power advantages over CMOS
Generic two-qubit photonic gates implemented by number-resolving photodetection
International Nuclear Information System (INIS)
Uskov, Dmitry B.; Smith, A. Matthew; Kaplan, Lev
2010-01-01
We combine numerical optimization techniques [Uskov et al., Phys. Rev. A 79, 042326 (2009)] with symmetries of the Weyl chamber to obtain optimal implementations of generic linear-optical Knill-Laflamme-Milburn-type two-qubit entangling gates. We find that while any two-qubit controlled-U gate, including controlled-NOT (CNOT) and controlled-sign gates, can be implemented using only two ancilla resources with a success probability S>0.05, a generic SU(4) operation requires three unentangled ancilla photons, with success S>0.0063. Specifically, we obtain a maximal success probability close to 0.0072 for the B gate. We show that single-shot implementation of a generic SU(4) gate offers more than an order of magnitude increase in the success probability and a two-fold reduction in overhead ancilla resources compared to standard triple-CNOT and double-B gate decompositions.
Programmable delay unit incorporating a semi-custom integrated circuit
International Nuclear Information System (INIS)
Linstadt, E.
1985-04-01
The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given
Single-server blind quantum computation with quantum circuit model
Zhang, Xiaoqian; Weng, Jian; Li, Xiaochun; Luo, Weiqi; Tan, Xiaoqing; Song, Tingting
2018-06-01
Blind quantum computation (BQC) enables the client, who has few quantum technologies, to delegate her quantum computation to a server, who has strong quantum computabilities and learns nothing about the client's quantum inputs, outputs and algorithms. In this article, we propose a single-server BQC protocol with quantum circuit model by replacing any quantum gate with the combination of rotation operators. The trap quantum circuits are introduced, together with the combination of rotation operators, such that the server is unknown about quantum algorithms. The client only needs to perform operations X and Z, while the server honestly performs rotation operators.
Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.
Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R
2015-10-14
We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.
Improving the Short-Circuit Reliability in IGBTs
DEFF Research Database (Denmark)
Reigosa, Paula Diaz; Iannuzzo, Francesco; Rahimo, Munaf
2018-01-01
takes place during the IGBT short-circuit, whose time-varying element is the Miller capacitance, which is involved in the amplification mechanism. This hypothesis has been validated through simulations and its mitigation is possible by increasing the electric field at the emitter of the IGBT......In this paper, the oscillation mechanism limiting the ruggedness of IGBTs is investigated through both circuit and device analysis. The work presented here is based on a time-domain approach for two different IGBT cell structures (i.e., trench-gate and planar), illustrating the 2-D effects during...
Diagnosis of constant faults in iteration-free circuits over monotone basis
Alrawaf, Saad Abdullah; Chikalov, Igor; Hussain, Shahid; Moshkov, Mikhail
2014-01-01
We show that for each iteration-free combinatorial circuit S over a basis B containing only monotone Boolean functions with at most five variables, there exists a decision tree for diagnosis of constant faults on inputs of gates with depth at most 7L(S) where L(S) is the number of gates in S. © 2013 Elsevier B.V. All rights reserved.
Diagnosis of constant faults in iteration-free circuits over monotone basis
Alrawaf, Saad Abdullah
2014-03-01
We show that for each iteration-free combinatorial circuit S over a basis B containing only monotone Boolean functions with at most five variables, there exists a decision tree for diagnosis of constant faults on inputs of gates with depth at most 7L(S) where L(S) is the number of gates in S. © 2013 Elsevier B.V. All rights reserved.
Equivalent circuit simulation of HPEM-induced transient responses at nonlinear loads
Directory of Open Access Journals (Sweden)
M. Kotzev
2017-09-01
Full Text Available In this paper the equivalent circuit modeling of a nonlinearly loaded loop antenna and its transient responses to HPEM field excitations are investigated. For the circuit modeling the general strategy to characterize the nonlinearly loaded antenna by a linear and a nonlinear circuit part is pursued. The linear circuit part can be determined by standard methods of antenna theory and numerical field computation. The modeling of the nonlinear circuit part requires realistic circuit models of the nonlinear loads that are given by Schottky diodes. Combining both parts, appropriate circuit models are obtained and analyzed by means of a standard SPICE circuit simulator. It is the main result that in this way full-wave simulation results can be reproduced. Furthermore it is clearly seen that the equivalent circuit modeling offers considerable advantages with respect to computation speed and also leads to improved physical insights regarding the coupling between HPEM field excitation and nonlinearly loaded loop antenna.
High energy X-ray photon counting imaging using linear accelerator and silicon strip detectors
Energy Technology Data Exchange (ETDEWEB)
Tian, Y., E-mail: cycjty@sophie.q.t.u-tokyo.ac.jp [Department of Bioengineering, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Shimazoe, K.; Yan, X. [Department of Nuclear Engineering and Management, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Ueda, O.; Ishikura, T. [Fuji Electric Co., Ltd., Fuji, Hino, Tokyo 191-8502 (Japan); Fujiwara, T. [National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568 (Japan); Uesaka, M.; Ohno, M. [Nuclear Professional School, the University of Tokyo, 2-22 Shirakata-shirane, Tokai, Ibaraki 319-1188 (Japan); Tomita, H. [Department of Quantum Engineering, Nagoya University, Furo, Chikusa, Nagoya 464-8603 (Japan); Yoshihara, Y. [Department of Nuclear Engineering and Management, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Takahashi, H. [Department of Bioengineering, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan); Department of Nuclear Engineering and Management, the University of Tokyo, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-8656 (Japan)
2016-09-11
A photon counting imaging detector system for high energy X-rays is developed for on-site non-destructive testing of thick objects. One-dimensional silicon strip (1 mm pitch) detectors are stacked to form a two-dimensional edge-on module. Each detector is connected to a 48-channel application specific integrated circuit (ASIC). The threshold-triggered events are recorded by a field programmable gate array based counter in each channel. The detector prototype is tested using 950 kV linear accelerator X-rays. The fast CR shaper (300 ns pulse width) of the ASIC makes it possible to deal with the high instant count rate during the 2 μs beam pulse. The preliminary imaging results of several metal and concrete samples are demonstrated.
High energy X-ray photon counting imaging using linear accelerator and silicon strip detectors
International Nuclear Information System (INIS)
Tian, Y.; Shimazoe, K.; Yan, X.; Ueda, O.; Ishikura, T.; Fujiwara, T.; Uesaka, M.; Ohno, M.; Tomita, H.; Yoshihara, Y.; Takahashi, H.
2016-01-01
A photon counting imaging detector system for high energy X-rays is developed for on-site non-destructive testing of thick objects. One-dimensional silicon strip (1 mm pitch) detectors are stacked to form a two-dimensional edge-on module. Each detector is connected to a 48-channel application specific integrated circuit (ASIC). The threshold-triggered events are recorded by a field programmable gate array based counter in each channel. The detector prototype is tested using 950 kV linear accelerator X-rays. The fast CR shaper (300 ns pulse width) of the ASIC makes it possible to deal with the high instant count rate during the 2 μs beam pulse. The preliminary imaging results of several metal and concrete samples are demonstrated.
Entangling distant resonant exchange qubits via circuit quantum electrodynamics
Srinivasa, V.; Taylor, J. M.; Tahan, Charles
2016-11-01
We investigate a hybrid quantum system consisting of spatially separated resonant exchange qubits, defined in three-electron semiconductor triple quantum dots, that are coupled via a superconducting transmission line resonator. Drawing on methods from circuit quantum electrodynamics and Hartmann-Hahn double resonance techniques, we analyze three specific approaches for implementing resonator-mediated two-qubit entangling gates in both dispersive and resonant regimes of interaction. We calculate entangling gate fidelities as well as the rate of relaxation via phonons for resonant exchange qubits in silicon triple dots and show that such an implementation is particularly well suited to achieving the strong coupling regime. Our approach combines the favorable coherence properties of encoded spin qubits in silicon with the rapid and robust long-range entanglement provided by circuit QED systems.
Deutsch, Toffoli, and cnot Gates via Rydberg Blockade of Neutral Atoms
Shi, Xiao-Feng
2018-05-01
Universal quantum gates and quantum error correction (QEC) lie at the heart of quantum-information science. Large-scale quantum computing depends on a universal set of quantum gates, in which some gates may be easily carried out, while others are restricted to certain physical systems. There is a unique three-qubit quantum gate called the Deutsch gate [D (θ )], from which a circuit can be constructed so that any feasible quantum computing is attainable. We design an easily realizable D (θ ) by using the Rydberg blockade of neutral atoms, where θ can be tuned to any value in [0 ,π ] by adjusting the strengths of external control fields. Using similar protocols, we further show that both the Toffoli and controlled-not gates can be achieved with only three laser pulses. The Toffoli gate, being universal for classical reversible computing, is also useful for QEC, which plays an important role in quantum communication and fault-tolerant quantum computation. The possibility and speed of realizing these gates shed light on the study of quantum information with neutral atoms.
Energy Technology Data Exchange (ETDEWEB)
Anstrom, Joel
2012-08-31
The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.
Piezoconductivity of gated suspended graphene
Medvedyeva, M.V.; Blanter, Y.M.
2011-01-01
We investigate the conductivity of graphene sheet deformed over a gate. The effect of the deformation on the conductivity is twofold: The lattice distortion can be represented as pseudovector potential in the Dirac equation formalism, whereas the gate causes inhomogeneous density redistribution. We
MO-FG-BRA-03: A Novel Method for Characterizing Gating Response Time in Radiation Therapy
Energy Technology Data Exchange (ETDEWEB)
Wiersma, R; McCabe, B; Belcher, A; Jenson, P [The University of Chicago, Chicago, IL (United States); Smith, B [University Illinois at Chicago, Orland Park, IL (United States); Aydogan, B [The University of Chicago, Chicago, IL (United States); University Illinois at Chicago, Orland Park, IL (United States)
2016-06-15
Purpose: Low temporal latency between a gating ON/OFF signal and the LINAC beam ON/OFF during respiratory gating is critical for patient safety. Current film based methods to assess gating response have poor temporal resolution and are highly qualitative. We describe a novel method to precisely measure gating lag times at high temporal resolutions and use it to characterize the temporal response of several gating systems. Methods: A respiratory gating simulator with an oscillating platform was modified to include a linear potentiometer for position measurement. A photon diode was placed at linear accelerator isocenter for beam output measurement. The output signals of the potentiometer and diode were recorded simultaneously at 2500 Hz (0.4 millisecond (ms) sampling interval) with an analogue-to-digital converter (ADC). The techniques was used on three commercial respiratory gating systems. The ON and OFF of the beam signal were located and compared to the expected gating window for both phase and position based gating and the temporal lag times extracted using a polynomial fit method. Results: A Varian RPM system with a monoscopic IR camera was measured to have mean beam ON and OFF lag times of 98.2 ms and 89.6 ms, respectively. A Varian RPM system with a stereoscopic IR camera was measured to have mean beam ON and OFF lag times of 86.0 ms and 44.0 ms, respectively. A Calypso magnetic fiducial tracking system was measured to have mean beam ON and OFF lag times of 209.0 ms and 60.0 ms, respectively. Conclusions: A novel method allowed for quantitative determination of gating timing accuracy for several clinically used gating systems. All gating systems met the 100 ms TG-142 criteria for mean beam OFF times. For beam ON response, the Calypso system exceeded the recommended response time.
Edmonds, L. D.
2016-01-01
Since advancing technology has been producing smaller structures in electronic circuits, the floating gates in modern flash memories are becoming susceptible to prompt charge loss from ionizing radiation environments found in space. A method for estimating the risk of a charge-loss event is given.
DEFF Research Database (Denmark)
Hansen, Kristoffer Arnsfelt; Miltersen, Peter Bro; Vinay, V
2006-01-01
We consider the computational power of constant width polynomial size cylindrical circuits and nondeterministic branching programs. We show that every function computed by a Pi2 o MOD o AC0 circuit can also be computed by a constant width polynomial size cylindrical nondeterministic branching pro...
A reliable ground bounce noise reduction technique for nanoscale CMOS circuits
Sharma, Vijay Kumar; Pattanaik, Manisha
2015-11-01
Power gating is the most effective method to reduce the standby leakage power by adding header/footer high-VTH sleep transistors between actual and virtual power/ground rails. When a power gating circuit transitions from sleep mode to active mode, a large instantaneous charge current flows through the sleep transistors. Ground bounce noise (GBN) is the high voltage fluctuation on real ground rail during sleep mode to active mode transitions of power gating circuits. GBN disturbs the logic states of internal nodes of circuits. A novel and reliable power gating structure is proposed in this article to reduce the problem of GBN. The proposed structure contains low-VTH transistors in place of high-VTH footer. The proposed power gating structure not only reduces the GBN but also improves other performance metrics. A large mitigation of leakage power in both modes eliminates the need of high-VTH transistors. A comprehensive and comparative evaluation of proposed technique is presented in this article for a chain of 5-CMOS inverters. The simulation results are compared to other well-known GBN reduction circuit techniques at 22 nm predictive technology model (PTM) bulk CMOS model using HSPICE tool. Robustness against process, voltage and temperature (PVT) variations is estimated through Monte-Carlo simulations.
A refractory metal gate approach for micronic CMOS technology
International Nuclear Information System (INIS)
Lubowiecki, V.; Ledys, J.L.; Plossu, C.; Balland, B.
1987-01-01
In the future, devices scaling down, integration density and performance improvements are going to bring a number of conventional circuit design and process techniques to their fundamental limits. To avoid any severe limitations in MOS ULSI (Ultra Large Scale Integration) technologies, interconnection materials and schemes are required to emerge, in order to face the Megabits memory field. Among those, the gate approach will obviously take a keyrole, when the operating speed of ULSI chips will reach the practical upper limits imposed by parasitic resistances and capacitances which stem from the circuit interconnect wiring. Even if fairly suitable for MOS process, doped polycrystalline silicon is being gradually replaced by refractory metal silicide or polycide structures, which match better with low resistivity requirements. However, as we approach the submicronic IC's, higher conductivity materials will be paid more and more attention. Recently, works have been devoted and published on refractory metal gate technologies. Molybdenum or tungsten, deposited either by CVD or PVD methods, are currently reported even if some drawbacks in their process integration still remain. This paper is willing to present such an approach based on tungsten (more reliable than Molybdenum deposited by LPCVD (giving more conductive and more stable films than PVD). Deposition process will be first described. Then CMOS process flow will allow us to focus on specific refractory metal gate issues. Finally, electrical and physical properties will be assessed, which will demonstrate the feasibility of such a technology as well as the compatibility of the tungsten with most of the usual techniques
GATE: Improving the computational efficiency
International Nuclear Information System (INIS)
Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.
2006-01-01
GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable
Allen, Phillip E
1987-01-01
This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.
Alternative Approach of Developing Optical Binary Adder Using Reversible Peres Gates
Directory of Open Access Journals (Sweden)
Dhoumendra Mandal
2018-01-01
Full Text Available All-optical devices will play a very significant and crucial role in the modern all-optical network by eliminating the bottleneck of opto-electro-opto- (O-E-O- conversion. Unfortunately, the conventional logic gates lose information at the output, and the states of the outputs cannot give any credible impressions of the states of the inputs. In this article, at first, the authors have proposed a method of designing an optical three-input-three-output reversible Peres gate. Authors have deployed polarization switching characteristic of Semiconductor Optical Amplifier (SOA for designing this circuit. The authors have also proposed a method of designing an optical reversible full adder, using two such Peres gates and subsequently a data recovery circuit which can recover the input data of the adder. The authors have chosen frequency encoded data for processing the operation. The proposed scheme has been verified by simulation results.
Design Principles of A Sigma-delta Flux-gate Magnetometer
Magnes, W.; Valavanoglou, A.; Pierce, D.; Frank, A.; Schwingenschuh, K.
A state-of-the-art flux-gate magnetometer is characterised by magnetic field resolution of several pT in a wide frequency range, low power consumption, low weight and high robustness. Therefore, flux-gate magnetometers are frequently used for ground-based Earth's field observation as well as for measurements aboard scientific space missions. But both traditional analogue and recently developed digital flux-gate magnetometers need low power and high-resolution analogue-to-digital converters for signal quan- tization. The disadvantage of such converters is the low radiation hardness. This fact has led to the idea of combining a traditional analogue flux-gate regulation circuit with that of a discretely realized sigma-delta converter in order to get a radiation hard and further miniaturized magnetometer. The name sigma-delta converter is derived from putting an integrator in front of a 1-bit delta modulator which forms the sigma-delta loop. It is followed by a digital decimation filter realized in a field-programmable gate array (FPGA). The flux-gate regulation and the sigma-delta loop are quite similar in the way of realizing the integrator and feedback circuit, which makes it easy to com- bine these two systems. The presented talk deals with the design principles and the results of a first bread board model.
The memory effect of a pentacene field-effect transistor with a polarizable gate dielectric
Unni, K. N. N.; de Bettignies, Remi; Dabos-Seignon, Sylvie; Nunzi, Jean-Michel
2004-06-01
The nonvolatile transistor memory element is an interesting topic in organic electronics. In this case a memory cell consists of only one device where the stored information is written as a gate insulator polarization by a gate voltage pulse and read by the channel conductance control with channel voltage pulse without destruction of the stored information. Therefore such transistor could be the base of non-volatile non-destructively readable computer memory of extremely high density. Also devices with polarizable gate dielectrics can function more effectively in certain circuits. The effective threshold voltage Vt can be brought very close to zero, for applications where the available gate voltage is limited. Resonant and adaptive circuits can be tuned insitu by polarizing the gates. Poly(vinylidene fluoride), PVDF and its copolymer with trifluoroethylene P(VDF-TrFE) are among the best known and most widely used ferroelectric polymers. In this manuscript, we report new results of an organic FET, fabricated with pentacene as the active material and P(VDF-TrFE) as the gate insulator. Application of a writing voltage of -50 V for short duration results in significant change in the threshold voltage and remarkable increase in the drain current. The memory effect is retained over a period of 20 hours.
Hybrid integrated circuit for charge-to-time interval conversion
Energy Technology Data Exchange (ETDEWEB)
Basiladze, S.G.; Dotsenko, Yu.Yu.; Man' yakov, P.K.; Fedorchenko, S.N. (Joint Inst. for Nuclear Research, Dubna (USSR))
The hybrid integrated circuit for charge-to time interval conversion with nanosecond input fast response is described. The circuit can be used in energy measuring channels, time-to-digital converters and in the modified variant in amplitude-to-digital converters. The converter described consists of a buffer amplifier, a linear transmission circuit, a direct current source and a unit of time interval separation. The buffer amplifier represents a current follower providing low input and high output resistances by the current feedback. It is concluded that the described converter excelled the QT100B circuit analogous to it in a number of parameters especially, in thermostability.
Ultrafast quantum computation in ultrastrongly coupled circuit QED systems
Wang, Yimin; Guo, Chu; Zhang, Guo-Qiang; Wang, Gangcheng; Wu, Chunfeng
2017-01-01
The latest technological progress of achieving the ultrastrong-coupling regime in circuit quantum electrodynamics (QED) systems has greatly promoted the developments of quantum physics, where novel quantum optics phenomena and potential computational benefits have been predicted. Here, we propose a scheme to accelerate the nontrivial two-qubit phase gate in a circuit QED system, where superconducting flux qubits are ultrastrongly coupled to a transmission line resonator (TLR), and two more TLRs are coupled to the ultrastrongly-coupled system for assistant. The nontrivial unconventional geometric phase gate between the two flux qubits is achieved based on close-loop displacements of the three-mode intracavity fields. Moreover, as there are three resonators contributing to the phase accumulation, the requirement of the coupling strength to realize the two-qubit gate can be reduced. Further reduction in the coupling strength to achieve a specific controlled-phase gate can be realized by adding more auxiliary resonators to the ultrastrongly-coupled system through superconducting quantum interference devices. We also present a study of our scheme with realistic parameters considering imperfect controls and noisy environment. Our scheme possesses the merits of ultrafastness and noise-tolerance due to the advantages of geometric phases. PMID:28281654
International Nuclear Information System (INIS)
Fujiwara, Shingo; Hasegawa, Shuichi
2005-01-01
It is well known that, in order to build the universal quantum circuit, one only needs one-qubit rotation gate and two-qubit controlled-NOT gate and until now quantum networks have been built from these gates. However, the minimum components of quantum networks in real experiments are not these quantum gates, so we develop a general method for realizing the conditional phase-shift gate in multiqubit ion-trap quantum computation which has the scalability to N qubits (N≥3). The duration of the laser manipulations for the proposed conditional phase-shift gate is almost the same as that for the controlled-NOT gate in ion-trap quantum computation. Moreover, we simulate Grover's algorithm taking into consideration the real laser fluctuations and analyze the effect of decoherence on the practical search
Block QCA Fault-Tolerant Logic Gates
Firjany, Amir; Toomarian, Nikzad; Modarres, Katayoon
2003-01-01
Suitably patterned arrays (blocks) of quantum-dot cellular automata (QCA) have been proposed as fault-tolerant universal logic gates. These block QCA gates could be used to realize the potential of QCA for further miniaturization, reduction of power consumption, increase in switching speed, and increased degree of integration of very-large-scale integrated (VLSI) electronic circuits. The limitations of conventional VLSI circuitry, the basic principle of operation of QCA, and the potential advantages of QCA-based VLSI circuitry were described in several NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35; and Hybrid VLSI/QCA Architecture for Computing FFTs (NPO-20923), which follows this article. To recapitulate the principle of operation (greatly oversimplified because of the limitation on space available for this article): A quantum-dot cellular automata contains four quantum dots positioned at or between the corners of a square cell. The cell contains two extra mobile electrons that can tunnel (in the quantummechanical sense) between neighboring dots within the cell. The Coulomb repulsion between the two electrons tends to make them occupy antipodal dots in the cell. For an isolated cell, there are two energetically equivalent arrangements (denoted polarization states) of the extra electrons. The cell polarization is used to encode binary information. Because the polarization of a nonisolated cell depends on Coulomb-repulsion interactions with neighboring cells, universal logic gates and binary wires could be constructed, in principle, by arraying QCA of suitable design in suitable patterns. Heretofore, researchers have recognized two major obstacles to realization of QCA
Nonlinear properties of gated graphene in a strong electromagnetic field
Energy Technology Data Exchange (ETDEWEB)
Avetisyan, A. A., E-mail: artakav@ysu.am; Djotyan, A. P., E-mail: adjotyan@ysu.am [Yerevan State University, Department of Physics (Armenia); Moulopoulos, K., E-mail: cos@ucy.ac.cy [University of Cyprus, Department of Physics (Cyprus)
2017-03-15
We develop a microscopic theory of a strong electromagnetic field interaction with gated bilayer graphene. Quantum kinetic equations for density matrix are obtained using a tight binding approach within second quantized Hamiltonian in an intense laser field. We show that adiabatically changing the gate potentials with time may produce (at resonant photon energy) a full inversion of the electron population with high density between valence and conduction bands. In the linear regime, excitonic absorption of an electromagnetic radiation in a graphene monolayer with opened energy gap is also studied.
On the dynamic analysis of piecewise-linear networks
Heemels, WPMH; Camlibel, MK; Schumacher, JM
Piecewise-linear (PL) modeling is often used to approximate the behavior of nonlinear circuits. One of the possible PL modeling methodologies is based on the linear complementarity problem, and this approach has already been used extensively in the circuits and systems community for static networks.
Gated equilibrium bloodpool scintigraphy
International Nuclear Information System (INIS)
Reinders Folmer, S.C.C.
1981-01-01
This thesis deals with the clinical applications of gated equilibrium bloodpool scintigraphy, performed with either a gamma camera or a portable detector system, the nuclear stethoscope. The main goal has been to define the value and limitations of noninvasive measurements of left ventricular ejection fraction as a parameter of cardiac performance in various disease states, both for diagnostic purposes as well as during follow-up after medical or surgical intervention. Secondly, it was attempted to extend the use of the equilibrium bloodpool techniques beyond the calculation of ejection fraction alone by considering the feasibility to determine ventricular volumes and by including the possibility of quantifying valvular regurgitation. In both cases, it has been tried to broaden the perspective of the observations by comparing them with results of other, invasive and non-invasive, procedures, in particular cardiac catheterization, M-mode echocardiography and myocardial perfusion scintigraphy. (Auth.)
Song, Chao; Zheng, Shi-Biao; Zhang, Pengfei; Xu, Kai; Zhang, Libo; Guo, Qiujiang; Liu, Wuxin; Xu, Da; Deng, Hui; Huang, Keqiang; Zheng, Dongning; Zhu, Xiaobo; Wang, H
2017-10-20
Geometric phase, associated with holonomy transformation in quantum state space, is an important quantum-mechanical effect. Besides fundamental interest, this effect has practical applications, among which geometric quantum computation is a paradigm, where quantum logic operations are realized through geometric phase manipulation that has some intrinsic noise-resilient advantages and may enable simplified implementation of multi-qubit gates compared to the dynamical approach. Here we report observation of a continuous-variable geometric phase and demonstrate a quantum gate protocol based on this phase in a superconducting circuit, where five qubits are controllably coupled to a resonator. Our geometric approach allows for one-step implementation of n-qubit controlled-phase gates, which represents a remarkable advantage compared to gate decomposition methods, where the number of required steps dramatically increases with n. Following this approach, we realize these gates with n up to 4, verifying the high efficiency of this geometric manipulation for quantum computation.
Jones, C.S.; Eaton, T.E.
1958-02-01
This patent relates to pulse generating circuits and more particularly to rectangular pulse generators. The pulse generator of the present invention incorporates thyratrons as switching elements to discharge a first capacitor through a load resistor to initiate and provide the body of a Pulse, and subsequently dlscharge a second capacitor to impress the potential of its charge, with opposite potential polarity across the load resistor to terminate the pulse. Accurate rectangular pulses in the millimicrosecond range are produced across a low impedance by this generator.
DEFF Research Database (Denmark)
Dalal, Dipen Narendrabhai; Christensen, Nicklas; Jørgensen, Asger Bjørn
2017-01-01
Miller clamp circuit for a 10 kV half bridge SiC MOSFET power module. Designed power supply and the gate driver circuit are verified in a double pulse test setup and a continuous switching operation using the 10 kV half bridge silicon carbide MOSFET power module. An in-depth experimental verification...
Approximate circuits for increased reliability
Hamlet, Jason R.; Mayo, Jackson R.
2015-08-18
Embodiments of the invention describe a Boolean circuit having a voter circuit and a plurality of approximate circuits each based, at least in part, on a reference circuit. The approximate circuits are each to generate one or more output signals based on values of received input signals. The voter circuit is to receive the one or more output signals generated by each of the approximate circuits, and is to output one or more signals corresponding to a majority value of the received signals. At least some of the approximate circuits are to generate an output value different than the reference circuit for one or more input signal values; however, for each possible input signal value, the majority values of the one or more output signals generated by the approximate circuits and received by the voter circuit correspond to output signal result values of the reference circuit.
Receiver Front-End Circuits for Future Generations of Wireless Communications
Sanduleanu, M.A.T.; Vidojkovic - Andjelovic, M.; Vidojkovic, V.; Roermund, van A.H.M.; Tasic, A.
2007-01-01
In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in
A Linear Electromagnetic Piston Pump
Hogan, Paul H.
Advancements in mobile hydraulics for human-scale applications have increased demand for a compact hydraulic power supply. Conventional designs couple a rotating electric motor to a hydraulic pump, which increases the package volume and requires several energy conversions. This thesis investigates the use of a free piston as the moving element in a linear motor to eliminate multiple energy conversions and decrease the overall package volume. A coupled model used a quasi-static magnetic equivalent circuit to calculate the motor inductance and the electromagnetic force acting on the piston. The force was an input to a time domain model to evaluate the mechanical and pressure dynamics. The magnetic circuit model was validated with finite element analysis and an experimental prototype linear motor. The coupled model was optimized using a multi-objective genetic algorithm to explore the parameter space and maximize power density and efficiency. An experimental prototype linear pump coupled pistons to an off-the-shelf linear motor to validate the mechanical and pressure dynamics models. The magnetic circuit force calculation agreed within 3% of finite element analysis, and within 8% of experimental data from the unoptimized prototype linear motor. The optimized motor geometry also had good agreement with FEA; at zero piston displacement, the magnetic circuit calculates optimized motor force within 10% of FEA in less than 1/1000 the computational time. This makes it well suited to genetic optimization algorithms. The mechanical model agrees very well with the experimental piston pump position data when tuned for additional unmodeled mechanical friction. Optimized results suggest that an improvement of 400% of the state of the art power density is attainable with as high as 85% net efficiency. This demonstrates that a linear electromagnetic piston pump has potential to serve as a more compact and efficient supply of fluid power for the human scale.
International Nuclear Information System (INIS)
Vretenar, M
2014-01-01
The main features of radio-frequency linear accelerators are introduced, reviewing the different types of accelerating structures and presenting the main characteristics aspects of linac beam dynamics
Troubleshooting analog circuits
Pease, Robert A
1991-01-01
Troubleshooting Analog Circuits is a guidebook for solving product or process related problems in analog circuits. The book also provides advice in selecting equipment, preventing problems, and general tips. The coverage of the book includes the philosophy of troubleshooting; the modes of failure of various components; and preventive measures. The text also deals with the active components of analog circuits, including diodes and rectifiers, optically coupled devices, solar cells, and batteries. The book will be of great use to both students and practitioners of electronics engineering. Other
Marston, R M
2013-01-01
Modern TTL Circuits Manual provides an introduction to the basic principles of Transistor-Transistor Logic (TTL). This book outlines the major features of the 74 series of integrated circuits (ICs) and introduces the various sub-groups of the TTL family.Organized into seven chapters, this book begins with an overview of the basics of digital ICs. This text then examines the symbology and mathematics of digital logic. Other chapters consider a variety of topics, including waveform generator circuitry, clocked flip-flop and counter circuits, special counter/dividers, registers, data latches, com
Circuit analysis with Multisim
Baez-Lopez, David
2011-01-01
This book is concerned with circuit simulation using National Instruments Multisim. It focuses on the use and comprehension of the working techniques for electrical and electronic circuit simulation. The first chapters are devoted to basic circuit analysis.It starts by describing in detail how to perform a DC analysis using only resistors and independent and controlled sources. Then, it introduces capacitors and inductors to make a transient analysis. In the case of transient analysis, it is possible to have an initial condition either in the capacitor voltage or in the inductor current, or bo
Optoelectronics circuits manual
Marston, R M
2013-01-01
Optoelectronics Circuits Manual covers the basic principles and characteristics of the best known types of optoelectronic devices, as well as the practical applications of many of these optoelectronic devices. The book describes LED display circuits and LED dot- and bar-graph circuits and discusses the applications of seven-segment displays, light-sensitive devices, optocouplers, and a variety of brightness control techniques. The text also tackles infrared light-beam alarms and multichannel remote control systems. The book provides practical user information and circuitry and illustrations.
'Speedy' superconducting circuits
International Nuclear Information System (INIS)
Holst, T.
1994-01-01
The most promising concept for realizing ultra-fast superconducting digital circuits is the Rapid Single Flux Quantum (RSFQ) logic. The basic physical principle behind RSFQ logic, which include the storage and transfer of individual magnetic flux quanta in Superconducting Quantum Interference Devices (SQUIDs), is explained. A Set-Reset flip-flop is used as an example of the implementation of an RSFQ based circuit. Finally, the outlook for high-temperature superconducting materials in connection with RSFQ circuits is discussed in some details. (au)
Potential and limits to cluster-state quantum computing using probabilistic gates
International Nuclear Information System (INIS)
Gross, D.; Kieling, K.; Eisert, J.
2006-01-01
We establish bounds to the necessary resource consumption when building up cluster states for one-way computing using probabilistic gates. Emphasis is put on state preparation with linear optical gates, as the probabilistic character is unavoidable here. We identify rigorous general bounds to the necessary consumption of initially available maximally entangled pairs when building up one-dimensional cluster states with individually acting linear optical quantum gates, entangled pairs, and vacuum modes. As the known linear optics gates have a limited maximum success probability, as we show, this amounts to finding the optimal classical strategy of fusing pieces of linear cluster states. A formal notion of classical configurations and strategies is introduced for probabilistic nonfaulty gates. We study the asymptotic performance of strategies that can be simply described, and prove ultimate bounds to the performance of the globally optimal strategy. The arguments employ methods of random walks and convex optimization. This optimal strategy is also the one that requires the shortest storage time, and necessitates the fewest invocations of probabilistic gates. For two-dimensional cluster states, we find, for any elementary success probability, an essentially deterministic preparation of a cluster state with quadratic, hence optimal, asymptotic scaling in the use of entangled pairs. We also identify a percolation effect in state preparation, in that from a threshold probability on, almost all preparations will be either successful or fail. We outline the implications on linear optical architectures and fault-tolerant computations
A New Simple Chaotic Circuit Based on Memristor
Wu, Renping; Wang, Chunhua
In this paper, a new memristor is proposed, and then an emulator built from off-the-shelf solid state components imitating the behavior of the proposed memristor is presented. Multisim simulation and breadboard experiment are done on the emulator, exhibiting a pinched hysteresis loop in the voltage-current plane when the emulator is driven by a periodic excitation voltage. In addition, a new simple chaotic circuit is designed by using the proposed memristor and other circuit elements. It is exciting that this circuit with only a linear negative resistor, a capacitor, an inductor and a memristor can generate a chaotic attractor. The dynamical behaviors of the proposed chaotic system are analyzed by Lyapunov exponents, phase portraits and bifurcation diagrams. Finally, an electronic circuit is designed to implement the chaotic system. For the sake of simple circuit topology, the proposed chaotic circuit can be easily manufactured at low cost.
Microdroplet-based universal logic gates by electrorheological fluid
Zhang, Mengying
2011-01-01
We demonstrate a uniquely designed microfluid logic gate with universal functionality, which is capable of conducting all 16 logic operations in one chip, with different input voltage combinations. A kind of smart colloid, giant electrorheological (GER) fluid, functions as the translation media among fluidic, electronic and mechanic information, providing us with the capability of performing large integrations either on-chip or off-chip, while the on-chip hybrid circuit is formed by the interconnection of the electric components and fluidic channels, where the individual microdroplets travelling in a channel represents a bit. The universal logic gate reveals the possibilities of achieving a large-scale microfluidic processor with more complexity for on-chip processing for biological, chemical as well as computational experiments. © 2011 The Royal Society of Chemistry.
Assembly of Nanoscale Organic Single-Crystal Cross-Wire Circuits
DEFF Research Database (Denmark)
Bjørnholm, Thomas
2009-01-01
Organic single-crystal transistors and circuits can be assembled by nanomechanical manipulation of nanowires of CuPc, F(16)CuPc, and SnO(2):Sb. The crossed bar devices have low operational voltage, high mobility and are stable in air. They can be combined into circuits, providing varied functions...... including inverters and NOR and NAND logic gates, opening new opportunities for organic nanoelectronics and highly sophisticated integrated logic devices....
Field-Programmable Gate Array-based fluxgate magnetometer with digital integration
Butta, Mattia; Janosek, Michal; Ripka, Pavel
2010-05-01
In this paper, a digital magnetometer based on printed circuit board fluxgate is presented. The fluxgate is pulse excited and the signal is extracted by gate integration. We investigate the possibility to perform integration on very narrow gates (typically 500 ns) by using digital techniques. The magnetometer is based on field-programmable gate array (FPGA) card: we will show all the advantages and disadvantages, given by digitalization of fluxgate output voltage by means of analog-to-digital converter on FPGA card, as well as digitalization performed by external digitizer. Due to very narrow gate, it is shown that a magnetometer entirely based on a FPGA card is preferable, because it avoids noise due to trigger instability. Both open loop and feedback operative mode are described and achieved results are presented.
Microwave potentials and optimal control for robust quantum gates on an atom chip
International Nuclear Information System (INIS)
Treutlein, Philipp; Haensch, Theodor W.; Reichel, Jakob; Negretti, Antonio; Cirone, Markus A.; Calarco, Tommaso
2006-01-01
We propose a two-qubit collisional phase gate that can be implemented with available atom chip technology and present a detailed theoretical analysis of its performance. The gate is based on earlier phase gate schemes, but uses a qubit state pair with an experimentally demonstrated, very long coherence lifetime. Microwave near fields play a key role in our implementation as a means to realize the state-dependent potentials required for conditional dynamics. Quantum control algorithms are used to optimize gate performance. We employ circuit configurations that can be built with current fabrication processes and extensively discuss the impact of technical noise and imperfections that characterize an actual atom chip. We find an overall infidelity compatible with requirements for fault-tolerant quantum computation
The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator
Jafar, N.; Soin, N.
2009-06-01
This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.
Integrated-optics heralded controlled-NOT gate for polarization-encoded qubits
Zeuner, Jonas; Sharma, Aditya N.; Tillmann, Max; Heilmann, René; Gräfe, Markus; Moqanaki, Amir; Szameit, Alexander; Walther, Philip
2018-03-01
Recent progress in integrated-optics technology has made photonics a promising platform for quantum networks and quantum computation protocols. Integrated optical circuits are characterized by small device footprints and unrivalled intrinsic interferometric stability. Here, we take advantage of femtosecond-laser-written waveguides' ability to process polarization-encoded qubits and present an implementation of a heralded controlled-NOT gate on chip. We evaluate the gate performance in the computational basis and a superposition basis, showing that the gate can create polarization entanglement between two photons. Transmission through the integrated device is optimized using thermally expanded core fibers and adiabatically reduced mode-field diameters at the waveguide facets. This demonstration underlines the feasibility of integrated quantum gates for all-optical quantum networks and quantum repeaters.
Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng
2017-01-01
Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...
Energy Technology Data Exchange (ETDEWEB)
Mendo, C
1988-09-01
Most analogue simulators have evolved from SPICE. The history and description of SPICE-like simulators are given. From a mathematical formulation of the electronic circuit the following analysis are possible: DC, AC, transient, noise, distortion, Worst Case and Statistical.
Laurent Guiraud
1999-01-01
A printed circuit board made by scientists in the ATLAS collaboration for the transition radiaton tracker (TRT). This will read data produced when a high energy particle crosses the boundary between two materials with different electrical properties.
Energy Technology Data Exchange (ETDEWEB)
Munehiro, H
1980-05-29
When driving the carriage of a printer through a rotating motor, there are problems regarding the limited accuracy of the carriage position due to rotation or contraction and ageing of the cable. In order to solve the problem, a direct drive system was proposed, in which the printer carriage is driven by a linear motor. If one wants to keep the motor circuit of such a motor compact, then the magnetic flux density in the air gap must be reduced or the motor travel must be reduced. It is the purpose of this invention to create an electrodynamic linear motor, which on the one hand is compact and light and on the other hand has a relatively high constant force over a large travel. The invention is characterised by the fact that magnetic fields of alternating polarity are generated at equal intervals in the magnetic field, and that the coil arrangement has 2 adjacent coils, whose size corresponds to half the length of each magnetic pole. A logic circuit is provided to select one of the two coils and to determine the direction of the current depending on the signals of a magnetic field sensor on the coil arrangement.
Said-Houari, Belkacem
2017-01-01
This self-contained, clearly written textbook on linear algebra is easily accessible for students. It begins with the simple linear equation and generalizes several notions from this equation for the system of linear equations and introduces the main ideas using matrices. It then offers a detailed chapter on determinants and introduces the main ideas with detailed proofs. The third chapter introduces the Euclidean spaces using very simple geometric ideas and discusses various major inequalities and identities. These ideas offer a solid basis for understanding general Hilbert spaces in functional analysis. The following two chapters address general vector spaces, including some rigorous proofs to all the main results, and linear transformation: areas that are ignored or are poorly explained in many textbooks. Chapter 6 introduces the idea of matrices using linear transformation, which is easier to understand than the usual theory of matrices approach. The final two chapters are more advanced, introducing t...
Topics in linear optical quantum computation
Glancy, Scott Charles
This thesis covers several topics in optical quantum computation. A quantum computer is a computational device which is able to manipulate information by performing unitary operations on some physical system whose state can be described as a vector (or mixture of vectors) in a Hilbert space. The basic unit of information, called the qubit, is considered to be a system with two orthogonal states, which are assigned logical values of 0 and 1. Photons make excellent candidates to serve as qubits. They have little interactions with the environment. Many operations can be performed using very simple linear optical devices such as beam splitters and phase shifters. Photons can easily be processed through circuit-like networks. Operations can be performed in very short times. Photons are ideally suited for the long-distance communication of quantum information. The great difficulty in constructing an optical quantum computer is that photons naturally interact weakly with one another. This thesis first gives a brief review of two early approaches to optical quantum computation. It will describe how any discrete unitary operation can be performed using a single photon and a network of beam splitters, and how the Kerr effect can be used to construct a two photon logic gate. Second, this work provides a thorough introduction to the linear optical quantum computer developed by Knill, Laflamme, and Milburn. It then presents this author's results on the reliability of this scheme when implemented using imperfect photon detectors. This author finds that quantum computers of this sort cannot be built using current technology. Third, this dissertation describes a method for constructing a linear optical quantum computer using nearly orthogonal coherent states of light as the qubits. It shows how a universal set of logic operations can be performed, including calculations of the fidelity with which these operations may be accomplished. It discusses methods for reducing and
Demonstration of a Quantum Nondemolition Sum Gate
DEFF Research Database (Denmark)
Yoshikawa, J.; Miwa, Y.; Huck, Alexander
2008-01-01
The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...
Exact Synthesis of Reversible Circuits Using A* Algorithm
Datta, K.; Rathi, G. K.; Sengupta, I.; Rahaman, H.
2015-06-01
With the growing emphasis on low-power design methodologies, and the result that theoretical zero power dissipation is possible only if computations are information lossless, design and synthesis of reversible logic circuits have become very important in recent years. Reversible logic circuits are also important in the context of quantum computing, where the basic operations are reversible in nature. Several synthesis methodologies for reversible circuits have been reported. Some of these methods are termed as exact, where the motivation is to get the minimum-gate realization for a given reversible function. These methods are computationally very intensive, and are able to synthesize only very small functions. There are other methods based on function transformations or higher-level representation of functions like binary decision diagrams or exclusive-or sum-of-products, that are able to handle much larger circuits without any guarantee of optimality or near-optimality. Design of exact synthesis algorithms is interesting in this context, because they set some kind of benchmarks against which other methods can be compared. This paper proposes an exact synthesis approach based on an iterative deepening version of the A* algorithm using the multiple-control Toffoli gate library. Experimental results are presented with comparisons with other exact and some heuristic based synthesis approaches.
Application of Memristors in Microwave Passive Circuits
Directory of Open Access Journals (Sweden)
M.Potrebic
2015-06-01
Full Text Available The recent implementation of the fourth fundamental electric circuit element, the memristor, opened new vistas in many fields of engineering applications. In this paper, we explore several RF/microwave passive circuits that might benefit from the memristor salient characteristics. We consider a power divider, coupled resonator bandpass filters, and a low-reflection quasi-Gaussian lowpass filter with lossy elements. We utilize memristors as configurable linear resistors and we propose memristor-based bandpass filters that feature suppression of parasitic frequency pass bands and widening of the desired rejection band. The simulations are performed in the time domain, using LTspice, and the RF/microwave circuits under consideration are modeled by ideal elements available in LTspice.
Ultra-Low-Dropout Linear Regulator
Thornton, Trevor; Lepkowski, William; Wilk, Seth
2011-01-01
A radiation-tolerant, ultra-low-dropout linear regulator can operate between -150 and 150 C. Prototype components were demonstrated to be performing well after a total ionizing dose of 1 Mrad (Si). Unlike existing components, the linear regulator developed during this activity is unconditionally stable over all operating regimes without the need for an external compensation capacitor. The absence of an external capacitor reduces overall system mass/volume, increases reliability, and lowers cost. Linear regulators generate a precisely controlled voltage for electronic circuits regardless of fluctuations in the load current that the circuit draws from the regulator.
International Nuclear Information System (INIS)
Courtin, E.; Grund, K.; Traub, S.; Zeeb, H.
1975-01-01
The peak reading detector circuit serves for picking up the instants during which peaks of a given polarity occur in sequences of signals in which the extreme values, their time intervals, and the curve shape of the signals vary. The signal sequences appear in measuring the foetal heart beat frequence from amplitude-modulated ultrasonic, electrocardiagram, and blood pressure signals. In order to prevent undesired emission of output signals from, e. g., disturbing intermediate extreme values, the circuit consists of the series connections of a circuit to simulate an ideal diode, a strong unit, a discriminator for the direction of charging current, a time-delay circuit, and an electronic switch lying in the decharging circuit of the storage unit. The time-delay circuit thereby causes storing of a preliminary maximum value being used only after a certain time delay for the emission of the output signal. If a larger extreme value occurs during the delay time the preliminary maximum value is cleared and the delay time starts running anew. (DG/PB) [de
Color Coding of Circuit Quantities in Introductory Circuit Analysis Instruction
Reisslein, Jana; Johnson, Amy M.; Reisslein, Martin
2015-01-01
Learning the analysis of electrical circuits represented by circuit diagrams is often challenging for novice students. An open research question in electrical circuit analysis instruction is whether color coding of the mathematical symbols (variables) that denote electrical quantities can improve circuit analysis learning. The present study…
Project Circuits in a Basic Electric Circuits Course
Becker, James P.; Plumb, Carolyn; Revia, Richard A.
2014-01-01
The use of project circuits (a photoplethysmograph circuit and a simple audio amplifier), introduced in a sophomore-level electric circuits course utilizing active learning and inquiry-based methods, is described. The development of the project circuits was initiated to promote enhanced engagement and deeper understanding of course content among…
An electrically reconfigurable logic gate intrinsically enabled by spin-orbit materials.
Kazemi, Mohammad
2017-11-10
The spin degree of freedom in magnetic devices has been discussed widely for computing, since it could significantly reduce energy dissipation, might enable beyond Von Neumann computing, and could have applications in quantum computing. For spin-based computing to become widespread, however, energy efficient logic gates comprising as few devices as possible are required. Considerable recent progress has been reported in this area. However, proposals for spin-based logic either require ancillary charge-based devices and circuits in each individual gate or adopt principals underlying charge-based computing by employing ancillary spin-based devices, which largely negates possible advantages. Here, we show that spin-orbit materials possess an intrinsic basis for the execution of logic operations. We present a spin-orbit logic gate that performs a universal logic operation utilizing the minimum possible number of devices, that is, the essential devices required for representing the logic operands. Also, whereas the previous proposals for spin-based logic require extra devices in each individual gate to provide reconfigurability, the proposed gate is 'electrically' reconfigurable at run-time simply by setting the amplitude of the clock pulse applied to the gate. We demonstrate, analytically and numerically with experimentally benchmarked models, that the gate performs logic operations and simultaneously stores the result, realizing the 'stateful' spin-based logic scalable to ultralow energy dissipation.
Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates
Chappanda, K. N.; Ilyas, S.; Younis, M. I.
2018-05-01
Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 1012 oscillations.
Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates
Chappanda , K. N.; Ilyas, Saad; Younis, Mohammad I.
2018-01-01
Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.
Micro-mechanical resonators for dynamically reconfigurable reduced voltage logic gates
Chappanda, K N
2018-02-16
Due to the limitations of transistor-based logic devices such as their poor performance at elevated temperature, alternative computing methods are being actively investigated. In this work, we present electromechanical logic gates using electrostatically coupled in-plane micro-cantilever resonators operated at modest vacuum conditions of 5 Torr. Operating in the first resonant mode, we demonstrate 2-bit XOR, 2- and 3-bit AND, 2- and 3-bit NOR, and 1-bit NOT gates; all condensed in the same device. Through the designed electrostatic coupling, the required voltage for the logic gates is reduced by 80%, along with the reduction in the number of electrical interconnects and devices per logic operation (contrary to transistors). The device is dynamically reconfigurable between any logic gates in real time without the need for any change in the electrical interconnects and the drive circuit. By operating in the first two resonant vibration modes, we demonstrate mechanical logic gates consisting of two 2-bit AND and two 2-bit XOR gates. The device is tested at elevated temperatures and is shown to be functional as a logic gate up to 150 °C. Also, the device has high reliability with demonstrated lifetime greater than 5 × 10 oscillations.
Deep Gate Recurrent Neural Network
2016-11-22
and Fred Cummins. Learning to forget: Continual prediction with lstm . Neural computation, 12(10):2451–2471, 2000. Alex Graves. Generating sequences...DSGU) and Simple Gated Unit (SGU), which are structures for learning long-term dependencies. Compared to traditional Long Short-Term Memory ( LSTM ) and...Gated Recurrent Unit (GRU), both structures require fewer parameters and less computation time in sequence classification tasks. Unlike GRU and LSTM
Bill Gates vil redde Folkeskolen
DEFF Research Database (Denmark)
Fejerskov, Adam Moe
2014-01-01
Det amerikanske uddannelsessystem bliver for tiden udsat for hård kritik, ledt an af Microsoft stifteren Bill Gates. Gates har indtil videre brugt 3 mia. kroner på at skabe opbakning til tiltag som præstationslønning af lærere og strømlining af pensum på tværs af alle skoler i landet...
Single Day Construction of Multigene Circuits with 3G Assembly.
Halleran, Andrew D; Swaminathan, Anandh; Murray, Richard M
2018-05-18
The ability to rapidly design, build, and test prototypes is of key importance to every engineering discipline. DNA assembly often serves as a rate limiting step of the prototyping cycle for synthetic biology. Recently developed DNA assembly methods such as isothermal assembly and type IIS restriction enzyme systems take different approaches to accelerate DNA construction. We introduce a hybrid method, Golden Gate-Gibson (3G), that takes advantage of modular part libraries introduced by type IIS restriction enzyme systems and isothermal assembly's ability to build large DNA constructs in single pot reactions. Our method is highly efficient and rapid, facilitating construction of entire multigene circuits in a single day. Additionally, 3G allows generation of variant libraries enabling efficient screening of different possible circuit constructions. We characterize the efficiency and accuracy of 3G assembly for various construct sizes, and demonstrate 3G by characterizing variants of an inducible cell-lysis circuit.
Sasamal, Trailokya Nath; Singh, Ashutosh Kumar; Ghanekar, Umesh
2018-04-01
Nanotechnologies, remarkably Quantum-dot Cellular Automata (QCA), offer an attractive perspective for future computing technologies. In this paper, QCA is investigated as an implementation method for designing area and power efficient reversible logic gates. The proposed designs achieve superior performance by incorporating a compact 2-input XOR gate. The proposed design for Feynman, Toffoli, and Fredkin gates demonstrates 28.12, 24.4, and 7% reduction in cell count and utilizes 46, 24.4, and 7.6% less area, respectively over previous best designs. Regarding the cell count (area cover) that of the proposed Peres gate and Double Feynman gate are 44.32% (21.5%) and 12% (25%), respectively less than the most compact previous designs. Further, the delay of Fredkin and Toffoli gates is 0.75 clock cycles, which is equal to the delay of the previous best designs. While the Feynman and Double Feynman gates achieve a delay of 0.5 clock cycles, equal to the least delay previous one. Energy analysis confirms that the average energy dissipation of the developed Feynman, Toffoli, and Fredkin gates is 30.80, 18.08, and 4.3% (for 1.0 E k energy level), respectively less compared to best reported designs. This emphasizes the beneficial role of using proposed reversible gates to design complex and power efficient QCA circuits. The QCADesigner tool is used to validate the layout of the proposed designs, and the QCAPro tool is used to evaluate the energy dissipation.
High-fidelity quantum gates on quantum-dot-confined electron spins in low-Q optical microcavities
Li, Tao; Gao, Jian-Cun; Deng, Fu-Guo; Long, Gui-Lu
2018-04-01
We propose some high-fidelity quantum circuits for quantum computing on electron spins of quantum dots (QD) embedded in low-Q optical microcavities, including the two-qubit controlled-NOT gate and the multiple-target-qubit controlled-NOT gate. The fidelities of both quantum gates can, in principle, be robust to imperfections involved in a practical input-output process of a single photon by converting the infidelity into a heralded error. Furthermore, the influence of two different decay channels is detailed. By decreasing the quality factor of the present microcavity, we can largely increase the efficiencies of these quantum gates while their high fidelities remain unaffected. This proposal also has another advantage regarding its experimental feasibility, in that both quantum gates can work faithfully even when the QD-cavity systems are non-identical, which is of particular importance in current semiconductor QD technology.
Energy Technology Data Exchange (ETDEWEB)
Kurzhofer, U.; Stolte, J.; Weyand, M.
1996-12-01
Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.
Qualitative models and experimental investigation of chaotic NOR gates and set/reset flip-flops
Rahman, Aminur; Jordan, Ian; Blackmore, Denis
2018-01-01
It has been observed through experiments and SPICE simulations that logical circuits based upon Chua's circuit exhibit complex dynamical behaviour. This behaviour can be used to design analogues of more complex logic families and some properties can be exploited for electronics applications. Some of these circuits have been modelled as systems of ordinary differential equations. However, as the number of components in newer circuits increases so does the complexity. This renders continuous dynamical systems models impractical and necessitates new modelling techniques. In recent years, some discrete dynamical models have been developed using various simplifying assumptions. To create a robust modelling framework for chaotic logical circuits, we developed both deterministic and stochastic discrete dynamical models, which exploit the natural recurrence behaviour, for two chaotic NOR gates and a chaotic set/reset flip-flop. This work presents a complete applied mathematical investigation of logical circuits. Experiments on our own designs of the above circuits are modelled and the models are rigorously analysed and simulated showing surprisingly close qualitative agreement with the experiments. Furthermore, the models are designed to accommodate dynamics of similarly designed circuits. This will allow researchers to develop ever more complex chaotic logical circuits with a simple modelling framework.
Stoll, R R
1968-01-01
Linear Algebra is intended to be used as a text for a one-semester course in linear algebra at the undergraduate level. The treatment of the subject will be both useful to students of mathematics and those interested primarily in applications of the theory. The major prerequisite for mastering the material is the readiness of the student to reason abstractly. Specifically, this calls for an understanding of the fact that axioms are assumptions and that theorems are logical consequences of one or more axioms. Familiarity with calculus and linear differential equations is required for understand