WorldWideScience

Sample records for integrated optical processors

  1. Optical backplane interconnect switch for data processors and computers

    Science.gov (United States)

    Hendricks, Herbert D.; Benz, Harry F.; Hammer, Jacob M.

    1989-01-01

    An optoelectronic integrated device design is reported which can be used to implement an all-optical backplane interconnect switch. The switch is sized to accommodate an array of processors and memories suitable for direct replacement into the basic avionic multiprocessor backplane. The optical backplane interconnect switch is also suitable for direct replacement of the PI bus traffic switch and at the same time, suitable for supporting pipelining of the processor and memory. The 32 bidirectional switchable interconnects are configured with broadcast capability for controls, reconfiguration, and messages. The approach described here can handle a serial interconnection of data processors or a line-to-link interconnection of data processors. An optical fiber demonstration of this approach is presented.

  2. Optical Array Processor: Laboratory Results

    Science.gov (United States)

    Casasent, David; Jackson, James; Vaerewyck, Gerard

    1987-01-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) is described and laboratory results on its performance in several practical engineering problems are presented. The applications include its use in the solution of a nonlinear matrix equation for optimal control and a parabolic Partial Differential Equation (PDE), the transient diffusion equation with two spatial variables. Frequency-multiplexed, analog and high accuracy non-base-two data encoding are used and discussed. A multi-processor OLAP architecture is described and partitioning and data flow issues are addressed.

  3. Optical linear algebra processors - Architectures and algorithms

    Science.gov (United States)

    Casasent, David

    1986-01-01

    Attention is given to the component design and optical configuration features of a generic optical linear algebra processor (OLAP) architecture, as well as the large number of OLAP architectures, number representations, algorithms and applications encountered in current literature. Number-representation issues associated with bipolar and complex-valued data representations, high-accuracy (including floating point) performance, and the base or radix to be employed, are discussed, together with case studies on a space-integrating frequency-multiplexed architecture and a hybrid space-integrating and time-integrating multichannel architecture.

  4. Accuracies Of Optical Processors For Adaptive Optics

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1992-01-01

    Paper presents analysis of accuracies and requirements concerning accuracies of optical linear-algebra processors (OLAP's) in adaptive-optics imaging systems. Much faster than digital electronic processor and eliminate some residual distortion. Question whether errors introduced by analog processing of OLAP overcome advantage of greater speed. Paper addresses issue by presenting estimate of accuracy required in general OLAP that yields smaller average residual aberration of wave front than digital electronic processor computing at given speed.

  5. Programmable optical processor chips: toward photonic RF filters with DSP-level flexibility and MHz-band selectivity

    Directory of Open Access Journals (Sweden)

    Xie Yiwei

    2017-12-01

    Full Text Available Integrated optical signal processors have been identified as a powerful engine for optical processing of microwave signals. They enable wideband and stable signal processing operations on miniaturized chips with ultimate control precision. As a promising application, such processors enables photonic implementations of reconfigurable radio frequency (RF filters with wide design flexibility, large bandwidth, and high-frequency selectivity. This is a key technology for photonic-assisted RF front ends that opens a path to overcoming the bandwidth limitation of current digital electronics. Here, the recent progress of integrated optical signal processors for implementing such RF filters is reviewed. We highlight the use of a low-loss, high-index-contrast stoichiometric silicon nitride waveguide which promises to serve as a practical material platform for realizing high-performance optical signal processors and points toward photonic RF filters with digital signal processing (DSP-level flexibility, hundreds-GHz bandwidth, MHz-band frequency selectivity, and full system integration on a chip scale.

  6. Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

    Science.gov (United States)

    Downie, John D.; Goodman, Joseph W.

    1989-10-01

    The accuracy requirements of optical processors in adaptive optics systems are determined by estimating the required accuracy in a general optical linear algebra processor (OLAP) that results in a smaller average residual aberration than that achieved with a conventional electronic digital processor with some specific computation speed. Special attention is given to an error analysis of a general OLAP with regard to the residual aberration that is created in an adaptive mirror system by the inaccuracies of the processor, and to the effect of computational speed of an electronic processor on the correction. Results are presented on the ability of an OLAP to compete with a digital processor in various situations.

  7. Accuracy requirements of optical linear algebra processors in adaptive optics imaging systems

    Science.gov (United States)

    Downie, John D.

    1990-01-01

    A ground-based adaptive optics imaging telescope system attempts to improve image quality by detecting and correcting for atmospherically induced wavefront aberrations. The required control computations during each cycle will take a finite amount of time. Longer time delays result in larger values of residual wavefront error variance since the atmosphere continues to change during that time. Thus an optical processor may be well-suited for this task. This paper presents a study of the accuracy requirements in a general optical processor that will make it competitive with, or superior to, a conventional digital computer for the adaptive optics application. An optimization of the adaptive optics correction algorithm with respect to an optical processor's degree of accuracy is also briefly discussed.

  8. Photonics and Fiber Optics Processor Lab

    Data.gov (United States)

    Federal Laboratory Consortium — The Photonics and Fiber Optics Processor Lab develops, tests and evaluates high speed fiber optic network components as well as network protocols. In addition, this...

  9. A high-accuracy optical linear algebra processor for finite element applications

    Science.gov (United States)

    Casasent, D.; Taylor, B. K.

    1984-01-01

    Optical linear processors are computationally efficient computers for solving matrix-matrix and matrix-vector oriented problems. Optical system errors limit their dynamic range to 30-40 dB, which limits their accuray to 9-12 bits. Large problems, such as the finite element problem in structural mechanics (with tens or hundreds of thousands of variables) which can exploit the speed of optical processors, require the 32 bit accuracy obtainable from digital machines. To obtain this required 32 bit accuracy with an optical processor, the data can be digitally encoded, thereby reducing the dynamic range requirements of the optical system (i.e., decreasing the effect of optical errors on the data) while providing increased accuracy. This report describes a new digitally encoded optical linear algebra processor architecture for solving finite element and banded matrix-vector problems. A linear static plate bending case study is described which quantities the processor requirements. Multiplication by digital convolution is explained, and the digitally encoded optical processor architecture is advanced.

  10. Recursive Matrix Inverse Update On An Optical Processor

    Science.gov (United States)

    Casasent, David P.; Baranoski, Edward J.

    1988-02-01

    A high accuracy optical linear algebraic processor (OLAP) using the digital multiplication by analog convolution (DMAC) algorithm is described for use in an efficient matrix inverse update algorithm with speed and accuracy advantages. The solution of the parameters in the algorithm are addressed and the advantages of optical over digital linear algebraic processors are advanced.

  11. An integrated processor for photonic quantum states using a broadband light–matter interface

    International Nuclear Information System (INIS)

    Saglamyurek, E; Sinclair, N; Slater, J A; Heshami, K; Oblak, D; Tittel, W

    2014-01-01

    Faithful storage and coherent manipulation of quantum optical pulses are key for long distance quantum communications and quantum computing. Combining these functions in a light–matter interface that can be integrated on-chip with other photonic quantum technologies, e.g. sources of entangled photons, is an important step towards these applications. To date there have only been a few demonstrations of coherent pulse manipulation utilizing optical storage devices compatible with quantum states, and that only in atomic gas media (making integration difficult) and with limited capabilities. Here we describe how a broadband waveguide quantum memory based on the atomic frequency comb (AFC) protocol can be used as a programmable processor for essentially arbitrary spectral and temporal manipulations of individual quantum optical pulses. Using weak coherent optical pulses at the few photon level, we experimentally demonstrate sequencing, time-to-frequency multiplexing and demultiplexing, splitting, interfering, temporal and spectral filtering, compressing and stretching as well as selective delaying. Our integrated light–matter interface offers high-rate, robust and easily configurable manipulation of quantum optical pulses and brings fully practical optical quantum devices one step closer to reality. Furthermore, as the AFC protocol is suitable for storage of intense light pulses, our processor may also find applications in classical communications. (paper)

  12. Ring-array processor distribution topology for optical interconnects

    Science.gov (United States)

    Li, Yao; Ha, Berlin; Wang, Ting; Wang, Sunyu; Katz, A.; Lu, X. J.; Kanterakis, E.

    1992-01-01

    The existing linear and rectangular processor distribution topologies for optical interconnects, although promising in many respects, cannot solve problems such as clock skews, the lack of supporting elements for efficient optical implementation, etc. The use of a ring-array processor distribution topology, however, can overcome these problems. Here, a study of the ring-array topology is conducted with an aim of implementing various fast clock rate, high-performance, compact optical networks for digital electronic multiprocessor computers. Practical design issues are addressed. Some proof-of-principle experimental results are included.

  13. Integrated fuel processor development

    International Nuclear Information System (INIS)

    Ahmed, S.; Pereira, C.; Lee, S. H. D.; Krumpelt, M.

    2001-01-01

    The Department of Energy's Office of Advanced Automotive Technologies has been supporting the development of fuel-flexible fuel processors at Argonne National Laboratory. These fuel processors will enable fuel cell vehicles to operate on fuels available through the existing infrastructure. The constraints of on-board space and weight require that these fuel processors be designed to be compact and lightweight, while meeting the performance targets for efficiency and gas quality needed for the fuel cell. This paper discusses the performance of a prototype fuel processor that has been designed and fabricated to operate with liquid fuels, such as gasoline, ethanol, methanol, etc. Rated for a capacity of 10 kWe (one-fifth of that needed for a car), the prototype fuel processor integrates the unit operations (vaporization, heat exchange, etc.) and processes (reforming, water-gas shift, preferential oxidation reactions, etc.) necessary to produce the hydrogen-rich gas (reformate) that will fuel the polymer electrolyte fuel cell stacks. The fuel processor work is being complemented by analytical and fundamental research. With the ultimate objective of meeting on-board fuel processor goals, these studies include: modeling fuel cell systems to identify design and operating features; evaluating alternative fuel processing options; and developing appropriate catalysts and materials. Issues and outstanding challenges that need to be overcome in order to develop practical, on-board devices are discussed

  14. Accuracy Limitations in Optical Linear Algebra Processors

    Science.gov (United States)

    Batsell, Stephen Gordon

    1990-01-01

    One of the limiting factors in applying optical linear algebra processors (OLAPs) to real-world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication and addition operations, noise from spatial variations across arrays, and from crosstalk. In this dissertation, we propose a second-order statistical model for an OLAP which incorporates all these system noise sources. We now apply this knowledge to determining upper and lower bounds on the achievable accuracy. This is accomplished by first translating the standard definition of accuracy used in electronic digital processors to analog optical processors. We then employ our second-order statistical model. Having determined a general accuracy equation, we consider limiting cases such as for ideal and noisy components. From the ideal case, we find the fundamental limitations on improving analog processor accuracy. From the noisy case, we determine the practical limitations based on both device and system noise sources. These bounds allow system trade-offs to be made both in the choice of architecture and in individual components in such a way as to maximize the accuracy of the processor. Finally, by determining the fundamental limitations, we show the system engineer when the accuracy desired can be achieved from hardware or architecture improvements and when it must come from signal pre-processing and/or post-processing techniques.

  15. Optical chirp z-transform processor with a simplified architecture.

    Science.gov (United States)

    Ngo, Nam Quoc

    2014-12-29

    Using a simplified chirp z-transform (CZT) algorithm based on the discrete-time convolution method, this paper presents the synthesis of a simplified architecture of a reconfigurable optical chirp z-transform (OCZT) processor based on the silica-based planar lightwave circuit (PLC) technology. In the simplified architecture of the reconfigurable OCZT, the required number of optical components is small and there are no waveguide crossings which make fabrication easy. The design of a novel type of optical discrete Fourier transform (ODFT) processor as a special case of the synthesized OCZT is then presented to demonstrate its effectiveness. The designed ODFT can be potentially used as an optical demultiplexer at the receiver of an optical fiber orthogonal frequency division multiplexing (OFDM) transmission system.

  16. Integrated Optical Synthetic Aperture Radar Processor.

    Science.gov (United States)

    1987-09-01

    acoustooptic cell was employed to input each radar return into a time-and-space integrating optical architecture comprised of several lenses, a CCD area array...acoustooptic cell and parallel rib waveguide structure. During the course of the literature survey, we became aware of an elegant and poten- tially profound...wave.) scatterer at (f , A(t) is the far-field pattern of the antenna. From the geometry of Si. 1. R can be written as [I-2R,/c - nT1 r(t) = A(nT) rectj

  17. Integrated optical circuits for numerical computation

    Science.gov (United States)

    Verber, C. M.; Kenan, R. P.

    1983-01-01

    The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

  18. Optical Finite Element Processor

    Science.gov (United States)

    Casasent, David; Taylor, Bradley K.

    1986-01-01

    A new high-accuracy optical linear algebra processor (OLAP) with many advantageous features is described. It achieves floating point accuracy, handles bipolar data by sign-magnitude representation, performs LU decomposition using only one channel, easily partitions and considers data flow. A new application (finite element (FE) structural analysis) for OLAPs is introduced and the results of a case study presented. Error sources in encoded OLAPs are addressed for the first time. Their modeling and simulation are discussed and quantitative data are presented. Dominant error sources and the effects of composite error sources are analyzed.

  19. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    Energy Technology Data Exchange (ETDEWEB)

    Barhen, Jacob [ORNL; Kerekes, Ryan A [ORNL; ST Charles, Jesse Lee [ORNL; Buckner, Mark A [ORNL

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  20. MULTI-CORE AND OPTICAL PROCESSOR RELATED APPLICATIONS RESEARCH AT OAK RIDGE NATIONAL LABORATORY

    International Nuclear Information System (INIS)

    Barhen, Jacob; Kerekes, Ryan A.; St Charles, Jesse Lee; Buckner, Mark A.

    2008-01-01

    High-speed parallelization of common tasks holds great promise as a low-risk approach to achieving the significant increases in signal processing and computational performance required for next generation innovations in reconfigurable radio systems. Researchers at the Oak Ridge National Laboratory have been working on exploiting the parallelization offered by this emerging technology and applying it to a variety of problems. This paper will highlight recent experience with four different parallel processors applied to signal processing tasks that are directly relevant to signal processing required for SDR/CR waveforms. The first is the EnLight Optical Core Processor applied to matched filter (MF) correlation processing via fast Fourier transform (FFT) of broadband Dopplersensitive waveforms (DSW) using active sonar arrays for target tracking. The second is the IBM CELL Broadband Engine applied to 2-D discrete Fourier transform (DFT) kernel for image processing and frequency domain processing. And the third is the NVIDIA graphical processor applied to document feature clustering. EnLight Optical Core Processor. Optical processing is inherently capable of high-parallelism that can be translated to very high performance, low power dissipation computing. The EnLight 256 is a small form factor signal processing chip (5x5 cm2) with a digital optical core that is being developed by an Israeli startup company. As part of its evaluation of foreign technology, ORNL's Center for Engineering Science Advanced Research (CESAR) had access to a precursor EnLight 64 Alpha hardware for a preliminary assessment of capabilities in terms of large Fourier transforms for matched filter banks and on applications related to Doppler-sensitive waveforms. This processor is optimized for array operations, which it performs in fixed-point arithmetic at the rate of 16 TeraOPS at 8-bit precision. This is approximately 1000 times faster than the fastest DSP available today. The optical core

  1. Parallel Processor for 3D Recovery from Optical Flow

    Directory of Open Access Journals (Sweden)

    Jose Hugo Barron-Zambrano

    2009-01-01

    Full Text Available 3D recovery from motion has received a major effort in computer vision systems in the recent years. The main problem lies in the number of operations and memory accesses to be performed by the majority of the existing techniques when translated to hardware or software implementations. This paper proposes a parallel processor for 3D recovery from optical flow. Its main feature is the maximum reuse of data and the low number of clock cycles to calculate the optical flow, along with the precision with which 3D recovery is achieved. The results of the proposed architecture as well as those from processor synthesis are presented.

  2. Rational calculation accuracy in acousto-optical matrix-vector processor

    Science.gov (United States)

    Oparin, V. V.; Tigin, Dmitry V.

    1994-01-01

    The high speed of parallel computations for a comparatively small-size processor and acceptable power consumption makes the usage of acousto-optic matrix-vector multiplier (AOMVM) attractive for processing of large amounts of information in real time. The limited accuracy of computations is an essential disadvantage of such a processor. The reduced accuracy requirements allow for considerable simplification of the AOMVM architecture and the reduction of the demands on its components.

  3. Noise limitations in optical linear algebra processors.

    Science.gov (United States)

    Batsell, S G; Jong, T L; Walkup, J F; Krile, T F

    1990-05-10

    A general statistical noise model is presented for optical linear algebra processors. A statistical analysis which includes device noise, the multiplication process, and the addition operation is undertaken. We focus on those processes which are architecturally independent. Finally, experimental results which verify the analytical predictions are also presented.

  4. Matrix preconditioning: a robust operation for optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A; Paparao, P

    1987-07-15

    Analog electrooptical processors are best suited for applications demanding high computational throughput with tolerance for inaccuracies. Matrix preconditioning is one such application. Matrix preconditioning is a preprocessing step for reducing the condition number of a matrix and is used extensively with gradient algorithms for increasing the rate of convergence and improving the accuracy of the solution. In this paper, we describe a simple parallel algorithm for matrix preconditioning, which can be implemented efficiently on a pipelined optical linear algebra processor. From the results of our numerical experiments we show that the efficacy of the preconditioning algorithm is affected very little by the errors of the optical system.

  5. Space and frequency-multiplexed optical linear algebra processor - Fabrication and initial tests

    Science.gov (United States)

    Casasent, D.; Jackson, J.

    1986-01-01

    A new optical linear algebra processor architecture is described. Space and frequency-multiplexing are used to accommodate bipolar and complex-valued data. A fabricated laboratory version of this processor is described, the electronic support system used is discussed, and initial test data obtained on it are presented.

  6. Microlens array processor with programmable weight mask and direct optical input

    Science.gov (United States)

    Schmid, Volker R.; Lueder, Ernst H.; Bader, Gerhard; Maier, Gert; Siegordner, Jochen

    1999-03-01

    We present an optical feature extraction system with a microlens array processor. The system is suitable for online implementation of a variety of transforms such as the Walsh transform and DCT. Operating with incoherent light, our processor accepts direct optical input. Employing a sandwich- like architecture, we obtain a very compact design of the optical system. The key elements of the microlens array processor are a square array of 15 X 15 spherical microlenses on acrylic substrate and a spatial light modulator as transmissive mask. The light distribution behind the mask is imaged onto the pixels of a customized a-Si image sensor with adjustable gain. We obtain one output sample for each microlens image and its corresponding weight mask area as summation of the transmitted intensity within one sensor pixel. The resulting architecture is very compact and robust like a conventional camera lens while incorporating a high degree of parallelism. We successfully demonstrate a Walsh transform into the spatial frequency domain as well as the implementation of a discrete cosine transform with digitized gray values. We provide results showing the transformation performance for both synthetic image patterns and images of natural texture samples. The extracted frequency features are suitable for neural classification of the input image. Other transforms and correlations can be implemented in real-time allowing adaptive optical signal processing.

  7. Reconfigurable lattice mesh designs for programmable photonic processors.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José; Soref, Richard A

    2016-05-30

    We propose and analyse two novel mesh design geometries for the implementation of tunable optical cores in programmable photonic processors. These geometries are the hexagonal and the triangular lattice. They are compared here to a previously proposed square mesh topology in terms of a series of figures of merit that account for metrics that are relevant to on-chip integration of the mesh. We find that that the hexagonal mesh is the most suitable option of the three considered for the implementation of the reconfigurable optical core in the programmable processor.

  8. Optical linear algebra processors - Noise and error-source modeling

    Science.gov (United States)

    Casasent, D.; Ghosh, A.

    1985-01-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAPs) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  9. Optical linear algebra processors: noise and error-source modeling.

    Science.gov (United States)

    Casasent, D; Ghosh, A

    1985-06-01

    The modeling of system and component noise and error sources in optical linear algebra processors (OLAP's) are considered, with attention to the frequency-multiplexed OLAP. General expressions are obtained for the output produced as a function of various component errors and noise. A digital simulator for this model is discussed.

  10. International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

    Science.gov (United States)

    Ostrowsky, D. B.; Sriram, S.

    Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

  11. Performance of direct and iterative algorithms on an optical systolic processor

    Science.gov (United States)

    Ghosh, A. K.; Casasent, D.; Neuman, C. P.

    1985-11-01

    The frequency-multiplexed optical linear algebra processor (OLAP) is treated in detail with attention to its performance in the solution of systems of linear algebraic equations (LAEs). General guidelines suitable for most OLAPs, including digital-optical processors, are advanced concerning system and component error source models, guidelines for appropriate use of direct and iterative algorithms, the dominant error sources, and the effect of multiple simultaneous error sources. Specific results are advanced on the quantitative performance of both direct and iterative algorithms in the solution of systems of LAEs and in the solution of nonlinear matrix equations. Acoustic attenuation is found to dominate iterative algorithms and detector noise to dominate direct algorithms. The effect of multiple spatial errors is found to be additive. A theoretical expression for the amount of acoustic attenuation allowed is advanced and verified. Simulations and experimental data are included.

  12. Optical Associative Processors For Visual Perception"

    Science.gov (United States)

    Casasent, David; Telfer, Brian

    1988-05-01

    We consider various associative processor modifications required to allow these systems to be used for visual perception, scene analysis, and object recognition. For these applications, decisions on the class of the objects present in the input image are required and thus heteroassociative memories are necessary (rather than the autoassociative memories that have been given most attention). We analyze the performance of both associative processors and note that there is considerable difference between heteroassociative and autoassociative memories. We describe associative processors suitable for realizing functions such as: distortion invariance (using linear discriminant function memory synthesis techniques), noise and image processing performance (using autoassociative memories in cascade with with a heteroassociative processor and with a finite number of autoassociative memory iterations employed), shift invariance (achieved through the use of associative processors operating on feature space data), and the analysis of multiple objects in high noise (which is achieved using associative processing of the output from symbolic correlators). We detail and provide initial demonstrations of the use of associative processors operating on iconic, feature space and symbolic data, as well as adaptive associative processors.

  13. Bounds on achievable accuracy in analog optical linear-algebra processors

    Science.gov (United States)

    Batsell, Stephen G.; Walkup, John F.; Krile, Thomas F.

    1990-07-01

    Upper arid lower bounds on the number of bits of accuracy achievable are determined by applying a seconth-ortler statistical model to the linear algebra processor. The use of bounds was found necessary due to the strong signal-dependence of the noise at the output of the optical linear algebra processor (OLAP). 1 1. ACCURACY BOUNDS One of the limiting factors in applying OLAPs to real world problems has been the poor achievable accuracy of these processors. Little previous research has been done on determining noise sources from a systems perspective which would include noise generated in the multiplication ard addition operations spatial variations across arrays and crosstalk. We have previously examined these noise sources and determined a general model for the output noise mean and variance. The model demonstrates a strony signaldependency in the noise at the output of the processor which has been confirmed by our experiments. 1 We define accuracy similar to its definition for an analog signal input to an analog-to-digital (ND) converter. The number of bits of accuracy achievable is related to the log (base 2) of the number of separable levels at the P/D converter output. The number of separable levels is fouri by dividing the dynamic range by m times the standard deviation of the signal a. 2 Here m determines the error rate in the P/D conversion. The dynamic range can be expressed as the

  14. Negative base encoding in optical linear algebra processors

    Science.gov (United States)

    Perlee, C.; Casasent, D.

    1986-01-01

    In the digital multiplication by analog convolution algorithm, the bits of two encoded numbers are convolved to form the product of the two numbers in mixed binary representation; this output can be easily converted to binary. Attention is presently given to negative base encoding, treating base -2 initially, and then showing that the negative base system can be readily extended to any radix. In general, negative base encoding in optical linear algebra processors represents a more efficient technique than either sign magnitude or 2's complement encoding, when the additions of digitally encoded products are performed in parallel.

  15. Chip-integrated optical power limiter based on an all-passive micro-ring resonator

    Science.gov (United States)

    Yan, Siqi; Dong, Jianji; Zheng, Aoling; Zhang, Xinliang

    2014-10-01

    Recent progress in silicon nanophotonics has dramatically advanced the possible realization of large-scale on-chip optical interconnects integration. Adopting photons as information carriers can break the performance bottleneck of electronic integrated circuit such as serious thermal losses and poor process rates. However, in integrated photonics circuits, few reported work can impose an upper limit of optical power therefore prevent the optical device from harm caused by high power. In this study, we experimentally demonstrate a feasible integrated scheme based on a single all-passive micro-ring resonator to realize the optical power limitation which has a similar function of current limiting circuit in electronics. Besides, we analyze the performance of optical power limiter at various signal bit rates. The results show that the proposed device can limit the signal power effectively at a bit rate up to 20 Gbit/s without deteriorating the signal. Meanwhile, this ultra-compact silicon device can be completely compatible with the electronic technology (typically complementary metal-oxide semiconductor technology), which may pave the way of very large scale integrated photonic circuits for all-optical information processors and artificial intelligence systems.

  16. Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    Levinskas, D.

    1993-01-01

    This report discusses the pin processor which receives metal alloy pins cast from recycled Integral Fast Reactor (IFR) fuel and prepares them for assembly into new IFR fuel elements. Either full length as-cast or precut pins are fed to the machine from a magazine, cut if necessary, and measured for length, weight, diameter and deviation from straightness. Accepted pins are loaded into cladding jackets located in a magazine, while rejects and cutting scraps are separated into trays. The magazines, trays, and the individual modules that perform the different machine functions are assembled and removed using remote manipulators and master-slaves

  17. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  18. Wavelength-encoded OCDMA system using opto-VLSI processors

    Science.gov (United States)

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  19. Performance evaluation of integrated fuel processor for residential PEMFCs application

    International Nuclear Information System (INIS)

    Yu Taek Seo; Dong Joo Seo; Young-Seog Seo; Hyun-Seog Roh; Wang Lai Yoon; Jin Hyeok Jeong

    2006-01-01

    KIER has been developing the natural gas fuel processor to produce hydrogen rich gas for residential PEMFCs system. To realize a compact and high efficiency, the unit processes of steam reforming, water gas shift, and preferential oxidation are chemically and physically integrated in a package. Current fuel processor designed for 1 kW class PEMFCs shows thermal efficiency of 78% as a HHV basis with methane conversion of 90% at rated load operation. CO concentration below 10 ppm in the produced gas is achieved with preferential oxidation unit using Pt and Ru based catalyst under the condition of [O 2 ]/[CO]=2.0. The partial load operation have been carried out to test the performance of fuel processor from 40% to 80% load, showing stable methane conversion and CO concentration below 10 ppm. The durability test for the daily start-stop and 8 hr operation procedure is under investigation and shows no deterioration of its performance after 40 start-stop cycles. (authors)

  20. Realization of preconditioned Lanczos and conjugate gradient algorithms on optical linear algebra processors.

    Science.gov (United States)

    Ghosh, A

    1988-08-01

    Lanczos and conjugate gradient algorithms are important in computational linear algebra. In this paper, a parallel pipelined realization of these algorithms on a ring of optical linear algebra processors is described. The flow of data is designed to minimize the idle times of the optical multiprocessor and the redundancy of computations. The effects of optical round-off errors on the solutions obtained by the optical Lanczos and conjugate gradient algorithms are analyzed, and it is shown that optical preconditioning can improve the accuracy of these algorithms substantially. Algorithms for optical preconditioning and results of numerical experiments on solving linear systems of equations arising from partial differential equations are discussed. Since the Lanczos algorithm is used mostly with sparse matrices, a folded storage scheme to represent sparse matrices on spatial light modulators is also described.

  1. A lock circuit for a multi-core processor

    DEFF Research Database (Denmark)

    2015-01-01

    An integrated circuit comprising a multiple processor cores and a lock circuit that comprises a queue register with respective bits set or reset via respective, connections dedicated to respective processor cores, whereby the queue register identifies those among the multiple processor cores...... that are enqueued in the queue register. Furthermore, the integrated circuit comprises a current register and a selector circuit configured to select a processor core and identify that processor core by a value in the current register. A selected processor core is a prioritized processor core among the cores...... configured with an integrated circuit; and a silicon die configured with an integrated circuit....

  2. Compact optical processor for Hough and frequency domain features

    Science.gov (United States)

    Ott, Peter

    1996-11-01

    Shape recognition is necessary in a broad band of applications such as traffic sign or work piece recognition. It requires not only neighborhood processing of the input image pixels but global interconnection of them. The Hough transform (HT) performs such a global operation and it is well suited in the preprocessing stage of a shape recognition system. Translation invariant features can be easily calculated form the Hough domain. We have implemented on the computer a neural network shape recognition system which contains a HT, a feature extraction, and a classification layer. The advantage of this approach is that the total system can be optimized with well-known learning techniques and that it can explore the parallelism of the algorithms. However, the HT is a time consuming operation. Parallel, optical processing is therefore advantageous. Several systems have been proposed, based on space multiplexing with arrays of holograms and CGH's or time multiplexing with acousto-optic processors or by image rotation with incoherent and coherent astigmatic optical processors. We took up the last mentioned approach because 2D array detectors are read out line by line, so a 2D detector can achieve the same speed and is easier to implement. Coherent processing can allow the implementation of tilers in the frequency domain. Features based on wedge/ring, Gabor, or wavelet filters have been proven to show good discrimination capabilities for texture and shape recognition. The astigmatic lens system which is derived form the mathematical formulation of the HT is long and contains a non-standard, astigmatic element. By methods of lens transformation s for coherent applications we map the original design to a shorter lens with a smaller number of well separated standard elements and with the same coherent system response. The final lens design still contains the frequency plane for filtering and ray-tracing shows diffraction limited performance. Image rotation can be done

  3. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Science.gov (United States)

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  4. Simple example of track finding by Fourier transform and possibilities for vector or optical processors

    International Nuclear Information System (INIS)

    Underwood, D.

    1986-01-01

    Simple examples of finding tracks by Fourier transform with filter or correlation function are presented. Possibilities for using this method in more complicated real situations and the processing times which might be achieved are discussed. The method imitates the simplest examples in the literature on optical pattern recognition and optical processing. The possible benefits of the method are in speed of processing in the optical Fourier transform wherein an entire picture is processed simultaneously. The speed of a computer vector processor may be competitive with present electro-optical devices. 2 refs., 6 figs

  5. Acoustooptic linear algebra processors - Architectures, algorithms, and applications

    Science.gov (United States)

    Casasent, D.

    1984-01-01

    Architectures, algorithms, and applications for systolic processors are described with attention to the realization of parallel algorithms on various optical systolic array processors. Systolic processors for matrices with special structure and matrices of general structure, and the realization of matrix-vector, matrix-matrix, and triple-matrix products and such architectures are described. Parallel algorithms for direct and indirect solutions to systems of linear algebraic equations and their implementation on optical systolic processors are detailed with attention to the pipelining and flow of data and operations. Parallel algorithms and their optical realization for LU and QR matrix decomposition are specifically detailed. These represent the fundamental operations necessary in the implementation of least squares, eigenvalue, and SVD solutions. Specific applications (e.g., the solution of partial differential equations, adaptive noise cancellation, and optimal control) are described to typify the use of matrix processors in modern advanced signal processing.

  6. Green Secure Processors: Towards Power-Efficient Secure Processor Design

    Science.gov (United States)

    Chhabra, Siddhartha; Solihin, Yan

    With the increasing wealth of digital information stored on computer systems today, security issues have become increasingly important. In addition to attacks targeting the software stack of a system, hardware attacks have become equally likely. Researchers have proposed Secure Processor Architectures which utilize hardware mechanisms for memory encryption and integrity verification to protect the confidentiality and integrity of data and computation, even from sophisticated hardware attacks. While there have been many works addressing performance and other system level issues in secure processor design, power issues have largely been ignored. In this paper, we first analyze the sources of power (energy) increase in different secure processor architectures. We then present a power analysis of various secure processor architectures in terms of their increase in power consumption over a base system with no protection and then provide recommendations for designs that offer the best balance between performance and power without compromising security. We extend our study to the embedded domain as well. We also outline the design of a novel hybrid cryptographic engine that can be used to minimize the power consumption for a secure processor. We believe that if secure processors are to be adopted in future systems (general purpose or embedded), it is critically important that power issues are considered in addition to performance and other system level issues. To the best of our knowledge, this is the first work to examine the power implications of providing hardware mechanisms for security.

  7. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  8. Dual-core Itanium Processor

    CERN Multimedia

    2006-01-01

    Intel’s first dual-core Itanium processor, code-named "Montecito" is a major release of Intel's Itanium 2 Processor Family, which implements the Intel Itanium architecture on a dual-core processor with two cores per die (integrated circuit). Itanium 2 is much more powerful than its predecessor. It has lower power consumption and thermal dissipation.

  9. Satellite on-board real-time SAR processor prototype

    Science.gov (United States)

    Bergeron, Alain; Doucet, Michel; Harnisch, Bernd; Suess, Martin; Marchese, Linda; Bourqui, Pascal; Desnoyers, Nicholas; Legros, Mathieu; Guillot, Ludovic; Mercier, Luc; Châteauneuf, François

    2017-11-01

    A Compact Real-Time Optronic SAR Processor has been successfully developed and tested up to a Technology Readiness Level of 4 (TRL4), the breadboard validation in a laboratory environment. SAR, or Synthetic Aperture Radar, is an active system allowing day and night imaging independent of the cloud coverage of the planet. The SAR raw data is a set of complex data for range and azimuth, which cannot be compressed. Specifically, for planetary missions and unmanned aerial vehicle (UAV) systems with limited communication data rates this is a clear disadvantage. SAR images are typically processed electronically applying dedicated Fourier transformations. This, however, can also be performed optically in real-time. Originally the first SAR images were optically processed. The optical Fourier processor architecture provides inherent parallel computing capabilities allowing real-time SAR data processing and thus the ability for compression and strongly reduced communication bandwidth requirements for the satellite. SAR signal return data are in general complex data. Both amplitude and phase must be combined optically in the SAR processor for each range and azimuth pixel. Amplitude and phase are generated by dedicated spatial light modulators and superimposed by an optical relay set-up. The spatial light modulators display the full complex raw data information over a two-dimensional format, one for the azimuth and one for the range. Since the entire signal history is displayed at once, the processor operates in parallel yielding real-time performances, i.e. without resulting bottleneck. Processing of both azimuth and range information is performed in a single pass. This paper focuses on the onboard capabilities of the compact optical SAR processor prototype that allows in-orbit processing of SAR images. Examples of processed ENVISAT ASAR images are presented. Various SAR processor parameters such as processing capabilities, image quality (point target analysis), weight and

  10. High-performance parallel processors based on star-coupled wavelength division multiplexing optical interconnects

    Science.gov (United States)

    Deri, Robert J.; DeGroot, Anthony J.; Haigh, Ronald E.

    2002-01-01

    As the performance of individual elements within parallel processing systems increases, increased communication capability between distributed processor and memory elements is required. There is great interest in using fiber optics to improve interconnect communication beyond that attainable using electronic technology. Several groups have considered WDM, star-coupled optical interconnects. The invention uses a fiber optic transceiver to provide low latency, high bandwidth channels for such interconnects using a robust multimode fiber technology. Instruction-level simulation is used to quantify the bandwidth, latency, and concurrency required for such interconnects to scale to 256 nodes, each operating at 1 GFLOPS performance. Performance scales have been shown to .apprxeq.100 GFLOPS for scientific application kernels using a small number of wavelengths (8 to 32), only one wavelength received per node, and achievable optoelectronic bandwidth and latency.

  11. Adaptive signal processor

    Energy Technology Data Exchange (ETDEWEB)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 ..mu..sec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed.

  12. Adaptive signal processor

    International Nuclear Information System (INIS)

    Walz, H.V.

    1980-07-01

    An experimental, general purpose adaptive signal processor system has been developed, utilizing a quantized (clipped) version of the Widrow-Hoff least-mean-square adaptive algorithm developed by Moschner. The system accommodates 64 adaptive weight channels with 8-bit resolution for each weight. Internal weight update arithmetic is performed with 16-bit resolution, and the system error signal is measured with 12-bit resolution. An adapt cycle of adjusting all 64 weight channels is accomplished in 8 μsec. Hardware of the signal processor utilizes primarily Schottky-TTL type integrated circuits. A prototype system with 24 weight channels has been constructed and tested. This report presents details of the system design and describes basic experiments performed with the prototype signal processor. Finally some system configurations and applications for this adaptive signal processor are discussed

  13. Integrated Advanced Microwave Sounding Unit-A (AMSU-A). Engineering Test Report: METSAT A1 Signal Processor (P/N: 1331670-2, S/N: F04)

    Science.gov (United States)

    Lund, D.

    1998-01-01

    This report presents a description of the tests performed, and the test data, for the A1 METSAT Signal Processor Assembly PN: 1331679-2, S/N F04. The assembly was tested in accordance with AE-26754, "METSAT Signal Processor Scan Drive Test and Integration Procedure." The objective is to demonstrate functionality of the signal processor prior to instrument integration.

  14. Reducing adaptive optics latency using Xeon Phi many-core processors

    Science.gov (United States)

    Barr, David; Basden, Alastair; Dipper, Nigel; Schwartz, Noah

    2015-11-01

    The next generation of Extremely Large Telescopes (ELTs) for astronomy will rely heavily on the performance of their adaptive optics (AO) systems. Real-time control is at the heart of the critical technologies that will enable telescopes to deliver the best possible science and will require a very significant extrapolation from current AO hardware existing for 4-10 m telescopes. Investigating novel real-time computing architectures and testing their eligibility against anticipated challenges is one of the main priorities of technology development for the ELTs. This paper investigates the suitability of the Intel Xeon Phi, which is a commercial off-the-shelf hardware accelerator. We focus on wavefront reconstruction performance, implementing a straightforward matrix-vector multiplication (MVM) algorithm. We present benchmarking results of the Xeon Phi on a real-time Linux platform, both as a standalone processor and integrated into an existing real-time controller (RTC). Performance of single and multiple Xeon Phis are investigated. We show that this technology has the potential of greatly reducing the mean latency and variations in execution time (jitter) of large AO systems. We present both a detailed performance analysis of the Xeon Phi for a typical E-ELT first-light instrument along with a more general approach that enables us to extend to any AO system size. We show that systematic and detailed performance analysis is an essential part of testing novel real-time control hardware to guarantee optimal science results.

  15. Optical computing - an alternate approach to trigger processing

    International Nuclear Information System (INIS)

    Cleland, W.E.

    1981-01-01

    The enormous rate reduction factors required by most ISABELLE experiments suggest that we should examine every conceivable approach to trigger processing. One approach that has not received much attention by high energy physicists is optical data processing. The past few years have seen rapid advances in optoelectronic technology, stimulated mainly by the military and the communications industry. An intriguing question is whether one can utilize this technology together with the optical computing techniques that have been developed over the past two decades to develop a rapid trigger processor for high energy physics experiments. Optical data processing is a method for performing a few very specialized operations on data which is inherently two dimensional. Typical operations are the formation of convolution or correlation integrals between the input data and information stored in the processor in the form of an optical filter. Optical processors are classed as coherent or incoherent, according to the spatial coherence of the input wavefront. Typically, in a coherent processor a laser beam is modulated with a photographic transparency which represents the input data. In an incoherent processor, the input may be an incoherently illuminated transparency, but self-luminous objects, such as an oscilloscope trace, have also been used. We consider here an incoherent processor in which the input data is converted into an optical wavefront through the excitation of an array of point sources - either light emitting diodes or injection lasers

  16. Optical RAM-enabled cache memory and optical routing for chip multiprocessors: technologies and architectures

    Science.gov (United States)

    Pleros, Nikos; Maniotis, Pavlos; Alexoudi, Theonitsa; Fitsios, Dimitris; Vagionas, Christos; Papaioannou, Sotiris; Vyrsokinos, K.; Kanellos, George T.

    2014-03-01

    The processor-memory performance gap, commonly referred to as "Memory Wall" problem, owes to the speed mismatch between processor and electronic RAM clock frequencies, forcing current Chip Multiprocessor (CMP) configurations to consume more than 50% of the chip real-estate for caching purposes. In this article, we present our recent work spanning from Si-based integrated optical RAM cell architectures up to complete optical cache memory architectures for Chip Multiprocessor configurations. Moreover, we discuss on e/o router subsystems with up to Tb/s routing capacity for cache interconnection purposes within CMP configurations, currently pursued within the FP7 PhoxTrot project.

  17. Two-dimensional optoelectronic interconnect-processor and its operational bit error rate

    Science.gov (United States)

    Liu, J. Jiang; Gollsneider, Brian; Chang, Wayne H.; Carhart, Gary W.; Vorontsov, Mikhail A.; Simonis, George J.; Shoop, Barry L.

    2004-10-01

    Two-dimensional (2-D) multi-channel 8x8 optical interconnect and processor system were designed and developed using complementary metal-oxide-semiconductor (CMOS) driven 850-nm vertical-cavity surface-emitting laser (VCSEL) arrays and the photodetector (PD) arrays with corresponding wavelengths. We performed operation and bit-error-rate (BER) analysis on this free-space integrated 8x8 VCSEL optical interconnects driven by silicon-on-sapphire (SOS) circuits. Pseudo-random bit stream (PRBS) data sequence was used in operation of the interconnects. Eye diagrams were measured from individual channels and analyzed using a digital oscilloscope at data rates from 155 Mb/s to 1.5 Gb/s. Using a statistical model of Gaussian distribution for the random noise in the transmission, we developed a method to compute the BER instantaneously with the digital eye-diagrams. Direct measurements on this interconnects were also taken on a standard BER tester for verification. We found that the results of two methods were in the same order and within 50% accuracy. The integrated interconnects were investigated in an optoelectronic processing architecture of digital halftoning image processor. Error diffusion networks implemented by the inherently parallel nature of photonics promise to provide high quality digital halftoned images.

  18. Demonstration of two-qubit algorithms with a superconducting quantum processor.

    Science.gov (United States)

    DiCarlo, L; Chow, J M; Gambetta, J M; Bishop, Lev S; Johnson, B R; Schuster, D I; Majer, J; Blais, A; Frunzio, L; Girvin, S M; Schoelkopf, R J

    2009-07-09

    Quantum computers, which harness the superposition and entanglement of physical states, could outperform their classical counterparts in solving problems with technological impact-such as factoring large numbers and searching databases. A quantum processor executes algorithms by applying a programmable sequence of gates to an initialized register of qubits, which coherently evolves into a final state containing the result of the computation. Building a quantum processor is challenging because of the need to meet simultaneously requirements that are in conflict: state preparation, long coherence times, universal gate operations and qubit readout. Processors based on a few qubits have been demonstrated using nuclear magnetic resonance, cold ion trap and optical systems, but a solid-state realization has remained an outstanding challenge. Here we demonstrate a two-qubit superconducting processor and the implementation of the Grover search and Deutsch-Jozsa quantum algorithms. We use a two-qubit interaction, tunable in strength by two orders of magnitude on nanosecond timescales, which is mediated by a cavity bus in a circuit quantum electrodynamics architecture. This interaction allows the generation of highly entangled states with concurrence up to 94 per cent. Although this processor constitutes an important step in quantum computing with integrated circuits, continuing efforts to increase qubit coherence times, gate performance and register size will be required to fulfil the promise of a scalable technology.

  19. A CNN-Specific Integrated Processor

    Directory of Open Access Journals (Sweden)

    Suleyman Malki

    2009-01-01

    Full Text Available Integrated Processors (IP are algorithm-specific cores that either by programming or by configuration can be re-used within many microelectronic systems. This paper looks at Cellular Neural Networks (CNN to become realized as IP. First current digital implementations are reviewed, and the memoryprocessor bandwidth issues are analyzed. Then a generic view is taken on the structure of the network, and a new intra-communication protocol based on rotating wheels is proposed. It is shown that this provides for guaranteed high-performance with a minimal network interface. The resulting node is small and supports multi-level CNN designs, giving the system a 30-fold increase in capacity compared to classical designs. As it facilitates multiple operations on a single image, and single operations on multiple images, with minimal access to the external image memory, balancing the internal and external data transfer requirements optimizes the system operation. In conventional digital CNN designs, the treatment of boundary nodes requires additional logic to handle the CNN value propagation scheme. In the new architecture, only a slight modification of the existing cells is necessary to model the boundary effect. A typical prototype for visual pattern recognition will house 4096 CNN cells with a 2% overhead for making it an IP.

  20. Integrated Optical Circuit Engineering

    Science.gov (United States)

    Sriram, S.

    1985-04-01

    Implementation of single-mode optical fiber systems depends largely on the availability of integrated optical components for such functions as switching, multiplexing, and modulation. The technology of integrated optics is maturing very rapidly, and its growth justifies the optimism that now exists in the optical community.

  1. Parallel optical information, concept, and response evolver: POINCARE

    Science.gov (United States)

    Caulfield, H. John; Caulfield, Kimberly

    1991-08-01

    It is now possible to build a nonlinear adaptive system which will incorporate many of the properties of the human mind, such as true originality in such skills as reasoning by analogy and reasoning by retrodiction, including literally unpredictable thoughts; and development of individual styles, personalities, expertise, etc. Like humans, these optical processors will have a rich `subconscious'' experience. Like humans, they will be clonable, but clones will develop differently as they experience the world differently, make different decisions, develop different habits, etc. In short, powerful optical processors with some of the properties normally associated with human intelligence can be made. This approach can result in a powerful optical processor with those properties. A demonstration chosen for simplicity of implementation is suggested. This could be the first computer of any type which uses quantum indeterminacy in an integral and important way.

  2. Functional Verification of Enhanced RISC Processor

    OpenAIRE

    SHANKER NILANGI; SOWMYA L

    2013-01-01

    This paper presents design and verification of a 32-bit enhanced RISC processor core having floating point computations integrated within the core, has been designed to reduce the cost and complexity. The designed 3 stage pipelined 32-bit RISC processor is based on the ARM7 processor architecture with single precision floating point multiplier, floating point adder/subtractor for floating point operations and 32 x 32 booths multiplier added to the integer core of ARM7. The binary representati...

  3. Air-Lubricated Thermal Processor For Dry Silver Film

    Science.gov (United States)

    Siryj, B. W.

    1980-09-01

    Since dry silver film is processed by heat, it may be viewed on a light table only seconds after exposure. On the other hand, wet films require both bulky chemicals and substantial time before an image can be analyzed. Processing of dry silver film, although simple in concept, is not so simple when reduced to practice. The main concern is the effect of film temperature gradients on uniformity of optical film density. RCA has developed two thermal processors, different in implementation but based on the same philosophy. Pressurized air is directed to both sides of the film to support the film and to conduct the heat to the film. Porous graphite is used as the medium through which heat and air are introduced. The initial thermal processor was designed to process 9.5-inch-wide film moving at speeds ranging from 0.0034 to 0.008 inch per second. The processor configuration was curved to match the plane generated by the laser recording beam. The second thermal processor was configured to process 5-inch-wide film moving at a continuously variable rate ranging from 0.15 to 3.5 inches per second. Due to field flattening optics used in this laser recorder, the required film processing area was plane. In addition, this processor was sectioned in the direction of film motion, giving the processor the capability of varying both temperature and effective processing area.

  4. Advances in integrated optics

    CERN Document Server

    Chester, A; Bertolotti, M

    1994-01-01

    This volwne contains the Proceedings of a two-week summer conference titled "Advances in Integrated Optics" held June 1-9, 1993, in Erice, Sicily. This was the 18th annual course organized by the International School of Quantum Electronics, under the auspices of the "Ettore Majorana" Centre for Scientific Culture. The term Integrated Optics signifies guided-wave optical circuits consisting of two or more devices on a single substrate. Since its inception in the late 1960's, Integrated Optics has evolved from a specialized research topic into a broad field of work, ranging from basic research through commercial applications. Today many devices are available on market while a big effort is devolved to research on integrated nonlinear optical devices. This conference was organized to provide a comprehensive survey of the frontiers of this technology, including fundamental concepts, nonlinear optical materials, devices both in the linear and nonlinear regimes, and selected applications. These Proceedings update a...

  5. Multipurpose silicon photonics signal processor core.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Crudgington, Lee; Thomson, David J; Khokhar, Ali Z; Li, Ke; Cao, Wei; Mashanovich, Goran Z; Capmany, José

    2017-09-21

    Integrated photonics changes the scaling laws of information and communication systems offering architectural choices that combine photonics with electronics to optimize performance, power, footprint, and cost. Application-specific photonic integrated circuits, where particular circuits/chips are designed to optimally perform particular functionalities, require a considerable number of design and fabrication iterations leading to long development times. A different approach inspired by electronic Field Programmable Gate Arrays is the programmable photonic processor, where a common hardware implemented by a two-dimensional photonic waveguide mesh realizes different functionalities through programming. Here, we report the demonstration of such reconfigurable waveguide mesh in silicon. We demonstrate over 20 different functionalities with a simple seven hexagonal cell structure, which can be applied to different fields including communications, chemical and biomedical sensing, signal processing, multiprocessor networks, and quantum information systems. Our work is an important step toward this paradigm.Integrated optical circuits today are typically designed for a few special functionalities and require complex design and development procedures. Here, the authors demonstrate a reconfigurable but simple silicon waveguide mesh with different functionalities.

  6. Real-time wavefront processors for the next generation of adaptive optics systems: a design and analysis

    Science.gov (United States)

    Truong, Tuan; Brack, Gary L.; Troy, Mitchell; Trinh, Thang; Shi, Fang; Dekany, Richard G.

    2003-02-01

    Adaptive optics (AO) systems currently under investigation will require at least two orders of magitude increase in the number of actuators, which in turn translates to effectively a 104 increase in compute latency. Since the performance of an AO system invariably improves as the compute latency decreases, it is important to study how today's computer systems will scale to address this expected increase in actuator utilization. This paper answers this question by characterizing the performance of a single deformable mirror (DM) Shack-Hartmann natural guide star AO system implemented on the present-generation digital signal processor (DSP) TMS320C6701 from Texas Instruments. We derive the compute latency of such a system in terms of a few basic parameters, such as the number of DM actuators, the number of data channels used to read out the camera pixels, the number of DSPs, the available memory bandwidth, as well as the inter-processor communication (IPC) bandwidth and the pixel transfer rate. We show how the results would scale for future systems that utilizes multiple DMs and guide stars. We demonstrate that the principal performance bottleneck of such a system is the available memory bandwidth of the processors and to lesser extent the IPC bandwidth. This paper concludes with suggestions for mitigating this bottleneck.

  7. Advanced control system for the Integral Fast Reactor fuel pin processor

    International Nuclear Information System (INIS)

    Lau, L.D.; Randall, P.F.; Benedict, R.W.; Levinskas, D.

    1993-01-01

    A computerized control system has been developed for the remotely-operated fuel pin processor used in the Integral Fast Reactor Program, Fuel Cycle Facility (FCF). The pin processor remotely shears cast EBR- reactor fuel pins to length, inspects them for diameter, straightness, length, and weight, and then inserts acceptable pins into new sodium-loaded stainless-steel fuel element jackets. Two main components comprise the control system: (1) a programmable logic controller (PLC), together with various input/output modules and associated relay ladder-logic associated computer software. The PLC system controls the remote operation of the machine as directed by the OCS, and also monitors the machine operation to make operational data available to the OCS. The OCS allows operator control of the machine, provides nearly real-time viewing of the operational data, allows on-line changes of machine operational parameters, and records the collected data for each acceptable pin on a central data archiving computer. The two main components of the control system provide the operator with various levels of control ranging from manual operation to completely automatic operation by means of a graphic touch screen interface

  8. Error-source effects on the performance of direct and iterative algorithms on an optical matrix-vector processor

    Science.gov (United States)

    Perlee, Caroline J.; Casasent, David P.

    1990-09-01

    Error sources in an optical matrix-vector processor are analyzed in terms of their effect on the performance of the algorithms used to solve a set of nonlinear and linear algebraic equations. A direct and an iterative algorithm are used to solve a nonlinear time-dependent case-study from computational fluid dynamics. A simulator which emulates the data flow and number representation of the OLAP is used to studs? these error effects. The ability of each algorithm to tolerate or correct the error sources is quantified. These results are extended to the general case of solving nonlinear and linear algebraic equations on the optical system.

  9. Effect of processor temperature on film dosimetry

    International Nuclear Information System (INIS)

    Srivastava, Shiv P.; Das, Indra J.

    2012-01-01

    Optical density (OD) of a radiographic film plays an important role in radiation dosimetry, which depends on various parameters, including beam energy, depth, field size, film batch, dose, dose rate, air film interface, postexposure processing time, and temperature of the processor. Most of these parameters have been studied for Kodak XV and extended dose range (EDR) films used in radiation oncology. There is very limited information on processor temperature, which is investigated in this study. Multiple XV and EDR films were exposed in the reference condition (d max. , 10 × 10 cm 2 , 100 cm) to a given dose. An automatic film processor (X-Omat 5000) was used for processing films. The temperature of the processor was adjusted manually with increasing temperature. At each temperature, a set of films was processed to evaluate OD at a given dose. For both films, OD is a linear function of processor temperature in the range of 29.4–40.6°C (85–105°F) for various dose ranges. The changes in processor temperature are directly related to the dose by a quadratic function. A simple linear equation is provided for the changes in OD vs. processor temperature, which could be used for correcting dose in radiation dosimetry when film is used.

  10. Peptide Integrated Optics.

    Science.gov (United States)

    Handelman, Amir; Lapshina, Nadezda; Apter, Boris; Rosenman, Gil

    2018-02-01

    Bio-nanophotonics is a wide field in which advanced optical materials, biomedicine, fundamental optics, and nanotechnology are combined and result in the development of biomedical optical chips. Silk fibers or synthetic bioabsorbable polymers are the main light-guiding components. In this work, an advanced concept of integrated bio-optics is proposed, which is based on bioinspired peptide optical materials exhibiting wide optical transparency, nonlinear and electrooptical properties, and effective passive and active waveguiding. Developed new technology combining bottom-up controlled deposition of peptide planar wafers of a large area and top-down focus ion beam lithography provides direct fabrication of peptide optical integrated circuits. Finding a deep modification of peptide optical properties by reconformation of biological secondary structure from native phase to β-sheet architecture is followed by the appearance of visible fluorescence and unexpected transition from a native passive optical waveguiding to an active one. Original biocompatibility, switchable regimes of waveguiding, and multifunctional nonlinear optical properties make these new peptide planar optical materials attractive for application in emerging technology of lab-on-biochips, combining biomedical photonic and electronic circuits toward medical diagnosis, light-activated therapy, and health monitoring. © 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  11. Multi-gigabit optical interconnects for next-generation on-board digital equipment

    Science.gov (United States)

    Venet, Norbert; Favaro, Henri; Sotom, Michel; Maignan, Michel; Berthon, Jacques

    2017-11-01

    Parallel optical interconnects are experimentally assessed as a technology that may offer the high-throughput data communication capabilities required to the next-generation on-board digital processing units. An optical backplane interconnect was breadboarded, on the basis of a digital transparent processor that provides flexible connectivity and variable bandwidth in telecom missions with multi-beam antenna coverage. The unit selected for the demonstration required that more than tens of Gbit/s be supported by the backplane. The demonstration made use of commercial parallel optical link modules at 850 nm wavelength, with 12 channels running at up to 2.5 Gbit/s. A flexible optical fibre circuit was developed so as to route board-to-board connections. It was plugged to the optical transmitter and receiver modules through 12-fibre MPO connectors. BER below 10-14 and optical link budgets in excess of 12 dB were measured, which would enable to integrate broadcasting. Integration of the optical backplane interconnect was successfully demonstrated by validating the overall digital processor functionality.

  12. Optical Communication over Plastic Optical Fibers Integrated Optical Receiver Technology

    CERN Document Server

    Atef, Mohamed

    2013-01-01

    This book presents high-performance data transmission over plastic optical fibers (POF) using integrated optical receivers having good properties with multilevel modulation, i.e. a higher sensitivity and higher data rate transmission over a longer plastic optical fiber length. Integrated optical receivers and transmitters with high linearity are introduced for multilevel communication. For binary high-data rate transmission over plastic optical fibers, an innovative receiver containing an equalizer is described leading also to a high performance of a plastic optical fiber link. The cheap standard PMMA SI-POF (step-index plastic optical fiber) has the lowest bandwidth and the highest attenuation among multimode fibers. This small bandwidth limits the maximum data rate which can be transmitted through plastic optical fibers. To overcome the problem of the plastic optical fibers high transmission loss, very sensitive receivers must be used to increase the transmitted length over POF. The plastic optical fiber li...

  13. A digital-signal-processor-based optical tomographic system for dynamic imaging of joint diseases

    Science.gov (United States)

    Lasker, Joseph M.

    Over the last decade, optical tomography (OT) has emerged as viable biomedical imaging modality. Various imaging systems have been developed that are employed in preclinical as well as clinical studies, mostly targeting breast imaging, brain imaging, and cancer related studies. Of particular interest are so-called dynamic imaging studies where one attempts to image changes in optical properties and/or physiological parameters as they occur during a system perturbation. To successfully perform dynamic imaging studies, great effort is put towards system development that offers increasingly enhanced signal-to-noise performance at ever shorter data acquisition times, thus capturing high fidelity tomographic data within narrower time periods. Towards this goal, I have developed in this thesis a dynamic optical tomography system that is, unlike currently available analog instrumentation, based on digital data acquisition and filtering techniques. At the core of this instrument is a digital signal processor (DSP) that collects, collates, and processes the digitized data set. Complementary protocols between the DSP and a complex programmable logic device synchronizes the sampling process and organizes data flow. Instrument control is implemented through a comprehensive graphical user interface which integrates automated calibration, data acquisition, and signal post-processing. Real-time data is generated at frame rates as high as 140 Hz. An extensive dynamic range (˜190 dB) accommodates a wide scope of measurement geometries and tissue types. Performance analysis demonstrates very low system noise (˜1 pW rms noise equivalent power), excellent signal precision (˜0.04%--0.2%) and long term system stability (˜1% over 40 min). Experiments on tissue phantoms validate spatial and temporal accuracy of the system. As a potential new application of dynamic optical imaging I present the first application of this method to use vascular hemodynamics as a means of characterizing

  14. Optical pulse generation using fiber lasers and integrated optics

    International Nuclear Information System (INIS)

    Wilcox, R.B.; Browning, D.F.; Burkhart, S.C.; VanWonterghem, B.W.

    1995-01-01

    We have demonstrated an optical pulse forming system using fiber and integrated optics, and have designed a multiple-output system for a proposed fusion laser facility. Our approach is an advancement over previous designs for fusion lasers, and an unusual application of fiber lasers and integrated optics

  15. Integrating a Hypernymic Proposition Interpreter into a Semantic Processor for Biomedical Texts

    Science.gov (United States)

    Fiszman, Marcelo; Rindflesch, Thomas C.; Kilicoglu, Halil

    2003-01-01

    Semantic processing provides the potential for producing high quality results in natural language processing (NLP) applications in the biomedical domain. In this paper, we address a specific semantic phenomenon, the hypernymic proposition, and concentrate on integrating the interpretation of such predications into a more general semantic processor in order to improve overall accuracy. A preliminary evaluation assesses the contribution of hypernymic propositions in providing more specific semantic predications and thus improving effectiveness in retrieving treatment propositions in MEDLINE abstracts. Finally, we discuss the generalization of this methodology to additional semantic propositions as well as other types of biomedical texts. PMID:14728170

  16. Making CSB + -Trees Processor Conscious

    DEFF Research Database (Denmark)

    Samuel, Michael; Pedersen, Anders Uhl; Bonnet, Philippe

    2005-01-01

    of the CSB+-tree. We argue that it is necessary to consider a larger group of parameters in order to adapt CSB+-tree to processor architectures as different as Pentium and Itanium. We identify this group of parameters and study how it impacts the performance of CSB+-tree on Itanium 2. Finally, we propose......Cache-conscious indexes, such as CSB+-tree, are sensitive to the underlying processor architecture. In this paper, we focus on how to adapt the CSB+-tree so that it performs well on a range of different processor architectures. Previous work has focused on the impact of node size on the performance...... a systematic method for adapting CSB+-tree to new platforms. This work is a first step towards integrating CSB+-tree in MySQL’s heap storage manager....

  17. "Real-Time Optical Laboratory Linear Algebra Solution Of Partial Differential Equations"

    Science.gov (United States)

    Casasent, David; Jackson, James

    1986-03-01

    A Space Integrating (SI) Optical Linear Algebra Processor (OLAP) employing space and frequency-multiplexing, new partitioning and data flow, and achieving high accuracy performance with a non base-2 number system is described. Laboratory data on the performance of this system and the solution of parabolic Partial Differential Equations (PDEs) is provided. A multi-processor OLAP system is also described for the first time. It use in the solution of multiple banded matrices that frequently arise is then discussed. The utility and flexibility of this processor compared to digital systolic architectures should be apparent.

  18. Advanced optical manufacturing digital integrated system

    Science.gov (United States)

    Tao, Yizheng; Li, Xinglan; Li, Wei; Tang, Dingyong

    2012-10-01

    It is necessarily to adapt development of advanced optical manufacturing technology with modern science technology development. To solved these problems which low of ration, ratio of finished product, repetition, consistent in big size and high precision in advanced optical component manufacturing. Applied business driven and method of Rational Unified Process, this paper has researched advanced optical manufacturing process flow, requirement of Advanced Optical Manufacturing integrated System, and put forward architecture and key technology of it. Designed Optical component core and Manufacturing process driven of Advanced Optical Manufacturing Digital Integrated System. the result displayed effective well, realized dynamic planning Manufacturing process, information integration improved ratio of production manufactory.

  19. All-optically integrated photoacoustic and optical coherence tomography: A review

    Directory of Open Access Journals (Sweden)

    Wei Qiao

    2017-07-01

    Full Text Available All-optically integrated photoacoustic (PA and optical coherence tomography (OCT dual-mode imaging technology that could offer comprehensive pathological information for accurate diagnosis in clinic has gradually become a promising imaging technology in the aspect of biomedical imaging during the recent years. This review refers to the technology aspects of all-optical PA detection and system evolution of optically integrated PA and OCT, including Michelson interferometer dual-mode imaging system, Fabry–Perot (FP interferometer dual-mode imaging system and Mach–Zehnder interferometer dual-mode imaging system. It is believed that the optically integrated PA and OCT has great potential applications in biomedical imaging.

  20. Integrated Optical Circuit Engineering For Optical Fiber Gyrocopes

    Science.gov (United States)

    Bristow, Julian P.; We, Albert C.; Keur, M.; Lukas, Greg; Ott, Daniel M...; Sriram, S.

    1988-03-01

    Fiber optic gyroscopes are of interest for low-cost, high performance rotation sensors. Integrated optical implementations of the processing optics offer the hope of mass-production, and associated cost reductions. The development of a suitable integrated optical system has been reported by other authors at a wavelength of 850nm [1]. Despite strong technical advantages at 1.3μm wavelength [2], no results have yet appeared. This wavelength is preferred for telecommunications applications applications, thus significantly reduced fiber costs may be realized. Lithium niobate is relatively immune from the photorefractive effect at this wavelength, whereas it is not at at 850nm [3].

  1. Optical electronics self-organized integration and applications

    CERN Document Server

    Yoshimura, Tetsuzo

    2012-01-01

    IntroductionFrom Electronics to Optical ElectronicsAnalysis Tools for Optical CircuitsSelf-Organized Optical Waveguides: Theoretical AnalysisSelf-Organized Optical Waveguides: Experimental DemonstrationsOptical Waveguide Films with Vertical Mirrors 3-D Optical Circuits with Stacked Waveguide Films Heterogeneous Thin-Film Device IntegrationOptical Switches OE Hardware Built by Optical ElectronicsIntegrated Solar Energy Conversion SystemsFuture Challenges.

  2. Integrated optical 3D digital imaging based on DSP scheme

    Science.gov (United States)

    Wang, Xiaodong; Peng, Xiang; Gao, Bruce Z.

    2008-03-01

    We present a scheme of integrated optical 3-D digital imaging (IO3DI) based on digital signal processor (DSP), which can acquire range images independently without PC support. This scheme is based on a parallel hardware structure with aid of DSP and field programmable gate array (FPGA) to realize 3-D imaging. In this integrated scheme of 3-D imaging, the phase measurement profilometry is adopted. To realize the pipeline processing of the fringe projection, image acquisition and fringe pattern analysis, we present a multi-threads application program that is developed under the environment of DSP/BIOS RTOS (real-time operating system). Since RTOS provides a preemptive kernel and powerful configuration tool, with which we are able to achieve a real-time scheduling and synchronization. To accelerate automatic fringe analysis and phase unwrapping, we make use of the technique of software optimization. The proposed scheme can reach a performance of 39.5 f/s (frames per second), so it may well fit into real-time fringe-pattern analysis and can implement fast 3-D imaging. Experiment results are also presented to show the validity of proposed scheme.

  3. Catalyst development and systems analysis of methanol partial oxidation for the fuel processor - fuel cell integration

    Energy Technology Data Exchange (ETDEWEB)

    Newson, E; Mizsey, P; Hottinger, P; Truong, T B; Roth, F von; Schucan, Th H [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1999-08-01

    Methanol partial oxidation (pox) to produce hydrogen for mobile fuel cell applications has proved initially more successful than hydrocarbon pox. Recent results of catalyst screening and kinetic studies with methanol show that hydrogen production rates have reached 7000 litres/hour/(litre reactor volume) for the dry pox route and 12,000 litres/hour/(litre reactor volume) for wet pox. These rates are equivalent to 21 and 35 kW{sub th}/(litre reactor volume) respectively. The reaction engineering problems remain to be solved for dry pox due to the significant exotherm of the reaction (hot spots of 100-200{sup o}C), but wet pox is essentially isothermal in operation. Analyses of the integrated fuel processor - fuel cell systems show that two routes are available to satisfy the sensitivity of the fuel cell catalysts to carbon monoxide, i.e. a preferential oxidation reactor or a membrane separator. Targets for individual system components are evaluated for the base and best case systems for both routes to reach the combined 40% efficiency required for the integrated fuel processor - fuel cell system. (author) 2 figs., 1 tab., 3 refs.

  4. Dual-scale topology optoelectronic processor.

    Science.gov (United States)

    Marsden, G C; Krishnamoorthy, A V; Esener, S C; Lee, S H

    1991-12-15

    The dual-scale topology optoelectronic processor (D-STOP) is a parallel optoelectronic architecture for matrix algebraic processing. The architecture can be used for matrix-vector multiplication and two types of vector outer product. The computations are performed electronically, which allows multiplication and summation concepts in linear algebra to be generalized to various nonlinear or symbolic operations. This generalization permits the application of D-STOP to many computational problems. The architecture uses a minimum number of optical transmitters, which thereby reduces fabrication requirements while maintaining area-efficient electronics. The necessary optical interconnections are space invariant, minimizing space-bandwidth requirements.

  5. Alternative Water Processor Test Development

    Science.gov (United States)

    Pickering, Karen D.; Mitchell, Julie; Vega, Leticia; Adam, Niklas; Flynn, Michael; Wjee (er. Rau); Lunn, Griffin; Jackson, Andrew

    2012-01-01

    The Next Generation Life Support Project is developing an Alternative Water Processor (AWP) as a candidate water recovery system for long duration exploration missions. The AWP consists of biological water processor (BWP) integrated with a forward osmosis secondary treatment system (FOST). The basis of the BWP is a membrane aerated biological reactor (MABR), developed in concert with Texas Tech University. Bacteria located within the MABR metabolize organic material in wastewater, converting approximately 90% of the total organic carbon to carbon dioxide. In addition, bacteria convert a portion of the ammonia-nitrogen present in the wastewater to nitrogen gas, through a combination of nitrogen and denitrification. The effluent from the BWP system is low in organic contaminants, but high in total dissolved solids. The FOST system, integrated downstream of the BWP, removes dissolved solids through a combination of concentration-driven forward osmosis and pressure driven reverse osmosis. The integrated system is expected to produce water with a total organic carbon less than 50 mg/l and dissolved solids that meet potable water requirements for spaceflight. This paper describes the test definition, the design of the BWP and FOST subsystems, and plans for integrated testing.

  6. High-speed special-purpose processor for event selection by number of direct tracks

    International Nuclear Information System (INIS)

    Kalinnikov, V.A.; Krastev, V.R.; Chudakov, E.A.

    1986-01-01

    A processor which uses data on events from five detector planes is described. To increase economy and speed in parallel processing, the processor converts the input data to superposition code and recognizes tracks by a generated search mask. The resolving time of the processor is ≤300 nsec. The processor is CAMAC-compatible and uses ECL integrated circuits

  7. Quality assurance through constancy control for X-ray film processors

    International Nuclear Information System (INIS)

    Weberling, R.

    1982-01-01

    A control method to check the reproduction of X-ray film processors and necessary instruments is presented. The application of a light sensitometer allows the production of test films daily, independent of X-ray exposures, X-ray film cassettes and X-ray intensifying screens. The optical densities on the test films will be read by means of a densitometer and the results are plotted on a special control chart. A limitation through optical densities of +-0,15 for Speed Index and +-0,20 for Contrast Index determines the tolerance variation for X-ray film processors. Targets of this control method are uniform image quality, dose reduction and saving of cost. (orig.) [de

  8. Integrating optical, mechanical, and test software (with applications to freeform optics)

    Science.gov (United States)

    Genberg, Victor; Michels, Gregory; Myer, Brian

    2017-10-01

    Optical systems must perform under environmental conditions including thermal and mechanical loading. To predict the performance in the field, integrated analysis combining optical and mechanical software is required. Freeform and conformal optics offer many new opportunities for optical design. The unconventional geometries can lead to unconventional, and therefore unintuitive, mechanical behavior. Finite element (FE) analysis offers the ability to predict the deformations of freeform optics under various environments and load conditions. To understand the impact on optical performance, the deformations must be brought into optical analysis codes. This paper discusses several issues related to the integrated optomechanical analysis of freeform optics.

  9. All-optical SR flip-flop based on SOA-MZI switches monolithically integrated on a generic InP platform

    Science.gov (United States)

    Pitris, St.; Vagionas, Ch.; Kanellos, G. T.; Kisacik, R.; Tekin, T.; Broeke, R.; Pleros, N.

    2016-03-01

    At the dawning of the exaflop era, High Performance Computers are foreseen to exploit integrated all-optical elements, to overcome the speed limitations imposed by electronic counterparts. Drawing from the well-known Memory Wall limitation, imposing a performance gap between processor and memory speeds, research has focused on developing ultra-fast latching devices and all-optical memory elements capable of delivering buffering and switching functionalities at unprecedented bit-rates. Following the master-slave configuration of electronic Flip-Flops, coupled SOA-MZI based switches have been theoretically investigated to exceed 40 Gb/s operation, provided a short coupling waveguide. However, this flip-flop architecture has been only hybridly integrated with silica-on-silicon integration technology exhibiting a total footprint of 45x12 mm2 and intra-Flip-Flop coupling waveguide of 2.5cm, limited at 5 Gb/s operation. Monolithic integration offers the possibility to fabricate multiple active and passive photonic components on a single chip at a close proximity towards, bearing promises for fast all-optical memories. Here, we present for the first time a monolithically integrated all-optical SR Flip-Flop with coupled master-slave SOA-MZI switches. The photonic chip is integrated on a 6x2 mm2 die as a part of a multi-project wafer run using library based components of a generic InP platform, fiber-pigtailed and fully packaged on a temperature controlled ceramic submount module with electrical contacts. The intra Flip-Flop coupling waveguide is 5 mm long, reducing the total footprint by two orders of magnitude. Successful flip flop functionality is evaluated at 10 Gb/s with clear open eye diagram, achieving error free operation with a power penalty of 4dB.

  10. Recovery Act: Integrated DC-DC Conversion for Energy-Efficient Multicore Processors

    Energy Technology Data Exchange (ETDEWEB)

    Shepard, Kenneth L

    2013-03-31

    In this project, we have developed the use of thin-film magnetic materials to improve in energy efficiency of digital computing applications by enabling integrated dc-dc power conversion and management with on-chip power inductors. Integrated voltage regulators also enables fine-grained power management, by providing dynamic scaling of the supply voltage in concert with the clock frequency of synchronous logic to throttle power consumption at periods of low computational demand. The voltage converter generates lower output voltages during periods of low computational performance requirements and higher output voltages during periods of high computational performance requirements. Implementation of integrated power conversion requires high-capacity energy storage devices, which are generally not available in traditional semiconductor processes. We achieve this with integration of thin-film magnetic materials into a conventional complementary metal-oxide-semiconductor (CMOS) process for high-quality on-chip power inductors. This project includes a body of work conducted to develop integrated switch-mode voltage regulators with thin-film magnetic power inductors. Soft-magnetic materials and inductor topologies are selected and optimized, with intent to maximize efficiency and current density of the integrated regulators. A custom integrated circuit (IC) is designed and fabricated in 45-nm CMOS silicon-on-insulator (SOI) to provide the control system and power-train necessary to drive the power inductors, in addition to providing a digital load for the converter. A silicon interposer is designed and fabricated in collaboration with IBM Research to integrate custom power inductors by chip stacking with the 45-nm CMOS integrated circuit, enabling power conversion with current density greater than 10A/mm2. The concepts and designs developed from this work enable significant improvements in performance-per-watt of future microprocessors in servers, desktops, and mobile

  11. The microelectronic and photonic test bed RISC processor and DRAM memory stack experiments

    International Nuclear Information System (INIS)

    Clark, K.A.; Meehan, T.J.

    1999-01-01

    This paper reports on the on-orbit data obtained from the MPTB RISC Processor Experiment, containing three Integrated Device Technologies R3081 processors. During operations, nine SEUs were observed in the processors, and four SEUs were observed in the memory and/or support circuitry. (authors)

  12. Software-defined reconfigurable microwave photonics processor.

    Science.gov (United States)

    Pérez, Daniel; Gasulla, Ivana; Capmany, José

    2015-06-01

    We propose, for the first time to our knowledge, a software-defined reconfigurable microwave photonics signal processor architecture that can be integrated on a chip and is capable of performing all the main functionalities by suitable programming of its control signals. The basic configuration is presented and a thorough end-to-end design model derived that accounts for the performance of the overall processor taking into consideration the impact and interdependencies of both its photonic and RF parts. We demonstrate the model versatility by applying it to several relevant application examples.

  13. Advanced materials for integrated optical waveguides

    CERN Document Server

    Tong Ph D, Xingcun Colin

    2014-01-01

    This book provides a comprehensive introduction to integrated optical waveguides for information technology and data communications. Integrated coverage ranges from advanced materials, fabrication, and characterization techniques to guidelines for design and simulation. A concluding chapter offers perspectives on likely future trends and challenges. The dramatic scaling down of feature sizes has driven exponential improvements in semiconductor productivity and performance in the past several decades. However, with the potential of gigascale integration, size reduction is approaching a physical limitation due to the negative impact on resistance and inductance of metal interconnects with current copper-trace based technology. Integrated optics provides a potentially lower-cost, higher performance alternative to electronics in optical communication systems. Optical interconnects, in which light can be generated, guided, modulated, amplified, and detected, can provide greater bandwidth, lower power consumption, ...

  14. CMOS optical centroid processor for an integrated Shack-Hartmann wavefront sensor

    OpenAIRE

    Pui, Boon Hean

    2004-01-01

    A Shack Hartmann wavefront sensor is used to detect the distortion of light in an optical wavefront. It does this by sampling the wavefront with an array of lenslets and measuring the displacement of focused spots from reference positions. These displacements are linearly related to the local wavefront tilts from which the entire wavefront can be reconstructed. In most Shack Hartmann wavefront sensors, a CCD is used to sample the entire wavefront, typically at a rate of 25 to 60 Hz, and a who...

  15. A dedicated line-processor as used at the SHF

    International Nuclear Information System (INIS)

    Bevan, A.V.; Hatley, R.W.; Price, D.R.; Rankin, P.

    1985-01-01

    A hardwired trigger processor was used at the SLAC Hybrid Facility to find evidence for charged tracks originating from the fiducial volume of a 40'' rapidcycling bubble chamber. Straight-line projections of these tracks in the plane perpendicular to the applied magnetic field were searched for using data from three sets of proportional wire chambers (PWC). This information was made directly available to the processor by means of a special digitizing card. The results memory of the processor simulated read-only memory in a 168/E processor and was accessible by it. The 168/E controlled the issuing of a trigger command to the bubble chamber flash tubes. The same design of digitizer card used by the line processor was incorporated into the 168/E, again as read only memory, which allowed it access to the raw data for continual monitoring of trigger integrity. The design logic of the trigger processor was verified by running real PWC data through a FORTRAN simulation of the hardware. This enabled the debugging to become highly automated since a step by step, computer controlled comparison of processor registers to simulation predictions could be made

  16. An updated program-controlled analog processor, model AP-006, for semiconductor detector spectrometers

    International Nuclear Information System (INIS)

    Shkola, N.F.; Shevchenko, Yu.A.

    1989-01-01

    An analog processor, model AP-006, is reported. The processor is a development of a series of spectrometric units based on a shaper of the type 'DL dif +TVS+gated ideal integrator'. Structural and circuits design features are described. The results of testing the processor in a setup with a Si(Li) detecting unit over an input count-rate range of up to 5x10 5 cps are presented. Processor applications are illustrated. (orig.)

  17. A light hydrocarbon fuel processor producing high-purity hydrogen

    Science.gov (United States)

    Löffler, Daniel G.; Taylor, Kyle; Mason, Dylan

    This paper discusses the design process and presents performance data for a dual fuel (natural gas and LPG) fuel processor for PEM fuel cells delivering between 2 and 8 kW electric power in stationary applications. The fuel processor resulted from a series of design compromises made to address different design constraints. First, the product quality was selected; then, the unit operations needed to achieve that product quality were chosen from the pool of available technologies. Next, the specific equipment needed for each unit operation was selected. Finally, the unit operations were thermally integrated to achieve high thermal efficiency. Early in the design process, it was decided that the fuel processor would deliver high-purity hydrogen. Hydrogen can be separated from other gases by pressure-driven processes based on either selective adsorption or permeation. The pressure requirement made steam reforming (SR) the preferred reforming technology because it does not require compression of combustion air; therefore, steam reforming is more efficient in a high-pressure fuel processor than alternative technologies like autothermal reforming (ATR) or partial oxidation (POX), where the combustion occurs at the pressure of the process stream. A low-temperature pre-reformer reactor is needed upstream of a steam reformer to suppress coke formation; yet, low temperatures facilitate the formation of metal sulfides that deactivate the catalyst. For this reason, a desulfurization unit is needed upstream of the pre-reformer. Hydrogen separation was implemented using a palladium alloy membrane. Packed beds were chosen for the pre-reformer and reformer reactors primarily because of their low cost, relatively simple operation and low maintenance. Commercial, off-the-shelf balance of plant (BOP) components (pumps, valves, and heat exchangers) were used to integrate the unit operations. The fuel processor delivers up to 100 slm hydrogen >99.9% pure with <1 ppm CO, <3 ppm CO 2. The

  18. gFEX, the ATLAS Calorimeter Level-1 Real Time Processor

    CERN Document Server

    AUTHOR|(SzGeCERN)759889; The ATLAS collaboration; Begel, Michael; Chen, Hucheng; Lanni, Francesco; Takai, Helio; Wu, Weihao

    2016-01-01

    The global feature extractor (gFEX) is a component of the Level-1 Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Vertex Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 276 optical fibers with the data transferred at the 40 MHz Large Hadron Collider (LHC) clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor Field-Programmable Gate Array (FPGAs), monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA ...

  19. gFEX, the ATLAS Calorimeter Level 1 Real Time Processor

    CERN Document Server

    Tang, Shaochun; The ATLAS collaboration

    2015-01-01

    The global feature extractor (gFEX) is a component of the Level-1Calorimeter trigger Phase-I upgrade for the ATLAS experiment. It is intended to identify patterns of energy associated with the hadronic decays of high momentum Higgs, W, & Z bosons, top quarks, and exotic particles in real time at the LHC crossing rate. The single processor board will be packaged in an Advanced Telecommunications Computing Architecture (ATCA) module and implemented as a fast reconfigurable processor based on three Xilinx Ultra-scale FPGAs. The board will receive coarse-granularity information from all the ATLAS calorimeters on 264 optical fibers with the data transferred at the 40 MHz LHC clock frequency. The gFEX will be controlled by a single system-on-chip processor, ZYNQ, that will be used to configure all the processor FPGAs, monitor board health, and interface to external signals. Now, the pre-prototype board which includes one ZYNQ and one Vertex-7 FPGA has been designed for testing and verification. The performance ...

  20. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

  1. Automotive Fuel Processor Development and Demonstration with Fuel Cell Systems

    Energy Technology Data Exchange (ETDEWEB)

    Nuvera Fuel Cells

    2005-04-15

    The potential for fuel cell systems to improve energy efficiency and reduce emissions over conventional power systems has generated significant interest in fuel cell technologies. While fuel cells are being investigated for use in many applications such as stationary power generation and small portable devices, transportation applications present some unique challenges for fuel cell technology. Due to their lower operating temperature and non-brittle materials, most transportation work is focusing on fuel cells using proton exchange membrane (PEM) technology. Since PEM fuel cells are fueled by hydrogen, major obstacles to their widespread use are the lack of an available hydrogen fueling infrastructure and hydrogen's relatively low energy storage density, which leads to a much lower driving range than conventional vehicles. One potential solution to the hydrogen infrastructure and storage density issues is to convert a conventional fuel such as gasoline into hydrogen onboard the vehicle using a fuel processor. Figure 2 shows that gasoline stores roughly 7 times more energy per volume than pressurized hydrogen gas at 700 bar and 4 times more than liquid hydrogen. If integrated properly, the fuel processor/fuel cell system would also be more efficient than traditional engines and would give a fuel economy benefit while hydrogen storage and distribution issues are being investigated. Widespread implementation of fuel processor/fuel cell systems requires improvements in several aspects of the technology, including size, startup time, transient response time, and cost. In addition, the ability to operate on a number of hydrocarbon fuels that are available through the existing infrastructure is a key enabler for commercializing these systems. In this program, Nuvera Fuel Cells collaborated with the Department of Energy (DOE) to develop efficient, low-emission, multi-fuel processors for transportation applications. Nuvera's focus was on (1) developing fuel

  2. Control structures for high speed processors

    Science.gov (United States)

    Maki, G. K.; Mankin, R.; Owsley, P. A.; Kim, G. M.

    1982-01-01

    A special processor was designed to function as a Reed Solomon decoder with throughput data rate in the Mhz range. This data rate is significantly greater than is possible with conventional digital architectures. To achieve this rate, the processor design includes sequential, pipelined, distributed, and parallel processing. The processor was designed using a high level language register transfer language. The RTL can be used to describe how the different processes are implemented by the hardware. One problem of special interest was the development of dependent processes which are analogous to software subroutines. For greater flexibility, the RTL control structure was implemented in ROM. The special purpose hardware required approximately 1000 SSI and MSI components. The data rate throughput is 2.5 megabits/second. This data rate is achieved through the use of pipelined and distributed processing. This data rate can be compared with 800 kilobits/second in a recently proposed very large scale integration design of a Reed Solomon encoder.

  3. Optical technologies for data communication in large parallel systems

    International Nuclear Information System (INIS)

    Ritter, M B; Vlasov, Y; Kash, J A; Benner, A

    2011-01-01

    Large, parallel systems have greatly aided scientific computation and data collection, but performance scaling now relies on chip and system-level parallelism. This has happened because power density limits have caused processor frequency growth to stagnate, driving the new multi-core architecture paradigm, which would seem to provide generations of performance increases as transistors scale. However, this paradigm will be constrained by electrical I/O bandwidth limits; first off the processor card, then off the processor module itself. We will present best-estimates of these limits, then show how optical technologies can help provide more bandwidth to allow continued system scaling. We will describe the current status of optical transceiver technology which is already being used to exceed off-board electrical bandwidth limits, then present work on silicon nanophotonic transceivers and 3D integration technologies which, taken together, promise to allow further increases in off-module and off-card bandwidth. Finally, we will show estimated limits of nanophotonic links and discuss breakthroughs that are needed for further progress, and will speculate on whether we will reach Exascale-class machine performance at affordable powers.

  4. Optical technologies for data communication in large parallel systems

    Energy Technology Data Exchange (ETDEWEB)

    Ritter, M B; Vlasov, Y; Kash, J A [IBM T.J. Watson Research Center, Yorktown Heights, NY (United States); Benner, A, E-mail: mritter@us.ibm.com [IBM Poughkeepsie, Poughkeepsie, NY (United States)

    2011-01-15

    Large, parallel systems have greatly aided scientific computation and data collection, but performance scaling now relies on chip and system-level parallelism. This has happened because power density limits have caused processor frequency growth to stagnate, driving the new multi-core architecture paradigm, which would seem to provide generations of performance increases as transistors scale. However, this paradigm will be constrained by electrical I/O bandwidth limits; first off the processor card, then off the processor module itself. We will present best-estimates of these limits, then show how optical technologies can help provide more bandwidth to allow continued system scaling. We will describe the current status of optical transceiver technology which is already being used to exceed off-board electrical bandwidth limits, then present work on silicon nanophotonic transceivers and 3D integration technologies which, taken together, promise to allow further increases in off-module and off-card bandwidth. Finally, we will show estimated limits of nanophotonic links and discuss breakthroughs that are needed for further progress, and will speculate on whether we will reach Exascale-class machine performance at affordable powers.

  5. Fibre Optic Gyroscope Developments Using Integrated Optic Components

    Science.gov (United States)

    Minford, W. J.; DePaula, R. M.

    1988-09-01

    The sensing of rotation using counterpropagating optical beams in a fiber loop (the SAGNAC effect) has gone through extensive developments and demonstrations since first proved feasible by Vali and Shorthilll in 1976. The interferometric fiber gyroscope minimum configuration2 which uses a common input-output port and single-mode filter was developed to provide the extreme high stability necessary to reach the sensitivities at low rotation rates attainable with current state-of-the-art detectors. The simplicity and performance of this configuration has led to its acceptance and wide-spread use. In order to increase the mechanical stability of this system, all single-mode fiber components are employed and a further advancement to integrated optics has enabled most of the optical functions to be placed on a single mass-producible substrate. Recent improvements in the components (eg polarization maintaining fiber and low coherence sources) have further enhanced the performance of the minimum configuration gyro. This presentation focused on the impact of LiNbO3 integrated optic components on gyroscope developments. The use of Ti-indiffused LiNbO3 waveguide optical circuits in interferometric fiber optic gyroscopes has taken two directions: to utilize only the phase modulator, or to combine many of the minimum configuration optical functions on the electro-optic substrate. The high-bandwidth phase modulator is the driving force for using LiNbO3 waveguide devices. This device allows both biasing the gyro for maximum sensitivity and closing the loop via frequency shifting, for example, thus increasing the dynamic range of the gyro and the linearity of the scale factor. Efforts to implement most of the minimum configuration optical functions onto a single LiNbO3 substrate have been led by Thomson CSF.3 They have demonstrated an interferometric gyroscope with excellent performance using a LiNbO3 optical circuit containing a Y-splitter, phase modulator, and surface

  6. Digital control card based on digital signal processor

    International Nuclear Information System (INIS)

    Hou Shigang; Yin Zhiguo; Xia Le

    2008-01-01

    A digital control card based on digital signal processor was developed. Two Freescale DSP-56303 processors were utilized to achieve 3 channels proportional- integral-differential regulations. The card offers high flexibility for 100 MeV cyclotron RF system development. It was used as feedback controller in low level radio frequency control prototype, with the feedback gain parameters continuously adjustable. By using high precision analog to digital converter with 500 kHz sampling rate, a regulation bandwidth of 20 kHz was achieved. (authors)

  7. Coordinated Energy Management in Heterogeneous Processors

    Directory of Open Access Journals (Sweden)

    Indrani Paul

    2014-01-01

    Full Text Available This paper examines energy management in a heterogeneous processor consisting of an integrated CPU–GPU for high-performance computing (HPC applications. Energy management for HPC applications is challenged by their uncompromising performance requirements and complicated by the need for coordinating energy management across distinct core types – a new and less understood problem. We examine the intra-node CPU–GPU frequency sensitivity of HPC applications on tightly coupled CPU–GPU architectures as the first step in understanding power and performance optimization for a heterogeneous multi-node HPC system. The insights from this analysis form the basis of a coordinated energy management scheme, called DynaCo, for integrated CPU–GPU architectures. We implement DynaCo on a modern heterogeneous processor and compare its performance to a state-of-the-art power- and performance-management algorithm. DynaCo improves measured average energy-delay squared (ED2 product by up to 30% with less than 2% average performance loss across several exascale and other HPC workloads.

  8. All-Optical Network Subsystems Using Integrated SOA-Based Optical Gates and Flip-Flops for Label-Swapped Netorks

    DEFF Research Database (Denmark)

    Seoane, Jorge; Holm-Nielsen, Pablo Villanueva; Kehayas, E.

    2006-01-01

    In this letter, we demonstrate that all-optical network subsystems, offering intelligence in the optical layer, can be constructed by functional integration of integrated all-optical logic gates and flip-flops. In this context, we show 10-Gb/s all-optical 2-bit label address recognition......-level advantages of these all-optical subsystems combined with their realization with compact integrated devices, suggest that they are strong candidates for future packet/label switched optical networks....... by interconnecting two optical gates that perform xor operation on incoming optical labels. We also demonstrate 40-Gb/s all-optical wavelength-switching through an optically controlled wavelength converter, consisting of an integrated flip-flop prototype device driven by an integrated optical gate. The system...

  9. Onboard spectral imager data processor

    Science.gov (United States)

    Otten, Leonard J.; Meigs, Andrew D.; Franklin, Abraham J.; Sears, Robert D.; Robison, Mark W.; Rafert, J. Bruce; Fronterhouse, Donald C.; Grotbeck, Ronald L.

    1999-10-01

    Previous papers have described the concept behind the MightySat II.1 program, the satellite's Fourier Transform imaging spectrometer's optical design, the design for the spectral imaging payload, and its initial qualification testing. This paper discusses the on board data processing designed to reduce the amount of downloaded data by an order of magnitude and provide a demonstration of a smart spaceborne spectral imaging sensor. Two custom components, a spectral imager interface 6U VME card that moves data at over 30 MByte/sec, and four TI C-40 processors mounted to a second 6U VME and daughter card, are used to adapt the sensor to the spacecraft and provide the necessary high speed processing. A system architecture that offers both on board real time image processing and high-speed post data collection analysis of the spectral data has been developed. In addition to the on board processing of the raw data into a usable spectral data volume, one feature extraction technique has been incorporated. This algorithm operates on the basic interferometric data. The algorithm is integrated within the data compression process to search for uploadable feature descriptions.

  10. Glass-based integrated optical splitters: engineering oriented research

    Science.gov (United States)

    Hao, Yinlei; Zheng, Weiwei; Yang, Jianyi; Jiang, Xiaoqing; Wang, Minghua

    2010-10-01

    Optical splitter is one of most typical device heavily demanded in implementation of Fiber To The Home (FTTH) system. Due to its compatibility with optical fibers, low propagation loss, flexibility, and most distinguishingly, potentially costeffectiveness, glass-based integrated optical splitters made by ion-exchange technology promise to be very attractive in application of optical communication networks. Aiming at integrated optical splitters applied in optical communication network, glass ion-exchange waveguide process is developed, which includes two steps: thermal salts ion-exchange and field-assisted ion-diffusion. By this process, high performance optical splitters are fabricated in specially melted glass substrate. Main performance parameters of these splitters, including maximum insertion loss (IL), polarization dependence loss (PDL), and IL uniformity are all in accordance with corresponding specifications in generic requirements for optic branching components (GR-1209-CORE). In this paper, glass based integrated optical splitters manufacturing is demonstrated, after which, engineering-oriented research work results on glass-based optical splitter are presented.

  11. Monolithically integrated quantum dot optical modulator with Semiconductor optical amplifier for short-range optical communications

    Science.gov (United States)

    Yamamoto, Naokatsu; Akahane, Kouichi; Umezawa, Toshimasa; Kawanishi, Tetsuya

    2015-04-01

    A monolithically integrated quantum dot (QD) optical gain modulator (OGM) with a QD semiconductor optical amplifier (SOA) was successfully developed. Broadband QD optical gain material was used to achieve Gbps-order high-speed optical data transmission, and an optical gain change as high as approximately 6-7 dB was obtained with a low OGM voltage of 2.0 V. Loss of optical power due to insertion of the device was also effectively compensated for by the SOA section. Furthermore, it was confirmed that the QD-OGM/SOA device helped achieve 6.0-Gbps error-free optical data transmission over a 2.0-km-long photonic crystal fiber. We also successfully demonstrated generation of Gbps-order, high-speed, and error-free optical signals in the >5.5-THz broadband optical frequency bandwidth larger than the C-band. These results suggest that the developed monolithically integrated QD-OGM/SOA device will be an advantageous and compact means of increasing the usable optical frequency channels for short-reach communications.

  12. Interferometric interrogation concepts for integrated electro-optical sensor systems

    NARCIS (Netherlands)

    Ikkink, T.J.; Ikkink, Teunis Jan

    1998-01-01

    Integrated optical sensors have a high potential in the measurement of a large variety of measurands. Research on integrated optical sensors enjoys increasing interest. In order to reach accurate performance and to facilitate the use of integrated optical sensors, electronic functions for sensor

  13. Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

    Directory of Open Access Journals (Sweden)

    Cheng Chuantong

    2017-07-01

    Full Text Available Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

  14. Monolithic optoelectronic integrated broadband optical receiver with graphene photodetectors

    Science.gov (United States)

    Cheng, Chuantong; Huang, Beiju; Mao, Xurui; Zhang, Zanyun; Zhang, Zan; Geng, Zhaoxin; Xue, Ping; Chen, Hongda

    2017-07-01

    Optical receivers with potentially high operation bandwidth and low cost have received considerable interest due to rapidly growing data traffic and potential Tb/s optical interconnect requirements. Experimental realization of 65 GHz optical signal detection and 262 GHz intrinsic operation speed reveals the significance role of graphene photodetectors (PDs) in optical interconnect domains. In this work, a novel complementary metal oxide semiconductor post-backend process has been developed for integrating graphene PDs onto silicon integrated circuit chips. A prototype monolithic optoelectronic integrated optical receiver has been successfully demonstrated for the first time. Moreover, this is a firstly reported broadband optical receiver benefiting from natural broadband light absorption features of graphene material. This work is a perfect exhibition of the concept of monolithic optoelectronic integration and will pave way to monolithically integrated graphene optoelectronic devices with silicon ICs for three-dimensional optoelectronic integrated circuit chips.

  15. Framework Programmable Platform for the advanced software development workstation: Framework processor design document

    Science.gov (United States)

    Mayer, Richard J.; Blinn, Thomas M.; Mayer, Paula S. D.; Ackley, Keith A.; Crump, Wes; Sanders, Les

    1991-01-01

    The design of the Framework Processor (FP) component of the Framework Programmable Software Development Platform (FFP) is described. The FFP is a project aimed at combining effective tool and data integration mechanisms with a model of the software development process in an intelligent integrated software development environment. Guided by the model, this Framework Processor will take advantage of an integrated operating environment to provide automated support for the management and control of the software development process so that costly mistakes during the development phase can be eliminated.

  16. A multi-ring optical packet and circuit integrated network with optical buffering.

    Science.gov (United States)

    Furukawa, Hideaki; Shinada, Satoshi; Miyazawa, Takaya; Harai, Hiroaki; Kawasaki, Wataru; Saito, Tatsuhiko; Matsunaga, Koji; Toyozumi, Tatuya; Wada, Naoya

    2012-12-17

    We newly developed a 3 × 3 integrated optical packet and circuit switch-node. Optical buffers and burst-mode erbium-doped fiber amplifiers with the gain flatness are installed in the 3 × 3 switch-node. The optical buffer can prevent packet collisions and decrease packet loss. We constructed a multi-ring optical packet and circuit integrated network testbed connecting two single-ring networks and a client network by the 3 × 3 switch-node. For the first time, we demonstrated 244 km fiber transmission and 5-node hopping of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10 Gigabit Ethernet frames on the testbed. Error-free (frame error rate optical packets of various packet lengths. In addition, successful avoidance of packet collisions by optical buffers was confirmed.

  17. Integrated optical circuit comprising a polarization convertor

    NARCIS (Netherlands)

    1998-01-01

    An integrated optical circuit includes a first device and a second device, which devices are connected by a polarization convertor. The polarization convertor includes a curved section of a waveguide, integrated in the optical circuit. The curved section may have several differently curved

  18. All-optical temporal integration of ultrafast pulse waveforms.

    Science.gov (United States)

    Park, Yongwoo; Ahn, Tae-Jung; Dai, Yitang; Yao, Jianping; Azaña, José

    2008-10-27

    An ultrafast all-optical temporal integrator is experimentally demonstrated. The demonstrated integrator is based on a very simple and practical solution only requiring the use of a widely available all-fiber passive component, namely a reflection uniform fiber Bragg grating (FBG). This design allows overcoming the severe speed (bandwidth) limitations of the previously demonstrated photonic integrator designs. We demonstrate temporal integration of a variety of ultrafast optical waveforms, including Gaussian, odd-symmetry Hermite Gaussian, and (odd-)symmetry double pulses, with temporal features as fast as ~6-ps, which is about one order of magnitude faster than in previous photonic integration demonstrations. The developed device is potentially interesting for a multitude of applications in all-optical computing and information processing, ultrahigh-speed optical communications, ultrafast pulse (de-)coding, shaping and metrology.

  19. Energy challenges in optical access and aggregation networks.

    Science.gov (United States)

    Kilper, Daniel C; Rastegarfar, Houman

    2016-03-06

    Scalability is a critical issue for access and aggregation networks as they must support the growth in both the size of data capacity demands and the multiplicity of access points. The number of connected devices, the Internet of Things, is growing to the tens of billions. Prevailing communication paradigms are reaching physical limitations that make continued growth problematic. Challenges are emerging in electronic and optical systems and energy increasingly plays a central role. With the spectral efficiency of optical systems approaching the Shannon limit, increasing parallelism is required to support higher capacities. For electronic systems, as the density and speed increases, the total system energy, thermal density and energy per bit are moving into regimes that become impractical to support-for example requiring single-chip processor powers above the 100 W limit common today. We examine communication network scaling and energy use from the Internet core down to the computer processor core and consider implications for optical networks. Optical switching in data centres is identified as a potential model from which scalable access and aggregation networks for the future Internet, with the application of integrated photonic devices and intelligent hybrid networking, will emerge. © 2016 The Author(s).

  20. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Directory of Open Access Journals (Sweden)

    Heck Martijn J.R.

    2016-06-01

    Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  1. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Science.gov (United States)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  2. Design and development of a diesel and JP-8 logistic fuel processor

    Science.gov (United States)

    Roychoudhury, Subir; Lyubovsky, Maxim; Walsh, D.; Chu, Deryn; Kallio, Erik

    The paper describes the design and performance of a breadboard prototype for a 5 kW fuel-processor for powering a solid oxide fuel cell (SOFC) stack. The system was based on a small, modular catalytic Microlith auto-thermal (ATR) reactor with the versatility of operating on diesel, Jet-A or JP-8 fuels. The reforming reactor utilized Microlith substrates and catalyst technology (patented and trademarked). These reactors have demonstrated the capability of efficiently reforming liquid and gaseous hydrocarbon fuels at exceptionally high power densities. The performance characteristics of the auto-thermal reactor (ATR) have been presented along with durability data. The fuel processor integrates fuel preparation, steam generation, sulfur removal, pumps, blowers and controls. The system design was developed via ASPEN ® Engineering Suite process simulation software and was analyzed with reference to system balance requirements. Since the fuel processor has not been integrated with a fuel cell, aspects of thermal integration with the stack have not been specifically addressed.

  3. Evaluation of the Intel Nehalem-EX server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by the CERN openlab by comparing the 4-socket, 32-core Intel Xeon X7560 server with the previous generation 4-socket server, based on the Xeon X7460 processor. The Xeon X7560 processor represents a major change in many respects, especially the memory sub-system, so it was important to make multiple comparisons. In most benchmarks the two 4-socket servers were compared. It should be underlined that both servers represent the “top of the line” in terms of frequency. However, in some cases, it was important to compare systems that integrated the latest processor features, such as QPI links, Symmetric multithreading and over-clocking via Turbo mode, and in such situations the X7560 server was compared to a dual socket L5520 based system with an identical frequency of 2.26 GHz. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following ...

  4. A single chip pulse processor for nuclear spectroscopy

    International Nuclear Information System (INIS)

    Hilsenrath, F.; Bakke, J.C.; Voss, H.D.

    1985-01-01

    A high performance digital pulse processor, integrated into a single gate array microcircuit, has been developed for spaceflight applications. The new approach takes advantage of the latest CMOS high speed A/D flash converters and low-power gated logic arrays. The pulse processor measures pulse height, pulse area and the required timing information (e.g. multi detector coincidence and pulse pile-up detection). The pulse processor features high throughput rate (e.g. 0.5 Mhz for 2 usec gausssian pulses) and improved differential linearity (e.g. + or - 0.2 LSB for a + or - 1 LSB A/D). Because of the parallel digital architecture of the device, the interface is microprocessor bus compatible. A satellite flight application of this module is presented for use in the X-ray imager and high energy particle spectrometers of the PEM experiment on the Upper Atmospheric Research Satellite

  5. Array processor architecture

    Science.gov (United States)

    Barnes, George H. (Inventor); Lundstrom, Stephen F. (Inventor); Shafer, Philip E. (Inventor)

    1983-01-01

    A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

  6. Interleaved Subtask Scheduling on Multi Processor SOC

    NARCIS (Netherlands)

    Zhe, M.

    2006-01-01

    The ever-progressing semiconductor processing technique has integrated more and more embedded processors on a single system-on-achip (SoC). With such powerful SoC platforms, and also due to the stringent time-to-market deadlines, many functionalities which used to be implemented in ASICs are

  7. NeuroFlow: A General Purpose Spiking Neural Network Simulation Platform using Customizable Processors.

    Science.gov (United States)

    Cheung, Kit; Schultz, Simon R; Luk, Wayne

    2015-01-01

    NeuroFlow is a scalable spiking neural network simulation platform for off-the-shelf high performance computing systems using customizable hardware processors such as Field-Programmable Gate Arrays (FPGAs). Unlike multi-core processors and application-specific integrated circuits, the processor architecture of NeuroFlow can be redesigned and reconfigured to suit a particular simulation to deliver optimized performance, such as the degree of parallelism to employ. The compilation process supports using PyNN, a simulator-independent neural network description language, to configure the processor. NeuroFlow supports a number of commonly used current or conductance based neuronal models such as integrate-and-fire and Izhikevich models, and the spike-timing-dependent plasticity (STDP) rule for learning. A 6-FPGA system can simulate a network of up to ~600,000 neurons and can achieve a real-time performance of 400,000 neurons. Using one FPGA, NeuroFlow delivers a speedup of up to 33.6 times the speed of an 8-core processor, or 2.83 times the speed of GPU-based platforms. With high flexibility and throughput, NeuroFlow provides a viable environment for large-scale neural network simulation.

  8. Probabilistic programmable quantum processors

    International Nuclear Information System (INIS)

    Buzek, V.; Ziman, M.; Hillery, M.

    2004-01-01

    We analyze how to improve performance of probabilistic programmable quantum processors. We show how the probability of success of the probabilistic processor can be enhanced by using the processor in loops. In addition, we show that an arbitrary SU(2) transformations of qubits can be encoded in program state of a universal programmable probabilistic quantum processor. The probability of success of this processor can be enhanced by a systematic correction of errors via conditional loops. Finally, we show that all our results can be generalized also for qudits. (Abstract Copyright [2004], Wiley Periodicals, Inc.)

  9. Architecture-Aware Optimization of an HEVC decoder on Asymmetric Multicore Processors

    OpenAIRE

    Rodríguez-Sánchez, Rafael; Quintana-Ortí, Enrique S.

    2016-01-01

    Low-power asymmetric multicore processors (AMPs) attract considerable attention due to their appealing performance-power ratio for energy-constrained environments. However, these processors pose a significant programming challenge due to the integration of cores with different performance capabilities, asking for an asymmetry-aware scheduling solution that carefully distributes the workload. The recent HEVC standard, which offers several high-level parallelization strategies, is an important ...

  10. Development of an integrated filing system for endoscopic images.

    Science.gov (United States)

    Fujino, M A; Ikeda, M; Yamamoto, Y; Kinose, T; Tachikawa, H; Morozumi, A; Sano, S; Kojima, Y; Nakamura, T; Kawai, T

    1991-01-01

    A new integrated filing system for endoscopic images has been developed, comprising a main image filing system and subsystems located at different stations. A hybrid filing system made up of both digital and analog filing devices was introduced to construct this system that combines the merits of the two filing methods. Each subsystem provided with a video processor, is equipped with a digital filing device, and routine images were recorded in the analog image filing device of the main system. The use of a multi-input adapter enabled simultaneous input of analog images from up to 8 video processors. Recorded magneto-optical disks make it possible to recall the digital images at any station in the hospital; the disks are copied without image degradation and also utilised for image processing. This system promises reliable storage and integrated, efficient management of endoscopic information. It also costs less to install than the so-called PACS (picture archiving and communication system), which connects all the stations of the hospital using optical fiber cables.

  11. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    OpenAIRE

    Abdul Kareem PARCHUR; Ram Asaray SINGH

    2012-01-01

    High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310). The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many ke...

  12. The LASS hardware processor

    International Nuclear Information System (INIS)

    Kunz, P.F.

    1976-01-01

    The problems of data analysis with hardware processors are reviewed and a description is given of a programmable processor. This processor, the 168/E, has been designed for use in the LASS multi-processor system; it has an execution speed comparable to the IBM 370/168 and uses the subset of IBM 370 instructions appropriate to the LASS analysis task. (Auth.)

  13. Theory of absorption integrated optical sensor of gaseous materials

    Science.gov (United States)

    Egorov, A. A.

    2010-10-01

    The eigen and noneigen (leaky) modes of a three-layer planar integrated optical waveguide are described. The dispersion relation of a three-layer planar waveguide and other dependences are derived, and the cutoff conditions are analyzed. The diagram of propagation constants of the guided and radiation modes of an irregular asymmetric three-layer waveguide and the dependence of the electric field amplitudes of radiation modes of substrate on vertical coordinate in a tantalum integrated optical waveguide are presented. The operating principles of an absorption integrated optical waveguide sensor are investigated. The dependences of sensitivity of an integrated optical waveguide sensor on the sensory cell length, the coupling efficiency of the laser radiation into the waveguide, the absorption cross-section of the studied material, and the level of additive statistical noise are investigated. Some of the prospective areas of application of integrated-optical waveguide sensors are outlined.

  14. Automated target recognition and tracking using an optical pattern recognition neural network

    Science.gov (United States)

    Chao, Tien-Hsin

    1991-01-01

    The on-going development of an automatic target recognition and tracking system at the Jet Propulsion Laboratory is presented. This system is an optical pattern recognition neural network (OPRNN) that is an integration of an innovative optical parallel processor and a feature extraction based neural net training algorithm. The parallel optical processor provides high speed and vast parallelism as well as full shift invariance. The neural network algorithm enables simultaneous discrimination of multiple noisy targets in spite of their scales, rotations, perspectives, and various deformations. This fully developed OPRNN system can be effectively utilized for the automated spacecraft recognition and tracking that will lead to success in the Automated Rendezvous and Capture (AR&C) of the unmanned Cargo Transfer Vehicle (CTV). One of the most powerful optical parallel processors for automatic target recognition is the multichannel correlator. With the inherent advantages of parallel processing capability and shift invariance, multiple objects can be simultaneously recognized and tracked using this multichannel correlator. This target tracking capability can be greatly enhanced by utilizing a powerful feature extraction based neural network training algorithm such as the neocognitron. The OPRNN, currently under investigation at JPL, is constructed with an optical multichannel correlator where holographic filters have been prepared using the neocognitron training algorithm. The computation speed of the neocognitron-type OPRNN is up to 10(exp 14) analog connections/sec that enabling the OPRNN to outperform its state-of-the-art electronics counterpart by at least two orders of magnitude.

  15. An Integrated Approach to Locality-Conscious Processor Allocation and Scheduling of Mixed-Parallel Applications

    Energy Technology Data Exchange (ETDEWEB)

    Vydyanathan, Naga; Krishnamoorthy, Sriram; Sabin, Gerald M.; Catalyurek, Umit V.; Kurc, Tahsin; Sadayappan, Ponnuswamy; Saltz, Joel H.

    2009-08-01

    Complex parallel applications can often be modeled as directed acyclic graphs of coarse-grained application-tasks with dependences. These applications exhibit both task- and data-parallelism, and combining these two (also called mixedparallelism), has been shown to be an effective model for their execution. In this paper, we present an algorithm to compute the appropriate mix of task- and data-parallelism required to minimize the parallel completion time (makespan) of these applications. In other words, our algorithm determines the set of tasks that should be run concurrently and the number of processors to be allocated to each task. The processor allocation and scheduling decisions are made in an integrated manner and are based on several factors such as the structure of the taskgraph, the runtime estimates and scalability characteristics of the tasks and the inter-task data communication volumes. A locality conscious scheduling strategy is used to improve inter-task data reuse. Evaluation through simulations and actual executions of task graphs derived from real applications as well as synthetic graphs shows that our algorithm consistently generates schedules with lower makespan as compared to CPR and CPA, two previously proposed scheduling algorithms. Our algorithm also produces schedules that have lower makespan than pure taskand data-parallel schedules. For task graphs with known optimal schedules or lower bounds on the makespan, our algorithm generates schedules that are closer to the optima than other scheduling approaches.

  16. Integrated Optical Interconnect Architectures for Embedded Systems

    CERN Document Server

    Nicolescu, Gabriela

    2013-01-01

    This book provides a broad overview of current research in optical interconnect technologies and architectures. Introductory chapters on high-performance computing and the associated issues in conventional interconnect architectures, and on the fundamental building blocks for integrated optical interconnect, provide the foundations for the bulk of the book which brings together leading experts in the field of optical interconnect architectures for data communication. Particular emphasis is given to the ways in which the photonic components are assembled into architectures to address the needs of data-intensive on-chip communication, and to the performance evaluation of such architectures for specific applications.   Provides state-of-the-art research on the use of optical interconnects in Embedded Systems; Begins with coverage of the basics for high-performance computing and optical interconnect; Includes a variety of on-chip optical communication topologies; Features coverage of system integration and opti...

  17. Color sensor and neural processor on one chip

    Science.gov (United States)

    Fiesler, Emile; Campbell, Shannon R.; Kempem, Lother; Duong, Tuan A.

    1998-10-01

    Low-cost, compact, and robust color sensor that can operate in real-time under various environmental conditions can benefit many applications, including quality control, chemical sensing, food production, medical diagnostics, energy conservation, monitoring of hazardous waste, and recycling. Unfortunately, existing color sensor are either bulky and expensive or do not provide the required speed and accuracy. In this publication we describe the design of an accurate real-time color classification sensor, together with preprocessing and a subsequent neural network processor integrated on a single complementary metal oxide semiconductor (CMOS) integrated circuit. This one-chip sensor and information processor will be low in cost, robust, and mass-producible using standard commercial CMOS processes. The performance of the chip and the feasibility of its manufacturing is proven through computer simulations based on CMOS hardware parameters. Comparisons with competing methodologies show a significantly higher performance for our device.

  18. The hardware track finder processor in CMS at CERN

    CERN Document Server

    Kluge, A

    1997-01-01

    The work covers the design of the Track Finder Processor in the high energy experiment CMS (Compact Muon Solenoid, planned for 2005) at CERN/Geneva. The task of this processor is to identify muons and measure their transverse momentum. The track finder processor makes it possible to determine the physical relevance of each high energetic collision and to forward only interesting data to the data an alysis units. Data of more than two hundred thousand detector cells are used to determine the location of muons and measure their transverse momentum. Each 25 ns a new data set is generated. Measurem ent of location and transverse momentum of the muons can be terminated within 350 ns by using an ASIC (Application Specific Integrated Circuit). A pipeline architecture processes new data sets with th e required data rate of 40 MHz to ensure dead time free operation. In the framework of this study specifications and the overall concept of the track finder processor were worked out in detail. Simul ations were performed...

  19. Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

    Science.gov (United States)

    Lindgren, R. W.; Tarbell, T. D.

    1981-01-01

    The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

  20. Performing derivative and integral operations for optical waves with optical metamaterials

    Energy Technology Data Exchange (ETDEWEB)

    Dai, Cun-Li [College of Engineering, Nanjing Agriculture University, Nanjing Jiangsu, 210031 (China); College of Science, Nanjing Agriculture University, Nanjing Jiangsu, 210095 (China); Zhao, Zhi-Gang; Li, Xiao-Lin [College of Engineering, Nanjing Agriculture University, Nanjing Jiangsu, 210031 (China); Yang, Hong-Wei, E-mail: phd_hwyang@njau.edu.cn [College of Science, Nanjing Agriculture University, Nanjing Jiangsu, 210095 (China)

    2016-12-01

    The graded refractive index waveguides can perform Fourier transform for an optical wave. According to this characteristic, simpler optical metamaterials with three waveguides are theoretically proposed, in which all of the waveguides are materials with a positive refractive index. By selecting the appropriate refractive index and structure size, the theory and simulations demonstrated that these metamaterials can perform mathematical operations for the outline of incident optical waves, including the first-order derivative, second-order derivative and the integral. - Highlights: • The derivative and integral operations of optical waves are achieved with a simpler model. • Both negative and positive refractive index boast the same functions. • The mathematical operations can be implemented only by changing the refractive index of the intermediate material. • The results will greatly expand the possible applications, including photon computers, picture processing, video displays and data storage.

  1. Comparison of Processor Performance of SPECint2006 Benchmarks of some Intel Xeon Processors

    Directory of Open Access Journals (Sweden)

    Abdul Kareem PARCHUR

    2012-08-01

    Full Text Available High performance is a critical requirement to all microprocessors manufacturers. The present paper describes the comparison of performance in two main Intel Xeon series processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310. The microarchitecture of these processors is implemented using the basis of a new family of processors from Intel starting with the Pentium 4 processor. These processors can provide a performance boost for many key application areas in modern generation. The scaling of performance in two major series of Intel Xeon processors (Type A: Intel Xeon X5260, X5460, E5450 and L5320 and Type B: Intel Xeon X5140, 5130, 5120 and E5310 has been analyzed using the performance numbers of 12 CPU2006 integer benchmarks, performance numbers that exhibit significant differences in performance. The results and analysis can be used by performance engineers, scientists and developers to better understand the performance scaling in modern generation processors.

  2. Simulation of a parallel processor on a serial processor: The neutron diffusion equation

    International Nuclear Information System (INIS)

    Honeck, H.C.

    1981-01-01

    Parallel processors could provide the nuclear industry with very high computing power at a very moderate cost. Will we be able to make effective use of this power. This paper explores the use of a very simple parallel processor for solving the neutron diffusion equation to predict power distributions in a nuclear reactor. We first describe a simple parallel processor and estimate its theoretical performance based on the current hardware technology. Next, we show how the parallel processor could be used to solve the neutron diffusion equation. We then present the results of some simulations of a parallel processor run on a serial processor and measure some of the expected inefficiencies. Finally we extrapolate the results to estimate how actual design codes would perform. We find that the standard numerical methods for solving the neutron diffusion equation are still applicable when used on a parallel processor. However, some simple modifications to these methods will be necessary if we are to achieve the full power of these new computers. (orig.) [de

  3. Integrated Optical lightguide device

    NARCIS (Netherlands)

    Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

    2005-01-01

    In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

  4. Integrated Optical lightguide device

    NARCIS (Netherlands)

    Heideman, Rene; Lambeck, Paul; Veldhuis, G.J.

    2000-01-01

    In an integrated optical lightguide device including a light-transmitting core layer, an inclusion or buffer layer, and an active or cladding layer. The cladding layer is divided into segments. Groups of different segments exhibit different refractive indices, light intensity profiles or different

  5. Editorial European conference on integrated optics (ECIO'10)

    NARCIS (Netherlands)

    Williams, K.A.

    2011-01-01

    This Special Issue contains a selection of extended papers from the Fifteenth European Conference on Integrated Optics held on 7-9 April 2010. The First European Conference on Integrated Optics in the series was held in London, UK thirty years ago, and the conference has been held biannually across

  6. Functional unit for a processor

    NARCIS (Netherlands)

    Rohani, A.; Kerkhoff, Hans G.

    2013-01-01

    The invention relates to a functional unit for a processor, such as a Very Large Instruction Word Processor. The invention further relates to a processor comprising at least one such functional unit. The invention further relates to a functional unit and processor capable of mitigating the effect of

  7. Trigger and decision processors

    International Nuclear Information System (INIS)

    Franke, G.

    1980-11-01

    In recent years there have been many attempts in high energy physics to make trigger and decision processes faster and more sophisticated. This became necessary due to a permanent increase of the number of sensitive detector elements in wire chambers and calorimeters, and in fact it was possible because of the fast developments in integrated circuits technique. In this paper the present situation will be reviewed. The discussion will be mainly focussed upon event filtering by pure software methods and - rather hardware related - microprogrammable processors as well as random access memory triggers. (orig.)

  8. Development of a Next-Generation Membrane-Integrated Adsorption Processor for CO2 Removal and Compression for Closed-Loop Air Revitalization Systems

    Science.gov (United States)

    Mulloth, Lila; LeVan, Douglas

    2002-01-01

    The current CO2 removal technology of NASA is very energy intensive and contains many non-optimized subsystems. This paper discusses the concept of a next-generation, membrane integrated, adsorption processor for CO2 removal nd compression in closed-loop air revitalization systems. This processor will use many times less power than NASA's current CO2 removal technology and will be capable of maintaining a lower CO2 concentration in the cabin than that can be achieved by the existing CO2 removal systems. The compact, consolidated, configuration of gas dryer, CO2 separator, and CO2 compressor will allow continuous recycling of humid air in the cabin and supply of compressed CO2 to the reduction unit for oxygen recovery. The device has potential application to the International Space Station and future, long duration, transit, and planetary missions.

  9. Accuracy in Optical Information Processing

    Science.gov (United States)

    Timucin, Dogan Aslan

    Low computational accuracy is an important obstacle for optical processors which blocks their way to becoming a practical reality and a serious challenger for classical computing paradigms. This research presents a comprehensive solution approach to the problem of accuracy enhancement in discrete analog optical information processing systems. Statistical analysis of a generic three-plane optical processor is carried out first, taking into account the effects of diffraction, interchannel crosstalk, and background radiation. Noise sources included in the analysis are photon, excitation, and emission fluctuations in the source array, transmission and polarization fluctuations in the modulator, and photoelectron, gain, dark, shot, and thermal noise in the detector array. Means and mutual coherence and probability density functions are derived for both optical and electrical output signals. Next, statistical models for a number of popular optoelectronic devices are studied. Specific devices considered here are light-emitting and laser diode sources, an ideal noiseless modulator and a Gaussian random-amplitude-transmittance modulator, p-i-n and avalanche photodiode detectors followed by electronic postprocessing, and ideal free-space geometrical -optics propagation and single-lens imaging systems. Output signal statistics are determined for various interesting device combinations by inserting these models into the general formalism. Finally, based on these special-case output statistics, results on accuracy limitations and enhancement in optical processors are presented. Here, starting with the formulation of the accuracy enhancement problem as (1) an optimal detection problem and (2) as a parameter estimation problem, the potential accuracy improvements achievable via the classical multiple-hypothesis -testing and maximum likelihood and Bayesian parameter estimation methods are demonstrated. Merits of using proper normalizing transforms which can potentially stabilize

  10. Study on the management of the Boohung X-Dol 90 developer and fixing solution for automatic X-ray film processor

    International Nuclear Information System (INIS)

    Hyan, Yong Sil; Kim, Heung Tae; Kwon, Dal Gwan; Choi, Myung Joon; Cheung, Hwan

    1986-01-01

    Recently, Demands of Automatic X-ray film Processors are increasing more and more at University Hospitals and general Hospitals and Private clinics, but various troubles because of incorrect control were found out. Authors have researched to find out the function and Activity of Automatic X-ray film processor for 2 weeks Kodak RPX-OMAT Processor and Sakura GX3000 Processor and Doosan parka 2000 Processor and results obtained were as follows: 1. Automatic X-ray film processor have an advantage to conduct the rapid treatment of X-ray film processing but incorrect handling of developing and fixing agents were brought about a great change in Contrast and Optical density of X-ray film pictures. 2. About 300 X-ray film could be finished by same developing and fixing solution without exchanging any other solutions in each Automatic X-ray film processor

  11. Multithreading in vector processors

    Science.gov (United States)

    Evangelinos, Constantinos; Kim, Changhoan; Nair, Ravi

    2018-01-16

    In one embodiment, a system includes a processor having a vector processing mode and a multithreading mode. The processor is configured to operate on one thread per cycle in the multithreading mode. The processor includes a program counter register having a plurality of program counters, and the program counter register is vectorized. Each program counter in the program counter register represents a distinct corresponding thread of a plurality of threads. The processor is configured to execute the plurality of threads by activating the plurality of program counters in a round robin cycle.

  12. Real-time optical laboratory solution of parabolic differential equations

    Science.gov (United States)

    Casasent, David; Jackson, James

    1988-01-01

    An optical laboratory matrix-vector processor is used to solve parabolic differential equations (the transient diffusion equation with two space variables and time) by an explicit algorithm. This includes optical matrix-vector nonbase-2 encoded laboratory data, the combination of nonbase-2 and frequency-multiplexed data on such processors, a high-accuracy optical laboratory solution of a partial differential equation, new data partitioning techniques, and a discussion of a multiprocessor optical matrix-vector architecture.

  13. Characterization methods of integrated optics for mid-infrared interferometry

    Science.gov (United States)

    Labadie, Lucas; Kern, Pierre Y.; Schanen-Duport, Isabelle; Broquin, Jean-Emmanuel

    2004-10-01

    his article deals with one of the important instrumentation challenges of the stellar interferometry mission IRSI-Darwin of the European Space Agency: the necessity to have a reliable and performant system for beam combination has enlightened the advantages of an integrated optics solution, which is already in use for ground-base interferometry in the near infrared. Integrated optics provides also interesting features in terms of filtering, which is a main issue for the deep null to be reached by Darwin. However, Darwin will operate in the mid infrared range from 4 microns to 20 microns where no integrated optics functions are available on-the-shelf. This requires extending the integrated optics concept and the undergoing technology in this spectral range. This work has started with the IODA project (Integrated Optics for Darwin) under ESA contract and aims to provide a first component for interferometry. In this paper are presented the guidelines of the characterization work that is implemented to test and validate the performances of a component at each step of the development phase. We present also an example of characterization experiment used within the frame of this work, is theoretical approach and some results.

  14. Processor farming in two-level analysis of historical bridge

    Science.gov (United States)

    Krejčí, T.; Kruis, J.; Koudelka, T.; Šejnoha, M.

    2017-11-01

    This contribution presents a processor farming method in connection with a multi-scale analysis. In this method, each macro-scopic integration point or each finite element is connected with a certain meso-scopic problem represented by an appropriate representative volume element (RVE). The solution of a meso-scale problem provides then effective parameters needed on the macro-scale. Such an analysis is suitable for parallel computing because the meso-scale problems can be distributed among many processors. The application of the processor farming method to a real world masonry structure is illustrated by an analysis of Charles bridge in Prague. The three-dimensional numerical model simulates the coupled heat and moisture transfer of one half of arch No. 3. and it is a part of a complex hygro-thermo-mechanical analysis which has been developed to determine the influence of climatic loading on the current state of the bridge.

  15. 3081/E processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.

    1984-04-01

    The 3081/E project was formed to prepare a much improved IBM mainframe emulator for the future. Its design is based on a large amount of experience in using the 168/E processor to increase available CPU power in both online and offline environments. The processor will be at least equal to the execution speed of a 370/168 and up to 1.5 times faster for heavy floating point code. A single processor will thus be at least four times more powerful than the VAX 11/780, and five processors on a system would equal at least the performance of the IBM 3081K. With its large memory space and simple but flexible high speed interface, the 3081/E is well suited for the online and offline needs of high energy physics in the future

  16. Characterization of hybrid integrated all-optical flip-flop

    NARCIS (Netherlands)

    Liu, Y.; McDougall, R.; Seoane, J.; Kehayas, E.; Hill, M.T.; Maxwell, G.D.; Zhang, S.; Harmon, R.; Huijskens, Frans; Rivers, L.; Van Holm-Nielsen, P.; Martinez, J.M.; Herrera Llorente, J.; Ramos, F.; Marti, J.; Avramopoulos, H.; Jeppesen, P.; Koonen, A.M.J.; Poustie, A.; Dorren, H.J.S.

    2006-01-01

    We present a fully-packaged, hybrid-integrated all-optical flip-flop with separate optical set and reset operation. The flip-flop can control a wavelength converter to route 40 Gb/s data packets all-optically. The experimental results are given

  17. Characterisation of hybrid integrated all-optical flip-flop

    DEFF Research Database (Denmark)

    Liu, Y.; McDougall, R.; Seoane, Jorge

    2006-01-01

    We present a fully-packaged, hybrid-integrated all-optical flip-flop with separate optical set and reset operation. The flip-flop can control a wavelength converter to route 40 Gb/s data packets all-optically. The experimental results are given....

  18. Development of the multiwavelength monolithic integrated fiber optics terminal

    Science.gov (United States)

    Chubb, C. R.; Bryan, D. A.; Powers, J. K.; Rice, R. R.; Nettle, V. H.; Dalke, E. A.; Reed, W. R.

    1982-01-01

    This paper describes the development of the Multiwavelength Monolithic Integrated Fiber Optic Terminal (MMIFOT) for the NASA Johnson Space Center. The program objective is to utilize guided wave optical technology to develop wavelength-multiplexing and -demultiplexing units, using a single mode optical fiber for transmission between terminals. Intensity modulated injection laser diodes, chirped diffraction gratings and thin film lenses are used to achieve the wavelength-multiplexing and -demultiplexing. The video and audio data transmission test of an integrated optical unit with a Luneburg collimation lens, waveguide diffraction grating and step index condensing lens is described.

  19. Designing neutral-atom nanotraps with integrated optical waveguides

    International Nuclear Information System (INIS)

    Burke, James P. Jr.; Chu, S.-T.; Bryant, Garnett W.; Williams, C.J.; Julienne, P.S.

    2002-01-01

    Integrated optical structures offer the intriguing potential of compact, reproducible waveguide arrays, rings, Y junctions, etc., that could be used to design evanescent field traps to transport, store, and interact atoms in networks as complicated as any integrated optical waveguide circuit. We theoretically investigate three approaches to trapping atoms above linear integrated optical waveguides. A two-color scheme balances the decaying evanescent fields of red- and blue-detuned light to produce a potential minimum above the guide. A one-color surface trap proposal uses blue-detuned light and the attractive surface interaction to provide a potential minimum. A third proposal uses blue-detuned light in two guides positioned above and below one another. The atoms are confined to the 'dark' spot in the vacuum gap between the guides. We find that all three approaches can be used to trap atoms in two or three dimensions with approximately 100 mW of laser power. We show that the dark spot guide is robust to light scatter and provides the most viable approach for constructing integrated optical circuits that could be used to transport and manipulate atoms in a controlled manner

  20. Amorphous silicon rich silicon nitride optical waveguides for high density integrated optics

    DEFF Research Database (Denmark)

    Philipp, Hugh T.; Andersen, Karin Nordström; Svendsen, Winnie Edith

    2004-01-01

    Amorphous silicon rich silicon nitride optical waveguides clad in silica are presented as a high-index contrast platform for high density integrated optics. Performance of different cross-sectional geometries have been measured and are presented with regards to bending loss and insertion loss...

  1. Performance evaluation of throughput computing workloads using multi-core processors and graphics processors

    Science.gov (United States)

    Dave, Gaurav P.; Sureshkumar, N.; Blessy Trencia Lincy, S. S.

    2017-11-01

    Current trend in processor manufacturing focuses on multi-core architectures rather than increasing the clock speed for performance improvement. Graphic processors have become as commodity hardware for providing fast co-processing in computer systems. Developments in IoT, social networking web applications, big data created huge demand for data processing activities and such kind of throughput intensive applications inherently contains data level parallelism which is more suited for SIMD architecture based GPU. This paper reviews the architectural aspects of multi/many core processors and graphics processors. Different case studies are taken to compare performance of throughput computing applications using shared memory programming in OpenMP and CUDA API based programming.

  2. The Molen Polymorphic Media Processor

    NARCIS (Netherlands)

    Kuzmanov, G.K.

    2004-01-01

    In this dissertation, we address high performance media processing based on a tightly coupled co-processor architectural paradigm. More specifically, we introduce a reconfigurable media augmentation of a general purpose processor and implement it into a fully operational processor prototype. The

  3. Embedded SoPC Design with Nios II Processor and Verilog Examples

    CERN Document Server

    Chu, Pong P

    2012-01-01

    Explores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog An SoPC (system on a programmable chip) integrates a processor, memory modules, I/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well-allowing us to configure the soft-core processor, create tailored I/O interfaces, and develop s

  4. Experimental Investigation of Integrated Optical Intensive Impulse Electric Field Sensors

    International Nuclear Information System (INIS)

    Bao, Sun; Fu-Shen, Chen

    2009-01-01

    We design and fabricate an integrated optical electric field sensor with segmented electrode for intensive impulse electric field measurement. The integrated optical sensor is based on a Mach–Zehnder interferometer with segmented electrodes. The output/input character of the sensing system is analysed and measured. The maximal detectable electric field range (−75 kV/m to 245 kV/m) is obtained by analysing the results. As a result, the integrated optics electric field sensing system is suitable for transient intensive electric field measurement investigation

  5. Demonstration of glass-based photonic interposer for mid-board-optical engines and electrical-optical circuit board (EOCB) integration strategy

    Science.gov (United States)

    Schröder, H.; Neitz, M.; Schneider-Ramelow, M.

    2018-02-01

    Due to its optical transparency and superior dielectric properties glass is regarded as a promising candidate for advanced applications as active photonic interposer for mid-board-optics and optical PCB waveguide integration. The concepts for multi-mode and single-mode photonic system integration are discussed and related demonstration project results will be presented. A hybrid integrated photonic glass body interposer with integrated optical lenses for multi-mode data communication wavelength of 850 nm have been realized. The paper summarizes process developments which allow cost efficient metallization of TGV. Electro-optical elements like photodiodes and VCSELs can be directly flip-chip mounted on the glass substrate according to the desired lens positions. Furthermore results for a silicon photonic based single-mode active interposer integration onto a single mode glass made EOCB will be compared in terms of packaging challenges. The board level integration strategy for both of these technological approaches and general next generation board level integration concepts for photonic interposer will be introductorily discussed.

  6. Integrated liquid-core optical fibers for ultra-efficient nonlinear liquid photonics.

    Science.gov (United States)

    Kieu, K; Schneebeli, L; Norwood, R A; Peyghambarian, N

    2012-03-26

    We have developed a novel integrated platform for liquid photonics based on liquid core optical fiber (LCOF). The platform is created by fusion splicing liquid core optical fiber to standard single-mode optical fiber making it fully integrated and practical - a major challenge that has greatly hindered progress in liquid-photonic applications. As an example, we report here the realization of ultralow threshold Raman generation using an integrated CS₂ filled LCOF pumped with sub-nanosecond pulses at 532 nm and 1064 nm. The measured energy threshold for the Stokes generation is 1nJ, about three orders of magnitude lower than previously reported values in the literature for hydrogen gas, a popular Raman medium. The integrated LCOF platform opens up new possibilities for ultralow power nonlinear optics such as efficient white light generation for displays, mid-IR generation, slow light generation, parametric amplification, all-optical switching and wavelength conversion using liquids that have orders of magnitude larger optical nonlinearities compared with silica glass.

  7. Compressive sensing in a photonic link with optical integration

    DEFF Research Database (Denmark)

    Chen, Ying; Yu, Xianbin; Chi, Hao

    2014-01-01

    In this Letter, we present a novel structure to realize photonics-assisted compressive sensing (CS) with optical integration. In the system, a spectrally sparse signal modulates a multiwavelength continuous-wave light and then is mixed with a random sequence in optical domain. The optical signal......, which is equivalent to the function of integration required in CS. A proof-of-concept experiment with four wavelengths, corresponding to a compression factor of 4, is demonstrated. More simulation results are also given to show the potential of the technique....

  8. Potential for integrated optical circuits in advanced aircraft with fiber optic control and monitoring systems

    Science.gov (United States)

    Baumbick, Robert J.

    1991-02-01

    Fiber optic technology is expected to be used in future advanced weapons platforms as well as commercial aerospace applications. Fiber optic waveguides will be used to transmit noise free high speed data between a multitude of computers as well as audio and video information to the flight crew. Passive optical sensors connected to control computers with optical fiber interconnects will serve both control and monitoring functions. Implementation of fiber optic technology has already begun. Both the military and NASA have several programs in place. A cooperative program called FOCSI (Fiber Optic Control System Integration) between NASA Lewis and the NAVY to build environmentally test and flight demonstrate sensor systems for propul sion and flight control systems is currently underway. Integrated Optical Circuits (IOC''s) are also being given serious consideration for use in advanced aircraft sys tems. IOC''s will result in miniaturization and localization of components to gener ate detect optical signals and process them for use by the control computers. In some complex systems IOC''s may be required to perform calculations optically if the technology is ready replacing some of the electronic systems used today. IOC''s are attractive because they will result in rugged components capable of withstanding severe environments in advanced aerospace vehicles. Manufacturing technology devel oped for microelectronic integrated circuits applied to IOC''s will result in cost effective manufacturing. This paper reviews the current FOCSI program and describes the role of IOC''s in FOCSI applications.

  9. JPP: A Java Pre-Processor

    OpenAIRE

    Kiniry, Joseph R.; Cheong, Elaine

    1998-01-01

    The Java Pre-Processor, or JPP for short, is a parsing pre-processor for the Java programming language. Unlike its namesake (the C/C++ Pre-Processor, cpp), JPP provides functionality above and beyond simple textual substitution. JPP's capabilities include code beautification, code standard conformance checking, class and interface specification and testing, and documentation generation.

  10. A VLSI image processor via pseudo-mersenne transforms

    International Nuclear Information System (INIS)

    Sei, W.J.; Jagadeesh, J.M.

    1986-01-01

    The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

  11. Integrated optics theory and technology

    CERN Document Server

    Hunsperger, Robert G

    1984-01-01

    Our intent in producing this book was to provide a text that would be comprehensive enough for an introductory course in integrated optics, yet concise enough in its mathematical derivations to be easily readable by a practicing engineer who desires an overview of the field. The response to the first edition has indeed been gratifying; unusually strong demand has caused it to be sold out during the initial year of publication, thus providing us with an early opportunity to produce this updated and improved second edition. This development is fortunate, because integrated optics is a very rapidly progressing field, with significant new research being regularly reported. Hence, a new chapter (Chap. 17) has been added to review recent progress and to provide numerous additional references to the relevant technical literature. Also, thirty-five new problems for practice have been included to supplement those at the ends of chapters in the first edition. Chapters I through 16 are essentially unchanged, except for ...

  12. Compact gasoline fuel processor for passenger vehicle APU

    Science.gov (United States)

    Severin, Christopher; Pischinger, Stefan; Ogrzewalla, Jürgen

    Due to the increasing demand for electrical power in today's passenger vehicles, and with the requirements regarding fuel consumption and environmental sustainability tightening, a fuel cell-based auxiliary power unit (APU) becomes a promising alternative to the conventional generation of electrical energy via internal combustion engine, generator and battery. It is obvious that the on-board stored fuel has to be used for the fuel cell system, thus, gasoline or diesel has to be reformed on board. This makes the auxiliary power unit a complex integrated system of stack, air supply, fuel processor, electrics as well as heat and water management. Aside from proving the technical feasibility of such a system, the development has to address three major barriers:start-up time, costs, and size/weight of the systems. In this paper a packaging concept for an auxiliary power unit is presented. The main emphasis is placed on the fuel processor, as good packaging of this large subsystem has the strongest impact on overall size. The fuel processor system consists of an autothermal reformer in combination with water-gas shift and selective oxidation stages, based on adiabatic reactors with inter-cooling. The configuration was realized in a laboratory set-up and experimentally investigated. The results gained from this confirm a general suitability for mobile applications. A start-up time of 30 min was measured, while a potential reduction to 10 min seems feasible. An overall fuel processor efficiency of about 77% was measured. On the basis of the know-how gained by the experimental investigation of the laboratory set-up a packaging concept was developed. Using state-of-the-art catalyst and heat exchanger technology, the volumes of these components are fixed. However, the overall volume is higher mainly due to mixing zones and flow ducts, which do not contribute to the chemical or thermal function of the system. Thus, the concept developed mainly focuses on minimization of those

  13. Integrated resource management for Hybrid Optical Wireless (HOW) networks

    DEFF Research Database (Denmark)

    Yan, Ying; Yu, Hao; Wessing, Henrik

    2009-01-01

    Efficient utilization of available bandwidth over hybrid optical wireless networks is a critical issue, especially for multimedia applications with high data rates and stringent Quality of Service (QoS) requirements. In this paper, we propose an integrated resource management including an enhanced...... resource sharing scheme and an integrated admission control scheme for the hybrid optical wireless networks. It provides QoS guarantees for connections through both optical and wireless domain. Simulation results show that our proposed scheme improves QoS performances in terms of high throughput and low...

  14. Optical Doppler tomography based on a field programmable gate array

    DEFF Research Database (Denmark)

    Larsen, Henning Engelbrecht; Nilsson, Ronnie Thorup; Thrane, Lars

    2008-01-01

    We report the design of and results obtained by using a field programmable gate array (FPGA) to digitally process optical Doppler tomography signals. The processor fits into the analog signal path in an existing optical coherence tomography setup. We demonstrate both Doppler frequency and envelope...... extraction using the Hilbert transform, all in a single FPGA. An FPGA implementation has certain advantages over general purpose digital signal processor (DSP) due to the fact that the processing elements operate in parallel as opposed to the DSP. which is primarily a sequential processor....

  15. Materials and integration schemes for above-IC integrated optics

    NARCIS (Netherlands)

    Schmitz, Jurriaan; Rangarajan, B.; Kovalgin, Alexeij Y.

    2014-01-01

    A study is presented on silicon oxynitride material for waveguides and germanium-silicon alloys for p-i-n diodes. The materials are manufactured at low, CMOS-backend compatible temperatures, targeting the integration of optical functions on top of CMOS chips. Low-temperature germanium-silicon

  16. Producing chopped firewood with firewood processors

    International Nuclear Information System (INIS)

    Kaerhae, K.; Jouhiaho, A.

    2009-01-01

    The TTS Institute's research and development project studied both the productivity of new, chopped firewood processors (cross-cutting and splitting machines) suitable for professional and independent small-scale production, and the costs of the chopped firewood produced. Seven chopped firewood processors were tested in the research, six of which were sawing processors and one shearing processor. The chopping work was carried out using wood feeding racks and a wood lifter. The work was also carried out without any feeding appliances. Altogether 132.5 solid m 3 of wood were chopped in the time studies. The firewood processor used had the most significant impact on chopping work productivity. In addition to the firewood processor, the stem mid-diameter, the length of the raw material, and of the firewood were also found to affect productivity. The wood feeding systems also affected productivity. If there is a feeding rack and hydraulic grapple loader available for use in chopping firewood, then it is worth using the wood feeding rack. A wood lifter is only worth using with the largest stems (over 20 cm mid-diameter) if a feeding rack cannot be used. When producing chopped firewood from small-diameter wood, i.e. with a mid-diameter less than 10 cm, the costs of chopping work were over 10 EUR solid m -3 with sawing firewood processors. The shearing firewood processor with a guillotine blade achieved a cost level of 5 EUR solid m -3 when the mid-diameter of the chopped stem was 10 cm. In addition to the raw material, the cost-efficient chopping work also requires several hundred annual operating hours with a firewood processor, which is difficult for individual firewood entrepreneurs to achieve. The operating hours of firewood processors can be increased to the required level by the joint use of the processors by a number of firewood entrepreneurs. (author)

  17. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    DEFF Research Database (Denmark)

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  18. Breaking the Memory Bottleneck with an Optical Data Path

    National Research Council Canada - National Science Library

    Fritts, Jason E; Chamberlain, Roger D

    2005-01-01

    .... Through a simulation-based performance analysis of a 1 GHz processor model, we provide a preliminary evaluation of the benefits of an optical processor-to-memory bus in both eliminating the bandwidth...

  19. Keystone Business Models for Network Security Processors

    Directory of Open Access Journals (Sweden)

    Arthur Low

    2013-07-01

    Full Text Available Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor” models nor the silicon intellectual-property licensing (“IP-licensing” models allow small technology companies to successfully compete. This article describes an alternative approach that produces an ongoing stream of novel network security processors for niche markets through continuous innovation by both large and small companies. This approach, referred to here as the "business ecosystem model for network security processors", includes a flexible and reconfigurable technology platform, a “keystone” business model for the company that maintains the platform architecture, and an extended ecosystem of companies that both contribute and share in the value created by innovation. New opportunities for business model innovation by participating companies are made possible by the ecosystem model. This ecosystem model builds on: i the lessons learned from the experience of the first author as a senior integrated circuit architect for providers of public-key cryptography solutions and as the owner of a semiconductor startup, and ii the latest scholarly research on technology entrepreneurship, business models, platforms, and business ecosystems. This article will be of interest to all technology entrepreneurs, but it will be of particular interest to owners of small companies that provide security solutions and to specialized security professionals seeking to launch their own companies.

  20. Designing High-Performance Fuzzy Controllers Combining IP Cores and Soft Processors

    Directory of Open Access Journals (Sweden)

    Oscar Montiel-Ross

    2012-01-01

    Full Text Available This paper presents a methodology to integrate a fuzzy coprocessor described in VHDL (VHSIC Hardware Description Language to a soft processor embedded into an FPGA, which increases the throughput of the whole system, since the controller uses parallelism at the circuitry level for high-speed-demanding applications, the rest of the application can be written in C/C++. We used the ARM 32-bit soft processor, which allows sequential and parallel programming. The FLC coprocessor incorporates a tuning method that allows to manipulate the system response. We show experimental results using a fuzzy PD+I controller as the embedded coprocessor.

  1. Supertracker: A Programmable Parallel Pipeline Arithmetic Processor For Auto-Cueing Target Processing

    Science.gov (United States)

    Mack, Harold; Reddi, S. S.

    1980-04-01

    Supertracker represents a programmable parallel pipeline computer architecture that has been designed to meet the real time image processing requirements of auto-cueing target data processing. The prototype bread-board currently under development will be designed to perform input video preprocessing and processing for 525-line and 875-line TV formats FLIR video, automatic display gain and contrast control, and automatic target cueing, classification, and tracking. The video preprocessor is capable of performing operations full frames of video data in real time, e.g., frame integration, storage, 3 x 3 convolution, and neighborhood processing. The processor architecture is being implemented using bit-slice microprogrammable arithmetic processors, operating in parallel. Each processor is capable of up to 20 million operations per second. Multiple frame memories are used for additional flexibility.

  2. Integrated-optics heralded controlled-NOT gate for polarization-encoded qubits

    Science.gov (United States)

    Zeuner, Jonas; Sharma, Aditya N.; Tillmann, Max; Heilmann, René; Gräfe, Markus; Moqanaki, Amir; Szameit, Alexander; Walther, Philip

    2018-03-01

    Recent progress in integrated-optics technology has made photonics a promising platform for quantum networks and quantum computation protocols. Integrated optical circuits are characterized by small device footprints and unrivalled intrinsic interferometric stability. Here, we take advantage of femtosecond-laser-written waveguides' ability to process polarization-encoded qubits and present an implementation of a heralded controlled-NOT gate on chip. We evaluate the gate performance in the computational basis and a superposition basis, showing that the gate can create polarization entanglement between two photons. Transmission through the integrated device is optimized using thermally expanded core fibers and adiabatically reduced mode-field diameters at the waveguide facets. This demonstration underlines the feasibility of integrated quantum gates for all-optical quantum networks and quantum repeaters.

  3. Boson sampling with integrated optical circuits

    International Nuclear Information System (INIS)

    Bentivegna, M.

    2014-01-01

    Simulating the evolution of non-interacting bosons through a linear transformation acting on the system’s Fock state is strongly believed to be hard for a classical computer. This is commonly known as the Boson Sampling problem, and has recently got attention as the first possible way to demonstrate the superior computational power of quantum devices over classical ones. In this paper we describe the quantum optics approach to this problem, highlighting the role of integrated optical circuits.

  4. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-01-01

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

  5. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-04-13

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

  6. Packaged and hybrid integrated all-optical flip-flop memory

    NARCIS (Netherlands)

    Liu, Y.; McDougall, R.; Hill, M.T.; Maxwell, G.D.; Zhang, S.; Harmon, R.; Huijskens, Frans; Rivers, L.; Dorren, H.J.S.; Poustie, A.

    2006-01-01

    A fully-packaged hybrid-integrated all-optical flip-flop, where InP-based semiconductor optical amplifiers are assembled onto a planar silica waveguide board, is demonstrated. It is shown experimentally that the flip-flop can dynamically toggle between its two states by injecting 150 ps optical

  7. AMD's 64-bit Opteron processor

    CERN Multimedia

    CERN. Geneva

    2003-01-01

    This talk concentrates on issues that relate to obtaining peak performance from the Opteron processor. Compiler options, memory layout, MPI issues in multi-processor configurations and the use of a NUMA kernel will be covered. A discussion of recent benchmarking projects and results will also be included.BiographiesDavid RichDavid directs AMD's efforts in high performance computing and also in the use of Opteron processors...

  8. Composable processor virtualization for embedded systems

    NARCIS (Netherlands)

    Molnos, A.M.; Milutinovic, A.; She, D.; Goossens, K.G.W.

    2010-01-01

    Processor virtualization divides a physical processor's time among a set of virual machines, enabling efficient hardware utilization, application security and allowing co-existence of different operating systems on the same processor. Through initially intended for the server domain, virtualization

  9. Development of optical packet and circuit integrated ring network testbed.

    Science.gov (United States)

    Furukawa, Hideaki; Harai, Hiroaki; Miyazawa, Takaya; Shinada, Satoshi; Kawasaki, Wataru; Wada, Naoya

    2011-12-12

    We developed novel integrated optical packet and circuit switch-node equipment. Compared with our previous equipment, a polarization-independent 4 × 4 semiconductor optical amplifier switch subsystem, gain-controlled optical amplifiers, and one 100 Gbps optical packet transponder and seven 10 Gbps optical path transponders with 10 Gigabit Ethernet (10GbE) client-interfaces were newly installed in the present system. The switch and amplifiers can provide more stable operation without equipment adjustments for the frequent polarization-rotations and dynamic packet-rate changes of optical packets. We constructed an optical packet and circuit integrated ring network testbed consisting of two switch nodes for accelerating network development, and we demonstrated 66 km fiber transmission and switching operation of multiplexed 14-wavelength 10 Gbps optical paths and 100 Gbps optical packets encapsulating 10GbE frames. Error-free (frame error rate optical packets of various packet lengths and packet rates, and stable operation of the network testbed was confirmed. In addition, 4K uncompressed video streaming over OPS links was successfully demonstrated. © 2011 Optical Society of America

  10. Advanced Avionics and Processor Systems for a Flexible Space Exploration Architecture

    Science.gov (United States)

    Keys, Andrew S.; Adams, James H.; Smith, Leigh M.; Johnson, Michael A.; Cressler, John D.

    2010-01-01

    the Federal fiscal year of 2010 are: Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments, Modeling of Radiation Effects on Electronics, Radiation Hardened High Performance Processors (HPP), and and Reconfigurable Computing.

  11. Integrated-optic current sensors with a multimode interference waveguide device.

    Science.gov (United States)

    Kim, Sung-Moon; Chu, Woo-Sung; Kim, Sang-Guk; Oh, Min-Cheol

    2016-04-04

    Optical current sensors based on polarization-rotated reflection interferometry are demonstrated using polymeric integrated optics and various functional optical waveguide devices. Interferometric sensors normally require bias feedback control for maintaining the operating point, which increases the cost. In order to resolve this constraint of feedback control, a multimode interference (MMI) waveguide device is integrated onto the current-sensor optical chip in this work. From the multiple outputs of the MMI, a 90° phase-shifted transfer function is obtained. Using passive quadrature demodulation, we demonstrate that the sensor could maintain the output signal regardless of the drift in the operating bias-point.

  12. Evaluation of the Xeon phi processor as a technology for the acceleration of real-time control in high-order adaptive optics systems

    Science.gov (United States)

    Barr, David; Basden, Alastair; Dipper, Nigel; Schwartz, Noah; Vick, Andy; Schnetler, Hermine

    2014-08-01

    We present wavefront reconstruction acceleration of high-order AO systems using an Intel Xeon Phi processor. The Xeon Phi is a coprocessor providing many integrated cores and designed for accelerating compute intensive, numerical codes. Unlike other accelerator technologies, it allows virtually unchanged C/C++ to be recompiled to run on the Xeon Phi, giving the potential of making development, upgrade and maintenance faster and less complex. We benchmark the Xeon Phi in the context of AO real-time control by running a matrix vector multiply (MVM) algorithm. We investigate variability in execution time and demonstrate a substantial speed-up in loop frequency. We examine the integration of a Xeon Phi into an existing RTC system and show that performance improvements can be achieved with limited development effort.

  13. Deterministic chaos in the processor load

    International Nuclear Information System (INIS)

    Halbiniak, Zbigniew; Jozwiak, Ireneusz J.

    2007-01-01

    In this article we present the results of research whose purpose was to identify the phenomenon of deterministic chaos in the processor load. We analysed the time series of the processor load during efficiency tests of database software. Our research was done on a Sparc Alpha processor working on the UNIX Sun Solaris 5.7 operating system. The conducted analyses proved the presence of the deterministic chaos phenomenon in the processor load in this particular case

  14. Optical Characteristics of a Multichannel Hybrid Integrated Light Source for Ultra-High-Bandwidth Optical Interconnections

    Directory of Open Access Journals (Sweden)

    Takanori Shimizu

    2015-11-01

    Full Text Available The optical characteristics of a multi-channel hybrid integrated light source were described for an optical interconnection with a bandwidth of over 10 Tbit/s. The power uniformity of the relative intensity of a 1000-channel light source was shown, and the minimum standard deviation s of the optical power of the 200 output ports at each 25-channel laser diode (LD array was estimated to be 0.49 dB. This hybrid integrated light source is expected to be easily adaptable to a photonics-electronics convergence system for ultra-high-bandwidth interchip interconnections.

  15. Integrated optical delay lines for time-division multiplexers

    NARCIS (Netherlands)

    Stopinski, S.T.; Malinowski, M.; Piramidowicz, R.; Kleijn, E.; Smit, M.K.; Leijtens, X.J.M.

    2013-01-01

    In this paper, we present a study of integrated optical delay lines (DLs) for application in optical time-division multiplexers. The investigated DLs are formed by spirally folded waveguides. The components were designed in a generic approach and fabricated in multi-project wafer runs on an

  16. Advances in optical information processing IV; Proceedings of the Meeting, Orlando, FL, Apr. 18-20, 1990

    Science.gov (United States)

    Pape, Dennis R.

    1990-09-01

    The present conference discusses topics in optical image processing, optical signal processing, acoustooptic spectrum analyzer systems and components, and optical computing. Attention is given to tradeoffs in nonlinearly recorded matched filters, miniature spatial light modulators, detection and classification using higher-order statistics of optical matched filters, rapid traversal of an image data base using binary synthetic discriminant filters, wideband signal processing for emitter location, an acoustooptic processor for autonomous SAR guidance, and sampling of Fresnel transforms. Also discussed are an acoustooptic RF signal-acquisition system, scanning acoustooptic spectrum analyzers, the effects of aberrations on acoustooptic systems, fast optical digital arithmetic processors, information utilization in analog and digital processing, optical processors for smart structures, and a self-organizing neural network for unsupervised learning.

  17. A Miniaturized Optical Sensor with Integrated Gas Cell

    NARCIS (Netherlands)

    Ayerden, N.P.; Ghaderi, M.; De Graaf, G.; Wolffenbuttel, R.F.

    2015-01-01

    The design, fabrication and characterization of a highly integrated optical gas sensor is presented. The gas cell takes up most of the space in a microspectrometer and is the only component that has so far not been miniaturized. Using the tapered resonator cavity of a linear variable optical filter

  18. Integrated Miniature Arrays of Optical Biomolecule Detectors

    Science.gov (United States)

    Iltchenko, Vladimir; Maleki, Lute; Lin, Ying; Le, Thanh

    2009-01-01

    Integrated miniature planar arrays of optical sensors for detecting specific biochemicals in extremely small quantities have been proposed. An array of this type would have an area of about 1 cm2. Each element of the array would include an optical microresonator that would have a high value of the resonance quality factor (Q . 107). The surface of each microresonator would be derivatized to make it bind molecules of a species of interest, and such binding would introduce a measurable change in the optical properties of the microresonator. Because each microresonator could be derivatized for detection of a specific biochemical different from those of the other microresonators, it would be possible to detect multiple specific biochemicals by simultaneous or sequential interrogation of all the elements in the array. Moreover, the derivatization would make it unnecessary to prepare samples by chemical tagging. Such interrogation would be effected by means of a grid of row and column polymer-based optical waveguides that would be integral parts of a chip on which the array would be fabricated. The row and column polymer-based optical waveguides would intersect at the elements of the array (see figure). At each intersection, the row and column waveguides would be optically coupled to one of the microresonators. The polymer-based waveguides would be connected via optical fibers to external light sources and photodetectors. One set of waveguides and fibers (e.g., the row waveguides and fibers) would couple light from the sources to the resonators; the other set of waveguides and fibers (e.g., the column waveguides and fibers) would couple light from the microresonators to the photodetectors. Each microresonator could be addressed individually by row and column for measurement of its optical transmission. Optionally, the chip could be fabricated so that each microresonator would lie inside a microwell, into which a microscopic liquid sample could be dispensed.

  19. Neurovision processor for designing intelligent sensors

    Science.gov (United States)

    Gupta, Madan M.; Knopf, George K.

    1992-03-01

    A programmable multi-task neuro-vision processor, called the Positive-Negative (PN) neural processor, is proposed as a plausible hardware mechanism for constructing robust multi-task vision sensors. The computational operations performed by the PN neural processor are loosely based on the neural activity fields exhibited by certain nervous tissue layers situated in the brain. The neuro-vision processor can be programmed to generate diverse dynamic behavior that may be used for spatio-temporal stabilization (STS), short-term visual memory (STVM), spatio-temporal filtering (STF) and pulse frequency modulation (PFM). A multi- functional vision sensor that performs a variety of information processing operations on time- varying two-dimensional sensory images can be constructed from a parallel and hierarchical structure of numerous individually programmed PN neural processors.

  20. Integrated optics on Lithium Niobate for sensing applications

    Science.gov (United States)

    Zaltron, A.; Bettella, G.; Pozza, G.; Zamboni, R.; Ciampolillo, M.; Argiolas, N.; Sada, C.; Kroesen, S.; Esseling, M.; Denz, C.

    2015-05-01

    In micro-analytical chemistry and biology applications, optofluidic technology holds great promise for creating efficient lab-on-chip systems where higher levels of integration of different stages on the same platform is constantly addressed. Therefore, in this work the possibility of integrating opto-microfluidic functionalities in lithium niobate (LiNbO3) crystals is presented. In particular, a T-junction droplet generator is directly engraved in a LiNbO3 substrate by means of laser ablation process and optical waveguides are realized in the same material by exploiting the Titanium in-diffusion approach. The coupling of these two stages as well as the realization of holographic gratings in the same substrate will allow creating new compact optical sensor prototypes, where the optical properties of the droplets constituents can be monitored.

  1. Complete achromatic and robustness electro-optic switch between two integrated optical waveguides

    Science.gov (United States)

    Huang, Wei; Kyoseva, Elica

    2018-01-01

    In this paper, we present a novel design of electro-optic modulator and optical switching device, based on current integrated optics technique. The advantages of our optical switching device are broadband of input light wavelength, robustness against varying device length and operation voltages, with reference to previous design. Conforming to our results of previous paper [Huang et al, phys. lett. a, 90, 053837], the coupling of the waveguides has a hyperbolic-secant shape. while detuning has a sign flip at maximum coupling, we called it as with a sign flip of phase mismatch model. The a sign flip of phase mismatch model can produce complete robust population transfer. In this paper, we enhance this device to switch light intensity controllable, by tuning external electric field based on electro-optic effect.

  2. VIRTUS: a multi-processor system in FASTBUS

    International Nuclear Information System (INIS)

    Ellett, J.; Jackson, R.; Ritter, R.; Schlein, P.; Yaeger, D.; Zweizig, J.

    1986-01-01

    VIRTUS is a system of parallel MC68000-based processors interconnected by FASTBUS that is used either on-line as an intelligent trigger component or off-line for full event processing. Each processor receives the complete set of data from one event. The host computer, a VAX 11/780, down-line loads all software to the processors, controls and monitors the functioning of all processors, and writes processed data to tape. Instructions, programs, and data are transferred among the processors and the host in the form of fixed format, variable length data blocks. (Auth.)

  3. Integrated all optical transmodulator circuits with non-linear gain elements and tunable optical fibers

    NARCIS (Netherlands)

    Kuindersma, P.I.; Leijtens, X.J.M.; Zantvoort, van J.H.C.; Waardt, de H.

    2012-01-01

    We characterize integrated InP circuits for high speed ‘all-optical’ signal processing. Single chip circuits act as optical transistors. Transmodulation is performed by non-linear gain sections. Integrated tunable filters give signal equalization in time domain.

  4. QKD-Based Secured Burst Integrity Design for Optical Burst Switched Networks

    Science.gov (United States)

    Balamurugan, A. M.; Sivasubramanian, A.; Parvathavarthini, B.

    2016-03-01

    The field of optical transmission has undergone numerous advancements and is still being researched mainly due to the fact that optical data transmission can be done at enormous speeds. It is quite evident that people prefer optical communication when it comes to large amount of data involving its transmission. The concept of switching in networks has matured enormously with several researches, architecture to implement and methods starting with Optical circuit switching to Optical Burst Switching. Optical burst switching is regarded as viable solution for switching bursts over networks but has several security vulnerabilities. However, this work exploited the security issues associated with Optical Burst Switching with respect to integrity of burst. This proposed Quantum Key based Secure Hash Algorithm (QKBSHA-512) with enhanced compression function design provides better avalanche effect over the conventional integrity algorithms.

  5. Advances in optical information processing V; Proceedings of the Meeting, Orlando, FL, Apr. 21-24, 1992

    Science.gov (United States)

    Pape, Dennis R.

    Consideration is given to the following topics: transition of optical processing into systems (TOPS), optical signal processing, optical signal processing devices, optical image processing, Russian optical information processing, optical interconnects, and optical computing. Particular papers are presented on an acoustooptic range-Doppler processor design for radar insertion, an optical SAR processor and target recognition system, an advanced magnetooptic spatial light modulator device development update, an algorithm for controlling speckle-noise parameters, optical image processing in Russia, a massively parallel optical interconnect for long data stream convolution, and a reprogrammable digital optical coprocessor. (For individual items see A93-27718 to A93-27723)

  6. Commodity multi-processor systems in the ATLAS level-2 trigger

    International Nuclear Information System (INIS)

    Abolins, M.; Blair, R.; Bock, R.; Bogaerts, A.; Dawson, J.; Ermoline, Y.; Hauser, R.; Kugel, A.; Lay, R.; Muller, M.; Noffz, K.-H.; Pope, B.; Schlereth, J.; Werner, P.

    2000-01-01

    Low cost SMP (Symmetric Multi-Processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS the authors consider them as intelligent input buffers (active ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4-processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term program of work. The SMP systems may be considered as an important building block in future data acquisition systems

  7. Commodity multi-processor systems in the ATLAS level-2 trigger

    CERN Document Server

    Abolins, M; Bock, R; Bogaerts, J A C; Dawson, J; Ermoline, Y; Hauser, R; Kugel, A; Lay, R; Müller, M; Noffz, K H; Pope, B; Schlereth, J L; Werner, P

    2000-01-01

    Low cost SMP (symmetric multi-processor) systems provide substantial CPU and I/O capacity. These features together with the ease of system integration make them an attractive and cost effective solution for a number of real-time applications in event selection. In ATLAS we consider them as intelligent input buffers (an "active" ROB complex), as event flow supervisors or as powerful processing nodes. Measurements of the performance of one off-the-shelf commercial 4- processor PC with two PCI buses, equipped with commercial FPGA based data source cards (microEnable) and running commercial software are presented and mapped on such applications together with a long-term programme of work. The SMP systems may be considered as an important building block in future data acquisition systems. (9 refs).

  8. Sensitometric control of roentgen film processors

    International Nuclear Information System (INIS)

    Forsberg, H.; Karolinska Sjukhuset, Stockholm

    1987-01-01

    Monitoring of film processors performance is essential since image quality, patient dose and costs are influenced by the performance. A system for sensitometric constancy control of film processors and their associated components is described. Experience with the system for 3 years is given when implemented on 17 film processors. Modern high quality film processors have a stability that makes a test frequency of once a week sufficient to maintain adequate image quality. The test system is so sensitive that corrective actions almost invariably have been taken before any technical problem degraded the image quality to a visible degree. (orig.)

  9. Special purpose processors for high energy physics applications

    International Nuclear Information System (INIS)

    Verkerk, C.

    1978-01-01

    The review on the subject of hardware processors from very fast decision logic for the split field magnet facility at CERN, to a point-finding processor used to relieve the data-acquisition minicomputer from the task of monitoring the SPS experiment is given. Block diagrams of decision making processor, point-finding processor, complanarity and opening angle processor and programmable track selector module are presented and discussed. The applications of fully programmable but slower processor on the one hand, and very fast and programmable decision logic on the other hand are given in this review

  10. The Central Trigger Processor (CTP)

    CERN Multimedia

    Franchini, Matteo

    2016-01-01

    The Central Trigger Processor (CTP) receives trigger information from the calorimeter and muon trigger processors, as well as from other sources of trigger. It makes the Level-1 decision (L1A) based on a trigger menu.

  11. Enabling technologies for fiber optic sensing

    Science.gov (United States)

    Ibrahim, Selwan K.; Farnan, Martin; Karabacak, Devrez M.; Singer, Johannes M.

    2016-04-01

    In order for fiber optic sensors to compete with electrical sensors, several critical parameters need to be addressed such as performance, cost, size, reliability, etc. Relying on technologies developed in different industrial sectors helps to achieve this goal in a more efficient and cost effective way. FAZ Technology has developed a tunable laser based optical interrogator based on technologies developed in the telecommunication sector and optical transducer/sensors based on components sourced from the automotive market. Combining Fiber Bragg Grating (FBG) sensing technology with the above, high speed, high precision, reliable quasi distributed optical sensing systems for temperature, pressure, acoustics, acceleration, etc. has been developed. Careful design needs to be considered to filter out any sources of measurement drifts/errors due to different effects e.g. polarization and birefringence, coating imperfections, sensor packaging etc. Also to achieve high speed and high performance optical sensing systems, combining and synchronizing multiple optical interrogators similar to what has been used with computer/processors to deliver super computing power is an attractive solution. This path can be achieved by using photonic integrated circuit (PIC) technology which opens the doors to scaling up and delivering powerful optical sensing systems in an efficient and cost effective way.

  12. Broadband demonstrations of true-time delay using linear sideband chirped programming and optical coherent transients

    International Nuclear Information System (INIS)

    Reibel, R.R.; Barber, Z.W.; Fischer, J.A.; Tian, M.; Babbitt, W.R.

    2004-01-01

    Linear sideband chirped (LSC) programming is introduced as a means of configuring spatial-spectral holographic gratings for optical coherent transient processors. Similar to linear frequency chirped programming, LSC programming allows the use of broadband integrated electro-optic phase modulators to produce chirps instead of using elaborate broadband chirped lasers. This approach has several advantages including the ability to use a stabilized laser for the optical carrier as well as stable, reproducible chirped optical signals when the modulator is driven digitally. Using LSC programming, we experimentally demonstrate broadband true-time delay as a proof of principle for the optical control of phased array radars. Here both cw phase modulated and binary phase shift keyed probe signals are true-time delayed with bandwidths of 1 GHz and delay resolutions better than 60 ps

  13. Very Long Instruction Word Processors

    Indian Academy of Sciences (India)

    Pentium Processor have modified the processor architecture to exploit parallelism in a program. .... The type of operation itself is encoded using 14 bits. .... text of designing simple architectures with low power consump- tion and execute x86 ...

  14. Assessing the Progress of Trapped-Ion Processors Towards Fault-Tolerant Quantum Computation

    Science.gov (United States)

    Bermudez, A.; Xu, X.; Nigmatullin, R.; O'Gorman, J.; Negnevitsky, V.; Schindler, P.; Monz, T.; Poschinger, U. G.; Hempel, C.; Home, J.; Schmidt-Kaler, F.; Biercuk, M.; Blatt, R.; Benjamin, S.; Müller, M.

    2017-10-01

    A quantitative assessment of the progress of small prototype quantum processors towards fault-tolerant quantum computation is a problem of current interest in experimental and theoretical quantum information science. We introduce a necessary and fair criterion for quantum error correction (QEC), which must be achieved in the development of these quantum processors before their sizes are sufficiently big to consider the well-known QEC threshold. We apply this criterion to benchmark the ongoing effort in implementing QEC with topological color codes using trapped-ion quantum processors and, more importantly, to guide the future hardware developments that will be required in order to demonstrate beneficial QEC with small topological quantum codes. In doing so, we present a thorough description of a realistic trapped-ion toolbox for QEC and a physically motivated error model that goes beyond standard simplifications in the QEC literature. We focus on laser-based quantum gates realized in two-species trapped-ion crystals in high-optical aperture segmented traps. Our large-scale numerical analysis shows that, with the foreseen technological improvements described here, this platform is a very promising candidate for fault-tolerant quantum computation.

  15. Hybrid graphene/silicon integrated optical isolators with photonic spin–orbit interaction

    International Nuclear Information System (INIS)

    Ma, Jingwen; Sun, Xiankai; Xi, Xiang; Yu, Zejie

    2016-01-01

    Optical isolators are an important building block in photonic computation and communication. In traditional optics, isolators are realized with magneto-optical garnets. However, it remains challenging to incorporate such materials on an integrated platform because of the difficulty in material growth and bulky device footprint. Here, we propose an ultracompact integrated isolator by exploiting graphene's magneto-optical property on a silicon-on-insulator platform. The photonic nonreciprocity is achieved because the cyclotrons in graphene experiencing different optical spins exhibit different responses to counterpropagating light. Taking advantage of cavity resonance effects, we have numerically optimized a device design, which shows excellent isolation performance with the extinction ratio over 45 dB and the insertion loss around 12 dB at a wavelength near 1.55 μm. Featuring graphene's CMOS compatibility and substantially reduced device footprint, our proposal sheds light on monolithic integration of nonreciprocal photonic devices.

  16. Climbing Mont Blanc - A Training Site for Energy Efficient Programming on Heterogeneous Multicore Processors

    OpenAIRE

    Natvig, Lasse; Follan, Torbjørn; Støa, Simen; Magnussen, Sindre; Guirado, Antonio Garcia

    2015-01-01

    Climbing Mont Blanc (CMB) is an open online judge used for training in energy efficient programming of state-of-the-art heterogeneous multicores. It uses an Odroid-XU3 board from Hardkernel with an Exynos Octa processor and integrated power sensors. This processor is three-way heterogeneous containing 14 different cores of three different types. The board currently accepts C and C++ programs, with support for OpenCL v1.1, OpenMP 4.0 and Pthreads. Programs submitted using the graphical user in...

  17. Integrated Micro-Optical Fluorescence Detection System for Microfluidic Electrochromatography

    International Nuclear Information System (INIS)

    ALLERMAN, ANDREW A.; ARNOLD, DON W.; ASBILL, RANDOLPH E.; BAILEY, CHRISTOPHER G.; CARTER, TONY RAY; KEMME, SHANALYN A.; MATZKE, CAROLYN M.; SAMORA, SALLY; SWEATT, WILLIAM C.; WARREN, MIAL E.; WENDT, JOEL R.

    1999-01-01

    The authors describe the design and microfabrication of an extremely compact optical system as a key element in an integrated capillary-channel electrochromatograph with laser induced fluorescence detection. The optical design uses substrate-mode propagation within the fused silica substrate. The optical system includes a vertical cavity surface-emitting laser (VCSEL) array, two high performance microlenses and a commercial photodetector. The microlenses are multilevel diffractive optics patterned by electron beam lithography and etched by reactive ion etching in fused silica. Two generations of optical subsystems are described. The first generation design is integrated directly onto the capillary channel-containing substrate with a 6 mm separation between the VCSEL and photodetector. The second generation design separates the optical system onto its own module and the source to detector length is further compressed to 3.5 mm. The systems are designed for indirect fluorescence detection using infrared dyes. The first generation design has been tested with a 750 nm VCSEL exciting a 10(sup -4) M solution of CY-7 dye. The observed signal-to-noise ratio of better than 100:1 demonstrates that the background signal from scattered pump light is low despite the compact size of the optical system and meets the system sensitivity requirements

  18. HEP - A semaphore-synchronized multiprocessor with central control. [Heterogeneous Element Processor

    Science.gov (United States)

    Gilliland, M. C.; Smith, B. J.; Calvert, W.

    1976-01-01

    The paper describes the design concept of the Heterogeneous Element Processor (HEP), a system tailored to the special needs of scientific simulation. In order to achieve high-speed computation required by simulation, HEP features a hierarchy of processes executing in parallel on a number of processors, with synchronization being largely accomplished by hardware. A full-empty-reserve scheme of synchronization is realized by zero-one-valued hardware semaphores. A typical system has, besides the control computer and the scheduler, an algebraic module, a memory module, a first-in first-out (FIFO) module, an integrator module, and an I/O module. The architecture of the scheduler and the algebraic module is examined in detail.

  19. Experimental testing of the noise-canceling processor.

    Science.gov (United States)

    Collins, Michael D; Baer, Ralph N; Simpson, Harry J

    2011-09-01

    Signal-processing techniques for localizing an acoustic source buried in noise are tested in a tank experiment. Noise is generated using a discrete source, a bubble generator, and a sprinkler. The experiment has essential elements of a realistic scenario in matched-field processing, including complex source and noise time series in a waveguide with water, sediment, and multipath propagation. The noise-canceling processor is found to outperform the Bartlett processor and provide the correct source range for signal-to-noise ratios below -10 dB. The multivalued Bartlett processor is found to outperform the Bartlett processor but not the noise-canceling processor. © 2011 Acoustical Society of America

  20. Modular initiator with integrated optical diagnostic

    Science.gov (United States)

    Alam, M Kathleen [Cedar Crest, NM; Schmitt, Randal L [Tijeras, NM; Welle, Eric J [Niceville, FL; Madden, Sean P [Arlington, MA

    2011-05-17

    A slapper detonator which integrally incorporates an optical wavequide structure for determining whether there has been degradation of the explosive in the explosive device that is to be initiated by the detonator. Embodiments of this invention take advantage of the barrel-like character of a typical slapper detonator design. The barrel assembly, being in direct contact with the energetic material, incorporates an optical diagnostic device into the barrel assembly whereby one can monitor the state of the explosive material. Such monitoring can be beneficial because the chemical degradation of the explosive plays an important in achieving proper functioning of a detonator/initiator device.

  1. Integrated Active and Passive Polymer Optical Components with nm to mm Features

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Kristensen, Anders

    2007-01-01

    We present wafer-scale fabrication of integrated active and passive polymer optics with nm to mm features. First order DFB lasers, defined in dye doped SU-8 resist are integrated with SU-8 waveguides.......We present wafer-scale fabrication of integrated active and passive polymer optics with nm to mm features. First order DFB lasers, defined in dye doped SU-8 resist are integrated with SU-8 waveguides....

  2. MAP3D: a media processor approach for high-end 3D graphics

    Science.gov (United States)

    Darsa, Lucia; Stadnicki, Steven; Basoglu, Chris

    1999-12-01

    Equator Technologies, Inc. has used a software-first approach to produce several programmable and advanced VLIW processor architectures that have the flexibility to run both traditional systems tasks and an array of media-rich applications. For example, Equator's MAP1000A is the world's fastest single-chip programmable signal and image processor targeted for digital consumer and office automation markets. The Equator MAP3D is a proposal for the architecture of the next generation of the Equator MAP family. The MAP3D is designed to achieve high-end 3D performance and a variety of customizable special effects by combining special graphics features with high performance floating-point and media processor architecture. As a programmable media processor, it offers the advantages of a completely configurable 3D pipeline--allowing developers to experiment with different algorithms and to tailor their pipeline to achieve the highest performance for a particular application. With the support of Equator's advanced C compiler and toolkit, MAP3D programs can be written in a high-level language. This allows the compiler to successfully find and exploit any parallelism in a programmer's code, thus decreasing the time to market of a given applications. The ability to run an operating system makes it possible to run concurrent applications in the MAP3D chip, such as video decoding while executing the 3D pipelines, so that integration of applications is easily achieved--using real-time decoded imagery for texturing 3D objects, for instance. This novel architecture enables an affordable, integrated solution for high performance 3D graphics.

  3. Monolithically integrated quantum dot optical modulator with semiconductor optical amplifier for thousand and original band optical communication

    Science.gov (United States)

    Yamamoto, Naokatsu; Akahane, Kouichi; Umezawa, Toshimasa; Matsumoto, Atsushi; Kawanishi, Tetsuya

    2016-04-01

    A monolithically integrated quantum dot (QD) optical gain modulator (OGM) with a QD semiconductor optical amplifier (SOA) was successfully developed with T-band (1.0 µm waveband) and O-band (1.3 µm waveband) QD optical gain materials for Gbps-order, high-speed optical data generation. The insertion loss due to coupling between the device and the optical fiber was effectively compensated for by the SOA section. It was also confirmed that the monolithic QD-OGM/SOA device enabled >4.8 Gbps optical data generation with a clear eye opening in the T-band. Furthermore, we successfully demonstrated error-free 4.8 Gbps optical data transmissions in each of the six wavelength channels over a 10-km-long photonic crystal fiber using the monolithic QD-OGM/SOA device in multiple O-band wavelength channels, which were generated by the single QD gain chip. These results suggest that the monolithic QD-OGM/SOA device will be advantageous in ultra-broadband optical frequency systems that utilize the T+O-band for short- and medium-range optical communications.

  4. Micro-resonators based on integrated polymer technology for optical sensing

    OpenAIRE

    Girault , Pauline; Lemaitre , Jonathan; Guendouz , Mohammed; Lorrain , Nathalie; Poffo , Luiz; Gadonna , Michel; Bosc , Dominique

    2014-01-01

    International audience; Research on sensors has experienced a noticeable development over the last decades especially in label free optical biosensors. However, compact sensors without markers for rapid, reliable and inexpensive detection of various substances induces a significant research of new technological solutions. The context of this work is the development of a sensor based on easily integrated and inexpensive micro-resonator (MR) component in integrated optics, highly sensitive and ...

  5. Implementation of 4-way Superscalar Hash MIPS Processor Using FPGA

    Science.gov (United States)

    Sahib Omran, Safaa; Fouad Jumma, Laith

    2018-05-01

    Due to the quick advancements in the personal communications systems and wireless communications, giving data security has turned into a more essential subject. This security idea turns into a more confounded subject when next-generation system requirements and constant calculation speed are considered in real-time. Hash functions are among the most essential cryptographic primitives and utilized as a part of the many fields of signature authentication and communication integrity. These functions are utilized to acquire a settled size unique fingerprint or hash value of an arbitrary length of message. In this paper, Secure Hash Algorithms (SHA) of types SHA-1, SHA-2 (SHA-224, SHA-256) and SHA-3 (BLAKE) are implemented on Field-Programmable Gate Array (FPGA) in a processor structure. The design is described and implemented using a hardware description language, namely VHSIC “Very High Speed Integrated Circuit” Hardware Description Language (VHDL). Since the logical operation of the hash types of (SHA-1, SHA-224, SHA-256 and SHA-3) are 32-bits, so a Superscalar Hash Microprocessor without Interlocked Pipelines (MIPS) processor are designed with only few instructions that were required in invoking the desired Hash algorithms, when the four types of hash algorithms executed sequentially using the designed processor, the total time required equal to approximately 342 us, with a throughput of 4.8 Mbps while the required to execute the same four hash algorithms using the designed four-way superscalar is reduced to 237 us with improved the throughput to 5.1 Mbps.

  6. Lattice design of the integrable optics test accelerator and optical stochastic cooling experiment at Fermilab

    Energy Technology Data Exchange (ETDEWEB)

    Kafka, Gene [Illinois Inst. of Technology, Chicago, IL (United States)

    2015-05-01

    The Integrable Optics Test Accelerator (IOTA) storage ring at Fermilab will serve as the backbone for a broad spectrum of Advanced Accelerator R&D (AARD) experiments, and as such, must be designed with signi cant exibility in mind, but without compromising cost e ciency. The nonlinear experiments at IOTA will include: achievement of a large nonlinear tune shift/spread without degradation of dynamic aperture; suppression of strong lattice resonances; study of stability of nonlinear systems to perturbations; and studies of di erent variants of nonlinear magnet design. The ring optics control has challenging requirements that reach or exceed the present state of the art. The development of a complete self-consistent design of the IOTA ring optics, meeting the demands of all planned AARD experiments, is presented. Of particular interest are the precise control for nonlinear integrable optics experiments and the transverse-to-longitudinal coupling and phase stability for the Optical Stochastic Cooling Experiment (OSC). Since the beam time-of- ight must be tightly controlled in the OSC section, studies of second order corrections in this section are presented.

  7. Effects of PEMFC operating parameters on the performance of an integrated ethanol processor

    Energy Technology Data Exchange (ETDEWEB)

    Francesconi, Javier A.; Mussati, Miguel C.; Aguirre, Pio A. [INGAR Instituto de Desarrollo y Diseno (CONICET-UTN), Avellaneda 3657, CP:S3002GJC, Santa Fe (Argentina)

    2010-06-15

    In this paper the performance of a complete fuel cell system processing ethanol fuel has been analyzed as a function of the main fuel cell operating parameters. The fuel processor is based on the steam reforming process, followed by high- and low-temperature shift reactors, and carbon monoxide preferential oxidation reactor, which are coupled to a polymeric fuel cell (PEMFC). The goal was to analyze and improve the fuel cell system performance by simulation techniques. PEMFC operation has been analyzed using an available parametric model, which was implemented within HYSYS environment software. Pinch Analysis concepts were used to investigate the process energy integration and determine the maximum efficiency minimizing ethanol consumption. The system performance was analyzed for the SR-12 Modular PEM Generator, the Ballard Mark V fuel cell and the BCS 500 W stack. The net system efficiency is dependent on the required power demand. Efficiency values higher than 50% at low loads and less than 30% at high power demands are computed. In addition, the effect of fuel cell temperature, pressure and hydrogen utilization was analyzed. The trade-off between the reformer yield and the fuel cell performance defines the optimal operation pressure. The cell temperature determines operating zones where the water, involved in the reforming reactions, can be produced or demanded. (author)

  8. Development of a highly reliable CRT processor

    International Nuclear Information System (INIS)

    Shimizu, Tomoya; Saiki, Akira; Hirai, Kenji; Jota, Masayoshi; Fujii, Mikiya

    1996-01-01

    Although CRT processors have been employed by the main control board to reduce the operator's workload during monitoring, the control systems are still operated by hardware switches. For further advancement, direct controller operation through a display device is expected. A CRT processor providing direct controller operation must be as reliable as the hardware switches are. The authors are developing a new type of highly reliable CRT processor that enables direct controller operations. In this paper, we discuss the design principles behind a highly reliable CRT processor. The principles are defined by studies of software reliability and of the functional reliability of the monitoring and operation systems. The functional configuration of an advanced CRT processor is also addressed. (author)

  9. Computer Generated Inputs for NMIS Processor Verification

    International Nuclear Information System (INIS)

    J. A. Mullens; J. E. Breeding; J. A. McEvers; R. W. Wysor; L. G. Chiang; J. R. Lenarduzzi; J. T. Mihalczo; J. K. Mattingly

    2001-01-01

    Proper operation of the Nuclear Identification Materials System (NMIS) processor can be verified using computer-generated inputs [BIST (Built-In-Self-Test)] at the digital inputs. Preselected sequences of input pulses to all channels with known correlation functions are compared to the output of the processor. These types of verifications have been utilized in NMIS type correlation processors at the Oak Ridge National Laboratory since 1984. The use of this test confirmed a malfunction in a NMIS processor at the All-Russian Scientific Research Institute of Experimental Physics (VNIIEF) in 1998. The NMIS processor boards were returned to the U.S. for repair and subsequently used in NMIS passive and active measurements with Pu at VNIIEF in 1999

  10. A Geometric Algebra Co-Processor for Color Edge Detection

    Directory of Open Access Journals (Sweden)

    Biswajit Mishra

    2015-01-01

    Full Text Available This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA co-processor implemented on an Application Specific Integrated Circuit (ASIC. GA provides a rich set of geometric operations, giving the advantage that many signal and image processing operations become straightforward and the algorithms intuitive to design. The use of GA allows images to be represented with the three R, G, B color channels defined as a single entity, rather than separate quantities. A novel custom ASIC is proposed and fabricated that directly targets GA operations and results in significant performance improvement for color edge detection. Use of the hardware described in this paper also shows that the convolution operation with the rotor masks within GA belongs to a class of linear vector filters and can be applied to image or speech signals. The contribution of the proposed approach has been demonstrated by implementing three different types of edge detection schemes on the proposed hardware. The overall performance gains using the proposed GA Co-Processor over existing software approaches are more than 3.2× faster than GAIGEN and more than 2800× faster than GABLE. The performance of the fabricated GA co-processor is approximately an order of magnitude faster than previously published results for hardware implementations.

  11. 3081//sub E/ processor

    International Nuclear Information System (INIS)

    Kunz, P.F.; Gravina, M.; Oxoby, G.; Trang, Q.; Fucci, A.; Jacobs, D.; Martin, B.; Storr, K.

    1983-03-01

    Since the introduction of the 168//sub E/, emulating processors have been successful over an amazingly wide range of applications. This paper will describe a second generation processor, the 3081//sub E/. This new processor, which is being developed as a collaboration between SLAC and CERN, goes beyond just fixing the obvious faults of the 168//sub E/. Not only will the 3081//sub E/ have much more memory space, incorporate many more IBM instructions, and have much more memory space, incorporate many more IBM instructions, and have full double precision floating point arithmetic, but it will also have faster execution times and be much simpler to build, debug, and maintain. The simple interface and reasonable cost of the 168//sub E/ will be maintained for the 3081//sub E/

  12. Multimode power processor

    Science.gov (United States)

    O'Sullivan, George A.; O'Sullivan, Joseph A.

    1999-01-01

    In one embodiment, a power processor which operates in three modes: an inverter mode wherein power is delivered from a battery to an AC power grid or load; a battery charger mode wherein the battery is charged by a generator; and a parallel mode wherein the generator supplies power to the AC power grid or load in parallel with the battery. In the parallel mode, the system adapts to arbitrary non-linear loads. The power processor may operate on a per-phase basis wherein the load may be synthetically transferred from one phase to another by way of a bumpless transfer which causes no interruption of power to the load when transferring energy sources. Voltage transients and frequency transients delivered to the load when switching between the generator and battery sources are minimized, thereby providing an uninterruptible power supply. The power processor may be used as part of a hybrid electrical power source system which may contain, in one embodiment, a photovoltaic array, diesel engine, and battery power sources.

  13. Radiation-induced attenuation in integrated optical materials

    International Nuclear Information System (INIS)

    Evans, B.D.

    1989-01-01

    This paper reports that three materials commonly employed in opto-electronic integrated circuits evaluated for radiation-induced optical attenuation in the range 300 nm to 3000 nm. These include optically clear epoxy and crystalline lithium niobate after Co-60 exposure and crystalline tellurium dioxide after mixed gamma/fast-neutron exposure. In all these materials, however, induced loss was restricted to shorter wavelengths; attenuation induced at the telecommunications windows near 850, 1300 and 1550 nm was <0.1 dB/cm

  14. Integrated optics and optoelectronics II; Proceedings of the Meeting, San Jose, CA, Sept. 17-19, 1990

    International Nuclear Information System (INIS)

    Wong, Ka-Kha

    1991-01-01

    The present volume on integrated optics and optoelectronics discusses proton- and ion-exchange technologies, radiation effects on GaAs optical system FET devices and on the dynamical behavior of LiNbO3 switching devices, advanced lightwave components and concepts, advanced optical interconnects concepts, advanced aircraft and engine control, IOCs for fiber-optic gyroscopes, and commercial integrated optical devices. Attention is given to integrated optical devices for high-data-rate serial-to-parallel conversion, the design of novel integrated optic devices using depressed index waveguides, and a low-loss L-band microwave fiber-optic link for control of a T/R module. Topics addressed include the temperature and modulation dependence of spectral linewidth in distributed Bragg reflector laser diodes, length-minimization design considerations in photonic integrated circuits incorporating directional couplers, and the photochemical formation of polymeric optical waveguides and devices for optical interconnection applications

  15. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  16. PixonVision real-time video processor

    Science.gov (United States)

    Puetter, R. C.; Hier, R. G.

    2007-09-01

    PixonImaging LLC and DigiVision, Inc. have developed a real-time video processor, the PixonVision PV-200, based on the patented Pixon method for image deblurring and denoising, and DigiVision's spatially adaptive contrast enhancement processor, the DV1000. The PV-200 can process NTSC and PAL video in real time with a latency of 1 field (1/60 th of a second), remove the effects of aerosol scattering from haze, mist, smoke, and dust, improve spatial resolution by up to 2x, decrease noise by up to 6x, and increase local contrast by up to 8x. A newer version of the processor, the PV-300, is now in prototype form and can handle high definition video. Both the PV-200 and PV-300 are FPGA-based processors, which could be spun into ASICs if desired. Obvious applications of these processors include applications in the DOD (tanks, aircraft, and ships), homeland security, intelligence, surveillance, and law enforcement. If developed into an ASIC, these processors will be suitable for a variety of portable applications, including gun sights, night vision goggles, binoculars, and guided munitions. This paper presents a variety of examples of PV-200 processing, including examples appropriate to border security, battlefield applications, port security, and surveillance from unmanned aerial vehicles.

  17. Crosstalk performance of integrated optical cross-connects

    NARCIS (Netherlands)

    Herben, C.G.P.; Leijtens, X.J.M.; Maat, D.H.P.; Blok, H.; Smit, M.K.

    1999-01-01

    Crosstalk performance of monolithically integrated multiwavelength optical cross-connects (OXC's) depends strongly on their architecture. In this paper, a semiquantitative analysis of crosstalk in 11 different architectures is presented. Two architectures are analyzed numerically in more detail and

  18. Processors and systems (picture processing)

    Energy Technology Data Exchange (ETDEWEB)

    Gemmar, P

    1983-01-01

    Automatic picture processing requires high performance computers and high transmission capacities in the processor units. The author examines the possibilities of operating processors in parallel in order to accelerate the processing of pictures. He therefore discusses a number of available processors and systems for picture processing and illustrates their capacities for special types of picture processing. He stresses the fact that the amount of storage required for picture processing is exceptionally high. The author concludes that it is as yet difficult to decide whether very large groups of simple processors or highly complex multiprocessor systems will provide the best solution. Both methods will be aided by the development of VLSI. New solutions have already been offered (systolic arrays and 3-d processing structures) but they also are subject to losses caused by inherently parallel algorithms. Greater efforts must be made to produce suitable software for multiprocessor systems. Some possibilities for future picture processing systems are discussed. 33 references.

  19. Special processor for in-core control systems

    International Nuclear Information System (INIS)

    Golovanov, M.N.; Duma, V.R.; Levin, G.L.; Mel'nikov, A.V.; Polikanin, A.V.; Filatov, V.P.

    1978-01-01

    The BUTs-20 special processor is discussed, designed to control the units of the in-core control equipment which are incorporated into the VECTOR communication channel, and to provide preliminary data processing prior to computer calculations. A set of instructions and flowsheet of the processor, organization of its communication with memories and other units of the system are given. The processor components: a control unit and an arithmetic logical unit are discussed. It is noted that the special processor permits more effective utilization of the computer time

  20. A high-speed digital signal processor for atmospheric radar, part 7.3A

    Science.gov (United States)

    Brosnahan, J. W.; Woodard, D. M.

    1984-01-01

    The Model SP-320 device is a monolithic realization of a complex general purpose signal processor, incorporating such features as a 32-bit ALU, a 16-bit x 16-bit combinatorial multiplier, and a 16-bit barrel shifter. The SP-320 is designed to operate as a slave processor to a host general purpose computer in applications such as coherent integration of a radar return signal in multiple ranges, or dedicated FFT processing. Presently available is an I/O module conforming to the Intel Multichannel interface standard; other I/O modules will be designed to meet specific user requirements. The main processor board includes input and output FIFO (First In First Out) memories, both with depths of 4096 W, to permit asynchronous operation between the source of data and the host computer. This design permits burst data rates in excess of 5 MW/s.

  1. Integrated control platform for converged optical and wireless networks

    DEFF Research Database (Denmark)

    Yan, Ying

    The next generation of broadband access networks is expected to be heterogeneous. Multiple wired and wireless systems can be integrated, in order to simultaneously provide seamless access with an appropriate Quality of Service (QoS). Wireless networks support ubiquitous connectivity yet low data...... rates, whereas optical networks can offer much higher data rates but only provide fixed connection structures. Their complementary characteristics make the integration of the two networks a promising trend for next generation networks. With combined strengths, the converged network will provide both...... the complementary characteristics of the optical networks and the wireless networks, addresses motivations for their interworking, discusses the current progress in hybrid network architectures as well as the functionalities of a control system, and identifies the achieved research contributions in the integrated...

  2. Integration of Magneto-Optical Materials for Novel Optical Devices & Magnetophotonic Crystals, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — This work proposes to capitalize on our Phase I success in monolithically integrating magneto-optic and magnetic materials with semiconductor platforms in order to...

  3. Integrated optical isolators based on two-mode interference couplers

    International Nuclear Information System (INIS)

    Sun, Yiling; Zhou, Haifeng; Jiang, Xiaoqing; Hao, Yinlei; Yang, Jianyi; Wang, Minghua

    2010-01-01

    This paper presents an optical waveguide isolator based on two-mode interference (TMI) couplers, by utilizing the magneto-optical nonreciprocal phase shift (NPS). The operating principle of this device is to utilize the difference between the nonreciprocal phase shifts of the two lowest-order modes. A two-dimensional (2D) semi-vectorial finite difference method is used to calculate the difference between the nonreciprocal phase shifts of the two lowest-order modes and optimize the parameters. The proposed device may play an important role in integrated optical devices and optical communication systems

  4. A scalable single-chip multi-processor architecture with on-chip RTOS kernel

    NARCIS (Netherlands)

    Theelen, B.D.; Verschueren, A.C.; Reyes Suarez, V.V.; Stevens, M.P.J.; Nunez, A.

    2003-01-01

    Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is the complexity of their on-chip interconnects and memory architecture. It is furthermore unclear at what level software should be integrated. An example of a

  5. Proposal of a uniform fiber Bragg grating as an ultrafast all-optical integrator.

    Science.gov (United States)

    Azaña, José

    2008-01-01

    It is demonstrated that a uniform fiber Bragg grating (FBG) working in the linear regime inherently behaves as an optical temporal integrator over a limited time window. Specifically, the reflected temporal waveform from a weak-coupling uniform FBG is proportional to the time integral of an (arbitrary) optical pulse launched at the component input. This integration extends over a time window fixed by the duration of the squarelike temporal impulse response of the FBG. Ultrafast all-optical integrators capable of accurate operation over nanosecond time windows can be implemented using readily feasible FBGs. The introduced concepts are demonstrated by numerical simulations.

  6. Directional radiation of Babinet-inverted optical nanoantenna integrated with plasmonic waveguide

    Science.gov (United States)

    Kim, Jineun; Roh, Young-Geun; Cheon, Sangmo; Jeong Kim, Un; Hwang, Sung Woo; Park, Yeonsang; Lee, Chang-Won

    2015-07-01

    We present a Babinet-inverted optical nanoantenna integrated with a plasmonic waveguide. Using an integrated nanoantenna, we can couple the plasmon guide mode in a metal-insulator-metal (MIM) structure into the resonant antenna feed directly. The resonantly excited feed slot then radiates to free space and generates a magnetic dipole-like far-field pattern. The coupling efficiency of the integrated nanoantenna is calculated as being approximately 19% using a three-dimensional finite-difference time-domain (3D FDTD) simulation. By adding an auxiliary groove structure along with the feed, the radiation direction can be controlled similar to an optical Yagi-Uda antenna. We also determine, both theoretically and experimentally, that groove depth plays a significant role to function groove structure as a reflector or a director. The demonstrated Babinet-inverted optical nanoantenna integrated with a plasmonic waveguide can be used as a “plasmonic via” in plasmonic nanocircuits.

  7. Integrated optical interrogation of micro-structures

    Science.gov (United States)

    Evans, III, Boyd M.; Datskos, Panagiotis G.; Rajic, Slobodan

    2003-01-01

    The invention is an integrated optical sensing element for detecting and measuring changes in position or deflection. A deflectable member, such as a microcantilever, is configured to receive a light beam. A waveguide, such as an optical waveguide or an optical fiber, is positioned to redirect light towards the deflectable member. The waveguide can be incorporated into the deflectable member or disposed adjacent to the deflectable member. Means for measuring the extent of position change or deflection of the deflectable member by receiving the light beam from the deflectable member, such as a photodetector or interferometer, receives the reflected light beam from the deflectable member. Changes in the light beam are correlated to the changes in position or deflection of the deflectable member. A plurality of deflectable members can be arranged in a matrix or an array to provide one or two-dimensional imaging or sensing capabilities.

  8. Bank switched memory interface for an image processor

    International Nuclear Information System (INIS)

    Barron, M.; Downward, J.

    1980-09-01

    A commercially available image processor is interfaced to a PDP-11/45 through an 8K window of memory addresses. When the image processor was not in use it was desired to be able to use the 8K address space as real memory. The standard method of accomplishing this would have been to use UNIBUS switches to switch in either the physical 8K bank of memory or the image processor memory. This method has the disadvantage of being rather expensive. As a simple alternative, a device was built to selectively enable or disable either an 8K bank of memory or the image processor memory. To enable the image processor under program control, GEN is contracted in size, the memory is disabled, a device partition for the image processor is created above GEN, and the image processor memory is enabled. The process is reversed to restore memory to GEN. The hardware to enable/disable the image and computer memories is controlled using spare bits from a DR-11K output register. The image processor and physical memory can be switched in or out on line with no adverse affects on the system's operation

  9. The ATLAS Muon to Central Trigger Processor Interface Upgrade for the Run 3 of the LHC

    CERN Document Server

    Armbruster, Aaron James; The ATLAS collaboration; Chelstowska, Magda Anna

    2017-01-01

    To cope with the higher luminosity and physics cross-sections for the third run of the Large Hadron Collider (LHC) and beyond, the Trigger and Data Acquisition (TDAQ) system of ATLAS experiment at CERN is being upgraded. Part of the TDAQ system, the Muon to Central Trigger Processor Interface (MUCTPI) receives muon candidates information from each of the 208 barrel and endcap muon trigger sectors, counts muon candidates for each transverse momentum threshold and sends the result to the Central Trigger Processor (CTP). The MUCTPI takes into account the possible overlap between trigger sectors in order to avoid double counting of muon candidates. A full redesign and replacement of the existing MUCTPI is required in order to provide full-granularity muon position information at the bunch crossing rate to the Topological Trigger processor (L1Topo) and to be able to interface with the new sector logic modules. State-of-the-art FPGA technology and high-density ribbon fiber-optic transmitters and receivers is being...

  10. The ATLAS Muon-to-Central Trigger Processor Interface Upgrade for the Run 3 of the LHC

    CERN Document Server

    Armbruster, Aaron James; The ATLAS collaboration

    2017-01-01

    To cope with the higher luminosity and physics cross-sections for the third run of the Large Hadron Collider (LHC) and beyond, the Trigger and Data Acquisition (TDAQ) system of ATLAS experiment at CERN is being upgraded. Part of the TDAQ system, the Muon to Central Trigger Processor Interface (MUCTPI) receives muon candidates information from each of the 208 barrel and endcap muon trigger sectors, counts muon candidates for each transverse momentum threshold and sends the result to the Central Trigger Processor (CTP). The MUCTPI takes into account the possible overlap between trigger sectors in order to avoid double counting of muon candidates. A full redesign and replacement of the existing MUCTPI is required in order to provide full-granularity muon position information at the bunch crossing rate to the Topological Trigger processor (L1Topo) and to be able to interface with the new sector logic modules. State-of-the-art FPGA technology and high-density ribbon fiber-optic transmitters and receivers is being...

  11. VON WISPR Family Processors: Volume 1

    National Research Council Canada - National Science Library

    Wagstaff, Ronald

    1997-01-01

    ...) and the background noise they are embedded in. Processors utilizing those fluctuations such as the von WISPR Family Processors discussed herein, are methods or algorithms that preferentially attenuate the fluctuating signals and noise...

  12. The design of a graphics processor

    International Nuclear Information System (INIS)

    Holmes, M.; Thorne, A.R.

    1975-12-01

    The design of a graphics processor is described which takes into account known and anticipated user requirements, the availability of cheap minicomputers, the state of integrated circuit technology, and the overall need to minimise cost for a given performance. The main user needs are the ability to display large high resolution pictures, and to dynamically change the user's view in real time by means of fast coordinate processing hardware. The transformations that can be applied to 2D or 3D coordinates either singly or in combination are: translation, scaling, mirror imaging, rotation, and the ability to map the transformation origin on to any point on the screen. (author)

  13. Cryogenic Fiber Optic Assemblies for Spaceflight Environments: Design, Manufacturing, Testing, and Integration

    Science.gov (United States)

    Thomes, W. Joe; Ott, Melanie N.; Chuska, Richard; Switzer, Robert; Onuma, Eleanya; Blair, Diana; Frese, Erich; Matyseck, Marc

    2016-01-01

    Fiber optic assemblies have been used on spaceflight missions for many years as an enabling technology for routing, transmitting, and detecting optical signals. Due to the overwhelming success of NASA in implementing fiber optic assemblies on spaceflight science-based instruments, system scientists increasingly request fibers that perform in extreme environments while still maintaining very high optical transmission, stability, and reliability. Many new applications require fiber optic assemblies that will operate down to cryogenic temperatures as low as 20 Kelvin. In order for the fiber assemblies to operate with little loss in optical throughput at these extreme temperatures requires a system level approach all the way from how the fiber assembly is manufactured to how it is held, routed, and integrated. The NASA Goddard Code 562 Photonics Group has been designing, manufacturing, testing, and integrating fiber optics for spaceflight and other high reliability applications for nearly 20 years. Design techniques and lessons learned over the years are consistently applied to developing new fiber optic assemblies that meet these demanding environments. System level trades, fiber assembly design methods, manufacturing, testing, and integration will be discussed. Specific recent examples of ground support equipment for the James Webb Space Telescope (JWST); the Ice, Cloud and Land Elevation Satellite-2 (ICESat-2); and others will be included.

  14. Integrated Quantum Optics: Experiments towards integrated quantum-light sources and quantum-enhanced sensing

    DEFF Research Database (Denmark)

    Hoff, Ulrich Busk

    The work presented in this thesis is focused on experimental application and generation of continuous variable quantum correlated states of light in integrated dielectric structures. Squeezed states are among the most exploited continuous variable optical states for free-space quantum-enhanced se...... is presented and an optimized device design is proposed. The devices have been fabricated and tested optically and preliminary interrogations of the output quantum noise have been performed....

  15. 40-Gb/s all-optical processing systems using hybrid photonic integration technology

    NARCIS (Netherlands)

    Kehayas, E.; Tsiokos, D.; Bakapoulos, P.; Apostolopoulos, D.; Petrantonakis, D.; Stampoulidis, L.; Poustie, A.; McDougall, R.; Maxwell, G.D.; Liu, Y.; Zhang, S.; Dorren, H.J.S.; Seoane, J.; Van Holm-Nielsen, P.; Jeppesen, P.; Avramopoulos, H.

    2006-01-01

    This paper presents an experimental performance characterization of all-optical subsystems at 40 Gb/s using interconnected hybrid integrated all-optical semiconductor optical amplifier (SOA) Mach-Zehnder interferometer (MZI) gates and flip-flop prototypes. It was shown that optical gates can be

  16. Many - body simulations using an array processor

    International Nuclear Information System (INIS)

    Rapaport, D.C.

    1985-01-01

    Simulations of microscopic models of water and polypeptides using molecular dynamics and Monte Carlo techniques have been carried out with the aid of an FPS array processor. The computational techniques are discussed, with emphasis on the development and optimization of the software to take account of the special features of the processor. The computing requirements of these simulations exceed what could be reasonably carried out on a normal 'scientific' computer. While the FPS processor is highly suited to the kinds of models described, several other computationally intensive problems in statistical mechanics are outlined for which alternative processor architectures are more appropriate

  17. Matrix-vector multiplication using digital partitioning for more accurate optical computing

    Science.gov (United States)

    Gary, C. K.

    1992-01-01

    Digital partitioning offers a flexible means of increasing the accuracy of an optical matrix-vector processor. This algorithm can be implemented with the same architecture required for a purely analog processor, which gives optical matrix-vector processors the ability to perform high-accuracy calculations at speeds comparable with or greater than electronic computers as well as the ability to perform analog operations at a much greater speed. Digital partitioning is compared with digital multiplication by analog convolution, residue number systems, and redundant number representation in terms of the size and the speed required for an equivalent throughput as well as in terms of the hardware requirements. Digital partitioning and digital multiplication by analog convolution are found to be the most efficient alogrithms if coding time and hardware are considered, and the architecture for digital partitioning permits the use of analog computations to provide the greatest throughput for a single processor.

  18. Ultrahigh-speed hybrid laser for silicon photonic integrated chips

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

    2013-01-01

    Increasing power consumption for electrical interconnects between and inside chips is posing a real challenge to continue the performance scaling of processors/computers as predicted by D. Moore. In recent processors, energy consumption for electrical interconnects is half of power supplied...... and will be 80% in near future. This challenge strongly has motivated replacing electrical interconnects with optical ones even in chip level communications [1]. This chip-level optical interconnects need quite different performance of optoelectronic devices than required for conventional optical communications....... For a light source, the energy consumption per sending a bit is required to be

  19. Development of a software interface for optical disk archival storage for a new life sciences flight experiments computer

    Science.gov (United States)

    Bartram, Peter N.

    1989-01-01

    The current Life Sciences Laboratory Equipment (LSLE) microcomputer for life sciences experiment data acquisition is now obsolete. Among the weaknesses of the current microcomputer are small memory size, relatively slow analog data sampling rates, and the lack of a bulk data storage device. While life science investigators normally prefer data to be transmitted to Earth as it is taken, this is not always possible. No down-link exists for experiments performed in the Shuttle middeck region. One important aspect of a replacement microcomputer is provision for in-flight storage of experimental data. The Write Once, Read Many (WORM) optical disk was studied because of its high storage density, data integrity, and the availability of a space-qualified unit. In keeping with the goals for a replacement microcomputer based upon commercially available components and standard interfaces, the system studied includes a Small Computer System Interface (SCSI) for interfacing the WORM drive. The system itself is designed around the STD bus, using readily available boards. Configurations examined were: (1) master processor board and slave processor board with the SCSI interface; (2) master processor with SCSI interface; (3) master processor with SCSI and Direct Memory Access (DMA); (4) master processor controlling a separate STD bus SCSI board; and (5) master processor controlling a separate STD bus SCSI board with DMA.

  20. Multi-processor network implementations in Multibus II and VME

    International Nuclear Information System (INIS)

    Briegel, C.

    1992-01-01

    ACNET (Fermilab Accelerator Controls Network), a proprietary network protocol, is implemented in a multi-processor configuration for both Multibus II and VME. The implementations are contrasted by the bus protocol and software design goals. The Multibus II implementation provides for multiple processors running a duplicate set of tasks on each processor. For a network connected task, messages are distributed by a network round-robin scheduler. Further, messages can be stopped, continued, or re-routed for each task by user-callable commands. The VME implementation provides for multiple processors running one task across all processors. The process can either be fixed to a particular processor or dynamically allocated to an available processor depending on the scheduling algorithm of the multi-processing operating system. (author)

  1. Integrated optical circuit engineering IV; Proceedings of the Meeting, Cambridge, MA, Sept. 16, 17, 1986

    Science.gov (United States)

    Mentzer, Mark A.; Sriram, S.

    The design and implementation of integrated optical circuits are discussed in reviews and reports. Topics addressed include lithium niobate devices, silicon integrated optics, waveguide phenomena, coupling considerations, processing technology, nonlinear guided-wave optics, integrated optics for fiber systems, and systems considerations and applications. Also included are eight papers and a panel discussion from an SPIE conference on the processing of guided-wave optoelectronic materials (held in Los Angeles, CA, on January 21-22, 1986).

  2. Integration of optical imaging with a small animal irradiator

    International Nuclear Information System (INIS)

    Weersink, Robert A.; Ansell, Steve; Wang, An; Wilson, Graham; Shah, Duoaud; Lindsay, Patricia E.; Jaffray, David A.

    2014-01-01

    Purpose: The authors describe the integration of optical imaging with a targeted small animal irradiator device, focusing on design, instrumentation, 2D to 3D image registration, 2D targeting, and the accuracy of recovering and mapping the optical signal to a 3D surface generated from the cone-beam computed tomography (CBCT) imaging. The integration of optical imaging will improve targeting of the radiation treatment and offer longitudinal tracking of tumor response of small animal models treated using the system. Methods: The existing image-guided small animal irradiator consists of a variable kilovolt (peak) x-ray tube mounted opposite an aSi flat panel detector, both mounted on a c-arm gantry. The tube is used for both CBCT imaging and targeted irradiation. The optical component employs a CCD camera perpendicular to the x-ray treatment/imaging axis with a computer controlled filter for spectral decomposition. Multiple optical images can be acquired at any angle as the gantry rotates. The optical to CBCT registration, which uses a standard pinhole camera model, was modeled and tested using phantoms with markers visible in both optical and CBCT images. Optically guided 2D targeting in the anterior/posterior direction was tested on an anthropomorphic mouse phantom with embedded light sources. The accuracy of the mapping of optical signal to the CBCT surface was tested using the same mouse phantom. A surface mesh of the phantom was generated based on the CBCT image and optical intensities projected onto the surface. The measured surface intensity was compared to calculated surface for a point source at the actual source position. The point-source position was also optimized to provide the closest match between measured and calculated intensities, and the distance between the optimized and actual source positions was then calculated. This process was repeated for multiple wavelengths and sources. Results: The optical to CBCT registration error was 0.8 mm. Two

  3. An integrated nonlinear optical loop mirror in silicon photonics for all-optical signal processing

    Directory of Open Access Journals (Sweden)

    Zifei Wang

    2018-02-01

    Full Text Available The nonlinear optical loop mirror (NOLM has been studied for several decades and has attracted considerable attention for applications in high data rate optical communications and all-optical signal processing. The majority of NOLM research has focused on silica fiber-based implementations. While various fiber designs have been considered to increase the nonlinearity and manage dispersion, several meters to hundreds of meters of fiber are still required. On the other hand, there is increasing interest in developing photonic integrated circuits for realizing signal processing functions. In this paper, we realize the first-ever passive integrated NOLM in silicon photonics and demonstrate its application for all-optical signal processing. In particular, we show wavelength conversion of 10 Gb/s return-to-zero on-off keying (RZ-OOK signals over a wavelength range of 30 nm with error-free operation and a power penalty of less than 2.5 dB, we achieve error-free nonreturn to zero (NRZ-to-RZ modulation format conversion at 10 Gb/s also with a power penalty of less than 2.8 dB, and we obtain error-free all-optical time-division demultiplexing of a 40 Gb/s RZ-OOK data signal into its 10 Gb/s tributary channels with a maximum power penalty of 3.5 dB.

  4. Integrated semiconductor twin-microdisk laser under mutually optical injection

    Energy Technology Data Exchange (ETDEWEB)

    Zou, Ling-Xiu; Liu, Bo-Wen; Lv, Xiao-Meng; Yang, Yue-De; Xiao, Jin-Long; Huang, Yong-Zhen, E-mail: yzhuang@semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2015-05-11

    We experimentally study the characteristics of an integrated semiconductor twin-microdisk laser under mutually optical injection through a connected optical waveguide. Based on the lasing spectra, four-wave mixing, injection locking, and period-two oscillation states are observed due to the mutually optical injection by adjusting the injected currents applied to the two microdisks. The enhanced 3 dB bandwidth is realized for the microdisk laser at the injection locking state, and photonic microwave is obtained from the electrode of the microdisk laser under the period-two oscillation state. The plentifully dynamical states similar as semiconductor lasers subject to external optical injection are realized due to strong optical interaction between the two microdisks.

  5. Towards a fully integrated optical gyroscope using whispering gallery modes resonators

    Science.gov (United States)

    Amrane, T.; Jager, J.-B.; Jager, T.; Calvo, V.; Léger, J.-M.

    2017-11-01

    Since the developments of lasers and the optical fibers in the 70s, the optical gyroscopes have been subject to an intensive research to improve both their resolution and stability performances. However the best optical gyroscopes currently on the market, the ring laser gyroscope and the interferometer fiber optic gyroscope are still macroscopic devices and cannot address specific applications where size and weight constraints are critical. One solution to overcome these limitations could be to use an integrated resonator as a sensitive part to build a fully Integrated Optical Resonant Gyroscope (IORG). To keep a high rotation sensitivity, which is usually degraded when downsizing this kind of optical sensors based on the Sagnac effect, the resonator has to exhibit a very high quality factor (Q): as detailed in equation (1) where the minimum rotation rate resolution for an IORG is given as a function of the resonator characteristics (Q and diameter D) and of the global system optical system characteristics (i.e. SNR and bandwidth B), the higher the Q×D product, the lower the resolution.

  6. Optical integration of Pancharatnam-Berry phase lens and dynamical phase lens

    International Nuclear Information System (INIS)

    Ke, Yougang; Liu, Yachao; Zhou, Junxiao; Liu, Yuanyuan; Luo, Hailu; Wen, Shuangchun

    2016-01-01

    In the optical system, most elements such as lens, prism, and optical fiber are made of silica glass. Therefore, integrating Pancharatnam-Berry phase elements into silica glass has potential applications in the optical system. In this paper, we take a lens, for example, which integrates a Pancharatnam-Berry phase lens into a conventional plano-convex lens. The spin states and positions of focal points can be modulated by controlling the polarization states of the incident beam. The proposed lens has a high transmission efficiency, and thereby acts as a simple and powerful tool to manipulate spin photons. Furthermore, the method can be conveniently extended to the optical fiber and laser cavity, and may provide a route to the design of the spin-photonic devices.

  7. Evaluation of the Intel Sandy Bridge-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2012-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing an 8-core “Sandy Bridge-EP” processor with Intel’s previous microarchitecture, the “Westmere-EP”. The Intel marketing names for these processors are “Xeon E5-2600 processor series” and “Xeon 5600 processor series”, respectively. Both processors are produced in a 32nm process, and both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores ...

  8. Array processors based on Gaussian fraction-free method

    Energy Technology Data Exchange (ETDEWEB)

    Peng, S; Sedukhin, S [Aizu Univ., Aizuwakamatsu, Fukushima (Japan); Sedukhin, I

    1998-03-01

    The design of algorithmic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements and computing time. (author)

  9. Fluorescence monitoring of capillary electrophoresis separation of biomolecules with monolithically integrated optical waveguides

    NARCIS (Netherlands)

    Dongre, C.; Dekker, R.; Hoekstra, Hugo; Martinez-Vazquez, R.; Osellame, R.; Ramponi, R.; Cerullo, G.; van Weeghel, R.; Besselink, G.A.J.; van den Vlekkert, H.H.; Pollnau, Markus

    2009-01-01

    Monolithic integration of optical waveguides in a commercial lab-on-a-chip by femtosecond-laser material processing enables arbitrary 3D geometries of optical sensing structures in combination with fluidic microchannels. Integrated fluorescence monitoring of molecular separation, as applicable in

  10. Multiple Embedded Processors for Fault-Tolerant Computing

    Science.gov (United States)

    Bolotin, Gary; Watson, Robert; Katanyoutanant, Sunant; Burke, Gary; Wang, Mandy

    2005-01-01

    A fault-tolerant computer architecture has been conceived in an effort to reduce vulnerability to single-event upsets (spurious bit flips caused by impingement of energetic ionizing particles or photons). As in some prior fault-tolerant architectures, the redundancy needed for fault tolerance is obtained by use of multiple processors in one computer. Unlike prior architectures, the multiple processors are embedded in a single field-programmable gate array (FPGA). What makes this new approach practical is the recent commercial availability of FPGAs that are capable of having multiple embedded processors. A working prototype (see figure) consists of two embedded IBM PowerPC 405 processor cores and a comparator built on a Xilinx Virtex-II Pro FPGA. This relatively simple instantiation of the architecture implements an error-detection scheme. A planned future version, incorporating four processors and two comparators, would correct some errors in addition to detecting them.

  11. Online track processor for the CDF upgrade

    International Nuclear Information System (INIS)

    Thomson, E. J.

    2002-01-01

    A trigger track processor, called the eXtremely Fast Tracker (XFT), has been designed for the CDF upgrade. This processor identifies high transverse momentum (> 1.5 GeV/c) charged particles in the new central outer tracking chamber for CDF II. The XFT design is highly parallel to handle the input rate of 183 Gbits/s and output rate of 44 Gbits/s. The processor is pipelined and reports the result for a new event every 132 ns. The processor uses three stages: hit classification, segment finding, and segment linking. The pattern recognition algorithms for the three stages are implemented in programmable logic devices (PLDs) which allow in-situ modification of the algorithm at any time. The PLDs reside on three different types of modules. The complete system has been installed and commissioned at CDF II. An overview of the track processor and performance in CDF Run II are presented

  12. Design Principles for Synthesizable Processor Cores

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; McKee, Sally A.; Karlsson, Sven

    2012-01-01

    As FPGAs get more competitive, synthesizable processor cores become an attractive choice for embedded computing. Currently popular commercial processor cores do not fully exploit current FPGA architectures. In this paper, we propose general design principles to increase instruction throughput...

  13. Design and implementation of a high performance network security processor

    Science.gov (United States)

    Wang, Haixin; Bai, Guoqiang; Chen, Hongyi

    2010-03-01

    The last few years have seen many significant progresses in the field of application-specific processors. One example is network security processors (NSPs) that perform various cryptographic operations specified by network security protocols and help to offload the computation intensive burdens from network processors (NPs). This article presents a high performance NSP system architecture implementation intended for both internet protocol security (IPSec) and secure socket layer (SSL) protocol acceleration, which are widely employed in virtual private network (VPN) and e-commerce applications. The efficient dual one-way pipelined data transfer skeleton and optimised integration scheme of the heterogenous parallel crypto engine arrays lead to a Gbps rate NSP, which is programmable with domain specific descriptor-based instructions. The descriptor-based control flow fragments large data packets and distributes them to the crypto engine arrays, which fully utilises the parallel computation resources and improves the overall system data throughput. A prototyping platform for this NSP design is implemented with a Xilinx XC3S5000 based FPGA chip set. Results show that the design gives a peak throughput for the IPSec ESP tunnel mode of 2.85 Gbps with over 2100 full SSL handshakes per second at a clock rate of 95 MHz.

  14. Progress in high index contrast integrated optics

    NARCIS (Netherlands)

    Baets, R.G.F.; Bienstman, P.; Bogaerts, W.; Brouckaert, J.; De Backere, P.; Dumon, P.; Roelkens, G.; Scheerlinck, S.; Smit, M.K.; Taillaert, D.; Van Campenhout, J.; Van Laere, F.; Thourhout, Van D.

    2007-01-01

    A large fraction of the recent innovation in integrated optics is enabled by the use of high index contrast structures and devices. The strong confinement achievable in such devices allows for dramatic performance benefits and downscaling. In this paper the progress in this field is reviewed.

  15. Integrated optical sensors for the chemical domain

    NARCIS (Netherlands)

    Lambeck, Paul

    2006-01-01

    During the last decade there has been a rapidly growing interest in integrated optical (IO) sensors, expecially because many of them principally allow for sensitive, real time, label-free-on-site measurements of the concentration of (bio-)chemical species. This review aims at giving an overview of

  16. Data register and processor for multiwire chambers

    International Nuclear Information System (INIS)

    Karpukhin, V.V.

    1985-01-01

    A data register and a processor for data receiving and processing from drift chambers of a device for investigating relativistic positroniums are described. The data are delivered to the register input in the form of the Grey 8 bit code, memorized and transformed to a position code. The register information is delivered to the KAMAK trunk and to the front panel plug. The processor selects particle tracks in a horizontal plane of the facility. ΔY maximum coordinate divergence and minimum point quantity on the track are set from the processor front panel. Processor solution time is 16 μs maximum quantity of simultaneously analyzed coordinates is 16

  17. Evaluation of polymer based third order nonlinear integrated optics devices

    NARCIS (Netherlands)

    Driessen, A.; Hoekstra, Hugo; Blom, F.C.; Horst, F.; Horst, F.; Krijnen, Gijsbertus J.M.; van Schoot, J.B.P.; van Schoot, J.B.P.; Lambeck, Paul; Popma, T.J.A.; Diemeer, Mart

    Nonlinear polymers are promising materials for high speed active integrated optics devices. In this paper we evaluate the perspectives polymer based nonlinear optical devices can offer. Special attention is directed to the materials aspects. In our experimental work we applied mainly Akzo Nobel DANS

  18. Integrated optical readout for miniaturization of cantilever-based sensor system

    DEFF Research Database (Denmark)

    Nordström, Maria; Zauner, Dan; Calleja, Montserrat

    2007-01-01

    The authors present the fabrication and characterization of an integrated optical readout scheme based on single-mode waveguides for cantilever-based sensors. The cantilever bending is read out by monitoring changes in the optical intensity of light transmitted through the cantilever that also acts...

  19. Development methods for VLSI-processors

    International Nuclear Information System (INIS)

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  20. The performance of an LSI-11/23 with a SKYMNK-Q array processor as a high speed front end processor

    International Nuclear Information System (INIS)

    Clark, D.L.

    1983-01-01

    The NSRL has recently installed a VAX-11/750 based data acquisition system which is networked to two LSI-11/23 satellite processors. Each of the LSI's are connected to CAMAC branch drivers. The LSI's have small array processors installed for use in preprocessing data. The objective is to provide an easy to use high speed processor that will relieve the VAX of some of the real-time data analysis tasks. The basic operation of the array processor and some of the results of performance tests are described

  1. Embedded Processor Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — The Embedded Processor Laboratory provides the means to design, develop, fabricate, and test embedded computers for missile guidance electronics systems in support...

  2. Multi-Core Processor Memory Contention Benchmark Analysis Case Study

    Science.gov (United States)

    Simon, Tyler; McGalliard, James

    2009-01-01

    Multi-core processors dominate current mainframe, server, and high performance computing (HPC) systems. This paper provides synthetic kernel and natural benchmark results from an HPC system at the NASA Goddard Space Flight Center that illustrate the performance impacts of multi-core (dual- and quad-core) vs. single core processor systems. Analysis of processor design, application source code, and synthetic and natural test results all indicate that multi-core processors can suffer from significant memory subsystem contention compared to similar single-core processors.

  3. Architectural design and analysis of a programmable image processor

    International Nuclear Information System (INIS)

    Siyal, M.Y.; Chowdhry, B.S.; Rajput, A.Q.K.

    2003-01-01

    In this paper we present an architectural design and analysis of a programmable image processor, nicknamed Snake. The processor was designed with a high degree of parallelism to speed up a range of image processing operations. Data parallelism found in array processors has been included into the architecture of the proposed processor. The implementation of commonly used image processing algorithms and their performance evaluation are also discussed. The performance of Snake is also compared with other types of processor architectures. (author)

  4. Analysis of the control structures for an integrated ethanol processor for proton exchange membrane fuel cell systems

    Energy Technology Data Exchange (ETDEWEB)

    Biset, S; Nieto Deglioumini, L; Basualdo, M [GIAIP-CIFASIS (UTN-FRRo-CONICET-UPCAM-UNR), BV. 27 de Febrero 210 Bis, S2000EZP Rosario (Argentina); Garcia, V M; Serra, M [Institut de Robotica i Informatica Industrial, C. Llorens i Artigas 4-6, 08028 Barcelona (Spain)

    2009-07-01

    The aim of this work is to investigate which would be a good preliminary plantwide control structure for the process of Hydrogen production from bioethanol to be used in a proton exchange membrane (PEM) accounting only steady-state information. The objective is to keep the process under optimal operation point, that is doing energy integration to achieve the maximum efficiency. Ethanol, produced from renewable feedstocks, feeds a fuel processor investigated for steam reforming, followed by high- and low-temperature shift reactors and preferential oxidation, which are coupled to a polymeric fuel cell. Applying steady-state simulation techniques and using thermodynamic models the performance of the complete system with two different control structures have been evaluated for the most typical perturbations. A sensitivity analysis for the key process variables together with the rigorous operability requirements for the fuel cell are taking into account for defining acceptable plantwide control structure. This is the first work showing an alternative control structure applied to this kind of process. (author)

  5. Thermal/structural/optical integrated design for optical sensor mounted on unmanned aerial vehicle

    Science.gov (United States)

    Zhang, Gaopeng; Yang, Hongtao; Mei, Chao; Wu, Dengshan; Shi, Kui

    2016-01-01

    With the rapid development of science and technology and the promotion of many local wars in the world, altitude optical sensor mounted on unmanned aerial vehicle is more widely applied in the airborne remote sensing, measurement and detection. In order to obtain high quality image of the aero optical remote sensor, it is important to analysis its thermal-optical performance on the condition of high speed and high altitude. Especially for the key imaging assembly, such as optical window, the temperature variation and temperature gradient can result in defocus and aberrations in optical system, which will lead to the poor quality image. In order to improve the optical performance of a high speed aerial camera optical window, the thermal/structural/optical integrated design method is developed. Firstly, the flight environment of optical window is analyzed. Based on the theory of aerodynamics and heat transfer, the convection heat transfer coefficient is calculated. The temperature distributing of optical window is simulated by the finite element analysis software. The maximum difference in temperature of the inside and outside of optical window is obtained. Then the deformation of optical window under the boundary condition of the maximum difference in temperature is calculated. The optical window surface deformation is fitted in Zernike polynomial as the interface, the calculated Zernike fitting coefficients is brought in and analyzed by CodeV Optical Software. At last, the transfer function diagrams of the optical system on temperature field are comparatively analyzed. By comparing and analyzing the result, it can be obtained that the optical path difference caused by thermal deformation of the optical window is 138.2 nm, which is under PV ≤1 4λ . The above study can be used as an important reference for other optical window designs.

  6. Hardware Realization of an FPGA Processor - Operating System Call Offload and Experiences

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Karlsson, Sven

    2014-01-01

    core that can be integrated in many signal and data processing platforms on FPGAs. We also show how we allow the processor to use operating system services. For a set of SPLASH-2 and SPEC2006 benchmarks we show an speedup of up to 64% over a similar Xilinx MicroBlaze implementation while using 27...

  7. Optical System Design and Integration of the Mercury Laser Altimeter

    Science.gov (United States)

    Ramos-Izquierdo, Luis; Scott, V. Stanley, III; Schmidt, Stephen; Britt, Jamie; Mamakos, William; Trunzo, Raymond; Cavanaugh, John; Miller, Roger

    2005-01-01

    The Mercury Laser Altimeter (MLA). developed for the 2004 MESSENGER mission to Mercury, is designed to measure the planet's topography via laser ranging. A description of the MLA optical system and its measured optical performance during instrument-level and spacecraft-level integration and testing are presented.

  8. Analytical Bounds on the Threads in IXP1200 Network Processor

    OpenAIRE

    Ramakrishna, STGS; Jamadagni, HS

    2003-01-01

    Increasing link speeds have placed enormous burden on the processing requirements and the processors are expected to carry out a variety of tasks. Network Processors (NP) [1] [2] is the blanket name given to the processors, which are traded for flexibility and performance. Network Processors are offered by a number of vendors; to take the main burden of processing requirement of network related operations from the conventional processors. The Network Processors cover a spectrum of design trad...

  9. Compact optical system for measuring linear and angular displacement of solid structures

    DEFF Research Database (Denmark)

    Jakobsen, M.L.; Larsen, H.E.; Hanson, Steen Grüner

    2004-01-01

    and rotation of the target. The presented free space propagation design can provide a sensor with no direct sensitivity on the working distance. The electrical signals from the sensor are processed with a digital algorithm, based on zero-crossings detection to provide real-time displacement measurements....... The spatial filter of the sensor is characterized here, and the precision of the sensor, integrated with a processor, which applies zero-crossing detection to the signal, is considered. © 2004 COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted...

  10. A UNIX-based prototype biomedical virtual image processor

    International Nuclear Information System (INIS)

    Fahy, J.B.; Kim, Y.

    1987-01-01

    The authors have developed a multiprocess virtual image processor for the IBM PC/AT, in order to maximize image processing software portability for biomedical applications. An interprocess communication scheme, based on two-way metacode exchange, has been developed and verified for this purpose. Application programs call a device-independent image processing library, which transfers commands over a shared data bridge to one or more Autonomous Virtual Image Processors (AVIP). Each AVIP runs as a separate process in the UNIX operating system, and implements the device-independent functions on the image processor to which it corresponds. Application programs can control multiple image processors at a time, change the image processor configuration used at any time, and are completely portable among image processors for which an AVIP has been implemented. Run-time speeds have been found to be acceptable for higher level functions, although rather slow for lower level functions, owing to the overhead associated with sending commands and data over the shared data bridge

  11. T-SDN architecture for space and ground integrated optical transport network

    Science.gov (United States)

    Nie, Kunkun; Hu, Wenjing; Gao, Shenghua; Chang, Chengwu

    2015-11-01

    Integrated optical transport network is the development trend of the future space information backbone network. The space and ground integrated optical transport network(SGIOTN) may contain a variety of equipment and systems. Changing the network or meeting some innovation missions in the network will be an expensive implement. Software Defined Network(SDN) provides a good solution to flexibly adding process logic, timely control states and resources of the whole network, as well as shielding the differences of heterogeneous equipment and so on. According to the characteristics of SGIOTN, we propose an transport SDN architecture for it, with hierarchical control plane and data plane composed of packet networks and optical transport networks.

  12. The communication processor of TUMULT-64

    NARCIS (Netherlands)

    Smit, Gerardus Johannes Maria; Jansen, P.G.

    1988-01-01

    Tumult (Twente University MULTi-processor system) is a modular extendible multi-processor system designed and implemented at the Twente University of Technology in co-operation with Oce Nederland B.V. and the Dr. Neher Laboratories (Dutch PTT). Characteristics of the hardware are: MIMD type,

  13. High-Speed General Purpose Genetic Algorithm Processor.

    Science.gov (United States)

    Hoseini Alinodehi, Seyed Pourya; Moshfe, Sajjad; Saber Zaeimian, Masoumeh; Khoei, Abdollah; Hadidi, Khairollah

    2016-07-01

    In this paper, an ultrafast steady-state genetic algorithm processor (GAP) is presented. Due to the heavy computational load of genetic algorithms (GAs), they usually take a long time to find optimum solutions. Hardware implementation is a significant approach to overcome the problem by speeding up the GAs procedure. Hence, we designed a digital CMOS implementation of GA in [Formula: see text] process. The proposed processor is not bounded to a specific application. Indeed, it is a general-purpose processor, which is capable of performing optimization in any possible application. Utilizing speed-boosting techniques, such as pipeline scheme, parallel coarse-grained processing, parallel fitness computation, parallel selection of parents, dual-population scheme, and support for pipelined fitness computation, the proposed processor significantly reduces the processing time. Furthermore, by relying on a built-in discard operator the proposed hardware may be used in constrained problems that are very common in control applications. In the proposed design, a large search space is achievable through the bit string length extension of individuals in the genetic population by connecting the 32-bit GAPs. In addition, the proposed processor supports parallel processing, in which the GAs procedure can be run on several connected processors simultaneously.

  14. MEMS optical sensor

    DEFF Research Database (Denmark)

    2013-01-01

    The present invention relates to an all-optical sensor utilizing effective index modulation of a waveguide and detection of a wavelength shift of reflected light and a force sensing system accommodating said optical sensor. One embodiment of the invention relates to a sensor system comprising...... at least one multimode light source, one or more optical sensors comprising a multimode sensor optical waveguide accommodating a distributed Bragg reflector, at least one transmitting optical waveguide for guiding light from said at least one light source to said one or more multimode sensor optical...... waveguides, a detector for measuring light reflected from said Bragg reflector in said one or more multimode sensor optical waveguides, and a data processor adapted for analyzing variations in the Bragg wavelength of at least one higher order mode of the reflected light....

  15. Thin Film Magnetless Faraday Rotators for Compact Heterogeneous Integrated Optical Isolators (Postprint)

    Science.gov (United States)

    2017-06-15

    AFRL-RX-WP-JA-2017-0348 THIN-FILM MAGNETLESS FARADAY ROTATORS FOR COMPACT HETEROGENEOUS INTEGRATED OPTICAL ISOLATORS (POSTPRINT) Dolendra Karki...Interim 9 May 2016 – 1 December 2016 4. TITLE AND SUBTITLE THIN-FILM MAGNETLESS FARADAY ROTATORS FOR COMPACT HETEROGENEOUS INTEGRATED OPTICAL...transfer of ultra-compact thin-film magnetless Faraday rotators to silicon photonic substrates. Thin films of magnetization latching bismuth

  16. Lipsi: Probably the Smallest Processor in the World

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2018-01-01

    While research on high-performance processors is important, it is also interesting to explore processor architectures at the other end of the spectrum: tiny processor cores for auxiliary functions. While it is common to implement small circuits for such functions, such as a serial port, in dedica...... at a minimal cost....

  17. Recommending the heterogeneous cluster type multi-processor system computing

    International Nuclear Information System (INIS)

    Iijima, Nobukazu

    2010-01-01

    Real-time reactor simulator had been developed by reusing the equipment of the Musashi reactor and its performance improvement became indispensable for research tools to increase sampling rate with introduction of arithmetic units using multi-Digital Signal Processor(DSP) system (cluster). In order to realize the heterogeneous cluster type multi-processor system computing, combination of two kinds of Control Processor (CP) s, Cluster Control Processor (CCP) and System Control Processor (SCP), were proposed with Large System Control Processor (LSCP) for hierarchical cluster if needed. Faster computing performance of this system was well evaluated by simulation results for simultaneous execution of plural jobs and also pipeline processing between clusters, which showed the system led to effective use of existing system and enhancement of the cost performance. (T. Tanaka)

  18. IDENTIFICATIONS OF FIVE INTEGRAL SOURCES VIA OPTICAL SPECTROSCOPY

    International Nuclear Information System (INIS)

    Butler, Suzanne C.; Tomsick, John A.; Chaty, Sylvain; Heras, Juan A. Zurita; Rodriguez, Jerome; Walter, Roland; Kaaret, Philip; Kalemci, Emrah; Oezbey, Mehtap

    2009-01-01

    The International Gamma-Ray Astrophysics Laboratory (INTEGRAL) is discovering hundreds of new hard X-ray sources, many of which remain unidentified. We report on optical spectroscopy of five such sources for which X-ray observations at lower energies (∼0.5-10 keV) and higher angular resolutions than INTEGRAL have allowed for unique optical counterparts to be located. We find that INTEGRAL Gamma-Ray (IGR) J16426+6536 and IGR J22292+6647 are Type 1 Seyfert active galactic nuclei (with IGR J16426+6536 further classified as a Seyfert 1.5) which have redshifts of z = 0.323 and z = 0.113, respectively. IGR J18308-1232 is identified as a cataclysmic variable (CV), and we confirm a previous identification of IGR J19267+1325 as a magnetic CV. IGR J18214-1318 is identified as an obscured high-mass X-ray binary (HMXB), which are systems thought to have a compact object embedded in the stellar wind of a massive star. We combine Chandra fluxes with distances based on the optical observations to calculate X-ray luminosities of the HMXB and CVs, finding L 0.3-10keV = 5 x 10 36 erg s -1 for IGR J18214-1318, L 0.3-10keV = 1.3 x 10 32 erg s -1 for IGR J18308-1232, and L 0.3-10keV = 6.7 x 10 32 erg s -1 for IGR J19267+1325.

  19. Silicon-based optical integrated circuits for terabit communication networks

    International Nuclear Information System (INIS)

    Svidzinsky, K K

    2003-01-01

    A brief review is presented of the development of silicon-based optical integrated circuits used as components in modern all-optical communication networks with the terabit-per-second transmission capacity. The designs and technologies for manufacturing these circuits are described and the problems related to their development and application in WDM communication systems are considered. (special issue devoted to the memory of academician a m prokhorov)

  20. First level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    This paper discusses the design of the first level trigger processor for the ZEUS calorimeter. This processor accepts data from the 13,000 photomultipliers of the calorimeter which is topologically divided into 16 regions, and after regional preprocessing, performs logical and numerical operations which cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K ECL, Advanced CMOS discrete devices, and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2GB/s, and processed data flows from the processor to the Global First-Level Trigger at a rate of 700MB/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor. 2 refs., 3 figs

  1. First-level trigger processor for the ZEUS calorimeter

    International Nuclear Information System (INIS)

    Dawson, J.W.; Talaga, R.L.; Burr, G.W.; Laird, R.J.; Smith, W.; Lackey, J.

    1990-01-01

    The design of the first-level trigger processor for the Zeus calorimeter is discussed. This processor accepts data from the 13,000 photomultipliers of the calorimeter, which is topologically divided into 16 regions, and after regional preprocessing performs logical and numerical operations that cross regional boundaries. Because the crossing period at the HERA collider is 96 ns, it is necessary that first-level trigger decisions be made in pipelined hardware. One microsecond is allowed for the processor to perform the required logical and numerical operations, during which time the data from ten crossings would be resident in the processor while being clocked through the pipelined hardware. The circuitry is implemented in 100K emitter-coupled logic (ECL), advanced CMOS discrete devices and programmable gate arrays, and operates in a VME environment. All tables and registers are written/read from VME, and all diagnostic codes are executed from VME. Preprocessed data flows into the processor at a rate of 5.2 Gbyte/s, and processed data flows from the processor to the global first-level trigger at a rate of 70 Mbyte/s. The system allows for subsets of the logic to be configured by software and for various important variables to be histogrammed as they flow through the processor

  2. A digital retina-like low-level vision processor.

    Science.gov (United States)

    Mertoguno, S; Bourbakis, N G

    2003-01-01

    This correspondence presents the basic design and the simulation of a low level multilayer vision processor that emulates to some degree the functional behavior of a human retina. This retina-like multilayer processor is the lower part of an autonomous self-organized vision system, called Kydon, that could be used on visually impaired people with a damaged visual cerebral cortex. The Kydon vision system, however, is not presented in this paper. The retina-like processor consists of four major layers, where each of them is an array processor based on hexagonal, autonomous processing elements that perform a certain set of low level vision tasks, such as smoothing and light adaptation, edge detection, segmentation, line recognition and region-graph generation. At each layer, the array processor is a 2D array of k/spl times/m hexagonal identical autonomous cells that simultaneously execute certain low level vision tasks. Thus, the hardware design and the simulation at the transistor level of the processing elements (PEs) of the retina-like processor and its simulated functionality with illustrative examples are provided in this paper.

  3. The Trigger Processor and Trigger Processor Algorithms for the ATLAS New Small Wheel Upgrade

    CERN Document Server

    Lazovich, Tomo; The ATLAS collaboration

    2015-01-01

    The ATLAS New Small Wheel (NSW) is an upgrade to the ATLAS muon endcap detectors that will be installed during the next long shutdown of the LHC. Comprising both MicroMegas (MMs) and small-strip Thin Gap Chambers (sTGCs), this system will drastically improve the performance of the muon system in a high cavern background environment. The NSW trigger, in particular, will significantly reduce the rate of fake triggers coming from track segments in the endcap not originating from the interaction point. We will present an overview of the trigger, the proposed sTGC and MM trigger algorithms, and the hardware implementation of the trigger. In particular, we will discuss both the heart of the trigger, an ATCA system with FPGA-based trigger processors (using the same hardware platform for both MM and sTGC triggers), as well as the full trigger electronics chain, including dedicated cards for transmission of data via GBT optical links. Finally, we will detail the challenges of ensuring that the trigger electronics can ...

  4. Size-selective detection in integrated optical interferometric biosensors

    NARCIS (Netherlands)

    Mulder, Harmen K P; Ymeti, Aurel; Subramaniam, Vinod; Kanger, Johannes S

    2012-01-01

    We present a new size-selective detection method for integrated optical interferometric biosensors that can strongly enhance their performance. We demonstrate that by launching multiple wavelengths into a Young interferometer waveguide sensor it is feasible to derive refractive index changes from

  5. Evaluation of MERIS Chlorophyll-a Retrieval Processors in a Complex Turbid Lake Kasumigaura over a 10-Year Mission

    Directory of Open Access Journals (Sweden)

    Salem Ibrahim Salem

    2017-10-01

    Full Text Available Abstract: The chlorophyll-a (Chla products of seven processors developed for the Medium Resolution Imaging Spectrometer (MERIS sensor were evaluated. The seven processors, based on a neural network and band height, were assessed over an optically complex water body with Chla concentrations of 8.10–187.40 mg∙m−3 using 10-year MERIS archival data. These processors were adopted for the Ocean and Land Color Instrument (OLCI sensor. Results indicated that the four processors of band height (i.e. the Maximum Chlorophyll Index (MCI_L1; and Fluorescence Line Height (FLH_L1; neural network (i.e. Eutrophic Lake (EUL; and Case 2 Regional (C2R possessed reasonable retrieval accuracy with root mean square error (R2 in the range of 0.42–0.65. However, these processors underestimated the retrieved Chla > 100 mg∙m−3, reflecting the limitation of the band height processors to eliminate the influence of non-phytoplankton matter and highlighting the need to train the neural network for highly turbid waters. MCI_L1 outperformed other processors during the calibration and validation stages (R2 = 0.65, Root mean square error (RMSE = 22.18 mg∙m−3, the mean absolute relative error (MARE = 36.88%. In contrast, the results from the Boreal Lake (BOL and Free University of Berlin (FUB processors demonstrated their inadequacy to accurately retrieve Chla concentration > 50 mg∙m−3, mainly due to the limitation of the training datasets that resulted in a high MARE for BOL (56.20% and FUB (57.00%. Mapping the spatial distribution of Chla concentrations across Lake Kasumigaura using the seven processors showed that all processors—except for the BOL and FUB—were able to accurately capture the Chla distribution for moderate and high Chla concentrations. In addition, MCI_L1 and C2R processors were evaluated over 10-years of monthly measured Chla as they demonstrated the best retrieval accuracy from both groups (i.e. band height and neural network

  6. Integrated polymer micro-ring resonators for optical sensing applications

    OpenAIRE

    Girault , Pauline; Lorrain , Nathalie; Poffo , Luiz; Guendouz , Mohammed; Lemaitre , Jonathan; Carré , Christiane; Gadonna , Michel; Bosc , Dominique; Vignaud , Guillaume

    2015-01-01

    International audience; Micro-resonators (MR) have become a key element for integrated optical sensors due to their integration capability and their easy fabrication with low cost polymer materials. Nowadays, there is a growing need on MRs as highly sensitive and selective functions especially in the areas of food and health. The context of this work is to implement and study integrated micro-ring resonators devoted to sensing applications. They are fabricated by processing SU8 polymer as cor...

  7. Median and Morphological Specialized Processors for a Real-Time Image Data Processing

    Directory of Open Access Journals (Sweden)

    Kazimierz Wiatr

    2002-01-01

    Full Text Available This paper presents the considerations on selecting a multiprocessor MISD architecture for fast implementation of the vision image processing. Using the author′s earlier experience with real-time systems, implementing of specialized hardware processors based on the programmable FPGA systems has been proposed in the pipeline architecture. In particular, the following processors are presented: median filter and morphological processor. The structure of a universal reconfigurable processor developed has been proposed as well. Experimental results are presented as delays on LCA level implementation for median filter, morphological processor, convolution processor, look-up-table processor, logic processor and histogram processor. These times compare with delays in general purpose processor and DSP processor.

  8. Java Processor Optimized for RTSJ

    Directory of Open Access Journals (Sweden)

    Tu Shiliang

    2007-01-01

    Full Text Available Due to the preeminent work of the real-time specification for Java (RTSJ, Java is increasingly expected to become the leading programming language in real-time systems. To provide a Java platform suitable for real-time applications, a Java processor which can execute Java bytecode is directly proposed in this paper. It provides efficient support in hardware for some mechanisms specified in the RTSJ and offers a simpler programming model through ameliorating the scoped memory of the RTSJ. The worst case execution time (WCET of the bytecodes implemented in this processor is predictable by employing the optimization method proposed in our previous work, in which all the processing interfering predictability is handled before bytecode execution. Further advantage of this method is to make the implementation of the processor simpler and suited to a low-cost FPGA chip.

  9. On-chip photonic microsystem for optical signal processing based on silicon and silicon nitride platforms

    Science.gov (United States)

    Li, Yu; Li, Jiachen; Yu, Hongchen; Yu, Hai; Chen, Hongwei; Yang, Sigang; Chen, Minghua

    2018-04-01

    The explosive growth of data centers, cloud computing and various smart devices is limited by the current state of microelectronics, both in terms of speed and heat generation. Benefiting from the large bandwidth, promising low power consumption and passive calculation capability, experts believe that the integrated photonics-based signal processing and transmission technologies can break the bottleneck of microelectronics technology. In recent years, integrated photonics has become increasingly reliable and access to the advanced fabrication process has been offered by various foundries. In this paper, we review our recent works on the integrated optical signal processing system. We study three different kinds of on-chip signal processors and use these devices to build microsystems for the fields of microwave photonics, optical communications and spectrum sensing. The microwave photonics front receiver was demonstrated with a signal processing range of a full-band (L-band to W-band). A fully integrated microwave photonics transceiver without the on-chip laser was realized on silicon photonics covering the signal frequency of up 10 GHz. An all-optical orthogonal frequency division multiplexing (OFDM) de-multiplier was also demonstrated and used for an OFDM communication system with the rate of 64 Gbps. Finally, we show our work on the monolithic integrated spectrometer with a high resolution of about 20 pm at the central wavelength of 1550 nm. These proposed on-chip signal processing systems potential applications in the fields of radar, 5G wireless communication, wearable devices and optical access networks.

  10. Data collection from FASTBUS to a DEC UNIBUS processor through the UNIBUS-Processor Interface

    International Nuclear Information System (INIS)

    Larwill, M.; Barsotti, E.; Lesny, D.; Pordes, R.

    1983-01-01

    This paper describes the use of the UNIBUS Processor Interface, an interface between FASTBUS and the Digital Equipment Corporation UNIBUS. The UPI was developed by Fermilab and the University of Illinois. Details of the use of this interface in a high energy physics experiment at Fermilab are given. The paper includes a discussion of the operation of the UPI on the UNIBUS of a VAX-11, and plans for using the UPI to perform data acquisition from FASTBUS to a VAX-11 Processor

  11. Optical MSD symbolic substitution system based on a higher ordered rule

    Science.gov (United States)

    Reddy, A. K.; Mallikarjun, Tatipamula; Raina, J. P.

    1992-12-01

    The advantages provided by Photonic Computing has been well documented. An Optical arithmetic processor has to take full advantage of the massive parallelism in optical signals. Such a processor, using the Modified - Signed - Digit (MSD) number . (i) representation, has been presented here based (2) on the symbolic substitution 1ogi. The higher order symbolic substitution rules are formulated for the addition operation, which is carried out in just two steps. Based on the addition operation, the other arithmetic operations - subtraction, multiplication and division - are implemented. Finally, the usefulness of this MSD system is studied.

  12. New development for low energy electron beam processor

    International Nuclear Information System (INIS)

    Takei, Taro; Goto, Hitoshi; Oizumi, Matsutoshi; Hirakawa, Tetsuya; Ochi, Masafumi

    2003-01-01

    Newly developed low-energy electron beam (EB) processors that have unique designs and configurations compared to conventional ones enable electron-beam treatment of small three-dimensional objects, such as grain-like agricultural products and small plastic parts. As the EB processor can irradiate the products from the whole angles, the uniform EB treatment can be achieved at one time regardless the complex shapes of the product. Here presented are two new EB processors: the first system has cylindrical process zone, which allows three-dimensional objects to be irradiated with one-pass treatment. The second is a tube-type small EB processor, achieving not only its compactor design, but also higher beam extraction efficiency and flexible installation of the irradiation heads. The basic design of each processor and potential applications with them will be presented in this paper. (author)

  13. Uni- and omnidirectional simulation tools for integrated optics

    NARCIS (Netherlands)

    Stoffer, Remco

    2001-01-01

    This thesis presents several improvements on simulation methods in integrated optics, as well as some new methods. Both uni- and omnidirectional tools are presented; for the unidirectional methods, the emphasis is on higher-order accuracy; for the omnidirectional methods, the boundary conditions are

  14. An Optical Receiver Post Processing System for the Integrated Radio and Optical Communications Software Defined Radio Test Bed

    Science.gov (United States)

    Nappier, Jennifer M.; Tokars, Roger P.; Wroblewski, Adam C.

    2016-01-01

    The Integrated Radio and Optical Communications (iROC) project at the National Aeronautics and Space Administrations (NASA) Glenn Research Center is investigating the feasibility of a hybrid radio frequency (RF) and optical communication system for future deep space missions. As a part of this investigation, a test bed for a radio frequency (RF) and optical software defined radio (SDR) has been built. Receivers and modems for the NASA deep space optical waveform are not commercially available so a custom ground optical receiver system has been built. This paper documents the ground optical receiver, which is used in order to test the RF and optical SDR in a free space optical communications link.

  15. An Optical Receiver Post-Processing System for the Integrated Radio and Optical Communications Software Defined Radio Test Bed

    Science.gov (United States)

    Nappier, Jennifer M.; Tokars, Roger P.; Wroblewski, Adam C.

    2016-01-01

    The Integrated Radio and Optical Communications (iROC) project at the National Aeronautics and Space Administration's (NASA) Glenn Research Center is investigating the feasibility of a hybrid radio frequency (RF) and optical communication system for future deep space missions. As a part of this investigation, a test bed for a radio frequency (RF) and optical software defined radio (SDR) has been built. Receivers and modems for the NASA deep space optical waveform are not commercially available so a custom ground optical receiver system has been built. This paper documents the ground optical receiver, which is used in order to test the RF and optical SDR in a free space optical communications link.

  16. Integrating nanophotonic concepts and topics into optics curricula

    Science.gov (United States)

    Sonek, Gregory J.

    2007-06-01

    Nanophotonics has emerged as a new and important field of study, not only in research, but also in undergraduate optics and photonics education and training. Beyond the study of classical and quantum optics, it is important for students to learn about how the flow of light can be manipulated on a nanoscale level, and used in applications such as telecommunications, imaging, and medicine. This paper reports on our work to integrate basic nanophotonic concepts and topics into existing optics and optical electronics courses, as well as independent study projects, at the undergraduate level. Through classroom lectures, topical readings, computer modeling exercises, and laboratory experiments, students are introduced to nanophotonic concepts subsequent to a study of physical and geometrical optics. A compare and contrast methodology is employed to help students identify similarities and differences that exist in the optical behavior of bulk and nanostructured media. Training is further developed through engineering design and simulation exercises that use advanced, vector-diffraction-based, modeling software for simulating the performance of various materials and structures. To date, the addition of a nanophotonics component to the optics curriculum has proven successful, been enthusiastically received by students, and should serve as a basis for further course development efforts that emphasize the combined capabilities of nanotechnology and photonics.

  17. Ray and wave optics of integrable and stochastic systems

    International Nuclear Information System (INIS)

    McDonald, S.W.; Kaufman, A.N.

    1979-07-01

    The generalization of WKB methods to more than one dimension is discussed in terms of the integrability or non-integrability of the geometrical optics (ray Hamiltonian) system derived in the short-wave approximation. In the two-dimensional case the ray trajectories are either regular or stochastic, and the qualitative differences between these types of motion are manifested in the characteristics of the spectra and eigenfunctions. These are examined for a model system which may be integrable or stochastic, depending on a single parameter

  18. A data base processor semantics specification package

    Science.gov (United States)

    Fishwick, P. A.

    1983-01-01

    A Semantics Specification Package (DBPSSP) for the Intel Data Base Processor (DBP) is defined. DBPSSP serves as a collection of cross assembly tools that allow the analyst to assemble request blocks on the host computer for passage to the DBP. The assembly tools discussed in this report may be effectively used in conjunction with a DBP compatible data communications protocol to form a query processor, precompiler, or file management system for the database processor. The source modules representing the components of DBPSSP are fully commented and included.

  19. Survivable integrated grooming in multi-granularity optical networks

    Science.gov (United States)

    Wu, Jingjing; Guo, Lei; Wei, Xuetao; Liu, Yejun

    2012-05-01

    Survivability is an important issue to ensure the service continuity in optical network. At the same time, with the granularity of traffic demands ranging from sub-wavelength-level to wavelength-level, traffic demands need to be aggregated and carried over the network in order to utilize resources effectively. Therefore, multi-granularity grooming is proposed to save the cost and reduce the number of switching ports in Optical-Cross Connects (OXCs). However, current works mostly addressed the survivable wavelength or waveband grooming. Therefore, in this paper, we propose three heuristic algorithms called Multi-granularity Dedicated Protection Grooming (MDPG), Multi-granularity Shared Protection Grooming (MSPG) and Multi-granularity Mixed Protection Grooming (MMPG), respectively. All of them are performed based on the Survivable Multi-granularity Integrated Auxiliary Graph (SMIAG) that includes one Wavelength Integrated Auxiliary Graph (WIAG) for wavelength protection and one waveBand Integrated Auxiliary Graph (BIAG) for waveband protection. Numerical results show that MMPG has the lowest average port-cost, the best resource utilization ratio and the lowest blocking probability among these three algorithms. Compared with MDPG, MSPG has lower average port-cost, better resource utilization ratio and lower blocking probability.

  20. Liquid lens: advances in adaptive optics

    Science.gov (United States)

    Casey, Shawn Patrick

    2010-12-01

    'Liquid lens' technologies promise significant advancements in machine vision and optical communications systems. Adaptations for machine vision, human vision correction, and optical communications are used to exemplify the versatile nature of this technology. Utilization of liquid lens elements allows the cost effective implementation of optical velocity measurement. The project consists of a custom image processor, camera, and interface. The images are passed into customized pattern recognition and optical character recognition algorithms. A single camera would be used for both speed detection and object recognition.

  1. Globe hosts launch of new processor

    CERN Multimedia

    2006-01-01

    Launch of the quadecore processor chip at the Globe. On 14 November, in a series of major media events around the world, the chip-maker Intel launched its new 'quadcore' processor. For the regions of Europe, the Middle East and Africa, the day-long launch event took place in CERN's Globe of Science and Innovation, with over 30 journalists in attendance, coming from as far away as Johannesburg and Dubai. CERN was a significant choice for the event: the first tests of this new generation of processor in Europe had been made at CERN over the preceding months, as part of CERN openlab, a research partnership with leading IT companies such as Intel, HP and Oracle. The event also provided the opportunity for the journalists to visit ATLAS and the CERN Computer Centre. The strategy of putting multiple processor cores on the same chip, which has been pursued by Intel and other chip-makers in the last few years, represents an important departure from the more traditional improvements in the sheer speed of such chips. ...

  2. Design of an ultra-low-power digital processor for passive UHF RFID tags

    Energy Technology Data Exchange (ETDEWEB)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan, E-mail: wanggen_shi@163.co [Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, Institute of Microelectronics, Xidian University, Xi' an 710071 (China)

    2009-04-15

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 mum process of Chartered Semiconductor.

  3. Design of integrated optics all-optical label swappers for spectral amplitude code label swapping optical packet networks on active/passive InP technology

    NARCIS (Netherlands)

    Habib, C.; Munoz, P.; Leijtens, X.J.M.; Chen, Lawrence; Smit, M.K.; Capmany, J.

    2009-01-01

    In this paper the designs of optical label swapper devices, for spectral amplitude coded labels, monolithically integrated on InP active/passive technology are pre sented. The devices are based on cross-gain modulation in a semiconductor optical amplifier. Multi-wavelength operation is enabled by

  4. XL-100S microprogrammable processor

    International Nuclear Information System (INIS)

    Gorbunov, N.V.; Guzik, Z.; Sutulin, V.A.; Forytski, A.

    1983-01-01

    The XL-100S microprogrammable processor providing the multiprocessor operation mode in the XL system crate is described. The processor meets the EUR 6500 CAMAC standards, address up to 4 Mbyte memory, and interacts with 7 CAMAC branchas. Eight external requests initiate operations preset by a sequence of microcommands in a memory of the capacity up to 64 kwords of 32-Git. The microprocessor architecture allows one to emulate commands of the majority of mini- or micro-computers, including floating point operations. The XL-100S processor may be used in various branches of experimental physics: for physical experiment apparatus control, fast selection of useful physical events, organization of the of input/output operations, organization of direct assess to memory included, etc. The Am2900 microprocessor set is used as an elementary base. The device is made in the form of a single width CAMAC module

  5. IOTA (Integrable Optics Test Accelerator): facility and experimental beam physics program

    Science.gov (United States)

    Antipov, S.; Broemmelsiek, D.; Bruhwiler, D.; Edstrom, D.; Harms, E.; Lebedev, V.; Leibfritz, J.; Nagaitsev, S.; Park, C. S.; Piekarz, H.; Piot, P.; Prebys, E.; Romanov, A.; Ruan, J.; Sen, T.; Stancari, G.; Thangaraj, C.; Thurman-Keup, R.; Valishev, A.; Shiltsev, V.

    2017-03-01

    The Integrable Optics Test Accelerator (IOTA) is a storage ring for advanced beam physics research currently being built and commissioned at Fermilab. It will operate with protons and electrons using injectors with momenta of 70 and 150 MeV/c, respectively. The research program includes the study of nonlinear focusing integrable optical beam lattices based on special magnets and electron lenses, beam dynamics of space-charge effects and their compensation, optical stochastic cooling, and several other experiments. In this article, we present the design and main parameters of the facility, outline progress to date and provide the timeline of the construction, commissioning and research. The physical principles, design, and hardware implementation plans for the major IOTA experiments are also discussed.

  6. IOTA (Integrable Optics Test Accelerator): Facility and experimental beam physics program

    International Nuclear Information System (INIS)

    Antipov, Sergei; Broemmelsiek, Daniel; Bruhwiler, David; Edstrom, Dean; Harms, Elvin

    2017-01-01

    The Integrable Optics Test Accelerator (IOTA) is a storage ring for advanced beam physics research currently being built and commissioned at Fermilab. It will operate with protons and electrons using injectors with momenta of 70 and 150 MeV/c, respectively. The research program includes the study of nonlinear focusing integrable optical beam lattices based on special magnets and electron lenses, beam dynamics of space-charge effects and their compensation, optical stochastic cooling, and several other experiments. In this article, we present the design and main parameters of the facility, outline progress to date and provide the timeline of the construction, commissioning and research. Finally, the physical principles, design, and hardware implementation plans for the major IOTA experiments are also discussed.

  7. Simulation of a processor switching circuit with APLSV

    International Nuclear Information System (INIS)

    Dilcher, H.

    1979-01-01

    The report describes the simulation of a processor switching circuit with APL. Furthermore an APL function is represented to simulate a processor in an assembly like language. Both together serve as a tool for studying processor properties. By means of the programming function it is also possible to program other simulated processors. The processor is to be used in the processing of data in real time analysis that occur in high energy physics experiments. The data are already offered to the computer in digitalized form. A typical data rate is at 10 KB/ sec. The data are structured in blocks. The particular blocks are 1 KB wide and are independent from each other. Aprocessor has to decide, whether the block data belong to an event that is part of the backround noise and can therefore be forgotten, or whether the data should be saved for a later evaluation. (orig./WB) [de

  8. Parallel processors and nonlinear structural dynamics algorithms and software

    Science.gov (United States)

    Belytschko, Ted

    1989-01-01

    A nonlinear structural dynamics finite element program was developed to run on a shared memory multiprocessor with pipeline processors. The program, WHAMS, was used as a framework for this work. The program employs explicit time integration and has the capability to handle both the nonlinear material behavior and large displacement response of 3-D structures. The elasto-plastic material model uses an isotropic strain hardening law which is input as a piecewise linear function. Geometric nonlinearities are handled by a corotational formulation in which a coordinate system is embedded at the integration point of each element. Currently, the program has an element library consisting of a beam element based on Euler-Bernoulli theory and trianglar and quadrilateral plate element based on Mindlin theory.

  9. The Heidelberg POLYP - a flexible and fault-tolerant poly-processor

    International Nuclear Information System (INIS)

    Maenner, R.; Deluigi, B.

    1981-01-01

    The Heidelberg poly-processor system POLYP is described. It is intended to be used in nuclear physics for reprocessing of experimental data, in high energy physics as second-stage trigger processor, and generally in other applications requiring high-computing power. The POLYP system consists of any number of I/O-processors, processor modules (eventually of different types), global memory segments, and a host processor. All modules (up to several hundred) are connected by a multiple common-data-bus system; all processors, additionally, by a multiple sync bus system for processor/task-scheduling. All hard- and software is designed to be decentralized and free of bottle-necks. Most hardware-faults like single-bit errors in memory or multi-bit errors during transfers are automatically corrected. Defective modules, buses, etc., can be removed with only a graceful degradation of the system-throughput. (orig.)

  10. QERx- A Faster than Real-Time Emulator for Space Processors

    Science.gov (United States)

    Carvalho, B.; Pidgeon, A.; Robinson, P.

    2012-08-01

    Developing software for space systems is challenging. Especially because, in order to be sure it can cope with the harshness of the environment and the imperative requirements and constrains imposed by the platform were it will run, it needs to be tested exhaustively. Software Validation Facilities (SVF) are known to the industry and developers, and provide the means to run the On-Board Software (OBSW) in a realistic environment, allowing the development team to debug and test the software.But the challenge is to be able to keep up with the performance of the new processors (LEON2 and LEON3), which need to be emulated within the SVF. Such processor emulators are also used in Operational Simulators, used to support mission preparation and train mission operators. These simulators mimic the satellite and its behaviour, as realistically as possible. For test/operational efficiency reasons and because they will need to interact with external systems, both these uses cases require the processor emulators to provide real-time, or faster, performance.It is known to the industry that the performance of previously available emulators is not enough to cope with the performance of the new processors available in the market. SciSys approached this problem with dynamic translation technology trying to keep costs down by avoiding a hardware solution and keeping the integration flexibility of full software emulation.SciSys presented “QERx: A High Performance Emulator for Software Validation and Simulations” [1], in a previous DASIA event. Since then that idea has evolved and QERx has been successfully validated. SciSys is now presenting QERx as a product that can be tailored to fit different emulation needs. This paper will present QERx latest developments and current status.

  11. Integrated, Continuous Emulsion Creamer.

    Science.gov (United States)

    Cochrane, Wesley G; Hackler, Amber L; Cavett, Valerie J; Price, Alexander K; Paegel, Brian M

    2017-12-19

    Automated and reproducible sample handling is a key requirement for high-throughput compound screening and currently demands heavy reliance on expensive robotics in screening centers. Integrated droplet microfluidic screening processors are poised to replace robotic automation by miniaturizing biochemical reactions to the droplet scale. These processors must generate, incubate, and sort droplets for continuous droplet screening, passively handling millions of droplets with complete uniformity, especially during the key step of sample incubation. Here, we disclose an integrated microfluidic emulsion creamer that packs ("creams") assay droplets by draining away excess oil through microfabricated drain channels. The drained oil coflows with creamed emulsion and then reintroduces the oil to disperse the droplets at the circuit terminus for analysis. Creamed emulsion assay incubation time dispersion was 1.7%, 3-fold less than other reported incubators. The integrated, continuous emulsion creamer (ICEcreamer) was used to miniaturize and optimize measurements of various enzymatic activities (phosphodiesterase, kinase, bacterial translation) under multiple- and single-turnover conditions. Combining the ICEcreamer with current integrated microfluidic DNA-encoded library bead processors eliminates potentially cumbersome instrumentation engineering challenges and is compatible with assays of diverse target class activities commonly investigated in drug discovery.

  12. Atmel's New Rad-Hard Sparc V8 Processor 200Mhz & Low Power System on Chip

    Science.gov (United States)

    Ganry, Nicolas; Mantelet, Guy; Parkes, Steve; McClements, Chris

    2014-08-01

    The AT6981 is a new generation of processor designed for critical spaceflight applications, which combines a high-performance SPARC® V8 radiation hard processor, with enough on-chip memory for many aerospace applications and state-of-the-art SpaceWire networking technology from STAR- Dundee. The AT6981 is implemented in Atmel 90nm rad-hard technology, enabling 200 MHz operating speed for the processor with power consumption levels around 1W. This advanced technology allows strong system integration in a SoC with embedded peripherals like CAN, 1553, Ethernet, DDR and embedded memory with 1Mbytes SRAM. The device is ITAR- free and is developed in France by Atmel Aerospace having more than of 30years space experience. This paper describes this new SoC architecture and technical options considered to insure the best performances, the minimum power consumption and high reliability. This device will be available on the market in H2 2014 for evaluation with first flight models targeted end 2015.

  13. An efficient ASIC implementation of 16-channel on-line recursive ICA processor for real-time EEG system.

    Science.gov (United States)

    Fang, Wai-Chi; Huang, Kuan-Ju; Chou, Chia-Ching; Chang, Jui-Chung; Cauwenberghs, Gert; Jung, Tzyy-Ping

    2014-01-01

    This is a proposal for an efficient very-large-scale integration (VLSI) design, 16-channel on-line recursive independent component analysis (ORICA) processor ASIC for real-time EEG system, implemented with TSMC 40 nm CMOS technology. ORICA is appropriate to be used in real-time EEG system to separate artifacts because of its highly efficient and real-time process features. The proposed ORICA processor is composed of an ORICA processing unit and a singular value decomposition (SVD) processing unit. Compared with previous work [1], this proposed ORICA processor has enhanced effectiveness and reduced hardware complexity by utilizing a deeper pipeline architecture, shared arithmetic processing unit, and shared registers. The 16-channel random signals which contain 8-channel super-Gaussian and 8-channel sub-Gaussian components are used to analyze the dependence of the source components, and the average correlation coefficient is 0.95452 between the original source signals and extracted ORICA signals. Finally, the proposed ORICA processor ASIC is implemented with TSMC 40 nm CMOS technology, and it consumes 15.72 mW at 100 MHz operating frequency.

  14. A low-latency optical switch architecture using integrated μm SOI-based contention resolution and switching

    Science.gov (United States)

    Mourgias-Alexandris, G.; Moralis-Pegios, M.; Terzenidis, N.; Cherchi, M.; Harjanne, M.; Aalto, T.; Vyrsokinos, K.; Pleros, N.

    2018-02-01

    The urgent need for high-bandwidth and high-port connectivity in Data Centers has boosted the deployment of optoelectronic packet switches towards bringing high data-rate optics closer to the ASIC, realizing optical transceiver functions directly at the ASIC package for high-rate, low-energy and low-latency interconnects. Even though optics can offer a broad range of low-energy integrated switch fabrics for replacing electronic switches and seamlessly interface with the optical I/Os, the use of energy- and latency-consuming electronic SerDes continues to be a necessity, mainly dictated by the absence of integrated and reliable optical buffering solutions. SerDes undertakes the role of optimally synergizing the lower-speed electronic buffers with the incoming and outgoing optical streams, suggesting that a SerDes-released chip-scale optical switch fabric can be only realized in case all necessary functions including contention resolution and switching can be implemented on a common photonic integration platform. In this paper, we demonstrate experimentally a hybrid Broadcast-and-Select (BS) / wavelength routed optical switch that performs both the optical buffering and switching functions with μm-scale Silicon-integrated building blocks. Optical buffering is carried out in a silicon-integrated variable delay line bank with a record-high on-chip delay/footprint efficiency of 2.6ns/mm2 and up to 17.2 nsec delay capability, while switching is executed via a BS design and a silicon-integrated echelle grating, assisted by SOA-MZI wavelength conversion stages and controlled by a FPGA header processing module. The switch has been experimentally validated in a 3x3 arrangement with 10Gb/s NRZ optical data packets, demonstrating error-free switching operation with a power penalty of <5dB.

  15. Parallel Algorithm for Adaptive Numerical Integration

    International Nuclear Information System (INIS)

    Sujatmiko, M.; Basarudin, T.

    1997-01-01

    This paper presents an automation algorithm for integration using adaptive trapezoidal method. The interval is adaptively divided where the width of sub interval are different and fit to the behavior of its function. For a function f, an integration on interval [a,b] can be obtained, with maximum tolerance ε, using estimation (f, a, b, ε). The estimated solution is valid if the error is still in a reasonable range, fulfil certain criteria. If the error is big, however, the problem is solved by dividing it into to similar and independent sub problem on to separate [a, (a+b)/2] and [(a+b)/2, b] interval, i. e. ( f, a, (a+b)/2, ε/2) and (f, (a+b)/2, b, ε/2) estimations. The problems are solved in two different kinds of processor, root processor and worker processor. Root processor function ti divide a main problem into sub problems and distribute them to worker processor. The division mechanism may go further until all of the sub problem are resolved. The solution of each sub problem is then submitted to the root processor such that the solution for the main problem can be obtained. The algorithm is implemented on C-programming-base distributed computer networking system under parallel virtual machine platform

  16. High-Resolution Integrated Optical System

    Science.gov (United States)

    Prakapenka, V. B.; Goncharov, A. F.; Holtgrewe, N.; Greenberg, E.

    2017-12-01

    Raman and optical spectroscopy in-situ at extreme high pressure and temperature conditions relevant to the planets' deep interior is a versatile tool for characterization of wide range of properties of minerals essential for understanding the structure, composition, and evolution of terrestrial and giant planets. Optical methods, greatly complementing X-ray diffraction and spectroscopy techniques, become crucial when dealing with light elements. Study of vibrational and optical properties of minerals and volatiles, was a topic of many research efforts in past decades. A great deal of information on the materials properties under extreme pressure and temperature has been acquired including that related to structural phase changes, electronic transitions, and chemical transformations. These provide an important insight into physical and chemical states of planetary interiors (e.g. nature of deep reservoirs) and their dynamics including heat and mass transport (e.g. deep carbon cycle). Optical and vibrational spectroscopy can be also very instrumental for elucidating the nature of the materials molten states such as those related to the Earth's volatiles (CO2, CH4, H2O), aqueous fluids and silicate melts, planetary ices (H2O, CH4, NH3), noble gases, and H2. The optical spectroscopy study performed concomitantly with X-ray diffraction and spectroscopy measurements at the GSECARS beamlines on the same sample and at the same P-T conditions would greatly enhance the quality of this research and, moreover, will provide unique new information on chemical state of matter. The advanced high-resolution user-friendly integrated optical system is currently under construction and expected to be completed by 2018. In our conceptual design we have implemented Raman spectroscopy with five excitation wavelengths (266, 473, 532, 660, 946 nm), confocal imaging, double sided IR laser heating combined with high temperature Raman (including coherent anti-Stokes Raman scattering) and

  17. Optical propagators in vector and spinor theories by path integral formalism

    International Nuclear Information System (INIS)

    Linares, J.

    1993-01-01

    The construction of an extended parabolic (wide-angle) vector and spinor wave theory is presented. For that, optical propagators in monochromatic vector light optics and monoenergetic spinor electron optics are evaluated by the path integral formalism. The auxiliary parameter method introduced by Fock and the Feynman-Dyson perturbative series are used. The proposed theory supplies, by a generalized Fermat's principle, the Mukunda-Simon-Sudarshan transformation for the passage from scalar to vector light (or spinor electron) optics in an asymptotic approximation. (author). 19 refs

  18. Metal membrane-type 25-kW methanol fuel processor for fuel-cell hybrid vehicle

    Science.gov (United States)

    Han, Jaesung; Lee, Seok-Min; Chang, Hyuksang

    A 25-kW on-board methanol fuel processor has been developed. It consists of a methanol steam reformer, which converts methanol to hydrogen-rich gas mixture, and two metal membrane modules, which clean-up the gas mixture to high-purity hydrogen. It produces hydrogen at rates up to 25 N m 3/h and the purity of the product hydrogen is over 99.9995% with a CO content of less than 1 ppm. In this fuel processor, the operating condition of the reformer and the metal membrane modules is nearly the same, so that operation is simple and the overall system construction is compact by eliminating the extensive temperature control of the intermediate gas streams. The recovery of hydrogen in the metal membrane units is maintained at 70-75% by the control of the pressure in the system, and the remaining 25-30% hydrogen is recycled to a catalytic combustion zone to supply heat for the methanol steam-reforming reaction. The thermal efficiency of the fuel processor is about 75% and the inlet air pressure is as low as 4 psi. The fuel processor is currently being integrated with 25-kW polymer electrolyte membrane fuel-cell (PEMFC) stack developed by the Hyundai Motor Company. The stack exhibits the same performance as those with pure hydrogen, which proves that the maximum power output as well as the minimum stack degradation is possible with this fuel processor. This fuel-cell 'engine' is to be installed in a hybrid passenger vehicle for road testing.

  19. INTEGRATED APPLICATION OF OPTICAL DIAGNOSTIC METHODS IN ULCERATIVE COLITIS

    Directory of Open Access Journals (Sweden)

    E. V. Velikanov

    2013-01-01

    Full Text Available Abstract. Our results suggest that the combined use of optical coherent tomography (OCT and fluorescence diagnosis helps to refine the nature and boundaries of the pathological process in the tissue of the colon in ulcerative colitis. Studies have shown that an integrated optical diagnostics allows us to differentiate lesions respectively to histology and to decide on the need for biopsy and venue. This method is most appropriate in cases difficult for diagnosis. 

  20. Embedded processor extensions for image processing

    Science.gov (United States)

    Thevenin, Mathieu; Paindavoine, Michel; Letellier, Laurent; Heyrman, Barthélémy

    2008-04-01

    The advent of camera phones marks a new phase in embedded camera sales. By late 2009, the total number of camera phones will exceed that of both conventional and digital cameras shipped since the invention of photography. Use in mobile phones of applications like visiophony, matrix code readers and biometrics requires a high degree of component flexibility that image processors (IPs) have not, to date, been able to provide. For all these reasons, programmable processor solutions have become essential. This paper presents several techniques geared to speeding up image processors. It demonstrates that a gain of twice is possible for the complete image acquisition chain and the enhancement pipeline downstream of the video sensor. Such results confirm the potential of these computing systems for supporting future applications.

  1. Novel Optical Processor for Phased Array Antenna.

    Science.gov (United States)

    1992-10-20

    parallel glass slide into the signal beam optical loop. The parallel glass acts like a variable phase shifter to the signal beam simulating phase drift...A list of possible designs are given as follows , _ _ Velocity fa (100dB/cm) Lumit Wavelength I M2I1 TeO2 Longi 4.2 /m/ns about 3 GHz 1.4 4m 34 Fast...subject to achievable acoustic frequency, the preferred materials are the slow shear wave in TeO2 , the fast shear wave in TeO2 or the shear waves in

  2. A COTS RF/Optical Software Defined Radio for the Integrated Radio and Optical Communications Test Bed

    Science.gov (United States)

    Nappier, Jennifer M.; Zeleznikar, Daniel J.; Wroblewski, Adam C.; Tokars, Roger P.; Schoenholz, Bryan L.; Lantz, Nicholas C.

    2017-01-01

    The Integrated Radio and Optical Communications (iROC) project at the National Aeronautics and Space Administration (NASA) is investigating the merits of a hybrid radio frequency (RF) and optical communication system for deep space missions. In an effort to demonstrate the feasibility and advantages of a hybrid RF/Optical software defined radio (SDR), a laboratory prototype was assembled from primarily commercial-off-the-shelf (COTS) hardware components. This COTS platform has been used to demonstrate simultaneous transmission of the radio and optical communications waveforms through to the physical layer (telescope and antenna). This paper details the hardware and software used in the platform and various measures of its performance. A laboratory optical receiver platform has also been assembled in order to demonstrate hybrid free space links in combination with the transmitter.

  3. Multiple optical code-label processing using multi-wavelength frequency comb generator and multi-port optical spectrum synthesizer.

    Science.gov (United States)

    Moritsuka, Fumi; Wada, Naoya; Sakamoto, Takahide; Kawanishi, Tetsuya; Komai, Yuki; Anzai, Shimako; Izutsu, Masayuki; Kodate, Kashiko

    2007-06-11

    In optical packet switching (OPS) and optical code division multiple access (OCDMA) systems, label generation and processing are key technologies. Recently, several label processors have been proposed and demonstrated. However, in order to recognize N different labels, N separate devices are required. Here, we propose and experimentally demonstrate a large-scale, multiple optical code (OC)-label generation and processing technology based on multi-port, a fully tunable optical spectrum synthesizer (OSS) and a multi-wavelength electro-optic frequency comb generator. The OSS can generate 80 different OC-labels simultaneously and can perform 80-parallel matched filtering. We also demonstrated its application to OCDMA.

  4. Sojourn time tails in processor-sharing systems

    NARCIS (Netherlands)

    Egorova, R.R.

    2009-01-01

    The processor-sharing discipline was originally introduced as a modeling abstraction for the design and performance analysis of the processing unit of a computer system. Under the processor-sharing discipline, all active tasks are assumed to be processed simultaneously, receiving an equal share of

  5. An interactive parallel processor for data analysis

    International Nuclear Information System (INIS)

    Mong, J.; Logan, D.; Maples, C.; Rathbun, W.; Weaver, D.

    1984-01-01

    A parallel array of eight minicomputers has been assembled in an attempt to deal with kiloparameter data events. By exporting computer system functions to a separate processor, the authors have been able to achieve computer amplification linearly proportional to the number of executing processors

  6. Preserving Simplecticity in the Numerical Integration of Linear Beam Optics

    Energy Technology Data Exchange (ETDEWEB)

    Allen, Christopher K. [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2017-07-01

    Presented are mathematical tools and methods for the development of numerical integration techniques that preserve the symplectic condition inherent to mechanics. The intended audience is for beam physicists with backgrounds in numerical modeling and simulation with particular attention to beam optics applications. The paper focuses on Lie methods that are inherently symplectic regardless of the integration accuracy order. Section 2 provides the mathematically tools used in the sequel and necessary for the reader to extend the covered techniques. Section 3 places those tools in the context of charged-particle beam optics; in particular linear beam optics is presented in terms of a Lie algebraic matrix representation. Section 4 presents numerical stepping techniques with particular emphasis on a third-order leapfrog method. Section 5 discusses the modeling of field imperfections with particular attention to the fringe fields of quadrupole focusing magnets. The direct computation of a third order transfer matrix for a fringe field is shown.

  7. Multiprocessor Real-Time Scheduling with Hierarchical Processor Affinities

    OpenAIRE

    Bonifaci , Vincenzo; Brandenburg , Björn; D'Angelo , Gianlorenzo; Marchetti-Spaccamela , Alberto

    2016-01-01

    International audience; Many multiprocessor real-time operating systems offer the possibility to restrict the migrations of any task to a specified subset of processors by setting affinity masks. A notion of " strong arbitrary processor affinity scheduling " (strong APA scheduling) has been proposed; this notion avoids schedulability losses due to overly simple implementations of processor affinities. Due to potential overheads, strong APA has not been implemented so far in a real-time operat...

  8. Hardware trigger processor for the MDT system

    CERN Document Server

    AUTHOR|(SzGeCERN)757787; The ATLAS collaboration; Hazen, Eric; Butler, John; Black, Kevin; Gastler, Daniel Edward; Ntekas, Konstantinos; Taffard, Anyes; Martinez Outschoorn, Verena; Ishino, Masaya; Okumura, Yasuyuki

    2017-01-01

    We are developing a low-latency hardware trigger processor for the Monitored Drift Tube system in the Muon spectrometer. The processor will fit candidate Muon tracks in the drift tubes in real time, improving significantly the momentum resolution provided by the dedicated trigger chambers. We present a novel pure-FPGA implementation of a Legendre transform segment finder, an associative-memory alternative implementation, an ARM (Zynq) processor-based track fitter, and compact ATCA carrier board architecture. The ATCA architecture is designed to allow a modular, staged approach to deployment of the system and exploration of alternative technologies.

  9. Optical links in handheld multimedia devices

    Science.gov (United States)

    van Geffen, S.; Duis, J.; Miller, R.

    2008-04-01

    Ever emerging applications in handheld multimedia devices such as mobile phones, laptop computers, portable video games and digital cameras requiring increased screen resolutions are driving higher aggregate bitrates between host processor and display(s) enabling services such as mobile video conferencing, video on demand and TV broadcasting. Larger displays and smaller phones require complex mechanical 3D hinge configurations striving to combine maximum functionality with compact building volumes. Conventional galvanic interconnections such as Micro-Coax and FPC carrying parallel digital data between host processor and display module may produce Electromagnetic Interference (EMI) and bandwidth limitations caused by small cable size and tight cable bends. To reduce the number of signals through a hinge, the mobile phone industry, organized in the MIPI (Mobile Industry Processor Interface) alliance, is currently defining an electrical interface transmitting serialized digital data at speeds >1Gbps. This interface allows for electrical or optical interconnects. Above 1Gbps optical links may offer a cost effective alternative because of their flexibility, increased bandwidth and immunity to EMI. This paper describes the development of optical links for handheld communication devices. A cable assembly based on a special Plastic Optical Fiber (POF) selected for its mechanical durability is terminated with a small form factor molded lens assembly which interfaces between an 850nm VCSEL transmitter and a receiving device on the printed circuit board of the display module. A statistical approach based on a Lean Design For Six Sigma (LDFSS) roadmap for new product development tries to find an optimum link definition which will be robust and low cost meeting the power consumption requirements appropriate for battery operated systems.

  10. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    Science.gov (United States)

    Hall, Trevor J; Hasan, Mehedi

    2016-04-04

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  11. Design of an ultra-low-power digital processor for passive UHF RFID tags

    International Nuclear Information System (INIS)

    Shi Wanggen; Zhuang Yiqi; Li Xiaoming; Wang Xianghua; Jin Zhao; Wang Dan

    2009-01-01

    A new architecture of digital processors for passive UHF radio-frequency identification tags is proposed. This architecture is based on ISO/IEC 18000-6C and targeted at ultra-low power consumption. By applying methods like system-level power management, global clock gating and low voltage implementation, the total power of the design is reduced to a few microwatts. In addition, an innovative way for the design of a true RNG is presented, which contributes to both low power and secure data transaction. The digital processor is verified by an integrated FPGA platform and implemented by the Synopsys design kit for ASIC flows. The design fits different CMOS technologies and has been taped out using the 2P4M 0.35 μm process of Chartered Semiconductor.

  12. Towards a Process Algebra for Shared Processors

    DEFF Research Database (Denmark)

    Buchholtz, Mikael; Andersen, Jacob; Løvengreen, Hans Henrik

    2002-01-01

    We present initial work on a timed process algebra that models sharing of processor resources allowing preemption at arbitrary points in time. This enables us to model both the functional and the timely behaviour of concurrent processes executed on a single processor. We give a refinement relation...

  13. High-speed packet filtering utilizing stream processors

    Science.gov (United States)

    Hummel, Richard J.; Fulp, Errin W.

    2009-04-01

    Parallel firewalls offer a scalable architecture for the next generation of high-speed networks. While these parallel systems can be implemented using multiple firewalls, the latest generation of stream processors can provide similar benefits with a significantly reduced latency due to locality. This paper describes how the Cell Broadband Engine (CBE), a popular stream processor, can be used as a high-speed packet filter. Results show the CBE can potentially process packets arriving at a rate of 1 Gbps with a latency less than 82 μ-seconds. Performance depends on how well the packet filtering process is translated to the unique stream processor architecture. For example the method used for transmitting data and control messages among the pseudo-independent processor cores has a significant impact on performance. Experimental results will also show the current limitations of a CBE operating system when used to process packets. Possible solutions to these issues will be discussed.

  14. Integrating sphere-based setup as an accurate system for optical properties measurements

    CSIR Research Space (South Africa)

    Abdalmonem, S

    2010-09-01

    Full Text Available Determination of the optical properties of solid and liquid samples has great importance. Since the integrating sphere-based setup is used to measure the amount of reflected and transmitted light by the examined samples, optical properties could...

  15. Load balancing in integrated optical wireless networks

    DEFF Research Database (Denmark)

    Yan, Ying; Dittmann, Lars; Wong, S-W.

    2010-01-01

    In this paper, we tackle the load balancing problem in Integrated Optical Wireless Networks, where cell breathing technique is used to solve congestion by changing the coverage area of a fully loaded cell tower. Our objective is to design a load balancing mechanism which works closely...... with the integrated control scheme so as to maximize overall network throughput in the integrated network architecture. To the best of our knowledge no load balancing mechanisms, especially based on the Multi-Point Control Protocol (MPCP) defined in the IEEE 802.3ah, have been proposed so far. The major research...... issues are outlined and a cost function based optimization model is developed for power management. In particularly, two alternative feedback schemes are proposed to report wireless network status. Simulation results show that our proposed load balancing mechanism improves network performances....

  16. Acceleration of spiking neural network based pattern recognition on NVIDIA graphics processors.

    Science.gov (United States)

    Han, Bing; Taha, Tarek M

    2010-04-01

    There is currently a strong push in the research community to develop biological scale implementations of neuron based vision models. Systems at this scale are computationally demanding and generally utilize more accurate neuron models, such as the Izhikevich and the Hodgkin-Huxley models, in favor of the more popular integrate and fire model. We examine the feasibility of using graphics processing units (GPUs) to accelerate a spiking neural network based character recognition network to enable such large scale systems. Two versions of the network utilizing the Izhikevich and Hodgkin-Huxley models are implemented. Three NVIDIA general-purpose (GP) GPU platforms are examined, including the GeForce 9800 GX2, the Tesla C1060, and the Tesla S1070. Our results show that the GPGPUs can provide significant speedup over conventional processors. In particular, the fastest GPGPU utilized, the Tesla S1070, provided a speedup of 5.6 and 84.4 over highly optimized implementations on the fastest central processing unit (CPU) tested, a quadcore 2.67 GHz Xeon processor, for the Izhikevich and the Hodgkin-Huxley models, respectively. The CPU implementation utilized all four cores and the vector data parallelism offered by the processor. The results indicate that GPUs are well suited for this application domain.

  17. Fast processor for dilepton triggers

    International Nuclear Information System (INIS)

    Katsanevas, S.; Kostarakis, P.; Baltrusaitis, R.

    1983-01-01

    We describe a fast trigger processor, developed for and used in Fermilab experiment E-537, for selecting high-mass dimuon events produced by negative pions and anti-protons. The processor finds candidate tracks by matching hit information received from drift chambers and scintillation counters, and determines their momenta. Invariant masses are calculated for all possible pairs of tracks and an event is accepted if any invariant mass is greater than some preselectable minimum mass. The whole process, accomplished within 5 to 10 microseconds, achieves up to a ten-fold reduction in trigger rate

  18. Design of RISC Processor Using VHDL and Cadence

    Science.gov (United States)

    Moslehpour, Saeid; Puliroju, Chandrasekhar; Abu-Aisheh, Akram

    The project deals about development of a basic RISC processor. The processor is designed with basic architecture consisting of internal modules like clock generator, memory, program counter, instruction register, accumulator, arithmetic and logic unit and decoder. This processor is mainly used for simple general purpose like arithmetic operations and which can be further developed for general purpose processor by increasing the size of the instruction register. The processor is designed in VHDL by using Xilinx 8.1i version. The present project also serves as an application of the knowledge gained from past studies of the PSPICE program. The study will show how PSPICE can be used to simplify massive complex circuits designed in VHDL Synthesis. The purpose of the project is to explore the designed RISC model piece by piece, examine and understand the Input/ Output pins, and to show how the VHDL synthesis code can be converted to a simplified PSPICE model. The project will also serve as a collection of various research materials about the pieces of the circuit.

  19. Real time processor for array speckle interferometry

    Science.gov (United States)

    Chin, Gordon; Florez, Jose; Borelli, Renan; Fong, Wai; Miko, Joseph; Trujillo, Carlos

    1989-02-01

    The authors are constructing a real-time processor to acquire image frames, perform array flat-fielding, execute a 64 x 64 element two-dimensional complex FFT (fast Fourier transform) and average the power spectrum, all within the 25 ms coherence time for speckles at near-IR (infrared) wavelength. The processor will be a compact unit controlled by a PC with real-time display and data storage capability. This will provide the ability to optimize observations and obtain results on the telescope rather than waiting several weeks before the data can be analyzed and viewed with offline methods. The image acquisition and processing, design criteria, and processor architecture are described.

  20. Integration of active and passive polymer optics

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Kristensen, Anders

    2007-01-01

    We demonstrate a wafer scale fabrication process for integration of active and passive polymer optics: Polymer DFB lasers and waveguides. Polymer dye DFB lasers are fabricated by combined nanoimprint and photolithography (CNP). The CNP fabrication relies on an UV transparent stamp with nm sized...... wavelength from temperature and refractive index changes in the surroundings is investigated, pointing towards the use of the described fabrication method for on-chip polymer sensor systems....

  1. Vector and parallel processors in computational science

    International Nuclear Information System (INIS)

    Duff, I.S.; Reid, J.K.

    1985-01-01

    These proceedings contain the articles presented at the named conference. These concern hardware and software for vector and parallel processors, numerical methods and algorithms for the computation on such processors, as well as applications of such methods to different fields of physics and related sciences. See hints under the relevant topics. (HSI)

  2. Semiclassical Path Integral Calculation of Nonlinear Optical Spectroscopy.

    Science.gov (United States)

    Provazza, Justin; Segatta, Francesco; Garavelli, Marco; Coker, David F

    2018-02-13

    Computation of nonlinear optical response functions allows for an in-depth connection between theory and experiment. Experimentally recorded spectra provide a high density of information, but to objectively disentangle overlapping signals and to reach a detailed and reliable understanding of the system dynamics, measurements must be integrated with theoretical approaches. Here, we present a new, highly accurate and efficient trajectory-based semiclassical path integral method for computing higher order nonlinear optical response functions for non-Markovian open quantum systems. The approach is, in principle, applicable to general Hamiltonians and does not require any restrictions on the form of the intrasystem or system-bath couplings. This method is systematically improvable and is shown to be valid in parameter regimes where perturbation theory-based methods qualitatively breakdown. As a test of the methodology presented here, we study a system-bath model for a coupled dimer for which we compare against numerically exact results and standard approximate perturbation theory-based calculations. Additionally, we study a monomer with discrete vibronic states that serves as the starting point for future investigation of vibronic signatures in nonlinear electronic spectroscopy.

  3. MPC Related Computational Capabilities of ARMv7A Processors

    DEFF Research Database (Denmark)

    Frison, Gianluca; Jørgensen, John Bagterp

    2015-01-01

    In recent years, the mass market of mobile devices has pushed the demand for increasingly fast but cheap processors. ARM, the world leader in this sector, has developed the Cortex-A series of processors with focus on computationally intensive applications. If properly programmed, these processors...... are powerful enough to solve the complex optimization problems arising in MPC in real-time, while keeping the traditional low-cost and low-power consumption. This makes these processors ideal candidates for use in embedded MPC. In this paper, we investigate the floating-point capabilities of Cortex A7, A9...... and A15 and show how to exploit the unique features of each processor to obtain the best performance, in the context of a novel implementation method for the linear-algebra routines used in MPC solvers. This method adapts high-performance computing techniques to the needs of embedded MPC. In particular...

  4. Influence of diffuse reflectance measurement accuracy on the scattering coefficient in determination of optical properties with integrating sphere optics (a secondary publication).

    Science.gov (United States)

    Horibe, Takuro; Ishii, Katsunori; Fukutomi, Daichi; Awazu, Kunio

    2015-12-30

    An estimation error of the scattering coefficient of hemoglobin in the high absorption wavelength range has been observed in optical property calculations of blood-rich tissues. In this study, the relationship between the accuracy of diffuse reflectance measurement in the integrating sphere and calculated scattering coefficient was evaluated with a system to calculate optical properties combined with an integrating sphere setup and the inverse Monte Carlo simulation. Diffuse reflectance was measured with the integrating sphere using a small incident port diameter and optical properties were calculated. As a result, the estimation error of the scattering coefficient was improved by accurate measurement of diffuse reflectance. In the high absorption wavelength range, the accuracy of diffuse reflectance measurement has an effect on the calculated scattering coefficient.

  5. Plasmonic nanopatch array for optical integrated circuit applications.

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  6. An automated data handling process integrating spreadsheets and word processors with analytical programs

    International Nuclear Information System (INIS)

    Fisher, G.F.; Bennett, L.G.I.

    1994-01-01

    A data handling process utilizing software programs that are commercially available for use on MS-DOS microcomputers was developed to reduce the time, energy and labour required to tabulate the final results of trace analyses. The elimination of hand computations reduced the possibility of transcription errors since, once the γ-ray spectrum analysis results are obtained and saved to a hard disk of a microcomputer, they can be manipulated very easily with little possibility of distortion. The 8 step process permitted the selection of each element of interest's best concentration value based upon its associated peak area. Calculated concentration values were automatically compared against the sample's determination limit. Unsatisfactory values were flagged for latter review and adjustment by the user. In the final step, a file was created which identified the samples with their appropriate particulars (i.e. source, sample, date, etc.), and the trace element concentration were displayed. This final file contained a fully formatted summary table that listed all of the sample's results and particulars such that it could be printed or imported into a word processor for inclusion in a report. In the illustrated application of analyzing wear debris in oil-lubricated systems, over 13,000 individual numbers were processed to arrive at final concentration estimates of 19 trace elements in 80 samples. The system works very well for the elements that were analyzed in this investigation. The usefulness of commercially available spreadsheets and word processors for this task was demonstrated. (author) 5 refs.; 2 figs.; 5 tabs

  7. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

    2009-12-15

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  8. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    International Nuclear Information System (INIS)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

    2009-01-01

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  9. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    The Air Base Technologies Division of the Air Force Research Laboratory has developed a logistic fuel processor that removes the sulfur content of the fuel and in the process converts logistic fuel...

  10. Cantilever-based sensor with integrated optical read-out using single mode waveguides

    DEFF Research Database (Denmark)

    Nordström, Maria; Zauner, Dan; Calleja, Montserrat

    2007-01-01

    This work presents the design, fabrication and mechanical characterisation of an integrated optical read-out scheme for cantilever-based biosensors. A cantilever can be used as a biosensor by monitoring its bending caused by the surface stress generated due to chemical reactions occurring on its...... surface. Here, we present a novel integrated optical read-out scheme based on single-mode waveguides that enables the fabrication of a compact system. The complete system is fabricated in the polymer SU-8. This manuscript shows the principle of operation and the design well as the fabrication...

  11. Optical dichroism: E1-M1 integral relations

    International Nuclear Information System (INIS)

    Marri, Ivan; Carra, Paolo; Bertoni, C M

    2006-01-01

    The present paper discusses optical dichroism in noncentrosymmetric systems. The cases of circular and linear polarizations are considered. Integrated spectra are interpreted using effective two-electron operators, which are derived within a localized (atomic) model. As a consequence, our theory is not suitable for quantitative predictions; nevertheless, it identifies microscopic origins of natural, nonreciprocal and Jones' dichroisms

  12. A COTS RF Optical Software Defined Radio for the Integrated Radio and Optical Communications Test Bed

    Science.gov (United States)

    Nappier, Jennifer M.; Zeleznikar, Daniel J.; Wroblewski, Adam C.; Tokars, Roger P.; Schoenholz, Bryan L.; Lantz, Nicholas C.

    2016-01-01

    The Integrated Radio and Optical Communications (iROC) project at the National Aeronautics and Space Administration (NASA) is investigating the merits of a hybrid radio frequency (RF) and optical communication system for deep space missions. In an effort to demonstrate the feasibility and advantages of a hybrid RFOptical software defined radio (SDR), a laboratory prototype was assembled from primarily commercial-off-the-shelf (COTS) hardware components. This COTS platform has been used to demonstrate simultaneous transmission of the radio and optical communications waveforms through to the physical layer (telescope and antenna). This paper details the hardware and software used in the platform and various measures of its performance. A laboratory optical receiver platform has also been assembled in order to demonstrate hybrid free space links in combination with the transmitter.

  13. Integrating cell on chip—Novel waveguide platform employing ultra-long optical paths

    Directory of Open Access Journals (Sweden)

    Lena Simone Fohrmann

    2017-09-01

    Full Text Available Optical waveguides are the most fundamental building blocks of integrated optical circuits. They are extremely well understood, yet there is still room for surprises. Here, we introduce a novel 2D waveguide platform which affords a strong interaction of the evanescent tail of a guided optical wave with an external medium while only employing a very small geometrical footprint. The key feature of the platform is its ability to integrate the ultra-long path lengths by combining low propagation losses in a silicon slab with multiple reflections of the guided wave from photonic crystal (PhC mirrors. With a reflectivity of 99.1% of our tailored PhC-mirrors, we achieve interaction paths of 25 cm within an area of less than 10 mm2. This corresponds to 0.17 dB/cm effective propagation which is much lower than the state-of-the-art loss of approximately 1 dB/cm of single mode silicon channel waveguides. In contrast to conventional waveguides, our 2D-approach leads to a decay of the guided wave power only inversely proportional to the optical path length. This entirely different characteristic is the major advantage of the 2D integrating cell waveguide platform over the conventional channel waveguide concepts that obey the Beer-Lambert law.

  14. Integrating cell on chip—Novel waveguide platform employing ultra-long optical paths

    Science.gov (United States)

    Fohrmann, Lena Simone; Sommer, Gerrit; Pitruzzello, Giampaolo; Krauss, Thomas F.; Petrov, Alexander Yu.; Eich, Manfred

    2017-09-01

    Optical waveguides are the most fundamental building blocks of integrated optical circuits. They are extremely well understood, yet there is still room for surprises. Here, we introduce a novel 2D waveguide platform which affords a strong interaction of the evanescent tail of a guided optical wave with an external medium while only employing a very small geometrical footprint. The key feature of the platform is its ability to integrate the ultra-long path lengths by combining low propagation losses in a silicon slab with multiple reflections of the guided wave from photonic crystal (PhC) mirrors. With a reflectivity of 99.1% of our tailored PhC-mirrors, we achieve interaction paths of 25 cm within an area of less than 10 mm2. This corresponds to 0.17 dB/cm effective propagation which is much lower than the state-of-the-art loss of approximately 1 dB/cm of single mode silicon channel waveguides. In contrast to conventional waveguides, our 2D-approach leads to a decay of the guided wave power only inversely proportional to the optical path length. This entirely different characteristic is the major advantage of the 2D integrating cell waveguide platform over the conventional channel waveguide concepts that obey the Beer-Lambert law.

  15. A web-based institutional DICOM distribution system with the integration of the Clinical Trial Processor (CTP).

    Science.gov (United States)

    Aryanto, K Y E; Broekema, A; Langenhuysen, R G A; Oudkerk, M; van Ooijen, P M A

    2015-05-01

    To develop and test a fast and easy rule-based web-environment with optional de-identification of imaging data to facilitate data distribution within a hospital environment. A web interface was built using Hypertext Preprocessor (PHP), an open source scripting language for web development, and Java with SQL Server to handle the database. The system allows for the selection of patient data and for de-identifying these when necessary. Using the services provided by the RSNA Clinical Trial Processor (CTP), the selected images were pushed to the appropriate services using a protocol based on the module created for the associated task. Five pipelines, each performing a different task, were set up in the server. In a 75 month period, more than 2,000,000 images are transferred and de-identified in a proper manner while 20,000,000 images are moved from one node to another without de-identification. While maintaining a high level of security and stability, the proposed system is easy to setup, it integrate well with our clinical and research practice and it provides a fast and accurate vendor-neutral process of transferring, de-identifying, and storing DICOM images. Its ability to run different de-identification processes in parallel pipelines is a major advantage in both clinical and research setting.

  16. Real time monitoring of electron processors

    International Nuclear Information System (INIS)

    Nablo, S.V.; Kneeland, D.R.; McLaughlin, W.L.

    1995-01-01

    A real time radiation monitor (RTRM) has been developed for monitoring the dose rate (current density) of electron beam processors. The system provides continuous monitoring of processor output, electron beam uniformity, and an independent measure of operating voltage or electron energy. In view of the device's ability to replace labor-intensive dosimetry in verification of machine performance on a real-time basis, its application to providing archival performance data for in-line processing is discussed. (author)

  17. Fast track trigger processor for the OPAL detector at LEP

    Energy Technology Data Exchange (ETDEWEB)

    Carter, A A; Carter, J R; Ward, D R; Heuer, R D; Jaroslawski, S; Wagner, A

    1986-09-20

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented.

  18. The Maia Spectroscopy Detector System: Engineering for Integrated Pulse Capture, Low-Latency Scanning and Real-Time Processing

    International Nuclear Information System (INIS)

    Kirkham, R.; Siddons, D.; Dunn, P.A.; Kuczewski, A.J.; Dodanwela, R.; Moorhead, G.F.; Ryan, C.G.; De Geronimo, G.; Beuttenmuller, R.; Pinelli, D.; Pfeffer, M.; Davey, P.; Jensen, M.; de Jonge, M.D.; Howard, D.L.; Kusel, M.; McKinlay, J.

    2010-01-01

    The Maia detector system is engineered for energy dispersive x-ray fluorescence spectroscopy and elemental imaging at photon rates exceeding 10 7 /s, integrated scanning of samples for pixel transit times as small as 50 (micro)s and high definition images of 10 8 pixels and real-time processing of detected events for spectral deconvolution and online display of pure elemental images. The system developed by CSIRO and BNL combines a planar silicon 384 detector array, application-specific integrated circuits for pulse shaping and peak detection and sampling and optical data transmission to an FPGA-based pipelined, parallel processor. This paper describes the system and the underpinning engineering solutions.

  19. Multi-processor data acquisition and monitoring systems for particle physics

    International Nuclear Information System (INIS)

    White, V.; Burch, B.; Eng, K.; Heinicke, P.; Pyatetsky, M.; Ritchie, D.

    1983-01-01

    A high speed distributed processing system, using PDP-11 and VAX processors, is being developed at Fermilab. The acquisition of data is done using one or more PDP-11s. Additional processors are connected to provide either data logging or extra data analysis capabilities. Within this framework, functional interchangeability of PDP-11 and VAX processors and of the PDP-11 operating systems, RT-11 and RSX-11M, has been maintained. Inter-processor connections have been implemented in a general way using the 5 megabit DR11-W hardware currently selected for the purpose. Using this approach the authors have been able to make use of several existing data acquisition and analysis packages, such as RT/MULTI, in a multi-processor system

  20. Deep Trek Re-configurable Processor for Data Acquisition (RPDA)

    Energy Technology Data Exchange (ETDEWEB)

    Bruce Ohme; Michael Johnson

    2009-06-30

    This report summarizes technical progress achieved during the cooperative research agreement between Honeywell and U.S. Department of Energy to develop a high-temperature Re-configurable Processor for Data Acquisition (RPDA). The RPDA development has incorporated multiple high-temperature (225C) electronic components within a compact co-fired ceramic Multi-Chip-Module (MCM) package. This assembly is suitable for use in down-hole oil and gas applications. The RPDA module is programmable to support a wide range of functionality. Specifically this project has demonstrated functional integrity of the RPDA package and internal components, as well as functional integrity of the RPDA configured to operate as a Multi-Channel Data Acquisition Controller. This report reviews the design considerations, electrical hardware design, MCM package design, considerations for manufacturing assembly, test and screening, and results from prototype assembly and characterization testing.

  1. GPU: the biggest key processor for AI and parallel processing

    Science.gov (United States)

    Baji, Toru

    2017-07-01

    Two types of processors exist in the market. One is the conventional CPU and the other is Graphic Processor Unit (GPU). Typical CPU is composed of 1 to 8 cores while GPU has thousands of cores. CPU is good for sequential processing, while GPU is good to accelerate software with heavy parallel executions. GPU was initially dedicated for 3D graphics. However from 2006, when GPU started to apply general-purpose cores, it was noticed that this architecture can be used as a general purpose massive-parallel processor. NVIDIA developed a software framework Compute Unified Device Architecture (CUDA) that make it possible to easily program the GPU for these application. With CUDA, GPU started to be used in workstations and supercomputers widely. Recently two key technologies are highlighted in the industry. The Artificial Intelligence (AI) and Autonomous Driving Cars. AI requires a massive parallel operation to train many-layers of neural networks. With CPU alone, it was impossible to finish the training in a practical time. The latest multi-GPU system with P100 makes it possible to finish the training in a few hours. For the autonomous driving cars, TOPS class of performance is required to implement perception, localization, path planning processing and again SoC with integrated GPU will play a key role there. In this paper, the evolution of the GPU which is one of the biggest commercial devices requiring state-of-the-art fabrication technology will be introduced. Also overview of the GPU demanding key application like the ones described above will be introduced.

  2. The Magnetic Physical Optics Scattered Field in Terms of a Line Integral

    DEFF Research Database (Denmark)

    Meincke, Peter; Breinbjerg, Olav; Jørgensen, Erik

    2000-01-01

    An exact line integral representation Is derived for the magnetic physical optics field scattered by a perfectly electrically conducting planar plate illuminated by a magnetic Hertzian dipole. A numerical example is presented to illustrate the exactness of the line integral representation...

  3. Integrable models of quantum optics

    Directory of Open Access Journals (Sweden)

    Yudson Vladimir

    2017-01-01

    Full Text Available We give an overview of exactly solvable many-body models of quantum optics. Among them is a system of two-level atoms which interact with photons propagating in a one-dimensional (1D chiral waveguide; exact eigenstates of this system can be explicitly constructed. This approach is used also for a system of closely located atoms in the usual (non-chiral waveguide or in 3D space. Moreover, it is shown that for an arbitrary atomic system with a cascade spontaneous radiative decay, the fluorescence spectrum can be described by an exact analytic expression which accounts for interference of emitted photons. Open questions related with broken integrability are discussed.

  4. Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices.

    Science.gov (United States)

    Bi, Lei; Hu, Juejun; Jiang, Peng; Kim, Hyun Suk; Kim, Dong Hun; Onbasli, Mehmet Cengiz; Dionne, Gerald F; Ross, Caroline A

    2013-11-08

    Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO₂ -δ , Co- or Fe-substituted SrTiO 3- δ , as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti 0.2 Ga 0.4 Fe 0.4 )O 3- δ and polycrystalline (CeY₂)Fe₅O 12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY₂)Fe₅O 12 /silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

  5. Rapid prototyping and evaluation of programmable SIMD SDR processors in LISA

    Science.gov (United States)

    Chen, Ting; Liu, Hengzhu; Zhang, Botao; Liu, Dongpei

    2013-03-01

    With the development of international wireless communication standards, there is an increase in computational requirement for baseband signal processors. Time-to-market pressure makes it impossible to completely redesign new processors for the evolving standards. Due to its high flexibility and low power, software defined radio (SDR) digital signal processors have been proposed as promising technology to replace traditional ASIC and FPGA fashions. In addition, there are large numbers of parallel data processed in computation-intensive functions, which fosters the development of single instruction multiple data (SIMD) architecture in SDR platform. So a new way must be found to prototype the SDR processors efficiently. In this paper we present a bit-and-cycle accurate model of programmable SIMD SDR processors in a machine description language LISA. LISA is a language for instruction set architecture which can gain rapid model at architectural level. In order to evaluate the availability of our proposed processor, three common baseband functions, FFT, FIR digital filter and matrix multiplication have been mapped on the SDR platform. Analytical results showed that the SDR processor achieved the maximum of 47.1% performance boost relative to the opponent processor.

  6. An ultra-efficient nonlinear planar integrated platform for optical signal processing and generation

    DEFF Research Database (Denmark)

    Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

    2017-01-01

    This paper will discuss the recently developed integrated platform: AlGaAs-oninsulator and its broad range of nonlinear applications. Recent demonstrations of broadband optical signal processing and efficient frequency comb generations in this platform will be reviewed.......This paper will discuss the recently developed integrated platform: AlGaAs-oninsulator and its broad range of nonlinear applications. Recent demonstrations of broadband optical signal processing and efficient frequency comb generations in this platform will be reviewed....

  7. Integrating photonics with silicon nanoelectronics for the next generation of systems on a chip.

    Science.gov (United States)

    Atabaki, Amir H; Moazeni, Sajjad; Pavanello, Fabio; Gevorgyan, Hayk; Notaros, Jelena; Alloatti, Luca; Wade, Mark T; Sun, Chen; Kruger, Seth A; Meng, Huaiyu; Al Qubaisi, Kenaish; Wang, Imbert; Zhang, Bohan; Khilo, Anatol; Baiocco, Christopher V; Popović, Miloš A; Stojanović, Vladimir M; Ram, Rajeev J

    2018-04-01

    Electronic and photonic technologies have transformed our lives-from computing and mobile devices, to information technology and the internet. Our future demands in these fields require innovation in each technology separately, but also depend on our ability to harness their complementary physics through integrated solutions 1,2 . This goal is hindered by the fact that most silicon nanotechnologies-which enable our processors, computer memory, communications chips and image sensors-rely on bulk silicon substrates, a cost-effective solution with an abundant supply chain, but with substantial limitations for the integration of photonic functions. Here we introduce photonics into bulk silicon complementary metal-oxide-semiconductor (CMOS) chips using a layer of polycrystalline silicon deposited on silicon oxide (glass) islands fabricated alongside transistors. We use this single deposited layer to realize optical waveguides and resonators, high-speed optical modulators and sensitive avalanche photodetectors. We integrated this photonic platform with a 65-nanometre-transistor bulk CMOS process technology inside a 300-millimetre-diameter-wafer microelectronics foundry. We then implemented integrated high-speed optical transceivers in this platform that operate at ten gigabits per second, composed of millions of transistors, and arrayed on a single optical bus for wavelength division multiplexing, to address the demand for high-bandwidth optical interconnects in data centres and high-performance computing 3,4 . By decoupling the formation of photonic devices from that of transistors, this integration approach can achieve many of the goals of multi-chip solutions 5 , but with the performance, complexity and scalability of 'systems on a chip' 1,6-8 . As transistors smaller than ten nanometres across become commercially available 9 , and as new nanotechnologies emerge 10,11 , this approach could provide a way to integrate photonics with state-of-the-art nanoelectronics.

  8. Integrated optical isolators using magnetic surface plasmon (Presentation Recording)

    Science.gov (United States)

    Shimizu, Hiromasa; Kaihara, Terunori; Umetsu, Saori; Hosoda, Masashi

    2015-09-01

    Optical isolators are one of the essential components to protect semiconductor laser diodes (LDs) from backward reflected light in integrated optics. In order to realize optical isolators, nonreciprocal propagation of light is necessary, which can be realized by magnetic materials. Semiconductor optical isolators have been strongly desired on Si and III/V waveguides. We have developed semiconductor optical isolators based on nonreciprocal loss owing to transverse magneto-optic Kerr effect, where the ferromagnetic metals are deposited on semiconductor optical waveguides1). Use of surface plasmon polariton at the interface of ferromagnetic metal and insulator leads to stronger optical confinement and magneto-optic effect. It is possible to modulate the optical confinement by changing the magnetic field direction, thus optical isolator operation is proposed2, 3). We have investigated surface plasmons at the interfaces between ferrimagnetic garnet/gold film, and applications to waveguide optical isolators. We assumed waveguides composed of Au/Si(38.63nm)/Ce:YIG(1700nm)/Si(220nm)/Si , and calculated the coupling lengths between Au/Si(38.63nm)/Ce:YIG plasmonic waveguide and Ce:YIG/Si(220nm)/Si waveguide for transversely magnetized Ce:YIG with forward and backward directions. The coupling length was calculated to 232.1um for backward propagating light. On the other hand, the coupling was not complete, and the length was calculated to 175.5um. The optical isolation by using the nonreciprocal coupling and propagation loss was calculated to be 43.7dB when the length of plasmonic waveguide is 700um. 1) H. Shimizu et al., J. Lightwave Technol. 24, 38 (2006). 2) V. Zayets et al., Materials, 5, 857-871 (2012). 3) J. Montoya, et al, J. Appl. Phys. 106, 023108, (2009).

  9. Stable integrated hyper-parametric oscillator based on coupled optical microcavities.

    Science.gov (United States)

    Armaroli, Andrea; Feron, Patrice; Dumeige, Yannick

    2015-12-01

    We propose a flexible scheme based on three coupled optical microcavities that permits us to achieve stable oscillations in the microwave range, the frequency of which depends only on the cavity coupling rates. We find that the different dynamical regimes (soft and hard excitation) affect the oscillation intensity, but not their periods. This configuration may permit us to implement compact hyper-parametric sources on an integrated optical circuit with interesting applications in communications, sensing, and metrology.

  10. Accelerating molecular dynamic simulation on the cell processor and Playstation 3.

    Science.gov (United States)

    Luttmann, Edgar; Ensign, Daniel L; Vaidyanathan, Vishal; Houston, Mike; Rimon, Noam; Øland, Jeppe; Jayachandran, Guha; Friedrichs, Mark; Pande, Vijay S

    2009-01-30

    Implementation of molecular dynamics (MD) calculations on novel architectures will vastly increase its power to calculate the physical properties of complex systems. Herein, we detail algorithmic advances developed to accelerate MD simulations on the Cell processor, a commodity processor found in PlayStation 3 (PS3). In particular, we discuss issues regarding memory access versus computation and the types of calculations which are best suited for streaming processors such as the Cell, focusing on implicit solvation models. We conclude with a comparison of improved performance on the PS3's Cell processor over more traditional processors. (c) 2008 Wiley Periodicals, Inc.

  11. Fast digital processor for event selection according to particle number difference

    International Nuclear Information System (INIS)

    Basiladze, S.G.; Gus'kov, B.N.; Li Van Sun; Maksimov, A.N.; Parfenov, A.N.

    1978-01-01

    A fast digital processor for a magnetic spectrometer is described. It is used in experimental searches for charmed particles. The basic purpose of the processor is discriminating events in the difference of numbers of particles passing through two proportional chambers (PC). The processor consists of three units for detecting signals with PC, and a binary coder. The number of inputs of the processor is 32 for the first PC and 64 for the second. The difference in the number of particles discriminated is from 0 to 8. The resolution time is 180 ns. The processor is built in the CAMAC standard

  12. Logistic Fuel Processor Development

    National Research Council Canada - National Science Library

    Salavani, Reza

    2004-01-01

    ... to light gases then steam reform the light gases into hydrogen rich stream. This report documents the efforts in developing a fuel processor capable of providing hydrogen to a 3kW fuel cell stack...

  13. A hybrid optic-fiber sensor network with the function of self-diagnosis and self-healing

    Science.gov (United States)

    Xu, Shibo; Liu, Tiegen; Ge, Chunfeng; Chen, Cheng; Zhang, Hongxia

    2014-11-01

    We develop a hybrid wavelength division multiplexing optical fiber network with distributed fiber-optic sensors and quasi-distributed FBG sensor arrays which detect vibrations, temperatures and strains at the same time. The network has the ability to locate the failure sites automatically designated as self-diagnosis and make protective switching to reestablish sensing service designated as self-healing by cooperative work of software and hardware. The processes above are accomplished by master-slave processors with the help of optical and wireless telemetry signals. All the sensing and optical telemetry signals transmit in the same fiber either working fiber or backup fiber. We take wavelength 1450nm as downstream signal and wavelength 1350nm as upstream signal to control the network in normal circumstances, both signals are sent by a light emitting node of the corresponding processor. There is also a continuous laser wavelength 1310nm sent by each node and received by next node on both working and backup fibers to monitor their healthy states, but it does not carry any message like telemetry signals do. When fibers of two sensor units are completely damaged, the master processor will lose the communication with the node between the damaged ones.However we install RF module in each node to solve the possible problem. Finally, the whole network state is transmitted to host computer by master processor. Operator could know and control the network by human-machine interface if needed.

  14. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Science.gov (United States)

    Barr, David R. W.; Dudek, Piotr

    2009-12-01

    We present a software environment for the efficient simulation of cellular processor arrays (CPAs). This software (APRON) is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  15. APRON: A Cellular Processor Array Simulation and Hardware Design Tool

    Directory of Open Access Journals (Sweden)

    David R. W. Barr

    2009-01-01

    Full Text Available We present a software environment for the efficient simulation of cellular processor arrays (CPAs. This software (APRON is used to explore algorithms that are designed for massively parallel fine-grained processor arrays, topographic multilayer neural networks, vision chips with SIMD processor arrays, and related architectures. The software uses a highly optimised core combined with a flexible compiler to provide the user with tools for the design of new processor array hardware architectures and the emulation of existing devices. We present performance benchmarks for the software processor array implemented on standard commodity microprocessors. APRON can be configured to use additional processing hardware if necessary and can be used as a complete graphical user interface and development environment for new or existing CPA systems, allowing more users to develop algorithms for CPA systems.

  16. Development of a synchrotron radiation beam monitor for the Integrable Optics Test Accelerator

    Energy Technology Data Exchange (ETDEWEB)

    Scarpelli, Andrea [Univ. of Ferrara (Italy)

    2016-01-01

    Nonlinear integrable optics applied to beam dynamics may mitigate multi-particle instabilities, but proof of principle experiments have never been carried out. The Integrable Optics Test Accelerator (IOTA) is an electron and proton storage ring currently being built at Fermilab, which addresses tests of nonlinear lattice elements in a real machine in addition to experiments on optical stochastic cooling and on the single-electron wave function. These experiments require an outstanding control over the lattice parameters, achievable with fast and precise beam monitoring systems. This work describes the steps for designing and building a beam monitor for IOTA based on synchrotron radiation, able to measure intensity, position and transverse cross-section beam.

  17. All-optical 40 Gbit/s compact integrated interferometric wavelength converter

    DEFF Research Database (Denmark)

    Jørgensen, Carsten; Danielsen, Søren Lykke; Hansen, Peter Bukhave

    1997-01-01

    An interferometric Michelson wavelength converter is presented that combines a speed-optimized semiconductor optical amplifier technology with the benefits of the integrated interferometer showing 40-Gbit/s wavelength conversion. The optimized wavelength converter demonstrates noninverted converted...

  18. Optical stretching of giant unilamellar vesicles with an integrated dual-beam optical trap.

    Science.gov (United States)

    Solmaz, Mehmet E; Biswas, Roshni; Sankhagowit, Shalene; Thompson, James R; Mejia, Camilo A; Malmstadt, Noah; Povinelli, Michelle L

    2012-10-01

    We have integrated a dual-beam optical trap into a microfluidic platform and used it to study membrane mechanics in giant unilamellar vesicles (GUVs). We demonstrate the trapping and stretching of GUVs and characterize the membrane response to a step stress. We then measure area strain as a function of applied stress to extract the bending modulus of the lipid bilayer in the low-tension regime.

  19. Design of all-optical high-order temporal integrators based on multiple-phase-shifted Bragg gratings.

    Science.gov (United States)

    Asghari, Mohammad H; Azaña, José

    2008-07-21

    In exact analogy with their electronic counterparts, photonic temporal integrators are fundamental building blocks for constructing all-optical circuits for ultrafast information processing and computing. In this work, we introduce a simple and general approach for realizing all-optical arbitrary-order temporal integrators. We demonstrate that the N(th) cumulative time integral of the complex field envelope of an input optical waveform can be obtained by simply propagating this waveform through a single uniform fiber/waveguide Bragg grating (BG) incorporating N pi-phase shifts along its axial profile. We derive here the design specifications of photonic integrators based on multiple-phase-shifted BGs. We show that the phase shifts in the BG structure can be arbitrarily located along the grating length provided that each uniform grating section (sections separated by the phase shifts) is sufficiently long so that its associated peak reflectivity reaches nearly 100%. The resulting designs are demonstrated by numerical simulations assuming all-fiber implementations. Our simulations show that the proposed approach can provide optical operation bandwidths in the tens-of-GHz regime using readily feasible photo-induced fiber BG structures.

  20. Integrated Optical Components Utilizing Long-Range Surface Plasmon Polaritons

    DEFF Research Database (Denmark)

    Boltasseva, Alexandra; Nikolajsen, Thomas; Leosson, Kristjan

    2005-01-01

    New optical waveguide technology for integrated optics, based on propagation of long-range surface plasmon polaritons (LR-SPPs) along metal stripes embedded in dielectric, is presented. Guiding and routing of electromagnetic radiation along nanometer-thin and micrometer-wide gold stripes embedded......), and a bend loss of ~5 dB for a bend radius of 15 mm are evaluated for 15-nm-thick and 8-mm-wide stripes at the wavelength of 1550 nm. LR-SPP-based 3-dB power Y-splitters, multimode interference waveguides, and directional couplers are demonstrated and investigated. At 1570 nm, coupling lengths of 1.9 and 0...

  1. Performance evaluation and comparison of fuel processors integrated with PEM fuel cell based on steam or autothermal reforming and on CO preferential oxidation or selective methanation

    International Nuclear Information System (INIS)

    Ercolino, Giuliana; Ashraf, Muhammad A.; Specchia, Vito; Specchia, Stefania

    2015-01-01

    Highlights: • Modeling of different fuel processors integrated with PEM fuel cell stack. • Steam or autothermal reforming + CO selective methanation or preferential oxidation. • Reforming of different hydrocarbons: gasoline, light diesel oil, natural gas. • 5 kW e net systems comparison via energy efficiency and primary fuel rate consumed. • Highest net efficiency: steam reformer + CO selective methanation based system. - Abstract: The performances of four different auxiliary power unit (APU) schemes, based on a 5 kW e net proton exchange membrane fuel cell (PEM-FC) stack, are evaluated and compared. The fuel processor section of each APU is characterized by a reformer (autothermal ATR or steam SR), a non-isothermal water gas shift (NI-WGS) reactor and a final syngas catalytic clean-up step: the CO preferential oxidation (PROX) reactor or the CO selective methanation (SMET) one. Furthermore, three hydrocarbon fuels, the most commonly found in service stations (gasoline, light diesel oil and natural gas) are considered as primary fuels. The comparison is carried out examining the results obtained by a series of steady-state system simulations in Aspen Plus® of the four different APU schemes by varying the fed fuel. From the calculated data, the performance of CO-PROX is not very different compared to that of the CO-SMET, but the performance of the SR based APUs is higher than the scheme of the ATR based APUs. The most promising APU scheme with respect to an overall performance target is the scheme fed with natural gas and characterized by a fuel processor chain consisting of SR, NI-WGS and CO-SMET reactors. This processing reactors scheme together with the fuel cell section, notwithstanding having practically the same energy efficiency of the scheme with SR, NI-WGS and CO-PROX reactors, ensures a less complex scheme, higher hydrogen concentration in the syngas, lower air mass rate consumption, the absence of nitrogen in the syngas and higher potential

  2. Improved parallel solution techniques for the integral transport matrix method

    Energy Technology Data Exchange (ETDEWEB)

    Zerr, R. Joseph, E-mail: rjz116@psu.edu [Department of Mechanical and Nuclear Engineering, The Pennsylvania State University, University Park, PA (United States); Azmy, Yousry Y., E-mail: yyazmy@ncsu.edu [Department of Nuclear Engineering, North Carolina State University, Burlington Engineering Laboratories, Raleigh, NC (United States)

    2011-07-01

    Alternative solution strategies to the parallel block Jacobi (PBJ) method for the solution of the global problem with the integral transport matrix method operators have been designed and tested. The most straightforward improvement to the Jacobi iterative method is the Gauss-Seidel alternative. The parallel red-black Gauss-Seidel (PGS) algorithm can improve on the number of iterations and reduce work per iteration by applying an alternating red-black color-set to the subdomains and assigning multiple sub-domains per processor. A parallel GMRES(m) method was implemented as an alternative to stationary iterations. Computational results show that the PGS method can improve on the PBJ method execution time by up to 10´ when eight sub-domains per processor are used. However, compared to traditional source iterations with diffusion synthetic acceleration, it is still approximately an order of magnitude slower. The best-performing cases are optically thick because sub-domains decouple, yielding faster convergence. Further tests revealed that 64 sub-domains per processor was the best performing level of sub-domain division. An acceleration technique that improves the convergence rate would greatly improve the ITMM. The GMRES(m) method with a diagonal block pre conditioner consumes approximately the same time as the PBJ solver but could be improved by an as yet undeveloped, more efficient pre conditioner. (author)

  3. Improved parallel solution techniques for the integral transport matrix method

    International Nuclear Information System (INIS)

    Zerr, R. Joseph; Azmy, Yousry Y.

    2011-01-01

    Alternative solution strategies to the parallel block Jacobi (PBJ) method for the solution of the global problem with the integral transport matrix method operators have been designed and tested. The most straightforward improvement to the Jacobi iterative method is the Gauss-Seidel alternative. The parallel red-black Gauss-Seidel (PGS) algorithm can improve on the number of iterations and reduce work per iteration by applying an alternating red-black color-set to the subdomains and assigning multiple sub-domains per processor. A parallel GMRES(m) method was implemented as an alternative to stationary iterations. Computational results show that the PGS method can improve on the PBJ method execution time by up to 10´ when eight sub-domains per processor are used. However, compared to traditional source iterations with diffusion synthetic acceleration, it is still approximately an order of magnitude slower. The best-performing cases are optically thick because sub-domains decouple, yielding faster convergence. Further tests revealed that 64 sub-domains per processor was the best performing level of sub-domain division. An acceleration technique that improves the convergence rate would greatly improve the ITMM. The GMRES(m) method with a diagonal block pre conditioner consumes approximately the same time as the PBJ solver but could be improved by an as yet undeveloped, more efficient pre conditioner. (author)

  4. Design of an optical temporal integrator based on a phase-shifted fiber Bragg grating in transmission.

    Science.gov (United States)

    Quoc Ngo, Nam

    2007-10-15

    We present a theoretical study of a new application of a simple pi-phase-shifted fiber Bragg grating (PSFBG) in transmission mode as a high-speed optical temporal integrator. The PSFBG consists of two concatenated identical uniform FBGs with a pi phase shift between them. When the reflectivities of the FBGs are extremely close to 100%, the transmissive PSFBG can perform the time integral of the complex envelope of an arbitrary input optical signal with high accuracy. As an example, the integrator is numerically shown to be able to convert an input Gaussian pulse into an optical step signal.

  5. A programmable two-qubit quantum processor in silicon.

    Science.gov (United States)

    Watson, T F; Philips, S G J; Kawakami, E; Ward, D R; Scarlino, P; Veldhorst, M; Savage, D E; Lagally, M G; Friesen, Mark; Coppersmith, S N; Eriksson, M A; Vandersypen, L M K

    2018-03-29

    Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing. In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform. Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations. However, as seen with small-scale demonstrations of quantum computers using other types of qubit, combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. Here we overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch-Josza algorithm and the Grover search algorithm-canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85-89 per cent and concurrences of 73-82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

  6. A programmable two-qubit quantum processor in silicon

    Science.gov (United States)

    Watson, T. F.; Philips, S. G. J.; Kawakami, E.; Ward, D. R.; Scarlino, P.; Veldhorst, M.; Savage, D. E.; Lagally, M. G.; Friesen, Mark; Coppersmith, S. N.; Eriksson, M. A.; Vandersypen, L. M. K.

    2018-03-01

    Now that it is possible to achieve measurement and control fidelities for individual quantum bits (qubits) above the threshold for fault tolerance, attention is moving towards the difficult task of scaling up the number of physical qubits to the large numbers that are needed for fault-tolerant quantum computing. In this context, quantum-dot-based spin qubits could have substantial advantages over other types of qubit owing to their potential for all-electrical operation and ability to be integrated at high density onto an industrial platform. Initialization, readout and single- and two-qubit gates have been demonstrated in various quantum-dot-based qubit representations. However, as seen with small-scale demonstrations of quantum computers using other types of qubit, combining these elements leads to challenges related to qubit crosstalk, state leakage, calibration and control hardware. Here we overcome these challenges by using carefully designed control techniques to demonstrate a programmable two-qubit quantum processor in a silicon device that can perform the Deutsch–Josza algorithm and the Grover search algorithm—canonical examples of quantum algorithms that outperform their classical analogues. We characterize the entanglement in our processor by using quantum-state tomography of Bell states, measuring state fidelities of 85–89 per cent and concurrences of 73–82 per cent. These results pave the way for larger-scale quantum computers that use spins confined to quantum dots.

  7. Structure of modes of smoothly irregular three-dimensional integrated optical four-layer waveguide

    International Nuclear Information System (INIS)

    Egorov, A.A.; Ajryan, Eh.A.; Sevast'yanov, A.L.; Sevast'yanov, L.A.

    2009-01-01

    As a method of research of an integrated optical multilayer waveguide, satisfying the condition of smooth modification of the shape of the studied three-dimensional structure, an asymptotic method is used. Three-dimensional fields of smoothly deforming modes of the integrated optical waveguide are circumscribed analytically. An evident dependence of the contributions of the first order of smallness in the amplitudes of the electrical and magnetic fields of the quasi-waveguide modes is obtained. The canonical type of the equations circumscribing propagation of quasi-TE and quasi-TM modes in the smoothly irregular part of a four-layer integrated optical waveguide is represented for an asymptotic method. With the help of the method of coupled waves and perturbation theory method, the shifts of complex propagation constants for quasi-TE and quasi-TM modes are obtained in an explicit form. The elaborated theory is applicable for the analysis of similar structures of dielectric, magnetic and metamaterials in a sufficiently broad band of electromagnetic wavelengths

  8. High performance graphics processors for medical imaging applications

    International Nuclear Information System (INIS)

    Goldwasser, S.M.; Reynolds, R.A.; Talton, D.A.; Walsh, E.S.

    1989-01-01

    This paper describes a family of high- performance graphics processors with special hardware for interactive visualization of 3D human anatomy. The basic architecture expands to multiple parallel processors, each processor using pipelined arithmetic and logical units for high-speed rendering of Computed Tomography (CT), Magnetic Resonance (MR) and Positron Emission Tomography (PET) data. User-selectable display alternatives include multiple 2D axial slices, reformatted images in sagittal or coronal planes and shaded 3D views. Special facilities support applications requiring color-coded display of multiple datasets (such as radiation therapy planning), or dynamic replay of time- varying volumetric data (such as cine-CT or gated MR studies of the beating heart). The current implementation is a single processor system which generates reformatted images in true real time (30 frames per second), and shaded 3D views in a few seconds per frame. It accepts full scale medical datasets in their native formats, so that minimal preprocessing delay exists between data acquisition and display

  9. Evaluation of the Intel Westmere-EP server processor

    CERN Document Server

    Jarp, S; Leduc, J; Nowak, A; CERN. Geneva. IT Department

    2010-01-01

    In this paper we report on a set of benchmark results recently obtained by CERN openlab when comparing the 6-core “Westmere-EP” processor with Intel’s previous generation of the same microarchitecture, the “Nehalem-EP”. The former is produced in a new 32nm process, the latter in 45nm. Both platforms are dual-socket servers. Multiple benchmarks were used to get a good understanding of the performance of the new processor. We used both industry-standard benchmarks, such as SPEC2006, and specific High Energy Physics benchmarks, representing both simulation of physics detectors and data analysis of physics events. Before summarizing the results we must stress the fact that benchmarking of modern processors is a very complex affair. One has to control (at least) the following features: processor frequency, overclocking via Turbo mode, the number of physical cores in use, the use of logical cores via Simultaneous Multi-Threading (SMT), the cache sizes available, the memory configuration installed, as well...

  10. Keystone Business Models for Network Security Processors

    OpenAIRE

    Arthur Low; Steven Muegge

    2013-01-01

    Network security processors are critical components of high-performance systems built for cybersecurity. Development of a network security processor requires multi-domain experience in semiconductors and complex software security applications, and multiple iterations of both software and hardware implementations. Limited by the business models in use today, such an arduous task can be undertaken only by large incumbent companies and government organizations. Neither the “fabless semiconductor...

  11. Development of level 2 processor for the readout of TMC

    International Nuclear Information System (INIS)

    Arai, Y.; Ikeno, M.; Murata, T.; Sudo, F.; Emura, T.

    1995-01-01

    We have developed a prototype 8-bit processor for the level 2 data processing for the Time Memory Cell (TMC). The first prototype processor successfully runs with 18 MHz clock. The operation of same clock frequency as TMC (30 MHz) will be easily achieved with simple modifications. Although the processor is very primitive one but shows its powerful performance and flexibility. To realize the compact TMC/L2P (Level 2 Processor) system, it is better to include the microcode memory within the chip. Encoding logic of the microcode must be included to reduce the microcode memory in this case. (J.P.N.)

  12. System performances of optical space code-division multiple-access-based fiber-optic two-dimensional parallel data link.

    Science.gov (United States)

    Nakamura, M; Kitayama, K

    1998-05-10

    Optical space code-division multiple access is a scheme to multiplex and link data between two-dimensional processors such as smart pixels and spatial light modulators or arrays of optical sources like vertical-cavity surface-emitting lasers. We examine the multiplexing characteristics of optical space code-division multiple access by using optical orthogonal signature patterns. The probability density function of interference noise in interfering optical orthogonal signature patterns is calculated. The bit-error rate is derived from the result and plotted as a function of receiver threshold, code length, code weight, and number of users. Furthermore, we propose a prethresholding method to suppress the interference noise, and we experimentally verify that the method works effectively in improving system performance.

  13. Optical wear monitoring

    Science.gov (United States)

    Kidane, Getnet S; Desilva, Upul P.; He, Chengli; Ulerich, Nancy H.

    2016-07-26

    A gas turbine includes first and second parts having outer surfaces located adjacent to each other to create an interface where wear occurs. A wear probe is provided for monitoring wear of the outer surface of the first part, and includes an optical guide having first and second ends, wherein the first end is configured to be located flush with the outer surface of the first part. A fiber bundle includes first and second ends, the first end being located proximate to the second end of the optical guide. The fiber bundle includes a transmit fiber bundle comprising a first plurality of optical fibers coupled to a light source, and a receive fiber bundle coupled to a light detector and configured to detect reflected light. A processor is configured to determine a length of the optical guide based on the detected reflected light.

  14. Advanced integrated spectrometer designs for miniaturized optical coherence tomography systems

    NARCIS (Netherlands)

    Akça, B.I.; Povazay, B.; Chang, Lantian; Alex, A.; Worhoff, Kerstin; de Ridder, R.M.; Drexler, W.; Pollnau, Markus

    Optical coherence tomography (OCT) has enabled clinical applications that revolutionized in vivo medical diagnostics. Nevertheless, its current limitations owing to cost, size, complexity, and the need for accurate alignment must be overcome by radically novel approaches. Exploiting integrated

  15. ISOGA: Integrated Services Optical Grid Architecture for Emerging E-Science Collaborative Applications

    Energy Technology Data Exchange (ETDEWEB)

    Oliver Yu

    2008-11-28

    This final report describes the accomplishments in the ISOGA (Integrated Services Optical Grid Architecture) project. ISOGA enables efficient deployment of existing and emerging collaborative grid applications with increasingly diverse multimedia communication requirements over a wide-area multi-domain optical network grid; and enables collaborative scientists with fast retrieval and seamless browsing of distributed scientific multimedia datasets over a wide-area optical network grid. The project focuses on research and development in the following areas: the polymorphic optical network control planes to enable multiple switching and communication services simultaneously; the intelligent optical grid user-network interface to enable user-centric network control and monitoring; and the seamless optical grid dataset browsing interface to enable fast retrieval of local/remote dataset for visualization and manipulation.

  16. Integration and application of optical chemical sensors in microbioreactors.

    Science.gov (United States)

    Gruber, Pia; Marques, Marco P C; Szita, Nicolas; Mayr, Torsten

    2017-08-08

    The quantification of key variables such as oxygen, pH, carbon dioxide, glucose, and temperature provides essential information for biological and biotechnological applications and their development. Microfluidic devices offer an opportunity to accelerate research and development in these areas due to their small scale, and the fine control over the microenvironment, provided that these key variables can be measured. Optical sensors are well-suited for this task. They offer non-invasive and non-destructive monitoring of the mentioned variables, and the establishment of time-course profiles without the need for sampling from the microfluidic devices. They can also be implemented in larger systems, facilitating cross-scale comparison of analytical data. This tutorial review presents an overview of the optical sensors and their technology, with a view to support current and potential new users in microfluidics and biotechnology in the implementation of such sensors. It introduces the benefits and challenges of sensor integration, including, their application for microbioreactors. Sensor formats, integration methods, device bonding options, and monitoring options are explained. Luminescent sensors for oxygen, pH, carbon dioxide, glucose and temperature are showcased. Areas where further development is needed are highlighted with the intent to guide future development efforts towards analytes for which reliable, stable, or easily integrated detection methods are not yet available.

  17. Definition, analysis and development of an optical data distribution network for integrated avionics and control systems. Part 2: Component development and system integration

    Science.gov (United States)

    Yen, H. W.; Morrison, R. J.

    1984-01-01

    Fiber optic transmission is emerging as an attractive concept in data distribution onboard civil aircraft. Development of an Optical Data Distribution Network for Integrated Avionics and Control Systems for commercial aircraft will provide a data distribution network that gives freedom from EMI-RFI and ground loop problems, eliminates crosstalk and short circuits, provides protection and immunity from lightning induced transients and give a large bandwidth data transmission capability. In addition there is a potential for significantly reducing the weight and increasing the reliability over conventional data distribution networks. Wavelength Division Multiplexing (WDM) is a candidate method for data communication between the various avionic subsystems. With WDM all systems could conceptually communicate with each other without time sharing and requiring complicated coding schemes for each computer and subsystem to recognize a message. However, the state of the art of optical technology limits the application of fiber optics in advanced integrated avionics and control systems. Therefore, it is necessary to address the architecture for a fiber optics data distribution system for integrated avionics and control systems as well as develop prototype components and systems.

  18. Review of trigger and on-line processors at SLAC

    International Nuclear Information System (INIS)

    Lankford, A.J.

    1984-07-01

    The role of trigger and on-line processors in reducing data rates to manageable proportions in e + e - physics experiments is defined not by high physics or background rates, but by the large event sizes of the general-purpose detectors employed. The rate of e + e - annihilation is low, and backgrounds are not high; yet the number of physics processes which can be studied is vast and varied. This paper begins by briefly describing the role of trigger processors in the e + e - context. The usual flow of the trigger decision process is illustrated with selected examples of SLAC trigger processing. The features are mentioned of triggering at the SLC and the trigger processing plans of the two SLC detectors: The Mark II and the SLD. The most common on-line processors at SLAC, the BADC, the SLAC Scanner Processor, the SLAC FASTBUS Controller, and the VAX CAMAC Channel, are discussed. Uses of the 168/E, 3081/E, and FASTBUS VAX processors are mentioned. The manner in which these processors are interfaced and the function they serve on line is described. Finally, the accelerator control system for the SLC is outlined. This paper is a survey in nature, and hence, relies heavily upon references to previous publications for detailed description of work mentioned here. 27 references, 9 figures, 1 table

  19. INVESTIGATING THE OPTICAL COUNTERPART CANDIDATES OF FOUR INTEGRAL SOURCES LOCALIZED WITH CHANDRA

    International Nuclear Information System (INIS)

    Özbey Arabacı, Mehtap; Kalemci, Emrah; Tomsick, John A.; Bodaghee, Arash; Halpern, Jules; Chaty, Sylvain; Rodriguez, Jerome; Rahoui, Farid

    2012-01-01

    We report on the optical spectroscopic follow-up observations of the candidate counterparts to four INTEGRAL sources: IGR J04069+5042, IGR J06552–1146, IGR J21188+4901, and IGR J22014+6034. The candidate counterparts were determined with Chandra, and the optical observations were performed with 1.5 m RTT-150 telescope (TÜBİTAK National Observatory, Antalya, Turkey) and 2.4 m Hiltner Telescope (MDM Observatory, Kitt Peak, Arizona). Our spectroscopic results show that one of the two candidates of IGR J04069+5042 and the one observed for IGR J06552–1146 could be active late-type stars in RS CVn systems. However, according to the likelihood analysis based on Chandra and INTEGRAL, two optically weaker sources in the INTEGRAL error circle of IGR J06552–1146 have higher probabilities to be the actual counterpart. The candidate counterparts of IGR J21188+4901 are classified as an active M-type star and a late-type star. Among the optical spectra of four candidates of IGR J22014+6034, two show Hα emission lines, one is a late-type star, and the other is an M type. The likelihood analysis favors a candidate with no distinguishing features in the optical spectrum. Two of the candidates classified as M-type dwarfs, are similar to some IGR candidates claimed to be symbiotic stars. However, some of the prominent features of symbiotic systems are missing in our spectra, and their NIR colors are not consistent with those expected for giants. We consider the IR colors of all IGR candidates claimed to be symbiotic systems and find that low-resolution optical spectrum may not be enough for conclusive identification.

  20. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  1. Magneto-Optical Thin Films for On-Chip Monolithic Integration of Non-Reciprocal Photonic Devices

    Directory of Open Access Journals (Sweden)

    Mehmet Cengiz Onbasli

    2013-11-01

    Full Text Available Achieving monolithic integration of nonreciprocal photonic devices on semiconductor substrates has been long sought by the photonics research society. One way to achieve this goal is to deposit high quality magneto-optical oxide thin films on a semiconductor substrate. In this paper, we review our recent research activity on magneto-optical oxide thin films toward the goal of monolithic integration of nonreciprocal photonic devices on silicon. We demonstrate high Faraday rotation at telecommunication wavelengths in several novel magnetooptical oxide thin films including Co substituted CeO2−δ, Co- or Fe-substituted SrTiO3−δ, as well as polycrystalline garnets on silicon. Figures of merit of 3~4 deg/dB and 21 deg/dB are achieved in epitaxial Sr(Ti0.2Ga0.4Fe0.4O3−δ and polycrystalline (CeY2Fe5O12 films, respectively. We also demonstrate an optical isolator on silicon, based on a racetrack resonator using polycrystalline (CeY2Fe5O12/silicon strip-loaded waveguides. Our work demonstrates that physical vapor deposited magneto-optical oxide thin films on silicon can achieve high Faraday rotation, low optical loss and high magneto-optical figure of merit, therefore enabling novel high-performance non-reciprocal photonic devices monolithically integrated on semiconductor substrates.

  2. Integration of optical fibers in radiative environments: Advantages and limitations

    International Nuclear Information System (INIS)

    Girard, S.; Ouerdane, Y.; Boukenter, A.; Marcandella, C.; Bisutti, J.; Baggio, J.; Meunier, J. P.

    2011-01-01

    We review the advantages and limitations for the integration of optical fibers in radiative environments. Optical fibers present numerous advantages for applications in harsh environments such as their electromagnetic immunity. This explains the increasing interest of the radiation effects community to evaluate their vulnerability for future facilities. However, it is also well-known that optical fibers suffer from a degradation of their macroscopic properties under irradiation. We illustrate the major mechanisms and parameters that govern the degradation mechanism, mainly the radiation-induced attenuation phenomena. We focus on the fiber transient radiation responses when exposed to the pulsed and mixed environment associated with the Megajoule class lasers devoted to the fusion by inertial confinement study. (authors)

  3. Simulation of a 250 kW diesel fuel processor/PEM fuel cell system

    Science.gov (United States)

    Amphlett, J. C.; Mann, R. F.; Peppley, B. A.; Roberge, P. R.; Rodrigues, A.; Salvador, J. P.

    Polymer-electrolyte membrane (PEM) fuel cell systems offer a potential power source for utility and mobile applications. Practical fuel cell systems use fuel processors for the production of hydrogen-rich gas. Liquid fuels, such as diesel or other related fuels, are attractive options as feeds to a fuel processor. The generation of hydrogen gas for fuel cells, in most cases, becomes the crucial design issue with respect to weight and volume in these applications. Furthermore, these systems will require a gas clean-up system to insure that the fuel quality meets the demands of the cell anode. The endothermic nature of the reformer will have a significant affect on the overall system efficiency. The gas clean-up system may also significantly effect the overall heat balance. To optimize the performance of this integrated system, therefore, waste heat must be used effectively. Previously, we have concentrated on catalytic methanol-steam reforming. A model of a methanol steam reformer has been previously developed and has been used as the basis for a new, higher temperature model for liquid hydrocarbon fuels. Similarly, our fuel cell evaluation program previously led to the development of a steady-state electrochemical fuel cell model (SSEM). The hydrocarbon fuel processor model and the SSEM have now been incorporated in the development of a process simulation of a 250 kW diesel-fueled reformer/fuel cell system using a process simulator. The performance of this system has been investigated for a variety of operating conditions and a preliminary assessment of thermal integration issues has been carried out. This study demonstrates the application of a process simulation model as a design analysis tool for the development of a 250 kW fuel cell system.

  4. FY1995 study of design methodology and environment of high-performance processor architectures; 1995 nendo koseino processor architecture sekkeiho to sekkei kankyo no kenkyu

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    1997-03-01

    The aim of our project is to develop high-performance processor architectures for both general purpose and application-specific purpose. We also plan to develop basic softwares, such as compliers, and various design aid tools for those architectures. We are particularly interested in performance evaluation at architecture design phase, design optimization, automatic generation of compliers from processor designs, and architecture design methodologies combined with circuit layout. We have investigated both microprocessor architectures and design methodologies / environments for the processors. Our goal is to establish design technologies for high-performance, low-power, low-cost and highly-reliable systems in system-on-silicon era. We have proposed PPRAM architecture for high-performance system using DRAM and logic mixture technology, Softcore processor architecture for special purpose processors in embedded systems, and Power-Pro architecture for low power systems. We also developed design methodologies and design environments for the above architectures as well as a new method for design verification of microprocessors. (NEDO)

  5. All-optical phase modulation for integrated interferometric biosensors.

    Science.gov (United States)

    Dante, Stefania; Duval, Daphné; Sepúlveda, Borja; González-Guerrero, Ana Belen; Sendra, José Ramón; Lechuga, Laura M

    2012-03-26

    We present the theoretical and the experimental implementation of an all-optical phase modulation system in integrated Mach-Zehnder Interferometers to solve the drawbacks related to the periodic nature of the interferometric signal. Sensor phase is tuned by modulating the emission wavelength of low-cost commercial laser diodes by changing their output power. FFT deconvolution of the signal allows for direct phase readout, immune to sensitivity variations and to light intensity fluctuations. This simple phase modulation scheme increases the signal-to-noise ratio of the measurements in one order of magnitude, rendering in a sensor with a detection limit of 1.9·10⁻⁷ RIU. The viability of the all-optical modulation approach is demonstrated with an immunoassay detection as a biosensing proof of concept.

  6. All-optical quantum computing with a hybrid solid-state processing unit

    International Nuclear Information System (INIS)

    Pei Pei; Zhang Fengyang; Li Chong; Song Heshan

    2011-01-01

    We develop an architecture of a hybrid quantum solid-state processing unit for universal quantum computing. The architecture allows distant and nonidentical solid-state qubits in distinct physical systems to interact and work collaboratively. All the quantum computing procedures are controlled by optical methods using classical fields and cavity QED. Our methods have a prominent advantage of the insensitivity to dissipation process benefiting from the virtual excitation of subsystems. Moreover, the quantum nondemolition measurements and state transfer for the solid-state qubits are proposed. The architecture opens promising perspectives for implementing scalable quantum computation in a broader sense that different solid-state systems can merge and be integrated into one quantum processor afterward.

  7. A comparison of integrated and fiber optic responses in the presence of nuclear fields

    International Nuclear Information System (INIS)

    Taylor, E.W.; Wilson, V.R.; Sanchez, A.D.; Coughenour, M.; Chapman, S.

    1988-01-01

    A short survey of past experimental results is presented along with new investigative data, mathematical and physical response models and a comparison of the nuclear effects compatibility of fiber and integrated optic guided wave structures. The disparity in radiation resistance between optical fibers and guided wave structures is discussed and predictions are offered on the impact that these differences may have on influencing the eventual development of totally integrated radiation resistant structures

  8. Designing a dataflow processor using CλaSH

    NARCIS (Netherlands)

    Niedermeier, A.; Wester, Rinse; Wester, Rinse; Rovers, K.C.; Baaij, C.P.R.; Kuper, Jan; Smit, Gerardus Johannes Maria

    2010-01-01

    In this paper we show how a simple dataflow processor can be fully implemented using CλaSH, a high level HDL based on the functional programming language Haskell. The processor was described using Haskell, the CλaSH compiler was then used to translate the design into a fully synthesisable VHDL code.

  9. Optically controlled phased array antenna concepts using GaAs monolithic microwave integrated circuits

    Science.gov (United States)

    Kunath, R. R.; Bhasin, K. B.

    1986-01-01

    The desire for rapid beam reconfigurability and steering has led to the exploration of new techniques. Optical techniques have been suggested as potential candidates for implementing these needs. Candidates generally fall into one of two areas: those using fiber optic Beam Forming Networks (BFNs) and those using optically processed BFNs. Both techniques utilize GaAs Monolithic Microwave Integrated Circuits (MMICs) in the BFN, but the role of the MMIC for providing phase and amplitude variations is largely eliminated by some new optical processing techniques. This paper discusses these two types of optical BFN designs and provides conceptual designs of both systems.

  10. Researching, building a soft-processor and Ethernet interface circuit using EDK

    International Nuclear Information System (INIS)

    Tuong Thi Thu Huong; Pham Ngoc Tuan; Truong Van Dat, Dang Lanh; Chau Thi Nhu Quynh

    2014-01-01

    The processor is an indispensable component in the measurement and automatic control systems. This report describes the fabrication of a soft-processor (32-bits, on-chip block RAM 64K, 50M clock, internal and peripheral bus) for receiving, sending and processing of data Ethernet packets. This processor is fabricated using the XPS component from EDK (Xilinx) software toolkit. After that, it is configured on the FPGA named Spartan XC3S500E circuit. A firmware of a processor for controlling the interface between processor and Ethernet port is written in C language and can play a role of a HOST (station) which has its own IP to connect to Ethernet network. Besides, there are some needed parts as follows: an Ethernet interfacing controller chip, a suitable cable providing a speed up to 100 Mbs and an application program running under Window XP environment written in LabView to communicate with soft-processor. (author)

  11. An integral design strategy combining optical system and image processing to obtain high resolution images

    Science.gov (United States)

    Wang, Jiaoyang; Wang, Lin; Yang, Ying; Gong, Rui; Shao, Xiaopeng; Liang, Chao; Xu, Jun

    2016-05-01

    In this paper, an integral design that combines optical system with image processing is introduced to obtain high resolution images, and the performance is evaluated and demonstrated. Traditional imaging methods often separate the two technical procedures of optical system design and imaging processing, resulting in the failures in efficient cooperation between the optical and digital elements. Therefore, an innovative approach is presented to combine the merit function during optical design together with the constraint conditions of image processing algorithms. Specifically, an optical imaging system with low resolution is designed to collect the image signals which are indispensable for imaging processing, while the ultimate goal is to obtain high resolution images from the final system. In order to optimize the global performance, the optimization function of ZEMAX software is utilized and the number of optimization cycles is controlled. Then Wiener filter algorithm is adopted to process the image simulation and mean squared error (MSE) is taken as evaluation criterion. The results show that, although the optical figures of merit for the optical imaging systems is not the best, it can provide image signals that are more suitable for image processing. In conclusion. The integral design of optical system and image processing can search out the overall optimal solution which is missed by the traditional design methods. Especially, when designing some complex optical system, this integral design strategy has obvious advantages to simplify structure and reduce cost, as well as to gain high resolution images simultaneously, which has a promising perspective of industrial application.

  12. Low voltage 80 KV to 125 KV electron processors

    International Nuclear Information System (INIS)

    Lauppi, U.V.

    1999-01-01

    The classic electron beam technology made use of accelerating energies in the voltage range of 300 to 800 kV. The first EB processors - built for the curing of coatings - operated at 300 kV. The products to be treated were thicker than a simple layer of coating with thicknesses up to 100g and more. It was only in the beginning of the 1970's that industrial EB processors with accelerating voltages below 300 kV appeared on the market. Our company developed the first commercial electron accelerator without a beam scanner. The new EB machine featured a linear cathode, emitting a shower or 'curtain' of electrons over the full width of the product. These units were much smaller than anv previous EB processors and dedicated to the curing of coatings and other thin layers. ESI's first EB units operated with accelerating voltages between 150 and 200 kV. In 1993 ESI announced the introduction of a new generation of Electrocure. EB processors operating at 120 kV, and in 1998, at the RadTech North America '98 Conference in Chicago, the introduction of an 80 kV electron beam processor under the designation Microbeam LV

  13. A fast track trigger processor for the OPAL detector at LEP

    International Nuclear Information System (INIS)

    Carter, A.A.; Jaroslawski, S.; Wagner, A.

    1986-01-01

    A fast hardware track trigger processor being built for the OPAL experiment is described. The processor will analyse data from the central drift chambers of OPAL to determine whether any tracks come from the interaction region, and thereby eliminate background events. The processor will find tracks over a large angular range, vertical strokecos thetavertical stroke < or approx. 0.95. The design of the processor is described, together with a brief account of its hardware implementation for OPAL. The results of feasibility studies are also presented. (orig.)

  14. Launching applications on compute and service processors running under different operating systems in scalable network of processor boards with routers

    Science.gov (United States)

    Tomkins, James L [Albuquerque, NM; Camp, William J [Albuquerque, NM

    2009-03-17

    A multiple processor computing apparatus includes a physical interconnect structure that is flexibly configurable to support selective segregation of classified and unclassified users. The physical interconnect structure also permits easy physical scalability of the computing apparatus. The computing apparatus can include an emulator which permits applications from the same job to be launched on processors that use different operating systems.

  15. Ultrafast all-optical integrator based on a fiber Bragg grating: proposal and design.

    Science.gov (United States)

    Preciado, Miguel A; Muriel, Miguel A

    2008-06-15

    We demonstrate a simple technique for the implementation of an all-optical integrator based on a uniform-period fiber Bragg grating (FBG) in reflection that is designed to present a decreasing exponential impulse response. The proposed FBG integrator is readily feasible and can perform close to ideal integration of few-picosecond and subpicosecond pulses.

  16. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector

    NARCIS (Netherlands)

    Lee, M.J.; Youn, J.S.; Park, K.Y.; Choi, W.Y.

    2014-01-01

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche

  17. Particle simulation on a distributed memory highly parallel processor

    International Nuclear Information System (INIS)

    Sato, Hiroyuki; Ikesaka, Morio

    1990-01-01

    This paper describes parallel molecular dynamics simulation of atoms governed by local force interaction. The space in the model is divided into cubic subspaces and mapped to the processor array of the CAP-256, a distributed memory, highly parallel processor developed at Fujitsu Labs. We developed a new technique to avoid redundant calculation of forces between atoms in different processors. Experiments showed the communication overhead was less than 5%, and the idle time due to load imbalance was less than 11% for two model problems which contain 11,532 and 46,128 argon atoms. From the software simulation, the CAP-II which is under development is estimated to be about 45 times faster than CAP-256 and will be able to run the same problem about 40 times faster than Fujitsu's M-380 mainframe when 256 processors are used. (author)

  18. Code compression for VLIW embedded processors

    Science.gov (United States)

    Piccinelli, Emiliano; Sannino, Roberto

    2004-04-01

    The implementation of processors for embedded systems implies various issues: main constraints are cost, power dissipation and die area. On the other side, new terminals perform functions that require more computational flexibility and effort. Long code streams must be loaded into memories, which are expensive and power consuming, to run on DSPs or CPUs. To overcome this issue, the "SlimCode" proprietary algorithm presented in this paper (patent pending technology) can reduce the dimensions of the program memory. It can run offline and work directly on the binary code the compiler generates, by compressing it and creating a new binary file, about 40% smaller than the original one, to be loaded into the program memory of the processor. The decompression unit will be a small ASIC, placed between the Memory Controller and the System bus of the processor, keeping unchanged the internal CPU architecture: this implies that the methodology is completely transparent to the core. We present comparisons versus the state-of-the-art IBM Codepack algorithm, along with its architectural implementation into the ST200 VLIW family core.

  19. Optical Flow in a Smart Sensor Based on Hybrid Analog-Digital Architecture

    Directory of Open Access Journals (Sweden)

    Pablo Guzmán

    2010-03-01

    Full Text Available The purpose of this study is to develop a motion sensor (delivering optical flow estimations using a platform that includes the sensor itself, focal plane processing resources, and co-processing resources on a general purpose embedded processor. All this is implemented on a single device as a SoC (System-on-a-Chip. Optical flow is the 2-D projection into the camera plane of the 3-D motion information presented at the world scenario. This motion representation is widespread well-known and applied in the science community to solve a wide variety of problems. Most applications based on motion estimation require work in real-time; hence, this restriction must be taken into account. In this paper, we show an efficient approach to estimate the motion velocity vectors with an architecture based on a focal plane processor combined on-chip with a 32 bits NIOS II processor. Our approach relies on the simplification of the original optical flow model and its efficient implementation in a platform that combines an analog (focal-plane and digital (NIOS II processor. The system is fully functional and is organized in different stages where the early processing (focal plane stage is mainly focus to pre-process the input image stream to reduce the computational cost in the post-processing (NIOS II stage. We present the employed co-design techniques and analyze this novel architecture. We evaluate the system’s performance and accuracy with respect to the different proposed approaches described in the literature. We also discuss the advantages of the proposed approach as well as the degree of efficiency which can be obtained from the focal plane processing capabilities of the system. The final outcome is a low cost smart sensor for optical flow computation with real-time performance and reduced power consumption that can be used for very diverse application domains.

  20. Optical Flow in a Smart Sensor Based on Hybrid Analog-Digital Architecture

    Science.gov (United States)

    Guzmán, Pablo; Díaz, Javier; Agís, Rodrigo; Ros, Eduardo

    2010-01-01

    The purpose of this study is to develop a motion sensor (delivering optical flow estimations) using a platform that includes the sensor itself, focal plane processing resources, and co-processing resources on a general purpose embedded processor. All this is implemented on a single device as a SoC (System-on-a-Chip). Optical flow is the 2-D projection into the camera plane of the 3-D motion information presented at the world scenario. This motion representation is widespread well-known and applied in the science community to solve a wide variety of problems. Most applications based on motion estimation require work in real-time; hence, this restriction must be taken into account. In this paper, we show an efficient approach to estimate the motion velocity vectors with an architecture based on a focal plane processor combined on-chip with a 32 bits NIOS II processor. Our approach relies on the simplification of the original optical flow model and its efficient implementation in a platform that combines an analog (focal-plane) and digital (NIOS II) processor. The system is fully functional and is organized in different stages where the early processing (focal plane) stage is mainly focus to pre-process the input image stream to reduce the computational cost in the post-processing (NIOS II) stage. We present the employed co-design techniques and analyze this novel architecture. We evaluate the system’s performance and accuracy with respect to the different proposed approaches described in the literature. We also discuss the advantages of the proposed approach as well as the degree of efficiency which can be obtained from the focal plane processing capabilities of the system. The final outcome is a low cost smart sensor for optical flow computation with real-time performance and reduced power consumption that can be used for very diverse application domains. PMID:22319283

  1. Graphical user interface for TOUGH/TOUGH2 - development of database, pre-processor, and post-processor

    Energy Technology Data Exchange (ETDEWEB)

    Sato, Tatsuya; Okabe, Takashi; Osato, Kazumi [Geothermal Energy Research and Development Co., Ltd., Tokyo (Japan)

    1995-03-01

    One of the advantages of the TOUGH/TOUGH2 (Pruess, 1987 and 1991) is the modeling using {open_quotes}free shape{close_quotes} polygonal blocks. However, the treatment of three-dimensional information, particularly for TOUGH/TOUGH2 is not easy because of the {open_quotes}free shape{close_quotes} polygonal blocks. Therefore, we have developed a database named {open_quotes}GEOBASE{close_quotes} and a pre/post-processor named {open_quotes}GEOGRAPH{close_quotes} for TOUGH/TOUGH2 on engineering work station (EWS). {open_quotes}GEOGRAPH{close_quotes} is based on the ORACLE{sup *1} relational database manager system to access data sets of surface exploration (geology, geophysics, geochemistry, etc.), drilling (well trajectory, geological column, logging, etc.), well testing (production test, injection test, interference test, tracer test, etc.) and production/injection history.{open_quotes}GEOGRAPH{close_quotes} consists of {open_quotes}Pre-processor{close_quotes} that can construct the three-dimensional free shape reservoir modeling by mouse operation on X-window and {open_quotes}Post-processor{close_quotes} that can display several kinds of two/three-dimensional maps and X-Y plots to compile data on {open_quotes}GEOBASE{close_quotes} and result of TOUGH/TOUGH2 calculation. This paper shows concept of the systems and examples of utilization.

  2. Optical device terahertz integration in a two-dimensional-three-dimensional heterostructure.

    Science.gov (United States)

    Feng, Zhifang; Lin, Jie; Feng, Shuai

    2018-01-10

    The transmission properties of an off-planar integrated circuit including two wavelength division demultiplexers are designed, simulated, and analyzed in detail by the finite-difference time-domain method. The results show that the wavelength selection for different ports (0.404[c/a] at B 2 port, 0.389[c/a] at B 3 port, and 0.394[c/a] at B 4 port) can be realized by adjusting the parameters. It is especially important that the off-planar integration between two complex devices is also realized. These simulated results give valuable promotions in the all-optical integrated circuit, especially in compact integration.

  3. All-fiber hybrid photon-plasmon circuits: integrating nanowire plasmonics with fiber optics.

    Science.gov (United States)

    Li, Xiyuan; Li, Wei; Guo, Xin; Lou, Jingyi; Tong, Limin

    2013-07-01

    We demonstrate all-fiber hybrid photon-plasmon circuits by integrating Ag nanowires with optical fibers. Relying on near-field coupling, we realize a photon-to-plasmon conversion efficiency up to 92% in a fiber-based nanowire plasmonic probe. Around optical communication band, we assemble an all-fiber resonator and a Mach-Zehnder interferometer (MZI) with Q-factor of 6 × 10(6) and extinction ratio up to 30 dB, respectively. Using the MZI, we demonstrate fiber-compatible plasmonic sensing with high sensitivity and low optical power.

  4. Integrated design course of applied optics focusing on operating and maintaining abilities

    Science.gov (United States)

    Xu, Zhongjie; Ning, Yu; Jiang, Tian; Cheng, Xiangai

    2017-08-01

    The abilities of operating and maintaining optical instruments are crucial in modern society. Besides the basic knowledge in optics, the optics courses in the National University of Defense Technology also focus on the training on handling typical optical equipment. As the link between classroom courses on applied optics and the field trips, the integrated design course of applied optics aims to give the students a better understanding on several instantly used optical equipment, such as hand-held telescope and periscope, etc. The basic concepts of optical system design are also emphasized as well. The course is arranged rightly after the classroom course of applied optics and composed of experimental and design tasks. The experimental tasks include the measurements of aberrations and major parameters of a primitive telescope, while in the design parts, the students are asked to design a Keplerian telescope. The whole course gives a deepened understandings on the concepts, assembling, and operating of telescopes. The students are also encouraged to extend their interests on other typical optical instruments.

  5. A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits.

    Science.gov (United States)

    Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

    2017-12-01

    One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe 2 , a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  6. A MoTe2-based light-emitting diode and photodetector for silicon photonic integrated circuits

    Science.gov (United States)

    Bie, Ya-Qing; Grosso, Gabriele; Heuck, Mikkel; Furchi, Marco M.; Cao, Yuan; Zheng, Jiabao; Bunandar, Darius; Navarro-Moratalla, Efren; Zhou, Lin; Efetov, Dmitri K.; Taniguchi, Takashi; Watanabe, Kenji; Kong, Jing; Englund, Dirk; Jarillo-Herrero, Pablo

    2017-12-01

    One of the current challenges in photonics is developing high-speed, power-efficient, chip-integrated optical communications devices to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, in part because of the promise that many components, such as waveguides, couplers, interferometers and modulators, could be directly integrated on silicon-based processors. However, light sources and photodetectors present ongoing challenges. Common approaches for light sources include one or few off-chip or wafer-bonded lasers based on III-V materials, but recent system architecture studies show advantages for the use of many directly modulated light sources positioned at the transmitter location. The most advanced photodetectors in the silicon photonic process are based on germanium, but this requires additional germanium growth, which increases the system cost. The emerging two-dimensional transition-metal dichalcogenides (TMDs) offer a path for optical interconnect components that can be integrated with silicon photonics and complementary metal-oxide-semiconductors (CMOS) processing by back-end-of-the-line steps. Here, we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with an infrared bandgap. This state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  7. Cylindrical integrated optical microresonators: modeling by 3-D vectorial coupled mode theory

    Czech Academy of Sciences Publication Activity Database

    Stoffer, R.; Hiremath, K. R.; Hammer, M.; Prkna, Ladislav; Čtyroký, Jiří

    2005-01-01

    Roč. 256, 1/3 (2005), s. 46-67 ISSN 0030-4018 R&D Projects: GA ČR(CZ) GA102/05/0987 Grant - others:European Commission(XE) IST-2000-28018 NAIS Institutional research plan: CEZ:AV0Z20670512 Keywords : integrated optics * optical waveguide theory * modelling Subject RIV: JA - Electronics ; Optoelectronics, Electrical Engineering Impact factor: 1.456, year: 2005

  8. ATLAS Level-1 Calorimeter Trigger Subsystem Tests of a Prototype Cluster Processor Module

    CERN Document Server

    Garvey, J; Apostologlou, P; Ay, C; Barnett, B M; Bauss, B; Brawn, I P; Bohm, C; Dahlhoff, A; Davis, A O; Edwards, J; Eisenhandler, E F; Gee, C N P; Gillman, A R; Hanke, P; Hellman, S; Hidévgi, A; Hillier, S J; Jakobs, K; Kluge, E E; Landon, M; Mahboubi, K; Mahout, G; Meier, K; Meshkov, P; Moye, T H; Mills, D; Moyse, E; Nix, O; Penno, K; Perera, V J O; Qian, W; Schmitt, K; Schäfer, U; Silverstein, S; Staley, R J; Thomas, J; Trefzger, T M; Watkins, P M; Watson, A; 9th Workshop On Electronics For LHC Experiments - LECC 2003

    2003-01-01

    The Level-1 Calorimeter Trigger consists of a Preprocessor (PP), a Cluster Processor (CP), and a Jet/Energy-sum Processor (JEP). The CP and JEP receive digitised trigger-tower data from the Preprocessor and produce trigger multiplicity and Region-of-Interest (RoI) information. The trigger will also provide intermediate results to the data acquisition (DAQ) system for monitoring and diagnostic purposes by using Readout Driver (ROD) Modules. The CP Modules (CPM) are designed to find isolated electron/photon and hadron/tau clusters in overlapping windows of trigger towers. Each pipelined CPM processes 8-bit data from a total of 128 trigger towers at each LHC crossing. Four full-specification prototypes of CPMs have been built and results of complete tests on individual boards will be presented. These modules were then integrated with other modules to build an ATLAS Level-1 Calorimeter Trigger subsystem test bench. Realtime data were exchanged between modules, and time-slice readout data were tagged and transferr...

  9. Solitonic guide and multiphoton absorption processes in photopolymerizable materials for optical integrated circuits

    Science.gov (United States)

    Klein, Stephane; Barsella, Alberto; Acker, D.; Sutter, C.; Beyer, N.; Andraud, Chantal; Fort, Alain F.; Dorkenoo, Kokou D.

    2004-09-01

    Up to now, most of the optical integrated devices are realized on glass or III-V substrates and the waveguides are usually obtained by photolithography techniques. We present here a new approach based on the use of photopolymerizable compounds. The conditions of self-written channel creation by solitonic propagation inside the bulk of these photopolymerizable formulations are analyzed. Both experimental and theoretical results of the various stages of self-written guide propagation are presented. A further step has been achieved by using a two-photon absorption process for the polymerization via a confocal microscopy technique. Combined with the solitonic guide creation, this technique allows to draw 3D optical circuits. Finally, by doping the photopolymerizable mixtures with push-pull chromophores having a controlled orientation, it will be possible to create active optical integrated devices.

  10. Integrated optic vector-matrix multiplier

    Science.gov (United States)

    Watts, Michael R [Albuquerque, NM

    2011-09-27

    A vector-matrix multiplier is disclosed which uses N different wavelengths of light that are modulated with amplitudes representing elements of an N.times.1 vector and combined to form an input wavelength-division multiplexed (WDM) light stream. The input WDM light stream is split into N streamlets from which each wavelength of the light is individually coupled out and modulated for a second time using an input signal representing elements of an M.times.N matrix, and is then coupled into an output waveguide for each streamlet to form an output WDM light stream which is detected to generate a product of the vector and matrix. The vector-matrix multiplier can be formed as an integrated optical circuit using either waveguide amplitude modulators or ring resonator amplitude modulators.

  11. Biomass is beginning to threaten the wood-processors

    International Nuclear Information System (INIS)

    Beer, G.; Sobinkovic, B.

    2004-01-01

    In this issue an exploitation of biomass in Slovak Republic is analysed. Some new projects of constructing of the stoke-holds for biomass processing are published. The grants for biomass are ascending the prices of wood raw material, which is thus becoming less accessible for the wood-processors. An excessive wood export threatens the domestic processors

  12. An Exact Line Integral Representation of the Magnetic Physical Optics Scattered Field

    DEFF Research Database (Denmark)

    Meincke, Peter; Breinbjerg, Olav; Jørgensen, Erik

    2003-01-01

    An exact line integral representation is derived for the magnetic physical optics field scattered by a perfectly electrically conducting planar plate illuminated by electric or magnetic Hertzian dipoles. The positions of source and observation points can be almost arbitrary. Numerical examples...... are presented to illustrate the exactness of the line integral representation....

  13. Reconfigurable signal processor designs for advanced digital array radar systems

    Science.gov (United States)

    Suarez, Hernan; Zhang, Yan (Rockee); Yu, Xining

    2017-05-01

    The new challenges originated from Digital Array Radar (DAR) demands a new generation of reconfigurable backend processor in the system. The new FPGA devices can support much higher speed, more bandwidth and processing capabilities for the need of digital Line Replaceable Unit (LRU). This study focuses on using the latest Altera and Xilinx devices in an adaptive beamforming processor. The field reprogrammable RF devices from Analog Devices are used as analog front end transceivers. Different from other existing Software-Defined Radio transceivers on the market, this processor is designed for distributed adaptive beamforming in a networked environment. The following aspects of the novel radar processor will be presented: (1) A new system-on-chip architecture based on Altera's devices and adaptive processing module, especially for the adaptive beamforming and pulse compression, will be introduced, (2) Successful implementation of generation 2 serial RapidIO data links on FPGA, which supports VITA-49 radio packet format for large distributed DAR processing. (3) Demonstration of the feasibility and capabilities of the processor in a Micro-TCA based, SRIO switching backplane to support multichannel beamforming in real-time. (4) Application of this processor in ongoing radar system development projects, including OU's dual-polarized digital array radar, the planned new cylindrical array radars, and future airborne radars.

  14. Parallel processor for fast event analysis

    International Nuclear Information System (INIS)

    Hensley, D.C.

    1983-01-01

    Current maximum data rates from the Spin Spectrometer of approx. 5000 events/s (up to 1.3 MBytes/s) and minimum analysis requiring at least 3000 operations/event require a CPU cycle time near 70 ns. In order to achieve an effective cycle time of 70 ns, a parallel processing device is proposed where up to 4 independent processors will be implemented in parallel. The individual processors are designed around the Am2910 Microsequencer, the AM29116 μP, and the Am29517 Multiplier. Satellite histogramming in a mass memory system will be managed by a commercial 16-bit μP system

  15. Optical computer utilization at the Superconducting Super Collider

    International Nuclear Information System (INIS)

    Johnson, M.B.; Woosley, J.K.; Fennelly, A.J.

    1990-01-01

    Optical computer systems offer the possibility of extremely high-speed, high efficiency processing for the SSC. The state of the art in optical computer system is described, with emphasis on the problems of timing, digitization, data readout, and storage. Particular emphasis is placed on the potential of utilizing detector optical signal readouts as a real-time trigger in a signal-rich environment (two to ten events per 16ns bunch crossing). A comparison of projected optical computer technology growth during the next decade and the capabilities required of SSC detectors and off-line processors is performed

  16. Asymmetrical floating point array processors, their application to exploration and exploitation

    Energy Technology Data Exchange (ETDEWEB)

    Geriepy, B L

    1983-01-01

    An asymmetrical floating point array processor is a special-purpose scientific computer which operates under asymmetrical control of a host computer. Although an array processor can receive fixed point input and produce fixed point output, its primary mode of operation is floating point. The first generation of array processors was oriented towards time series information. The next generation of array processors has proved much more versatile and their applicability ranges from petroleum reservoir simulation to speech syntheses. Array processors are becoming commonplace in mining, the primary usage being construction of grids-by usual methods or by kriging. The Australian mining community is among the world's leaders in regard to computer-assisted exploration and exploitation systems. Part of this leadership role must be providing guidance to computer vendors in regard to current and future requirements.

  17. Integration of Curved D-Type Optical Fiber Sensor with Microfluidic Chip.

    Science.gov (United States)

    Sun, Yung-Shin; Li, Chang-Jyun; Hsu, Jin-Cherng

    2016-12-30

    A curved D-type optical fiber sensor (OFS) combined with a microfluidic chip is proposed. This OFS, based on surface plasmon resonance (SPR) of the Kretchmann's configuration, is applied as a biosensor to measure the concentrations of different bio-liquids such as ethanol, methanol, and glucose solutions. The SPR phenomenon is attained by using the optical fiber to guide the light source to reach the side-polished, gold-coated region. Integrating this OFS with a polymethylmethacrylate (PMMA)-based microfluidic chip, the SPR spectra for liquids with different refractive indices are recorded. Experimentally, the sensitivity of the current biosensor was calculated to be in the order of 10 -5 RIU. This microfluidic chip-integrated OFS could be valuable for monitoring subtle changes in biological samples such as blood sugar, allergen, and biomolecular interactions.

  18. On the effective parallel programming of multi-core processors

    NARCIS (Netherlands)

    Varbanescu, A.L.

    2010-01-01

    Multi-core processors are considered now the only feasible alternative to the large single-core processors which have become limited by technological aspects such as power consumption and heat dissipation. However, due to their inherent parallel structure and their diversity, multi-cores are

  19. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, N.; Baird, S.A.; Biddulph, P.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no deadtime. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (author)

  20. The UA1 upgrade calorimeter trigger processor

    International Nuclear Information System (INIS)

    Bains, M.; Charleton, D.; Ellis, N.; Garvey, J.; Gregory, J.; Jimack, M.P.; Jovanovic, P.; Kenyon, I.R.; Baird, S.A.; Campbell, D.; Cawthraw, M.; Coughlan, J.; Flynn, P.; Galagedera, S.; Grayer, G.; Halsall, R.; Shah, T.P.; Stephens, R.; Biddulph, P.; Eisenhandler, E.; Fensome, I.F.; Landon, M.; Robinson, D.; Oliver, J.; Sumorok, K.

    1990-01-01

    The increased luminosity of the improved CERN Collider and the more subtle signals of second-generation collider physics demand increasingly sophisticated triggering. We have built a new first-level trigger processor designed to use the excellent granularity of the UA1 upgrade calorimeter. This device is entirely digital and handles events in 1.5 μs, thus introducing no dead time. Its most novel feature is fast two-dimensional electromagnetic cluster-finding with the possibility of demanding an isolated shower of limited penetration. The processor allows multiple combinations of triggers on electromagnetic showers, hadronic jets and energy sums, including a total-energy veto of multiple interactions and a full vector sum of missing transverse energy. This hard-wired processor is about five times more powerful than its predecessor, and makes extensive use of pipelining techniques. It was used extensively in the 1988 and 1989 runs of the CERN Collider. (orig.)

  1. Monolithic integration of optical waveguides for absorbance detection in microfabricated electrophoresis devices

    DEFF Research Database (Denmark)

    Mogensen, Klaus Bo; Petersen, Nickolaj Jacob; Hübner, Jörg

    2001-01-01

    . The waveguides on the device were connected to optical fibers, which enabled alignment free operation due to the absence of free-space optics. A 750 mum long U-shaped detection cell was used to facilitate longitudinal absorption detection. To minimize geometrically induced band broadening at the turn in the U......The fabrication and performance of an electrophoretic separation chip with integrated of optical waveguides for absorption detection is presented. The device was fabricated on a silicon substrate by standard microfabrication techniques with the use of two photolithographic mask steps...

  2. A full-duplex working integrated optoelectronic device for optical interconnect

    Science.gov (United States)

    Liu, Kai; Fan, Huize; Huang, Yongqing; Duan, Xiaofeng; Wang, Qi; Ren, Xiaomin; Wei, Qi; Cai, Shiwei

    2018-05-01

    In this paper, a full-duplex working integrated optoelectronic device is proposed. It is constructed by integrating a vertical cavity surface emitting laser (VCSEL) unit above a resonant cavity enhanced photodetector (RCE-PD) unit. Analysis shows that, the VCSEL unit has a threshold current of 1 mA and a slop efficiency of 0.66 W/A at 849.7 nm, the RCE-PD unit obtains its maximal absorption quantum efficiency of 90.24% at 811 nm with a FWHM of 4 nm. Moreover, the two units of the proposed integrated device can work independently from each other. So that the proposed integrated optoelectronic device can work full-duplex. It can be applied for single fiber bidirectional optical interconnects system.

  3. Benchmarking NWP Kernels on Multi- and Many-core Processors

    Science.gov (United States)

    Michalakes, J.; Vachharajani, M.

    2008-12-01

    Increased computing power for weather, climate, and atmospheric science has provided direct benefits for defense, agriculture, the economy, the environment, and public welfare and convenience. Today, very large clusters with many thousands of processors are allowing scientists to move forward with simulations of unprecedented size. But time-critical applications such as real-time forecasting or climate prediction need strong scaling: faster nodes and processors, not more of them. Moreover, the need for good cost- performance has never been greater, both in terms of performance per watt and per dollar. For these reasons, the new generations of multi- and many-core processors being mass produced for commercial IT and "graphical computing" (video games) are being scrutinized for their ability to exploit the abundant fine- grain parallelism in atmospheric models. We present results of our work to date identifying key computational kernels within the dynamics and physics of a large community NWP model, the Weather Research and Forecast (WRF) model. We benchmark and optimize these kernels on several different multi- and many-core processors. The goals are to (1) characterize and model performance of the kernels in terms of computational intensity, data parallelism, memory bandwidth pressure, memory footprint, etc. (2) enumerate and classify effective strategies for coding and optimizing for these new processors, (3) assess difficulties and opportunities for tool or higher-level language support, and (4) establish a continuing set of kernel benchmarks that can be used to measure and compare effectiveness of current and future designs of multi- and many-core processors for weather and climate applications.

  4. Novel microwave photonic fractional Hilbert transformer using a ring resonator-based optical all-pass filter.

    Science.gov (United States)

    Zhuang, Leimeng; Khan, Muhammad Rezaul; Beeker, Willem; Leinse, Arne; Heideman, René; Roeloffzen, Chris

    2012-11-19

    We propose and demonstrate a novel wideband microwave photonic fractional Hilbert transformer implemented using a ring resonator-based optical all-pass filter. The full programmability of the ring resonator allows variable and arbitrary fractional order of the Hilbert transformer. The performance analysis in both frequency and time domain validates that the proposed implementation provides a good approximation to an ideal fractional Hilbert transformer. This is also experimentally verified by an electrical S21 response characterization performed on a waveguide realization of a ring resonator. The waveguide-based structure allows the proposed Hilbert transformer to be integrated together with other building blocks on a photonic integrated circuit to create various system-level functionalities for on-chip microwave photonic signal processors. As an example, a circuit consisting of a splitter and a ring resonator has been realized which can perform on-chip phase control of microwave signals generated by means of optical heterodyning, and simultaneous generation of in-phase and quadrature microwave signals for a wide frequency range. For these functionalities, this simple and on-chip solution is considered to be practical, particularly when operating together with a dual-frequency laser. To our best knowledge, this is the first-time on-chip demonstration where ring resonators are employed to perform phase control functionalities for optical generation of microwave signals by means of optical heterodyning.

  5. Processors for wavelet analysis and synthesis: NIFS and TI-C80 MVP

    Science.gov (United States)

    Brooks, Geoffrey W.

    1996-03-01

    Two processors are considered for image quadrature mirror filtering (QMF). The neuromorphic infrared focal-plane sensor (NIFS) is an existing prototype analog processor offering high speed spatio-temporal Gaussian filtering, which could be used for the QMF low- pass function, and difference of Gaussian filtering, which could be used for the QMF high- pass function. Although not designed specifically for wavelet analysis, the biologically- inspired system accomplishes the most computationally intensive part of QMF processing. The Texas Instruments (TI) TMS320C80 Multimedia Video Processor (MVP) is a 32-bit RISC master processor with four advanced digital signal processors (DSPs) on a single chip. Algorithm partitioning, memory management and other issues are considered for optimal performance. This paper presents these considerations with simulated results leading to processor implementation of high-speed QMF analysis and synthesis.

  6. Optical microwave filter based on spectral slicing by use of arrayed waveguide gratings.

    Science.gov (United States)

    Pastor, Daniel; Ortega, Beatriz; Capmany, José; Sales, Salvador; Martinez, Alfonso; Muñoz, Pascual

    2003-10-01

    We have experimentally demonstrated a new optical signal processor based on the use of arrayed waveguide gratings. The structure exploits the concept of spectral slicing combined with the use of an optical dispersive medium. The approach presents increased flexibility from previous slicing-based structures in terms of tunability, reconfiguration, and apodization of the samples or coefficients of the transversal optical filter.

  7. ACP/R3000 processors in data acquisition systems

    International Nuclear Information System (INIS)

    Deppe, J.; Areti, H.; Atac, R.

    1989-02-01

    We describe ACP/R3000 processor based data acquisition systems for high energy physics. This VME bus compatible processor board, with a computational power equivalent to 15 VAX 11/780s or better, contains 8 Mb of memory for event buffering and has a high speed secondary bus that allows data gathering from front end electronics. 2 refs., 3 figs

  8. GA103: A microprogrammable processor for online filtering

    International Nuclear Information System (INIS)

    Calzas, A.; Danon, G.; Bouquet, B.

    1981-01-01

    GA 103 is a 16 bit microprogrammable processor which emulates the PDP 11 instruction set. It is based on the Am 2900 slices. It allows user-implemented microinstructions and addition of hardwired processors. It will perform on-line filtering tasks in the NA 14 experiment at CERN, based on the reconstruction of transverse momentum of photons detected in a lead glass calorimeter. (orig.)

  9. Integrated optical circuit engineering V; Proceedings of the Meeting, San Diego, CA, Aug. 17-20, 1987

    Science.gov (United States)

    Mentzer, Mark A.

    Recent advances in the theoretical and practical design and applications of optoelectronic devices and optical circuits are examined in reviews and reports. Topics discussed include system and market considerations, guided-wave phenomena, waveguide devices, processing technology, lithium niobate devices, and coupling problems. Consideration is given to testing and measurement, integrated optics for fiber-optic systems, optical interconnect technology, and optical computing.

  10. Real-time trajectory optimization on parallel processors

    Science.gov (United States)

    Psiaki, Mark L.

    1993-01-01

    A parallel algorithm has been developed for rapidly solving trajectory optimization problems. The goal of the work has been to develop an algorithm that is suitable to do real-time, on-line optimal guidance through repeated solution of a trajectory optimization problem. The algorithm has been developed on an INTEL iPSC/860 message passing parallel processor. It uses a zero-order-hold discretization of a continuous-time problem and solves the resulting nonlinear programming problem using a custom-designed augmented Lagrangian nonlinear programming algorithm. The algorithm achieves parallelism of function, derivative, and search direction calculations through the principle of domain decomposition applied along the time axis. It has been encoded and tested on 3 example problems, the Goddard problem, the acceleration-limited, planar minimum-time to the origin problem, and a National Aerospace Plane minimum-fuel ascent guidance problem. Execution times as fast as 118 sec of wall clock time have been achieved for a 128-stage Goddard problem solved on 32 processors. A 32-stage minimum-time problem has been solved in 151 sec on 32 processors. A 32-stage National Aerospace Plane problem required 2 hours when solved on 32 processors. A speed-up factor of 7.2 has been achieved by using 32-nodes instead of 1-node to solve a 64-stage Goddard problem.

  11. The ATLAS Level-1 Central Trigger Processor (CTP)

    CERN Document Server

    Spiwoks, Ralf; Ellis, Nick; Farthouat, P; Gällnö, P; Haller, J; Krasznahorkay, A; Maeno, T; Pauly, T; Pessoa-Lima, H; Resurreccion-Arcas, I; Schuler, G; De Seixas, J M; Torga-Teixeira, R; Wengler, T

    2005-01-01

    The ATLAS Level-1 Central Trigger Processor (CTP) combines information from calorimeter and muon trigger processors and makes the final Level-1 Accept (L1A) decision on the basis of lists of selection criteria (trigger menus). In addition to the event-selection decision, the CTP also provides trigger summary information to the Level-2 trigger and the data acquisition system. It further provides accumulated and bunch-by-bunch scaler data for monitoring of the trigger, detector and beam conditions. The CTP is presented and results are shown from tests with the calorimeter adn muon trigger processors connected to detectors in a particle beam, as well as from stand-alone full-system tests in the laboratory which were used to validate the CTP.

  12. A Processor-Sharing Scheduling Strategy for NFV Nodes

    Directory of Open Access Journals (Sweden)

    Giuseppe Faraci

    2016-01-01

    Full Text Available The introduction of the two paradigms SDN and NFV to “softwarize” the current Internet is making management and resource allocation two key challenges in the evolution towards the Future Internet. In this context, this paper proposes Network-Aware Round Robin (NARR, a processor-sharing strategy, to reduce delays in traversing SDN/NFV nodes. The application of NARR alleviates the job of the Orchestrator by automatically working at the intranode level, dynamically assigning the processor slices to the virtual network functions (VNFs according to the state of the queues associated with the output links of the network interface cards (NICs. An extensive simulation set is presented to show the improvements achieved with respect to two more processor-sharing strategies chosen as reference.

  13. Numeric processor and text manipulator for the ''MASTER CONTROL'' data-base-management system

    International Nuclear Information System (INIS)

    Kuhn, R.W.

    1976-01-01

    The numeric and text processor of the MASTER CONTROL (MCP) data-base-management system permits the user to define fields and arrays that are functionally dependent on the data retained in a data base. This allows the storage of only the essential and unique information and data, and the calculation of derivable quantities as required. The derived quantity can be expressed as an arithmetic expression, that is, a functional relationship. Functions can be multiply subscripted and can be embedded within other functions at up to 58 levels. They can be stored either semi-permanently in a repertoire of functional relations, or they can be defined interactively from a terminal and used immediately for searching on the derived value. The processor also permits the conversion of literal strings into numbers, and vice versa. In addition, the user can define dictionaries that allow the expansion of keyed sentinels associated with records in the data base into fully descriptive expressions. This option can be used for cost-effective searching and data compaction. The functional definitions are reduced to Polish notation and stored in a disk file from which they are either retrieved on demand and evaluated according to the data of records specified or used in any given MASTER CONTROL command. The language used for the definitions of the numeric processor is essentially FORTRAN; most of the standard functions and over two dozen special functions are thus available. The functional processor provides a powerful technique for the integration of text and data for energy research and for scientific and technological work in general. MASTER CONTROL is operational at the Lawrence Livermore Laboratory (LLL) and at the Los Alamos Scientific Laboratory (LASL). 6 figures, 1 table

  14. Processor farming method for multi-scale analysis of masonry structures

    Science.gov (United States)

    Krejčí, Tomáš; Koudelka, Tomáš

    2017-07-01

    This paper describes a processor farming method for a coupled heat and moisture transport in masonry using a two-level approach. The motivation for the two-level description comes from difficulties connected with masonry structures, where the size of stone blocks is much larger than the size of mortar layers and very fine finite element mesh has to be used. The two-level approach is suitable for parallel computing because nearly all computations can be performed independently with little synchronization. This approach is called processor farming. The master processor is dealing with the macro-scale level - the structure and the slave processors are dealing with a homogenization procedure on the meso-scale level which is represented by an appropriate representative volume element.

  15. [Improving speech comprehension using a new cochlear implant speech processor].

    Science.gov (United States)

    Müller-Deile, J; Kortmann, T; Hoppe, U; Hessel, H; Morsnowski, A

    2009-06-01

    The aim of this multicenter clinical field study was to assess the benefits of the new Freedom 24 sound processor for cochlear implant (CI) users implanted with the Nucleus 24 cochlear implant system. The study included 48 postlingually profoundly deaf experienced CI users who demonstrated speech comprehension performance with their current speech processor on the Oldenburg sentence test (OLSA) in quiet conditions of at least 80% correct scores and who were able to perform adaptive speech threshold testing using the OLSA in noisy conditions. Following baseline measures of speech comprehension performance with their current speech processor, subjects were upgraded to the Freedom 24 speech processor. After a take-home trial period of at least 2 weeks, subject performance was evaluated by measuring the speech reception threshold with the Freiburg multisyllabic word test and speech intelligibility with the Freiburg monosyllabic word test at 50 dB and 70 dB in the sound field. The results demonstrated highly significant benefits for speech comprehension with the new speech processor. Significant benefits for speech comprehension were also demonstrated with the new speech processor when tested in competing background noise.In contrast, use of the Abbreviated Profile of Hearing Aid Benefit (APHAB) did not prove to be a suitably sensitive assessment tool for comparative subjective self-assessment of hearing benefits with each processor. Use of the preprocessing algorithm known as adaptive dynamic range optimization (ADRO) in the Freedom 24 led to additional improvements over the standard upgrade map for speech comprehension in quiet and showed equivalent performance in noise. Through use of the preprocessing beam-forming algorithm BEAM, subjects demonstrated a highly significant improved signal-to-noise ratio for speech comprehension thresholds (i.e., signal-to-noise ratio for 50% speech comprehension scores) when tested with an adaptive procedure using the Oldenburg

  16. Evaluation of the optical conductivity tensor in terms of contour integrations

    OpenAIRE

    Szunyogh, Laszlo; Weinberger, Peter

    2000-01-01

    For the case of finite life-time broadening the standard Kubo-formula for the optical conductivity tensor is rederived in terms of Green's functions by using contour integrations, whereby finite temperatures are accounted for by using the Fermi-Dirac distribution function. For zero life-time broadening, the present formalism is related to expressions well-known in the literature. Numerical aspects of how to calculate the corresponding contour integrals are also outlined.

  17. Hardware processor for tracking particles in an alternating-gradient synchrotron

    International Nuclear Information System (INIS)

    Johnson, M.; Avilez, C.

    1987-01-01

    We discuss the design and performance of special-purpose processors for tracking particles through an alternating-gradient synchrotron. We present block diagram designs for two hardware processors. Both processors use algorithms based on the 'kick' approximation, i.e., transport matrices are used for dipoles and quadrupoles, and the thin-lens approximation is used for all higher multipoles. The faster processor makes extensive use of memory look-up tables for evaluating functions. For the case of magnets with multipoles up to pole 30 and using one kick per magnet, this processor can track 19 particles through an accelerator at a rate that is only 220 times slower than the time it takes real particles to travel around the machine. For a model consisting of only thin lenses, it is only 150 times slower than real particles. An additional factor of 2 can be obtained with chips now becoming available. The number of magnets in the accelerator is limited only by the amount of memory available for storing magnet parameters. (author) 20 refs., 7 figs., 2 tabs

  18. Monolithic integration of DUV-induced waveguides into plastic microfluidic chip for optical manipulation

    DEFF Research Database (Denmark)

    Khoury Arvelo, Maria; Vannahme, Christoph; Sørensen, Kristian Tølbøl

    2014-01-01

    A monolithic polymer optofluidic chip for manipulation of microbeads in flow is demonstrated. On this chip, polymer waveguides induced by Deep UV lithography are integrated with microfluidic channels. The optical propagation losses of the waveguides are measured to be 0.66±0.13 dB/mm at a wavelen......A monolithic polymer optofluidic chip for manipulation of microbeads in flow is demonstrated. On this chip, polymer waveguides induced by Deep UV lithography are integrated with microfluidic channels. The optical propagation losses of the waveguides are measured to be 0.66±0.13 d......B/mm at a wavelength of λ = 808 nm. An optimized bead tracking algorithm is implemented, allowing for determination of the optical forces acting on the particles. The algorithm features a spatio-temporal mapping of coordinates for uniting partial trajectories, without increased processing time. With an external laser...

  19. Integrated optoelectronic materials and circuits for optical interconnects

    International Nuclear Information System (INIS)

    Hutcheson, L.D.

    1988-01-01

    Conventional interconnect and switching technology is rapidly becoming a critical issue in the realization of systems using high speed silicon and GaAs based technologies. In recent years clock speeds and on-chip density for VLSI/VHSIC technology has made packaging these high speed chips extremely difficult. A strong case can be made for using optical interconnects for on-chip/on-wafer, chip-to-chip and board-to-board high speed communications. GaAs integrated optoelectronic circuits (IOC's) are being developed in a number of laboratories for performing Input/Output functions at all levels. In this paper integrated optoelectronic materials, electronics and optoelectronic devices are presented. IOC's are examined from the standpoint of what it takes to fabricate the devices and what performance can be expected

  20. Manufacturing a Micro-model with Integrated Fibre Optic Pressure Sensors

    NARCIS (Netherlands)

    Zarikos, I.; Hassanizadeh, S.M.; van Oosterhout, L.M.; van Oordt, Wim

    The measurement of fluid pressure inside pores is a major challenge in experimental studies of two-phase flow in porous media. In this paper, we describe the manufacturing procedure of a micro-model with integrated fibre optic pressure sensors. They have a circular measurement window with a diameter

  1. Multibus-based parallel processor for simulation

    Science.gov (United States)

    Ogrady, E. P.; Wang, C.-H.

    1983-01-01

    A Multibus-based parallel processor simulation system is described. The system is intended to serve as a vehicle for gaining hands-on experience, testing system and application software, and evaluating parallel processor performance during development of a larger system based on the horizontal/vertical-bus interprocessor communication mechanism. The prototype system consists of up to seven Intel iSBC 86/12A single-board computers which serve as processing elements, a multiple transmission controller (MTC) designed to support system operation, and an Intel Model 225 Microcomputer Development System which serves as the user interface and input/output processor. All components are interconnected by a Multibus/IEEE 796 bus. An important characteristic of the system is that it provides a mechanism for a processing element to broadcast data to other selected processing elements. This parallel transfer capability is provided through the design of the MTC and a minor modification to the iSBC 86/12A board. The operation of the MTC, the basic hardware-level operation of the system, and pertinent details about the iSBC 86/12A and the Multibus are described.

  2. Monitoring the performance of off-site processors

    International Nuclear Information System (INIS)

    Miller, C.C.

    1995-01-01

    Commercial nuclear power plants have been able to utilize the latest technologies and achieve large volume reduction by obtaining off-site waste processor services. Although the use of such services reduce the burden of waste processing it also reduces the utility's control over the process. Monitoring the performance of off-site processors is important so that the utility is cognizant of the waste disposition for required regulatory reporting. In addition to obtaining data for Reg Guide 1.21 reporting, Performance monitoring is important to determine which vendor and which services to utilize. Off-site processor services were initially offered for the decontamination of metallic waste. Since that time the list of services has expanded to include supercompaction, survey for release, incineration and metal melting. The number of vendors offering off-site services has increased and the services they offer vary. processing rates vary between vendors and have different charge bases. Determining which vendor to use for what service can be complicated and confusing

  3. Digital Signal Processor System for AC Power Drivers

    Directory of Open Access Journals (Sweden)

    Ovidiu Neamtu

    2009-10-01

    Full Text Available DSP (Digital Signal Processor is the bestsolution for motor control systems to make possible thedevelopment of advanced motor drive systems. The motorcontrol processor calculates the required motor windingvoltage magnitude and frequency to operate the motor atthe desired speed. A PWM (Pulse Width Modulationcircuit controls the on and off duty cycle of the powerinverter switches to vary the magnitude of the motorvoltages.

  4. Stechiometric neodymium compounds as new materials for light sources in integrated optics

    International Nuclear Information System (INIS)

    Malinowski, M.

    1981-01-01

    Short review of physico-chemical properties of stechiometric neodymium compounds has been presented. Several constructions of minilasers as promising light sources for integrated optics devices have been described. (author)

  5. Integration of Curved D-Type Optical Fiber Sensor with Microfluidic Chip

    Directory of Open Access Journals (Sweden)

    Yung-Shin Sun

    2016-12-01

    Full Text Available A curved D-type optical fiber sensor (OFS combined with a microfluidic chip is proposed. This OFS, based on surface plasmon resonance (SPR of the Kretchmann’s configuration, is applied as a biosensor to measure the concentrations of different bio-liquids such as ethanol, methanol, and glucose solutions. The SPR phenomenon is attained by using the optical fiber to guide the light source to reach the side-polished, gold-coated region. Integrating this OFS with a polymethylmethacrylate (PMMA-based microfluidic chip, the SPR spectra for liquids with different refractive indices are recorded. Experimentally, the sensitivity of the current biosensor was calculated to be in the order of 10−5 RIU. This microfluidic chip-integrated OFS could be valuable for monitoring subtle changes in biological samples such as blood sugar, allergen, and biomolecular interactions.

  6. Early experience with the cochlear ESPrit ear-level speech processor in children.

    Science.gov (United States)

    Totten, C; Cope, Y; McCormick, B

    2000-12-01

    The ESPrit ear-level speech processor has recently become available in the United Kingdom for use with the Nucleus CI24M multichannel cochlear implant. We report on the use of this ear-level processor with 6 children, ages 8 to 15 years. In this study, all patients were initially fitted with the SPrint body-worn processor, this being a prerequisite for programming the ESPrit. Five of the children were fitted successfully with the ESPrit and are using their devices consistently. The results show that patient experience with the ESPrit has been favorable, although there have been some device and programming difficulties. Aided threshold measures show that the ESPrit processor performs at least as well as the SPrint processor, with a trend toward improved aided thresholds for the ESPrit processor compared with the SPrint processor. Further study of the functional benefit of both of these devices may confirm these potential gains. The ESPrit device currently has a disadvantage for children in that it does not support FM radio hearing aid use. Finally, caution is advised in the fitting of the ESPrit in very young children or inexperienced listeners, because of difficulties in monitoring device function.

  7. Survey of cochlear implant user satisfaction with the Neptune™ waterproof sound processor

    Directory of Open Access Journals (Sweden)

    Jeroen J. Briaire

    2016-04-01

    Full Text Available A multi-center self-assessment survey was conducted to evaluate patient satisfaction with the Advanced Bionics Neptune™ waterproof sound processor used with the AquaMic™ totally submersible microphone. Subjective satisfaction with the different Neptune™ wearing options, comfort, ease of use, sound quality and use of the processor in a range of active and water related situations were assessed for 23 adults and 73 children, using an online and paper based questionnaire. Upgraded subjects compared their previous processor to the Neptune™. The Neptune™ was most popular for use in general sports and in the pool. Subjects were satisfied with the sound quality of the sound processor outside and under water and following submersion. Seventyeight percent of subjects rated waterproofness as being very useful and 83% of the newly implanted subjects selected waterproofness as one of the reasons why they chose the Neptune™ processor. Providing a waterproof sound processor is considered by cochlear implant recipients to be useful and important and is a factor in their processor choice. Subjects reported that they were satisfied with the Neptune™ sound quality, ease of use and different wearing options.

  8. Distributed strain measurement with polymer optical fibers integrated into multifunctional geotextiles

    Science.gov (United States)

    Liehr, Sascha; Lenke, Philipp; Krebber, Katerina; Seeger, Monika; Thiele, Elke; Metschies, Heike; Gebreselassie, Berhane; Münich, Johannes Christian; Stempniewski, Lothar

    2008-04-01

    Fiber optic sensors based on polymer optical fibers (POF) have the advantage of being very elastic and robust at the same time. Unlike silica fibers, standard PMMA POF fibers can be strained to more than 40% while fully maintaining their light guiding properties. We investigated POF as a distributed strain sensor by analysing the backscatter increase at the strained section using the optical time domain reflectometry (OTDR) technique. This sensing ability together with its high robustness and break-down strain makes POF well-suited for integration into technical textiles for structural health monitoring purposes. Within the European research project POLYTECT (Polyfunctional textiles against natural hazards) technical textiles with integrated POF sensors, among others sensors are being developed for online structural health monitoring of geotechnical structures. Mechanical deformation in slopes, dams, dikes, embankments and retrofitted masonry structures is to be detected before critical damage occurs. In this paper we present the POF strain sensor properties, reactions to disturbing influences as temperature and bends as well as the results of the different model tests we conducted within POLYTECT. We further show the potential of perfluorinated graded-index POF for distributed strain sensing with increased spatial resolution and measurement lengths.

  9. A word processor optimized for preparing journal articles and student papers.

    Science.gov (United States)

    Wolach, A H; McHale, M A

    2001-11-01

    A new Windows-based word processor for preparing journal articles and student papers is described. In addition to standard features found in word processors, the present word processor provides specific help in preparing manuscripts. Clicking on "Reference Help (APA Form)" in the "File" menu provides a detailed help system for entering the references in a journal article. Clicking on "Examples and Explanations of APA Form" provides a help system with examples of the various sections of a review article, journal article that has one experiment, or journal article that has two or more experiments. The word processor can automatically place the manuscript page header and page number at the top of each page using the form required by APA and Psychonomic Society journals. The "APA Form" submenu of the "Help" menu provides detailed information about how the word processor is optimized for preparing articles and papers.

  10. Foundry fabricated photonic integrated circuit optical phase lock loop.

    Science.gov (United States)

    Bałakier, Katarzyna; Fice, Martyn J; Ponnampalam, Lalitha; Graham, Chris S; Wonfor, Adrian; Seeds, Alwyn J; Renaud, Cyril C

    2017-07-24

    This paper describes the first foundry-based InP photonic integrated circuit (PIC) designed to work within a heterodyne optical phase locked loop (OPLL). The PIC and an external electronic circuit were used to phase-lock a single-line semiconductor laser diode to an incoming reference laser, with tuneable frequency offset from 4 GHz to 12 GHz. The PIC contains 33 active and passive components monolithically integrated on a single chip, fully demonstrating the capability of a generic foundry PIC fabrication model. The electronic part of the OPLL consists of commercially available RF components. This semi-packaged system stabilizes the phase and frequency of the integrated laser so that an absolute frequency, high-purity heterodyne signal can be generated when the OPLL is in operation, with phase noise lower than -100 dBc/Hz at 10 kHz offset from the carrier. This is the lowest phase noise level ever demonstrated by monolithically integrated OPLLs.

  11. Extended performance electric propulsion power processor design study. Volume 2: Technical summary

    Science.gov (United States)

    Biess, J. J.; Inouye, L. Y.; Schoenfeld, A. D.

    1977-01-01

    Electric propulsion power processor technology has processed during the past decade to the point that it is considered ready for application. Several power processor design concepts were evaluated and compared. Emphasis was placed on a 30 cm ion thruster power processor with a beam power rating supply of 2.2KW to 10KW for the main propulsion power stage. Extension in power processor performance were defined and were designed in sufficient detail to determine efficiency, component weight, part count, reliability and thermal control. A detail design was performed on a microprocessor as the thyristor power processor controller. A reliability analysis was performed to evaluate the effect of the control electronics redesign. Preliminary electrical design, mechanical design and thermal analysis were performed on a 6KW power transformer for the beam supply. Bi-Mod mechanical, structural and thermal control configurations were evaluated for the power processor and preliminary estimates of mechanical weight were determined.

  12. First Results of an “Artificial Retina” Processor Prototype

    International Nuclear Information System (INIS)

    Cenci, Riccardo; Bedeschi, Franco; Marino, Pietro; Morello, Michael J.; Ninci, Daniele; Piucci, Alessio; Punzi, Giovanni; Ristori, Luciano; Spinella, Franco; Stracka, Simone; Tonelli, Diego; Walsh, John

    2016-01-01

    We report on the performance of a specialized processor capable of reconstructing charged particle tracks in a realistic LHC silicon tracker detector, at the same speed of the readout and with sub-microsecond latency. The processor is based on an innovative pattern-recognition algorithm, called “artificial retina algorithm”, inspired from the vision system of mammals. A prototype of the processor has been designed, simulated, and implemented on Tel62 boards equipped with high-bandwidth Altera Stratix III FPGA devices. The prototype is the first step towards a real-time track reconstruction device aimed at processing complex events of high-luminosity LHC experiments at 40 MHz crossing rate

  13. Optical and digital GaAs technologies for signal-processing applications; Proceedings of the Meeting, Orlando, FL, Apr. 16-18, 1990

    Science.gov (United States)

    Bendett, Mark P.; Butler, Daniel H., Jr.; Prabhakar, Arati; Yang, Andrew

    1990-10-01

    Practical problems that need to be solved for the introduction of optical modules into processing systems are reviewed. Some papers deal with the state of the art in such key devices as Bragg cells, spatial light modulators, and fast CCDs. Issues unique to optical packaging are also highlightened. New architectures to enable real-time operations are demonstrated, and optical interconnects for parallel processors are discussed. Particular attention is given to the status and operational advantages of government-sponsored efforts to upgrade existing military systems with digital GaAs signal processors and the state of the art in computer-aided design and advanced system architectures.

  14. Integrated optical waveguides and inertial focussing microfluidics in silica for microflow cytometry applications

    International Nuclear Information System (INIS)

    Butement, Jonathan T; Rowe, David J; Sessions, Neil P; Hua, Ping; Murugan, G Senthil; Wilkinson, James S; Clark, Owain; Chad, John E; Hunt, Hamish C

    2016-01-01

    A key challenge in the development of a microflow cytometry platform is the integration of the optical components with the fluidics as this requires compatible micro-optical and microfluidic technologies. In this work a microflow cytometry platform is presented comprising monolithically integrated waveguides and deep microfluidics in a rugged silica chip. Integrated waveguides are used to deliver excitation light to an etched microfluidic channel and also collect transmitted light. The fluidics are designed to employ inertial focussing, a particle positioning technique, to reduce signal variation by bringing the flowing particles onto the same plane as the excitation light beam. A fabrication process is described which exploits microelectronics mass production techniques including: sputtering, ICP etching and PECVD. Example devices were fabricated and the effectiveness of inertial focussing of 5.6 µ m fluorescent beads was studied showing lateral and vertical confinement of flowing beads within the microfluidic channel. The fluorescence signals from flowing calibration beads were quantified demonstrating a CV of 26%. Finally the potential of this type of device for measuring the variation in optical transmission from input to output waveguide as beads flowed through the beam was evaluated. (paper)

  15. Localization and Imaging of Integrated Circuit Defect Using Simple Optical Feedback Detection

    Directory of Open Access Journals (Sweden)

    Vernon Julius Cemine

    2004-12-01

    Full Text Available High-contrast microscopy of semiconductor and metal edifices in integrated circuits is demonstrated by combining laser-scanning confocal reflectance microscopy, one-photon optical-beam-induced current (1P-OBIC imaging, and optical feedback detection via a commercially available semiconductor laser that also serves as the excitation source. The confocal microscope has a compact in-line arrangement with no external photodetector. Confocal and 1P-OBIC images are obtained simultaneously from the same focused beam that is scanned across the sample plane. Image pairs are processed to generate exclusive high-contrast distributions of the semiconductor, metal, and dielectric sites in a GaAs photodiode array sample. The method is then utilized to demonstrate defect localization and imaging in an integrated circuit.

  16. Lipid Multilayer Grating Arrays Integrated by Nanointaglio for Vapor Sensing by an Optical Nose

    Directory of Open Access Journals (Sweden)

    Troy W. Lowry

    2015-08-01

    Full Text Available Lipid multilayer gratings are recently invented nanomechanical sensor elements that are capable of transducing molecular binding to fluid lipid multilayers into optical signals in a label free manner due to shape changes in the lipid nanostructures. Here, we show that nanointaglio is suitable for the integration of chemically different lipid multilayer gratings into a sensor array capable of distinguishing vapors by means of an optical nose. Sensor arrays composed of six different lipid formulations are integrated onto a surface and their optical response to three different vapors (water, ethanol and acetone in air as well as pH under water is monitored as a function of time. Principal component analysis of the array response results in distinct clustering indicating the suitability of the arrays for distinguishing these analytes. Importantly, the nanointaglio process used here is capable of producing lipid gratings out of different materials with sufficiently uniform heights for the fabrication of an optical nose.

  17. Lipid Multilayer Grating Arrays Integrated by Nanointaglio for Vapor Sensing by an Optical Nose

    Science.gov (United States)

    Lowry, Troy W.; Prommapan, Plengchart; Rainer, Quinn; Van Winkle, David; Lenhert, Steven

    2015-01-01

    Lipid multilayer gratings are recently invented nanomechanical sensor elements that are capable of transducing molecular binding to fluid lipid multilayers into optical signals in a label free manner due to shape changes in the lipid nanostructures. Here, we show that nanointaglio is suitable for the integration of chemically different lipid multilayer gratings into a sensor array capable of distinguishing vapors by means of an optical nose. Sensor arrays composed of six different lipid formulations are integrated onto a surface and their optical response to three different vapors (water, ethanol and acetone) in air as well as pH under water is monitored as a function of time. Principal component analysis of the array response results in distinct clustering indicating the suitability of the arrays for distinguishing these analytes. Importantly, the nanointaglio process used here is capable of producing lipid gratings out of different materials with sufficiently uniform heights for the fabrication of an optical nose. PMID:26308001

  18. Nonlinear Wave Simulation on the Xeon Phi Knights Landing Processor

    Science.gov (United States)

    Hristov, Ivan; Goranov, Goran; Hristova, Radoslava

    2018-02-01

    We consider an interesting from computational point of view standing wave simulation by solving coupled 2D perturbed Sine-Gordon equations. We make an OpenMP realization which explores both thread and SIMD levels of parallelism. We test the OpenMP program on two different energy equivalent Intel architectures: 2× Xeon E5-2695 v2 processors, (code-named "Ivy Bridge-EP") in the Hybrilit cluster, and Xeon Phi 7250 processor (code-named "Knights Landing" (KNL). The results show 2 times better performance on KNL processor.

  19. M7--a high speed digital processor for second level trigger selections

    International Nuclear Information System (INIS)

    Droege, T.F.; Gaines, I.; Turner, K.J.

    1978-01-01

    A digital processor is described which reconstructs mass and momentum as a second-level trigger selection. The processor is a five-address, microprogramed, pipelined, ECL machine with simultaneous memory access to four operands which load two parallel multipliers and an ALU. Source data modules are extensions of the processor

  20. Systematic calibration of an integrated x-ray and optical tomography system for preclinical radiation research

    Energy Technology Data Exchange (ETDEWEB)

    Yang, Yidong, E-mail: yidongyang@med.miami.edu [Department of Radiation Oncology and Molecular Radiation Sciences, Johns Hopkins University School of Medicine, Baltimore, Maryland 21231 and Department of Radiation Oncology, University of Miami School of Medicine, Miami, Florida 33136 (United States); Wang, Ken Kang-Hsin; Wong, John W. [Department of Radiation Oncology and Molecular Radiation Sciences, Johns Hopkins University School of Medicine, Baltimore, Maryland 21231 (United States); Eslami, Sohrab; Iordachita, Iulian I. [Laboratory for Computational Sensing and Robotics, Johns Hopkins University, Baltimore, Maryland 21218 (United States); Patterson, Michael S. [Juravinski Cancer Centre and Department of Medical Physics and Applied Radiation Sciences, McMaster University, Hamilton, Ontario L8S4K1 (Canada)

    2015-04-15

    Purpose: The cone beam computed tomography (CBCT) guided small animal radiation research platform (SARRP) has been developed for focal tumor irradiation, allowing laboratory researchers to test basic biological hypotheses that can modify radiotherapy outcomes in ways that were not feasible previously. CBCT provides excellent bone to soft tissue contrast, but is incapable of differentiating tumors from surrounding soft tissue. Bioluminescence tomography (BLT), in contrast, allows direct visualization of even subpalpable tumors and quantitative evaluation of tumor response. Integration of BLT with CBCT offers complementary image information, with CBCT delineating anatomic structures and BLT differentiating luminescent tumors. This study is to develop a systematic method to calibrate an integrated CBCT and BLT imaging system which can be adopted onboard the SARRP to guide focal tumor irradiation. Methods: The integrated imaging system consists of CBCT, diffuse optical tomography (DOT), and BLT. The anatomy acquired from CBCT and optical properties acquired from DOT serve as a priori information for the subsequent BLT reconstruction. Phantoms were designed and procedures were developed to calibrate the CBCT, DOT/BLT, and the entire integrated system. Geometrical calibration was performed to calibrate the CBCT system. Flat field correction was performed to correct the nonuniform response of the optical imaging system. Absolute emittance calibration was performed to convert the camera readout to the emittance at the phantom or animal surface, which enabled the direct reconstruction of the bioluminescence source strength. Phantom and mouse imaging were performed to validate the calibration. Results: All calibration procedures were successfully performed. Both CBCT of a thin wire and a euthanized mouse revealed no spatial artifact, validating the accuracy of the CBCT calibration. The absolute emittance calibration was validated with a 650 nm laser source, resulting in a 3