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Sample records for insulator soi wafers

  1. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  2. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  3. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca; Diab, Amer El Hajj; Ionica, Irina; Ghibaudo, Gerard; Faraone, Lorenzo; Cristoloveanu, Sorin

    2015-01-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  4. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  5. Electrical characterization of thin SOI wafers using lateral MOS transient capacitance measurements

    International Nuclear Information System (INIS)

    Wang, D.; Ueda, A.; Takada, H.; Nakashima, H.

    2006-01-01

    A novel electrical evaluation method was proposed for crystal quality characterization of thin Si on insulator (SOI) wafers, which was done by measurement of minority carrier generation lifetime (τ g ) using transient capacitance method for lateral metal-oxide-semiconductor (MOS) capacitor. The lateral MOS capacitors were fabricated on three kinds of thin SOI wafers. The crystal quality difference among these three wafers was clearly shown by the τ g measurement results and discussed from a viewpoint of SOI fabrication. The series resistance influence on the capacitance measurement for this lateral MOS capacitor was discussed in detail. The validity of this method was confirmed by comparing the intensities of photoluminescence signals due to electron-hole droplet in the band-edge emission

  6. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  7. Second Harmonic Generation characterization of SOI wafers: Impact of layer thickness and interface electric field

    Science.gov (United States)

    Damianos, D.; Vitrant, G.; Lei, M.; Changala, J.; Kaminski-Cachopo, A.; Blanc-Pelissier, D.; Cristoloveanu, S.; Ionica, I.

    2018-05-01

    In this work, we investigate Second Harmonic Generation (SHG) as a non-destructive characterization method for Silicon-On-Insulator (SOI) materials. For thick SOI stacks, the SHG signal is related to the thickness variations of the different layers. However, in thin SOI films, the comparison between measurements and optical modeling suggests a supplementary SHG contribution attributed to the electric fields at the SiO2/Si interfaces. The impact of the electric field at each interface of the SOI on the SHG is assessed. The SHG technique can be used to evaluate interfacial electric fields and consequently interface charge density in SOI materials.

  8. A Lateral Differential Resonant Pressure Microsensor Based on SOI-Glass Wafer-Level Vacuum Packaging

    Directory of Open Access Journals (Sweden)

    Bo Xie

    2015-09-01

    Full Text Available This paper presents the fabrication and characterization of a resonant pressure microsensor based on SOI-glass wafer-level vacuum packaging. The SOI-based pressure microsensor consists of a pressure-sensitive diaphragm at the handle layer and two lateral resonators (electrostatic excitation and capacitive detection on the device layer as a differential setup. The resonators were vacuum packaged with a glass cap using anodic bonding and the wire interconnection was realized using a mask-free electrochemical etching approach by selectively patterning an Au film on highly topographic surfaces. The fabricated resonant pressure microsensor with dual resonators was characterized in a systematic manner, producing a quality factor higher than 10,000 (~6 months, a sensitivity of about 166 Hz/kPa and a reduced nonlinear error of 0.033% F.S. Based on the differential output, the sensitivity was increased to two times and the temperature-caused frequency drift was decreased to 25%.

  9. Boron impurity at the Si/SiO2 interface in SOI wafers and consequences for piezoresistive MEMS devices

    International Nuclear Information System (INIS)

    Nafari, A; Karlen, D; Enoksson, P; Rusu, C; Svensson, K

    2009-01-01

    In this work, the electrical performance of piezoresistive devices fabricated on thinned SOI wafers has been investigated. Specifically, SOI wafers manufactured with the standard bond-and-etch back method (BESOI), commonly used for MEMS fabrication, have been studied. Results from electrical measurements and SIMS characterization show the presence of a boron impurity close to the buried oxide, even on unprocessed wafers. If the boron impurity overlaps with the piezoresistors on the device, it can create non-defined pn-junctions and thus allow conduction through the substrate, leading to stray connections and excessive noise. The thickness of the boron impurity can extend up to several µm, thus setting a thickness limit for the thinnest parts of a MEMS device. This work shows how this impurity can fundamentally affect the functionality of piezoresistive devices. Design rules of how to avoid this are presented

  10. Si-nanowire-based multistage delayed Mach-Zehnder interferometer optical MUX/DeMUX fabricated by an ArF-immersion lithography process on a 300 mm SOI wafer.

    Science.gov (United States)

    Jeong, Seok-Hwan; Shimura, Daisuke; Simoyama, Takasi; Horikawa, Tsuyoshi; Tanaka, Yu; Morito, Ken

    2014-07-01

    We report good phase controllability and high production yield in Si-nanowire-based multistage delayed Mach-Zehnder interferometer-type optical multiplexers/demultiplexers (MUX/DeMUX) fabricated by an ArF-immersion lithography process on a 300 mm silicon-on-insulator (SOI) wafer. Three kinds of devices fabricated in this work exhibit clear 1×4 Ch wavelength filtering operations for various optical frequency spacing. These results are promising for their applications in high-density wavelength division multiplexing-based optical interconnects.

  11. Silicon-on-insulator (SOI) active pixel sensors with the photosite implemented in the substrate

    Science.gov (United States)

    Zheng, Xinyu (Inventor); Pain, Bedabrata (Inventor)

    2005-01-01

    Active pixel sensors for a high quality imager are fabricated using a silicon-on-insulator (SOI) process by integrating the photodetectors on the SOI substrate and forming pixel readout transistors on the SOI thin-film. The technique can include forming silicon islands on a buried insulator layer disposed on a silicon substrate and selectively etching away the buried insulator layer over a region of the substrate to define a photodetector area. Dopants of a first conductivity type are implanted to form a signal node in the photodetector area and to form simultaneously drain/source regions for a first transistor in at least a first one of the silicon islands. Dopants of a second conductivity type are implanted to form drain/source regions for a second transistor in at least a second one of the silicon islands. Isolation rings around the photodetector also can be formed when dopants of the second conductivity type are implanted. Interconnections among the transistors and the photodetector are provided to allow signals sensed by the photodetector to be read out via the transistors formed on the silicon islands.

  12. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    Science.gov (United States)

    Teo, Adrian J. T.; Li, Holden; Tan, Say Hwa; Yoon, Yong-Jin

    2017-06-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G-1, and a highest recorded sensitivity of 44.1 mV G-1. A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices.

  13. An optical MEMS accelerometer fabricated using double-sided deep reactive ion etching on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Teo, Adrian J T; Li, Holden; Yoon, Yong-Jin; Tan, Say Hwa

    2017-01-01

    Optical MEMS devices provide fast detection, electromagnetic resilience and high sensitivity. Using this technology, an optical gratings based accelerometer design concept was developed for seismic motion detection purposes that provides miniaturization, high manufacturability, low costs and high sensitivity. Detailed in-house fabrication procedures of a double-sided deep reactive ion etching (DRIE) on a silicon-on-insulator (SOI) wafer for a micro opto electro mechanical system (MOEMS) device are presented and discussed. Experimental results obtained show that the conceptual device successfully captured motion similar to a commercial accelerometer with an average sensitivity of 13.6 mV G −1 , and a highest recorded sensitivity of 44.1 mV G −1 . A noise level of 13.5 mV was detected due to experimental setup limitations. This is the first MOEMS accelerometer developed using double-sided DRIE on SOI wafer for the application of seismic motion detection, and is a breakthrough technology platform to open up options for lower cost MOEMS devices. (technical note)

  14. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  15. Device fabrication and transport measurements of FinFETs built with 28Si SOI wafers towards donor qubits in silicon

    Energy Technology Data Exchange (ETDEWEB)

    Lo, Cheuk Chi; Persaud, Arun; Dhuey, Scott; Olynick, Deirdre; Borondics, Ferenc; Martin, Michael C.; Bechtel, Hans A.; Bokor, Jeffrey; Schenkel, Thomas

    2009-06-10

    We report fabrication of transistors in a FinFET geometry using isotopically purified silicon-28 -on-insulator (28-SOI) substrates. Donor electron spin coherence in natural silicon is limited by spectral diffusion due to the residual 29Si nuclear spin bath, making isotopically enriched nuclear spin-free 28Si substrates a promising candidate for forming spin quantum bit devices. The FinFET architecture is fully compatible with single-ion implant detection for donor-based qubits, and the donor spin-state readout through electrical detection of spin resonance. We describe device processing steps and discuss results on electrical transport measurements at 0.3 K.

  16. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    Science.gov (United States)

    Song, In-Hyouk; Forfang, William B. D.; Cole, Bryan; You, Byoung Hee

    2014-10-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz.

  17. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  18. Analysis and modeling of wafer-level process variability in 28 nm FD-SOI using split C-V measurements

    Science.gov (United States)

    Pradeep, Krishna; Poiroux, Thierry; Scheer, Patrick; Juge, André; Gouget, Gilles; Ghibaudo, Gérard

    2018-07-01

    This work details the analysis of wafer level global process variability in 28 nm FD-SOI using split C-V measurements. The proposed approach initially evaluates the native on wafer process variability using efficient extraction methods on split C-V measurements. The on-wafer threshold voltage (VT) variability is first studied and modeled using a simple analytical model. Then, a statistical model based on the Leti-UTSOI compact model is proposed to describe the total C-V variability in different bias conditions. This statistical model is finally used to study the contribution of each process parameter to the total C-V variability.

  19. Analysis of silicon on insulator (SOI) optical microring add-drop filter based on waveguide intersections

    Science.gov (United States)

    Kaźmierczak, Andrzej; Bogaerts, Wim; Van Thourhout, Dries; Drouard, Emmanuel; Rojo-Romeo, Pedro; Giannone, Domenico; Gaffiot, Frederic

    2008-04-01

    We present a compact passive optical add-drop filter which incorporates two microring resonators and a waveguide intersection in silicon-on-insulator (SOI) technology. Such a filter is a key element for designing simple layouts of highly integrated complex optical networks-on-chip. The filter occupies an area smaller than 10μm×10μm and exhibits relatively high quality factors (up to 4000) and efficient signal dropping capabilities. In the present work, the influence of filter parameters such as the microring-resonators radii and the coupling section shape are analyzed theoretically and experimentally

  20. Technology development for SOI monolithic pixel detectors

    International Nuclear Information System (INIS)

    Marczewski, J.; Domanski, K.; Grabiec, P.; Grodner, M.; Jaroszewicz, B.; Kociubinski, A.; Kucharski, K.; Tomaszewski, D.; Caccia, M.; Kucewicz, W.; Niemiec, H.

    2006-01-01

    A monolithic detector of ionizing radiation has been manufactured using silicon on insulator (SOI) wafers with a high-resistivity substrate. In our paper the integration of a standard 3 μm CMOS technology, originally designed for bulk devices, with fabrication of pixels in the bottom wafer of a SOI substrate is described. Both technological sequences have been merged minimizing thermal budget and providing suitable properties of all the technological layers. The achieved performance proves that fully depleted monolithic active pixel matrix might be a viable option for a wide spectrum of future applications

  1. A Temperature Sensor using a Silicon-on-Insulator (SOI) Timer for Very Wide Temperature Measurement

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad; Elbuluk, Malik; Culley, Dennis E.

    2008-01-01

    A temperature sensor based on a commercial-off-the-shelf (COTS) Silicon-on-Insulator (SOI) Timer was designed for extreme temperature applications. The sensor can operate under a wide temperature range from hot jet engine compartments to cryogenic space exploration missions. For example, in Jet Engine Distributed Control Architecture, the sensor must be able to operate at temperatures exceeding 150 C. For space missions, extremely low cryogenic temperatures need to be measured. The output of the sensor, which consisted of a stream of digitized pulses whose period was proportional to the sensed temperature, can be interfaced with a controller or a computer. The data acquisition system would then give a direct readout of the temperature through the use of a look-up table, a built-in algorithm, or a mathematical model. Because of the wide range of temperature measurement and because the sensor is made of carefully selected COTS parts, this work is directly applicable to the NASA Fundamental Aeronautics/Subsonic Fixed Wing Program--Jet Engine Distributed Engine Control Task and to the NASA Electronic Parts and Packaging (NEPP) Program. In the past, a temperature sensor was designed and built using an SOI operational amplifier, and a report was issued. This work used an SOI 555 timer as its core and is completely new work.

  2. Fabrication of SGOI material by oxidation of an epitaxial SiGe layer on an SOI wafer with H ions implantation

    International Nuclear Information System (INIS)

    Cheng Xinli; Chen Zhijun; Wang Yongjin; Jin Bo; Zhang Feng; Zou Shichang

    2005-01-01

    SGOI materials were fabricated by thermal dry oxidation of epitaxial H-ion implanted SiGe layers on SOI wafers. The hydrogen implantation was found to delay the oxidation rate of SiGe layer and to decrease the loss of Ge atoms during oxidation. Further, the H implantation did not degrade the crystallinity of SiGe layer during fabrication of the SGOI

  3. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  4. DOUBLE BOSS SCULPTURED DIAPHRAGM EMPLOYED PIEZORESISTIVE MEMS PRESSURE SENSOR WITH SILICON-ON-INSULATOR (SOI

    Directory of Open Access Journals (Sweden)

    D. SINDHANAISELVI

    2017-07-01

    Full Text Available This paper presents the detailed study on the measurement of low pressure sensor using double boss sculptured diaphragm of piezoresistive type with MEMS technology in flash flood level measurement. The MEMS based very thin diaphragms to sense the low pressure is analyzed by introducing supports to achieve linearity. The simulation results obtained from Intellisuite MEMS CAD design tool show that very thin diaphragms with rigid centre or boss give acceptable linearity. Further investigations on very thin diaphragms embedded with piezoresistor for low pressure measurement show that it is essential to analyse the piezoresistor placement and size of piezoresistor to achieve good sensitivity. A modified analytical modelling developed in this study for double boss sculptured diaphragm results were compared with simulated results. Further the enhancement of sensitivity is analyzed using non uniform thickness diaphragm and Silicon-On-Insulator (SOI technique. The simulation results indicate that the double boss square sculptured diaphragm with SOI layer using 0.85μm thickness yields the higher voltage sensitivity, acceptable linearity with Small Scale Deflection.

  5. Photonic Hilbert transformers based on laterally apodized integrated waveguide Bragg gratings on a SOI wafer.

    Science.gov (United States)

    Bazargani, Hamed Pishvai; Burla, Maurizio; Chrostowski, Lukas; Azaña, José

    2016-11-01

    We experimentally demonstrate high-performance integer and fractional-order photonic Hilbert transformers based on laterally apodized Bragg gratings in a silicon-on-insulator technology platform. The sub-millimeter-long gratings have been fabricated using single-etch electron beam lithography, and the resulting HT devices offer operation bandwidths approaching the THz range, with time-bandwidth products between 10 and 20.

  6. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Science.gov (United States)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  7. A novel δ-doped partially insulated dopant-segregated Schottky barrier SOI MOSFET for analog/RF applications

    International Nuclear Information System (INIS)

    Patil, Ganesh C; Qureshi, S

    2011-01-01

    In this paper, a comparative analysis of single-gate dopant-segregated Schottky barrier (DSSB) SOI MOSFET and raised source/drain ultrathin-body SOI MOSFET (RSD UTB) has been carried out to explore the thermal efficiency, scalability and analog/RF performance of these devices. A novel p-type δ-doped partially insulated DSSB SOI MOSFET (DSSB Pi-OX-δ) has been proposed to reduce the self-heating effect and to improve the high-frequency performance of DSSB SOI MOSFET over RSD UTB. The improved analog/RF figures of merit such as transconductance, transconductance generation factor, unity-gain frequency, maximum oscillation frequency, short-circuit current gain and unilateral power gain in DSSB Pi-OX-δ MOSFET show the suitability of this device for analog/RF applications. The reduced drain-induced barrier lowering, subthreshold swing and parasitic capacitances also make this device highly scalable. By using mixed-mode simulation capability of MEDICI simulator a cascode amplifier has been implemented using all the structures (RSD UTB, DSSB SOI and DSSB Pi-OX-δ MOSFETs). The results of this implementation show that the gain-bandwidth product in the case of DSSB Pi-OX-δ MOSFET has improved by 50% as compared to RSD UTB and by 20% as compared to DSSB SOI MOSFET. The detailed fabrication flow of DSSB Pi-OX-δ MOSFET has been proposed which shows that with the bare minimum of steps the performance of DSSB SOI MOSFET can be improved significantly in comparison to RSD UTB

  8. VCSELs and silicon light sources exploiting SOI grating mirrors

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2012-01-01

    In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI...... the Bragg reflector. Numerical simulations show that both the silicon light source and the VCSEL exploiting SOI grating mirrors have superior performances, compared to existing silicon light sources and long wavelength VCSELs. These devices are highly adequate for chip-level optical interconnects as well...

  9. Integrated circuits of silicon on insulator S.O.I. technologies: State of the art and perspectives

    International Nuclear Information System (INIS)

    Leray, J.L.; Dupont-Nivet, E.; Raffaelli, M.; Coic, Y.M.; Musseau, O.; Pere, J.F.; Lalande, P.; Bredy, J.; Auberton-Herve, A.J.; Bruel, M.; Giffard, B.

    1989-01-01

    Silicon On Insulator technologies have been proposed to increase the integrated circuits performances in radiation operation. Active researches are conducted, in France and abroad. This paper reviews briefly radiation effects phenomenology in that particular type of structure S.O.I. New results are presented that show very good radiation behaviour in term of speed, dose (10 to 100 megarad (Si)), dose rate and S.E.U. performances [fr

  10. Influence of Bipolar Pulse Poling Technique for Piezoelectric Vibration Energy Harvesters using Pb(Zr,Ti)O3 Films on 200 mm SOI Wafers

    International Nuclear Information System (INIS)

    Moriwaki, N; Fujimoto, K; Suzuki, K; Kobayashi, T; Itoh, T; Maeda, R; Suzuki, Y; Makimoto, N

    2013-01-01

    Piezoelectric vibration energy harvester arrays using Pb(Zr,Ti)O 3 thin films on 200 mm SOI wafers were fabricated. In-plane distribution of influence of bipolar pulse poling technique on direct current (DC) power output from the harvesters was investigated. The results indicate that combination poling treatment of DC and bipolar pulse poling increases a piezoelectric property and reduces a dielectric constant. It means that this poling technique improves the figure of merit of sensors and harvesters. Maximum DC power from a harvester treated by DC poling after bipolar pulse poling is about five times larger than a one treated by DC poling only

  11. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  12. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination......A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  13. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  14. Electronics and Sensor Study with the OKI SOI process

    CERN Document Server

    Arai, Yasuo

    2007-01-01

    While the SOI (Silicon-On-Insulator) device concept is very old, commercialization of the technology is relatively new and growing rapidly in high-speed processor and lowpower applications. Furthermore, features such as latch-up immunity, radiation hardness and high-temperature operation are very attractive in high energy and space applications. Once high-quality bonded SOI wafers became available in the late 90s, it opened up the possibility to get two different kinds of Si on a single wafer. This makes it possible to realize an ideal pixel detector; pairing a fully-depleted radiation sensor with CMOS circuitry in an industrial technology. In 2005 we started Si pixel R&D with OKI Electric Ind. Co., Ltd. which is the first market supplier of Fully-Depleted SOI products. We have developed processes for p+/n+ implants to the substrate and for making connections between the implants and circuits in the OKI 0.15μm FD-SOI CMOS process. We have preformed two Multi Project Wafer (MPW) runs using this SOI proces...

  15. Formation of III–V-on-insulator structures on Si by direct wafer bonding

    International Nuclear Information System (INIS)

    Yokoyama, Masafumi; Iida, Ryo; Ikku, Yuki; Kim, Sanghyeon; Takenaka, Mitsuru; Takagi, Shinichi; Takagi, Hideki; Yasuda, Tetsuji; Yamada, Hisashi; Ichikawa, Osamu; Fukuhara, Noboru; Hata, Masahiko

    2013-01-01

    We have studied the formation of III–V-compound-semiconductors-on-insulator (III–V-OI) structures with thin buried oxide (BOX) layers on Si wafers by using developed direct wafer bonding (DWB). In order to realize III–V-OI MOSFETs with ultrathin body and extremely thin body (ETB) InGaAs-OI channel layers and ultrathin BOX layers, we have developed an electron-cyclotron resonance (ECR) O 2 plasma-assisted DWB process with ECR sputtered SiO 2 BOX layers and a DWB process based on atomic-layer-deposition Al 2 O 3 (ALD-Al 2 O 3 ) BOX layers. It is essential to suppress micro-void generation during wafer bonding process to achieve excellent wafer bonding. We have found that major causes of micro-void generation in DWB processes with ECR-SiO 2 and ALD-Al 2 O 3 BOX layers are desorption of Ar and H 2 O gas, respectively. In order to suppress micro-void generation in the ECR-SiO 2 BOX layers, it is effective to introduce the outgas process before bonding wafers. On the other hand, it is a possible solution for suppressing micro-void generation in the ALD-Al 2 O 3 BOX layers to increase the deposition temperature of the ALD-Al 2 O 3 BOX layers. It is also another possible solution to deposit ALD-Al 2 O 3 BOX layers on thermally oxidized SiO 2 layers, which can absorb the desorption gas from ALD-Al 2 O 3 BOX layers. (invited paper)

  16. Strong Electro-Absorption in GeSi Epitaxy on Silicon-on-Insulator (SOI

    Directory of Open Access Journals (Sweden)

    John E. Cunningham

    2012-04-01

    Full Text Available We have investigated the selective epitaxial growth of GeSi bulk material on silicon-on-insulator substrates by reduced pressure chemical vapor deposition. We employed AFM, SIMS, and Hall measurements, to characterize the GeSi heteroepitaxy quality. Optimal growth conditions have been identified to achieve low defect density, low RMS roughness with high selectivity and precise control of silicon content. Fabricated vertical p-i-n diodes exhibit very low dark current density of 5 mA/cm2 at −1 V bias. Under a 7.5 V/µm E-field, GeSi alloys with 0.6% Si content demonstrate very strong electro-absorption with an estimated effective ∆α/α around 3.5 at 1,590 nm. We compared measured ∆α/α performance to that of bulk Ge. Optical modulation up to 40 GHz is observed in waveguide devices while small signal analysis indicates bandwidth is limited by device parasitics.

  17. A monolithic active pixel sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany)

    2016-07-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-180 nm High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. Standard FD-SOI MAPS suffer from radiation damage such as transistor threshold voltage shifts due to trapped charge in the buried oxide layer and charged interface states created at the silicon oxide boundaries (back gate effect). The X-FAB 180 nm HV-SOI technology offers an additional isolation using a deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection. The design and measurement results from first prototypes are presented including radiation tolerance to total ionizing dose and charge collection properties of neutron irradiated samples.

  18. A Monolithic Active Pixel Sensor for ionizing radiation using a 180 nm HV-SOI process

    Energy Technology Data Exchange (ETDEWEB)

    Hemperek, Tomasz, E-mail: hemperek@uni-bonn.de; Kishishita, Tetsuichi; Krüger, Hans; Wermes, Norbert

    2015-10-01

    An improved SOI-MAPS (Silicon On Insulator Monolithic Active Pixel Sensor) for ionizing radiation based on thick-film High Voltage SOI technology (HV-SOI) has been developed. Similar to existing Fully Depleted SOI-based (FD-SOI) MAPS, a buried silicon oxide inter-dielectric (BOX) layer is used to separate the CMOS electronics from the handle wafer which is used as a depleted charge collection layer. FD-SOI MAPS suffers from radiation damage such as transistor threshold voltage shifts due to charge traps in the oxide layers and charge states created at the silicon oxide boundaries (back gate effect). The X-FAB 180-nm HV-SOI technology offers an additional isolation by deep non-depleted implant between the BOX layer and the active circuitry which mitigates this problem. Therefore we see in this technology a high potential to implement radiation-tolerant MAPS with fast charge collection property. The design and measurement results from a first prototype are presented including charge collection in neutron irradiated samples.

  19. Defects reduction of Ge epitaxial film in a germanium-on-insulator wafer by annealing in oxygen ambient

    Directory of Open Access Journals (Sweden)

    Kwang Hong Lee

    2015-01-01

    Full Text Available A method to remove the misfit dislocations and reduce the threading dislocations density (TDD in the germanium (Ge epilayer growth on a silicon (Si substrate is presented. The Ge epitaxial film is grown directly on the Si (001 donor wafer using a “three-step growth” approach in a reduced pressure chemical vapour deposition. The Ge epilayer is then bonded and transferred to another Si (001 handle wafer to form a germanium-on-insulator (GOI substrate. The misfit dislocations, which are initially hidden along the Ge/Si interface, are now accessible from the top surface. These misfit dislocations are then removed by annealing the GOI substrate. After the annealing, the TDD of the Ge epilayer can be reduced by at least two orders of magnitude to <5 × 106 cm−2.

  20. Process Optimization for Monolithic Integration of Piezoresistive Pressure Sensor and MOSFET Amplifier with SOI Approach

    International Nuclear Information System (INIS)

    Kumar, V Vinoth; Dasgupta, A; Bhat, K N; KNatarajan

    2006-01-01

    In this paper we present the design and process optimization for fabricating piezoresitive pressure sensor and MOSFET Differential Amplifier simultaneously on the same chip. Silicon On Insulator approach has been used for realizing the membrane as well as the electronics on the same chip. The amplifier circuit has been configured in the common source connection and it has been designed with PSPICE simulation to achieve a voltage gain of about 5. In the initial set of experiments the Pressure sensor and the amplifier were fabricated on separate chips to optimize the process steps and tested in the hybrid mode. In the next set of experiments, SOI wafer having the SOI layer thickness of about 11 microns was used for realizing the membrane by anisotropic etching from the backside. The piezo-resistive pressure sensor was realized on this membrane by connecting the polysilicon resistors in the form of a Wheatstone bridge. The MOSFET source follower amplifier was also fabricated on the same SOI wafer by tailoring the process steps to suit the requirement of simultaneous fabrication of piezoresistors and the amplifier for achieving MOSFET Integrated Pressure Sensor. Reproducible results have been achieved on the SOI wafers, with the process steps developed in the laboratory. Sensitivity of 270 mV /Bar/10V, with the on chip amplifier gain of 4.5, has been achieved with this process

  1. Performance of the INTPIX6 SOI pixel detector

    Science.gov (United States)

    Arai, Y.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Kucewicz, W.; Miyoshi, T.; Turala, M.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e-. The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e-. The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  2. Test-beam results of a SOI pixel detector prototype

    CERN Document Server

    Bugiel, Roma; Dannheim, Dominik; Fiergolski, Adrian; Hynds, Daniel; Idzik, Marek; Kapusta, P; Kucewicz, Wojciech; Munker, Ruth Magdalena; Nurnberg, Andreas Matthias

    2018-01-01

    This paper presents the test-beam results of a monolithic pixel-detector prototype fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology. The SOI detector was tested at the CERN SPS H6 beam line. The detector is fabricated on a 500 μm thick high-resistivity float- zone n-type (FZ-n) wafer. The pixel size is 30 μm × 30 μm and its readout uses a source- follower configuration. The test-beam data are analysed in order to compute the spatial resolution and detector efficiency. The analysis chain includes pedestal and noise calculation, cluster reconstruction, as well as alignment and η-correction for non-linear charge sharing. The results show a spatial resolution of about 4.3 μm.

  3. Terahertz wafer-scale mobility mapping of graphene on insulating substrates without a gate

    DEFF Research Database (Denmark)

    Buron, Jonas Due; Mackenzie, David M. A.; Petersen, Dirch Hjorth

    2015-01-01

    We demonstrate wafer-scale, non-contact mapping of essential carrier transport parameters, carrier mobility (mu(drift)), carrier density (N-S), DC sheet conductance (sigma(dc)), and carrier scattering time (tau(SC)) in CVD graphene, using spatially resolved terahertz time-domain conductance...

  4. Silicon on insulator self-aligned transistors

    Science.gov (United States)

    McCarthy, Anthony M.

    2003-11-18

    A method for fabricating thin-film single-crystal silicon-on-insulator (SOI) self-aligned transistors. Standard processing of silicon substrates is used to fabricate the transistors. Physical spaces, between the source and gate, and the drain and gate, introduced by etching the polysilicon gate material, are used to provide connecting implants (bridges) which allow the transistor to perform normally. After completion of the silicon substrate processing, the silicon wafer is bonded to an insulator (glass) substrate, and the silicon substrate is removed leaving the transistors on the insulator (glass) substrate. Transistors fabricated by this method may be utilized, for example, in flat panel displays, etc.

  5. Electrical activation of solid-phase epitaxially regrown ultra-low energy boron implants in Ge preamorphised silicon and SOI

    International Nuclear Information System (INIS)

    Hamilton, J.J.; Collart, E.J.H.; Colombeau, B.; Jeynes, C.; Bersani, M.; Giubertoni, D.; Sharp, J.A.; Cowern, N.E.B.; Kirkby, K.J.

    2005-01-01

    The formation of highly activated ultra-shallow junctions (USJ) is one of the key requirements for the next generation of CMOS devices. One promising method for achieving this is the use of Ge preamorphising implants (PAI) prior to ultra-low energy B implantation. In future technology nodes, bulk silicon wafers may be supplanted by Silicon-on-Insulator (SOI), and an understanding of the Solid Phase Epitaxial (SPE) regrowth process and its correlation to dopant electrical activation in both bulk silicon and SOI is essential in order to understand the impact of this potential technology change. This kind of understanding will also enable tests of fundamental models for defect evolution and point-defect reactions at silicon/oxide interfaces. In the present work, B is implanted into Ge PAI silicon and SOI wafers with different PAI conditions and B doses, and resulting samples are annealed at various temperatures and times. Glancing-exit Rutherford Backscattering Spectrometry (RBS) is used to monitor the regrowth of the amorphous silicon, and the resulting redistribution and electrical activity of B are monitored by SIMS and Hall measurements. The results confirm the expected enhancement of regrowth velocity by B doping, and show that this velocity is otherwise independent of the substrate type and the Ge implant distribution within the amorphised layer. Hall measurements on isochronally annealed samples show that B deactivates less in SOI material than in bulk silicon, in cases where the Ge PAI end-of-range defects are close to the SOI back interface

  6. Ultra-low power high temperature and radiation hard complementary metal-oxide-semiconductor (CMOS) silicon-on-insulator (SOI) voltage reference.

    Science.gov (United States)

    Boufouss, El Hafed; Francis, Laurent A; Kilchytska, Valeriya; Gérard, Pierre; Simon, Pascal; Flandre, Denis

    2013-12-13

    This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of -40-200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage V(REF) depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of V(REF) and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

  7. Characterization of dielectric materials in thin layers for the development of S.O.I. (Silicon on Insulator) substrates

    International Nuclear Information System (INIS)

    Gruber, Olivier

    1999-01-01

    This thesis deals with the characterization of oxide layer placed inside S.O.I. substrates and submitted to irradiation. This type of material is used for the development of hardened electronic components, that is to say components able to be used in a radiative environment. The irradiation induces charges (electrons or holes) in the recovered oxide. A part of these charges is trapped which leads to changes of the characteristics of the electronic components made on these substrates. The main topic of this study is the characterization of trapping properties of recovered oxides and more particularly of 'Unibond' material carried out with a new fabrication process: the 'smart-cut' process. This work is divided into three parts: - study with one carrier: this case is limited to low radiation doses where is only observed holes trapping. The evolution of the physical and chemical properties of the 'Unibond' material recovered oxide has been revealed, this evolution being due to the fabrication process. - Study with two carriers: in this case, there is trapping of holes and electrons. This type of trapping is observed in the case of strong radiation doses. A new type of electrons traps has been identified with the 'Unibond' material oxide. The transport and the trapping of holes and electrons have been studied in the case of transient phenomena created by short radiative pulses. This study has been carried out using a new measurement method. - Study with three carriers: here are added to holes and electrons the protons introduced in the recovered oxide by the annealing under hydrogen. These protons are movable when they are submitted to the effect of an electric field and they induce a memory effect according to their position in the oxide. These different works show that the 'Unibond' material is a very good solution for the future development of S.O.I. (author) [fr

  8. A high-temperature silicon-on-insulator stress sensor

    International Nuclear Information System (INIS)

    Wang Zheyao; Tian Kuo; Zhou Youzheng; Pan Liyang; Liu Litian; Hu Chaohong

    2008-01-01

    A piezoresistive stress sensor is developed using silicon-on-insulator (SOI) wafers and calibrated for stress measurement for high-temperature applications. The stress sensor consists of 'silicon-island-like' piezoresistor rosettes that are etched on the SOI layer. This eliminates leakage current and enables excellent electrical insulation at high temperature. To compensate for the measurement errors caused by the misalignment of the piezoresistor rosettes with respect to the crystallographic axes, an anisotropic micromachining technique, tetramethylammonium hydroxide etching, is employed to alleviate the misalignment issue. To realize temperature-compensated stress measurement, a planar diode is fabricated as a temperature sensor to decouple the temperature information from the piezoresistors, which are sensitive to both stress and temperature. Design, fabrication and calibration of the piezoresistors are given. SOI-related characteristics such as piezoresistive coefficients and temperature coefficients as well as the influence of the buried oxide layer are discussed in detail

  9. 110 GHz hybrid mode-locked fiber laser with enhanced extinction ratio based on nonlinear silicon-on-insulator micro-ring-resonator (SOI MRR)

    International Nuclear Information System (INIS)

    Liu, Yang; Hsu, Yung; Chow, Chi-Wai; Yang, Ling-Gang; Lai, Yin-Chieh; Yeh, Chien-Hung; Tsang, Hon-Ki

    2016-01-01

    We propose and experimentally demonstrate a new 110 GHz high-repetition-rate hybrid mode-locked fiber laser using a silicon-on-insulator microring-resonator (SOI MRR) acting as the optical nonlinear element and optical comb filter simultaneously. By incorporating a phase modulator (PM) that is electrically driven at a fraction of the harmonic frequency, an enhanced extinction ratio (ER) of the optical pulses can be produced. The ER of the optical pulse train increases from 3 dB to 10 dB. As the PM is only electrically driven by the signal at a fraction of the harmonic frequency, in this case 22 GHz (110 GHz/5 GHz), a low bandwidth PM and driving circuit can be used. The mode-locked pulse width and the 3 dB spectral bandwidth of the proposed mode-locked fiber laser are measured, showing that the optical pulses are nearly transform limited. Moreover, stability evaluation for an hour is performed, showing that the proposed laser can achieve stable mode-locking without the need for optical feedback or any other stabilization mechanism. (letter)

  10. Method to improve commercial bonded SOI material

    Science.gov (United States)

    Maris, Humphrey John; Sadana, Devendra Kumar

    2000-07-11

    A method of improving the bonding characteristics of a previously bonded silicon on insulator (SOI) structure is provided. The improvement in the bonding characteristics is achieved in the present invention by, optionally, forming an oxide cap layer on the silicon surface of the bonded SOI structure and then annealing either the uncapped or oxide capped structure in a slightly oxidizing ambient at temperatures greater than 1200.degree. C. Also provided herein is a method for detecting the bonding characteristics of previously bonded SOI structures. According to this aspect of the present invention, a pico-second laser pulse technique is employed to determine the bonding imperfections of previously bonded SOI structures.

  11. Large current MOSFET on photonic silicon-on-insulator wafers and its monolithic integration with a thermo-optic 2 × 2 Mach-Zehnder switch.

    Science.gov (United States)

    Cong, G W; Matsukawa, T; Chiba, T; Tadokoro, H; Yanagihara, M; Ohno, M; Kawashima, H; Kuwatsuka, H; Igarashi, Y; Masahara, M; Ishikawa, H

    2013-03-25

    n-channel body-tied partially depleted metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated for large current applications on a silicon-on-insulator wafer with photonics-oriented specifications. The MOSFET can drive an electrical current as large as 20 mA. We monolithically integrated this MOSFET with a 2 × 2 Mach-Zehnder interferometer optical switch having thermo-optic phase shifters. The static and dynamic performances of the integrated device are experimentally evaluated.

  12. Total dose radiation effects of pressure sensors fabricated on uni-bond-SOI materials

    International Nuclear Information System (INIS)

    Zhu Shiyang; Huang Yiping; Wang Jin; Li Anzhen; Shen Shaoqun; Bao Minhang

    2001-01-01

    Piezoresistive pressure sensors with a twin-island structure were successfully fabricated using high quality Uni-bond-SOI (On Insulator) materials. Since the piezoresistors were structured by the single crystalline silicon overlayer of the SOI wafer and were totally isolated by the buried SiO 2 , the sensors are radiation-hard. The sensitivity and the linearity of the pressure sensors keep their original values after being irradiated by 60 Co γ-rays up to 2.3 x 10 4 Gy(H 2 O). However, the offset voltage of the sensor has a slight drift, increasing with the radiation dose. The absolute value of the offset voltage deviation depends on the pressure sensor itself. For comparison, corresponding polysilicon pressure sensors were fabricated using the similar process and irradiated at the same condition

  13. Design and fabrication of piezoresistive p-SOI Wheatstone bridges for high-temperature applications

    Science.gov (United States)

    Kähler, Julian; Döring, Lutz; Merzsch, Stephan; Stranz, Andrej; Waag, Andreas; Peiner, Erwin

    2011-06-01

    For future measurements while depth drilling, commercial sensors are required for a temperature range from -40 up to 300 °C. Conventional piezoresistive silicon sensors cannot be used at higher temperatures due to an exponential increase of leakage currents which results in a drop of the bridge voltage. A well-known procedure to expand the temperature range of silicon sensors and to reduce leakage currents is to employ Silicon-On-Insulator (SOI) instead of standard wafer material. Diffused resistors can be operated up to 200 °C, but show the same problems beyond due to leakage of the p-njunction. Our approach is to use p-SOI where resistors as well as interconnects are defined by etching down to the oxide layer. Leakage is suppressed and the temperature dependence of the bridges is very low (TCR = (2.6 +/- 0.1) μV/K@1 mA up to 400 °C). The design and process flow will be presented in detail. The characteristics of Wheatstone bridges made of silicon, n- SOI, and p-SOI will be shown for temperatures up to 300 °C. Besides, thermal FEM-simulations will be described revealing the effect of stress between silicon and the silicon-oxide layer during temperature cycling.

  14. Performance of the INTPIX6 SOI pixel detector

    International Nuclear Information System (INIS)

    Arai, Y.; Miyoshi, T.; Bugiel, Sz.; Dasgupta, R.; Idzik, M.; Kapusta, P.; Turala, M.; Kucewicz, W.

    2017-01-01

    Characterization of the monolithic pixel detector INPTIX6, designed at KEK and fabricated in Lapis 0.2 μ  m Fully-Depleted, Low-Leakage Silicon-On-Insulator (SOI) CMOS technology, was performed. The INTPIX6 comprises a large area of 1408 × 896 integrating type squared pixels of 12 micron pitch. In this work the performance and measurement results of the prototypes produced on lower resistivity Czochralski type (CZ-n) and high resistivity floating zone (FZ-n) sensor wafers are presented. Using 241 Am radioactive source the noise of INTPIX6 was measured, showing the ENC (Equivalent Noise Charge) of about 70 e − . The resolution calculated from the FWHM of the Iron-55 X-ray peak was about 100 e − . The radiation hardness of the SOI pixel detector was also investigated. The CZ-n type INTPIX6 received a dose of 60 krad and its performance has been continuously monitored during the irradiation.

  15. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  16. SOI MESFETs for Extreme Environment Electronics, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — We are proposing a new extreme environment electronics (EEE) technology based on silicon-on-insulator (SOI) metal-semiconductor field-effect transistors (MESFETs)....

  17. Performance analysis of SOI MOSFET with rectangular recessed channel

    Science.gov (United States)

    Singh, M.; Mishra, S.; Mohanty, S. S.; Mishra, G. P.

    2016-03-01

    In this paper a two dimensional (2D) rectangular recessed channel-silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed.

  18. Performance analysis of SOI MOSFET with rectangular recessed channel

    International Nuclear Information System (INIS)

    Singh, M; Mishra, G P; Mishra, S; Mohanty, S S

    2016-01-01

    In this paper a two dimensional (2D) rectangular recessed channel–silicon on insulator metal oxide semiconductor field effect transistor (RRC-SOI MOSFET), using the concept of groove between source and drain regions, which is one of the channel engineering technique to suppress the short channel effect (SCE). This suppression is mainly due to corner potential barrier of the groove and the simulation is carried out by using ATLAS 2D device simulator. To have further improvement of SCE in RRC-SOI MOSFET, three more devices are designed by using dual material gate (DMG) and gate dielectric technique, which results in formation of devices i.e. DMRRC-SOI,MLSMRRC-SOI, MLDMRRC-SOI MOSFET. The effect of different structures of RRC-SOI on AC and RF parameters are investigated and the importance of these devices over RRC MOSFET regarding short channel effect is analyzed. (paper)

  19. Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

    International Nuclear Information System (INIS)

    Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

    2005-01-01

    This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

  20. Waveguide-integrated vertical pin photodiodes of Ge fabricated on p+ and n+ Si-on-insulator layers

    Science.gov (United States)

    Ito, Kazuki; Hiraki, Tatsurou; Tsuchizawa, Tai; Ishikawa, Yasuhiko

    2017-04-01

    Vertical pin structures of Ge photodiodes (PDs) integrated with Si optical waveguides are fabricated by depositing Ge epitaxial layers on Si-on-insulator (SOI) layers, and the performances of n+-Ge/i-Ge/p+-SOI PDs are compared with those of p+-Ge/i-Ge/n+-SOI PDs. Both types of PDs show responsivities as high as 1.0 A/W at 1.55 µm, while the dark leakage current is different, which is consistent with previous reports on free-space PDs formed on bulk Si wafers. The dark current of the p+-Ge/i-Ge/n+-SOI PDs is higher by more than one order of magnitude. Taking into account the activation energies for dark current as well as the dependence on PD area, the dark current of the n+-Ge/i-Ge/p+-SOI PDs is dominated by the thermal generation of carriers via mid-gap defect levels in Ge, while for the p+-Ge/i-Ge/n+-SOI PDs, the dark current is ascribed to not only thermal generation but also other mechanisms such as locally formed conduction paths.

  1. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  2. Mixed logic style adder circuit designed and fabricated using SOI substrate for irradiation-hardened experiment

    Science.gov (United States)

    Yuan, Shoucai; Liu, Yamei

    2016-08-01

    This paper proposed a rail to rail swing, mixed logic style 28-transistor 1-bit full adder circuit which is designed and fabricated using silicon-on-insulator (SOI) substrate with 90 nm gate length technology. The main goal of our design is space application where circuits may be damaged by outer space radiation; so the irradiation-hardened technique such as SOI structure should be used. The circuit's delay, power and power-delay product (PDP) of our proposed gate diffusion input (GDI)-based adder are HSPICE simulated and compared with other reported high-performance 1-bit adder. The GDI-based 1-bit adder has 21.61% improvement in delay and 18.85% improvement in PDP, over the reported 1-bit adder. However, its power dissipation is larger than that reported with 3.56% increased but is still comparable. The worst case performance of proposed 1-bit adder circuit is also seen to be less sensitive to variations in power supply voltage (VDD) and capacitance load (CL), over a wide range from 0.6 to 1.8 V and 0 to 200 fF, respectively. The proposed and reported 1-bit full adders are all layout designed and wafer fabricated with other circuits/systems together on one chip. The chip measurement and analysis has been done at VDD = 1.2 V, CL = 20 fF, and 200 MHz maximum input signal frequency with temperature of 300 K.

  3. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  4. Characterization of SOI monolithic detector system

    Science.gov (United States)

    Álvarez-Rengifo, P. L.; Soung Yee, L.; Martin, E.; Cortina, E.; Ferrer, C.

    2013-12-01

    A monolithic active pixel sensor for charged particle tracking was developed. This research is performed within the framework of an R&D project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology) whose aim is to evaluate the feasibility of developing a Monolithic Active Pixel Sensor (MAPS) with Silicon-on-Insulator (SOI) technology. Two chips were fabricated: TRAPPISTe-1 and TRAPPISTe-2. TRAPPISTe-1 was produced at the WINFAB facility at the Université catholique de Louvain (UCL), Belgium, in a 2 μm fully depleted (FD-SOI) CMOS process. TRAPPISTe-2 was fabricated with the LAPIS 0.2 μm FD-SOI CMOS process. The electrical characterization on single transistor test structures and of the electronic readout for the TRAPPISTe series of monolithic pixel detectors was carried out. The behavior of the prototypes’ electronics as a function of the back voltage was studied. Results showed that both readout circuits exhibited sensitivity to the back voltage. Despite this unwanted secondary effect, the responses of TRAPPISTe-2 amplifiers can be improved by a variation in the circuit parameters.

  5. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  6. Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

    Science.gov (United States)

    Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

    2018-02-01

    In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

  7. Characterization of light element impurities in ultrathin silicon-on-insulator layers by luminescence activation using electron irradiation

    International Nuclear Information System (INIS)

    Nakagawa-Toyota, Satoko; Tajima, Michio; Hirose, Kazuyuki; Ohshima, Takeshi; Itoh, Hisayoshi

    2009-01-01

    We analyzed light element impurities in ultrathin top Si layers of silicon-on-insulator (SOI) wafers by luminescence activation using electron irradiation. Photoluminescence (PL) analysis under ultraviolet (UV) light excitation was performed on various commercial SOI wafers after the irradiation. We detected the C-line related to a complex of interstitial carbon and oxygen impurities and the G-line related to a complex of interstitial and substitutional carbon impurities in the top Si layer with a thickness down to 62 nm after electron irradiation. We showed that there were differences in the impurity concentration depending on the wafer fabrication methods and also that there were variations in these concentrations in the respective wafers. Xenon ion implantation was used to activate top Si layers selectively so that we could confirm that the PL signal under the UV light excitation comes not from substrates but from top Si layers. The present method is a very promising tool to evaluate the light element impurities in top Si layers. (author)

  8. SOI Digital Accelerometer Based on Pull-in Time Configuration

    NARCIS (Netherlands)

    Pakula, L.S.; Rajaraman, V.; French, P.J.

    2009-01-01

    The operation principle, design, fabrication and measurement results of a quasi digital accelerometer fabricated on a thin silicon-on-insulator (SOI) substrate is presented. The accelerometer features quasi-digital output, therefore eliminating the need for analogue signal conditioning. The

  9. A high efficiency lateral light emitting device on SOI

    NARCIS (Netherlands)

    Hoang, T.; Le Minh, P.; Holleman, J.; Zieren, V.; Goossens, M.J.; Schmitz, Jurriaan

    2005-01-01

    The infrared light emission of lateral p/sup +/-p-n/sup +/ diodes realized on SIMOX-SOI (separation by implantation of oxygen - silicon on insulator) substrates has been studied. The confinement of the free carriers in one dimension due to the buried oxide was suggested to be a key point to increase

  10. An SEU resistant 256K SOI SRAM

    Science.gov (United States)

    Hite, L. R.; Lu, H.; Houston, T. W.; Hurta, D. S.; Bailey, W. E.

    1992-12-01

    A novel SEU (single event upset) resistant SRAM (static random access memory) cell has been implemented in a 256K SOI (silicon on insulator) SRAM that has attractive performance characteristics over the military temperature range of -55 to +125 C. These include worst-case access time of 40 ns with an active power of only 150 mW at 25 MHz, and a worst-case minimum WRITE pulse width of 20 ns. Measured SEU performance gives an Adams 10 percent worst-case error rate of 3.4 x 10 exp -11 errors/bit-day using the CRUP code with a conservative first-upset LET threshold. Modeling does show that higher bipolar gain than that measured on a sample from the SRAM lot would produce a lower error rate. Measurements show the worst-case supply voltage for SEU to be 5.5 V. Analysis has shown this to be primarily caused by the drain voltage dependence of the beta of the SOI parasitic bipolar transistor. Based on this, SEU experiments with SOI devices should include measurements as a function of supply voltage, rather than the traditional 4.5 V, to determine the worst-case condition.

  11. SOI MESFETs on high-resistivity, trap-rich substrates

    Science.gov (United States)

    Mehr, Payam; Zhang, Xiong; Lepkowski, William; Li, Chaojiang; Thornton, Trevor J.

    2018-04-01

    The DC and RF characteristics of metal-semiconductor field-effect-transistors (MESFETs) on conventional CMOS silicon-on-insulator (SOI) substrates are compared to nominally identical devices on high-resistivity, trap-rich SOI substrates. While the DC transfer characteristics are statistically identical on either substrate, the maximum available gain at GHz frequencies is enhanced by ∼2 dB when using the trap-rich substrates, with maximum operating frequencies, fmax, that are approximately 5-10% higher. The increased fmax is explained by the reduced substrate conduction at GHz frequencies using a lumped-element, small-signal model.

  12. Investigation of veritcal graded channel doping in nanoscale fully-depleted SOI-MOSFET

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2016-10-01

    For achieving reliable transistor, we investigate an amended channel doping (ACD) engineering which improves the electrical and thermal performances of fully-depleted silicon-on-insulator (SOI) MOSFET. We have called the proposed structure with the amended channel doping engineering as ACD-SOI structure and compared it with a conventional fully-depleted SOI MOSFET (C-SOI) with uniform doping distribution using 2-D ATLAS simulator. The amended channel doping is a vertical graded doping that is distributed from the surface of structure with high doping density to the bottom of channel, near the buried oxide, with low doping density. Short channel effects (SCEs) and leakage current suppress due to high barrier height near the source region and electric field modification in the ACD-SOI in comparison with the C-SOI structure. Furthermore, by lower electric field and electron temperature near the drain region that is the place of hot carrier generation, we except the improvement of reliability and gate induced drain lowering (GIDL) in the proposed structure. Undesirable Self heating effect (SHE) that become a critical challenge for SOI MOSFETs is alleviated in the ACD-SOI structure because of utilizing low doping density near the buried oxide. Thus, refer to accessible results, the ACD-SOI structure with graded distribution in vertical direction is a reliable device especially in low power and high temperature applications.

  13. Photoluminescence and TEM evaluations of defects generated during SiGe-on-insulator virtual substrate fabrication: Temperature ramping process

    International Nuclear Information System (INIS)

    Wang, D.; Ii, S.; Ikeda, K.; Nakashima, H.; Matsumoto, K.; Nakamae, M.; Nakashima, H.

    2006-01-01

    Crystal qualities were evaluated by photoluminescence (PL) and transmission electron microscopy (TEM) for cap-Si/SiGe/Si-on-insulater (SOI) structure, which is the typical structure for SiGe-on-insulator virtual substrate fabrication using the Ge condensation by dry oxidation. The thicknesses of cap-Si, SOI and BOX layers are 10, 70, and 140 nm, respectively. We have three kinds of wafers with SiGe thicknesses of 74, 154 and 234 nm. All of the wafers were heated from 200 deg.C to a target temperature (T t ) in the range of 820-1200 deg. C with a ramping rate of 5 deg. C/min, and maintained at T t for 10 min. The air in the furnace was a mixture of O 2 and N 2 . The PL measurements were carried out using a 325 nm UV line of a continuous-wave HeCd laser. Free exciton peaks were clearly observed for the as-grown wafers and decreased with an increase in the annealing temperature. For the selected wafers, cross-sectional and plan-view TEM measurements show clear generation and variation of dislocations at the interface of SiGe/SOI according to the T t . Defect-related PL signals were observed at around 0.82, 0.88, 0.95 and 1.0 eV, which also varied according to the T t and the SiGe thickness. They were identified to dislocation-related and stacking-fault-related defects by TEM

  14. SOI technology for power management in automotive and industrial applications

    Science.gov (United States)

    Stork, Johannes M. C.; Hosey, George P.

    2017-02-01

    Semiconductor on Insulator (SOI) technology offers an assortment of opportunities for chip manufacturers in the Power Management market. Recent advances in the automotive and industrial markets, along with emerging features, the increasing use of sensors, and the ever-expanding "Internet of Things" (IoT) are providing for continued growth in these markets while also driving more complex solutions. The potential benefits of SOI include the ability to place both high-voltage and low-voltage devices on a single chip, saving space and cost, simplifying designs and models, and improving performance, thereby cutting development costs and improving time to market. SOI also offers novel new approaches to long-standing technologies.

  15. Single-Event Upset and Scaling Trends in New Generation of the Commercial SOI PowerPC Microprocessors

    Science.gov (United States)

    Irom, Farokh; Farmanesh, Farhad; Kouba, Coy K.

    2006-01-01

    Single-event upset effects from heavy ions are measured for Motorola silicon-on-insulator (SOI) microprocessor with 90 nm feature sizes. The results are compared with previous results for SOI microprocessors with feature sizes of 130 and 180 nm. The cross section of the 90 nm SOI processors is smaller than results for 130 and 180 nm counterparts, but the threshold is about the same. The scaling of the cross section with reduction of feature size and core voltage for SOI microprocessors is discussed.

  16. Fully etched apodized grating coupler on the SOI platform with −058 dB coupling efficiency

    DEFF Research Database (Denmark)

    Ding, Yunhong; Peucheret, Christophe; Ou, Haiyan

    2014-01-01

    We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally investiga......We design and fabricate an ultrahigh coupling efficiency (CE) fully etched apodized grating coupler on the silicon- on-insulator (SOI) platform using subwavelength photonic crystals and bonded aluminum mirror. Fabrication error sensitivity andcoupling angle dependence are experimentally...

  17. Generation and confinement of mobile charges in buried oxide of SOI substrates; Generation et confinement de charges mobiles dans les oxydes enterres de substrats SOI

    Energy Technology Data Exchange (ETDEWEB)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A. [CEA Bruyeres-le-Chatel, DIF, 91 (France)

    1999-07-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO{sub 2} interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  18. A novel nanoscale SOI MOSFET by embedding undoped region for improving self-heating effect

    Science.gov (United States)

    Ghaffari, Majid; Orouji, Ali A.

    2018-06-01

    Because of the low thermal conductivity of the SiO2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (RTH), thermal capacitance (CTH), and SHE characteristic frequency (fTH). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device.

  19. Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

    Science.gov (United States)

    Zhao, Xiaofeng; Li, Dandan; Yu, Yang; Wen, Dianzhong

    2017-07-01

    Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors ({R}1, {R}2, {R}3 and {R}4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/°C, respectively. Through varying the ratio of the base region resistances {r}1 and {r}2, the TCS for the sensor with the compensation circuit is -127 ppm/°C. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor. Project supported by the National Natural Science Foundation of China (No. 61471159), the Natural Science Foundation of Heilongjiang Province (No. F201433), the University Nursing Program for Young Scholars with Creative Talents in Heilongjiang Province (No. 2015018), and the Special Funds for Science and Technology Innovation Talents of Harbin in China (No. 2016RAXXJ016).

  20. Effects of ultra-thin Si-fin body widths upon SOI PMOS FinFETs

    Science.gov (United States)

    Liaw, Yue-Gie; Chen, Chii-Wen; Liao, Wen-Shiang; Wang, Mu-Chun; Zou, Xuecheng

    2018-05-01

    Nano-node tri-gate FinFET devices have been developed after integrating a 14 Å nitrided gate oxide upon the silicon-on-insulator (SOI) wafers established on an advanced CMOS logic platform. These vertical double gate (FinFET) devices with ultra-thin silicon fin (Si-fin) widths ranging from 27 nm to 17 nm and gate length down to 30 nm have been successfully developed with a 193 nm scanner lithography tool. Combining the cobalt fully silicidation and the CESL strain technology beneficial for PMOS FinFETs was incorporated into this work. Detailed analyses of Id-Vg characteristics, threshold voltage (Vt), and drain-induced barrier lowering (DIBL) illustrate that the thinnest 17 nm Si-fin width FinFET exhibits the best gate controllability due to its better suppression of short channel effect (SCE). However, higher source/drain resistance (RSD), channel mobility degradation due to dry etch steps, or “current crowding effect” will slightly limit its transconductance (Gm) and drive current.

  1. Characterization of pixel sensor designed in 180 nm SOI CMOS technology

    Science.gov (United States)

    Benka, T.; Havranek, M.; Hejtmanek, M.; Jakovenko, J.; Janoska, Z.; Marcisovska, M.; Marcisovsky, M.; Neue, G.; Tomasek, L.; Vrba, V.

    2018-01-01

    A new type of X-ray imaging Monolithic Active Pixel Sensor (MAPS), X-CHIP-02, was developed using a 180 nm deep submicron Silicon On Insulator (SOI) CMOS commercial technology. Two pixel matrices were integrated into the prototype chip, which differ by the pixel pitch of 50 μm and 100 μm. The X-CHIP-02 contains several test structures, which are useful for characterization of individual blocks. The sensitive part of the pixel integrated in the handle wafer is one of the key structures designed for testing. The purpose of this structure is to determine the capacitance of the sensitive part (diode in the MAPS pixel). The measured capacitance is 2.9 fF for 50 μm pixel pitch and 4.8 fF for 100 μm pixel pitch at -100 V (default operational voltage). This structure was used to measure the IV characteristics of the sensitive diode. In this work, we report on a circuit designed for precise determination of sensor capacitance and IV characteristics of both pixel types with respect to X-ray irradiation. The motivation for measurement of the sensor capacitance was its importance for the design of front-end amplifier circuits. The design of pixel elements, as well as circuit simulation and laboratory measurement techniques are described. The experimental results are of great importance for further development of MAPS sensors in this technology.

  2. Performance study of double SOI image sensors

    Science.gov (United States)

    Miyoshi, T.; Arai, Y.; Fujita, Y.; Hamasaki, R.; Hara, K.; Ikegami, Y.; Kurachi, I.; Nishimura, R.; Ono, S.; Tauchi, K.; Tsuboyama, T.; Yamada, M.

    2018-02-01

    Double silicon-on-insulator (DSOI) sensors composed of two thin silicon layers and one thick silicon layer have been developed since 2011. The thick substrate consists of high resistivity silicon with p-n junctions while the thin layers are used as SOI-CMOS circuitry and as shielding to reduce the back-gate effect and crosstalk between the sensor and the circuitry. In 2014, a high-resolution integration-type pixel sensor, INTPIX8, was developed based on the DSOI concept. This device is fabricated using a Czochralski p-type (Cz-p) substrate in contrast to a single SOI (SSOI) device having a single thin silicon layer and a Float Zone p-type (FZ-p) substrate. In the present work, X-ray spectra of both DSOI and SSOI sensors were obtained using an Am-241 radiation source at four gain settings. The gain of the DSOI sensor was found to be approximately three times that of the SSOI device because the coupling capacitance is reduced by the DSOI structure. An X-ray imaging demonstration was also performed and high spatial resolution X-ray images were obtained.

  3. Launching of multi-project wafer runs in ePIXfab with micron-scale silicon rib waveguide technology

    Science.gov (United States)

    Aalto, Timo; Cherchi, Matteo; Harjanne, Mikko; Ylinen, Sami; Kapulainen, Markku; Vehmas, Tapani

    2014-03-01

    Silicon photonics is a rapidly growing R&D field where universities, institutes and companies are all involved and the business expectations for the next few years are high. One of the key enabling elements that led to the present success of silicon photonics is ePIXfab. It is a consortium of institutes that has together offered multi-project wafer (MPW) runs, packaging services, training, and feasibility studies. These services have significantly lowered the barrier of various research groups and companies to start developing silicon photonics. Until now the MPW services have been offered by the ePIXfab partners IMEC, CEA-Leti and IHP, which all use CMOS-type silicon photonics technology with a typical silicon-on-insulator (SOI) waveguide thickness of 220 nm. In November 2013 this MPW offering was expanded by the ePIXfab partner VTT that opened the access to its 3 μm SOI waveguide platform via ePIXfab MPW runs. This technology platform is complementary to the mainstream silicon photonics technology (220 nm) and it offers such benefits as very low losses, small polarization dependency, ultrabroadband operation and low starting costs

  4. Generation and confinement of mobile charges in buried oxide of SOI substrates

    International Nuclear Information System (INIS)

    Gruber, O.; Krawiec, S.; Musseau, O.; Paillet, Ph.; Courtot-Descharles, A.

    1999-01-01

    We analyze the mechanisms of generation and confinement of mobile protons resulting from hydrogen annealing of SOI buried oxides. This study of the mechanisms of generation and confinement of mobile protons in the buried oxide of SOI wafers emphasizes the importance of H+ diffusion in the oxide in the formation of a mobile charge. Under specific electric field conditions the irradiation of these devices results in a pinning of this mobile charge at the bottom Si-SiO 2 interface. Ab initio calculations are in progress to investigate the possible precursor defects in the oxide and detail the mechanism for mobile proton generation and confinement. (authors)

  5. FinFET and UTBB for RF SOI communication systems

    Science.gov (United States)

    Raskin, Jean-Pierre

    2016-11-01

    Performance of RF integrated circuit (IC) is directly linked to the analog and high frequency characteristics of the transistors, the quality of the back-end of line process as well as the electromagnetic properties of the substrate. Thanks to the introduction of the trap-rich high-resistivity Silicon-on-Insulator (SOI) substrate on the market, the ICs requirements in term of linearity are fulfilled. Today partially depleted SOI MOSFET is the mainstream technology for RF SOI systems. Future generations of mobile communication systems will require transistors with better high frequency performance at lower power consumption. The advanced MOS transistors in competition are FinFET and Ultra Thin Body and Buried oxide (UTBB) SOI MOSFETs. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.

  6. A high voltage SOI pLDMOS with a partial interface equipotential floating buried layer

    International Nuclear Information System (INIS)

    Wu Lijuan; Zhang Wentong; Zhang Bo; Li Zhaoji

    2013-01-01

    A novel silicon-on-insulator (SOI) high-voltage pLDMOS is presented with a partial interface equipotential floating buried layer (FBL) and its analytical model is analyzed in this paper. The surface heavily doped p-top layers, interface floating buried N + /P + layers, and three-step field plates are designed carefully in the FBL SOI pLDMOS to optimize the electric field distribution of the drift region and reduce the specific resistance. On the condition of ESIMOX (epoxy separated by implanted oxygen), it has been shown that the breakdown voltage of the FBL SOI pLDMOS is increased from −232 V of the conventional SOI to −425 V and the specific resistance R on,sp is reduced from 0.88 to 0.2424 Ω·cm 2 . (semiconductor devices)

  7. A novel SOI pressure sensor for high temperature application

    International Nuclear Information System (INIS)

    Li Sainan; Liang Ting; Wang Wei; Hong Yingping; Zheng Tingli; Xiong Jijun

    2015-01-01

    The silicon on insulator (SOI) high temperature pressure sensor is a novel pressure sensor with high-performance and high-quality. A structure of a SOI high-temperature pressure sensor is presented in this paper. The key factors including doping concentration and power are analyzed. The process of the sensor is designed with the critical process parameters set appropriately. The test result at room temperature and high temperature shows that nonlinear error below is 0.1%, and hysteresis is less than 0.5%. High temperature measuring results show that the sensor can be used for from room temperature to 350 °C in harsh environments. It offers a reference for the development of high temperature piezoresistive pressure sensors. (semiconductor devices)

  8. Ultra compact triplexing filters based on SOI nanowire AWGs

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei, E-mail: junming@red.semi.ac.cn [State Key Laboratory on Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2011-04-15

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  9. Ultra compact triplexing filters based on SOI nanowire AWGs

    International Nuclear Information System (INIS)

    Zhang Jiashun; An Junming; Zhao Lei; Song Shijiao; Wang Liangliang; Li Jianguang; Wang Hongjie; Wu Yuanda; Hu Xiongwei

    2011-01-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion. (semiconductor devices)

  10. Ultra compact triplexing filters based on SOI nanowire AWGs

    Science.gov (United States)

    Jiashun, Zhang; Junming, An; Lei, Zhao; Shijiao, Song; Liangliang, Wang; Jianguang, Li; Hongjie, Wang; Yuanda, Wu; Xiongwei, Hu

    2011-04-01

    An ultra compact triplexing filter was designed based on a silicon on insulator (SOI) nanowire arrayed waveguide grating (AWG) for fiber-to-the-home FTTH. The simulation results revealed that the design performed well in the sense of having a good triplexing function. The designed SOI nanowire AWGs were fabricated using ultraviolet lithography and induced coupler plasma etching. The experimental results showed that the crosstalk was less than -15 dB, and the 3 dB-bandwidth was 11.04 nm. The peak wavelength output from ports a, c, and b were 1455, 1510 and 1300 nm, respectively, which deviated from our original expectations. The deviation of the wavelength is mainly caused by 45 nm width deviation of the arrayed waveguides during the course of the fabrication process and partly caused by material dispersion.

  11. Silicon-on-Insulator Nanowire Based Optical Waveguide Biosensors

    International Nuclear Information System (INIS)

    Li, Mingyu; Liu, Yong; Chen, Yangqing; He, Jian-Jun

    2016-01-01

    Optical waveguide biosensors based on silicon-on-insulator (SOI) nanowire have been developed for label free molecular detection. This paper reviews our work on the design, fabrication and measurement of SOI nanowire based high-sensitivity biosensors employing Vernier effect. Biosensing experiments using cascaded double-ring sensor and Mach-Zehnder- ring sensor integrated with microfluidic channels are demonstrated (paper)

  12. LORINE: Neutron emission Locator by SOI detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hamrita, H.; Kondrasovs, V.; Borbotte, J. M.; Normand, S. [CEA, LIST, Laboratoire Capteurs et Architectures Electronique, F-91191 Gif-sur-Yvette Cedex (France); Saurel, N. [CEA, DAM, VALDUC, F-21120 Is sur Tille (France)

    2009-07-01

    The aim of this work is to develop a fast Neutron Emission Locator based on silicon on Insulator detector (LORINE). This locator can be used in the presence of significant flux of gamma radiation. LORINE was developed to locate areas containing a significant amount of actinide during the dismantling operations of equipment. From the results obtained in laboratory, we have proposed the prototype of neutron emission locator as follows: the developed design consists of 5 SOI (Silicon-on-insulator) detectors (1*1 cm{sup 2}) with their charge preamplifiers and their respective converters. All are installed on 5 faces of a boron polyethylene cube (5*5*5 cm{sup 3}). This cube plays the role of neutron shielding between the several detectors. The design must be so compact for use in glove boxes. An electronic card based on micro-controller has been made to control sensors and to send the necessary information to the computer. Location of fast neutron sources does not yet exist in a so compact design and it can be operated in the presence of very important gamma radiation flux

  13. The effect of gate length on SOI-MOSFETS operation | Baedi ...

    African Journals Online (AJOL)

    The effect of gate length on the operation of silicon-on-insulator (SOI) MOSFET structure with a layer of buried silicon oxide added to isolate the device body has been simulated. Three transistors with gate lengths of 100, 200 and 500 nm were simulated. Simulations showed that with a fixed channel length, when the gate ...

  14. Nonlinear Parasitic Capacitance Modelling of High Voltage Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    2016-01-01

    : off-state, sub-threshold region, and on-state in the linear region. A high voltage power MOSFET is designed in a partial Silicon on Insulator (SOI) process, with the bulk as a separate terminal. 3D plots and contour plots of the capacitances versus bias voltages for the transistor summarize...

  15. Design and fabrication process of silicon micro-calorimeters on simple SOI technology for X-ray spectral imaging

    International Nuclear Information System (INIS)

    Aliane, A.; Agnese, P.; Pigot, C.; Sauvageot, J.-L.; Moro, F. de; Ribot, H.; Gasse, A.; Szeflinski, V.; Gobil, Y.

    2008-01-01

    Several successful development programs have been conducted on infra-red bolometer arrays at the 'Commissariat a l'Energie Atomique' (CEA-LETI Grenoble) in collaboration with the CEA-SAp (Saclay); taking advantage of this background, we are now developing an X-ray spectro-imaging camera for next generation space astronomy missions, using silicon only technology. We have developed monolithic silicon micro-calorimeters based on implanted thermistors in an improved array that could be used for future space missions. The 8x8 array consists of a grid of 64 suspended pixels fabricated on a silicon on insulator (SOI) wafer. Each pixel of this detector array is made of a tantalum (Ta) absorber, which is bound by means of indium bump hybridization, to a silicon thermistor. The absorber array is bound to the thermistor array in a collective process. The fabrication process of our detector involves a combination of standard technologies and silicon bulk micro-machining techniques, based on deposition, photolithography and plasma etching steps. Finally, we present the results of measurements performed on these four primary building blocks that are required to create a detector array up to 32x32 pixels in size

  16. Research on SOI-based micro-resonator devices

    Science.gov (United States)

    Xiao, Xi; Xu, Haihua; Hu, Yingtao; Zhou, Liang; Xiong, Kang; Li, Zhiyong; Li, Yuntao; Fan, Zhongchao; Han, Weihua; Yu, Yude; Yu, Jinzhong

    2010-10-01

    SOI (silicon-on-insulator)-based micro-resonator is the key building block of silicon photonics, which is considered as a promising solution to alleviate the bandwidth bottleneck of on-chip interconnects. Silicon-based sub-micron waveguide, microring and microdisk devices are investigated in Institute of Semiconductors, Chinese Academy of Sciences. The main progress in recent years is presented in this talk, such as high Q factor single mode microdisk filters, compact thirdorder microring filters with the through/drop port extinctions to be ~ 30/40 dB, fast microring electro-optical switches with the switch time of 10 Gbit/s high speed microring modulators.

  17. Thin NbN film structures on SOI for SNSPD

    Energy Technology Data Exchange (ETDEWEB)

    Il' in, Konstantin; Kurz, Stephan; Henrich, Dagmar; Hofherr, Matthias; Siegel, Michael [IMS, KIT, Karlsruhe (Germany); Semenov, Alexei; Huebers, Heinz-Wilhelm [DLR, Berlin (Germany)

    2012-07-01

    Superconducting Nanowire Single-Photon Detectors (SNSPD) made from ultra-thin NbN films on sapphire demonstrate almost 100% intrinsic detection efficiency (DE). However the system DE values is less than 10% mostly limited by a very low absorptance of NbN films thinner than 5 nm. Integration of SNSPD in Si photonic circuit is a promising way to overcome this problem. We present results on optimization of technology of thin NbN film nanostructures on SOI (Silicon on Insulator) substrate used in Si photonics technology. Superconducting and normal state properties of these structures important for SNSPD development are presented and discussed.

  18. A MEMS SOI-based piezoresistive fluid flow sensor

    Science.gov (United States)

    Tian, B.; Li, H. F.; Yang, H.; Song, D. L.; Bai, X. W.; Zhao, Y. L.

    2018-02-01

    In this paper, a SOI (silicon-on-insulator)-based piezoresistive fluid flow sensor is presented; the presented flow sensor mainly consists of a nylon sensing head, stainless steel cantilever beam, SOI sensor chip, printed circuit board, half-cylinder gasket, and stainless steel shell. The working principle of the sensor and some detailed contrastive analysis about the sensor structure were introduced since the nylon sensing head and stainless steel cantilever beam have distinct influence on the sensor performance; the structure of nylon sensing head and stainless steel cantilever beam is also discussed. The SOI sensor chip was fabricated using micro-electromechanical systems technologies, such as reactive ion etching and low pressure chemical vapor deposition. The designed fluid sensor was packaged and tested; a calibration installation system was purposely designed for the sensor experiment. The testing results indicated that the output voltage of the sensor is proportional to the square of the fluid flow velocity, which is coincident with the theoretical derivation. The tested sensitivity of the sensor is 3.91 × 10-4 V ms2/kg.

  19. Fabrication of free standing LiNbO3 single crystal micro-platelets and their integration to Si-on-insulator platforms

    International Nuclear Information System (INIS)

    Lee, Yoo Seung; Lee, Sang-Shin; Lee, Wan-Gyu; Steier, William H.

    2011-01-01

    Free standing single crystal LiNbO 3 micro-platelets (mm long and 1 μm thick) have been obtained from a z-cut LiNbO 3 wafer by ion implantation and thermal treatment. X-ray diffraction measurement has proved that they have a single crystal structure. Their surface roughness and film quality have been investigated by atomic force microscope and field emission scanning electron microscope. These micro-platelets are transferable and bondable to other materials which require material properties of LiNbO 3 . They have been transferred, positioned and bonded to SiO 2 /LiNbO 3 , SiO 2 /Si, and Si-on-insulator (SOI: Si/SiO 2 /Si) by direct bonding method with optimum annealing conditions. For SiO 2 /Si and SOI substrates, there were large thermal mismatch between LiNbO 3 and Si. They were, however, bonded at high temperature since these ultra thin micro-platelets were flexible and stretchable. Finally, to realize multifunctional SOI applications, a hybrid structure of LiNbO 3 film and Si waveguide has been demonstrated.

  20. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  1. HARM processing techniques for MEMS and MOEMS devices using bonded SOI substrates and DRIE

    Science.gov (United States)

    Gormley, Colin; Boyle, Anne; Srigengan, Viji; Blackstone, Scott C.

    2000-08-01

    Silicon-on-Insulator (SOI) MEMS devices (1) are rapidly gaining popularity in realizing numerous solutions for MEMS, especially in the optical and inertia application fields. BCO recently developed a DRIE trench etch, utilizing the Bosch process, and refill process for high voltage dielectric isolation integrated circuits on thick SOI substrates. In this paper we present our most recently developed DRIE processes for MEMS and MOEMS devices. These advanced etch techniques are initially described and their integration with silicon bonding demonstrated. This has enabled process flows that are currently being utilized to develop optical router and filter products for fiber optics telecommunications and high precision accelerometers.

  2. Towards Polarization Diversity on the SOI Platform With Simple Fabrication Process

    DEFF Research Database (Denmark)

    Ding, Yunhong; Liu, Liu; Peucheret, Christophe

    2011-01-01

    We present a polarization diversity circuit built on the silicon-on-insulator (SOI) platform, which can be fabricated by a simple process. The polarization diversity is based on two identical air-clad asymmetrical directional couplers, which simultaneously play the roles of polarization splitter...... and rotator. A silicon polarization diversity circuit with a single microring resonator is fabricated on the SOI platform. Only ${1-dB polarization-dependent loss is demonstrated. A significant improvement of the polarization dependence is obtained for 20-Gb/s nonreturn-to-zero differential phase-shift keying...

  3. Indium arsenide-on-SOI MOSFETs with extreme lattice mismatch

    Science.gov (United States)

    Wu, Bin

    Both molecular beam epitaxy (MBE) and metal organic chemical vapor deposition (MOCVD) have been used to explore the growth of InAs on Si. Despite 11.6% lattice mismatch, planar InAs structures have been observed by scanning electron microscopy (SEM) when nucleating using MBE on patterned submicron Si-on-insulator (SOI) islands. Planar structures of size as large as 500 x 500 nm 2 and lines of width 200 nm and length a few microns have been observed. MOCVD growth of InAs also generates single grain structures on Si islands when the size is reduced to 100 x 100 nm2. By choosing SOI as the growth template, selective growth is enabled by MOCVD. Post-growth pattern-then-anneal process, in which MOCVD InAs is deposited onto unpatterned SOI followed with patterning and annealing of InAs-on-Si structure, is found to change the relative lattice parameters of encapsulated 17/5 nm InAs/Si island. Observed from transmission electron diffraction (TED) patterns, the lattice mismatch of 17/5 nm InAs/Si island reduces from 11.2 to 4.2% after being annealed at 800°C for 30 minutes. High-k Al2O3 dielectrics have been deposited by both electron-beam-enabled physical vapor deposition (PVD) and atomic layer deposition (ALD). Films from both techniques show leakage currents on the order of 10-9A/cm2, at ˜1 MV/cm electric field, breakdown field > ˜6 MV/cm, and dielectric constant > 6, comparable to those of reported ALD prior arts by Groner. The first MOSFETs with extreme lattice mismatch InAs-on-SOI channels using PVD Al2O3 as the gate dielectric are characterized. Channel recess was used to improve the gate control of the drain current.

  4. Comparative study of SOI/Si hybrid substrates fabricated using high-dose and low-dose oxygen implantation

    International Nuclear Information System (INIS)

    Dong Yemin; Chen Meng; Chen Jing; Wang Xiang; Wang Xi

    2004-01-01

    Hybrid substrates comprising both silicon-on-insulator (SOI) and bulk Si regions have been fabricated using the technique of patterned separation by implantation of oxygen (SIMOX) with high-dose (1.5 x 10 18 cm -2 ) and low-dose ((1.5-3.5) x 10 17 cm -2 ) oxygen ions, respectively. Cross-sectional transmission electron microscopy (XTEM) was employed to examine the microstructures of the resulting materials. Experimental results indicate that the SOI/Si hybrid substrate fabricated using high-dose SIMOX is of inferior quality with very large surface height step and heavily damaged transitions between the SOI and bulk regions. However, the quality of the SOI/Si hybrid substrate is enhanced dramatically by reducing the implant dose. The defect density in transitions is reduced considerably. Moreover, the expected surface height difference does not exist and the surface is exceptionally flat. The possible mechanisms responsible for the improvements in quality are discussed

  5. Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Luo Jie-Xin; Chen Jing; Zhou Jian-Hua; Wu Qing-Qing; Chai Zhan; Yu Tao; Wang Xi

    2012-01-01

    The hysteresis effect in the output characteristics, originating from the floating body effect, has been measured in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs at different back-gate biases. I D hysteresis has been developed to clarify the hysteresis characteristics. The fabricated devices show the positive and negative peaks in the I D hysteresis. The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-μm PD SOI MOSFETs and does not vary monotonously with the back-gate bias. Based on the steady-state Shockley-Read-Hall (SRH) recombination theory, we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs. (condensed matter: structural, mechanical, and thermal properties)

  6. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  7. Improved operation of graded-channel SOI nMOSFETs down to liquid helium temperature

    Science.gov (United States)

    Pavanello, Marcelo Antonio; de Souza, Michelly; Ribeiro, Thales Augusto; Martino, João Antonio; Flandre, Denis

    2016-11-01

    This paper presents the operation of Graded-Channel (GC) Silicon-On-Insulator (SOI) nMOSFETs at low temperatures down to liquid helium temperature in comparison to standard uniformly doped transistors. Devices from two different technologies have been measured and show that the mobility increase rate with temperature for GC SOI transistors is similar to uniformly doped devices for temperatures down to 90 K. However, at liquid helium temperature the rate of mobility increase is larger in GC SOI than in standard devices because of the different mobility scattering mechanisms. The analog properties of GC SOI devices have been investigated down to 4.16 K and show that because of its better transconductance and output conductance, an intrinsic voltage gain improvement with temperature is also obtained for devices in the whole studied temperature range. GC devices are also capable of reducing the impact ionization due to the high electric field in the drain region, increasing the drain breakdown voltage of fully-depleted SOI MOSFETs at any studied temperature and the kink voltage at 4.16 K.

  8. A 680 V LDMOS on a thin SOI with an improved field oxide structure and dual field plate

    International Nuclear Information System (INIS)

    Wang Zhongjian; Cheng Xinhong; Xia Chao; Xu Dawei; Cao Duo; Song Zhaorui; Yu Yuehui; Shen Dashen

    2012-01-01

    A 680 V LDMOS on a thin SOI with an improved field oxide (FOX) and dual field plate was studied experimentally. The FOX structure was formed by an 'oxidation-etch-oxidation' process, which took much less time to form, and had a low protrusion profile. A polysilicon field plate extended to the FOX and a long metal field plate was used to improve the specific on-resistance. An optimized drift region implant for linear-gradient doping was adopted to achieve a uniform lateral electric field. Using a SimBond SOI wafer with a 1.5 μm top silicon and a 3 μm buried oxide layer, CMOS compatible SOI LDMOS processes are designed and implemented successfully. The off-state breakdown voltage reached 680 V, and the specific on-resistance was 8.2 Ω·mm 2 . (semiconductor devices)

  9. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  10. Evaluation of a High Temperature SOI Half-Bridge MOSFET Driver, Type CHT-HYPERION

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2010-01-01

    Silicon-On-Insulator (SOI) technology utilizes the addition of an insulation layer in its structure to reduce leakage currents and to minimize parasitic junctions. As a result, SOIbased devices exhibit reduced internal heating as compared to the conventional silicon devices, consume less power, and can withstand higher operating temperatures. In addition, SOI electronic integrated circuits display good tolerance to radiation by virtue of introducing barriers or lengthening the path for penetrating particles and/or providing a region for trapping incident ionization. The benefits of these parts make them suitable for use in deep space and planetary exploration missions where extreme temperatures and radiation are encountered. Although designed for high temperatures, very little data exist on the operation of SOI devices and circuits at cryogenic temperatures. In this work, the performance of a commercial-off-the-shelf (COTS) SOI half-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  11. Process optimization of a deep trench isolation structure for high voltage SOI devices

    International Nuclear Information System (INIS)

    Zhu Kuiying; Qian Qinsong; Zhu Jing; Sun Weifeng

    2010-01-01

    The process reasons for weak point formation of the deep trench on SOI wafers have been analyzed in detail. An optimized trench process is also proposed. It is found that there are two main reasons: one is over-etching laterally of the silicon on the surface of the buried oxide caused by a fringe effect; and the other is the slow growth rate of the isolation oxide in the concave silicon corner of the trench bottom. In order to improve the isolation performance of the deep trench, two feasible ways for optimizing the trench process are proposed. The improved process thickens the isolation oxide and rounds sharp silicon corners at their weak points, increasing the applied voltage by 15-20 V at the same leakage current. The proposed new trench isolation process has been verified in the foundry's 0.5-μm HV SOI technology. (semiconductor devices)

  12. A technique for simultaneously improving the product of cutoff frequency-breakdown voltage and thermal stability of SOI SiGe HBT

    Science.gov (United States)

    Fu, Qiang; Zhang, Wan-Rong; Jin, Dong-Yue; Zhao, Yan-Xiao; Wang, Xiao

    2016-12-01

    The product of the cutoff frequency and breakdown voltage (fT×BVCEO) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N+-buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of fT×BVCEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness (TBOX) on fT, BVCEO, and the FOM of fT×BVCEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces fT, slightly increases BVCEO to some extent, but ultimately degrades the FOM of fT×BVCEO. Although the fT, BVCEO, and the FOM of fT×BVCEO can be improved by increasing SOI insulator SiO2 layer thickness TBOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick TBOX, a thin N+-buried layer is introduced into collector region to not only improve the FOM of fT×BVCEO, but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N+-buried layer in collector region is investigated in detail. The result show that the FOM of fT×BVCEO is improved and the device temperature decreases as the N+-buried layer shifts toward SOI substrate insulation layer. The approach to introducing a thin N+-buried layer

  13. A technique for simultaneously improving the product of cutoff frequency–breakdown voltage and thermal stability of SOI SiGe HBT

    International Nuclear Information System (INIS)

    Fu Qiang; Zhang Wan-Rong; Jin Dong-Yue; Zhao Yan-Xiao; Wang Xiao

    2016-01-01

    The product of the cutoff frequency and breakdown voltage ( f T ×BV CEO ) is an important figure of merit (FOM) to characterize overall performance of heterojunction bipolar transistor (HBT). In this paper, an approach to introducing a thin N + -buried layer into N collector region in silicon-on-insulator (SOI) SiGe HBT to simultaneously improve the FOM of f T ×BV CEO and thermal stability is presented by using two-dimensional (2D) numerical simulation through SILVACO device simulator. Firstly, in order to show some disadvantages of the introduction of SOI structure, the effects of SOI insulation layer thickness ( T BOX ) on f T , BV CEO , and the FOM of f T ×BV CEO are presented. The introduction of SOI structure remarkably reduces the electron concentration in collector region near SOI substrate insulation layer, obviously reduces f T , slightly increases BV CEO to some extent, but ultimately degrades the FOM of f T ×BV CEO . Although the f T , BV CEO , and the FOM of f T ×BV CEO can be improved by increasing SOI insulator SiO 2 layer thickness T BOX in SOI structure, the device temperature and collector current are increased due to lower thermal conductivity of SiO 2 layer, as a result, the self-heating effect of the device is enhanced, and the thermal stability of the device is degraded. Secondly, in order to alleviate the foregoing problem of low electron concentration in collector region near SOI insulation layer and the thermal stability resulting from thick T BOX , a thin N + -buried layer is introduced into collector region to not only improve the FOM of f T ×BV CEO , but also weaken the self-heating effect of the device, thus improving the thermal stability of the device. Furthermore, the effect of the location of the thin N + -buried layer in collector region is investigated in detail. The result show that the FOM of f T ×BV CEO is improved and the device temperature decreases as the N + -buried layer shifts toward SOI substrate insulation layer

  14. Output-Conductance Transition-Free Method for Improving Radio-Frequency Linearity of SOI MOSFET Circuits

    Directory of Open Access Journals (Sweden)

    A. Daghighi

    2013-09-01

    Full Text Available In this article, a novel concept is introduced to improve the radio frequency (RF linearity of partially-depleted (PD silicon-on-insulator (SOI MOSFET circuits. The transition due to the non-zero body resistance (RBody in output conductance of PD SOI devices leads to linearity degradation. A relation for RBody is defined to eliminate the transition and a method to obtain transition-free circuit is shown. 3-D Simulations of various body-contacted devices are carried out to extract the transition-free body resistances. To identify the output conductance transition-free concept and its application to RF circuits, a 2.4 GHz low noise amplifier (LNA is analyzed. Mixed mode device-circuit analysis is carried out to simultaneously solve device transport equations and circuit spice models. FFT calculations are performed on the output signal to compute harmonic distortion figures. Comparing the conventional body-contacted and transition-free SOI LNAs, third harmonic distortion (HD3 and total harmonic distortion (THD are improved by 16% and 24%, respectively. Two-tone test is used to analyze third order intermodulation distortions. OIP3 is improved in transition-free SOI LNA by 17% comparing with the conventional body-contacted SOI LNA. These results show the possibility of application of transition-free design concept to improve linearity of RF SOI MOSFET circuits.

  15. A Novel Non-Destructive Silicon-on-Insulator Nonvolatile Memory - LDRD 99-0750 Final Report

    Energy Technology Data Exchange (ETDEWEB)

    DRAPER,BRUCE L.; FLEETWOOD,D. M.; MEISENHEIMER,TIMOTHY L.; MURRAY,JAMES R.; SCHWANK,JAMES R.; SHANEYFELT,MARTY R.; SMITH,PAUL M.; VANHEUSDEN,KAREL J.; WARREN,WILLIAM L.

    1999-11-01

    Defects in silicon-on-insulator (SOI) buried oxides are normally considered deleterious to device operation. Similarly, exposing devices to hydrogen at elevated temperatures often can lead to radiation-induced charge buildup. However, in this work, we take advantage of as-processed defects in SOI buried oxides and moderate temperature hydrogen anneals to generate mobile protons in the buried oxide to form the basis of a ''protonic'' nonvolatile memory. Capacitors and fully-processed transistors were fabricated. SOI buried oxides are exposed to hydrogen at moderate temperatures using a variety of anneal conditions to optimize the density of mobile protons. A fast ramp cool down anneal was found to yield the maximum number of mobile protons. Unfortunately, we were unable to obtain uniform mobile proton concentrations across a wafer. Capacitors were irradiated to investigate the potential use of protonic memories for space and weapon applications. Irradiating under a negative top-gate bias or with no applied bias was observed to cause little degradation in the number of mobile protons. However, irradiating to a total dose of 100 krad(SiO{sub 2}) under a positive top-gate bias caused approximately a 100% reduction in the number of mobile protons. Cycling capacitors up to 10{sup 4} cycles had little effect on the switching characteristics. No change in the retention characteristics were observed for times up to 3 x 10{sup 4} s for capacitors stored unbiased at 200 C. These results show the proof-of-concept for a protonic nonvolatile memory. Two memory architectures are proposed for a protonic non-destructive, nonvolatile memory.

  16. Growth and characterization of InP/GaAs on SOI by MOCVD

    International Nuclear Information System (INIS)

    Karam, N.H.; Haven, V.; Vernon, S.M.; Namavar, F.; El-Masry, N.; Haegel, N.; Al-Jassin, M.M.

    1990-01-01

    This paper reports that epitaxial InP films have been successfully deposited on GaAs coated silicon wafers with a buried oxide for the first time by MOCVD. The SOI wafers were prepared using the Separation by Implantation of Oxygen (SIMOX) process. The quality of InP on SIMOX is comparable to the best of InP on Si deposited in the same reactor. Preliminary results on defect reduction techniques such as Thermal Cycle Growth (TCG) show an order of magnitude increase in the photoluminescence intensity and a factor of five reduction in the defect density. TCG has been found more effective than Thermal Cycle Annealing (TCA) in improving the crystalline perfection and optical properties of the deposited films

  17. Space and military radiation effects in silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Schwank, J.R.

    1996-09-01

    Advantages in transient ionizing and single-event upset (SEU) radiation hardness of silicon-on-insulator (SOI) technology spurred much of its early development. Both of these advantages are a direct result of the reduced charge collection volume inherent to SOI technology. The fact that SOI transistor structures do not include parasitic n-p-n-p paths makes them immune to latchup. Even though considerable improvement in transient and single-event radiation hardness can be obtained by using SOI technology, there are some attributes of SOI devices and circuits that tend to limit their overall hardness. These attributes include the bipolar effect that can ultimately reduce the hardness of SOI ICs to SEU and transient ionizing radiation, and charge buildup in buried and sidewall oxides that can degrade the total-dose hardness of SOI devices. Nevertheless, high-performance SOI circuits can be fabricated that are hardened to both space and nuclear radiation environments, and radiation-hardened systems remain an active market for SOI devices. The effects of radiation on SOI MOS devices are reviewed

  18. Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

    2012-01-01

    Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

  19. An analysis of radiation effects on electronics and soi-mos devices as an alternative

    International Nuclear Information System (INIS)

    Ikraiam, F. A.

    2013-01-01

    The effects of radiation on semiconductors and electronic components are analyzed. The performance of such circuitry depends upon the reliability of electronic devices where electronic components will be unavoidably exposed to radiation. This exposure can be detrimental or even fatal to the expected function of the devices. Single event effects (SEE), in particular, which lead to sudden device or system failure and total dose effects can reduce the lifetime of electronic devices in such systems are discussed. Silicon-on-insulator (SOI) technology is introduced as an alternative for radiation-hardened devices. I-V Characteristics Curves for SOI-MOS devices subjected to a different total radiation doses are illustrated. In addition, properties of some semiconductor materials such as diamond, diamond-like carbon films, SiC, GaP, and AlGaN/GaN are compared with those of SOI devices. The recognition of the potential usefulness of SOI-MOS semiconductor materials for harsh environments is discussed. A summary of radiation effects, impacts and mitigation techniques is also presented. (authors)

  20. Total dose hardening of buried insulator in implanted silicon-on-insulator structures

    International Nuclear Information System (INIS)

    Mao, B.Y.; Chen, C.E.; Pollack, G.; Hughes, H.L.; Davis, G.E.

    1987-01-01

    Total dose characteristics of the buried insulator in implanted silicon-on-insulator (SOI) substrates have been studied using MOS transistors. The threshold voltage shift of the parasitic back channel transistor, which is controlled by charge trapping in the buried insulator, is reduced by lowering the oxygen dose as well as by an additional nitrogen implant, without degrading the front channel transistor characteristics. The improvements in the radiation characteristics of the buried insulator are attributed to the decrease in the buried oxide thickness or to the presence of the interfacial oxynitride layer formed by the oxygen and nitrogen implants

  1. Development of a pixel sensor with fine space-time resolution based on SOI technology for the ILC vertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Ono, Shun, E-mail: s-ono@champ.hep.sci.osaka-u.ac.jp [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Togawa, Manabu; Tsuji, Ryoji; Mori, Teppei [Osaka University, 1-1 Machikaneyama, Toyonaka (Japan); Yamada, Miho; Arai, Yasuo; Tsuboyama, Toru; Hanagaki, Kazunori [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org. (KEK), 1-1 Oho, Tsukuba (Japan)

    2017-02-11

    We have been developing a new monolithic pixel sensor with silicon-on-insulator (SOI) technology for the International Linear Collider (ILC) vertex detector system. The SOI monolithic pixel detector is realized using standard CMOS circuits fabricated on a fully depleted sensor layer. The new SOI sensor SOFIST can store both the position and timing information of charged particles in each 20×20 μm{sup 2} pixel. The position resolution is further improved by the position weighted with the charges spread to multiple pixels. The pixel also records the hit timing with an embedded time-stamp circuit. The sensor chip has column-parallel analog-to-digital conversion (ADC) circuits and zero-suppression logic for high-speed data readout. We are designing and evaluating some prototype sensor chips for optimizing and minimizing the pixel circuit.

  2. A 2D simulation study and characterization of a novel vertical SOI MOSFET with a smart source/body tie

    International Nuclear Information System (INIS)

    Lin, Jyi-Tsong; Lee, Tai-Yi; Lin, Kao-Cheng

    2008-01-01

    A novel vertical silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) with a smart source/body contact, SSBVMOS, is presented here for the first time. 2D simulations reveal that the SSBVMOS reduces self-heating effects, with the lattice temperature reduced by 14% and the hole temperature reduced by 25%. The SSBVMOS also eliminates the floating body effect, something that other SOI vertical MOSFETs are unable to accomplish, regardless of the thickness of the thin film. The SSBVMOS is further found to have a better drain-induced barrier lowering and subthreshold swing than either a conventional vertical MOSFET or an SOI vertical MOSFET. Moreover, these results are achieved using typical pillar heights and buried oxide thicknesses. Should future technological advances allow for lower pillars or thinner buried oxides, the SSBVMOS performance would further increase

  3. Electron mobility in the inversion layers of fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Zaitseva, E. G., E-mail: ZaytsevaElza@yandex.ru; Naumova, O. V.; Fomin, B. I. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2017-04-15

    The dependences of the electron mobility μ{sub eff} in the inversion layers of fully depleted double–gate silicon-on-insulator (SOI) metal–oxide–semiconductor (MOS) transistors on the density N{sub e} of induced charge carriers and temperature T are investigated at different states of the SOI film (inversion–accumulation) from the side of one of the gates. It is shown that at a high density of induced charge carriers of N{sub e} > 6 × 10{sup 12} cm{sup –2} the μeff(T) dependences allow the components of mobility μ{sub eff} that are related to scattering at surface phonons and from the film/insulator surface roughness to be distinguished. The μ{sub eff}(N{sub e}) dependences can be approximated by the power functions μ{sub eff}(N{sub e}) ∝ N{sub e}{sup −n}. The exponents n in the dependences and the dominant mechanisms of scattering of electrons induced near the interface between the SOI film and buried oxide are determined for different N{sub e} ranges and film states from the surface side.

  4. Characterization of ultrathin SOI film and application to short channel MOSFETs.

    Science.gov (United States)

    Tang, Xiaohui; Reckinger, Nicolas; Larrieu, Guilhem; Dubois, Emmanuel; Flandre, Denis; Raskin, Jean-Pierre; Nysten, Bernard; Jonas, Alain M; Bayot, Vincent

    2008-04-23

    In this study, a very dilute solution (NH(4)OH:H(2)O(2):H(2)O 1:8:64 mixture) was employed to reduce the thickness of commercially available SOI wafers down to 3 nm. The etch rate is precisely controlled at 0.11 Å s(-1) based on the self-limited etching speed of the solution. The thickness uniformity of the thin film, evaluated by spectroscopic ellipsometry and by high-resolution x-ray reflectivity, remains constant through the thinning process. Moreover, the film roughness, analyzed by atomic force microscopy, slightly improves during the thinning process. The residual stress in the thin film is much smaller than that obtained by sacrificial oxidation. Mobility, measured by means of a bridge-type Hall bar on 15 nm film, is not significantly reduced compared to the value of bulk silicon. Finally, the thinned SOI wafers were used to fabricate Schottky-barrier metal-oxide-semiconductor field-effect transistors with a gate length down to 30 nm, featuring state-of-the-art current drive performance.

  5. BUSFET -- A radiation-hardened SOI transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, the authors propose a partially-depleted SOI transistor structure for mitigating the effects of trapped charge in the buried oxide on radiation hardness. They call this structure the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU or dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration, and the depth of the source. 3-D simulations show that for a body doping concentration of 10 18 cm -3 , a drain bias of 3 V, and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3 x 10 17 cm -3 , a thicker silicon film (300 nm) must be used

  6. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  7. Influence of edge effects on single event upset susceptibility of SOI SRAMs

    International Nuclear Information System (INIS)

    Gu, Song; Liu, Jie; Zhao, Fazhan; Zhang, Zhangang; Bi, Jinshun; Geng, Chao; Hou, Mingdong; Liu, Gang; Liu, Tianqi; Xi, Kai

    2015-01-01

    An experimental investigation of the single event upset (SEU) susceptibility for heavy ions at tilted incidence was performed. The differences of SEU cross-sections between tilted incidence and normal incidence at equivalent effective linear energy transfer were 21% and 57% for the silicon-on-insulator (SOI) static random access memories (SRAMs) of 0.5 μm and 0.18 μm feature size, respectively. The difference of SEU cross-section raised dramatically with increasing tilt angle for SOI SRAM of deep-submicron technology. The result of CRÈME-MC simulation for tilted irradiation of the sensitive volume indicates that the energy deposition spectrum has a substantial tail extending into the low energy region. The experimental results show that the influence of edge effects on SEU susceptibility cannot be ignored in particular with device scaling down

  8. Superconducting nanowire single-photon detectors (SNSPDs) on SOI for near-infrared range

    Energy Technology Data Exchange (ETDEWEB)

    Trojan, Philipp; Il' in, Konstantin; Henrich, Dagmar; Hofherr, Matthias; Doerner, Steffen; Siegel, Michael [Institut fuer Mikro- und Nanoelektronische Systeme (IMS), Karlsruher Institut fuer Technologie (KIT) (Germany); Semenov, Alexey [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Huebers, Heinz-Wilhelm [Institut fuer Planetenforschung, DLR, Berlin-Adlershof (Germany); Institut fuer Optik und Atomare Physik, Technische Universitaet Berlin (Germany)

    2013-07-01

    Superconducting nanowire single-photon detectors are promising devices for photon detectors with high count rates, low dark count rates and low dead times. At wavelengths beyond the visible range, the detection efficiency of today's SNSPDs drops significantly. Moreover, the low absorption in ultra-thin detector films is a limiting factor over the entire spectral range. Solving this problem requires approaches for an enhancement of the absorption range in feeding the light to the detector element. A possibility to obtain a better absorption is the use of multilayer substrate materials for photonic waveguide structures. We present results on development of superconducting nanowire single-photon detectors made from niobium nitride on silicon-on-insulator (SOI) multilayer substrates. Optical and superconducting properties of SNSPDs on SOI will be discussed and compared with the characteristics of detectors on common substrates.

  9. Room to high temperature measurements of flexible SOI FinFETs with sub-20-nm fins

    KAUST Repository

    Diab, Amer El Hajj

    2014-12-01

    We report the temperature dependence of the core electrical parameters and transport characteristics of a flexible version of fin field-effect transistor (FinFET) on silicon-on-insulator (SOI) with sub-20-nm wide fins and high-k/metal gate-stacks. For the first time, we characterize them from room to high temperature (150 °C) to show the impact of temperature variation on drain current, gate leakage current, and transconductance. Variation of extracted parameters, such as low-field mobility, subthreshold swing, threshold voltage, and ON-OFF current characteristics, is reported too. Direct comparison is made to a rigid version of the SOI FinFETs. The mobility degradation with temperature is mainly caused by phonon scattering mechanism. The overall excellent devices performance at high temperature after release is outlined proving the suitability of truly high-performance flexible inorganic electronics with such advanced architecture.

  10. New insights into fully-depleted SOI transistor response during total-dose irradiation

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Dodd, P.E.; Burns, J.A.; Keast, C.L.; Wyatt, P.W.

    1999-01-01

    In this paper, we present irradiation results on 2-fully depleted processes (HYSOI6, RKSOI) that show SOI (silicon on insulator) device response can be more complicated than originally suggested by others. The major difference between the 2 process versions is that the RKSOI process incorporates special techniques to minimize pre-irradiation parasitic leakage current from trench sidewalls. Transistors were irradiated at room temperature using 10 keV X-ray source. Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. It appears that the worst-case bias for HYPOI6 process is the bias that causes the largest increase in sidewall leakage. The RKSOI process shows a different response during irradiation, the transition response appears to be dominated by charge trapping in the buried oxide. These results have implications for hardness assurance testing. (A.C.)

  11. Anomalous radiation effects in fully depleted SOI MOSFETs fabricated on SIMOX

    Science.gov (United States)

    Li, Ying; Niu, Guofu; Cressler, J. D.; Patel, J.; Marshall, C. J.; Marshall, P. W.; Kim, H. S.; Reed, R. A.; Palmer, M. J.

    2001-12-01

    We investigate the proton tolerance of fully depleted silicon-on-insulator (SOI) MOSFETs with H-gate and regular-gate structural configurations. For the front-gate characteristics, the H-gate does not show the edge leakage observed in the regular-gate transistor. An anomalous kink in the back-gate linear I/sub D/-V/sub GS/ characteristics of the fully depleted SOI nFETs has been observed at high radiation doses. This kink is attributed to charged traps generated in the bandgap at the buried oxide/silicon film interface during irradiation. Extensive two-dimensional simulations with MEDICI were used to understand the physical origin of this kink. We also report unusual self-annealing effects in the devices when they are cooled to liquid nitrogen temperature.

  12. Electrical properties and radiation hardness of SOI systems with multilayer buried dielectric

    International Nuclear Information System (INIS)

    Barchuk, I.P.; Kilchitskaya, V.I.; Lysenko, V.S.

    1997-01-01

    In this work SOI structures with buried SiO 2 -Si 3 N 4 -SiO 2 layers have been fabricated by the ZMR-technique with the aim of improving the total dose radiation hardness of the buried dielectric layer. To optimize the fabrication process, buried layers were investigated by secondary ion mass spectrometry before and after the ZMR process, and the obtained results were compared with electrical measurements. It is shown that optimization of the preparation processes of the initial buried dielectric layers provides ZMR SOI structures with multilayer buried isolation, which are of high quality for both Si film interfaces. Particular attention is paid to the investigation of radiation-induced charge trapping in buried insulators. Buried isolation structures with a nitride layer exhibit significant reduction of radiation-induced positive charge as compared to classical buried SiO 2 layers produced by either the ZMR or the SIMOX technique

  13. A new partial SOI-LDMOSFET with a modified buried oxide layer for improving self-heating and breakdown voltage

    International Nuclear Information System (INIS)

    Jamali Mahabadi, S E; Orouji, Ali A; Keshavarzi, P; Moghadam, Hamid Amini

    2011-01-01

    In this paper, for the first time, we propose a partial silicon-on-insulator (P-SOI) lateral double-diffused metal-oxide-semiconductor-field-effect-transistor (LDMOSFET) with a modified buried layer in order to improve breakdown voltage (BV) and self-heating effects (SHEs). The main idea of this work is to control the electric field by shaping the buried layer. With two steps introduced in the buried layer, the electric field distribution is modified. Also a P-type window introduced makes the substrate share the vertical voltage drop, leading to a high vertical BV. Moreover, four interface electric field peaks are introduced by the buried P-layer, the Si window and two steps, which modulate the electric field in the SOI layer and the substrate. Hence, a more uniform electric field is obtained; consequently, a high BV is achieved. Furthermore, the Si window creates a conduction path between the active layer and substrate and alleviates the SHE. Two-dimensional simulations show that the BV of double step partial silicon on insulator is nearly 69% higher and alleviates SHEs 17% in comparison with its single step partial SOI counterpart and nearly 265% higher and alleviate SHEs 18% in comparison with its conventional SOI counterpart

  14. A Novel Fully Depleted Air AlN Silicon-on-Insulator Metal-Oxide-Semiconductor Field Effect Transistor

    International Nuclear Information System (INIS)

    Yuan, Yang; Yong, Gao; Peng-Liang, Gong

    2008-01-01

    A novel fully depleted air AlN silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOS-FET) is presented, which can eliminate the self-heating effect and solve the problem that the off-state current of SOI MOSFETs increases and the threshold voltage characteristics become worse when employing a high thermal conductivity material as a buried layer. The simulation results reveal that the lattice temperature in normal SOI devices is 75 K higher than the atmosphere temperature, while the lattice temperature is just 4K higher than the atmosphere temperature resulting in less severe self-heating effect in air AlN SOI MOSFETs and AlN SOI MOSFETs. The on-state current of air AlN SOI MOSFETs is similar to the AlN SOI structure, and improves 12.3% more than that of normal SOI MOSFETs. The off-state current of AlN SOI is 6.7 times of normal SOI MOSFETs, while the counterpart of air AlN SOI MOSFETs is lower than that of SOI MOSFETs by two orders of magnitude. The threshold voltage change of air AlN SOI MOSFETs with different drain voltage is much less than that of AlN SOI devices, when the drain voltage is biased at 0.8 V, this difference is 28mV, so the threshold voltage change induced by employing high thermal conductivity material is cured. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  15. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  16. Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications

    Science.gov (United States)

    Schwank, James R.; Shaneyfelt, Marty R.; Draper, Bruce L.; Dodd, Paul E.

    2001-01-01

    A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.

  17. Mapping the broadband polarization properties of linear 2D SOI photonic crystal waveguides

    DEFF Research Database (Denmark)

    Canning, John; Skivesen, Nina; Kristensen, Martin

    2007-01-01

    Both quasi-TE and TM polarisation spectra for a silicon- on-insulator (SOI) waveguide are recorded over (1100-1700) nm using a broadband supercontinuum source. By studying both the input and output polarisation eigenstates we observe narrowband resonant cross coupling near the lowest quasi-TE mode...... cut-off. We also observe relatively broadband mixing between the two eigenstates to generate a complete photonic bandgap. By careful analysis of the output polarisation state we report on an inherent non-reciprocity between quasi TE and TM fundamental mode cross coupling. The nature of polarisation...

  18. Intrinsic Nonlinearities and Layout Impacts of 100 V Integrated Power MOSFETs in Partial SOI Process

    DEFF Research Database (Denmark)

    Fan, Lin; Knott, Arnold; Jørgensen, Ivan Harald Holger

    Parasitic capacitances of power semiconductors are a part of the key design parameters of state-of-the-art very high frequency (VHF) power supplies. In this poster, four 100 V integrated power MOSFETs with different layout structures are designed, implemented, and analyzed in a 0.18 ȝm partial...... Silicon-on-Insulator (SOI) process with a die area 2.31 mm2.  A small-signal model of power MOSFETs is proposed to systematically analyze the nonlinear parasitic capacitances in different transistor states: off-state, sub-threshold region, and on-state in the linear region. 3D plots are used to summarize...

  19. A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology

    CERN Multimedia

    2002-01-01

    % RD-9 A Demonstrator Analog Signal Processing Circuit in a Radiation Hard SOI-CMOS Technology \\\\ \\\\Radiation hardened SOI-CMOS (Silicon-On-Insulator, Complementary Metal-Oxide- \\linebreak Semiconductor planar microelectronic circuit technology) was a likely candidate technology for mixed analog-digital signal processing electronics in experiments at the future high luminosity hadron colliders. We have studied the analog characteristics of circuit designs realized in the Thomson TCS radiation hard technologies HSOI3-HD. The feature size of this technology was 1.2 $\\mu$m. We have irradiated several devices up to 25~Mrad and 3.10$^{14}$ neutrons cm$^{-2}$. Gain, noise characteristics and speed have been measured. Irradiation introduces a degradation which in the interesting bandwidth of 0.01~MHz~-~1~MHz is less than 40\\%. \\\\ \\\\Some specific SOI phenomena have been studied in detail, like the influence on the noise spectrum of series resistence in the thin silicon film that constitutes the body of the transistor...

  20. Analyses of the radiation-caused characteristics change in SOI MOSFETs using field shield isolation

    International Nuclear Information System (INIS)

    Hirano, Yuuichi; Maeda, Shigeru; Fernandez, Warren; Iwamatsu, Toshiaki; Yamaguchi, Yasuo; Maegawa, Shigeto; Nishimura, Tadashi

    1999-01-01

    Reliability against radiation ia an important issue in silicon on insulator metal oxide semiconductor field effect transistors (SOI MOSFETs) used in satellites and nuclear power plants and so forth which are severely exposed to radiation. Radiation-caused characteristic change related to the isolation-edge in an irradiated environment was analyzed on SOI MOSFETs. Moreover short channel effects for an irradiated environment were investigated by simulations. It was revealed that the leakage current which was observed in local oxidation of silicon (LOCOS) isolated SOI MOSFETs was successfully suppressed by using field shield isolation. Simulated potential indicated that the potential rise at the LOCOS edge can not be seen in the case of field shield isolation edge which does not have physical isolation. Also it was found that the threshold voltage shift caused by radiation in short channel regime is severer than that in long regime channel. In transistors with a channel length of 0.18μm, a potential rise of the body region by radiation-induced trapped holes can be seen in comparison with that of 1.0μm. As a result, we must consider these effects for designing deep submicron devices used in an irradiated environment. (author)

  1. Density dependence of electron mobility in the accumulation mode for fully depleted SOI films

    Energy Technology Data Exchange (ETDEWEB)

    Naumova, O. V., E-mail: naumova@isp.nsc.ru; Zaitseva, E. G.; Fomin, B. I.; Ilnitsky, M. A.; Popov, V. P. [Russian Academy of Sciences, Rzhanov Institute of Semiconductor Physics, Siberian Branch (Russian Federation)

    2015-10-15

    The electron mobility µ{sub eff} in the accumulation mode is investigated for undepleted and fully depleted double-gate n{sup +}–n–n{sup +} silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistors (MOSFET). To determine the range of possible values of the mobility and the dominant scattering mechanisms in thin-film structures, it is proposed that the field dependence of the mobility µ{sub eff} be replaced with the dependence on the density N{sub e} of induced charge carriers. It is shown that the dependences µ{sub eff}(N{sub e}) can be approximated by the power functions µ{sub eff}(N{sub e}) ∝ N{sub e}{sup -n}, where the exponent n is determined by the chargecarrier scattering mechanism as in the mobility field dependence. The values of the exponent n in the dependences µ{sub eff}(N{sub e}) are determined when the SOI-film mode near one of its surfaces varies from inversion to accumulation. The obtained results are explained from the viewpoint of the electron-density redistribution over the SOI-film thickness and changes in the scattering mechanisms.

  2. Ultra-low specific on-resistance SOI double-gate trench-type MOSFET

    International Nuclear Information System (INIS)

    Lei Tianfei; Luo Xiaorong; Ge Rui; Chen Xi; Wang Yuangang; Yao Guoliang; Jiang Yongheng; Zhang Bo; Li Zhaoji

    2011-01-01

    An ultra-low specific on-resistance (R on,sp ) silicon-on-insulator (SOI) double-gate trench-type MOSFET (DG trench MOSFET) is proposed. The MOSFET features double gates and an oxide trench: the oxide trench is in the drift region, one trench gate is inset in the oxide trench and one trench gate is extended into the buried oxide. Firstly, the double gates reduce R on,sp by forming dual conduction channels. Secondly, the oxide trench not only folds the drift region, but also modulates the electric field, thereby reducing device pitch and increasing the breakdown voltage (BV). ABV of 93 V and a R on,sp of 51.8 mΩ·mm 2 is obtained for a DG trench MOSFET with a 3 μm half-cell pitch. Compared with a single-gate SOI MOSFET (SG MOSFET) and a single-gate SOI MOSFET with an oxide trench (SG trench MOSFET), the R on,sp of the DG trench MOSFET decreases by 63.3% and 33.8% at the same BV, respectively. (semiconductor devices)

  3. A low on-resistance SOI LDMOS using a trench gate and a recessed drain

    International Nuclear Information System (INIS)

    Ge Rui; Luo Xiaorong; Jiang Yongheng; Zhou Kun; Wang Pei; Wang Qi; Wang Yuangang; Zhang Bo; Li Zhaoji

    2012-01-01

    An integrable silicon-on-insulator (SOI) power lateral MOSFET with a trench gate and a recessed drain (TGRD MOSFET) is proposed to reduce the on-resistance. Both of the trench gate extended to the buried oxide (BOX) and the recessed drain reduce the specific on-resistance (R on,sp ) by widening the vertical conduction area and shortening the extra current path. The trench gate is extended as a field plate improves the electric field distribution. Breakdown voltage (BV) of 97 V and R on,sp of 0.985 mΩ·cm 2 (V GS = 5 V) are obtained for a TGRD MOSFET with 6.5 μm half-cell pitch. Compared with the trench gate SOI MOSFET (TG MOSFET) and the conventional MOSFET, R on,sp of the TGRD MOSFET decreases by 46% and 83% at the same BV, respectively. Compared with the SOI MOSFET with a trench gate and a trench drain (TGTD MOSFET), BV of the TGRD MOSFET increases by 37% at the same R on,sp . (semiconductor devices)

  4. Investigation of the stability of polysilicon layers in SOI-structures under irradiation by electrons and hard magnetic field influence

    Directory of Open Access Journals (Sweden)

    Khoverko Yu. N.

    2010-10-01

    Full Text Available The properties of recrystallized polysilicon on insulator layers of p-type conductive SOI-structures with different carrier concentration irradiated with high-energy electrons flow about 1017 сm–2 in temperature range 4,2—300 К and high magnetic fields were investigated. It was found that heavily doped laser recrystallized polysilicon on insulator layers show its radiation resistance under irradiation with high-energy electrons and magnetoresistance of such material remains quite low in magnetic field about 14 T does not exceed 1—2%. Such qulity can be applied in designing of microelectronic sensors of mechanical values operable in hard conditions of exploitation.

  5. Formation of SIMOX–SOI structure by high-temperature oxygen implantation

    International Nuclear Information System (INIS)

    Hoshino, Yasushi; Kamikawa, Tomohiro; Nakata, Jyoji

    2015-01-01

    We have performed oxygen ion implantation in silicon at very high substrate-temperatures (⩽1000 °C) for the purpose of forming silicon-on-insulator (SOI) structure. We have expected that the high-temperature implantation can effectively avoids ion-beam-induced damages in the SOI layer and simultaneously stabilizes the buried oxide (BOX) and SOI-Si layer. Such a high-temperature implantation makes it possible to reduce the post-implantation annealing temperature. In the present study, oxygen ions with 180 keV are incident on Si(0 0 1) substrates at various temperatures from room temperature (RT) up to 1000 °C. The ion-fluencies are in order of 10"1"7–10"1"8 ions/cm"2. Samples have been analyzed by atomic force microscope, Rutherford backscattering, and micro-Raman spectroscopy. It is found in the AFM analysis that the surface roughness of the samples implanted at 500 °C or below are significantly small with mean roughness of less than 1 nm, and gradually increased for the 800 °C-implanted sample. On the other hand, a lot of dents are observed for the 1000 °C-implanted sample. RBS analysis has revealed that stoichiometric SOI-Si and BOX-SiO_2 layers are formed by oxygen implantation at the substrate temperatures of RT, 500, and 800 °C. However, SiO_2-BOX layer has been desorbed during the implantation. Raman spectra shows that the ion-beam-induced damages are fairly suppressed by such a high-temperatures implantation.

  6. Bonding of Si wafers by surface activation method for the development of high efficiency high counting rate radiation detectors

    International Nuclear Information System (INIS)

    Kanno, Ikuo; Yamashita, Makoto; Onabe, Hideaki

    2006-01-01

    Si wafers with two different resistivities ranging over two orders of magnitude were bonded by the surface activation method. The resistivities of bonded Si wafers were measured as a function of annealing temperature. Using calculations based on a model, the interface resistivities of bonded Si wafers were estimated as a function of the measured resistivities of bonded Si wafers. With thermal treatment from 500degC to 900degC, all interfaces showed high resistivity, with behavior that was close to that of an insulator. Annealing at 1000degC decreased the interface resistivity and showed close to ideal bonding after thermal treatment at 1100degC. (author)

  7. Performance of an SOI Boot-Strapped Full-Bridge MOSFET Driver, Type CHT-FBDR, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems designed for use in deep space and planetary exploration missions are expected to encounter extreme temperatures and wide thermal swings. Silicon-based devices are limited in their wide-temperature capability and usually require extra measures, such as cooling or heating mechanisms, to provide adequate ambient temperature for proper operation. Silicon-On-Insulator (SOI) technology, on the other hand, lately has been gaining wide spread use in applications where high temperatures are encountered. Due to their inherent design, SOI-based integrated circuit chips are able to operate at temperatures higher than those of the silicon devices by virtue of reducing leakage currents, eliminating parasitic junctions, and limiting internal heating. In addition, SOI devices provide faster switching, consume less power, and offer improved radiation-tolerance. Very little data, however, exist on the performance of such devices and circuits under cryogenic temperatures. In this work, the performance of an SOI bootstrapped, full-bridge driver integrated circuit was evaluated under extreme temperatures and thermal cycling. The investigations were carried out to establish a baseline on the functionality and to determine suitability of this device for use in space exploration missions under extreme temperature conditions.

  8. Investigation of AWG demultiplexer based SOI for CWDM application

    Directory of Open Access Journals (Sweden)

    Juhari Nurjuliana

    2017-01-01

    Full Text Available 9-channel Arrayed Waveguide Grating (AWG demultiplexer for conventional and tapered structure were simulated using beam propagation method (BPM with channel spacing of 20 nm. The AWG demultiplexer was design using high refractive index (n~3.47 material namely silicon-on-insulator (SOI with rib waveguide structure. The characteristics of insertion loss, adjacent crosstalk and output spectrum response at central wavelength of 1.55 μm for both designs were compared and analyzed. The conventional AWG produced a minimum insertion loss of 6.64 dB whereas the tapered AWG design reduced the insertion loss by 2.66 dB. The lowest adjacent crosstalk value of -16.96 dB was obtained in the conventional AWG design and this was much smaller compared to the tapered AWG design where the lowest crosstalk value is -17.23 dB. Hence, a tapered AWG design significantly reduces the insertion loss but has a slightly higher adjacent crosstalk compared to the conventional AWG design. On the other hand, the output spectrum responses that are obtained from both designs were close to the Coarse Wavelength Division Multiplexing (CWDM wavelength grid.

  9. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-11-04

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

  10. An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications †

    Science.gov (United States)

    Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

    2016-01-01

    An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA–0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C–1.79 mV/°C in the range 20–300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(Vexcit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min)−0.1 in the tested range of 0–4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries. PMID:27827904

  11. A two dimensional analytical modeling of surface potential in triple metal gate (TMG) fully-depleted Recessed-Source/Drain (Re-S/D) SOI MOSFET

    Science.gov (United States)

    Priya, Anjali; Mishra, Ram Awadh

    2016-04-01

    In this paper, analytical modeling of surface potential is proposed for new Triple Metal Gate (TMG) fully depleted Recessed-Source/Dain Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The metal with the highest work function is arranged near the source region and the lowest one near the drain. Since Recessed-Source/Drain SOI MOSFET has higher drain current as compared to conventional SOI MOSFET due to large source and drain region. The surface potential model developed by 2D Poisson's equation is verified by comparison to the simulation result of 2-dimensional ATLAS simulator. The model is compared with DMG and SMG devices and analysed for different device parameters. The ratio of metal gate length is varied to optimize the result.

  12. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  13. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  14. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Dodd, P.E.; Draper, B.L.; Schwank, J.R.; Shaneyfelt, M.R.

    1999-01-01

    A partially-depleted SOI transistor structure has been designed that does not require the use of specially-processed hardened buried oxides for total-dose hardness and maintains the intrinsic SEU and dose rate hardness advantages of SOI technology

  15. A study of process-related electrical defects in SOI lateral bipolar transistors fabricated by ion implantation

    Science.gov (United States)

    Yau, J.-B.; Cai, J.; Hashemi, P.; Balakrishnan, K.; D'Emic, C.; Ning, T. H.

    2018-04-01

    We report a systematic study of process-related electrical defects in symmetric lateral NPN transistors on silicon-on-insulator (SOI) fabricated using ion implantation for all the doped regions. A primary objective of this study is to see if pipe defects (emitter-collector shorts caused by locally enhanced dopant diffusion) are a show stopper for such bipolar technology. Measurements of IC-VCE and Gummel currents in parallel-connected transistor chains as a function of post-fabrication rapid thermal anneal cycles allow several process-related electrical defects to be identified. They include defective emitter-base and collector-base diodes, pipe defects, and defects associated with a dopant-deficient region in an extrinsic base adjacent its intrinsic base. There is no evidence of pipe defects being a major concern in SOI lateral bipolar transistors.

  16. Nonuniformities of electrical resistivity in undoped 6H-SiC wafers

    International Nuclear Information System (INIS)

    Li, Q.; Polyakov, A.Y.; Skowronski, M.; Sanchez, E.K.; Loboda, M.J.; Fanton, M.A.; Bogart, T.; Gamble, R.D.

    2005-01-01

    Chemical elemental analysis, temperature-dependent Hall measurements, deep-level transient spectroscopy, and contactless resistivity mapping were performed on undoped semi-insulating (SI) and lightly nitrogen-doped conducting 6H-SiC crystals grown by physical vapor transport (PVT). Resistivity maps of commercial semi-insulating SiC wafers revealed resistivity variations across the wafers between one and two orders of magnitude. Two major types of variations were identified. First is the U-shape distribution with low resistivity in the center and high in the periphery of the wafer. The second type had an inverted U-shape distribution. Secondary-ion-mass spectrometry measurements of the distribution of nitrogen concentration along the growth axis and across the wafers sliced from different locations of lightly nitrogen-doped 6H-SiC boules were conducted. The measured nitrogen concentration gradually decreased along the growth direction and from the center to the periphery of the wafers. This change gives rise to the U-like distribution of resistivity in wafers of undoped SI-SiC. The concentrations of deep electron traps exhibited similar dependence. Compensation of nitrogen donors by these traps can result in the inverted U-like distribution of resistivity. Possible reasons for the observed nonuniformities include formation of a (0001) facet in PVT growth coupled with orientation-dependent nitrogen incorporation, systematic changes of the gas phase composition, and increase of the deposition temperature during boule growth

  17. Reduced nonlinearities in 100-nm high SOI waveguides

    Science.gov (United States)

    Lacava, C.; Marchetti, R.; Vitali, V.; Cristiani, I.; Giuliani, G.; Fournier, M.; Bernabe, S.; Minzioni, P.

    2016-03-01

    Here we show the results of an experimental analysis dedicated to investigate the impact of optical non linear effects, such as two-photon absorption (TPA), free-carrier absorption (FCA) and free-carrier dispersion (FCD), on the performance of integrated micro-resonator based filters for application in WDM telecommunication systems. The filters were fabricated using SOI (Silicon-on-Insulator) technology by CEA-Leti, in the frame of the FP7 Fabulous Project, which aims to develop low-cost and high-performance integrated optical devices to be used in new generation passive optical- networks (NG-PON2). Different designs were tested, including both ring-based structures and racetrack-based structures, with single-, double- or triple- resonator configuration, and using different waveguide cross-sections (from 500 x 200 nm to 825 x 100 nm). Measurements were carried out using an external cavity tunable laser source operating in the extended telecom bandwidth, using both continuous wave signals and 10 Gbit/s modulated signals. Results show that the use 100-nm high waveguide allows reducing the impact of non-linear losses, with respect to the standard waveguides, thus increasing by more than 3 dB the maximum amount of optical power that can be injected into the devices before causing significant non-linear effects. Measurements with OOK-modulated signals at 10 Gbit/s showed that TPA and FCA don't affect the back-to-back BER of the signal, even when long pseudo-random-bit-sequences (PRBS) are used, as the FCD-induced filter-detuning increases filter losses but "prevents" excessive signal degradation.

  18. Implant damage and redistribution of indium in indium-implanted thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Chen Peng; An Zhenghua; Zhu Ming; Fu, Ricky K.Y.; Chu, Paul K.; Montgomery, Neil; Biswas, Sukanta

    2004-01-01

    The indium implant damage and diffusion behavior in thin silicon-on-insulator (SOI) with a 200 nm top silicon layer were studied for different implantation energies and doses. Rutherford backscattering spectrometry in the channeling mode (RBS/C) was used to characterize the implant damage before and after annealing. Secondary ion mass spectrometry (SIMS) was used to study the indium transient enhanced diffusion (TED) behavior in the top Si layer of the SOI structure. An anomalous redistribution of indium after relatively high energy (200 keV) and dose (1 x 10 14 cm -2 ) implantation was observed in both bulk Si and SOI substrates. However, there exist differences in these two substrates that are attributable to the more predominant out-diffusion of indium as well as the influence of the buried oxide layer in the SOI structure

  19. Luminescence properties of ZnO layers grown on Si-on-insulator substrates

    International Nuclear Information System (INIS)

    Kumar, Bhupendra; Gong, Hao; Vicknesh, S.; Chua, S. J.; Tripathy, S.

    2006-01-01

    The authors report on the photoluminescence properties of polycrystalline ZnO thin films grown on compliant silicon-on-insulator (SOI) substrates by radio frequency magnetron sputtering. The ZnO thin films on SOI were characterized by micro-Raman and photoluminescence (PL) spectroscopy. The observation of E 2 high optical phonon mode near 438 cm -1 in the Raman spectra of the ZnO samples represents the wurtzite crystal structure. Apart from the near-band-edge free exciton (FX) transition around 3.35 eV at 77 K, the PL spectra of such ZnO films also showed a strong defect-induced violet emission peak in the range of 3.05-3.09 eV. Realization of such ZnO layers on SOI would be useful for heterointegration with SOI-based microelectronics and microelectromechanical systems

  20. Electrical characteristics of SiGe-base bipolar transistors on thin-film SOI substrates

    International Nuclear Information System (INIS)

    Liao, Shu-Hui; Chang, Shu-Tong

    2010-01-01

    This paper, based on two-dimensional simulations, provides a comprehensive analysis of the electrical characteristics of the Silicon germanium (SiGe)-base bipolar transistors on thin-film siliconon-insulator (SOI) substrates. The impact of the buried oxide thickness (T OX ), the emitter width (W E ), and the lateral distance between the edge of the intrinsic base and the reach-through region (L col ) on both the AC and DC device characteristics was analyzed in detail. Regarding the DC characteristics, the simulation results suggest that a thicker T OX gives a larger base-collector breakdown voltage (BV CEO ), whereas reducing the T OX leads to an enhanced maximum electric field at the B-C junction. As for the AC characteristics, cut-off frequency (f T ) increases slightly with increasing buried oxide thickness and finally saturates to a constant value when the buried oxide thickness is about 0.15 μm. The collector-substrate capacitance (C CS ) decreases with increasing buried oxide thickness while the maximum oscillation frequency (f max ) increases with increasing buried oxide thickness. Furthermore, the impact of self-heating effects in the device was analyzed in various areas. The thermal resistance as a function of the buried oxide thickness indicates that the thermal resistance of the SiGe-base bipolar transistor on a SOI substrate is slightly higher than that of a bulk SiGe-base bipolar transistor. The thermal resistance is reduced by ∼37.89% when the emitter width is increased by a factor of 5 for a fixed buried oxide thickness of 0.1 μm. All the results can be used to design and optimize SiGe-base bipolar transistors on SOI substrates with minimum thermal resistance to enhance device performance.

  1. Effect of nanoscale surface roughness on the bonding energy of direct-bonded silicon wafers

    Science.gov (United States)

    Miki, N.; Spearing, S. M.

    2003-11-01

    Direct wafer bonding of silicon wafers is a promising technology for manufacturing three-dimensional complex microelectromechanical systems as well as silicon-on-insulator substrates. Previous work has reported that the bond quality declines with increasing surface roughness, however, this relationship has not been quantified. This article explicitly correlates the bond quality, which is quantified by the apparent bonding energy, and the surface morphology via the bearing ratio, which describes the area of surface lying above a given depth. The apparent bonding energy is considered to be proportional to the real area of contact. The effective area of contact is defined as the area sufficiently close to contribute to the attractive force between the two bonding wafers. Experiments were conducted with silicon wafers whose surfaces were roughened by a buffered oxide etch solution (BOE, HF:NH4F=1:7) and/or a potassium hydroxide solution. The surface roughness was measured by atomic force microscopy. The wafers were direct bonded to polished "monitor" wafers following a standard RCA cleaning and the resulting bonding energy was measured by the crack-opening method. The experimental results revealed a clear correlation between the bonding energy and the bearing ratio. A bearing depth of ˜1.4 nm was found to be appropriate for the characterization of direct-bonded silicon at room temperature, which is consistent with the thickness of the water layer at the interface responsible for the hydrogen bonds that link the mating wafers.

  2. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  3. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  4. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    Science.gov (United States)

    Jie, Cui; Lei, Chen; Peng, Zhao; Xu, Niu; Yi, Liu

    2014-06-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than -45 dB isolation and maximum -103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator.

  5. A linear 180 nm SOI CMOS antenna switch module using integrated passive device filters for cellular applications

    International Nuclear Information System (INIS)

    Cui Jie; Chen Lei; Liu Yi; Zhao Peng; Niu Xu

    2014-01-01

    A broadband monolithic linear single pole, eight throw (SP8T) switch has been fabricated in 180 nm thin film silicon-on-insulator (SOI) CMOS technology with a quad-band GSM harmonic filter in integrated passive devices (IPD) technology, which is developed for cellular applications. The antenna switch module (ASM) features 1.2 dB insertion loss with filter on 2G bands and 0.4 dB insertion loss in 3G bands, less than −45 dB isolation and maximum −103 dB intermodulation distortion for mobile front ends by applying distributed architecture and adaptive supply voltage generator. (semiconductor integrated circuits)

  6. Development of an X-ray imaging system with SOI pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Nishimura, Ryutaro, E-mail: ryunishi@post.kek.jp [School of High Energy Accelerator Science, SOKENDAI (The Graduate University for Advanced Studies), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK-IPNS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan); Hirano, Keiichi; Kishimoto, Shunji; Hashimoto, Ryo [Institute of Materials Structure Science, High Energy Accelerator Research Organization (KEK-IMSS), Oho 1-1, Tsukuba, Ibaraki 305-0801 (Japan)

    2016-09-21

    An X-ray imaging system employing pixel sensors in silicon-on-insulator technology is currently under development. The system consists of an SOI pixel detector (INTPIX4) and a DAQ system based on a multi-purpose readout board (SEABAS2). To correct a bottleneck in the total throughput of the DAQ of the first prototype, parallel processing of the data taking and storing processes and a FIFO buffer were implemented for the new DAQ release. Due to these upgrades, the DAQ throughput was improved from 6 Hz (41 Mbps) to 90 Hz (613 Mbps). The first X-ray imaging system with the new DAQ software release was tested using 33.3 keV and 9.5 keV mono X-rays for three-dimensional computerized tomography. The results of these tests are presented. - Highlights: • The X-ray imaging system employing the SOI pixel sensor is currently under development. • The DAQ of the first prototype has the bottleneck in the total throughput. • The new DAQ release solve the bottleneck by parallel processing and FIFO buffer. • The new DAQ release was tested using 33.3 keV and 9.5 keV mono X-rays.

  7. Study of CMOS-SOI Integrated Temperature Sensing Circuits for On-Chip Temperature Monitoring.

    Science.gov (United States)

    Malits, Maria; Brouk, Igor; Nemirovsky, Yael

    2018-05-19

    This paper investigates the concepts, performance and limitations of temperature sensing circuits realized in complementary metal-oxide-semiconductor (CMOS) silicon on insulator (SOI) technology. It is shown that the MOSFET threshold voltage ( V t ) can be used to accurately measure the chip local temperature by using a V t extractor circuit. Furthermore, the circuit's performance is compared to standard circuits used to generate an accurate output current or voltage proportional to the absolute temperature, i.e., proportional-to-absolute temperature (PTAT), in terms of linearity, sensitivity, power consumption, speed, accuracy and calibration needs. It is shown that the V t extractor circuit is a better solution to determine the temperature of low power, analog and mixed-signal designs due to its accuracy, low power consumption and no need for calibration. The circuit has been designed using 1 µm partially depleted (PD) CMOS-SOI technology, and demonstrates a measurement inaccuracy of ±1.5 K across 300 K⁻500 K temperature range while consuming only 30 µW during operation.

  8. A low specific on-resistance SOI MOSFET with dual gates and a recessed drain

    International Nuclear Information System (INIS)

    Luo Xiao-Rong; Hu Gang-Yi; Zhang Zheng-Yuan; Luo Yin-Chun; Fan Ye; Wang Xiao-Wei; Fan Yuan-Hang; Cai Jin-Yong; Wang Pei; Zhou Kun

    2013-01-01

    A low specific on-resistance (R on,sp ) integrable silicon-on-insulator (SOI) metal-oxide semiconductor field-effect transistor (MOSFET) is proposed and investigated by simulation. The MOSFET features a recessed drain as well as dual gates, which consist of a planar gate and a trench gate extended to the buried oxide layer (BOX) (DGRD MOSFET). First, the dual gates form dual conduction channels, and the extended trench gate also acts as a field plate to improve the electric field distribution. Second, the combination of the trench gate and the recessed drain widens the vertical conduction area and shortens the current path. Third, the P-type top layer not only enhances the drift doping concentration but also modulates the surface electric field distributions. All of these sharply reduce R on,sp and maintain a high breakdown voltage (BV). The BV of 233 V and R on,sp of 4.151 mΩ·cm 2 (V GS = 15 V) are obtained for the DGRD MOSFET with 15-μm half-cell pitch. Compared with the trench gate SOI MOSFET and the conventional MOSFET, R on,sp of the DGRD MOSFET decreases by 36% and 33% with the same BV, respectively. The trench gate extended to the BOX synchronously acts as a dielectric isolation trench, simplifying the fabrication processes. (condensed matter: electronic structure, electrical, magnetic, and optical properties)

  9. Hybrid III-V/SOI Resonant Cavity Photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization.......A hybrid III-V/SOI resonant cavity photo detector has been demonstrated, which comprises an InP grating reflectorand a Si grating reflector. It can selectively detects an incident light with 1.54-µm wavelength and TM polarization....

  10. Scaling limits and reliability of SOI CMOS technology

    International Nuclear Information System (INIS)

    Ioannou, D E

    2005-01-01

    As bulk and PD-SOI CMOS approach their scaling limit (at gate length of around 50 nm), there is a renewed interest on FD-SOI because of its potential for continued scalability beyond this limit. In this review the performance and reliability of extremely scaled FD transistors are discussed and an attempt is made to identify critical areas for further research. (invited paper)

  11. Design of novel SOI 1 × 4 optical power splitter using seven horizontally slotted waveguides

    Science.gov (United States)

    Katz, Oded; Malka, Dror

    2017-07-01

    In this paper, we demonstrate a compact silicon on insulator (SOI) 1 × 4 optical power splitter using seven horizontal slotted waveguides. Aluminum nitride (AIN) surrounded by silicon (Si) was used to confine the optical field in the slot region. All of the power analysis has been done in transverse magnetic (TM) polarization mode and a compact optical power splitter as short as 14.5 μm was demonstrated. The splitter was designed by using full vectorial beam propagation method (FV-BPM) simulations. Numerical investigations show that this device can work across the whole C-band (1530-1565 nm) with excess loss better than 0.23 dB.

  12. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    International Nuclear Information System (INIS)

    Mohapatra, S K; Pradhan, K P; Sahu, P K; Pati, G S; Kumar, M R

    2014-01-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™. (paper)

  13. The effect of interface trapped charges in DMG-S-SOI MOSFET: a perspective study

    Science.gov (United States)

    Mohapatra, S. K.; Pradhan, K. P.; Sahu, P. K.; Pati, G. S.; Kumar, M. R.

    2014-12-01

    In this paper, the existing two-dimensional (2D) threshold voltage model for a dual material gate fully depleted strained silicon on insulator (DMG-FD-S-SOI) metal-oxide-semiconductor field effect transistor (MOSFET) is modified by considering the interface trapped charge effects. The interface trapped charge is a common phenomenon, and this charge cannot be neglected in nanoscale devices. For finding out the surface potential, parabolic approximation has been utilized and the virtual cathode potential method is used to formulate the threshold voltage. The developed threshold voltage model incorporates both positive as well as negative interface charges. Finally, validity of the presented model is verified with 2D device simulator Sentaurus™.

  14. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  15. Thermal insulation

    International Nuclear Information System (INIS)

    Aspden, G.J.; Howard, R.S.

    1988-01-01

    The patent concerns high temperature thermal insulation of large vessels, such as the primary vessel of a liquid metal cooled nuclear reactor. The thermal insulation consists of multilayered thermal insulation modules, and each module comprises a number of metal sheet layers sandwiched between a back and front plate. The layers are linked together by straps and clips to control the thickness of the module. (U.K.)

  16. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    International Nuclear Information System (INIS)

    Dehzangi, Arash; Larki, Farhad; Naseri, Mahmud G.; Navasery, Manizheh; Majlis, Burhanuddin Y.; Razip Wee, Mohd F.; Halimah, M.K.; Islam, Md. Shabiul; Md Ali, Sawal H.; Saion, Elias

    2015-01-01

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated

  17. Fabrication and simulation of single crystal p-type Si nanowire using SOI technology

    Energy Technology Data Exchange (ETDEWEB)

    Dehzangi, Arash, E-mail: arashd53@hotmail.com [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Larki, Farhad [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Naseri, Mahmud G. [Department of Physics, Faculty of Science, Malayer University, Malayer, Hamedan (Iran, Islamic Republic of); Navasery, Manizheh [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Majlis, Burhanuddin Y.; Razip Wee, Mohd F. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Halimah, M.K. [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia); Islam, Md. Shabiul; Md Ali, Sawal H. [Institute of Microengineering and Nanoelectronics (IMEN), Universiti Kebangsaan Malaysia, 43600 Bangi, Selangor (Malaysia); Saion, Elias [Department of Physics, Faculty of Science, Universiti Putra Malaysia, 43400 Serdang, Selangor (Malaysia)

    2015-04-15

    Highlights: • Single crystal silicon nanowire is fabricated on Si on insulator substrate, using atomic force microscope (AFM) nanolithography and KOH + IPA chemical wet etching. • Some of major parameters in fabrication process, such as writing speed and applied voltage along with KOH etching depth are investigated, and then the I–V characteristic of Si nanowires is measured. • For better understanding of the charge transmission through the nanowire, 3D-TCAD simulation is performed to simulate the Si nanowires with the same size of the fabricated ones, and variation of majority and minority carriers, hole quasi-Fermi level and generation/recombination rate are investigated. - Abstract: Si nanowires (SiNWs) as building blocks for nanostructured materials and nanoelectronics have attracted much attention due to their major role in device fabrication. In the present work a top-down fabrication approach as atomic force microscope (AFM) nanolithography was performed on Si on insulator (SOI) substrate to fabricate a single crystal p-type SiNW. To draw oxide patterns on top of the SOI substrate local anodic oxidation was carried out by AFM in contact mode. After the oxidation procedure, an optimized solution of 30 wt.% KOH with 10 vol.% IPA for wet etching at 63 °C was applied to extract the nanostructure. The fabricated SiNW had 70–85 nm full width at half maximum width, 90 nm thickness and 4 μm length. The SiNW was simulated using Sentaurus 3D software with the exact same size of the fabricated device. I–V characterization of the SiNW was measured and compared with simulation results. Using simulation results variation of carrier's concentrations, valence band edge energy and recombination generation rate for different applied voltage were investigated.

  18. Cellulose Insulation

    Science.gov (United States)

    1980-01-01

    Fire retardant cellulose insulation is produced by shredding old newspapers and treating them with a combination of chemicals. Insulating material is blown into walls and attics to form a fiber layer which blocks the flow of air. All-Weather Insulation's founders asked NASA/UK-TAP to help. They wanted to know what chemicals added to newspaper would produce an insulating material capable of meeting federal specifications. TAP researched the query and furnished extensive information. The information contributed to successful development of the product and helped launch a small business enterprise which is now growing rapidly.

  19. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  20. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  1. Guided Acoustic and Optical Waves in Silicon-on-Insulator for Brillouin Scattering and Optomechanics

    Science.gov (United States)

    2016-08-01

    APL PHOTONICS 1, 071301 (2016) Guided acoustic and optical waves in silicon-on- insulator for Brillouin scattering and optomechanics Christopher J...is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI) material system. Thin...high sound velocity — makes guiding acoustic waves difficult, motivating the use of soft chalcogenide glasses and partial or complete releases (removal

  2. Thermal insulation

    International Nuclear Information System (INIS)

    Pinsky, G.P.

    1977-01-01

    Thermal insulation for vessels and piping within the reactor containment area of nuclear power plants is disclosed. The thermal insulation of this invention can be readily removed and replaced from the vessels and piping for inservice inspection, can withstand repeated wettings and dryings, and can resist high temperatures for long periods of time. 4 claims, 3 figures

  3. A novel partial SOI LDMOSFET with periodic buried oxide for breakdown voltage and self heating effect enhancement

    Science.gov (United States)

    Jamali Mahabadi, S. E.; Rajabi, Saba; Loiacono, Julian

    2015-09-01

    In this paper a partial silicon on insulator (PSOI) lateral double diffused metal oxide semiconductor field effect transistor (LDMOSFET) with periodic buried oxide layer (PBO) for enhancing breakdown voltage (BV) and self-heating effects (SHEs) is proposed for the first time. This new structure is called periodic buried oxide partial silicon on insulator (PBO-PSOI). In this structure, periodic small pieces of SiO2 were used as the buried oxide (BOX) layer in PSOI to modulate the electric field in the structure. It was demonstrated that the electric field is distributed more evenly by producing additional electric field peaks, which decrease the common peaks near the drain and gate junctions in the PBO-PSOI structure. Hence, the area underneath the electric field curve increases which leads to higher breakdown voltage. Also a p-type Si window was introduced in the source side to force the substrate to share the vertical voltage drop, leading to a higher vertical BV. Furthermore, the Si window under the source and those between periodic pieces of SiO2 create parallel conduction paths between the active layer and substrate thereby alleviating the SHEs. Simulations with the two dimensional ATLAS device simulator from the Silvaco suite of simulation tools show that the BV of PBO-PSOI is 100% higher than that of the conventional partial SOI (C-PSOI) structure. Furthermore the PBO-PSOI structure alleviates SHEs to a greater extent than its C-PSOI counterpart. The achieved drain current for the PBO-PSOI structure (100 μA), at drain-source voltage of VDS = 100 V and gate-source voltage of VGS = 25 V, is shown to be significantly larger than that in C-PSOI and fully depleted SOI (FD-SOI) structures (87 μA and 51 μA respectively). Drain current can be further improved at the expense of BV by increasing the doping of the drift region.

  4. Improvement of SOI microdosimeter performance using pulse shape discrimination techniques

    International Nuclear Information System (INIS)

    Cornelius, I.

    2002-01-01

    Full text: Microdosimetry is used to study the radiobiological properties of densely ionising radiations encountered in hadron therapy and space environments by measuring energy deposition in microscopic volumes. The creation of a solid state microdosimeter to replace the traditional tissue equivalent proportional counter is a topic of ongoing research. The Centre for Medical Radiation Physics has been investigating a technique using microscopic arrays of reverse biased pn junctions to measure the linear energy transfer of ions. A prototype silicon-on-insulator (SOI) microdosimeter was developed and measurements were conducted at boron neutron capture therapy, proton therapy, and fast neutron therapy facilities. Previous studies have shown the current microdosimeter possesses a poorly defined sensitive volume, a consequence of charge collection events being measured for ion strikes outside the pn junction via the diffusion of charge carriers. As a result, the amount of charge collected by the microdosimeter following an ion strike has a strong dependence on the location of the strike on the device and the angle of incidence of the ion. The aim of this work was to investigate the use of pulse shape discrimination (PSD) techniques to preclude the acquisition of events resulting from ion strikes outside the depletion region of the pn junction. Experiments were carried out using the Heavy Ion Microprobe (HIMP) at the Australian Nuclear Science and Technology Organisation, Lucas Heights, Australia. The HIMP was used to measure the charge collection time as a function of ion strike location on the microdosimeter array. As expected, the charge collection time was seen to increase monotonically as the distance of the ion strike from the junction increased. The charge collection time corresponding to ion strikes within the junction was determined. Through use of suitable electronics it was possible to gate the charge collection signal based on simultaneous measurements of

  5. Hydrogen interactions with silicon-on-insulator materials

    OpenAIRE

    Rivera de Mena, A.J.

    2003-01-01

    The booming of microelectronics in recent decades has been made possible by the excellent properties of the Si/SiO2 interface in oxide on silicon systems.. This semiconductor/insulator combination has proven to be of great value for the semiconductor industry. It has made it possible to continuously increase the number of transistors per chip until the physical limit of integration is now almost reached. Silicon-on-insulator (SOI) materials were early on seen as a step in the logical evolutio...

  6. InP on SOI devices for optical communication and optical network on chip

    Science.gov (United States)

    Fedeli, J.-M.; Ben Bakir, B.; Olivier, N.; Grosse, Ph.; Grenouillet, L.; Augendre, E.; Phillippe, P.; Gilbert, K.; Bordel, D.; Harduin, J.

    2011-01-01

    For about ten years, we have been developing InP on Si devices under different projects focusing first on μlasers then on semicompact lasers. For aiming the integration on a CMOS circuit and for thermal issue, we relied on SiO2 direct bonding of InP unpatterned materials. After the chemical removal of the InP substrate, the heterostructures lie on top of silicon waveguides of an SOI wafer with a separation of about 100nm. Different lasers or photodetectors have been achieved for off-chip optical communication and for intra-chip optical communication within an optical network. For high performance computing with high speed communication between cores, we developed InP microdisk lasers that are coupled to silicon waveguide and produced 100μW of optical power and that can be directly modulated up to 5G at different wavelengths. The optical network is based on wavelength selective circuits with ring resonators. InGaAs photodetectors are evanescently coupled to the silicon waveguide with an efficiency of 0.8A/W. The fabrication has been demonstrated at 200mm wafer scale in a microelectronics clean room for CMOS compatibility. For off-chip communication, silicon on InP evanescent laser have been realized with an innovative design where the cavity is defined in silicon and the gain localized in the QW of bonded InP hererostructure. The investigated devices operate at continuous wave regime with room temperature threshold current below 100 mA, the side mode suppression ratio is as high as 20dB, and the fibercoupled output power is {7mW. Direct modulation can be achieved with already 6G operation.

  7. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  8. Croire en soi, croire en l'autre

    Directory of Open Access Journals (Sweden)

    Eugène Enriquez

    2014-04-01

    Full Text Available La croyance aux Dieux ou en un Dieu unique c'est-à-dire à l'incroyable est fort répandue et semble normale comme avoir confiance en soi et en l'autre. Mais croire en soi et en l'autre apparaît étonnant car ce serait se mettre sur le même rang que Dieu. Effectivement l'homme essaie de ressembler à Dieu. Mais à Dieu blessé, faillible, s'interrogeant constamment. Ce Dieu nouveau est un "sujet amoureux" amoureux de soi, de l'autre et de la vie. Il se conduit comme un "Dichter" assumant une responsabilité morale. Il est difficile, voire souvent impossible de se situer comme un "Dichter". C'est pourtant la tâche à laquelle l'homme contemporain est confronté.

  9. BUSFET - A Novel Radiation-Hardened SOI Transistor

    International Nuclear Information System (INIS)

    Schwank, J.R.; Shaneyfelt, M.R.; Draper, B.L.; Dodd, P.E.

    1999-01-01

    The total-dose hardness of SOI technology is limited by radiation-induced charge trapping in gate, field, and SOI buried oxides. Charge trapping in the buried oxide can lead to back-channel leakage and makes hardening SOI transistors more challenging than hardening bulk-silicon transistors. Two avenues for hardening the back-channel are (1) to use specially prepared SOI buried oxides that reduce the net amount of trapped positive charge or (2) to design transistors that are less sensitive to the effects of trapped charge in the buried oxide. In this work, we propose a new partially-depleted SOI transistor structure that we call the BUSFET--Body Under Source FET. The BUSFET utilizes a shallow source and a deep drain. As a result, the silicon depletion region at the back channel caused by radiation-induced charge trapping in the buried oxide does not form a conducting path between source and drain. Thus, the BUSFET structure design can significantly reduce radiation-induced back-channel leakage without using specially prepared buried oxides. Total dose hardness is achieved without degrading the intrinsic SEU and dose rate hardness of SOI technology. The effectiveness of the BUSFET structure for reducing total-dose back-channel leakage depends on several variables, including the top silicon film thickness and doping concentration and the depth of the source. 3-D simulations show that for a doping concentration of 10 18 cm -3 and a source depth of 90 nm, a silicon film thickness of 180 nm is sufficient to almost completely eliminate radiation-induced back-channel leakage. However, for a doping concentration of 3x10 17 cm -3 , a thicker silicon film (300 nm) must be used

  10. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  11. The Bridges SOI Model School Program at Palo Verde School, Palo Verde, Arizona.

    Science.gov (United States)

    Stock, William A.; DiSalvo, Pamela M.

    The Bridges SOI Model School Program is an educational service based upon the SOI (Structure of Intellect) Model School curriculum. For the middle seven months of the academic year, all students in the program complete brief daily exercises that develop specific cognitive skills delineated in the SOI model. Additionally, intensive individual…

  12. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  13. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    Science.gov (United States)

    Olszacki, M.; Maj, C.; Bahri, M. Al; Marrot, J.-C.; Boukabache, A.; Pons, P.; Napieralski, A.

    2010-06-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 1017 at cm-3 to 1.6 × 1019 at cm-3. The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 1018-1019 at cm-3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  14. Experimental verification of temperature coefficients of resistance for uniformly doped P-type resistors in SOI

    International Nuclear Information System (INIS)

    Olszacki, M; Maj, C; Al Bahri, M; Marrot, J-C; Boukabache, A; Pons, P; Napieralski, A

    2010-01-01

    Many today's microsystems like strain-gauge-based piezoresistive pressure sensors contain doped resistors. If one wants to predict correctly the temperature impact on the performance of such devices, the accurate data about the temperature coefficients of resistance (TCR) are essential. Although such data may be calculated using one of the existing mobility models, our experiments showed that we can observe the huge mismatch between the calculated and measured values. Thus, in order to investigate the TCR values, a set of the test structures that contained doped P-type resistors was fabricated. As the TCR value also depends on the doping profile shape, we decided to use the very thin, 340 nm thick SOI wafers in order to fabricate the quasi-uniformly doped silicon layers ranging from 2 × 10 17 at cm −3 to 1.6 × 10 19 at cm −3 . The results showed that the experimental data for the first-order TCR are quite far from the calculated ones especially over the doping range of 10 18 –10 19 at cm −3 and quite close to the experimental ones obtained by Bullis about 50 years ago for bulk silicon. Moreover, for the first time, second-order coefficients that were not very consistent with the calculations were obtained.

  15. Crosstalk analysis of silicon-on-insulator nanowire-arrayed waveguide grating

    International Nuclear Information System (INIS)

    Li Kai-Li; An Jun-Ming; Zhang Jia-Shun; Wang Yue; Wang Liang-Liang; Li Jian-Guang; Wu Yuan-Da; Yin Xiao-Jie; Hu Xiong-Wei

    2016-01-01

    The factors influencing the crosstalk of silicon-on-insulator (SOI) nanowire arrayed waveguide grating (AWG) are analyzed using the transfer function method. The analysis shows that wider and thicker arrayed waveguides, outsider fracture of arrayed waveguide, and larger channel space, could mitigate the deterioration of crosstalk. The SOI nanowire AWGs with different arrayed waveguide widths are fabricated by using deep ultraviolet lithography (DUV) and inductively coupled plasma etching (ICP) technology. The measurement results show that the crosstalk performance is improved by about 7 dB through adopting 800 nm arrayed waveguide width. (paper)

  16. High-Q silicon-on-insulator slot photonic crystal cavity infiltrated by a liquid

    International Nuclear Information System (INIS)

    Caër, Charles; Le Roux, Xavier; Cassan, Eric

    2013-01-01

    We report the experimental realization of a high-Q slot photonic crystal cavity in Silicon-On-Insulator (SOI) configuration infiltrated by a liquid. Loaded Q-factor of 23 000 is measured at telecom wavelength. The intrinsic quality factor inferred from the transmission spectrum is higher than 200 000, which represents a record value for slot photonic crystal cavities on SOI, whereas the maximum of intensity of the cavity is roughly equal to 20% of the light transmitted in the waveguide. This result makes filled slot photonic crystal cavities very promising for silicon-based light emission and ultrafast nonlinear optics

  17. Improving breakdown voltage performance of SOI power device with folded drift region

    Science.gov (United States)

    Qi, Li; Hai-Ou, Li; Ping-Jiang, Huang; Gong-Li, Xiao; Nian-Jiong, Yang

    2016-07-01

    A novel silicon-on-insulator (SOI) high breakdown voltage (BV) power device with interlaced dielectric trenches (IDT) and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer, which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges (holes) at the corner of IDT. The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V. Project supported by the Guangxi Natural Science Foundation of China (Grant Nos. 2013GXNSFAA019335 and 2015GXNSFAA139300), Guangxi Experiment Center of Information Science of China (Grant No. YB1406), Guangxi Key Laboratory of Wireless Wideband Communication and Signal Processing of China, Key Laboratory of Cognitive Radio and Information Processing (Grant No. GXKL061505), Guangxi Key Laboratory of Automobile Components and Vehicle Technology of China (Grant No. 2014KFMS04), and the National Natural Science Foundation of China (Grant Nos. 61361011, 61274077, and 61464003).

  18. SOI N-Channel Field Effect Transistors, CHT-NMOS80, for Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Almad

    2009-01-01

    Extreme temperatures, both hot and cold, are anticipated in many of NASA space exploration missions as well as in terrestrial applications. One can seldom find electronics that are capable of operation under both regimes. Even for operation under one (hot or cold) temperature extreme, some thermal controls need to be introduced to provide appropriate ambient temperatures so that spacecraft on-board or field on-site electronic systems work properly. The inclusion of these controls, which comprise of heating elements and radiators along with their associated structures, adds to the complexity in the design of the system, increases cost and weight, and affects overall reliability. Thus, it would be highly desirable and very beneficial to eliminate these thermal measures in order to simplify system's design, improve efficiency, reduce development and launch costs, and improve reliability. These requirements can only be met through the development of electronic parts that are designed for proper and efficient operation under extreme temperature conditions. Silicon-on-insulator (SOI) based devices are finding more use in harsh environments due to the benefits that their inherent design offers in terms of reduced leakage currents, less power consumption, faster switching speeds, good radiation tolerance, and extreme temperature operability. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. The objective of this work was to evaluate the performance of a new commercial-off-the-shelf (COTS) SOI parts over an extended temperature range and to determine the effects of thermal cycling on their performance. The results will establish a baseline on the suitability of such devices for use in space exploration missions under extreme temperatures, and will aid mission planners and circuit designers in the proper selection of electronic parts and circuits. The electronic part investigated in this work comprised of a CHT-NMOS80

  19. Operation of SOI P-Channel Field Effect Transistors, CHT-PMOS30, under Extreme Temperatures

    Science.gov (United States)

    Patterson, Richard; Hammoud, Ahmad

    2009-01-01

    Electronic systems are required to operate under extreme temperatures in NASA planetary exploration and deep space missions. Electronics on-board spacecraft must also tolerate thermal cycling between extreme temperatures. Thermal management means are usually included in today s spacecraft systems to provide adequate temperature for proper operation of the electronics. These measures, which may include heating elements, heat pipes, radiators, etc., however add to the complexity in the design of the system, increases its cost and weight, and affects its performance and reliability. Electronic parts and circuits capable of withstanding and operating under extreme temperatures would reflect in improvement in system s efficiency, reducing cost, and improving overall reliability. Semiconductor chips based on silicon-on-insulator (SOI) technology are designed mainly for high temperature applications and find extensive use in terrestrial well-logging fields. Their inherent design offers advantages over silicon devices in terms of reduced leakage currents, less power consumption, faster switching speeds, and good radiation tolerance. Little is known, however, about their performance at cryogenic temperatures and under wide thermal swings. Experimental investigation on the operation of SOI, N-channel field effect transistors under wide temperature range was reported earlier [1]. This work examines the performance of P-channel devices of these SOI transistors. The electronic part investigated in this work comprised of a Cissoid s CHT-PMOS30, high temperature P-channel MOSFET (metal-oxide semiconductor field-effect transistor) device [2]. This high voltage, medium-power transistor is designed for geothermal well logging applications, aerospace and avionics, and automotive industry, and is specified for operation in the temperature range of -55 C to +225 C. Table I shows some specifications of this transistor [2]. The CHT-PMOS30 device was characterized at various temperatures

  20. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  1. SOI Transistor measurement techniques using body contacted transistors

    International Nuclear Information System (INIS)

    Worley, E.R.; Williams, R.

    1989-01-01

    Measurements of body contacted SOI transistors are used to isolate parameters of the back channel and island edge transistor. Properties of the edge and back channel transistor have been measured before and after X-ray irradiation (ARACOR). The unique properties of the edge transistor are shown to be a result of edge geometry as confirmed by a two dimensional transistor simulator

  2. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  3. Thermal insulation

    International Nuclear Information System (INIS)

    Durston, J.G.; Birch, W.; Facer, R.I.; Stuart, R.A.

    1977-01-01

    Reference is made to liquid metal cooled nuclear reactors. In the arrangement described the reactor vessel is clad with thermal insulation comprising a layer of insulating blocks spaced from the wall and from each other; each block is rigidly secured to the wall, and the interspaces are substantially closed against convectional flow of liquid by resilient closure members. A membrane covering is provided for the layer of blocks, with venting means to allow liquid from the reactor vessel to penetrate between the covering and the layer of blocks. The membrane covering may comprise a stainless steel sheet ribbed in orthogonal pattern to give flexibility for the accommodation of thermal strain. The insulating blocks may be comprised of stainless steel or cellular or porous material and may be hollow shells containing ceramic material or gas fillings. (U.K.)

  4. Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode

    Directory of Open Access Journals (Sweden)

    Xiaojun Cheng

    2014-05-01

    Full Text Available Power SOI (Silicon-On-Insulator devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor gate which is very easy to suffer ESD (Electro-Static Discharge overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

  5. Fabrication, structural and electrical properties of (1 1 0) localized silicon-on-insulator devices

    International Nuclear Information System (INIS)

    Destefanis, V; Huguenin, J L; Samson, M P; Morand, Y; Arvet, C; Monfray, S; Skotnicki, T; Hartmann, J M; Delaye, V; Boulitreau, P; Brianceau, P; Gautier, P

    2010-01-01

    The aim being to fabricate (1 1 0) localized silicon-on-insulator (L-SOI) devices, we have first of all completed the Semicond. Sci. Technol. 23 105018 (2008) study of the differences between (1 1 0) and (1 0 0) surfaces in terms of (i) HCl etch kinetics and (ii) SiGe growth kinetics (with a chlorinated chemistry). The core layers of a L-SOI device are indeed obtained thanks to the in situ HCl etching (on patterned wafers) of the Si active areas followed by the selective epitaxial growth of a Si 0.7 Ge 0.3 /Si stack. Given that SiGe(1 1 0) layers grown at 650 °C in windows of patterned wafers are rough, we have first of all studied the 600 °C growth kinetics of SiGe(1 1 0). As expected, the SiGe growth rate decreases as the growth temperature decreases from 650 °C down to 600 °C (irrespective of the surface orientation). The SiGe(1 0 0) growth rate increases linearly with the germane mass flow. Meanwhile, the SiGe(1 1 0) growth rate increases in a sub-linear fashion and then saturates at much lower values than on (1 0 0). The Ge concentration x dependence on the F(GeH 4 )/F(SiH 2 Cl 2 ) mass flow ratio is parabolic on (1 0 0) and linear on (1 1 0), with lower values on the latter than on the former. We have then used those data to fabricate (1 0 0) and (1 1 0) L-SOI structures. The high HCl partial pressure recessing of the Si(1 1 0) and Si(1 0 0) active areas was performed at 675 °C and 725 °C, respectively. An increase of both the Si(1 1 0) HCl etch rate and the SiGe growth rate (be it at 650 °C on (1 0 0) or at 600 °C on (1 1 0)) was noticed when switching from blanket to patterned wafers (factors of 2.5–3 for HCI and 1.5 for SiGe). Finally, Si(1 1 0) growth times were multiplied by 4/3 compared to the Si(1 0 0) growth time in order to obtain similar thickness Si caps. Subsequent process steps were very similar on (1 0 0) and (1 1 0). Almost the same etch rates were

  6. Topological insulators

    CERN Document Server

    Franz, Marcel

    2013-01-01

    Topological Insulators, volume six in the Contemporary Concepts of Condensed Matter Series, describes the recent revolution in condensed matter physics that occurred in our understanding of crystalline solids. The book chronicles the work done worldwide that led to these discoveries and provides the reader with a comprehensive overview of the field. Starting in 2004, theorists began to explore the effect of topology on the physics of band insulators, a field previously considered well understood. However, the inclusion of topology brings key new elements into this old field. Whereas it was

  7. Propriété de soi et indifférence morale du rapport à soi

    Directory of Open Access Journals (Sweden)

    Nathalie Maillard Romagnoli

    2011-05-01

    Full Text Available Je m’interroge dans cet article sur les implications du principe libertarien de la pleine propriété de soi sur la question du rapport moral à soi-même. À travers le principe de la pleine propriété de soi, les libertariens défendent la liberté entière de chacun de vivre comme il l���entend, pourvu que les droits des autres soient respectés. Apparemment, ce principe n’a pas grand-chose à nous dire sur ce que nous sommes moralement autorisés à nous faire à nous-mêmes ou non. Certains libertariens, comme Vallentyne, soutiennent toutefois que le principe de la pleine propriété de soi est incompatible avec l’existence de devoirs envers soi. La pleine propriété de soi impliquerait l’indifférence morale du rapport à soi. Je soutiens dans cet article que le principe de la pleine propriété de soi n’implique pas que ce que nous nous faisons à nous-mêmes soit moralement indifférent. Je veux aussi montrer que même si les libertariens, et en particulier Vallentyne, soutiennent la thèse de l’indifférence morale du rapport à soi, celle-ci n’est pas liée à la thèse de la pleine propriété de soi, mais bien plutôt à leur subjectivisme moral.ABSTRACTI ask in this article what the libertarian principle of full self-ownership has to say about volontary actions directed towards oneself. Through the principle of full self-ownership, libertarians defend the persons’ individual liberty to live as they choose to do, as long as they don’t infringe on the rights of others. Apparently, this principle doesn’t have much to say about what we are morally allowed to do to ourselves or not. Some libertarians, however, like Vallentyne, maintain that, if we have duties or obligations to ourselves, then we cannot be full self-owner. In this perspective, full self-ownership would imply that what we do to ourselves is morally indifferent. I want to show in this article that full self-ownership is compatible with the

  8. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators.

    Science.gov (United States)

    Mizumoto, Tetsuya; Shoji, Yuya; Takei, Ryohei

    2012-05-24

    This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO₃. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI) waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  9. Direct Wafer Bonding and Its Application to Waveguide Optical Isolators

    Directory of Open Access Journals (Sweden)

    Ryohei Takei

    2012-05-01

    Full Text Available This paper reviews the direct bonding technique focusing on the waveguide optical isolator application. A surface activated direct bonding technique is a powerful tool to realize a tight contact between dissimilar materials. This technique has the potential advantage that dissimilar materials are bonded at low temperature, which enables one to avoid the issue associated with the difference in thermal expansion. Using this technique, a magneto-optic garnet is successfully bonded on silicon, III-V compound semiconductors and LiNbO3. As an application of this technique, waveguide optical isolators are investigated including an interferometric waveguide optical isolator and a semileaky waveguide optical isolator. The interferometric waveguide optical isolator that uses nonreciprocal phase shift is applicable to a variety of waveguide platforms. The low refractive index of buried oxide layer in a silicon-on-insulator (SOI waveguide enhances the magneto-optic phase shift, which contributes to the size reduction of the isolator. A semileaky waveguide optical isolator has the advantage of large fabrication-tolerance as well as a wide operation wavelength range.

  10. Proposal for fabrication-tolerant SOI polarization splitter-rotator based on cascaded MMI couplers and an assisted bi-level taper.

    Science.gov (United States)

    Wang, Jing; Qi, Minghao; Xuan, Yi; Huang, Haiyang; Li, You; Li, Ming; Chen, Xin; Jia, Qi; Sheng, Zhen; Wu, Aimin; Li, Wei; Wang, Xi; Zou, Shichang; Gan, Fuwan

    2014-11-17

    A novel silicon-on-insulator (SOI) polarization splitter-rotator (PSR) with a large fabrication tolerance is proposed based on cascaded multimode interference (MMI) couplers and an assisted mode-evolution taper. The tapers are designed to adiabatically convert the input TM(0) mode into the TE(1) mode, which will output as the TE(0) mode after processed by the subsequent MMI mode converter, 90-degree phase shifter (PS) and MMI 3 dB coupler. The numerical simulation results show that the proposed device has a silicon photonics technology.

  11. One-dimensional breakdown voltage model of SOI RESURF lateral power device based on lateral linearly graded approximation

    International Nuclear Information System (INIS)

    Zhang Jun; Guo Yu-Feng; Xu Yue; Lin Hong; Yang Hui; Hong Yang; Yao Jia-Fei

    2015-01-01

    A novel one-dimensional (1D) analytical model is proposed for quantifying the breakdown voltage of a reduced surface field (RESURF) lateral power device fabricated on silicon on an insulator (SOI) substrate. We assume that the charges in the depletion region contribute to the lateral PN junctions along the diagonal of the area shared by the lateral and vertical depletion regions. Based on the assumption, the lateral PN junction behaves as a linearly graded junction, thus resulting in a reduced surface electric field and high breakdown voltage. Using the proposed model, the breakdown voltage as a function of device parameters is investigated and compared with the numerical simulation by the TCAD tools. The analytical results are shown to be in fair agreement with the numerical results. Finally, a new RESURF criterion is derived which offers a useful scheme to optimize the structure parameters. This simple 1D model provides a clear physical insight into the RESURF effect and a new explanation on the improvement in breakdown voltage in an SOI RESURF device. (paper)

  12. Optimal Design of an Ultrasmall SOI-Based 1 × 8 Flat-Top AWG by Using an MMI

    Directory of Open Access Journals (Sweden)

    Hongqiang Li

    2013-01-01

    Full Text Available Four methods based on a multimode interference (MMI structure are optimally designed to flatten the spectral response of silicon-on-insulator- (SOI- based arrayed-waveguide grating (AWG applied in a demodulation integration microsystem. In the design for each method, SOI is selected as the material, the beam propagation method is used, and the performances (including the 3 dB passband width, the crosstalk, and the insertion loss of the flat-top AWG are studied. Moreover, the output spectrum responses of AWGs with or without a flattened structure are compared. The results show that low insertion loss, crosstalk, and a flat and efficient spectral response are simultaneously achieved for each kind of structure. By comparing the four designs, the design that combines a tapered MMI with tapered input/output waveguides, which has not been previously reported, was shown to yield better results than others. The optimized design reduced crosstalk to approximately −21.9 dB and had an insertion loss of −4.36 dB and a 3 dB passband width, that is, approximately 65% of the channel spacing.

  13. Monolithic integration of InGaAs/InP multiple quantum wells on SOI substrates for photonic devices

    Science.gov (United States)

    Li, Zhibo; Wang, Mengqi; Fang, Xin; Li, Yajie; Zhou, Xuliang; Yu, Hongyan; Wang, Pengfei; Wang, Wei; Pan, Jiaoqing

    2018-02-01

    A direct epitaxy of III-V nanowires with InGaAs/InP multiple quantum wells on v-shaped trenches patterned silicon on insulator (SOI) substrates was realized by combining the standard semiconductor fabrication process with the aspect ratio trapping growth technique. Silicon thickness as well as the width and gap of each nanowire were carefully designed to accommodate essential optical properties and appropriate growth conditions. The III-V element ingredient, crystalline quality, and surface topography of the grown nanowires were characterized by X-ray diffraction spectroscopy, photoluminescence, and scanning electron microscope. Geometrical details and chemical information of multiple quantum wells were revealed by transmission electron microscopy and energy dispersive spectroscopy. Numerical simulations confirmed that the optical guided mode supported by one single nanowire was able to propagate 50 μm with ˜30% optical loss. This proposed integration scheme opens up an alternative pathway for future photonic integrations of III-V devices on the SOI platform at nanoscale.

  14. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  15. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  16. A silicon doped hafnium oxide ferroelectric p–n–p–n SOI tunneling field–effect transistor with steep subthreshold slope and high switching state current ratio

    Directory of Open Access Journals (Sweden)

    Saeid Marjani

    2016-09-01

    Full Text Available In this paper, a silicon–on–insulator (SOI p–n–p–n tunneling field–effect transistor (TFET with a silicon doped hafnium oxide (Si:HfO2 ferroelectric gate stack is proposed and investigated via 2D device simulation with a calibrated nonlocal band–to–band tunneling model. Utilization of Si:HfO2 instead of conventional perovskite ferroelectrics such as lead zirconium titanate (PbZrTiO3 and strontium bismuth tantalate (SrBi2Ta2O9 provides compatibility to the CMOS process as well as improved device scalability. By using Si:HfO2 ferroelectric gate stack, the applied gate voltage is effectively amplified that causes increased electric field at the tunneling junction and reduced tunneling barrier width. Compared with the conventional p–n–p–n SOI TFET, the on–state current and switching state current ratio are appreciably increased; and the average subthreshold slope (SS is effectively reduced. The simulation results of Si:HfO2 ferroelectric p–n–p–n SOI TFET show significant improvement in transconductance (∼9.8X enhancement at high overdrive voltage and average subthreshold slope (∼35% enhancement over nine decades of drain current at room temperature, indicating that this device is a promising candidate to strengthen the performance of p–n–p–n and conventional TFET for a switching performance.

  17. Interfacial phonon scattering and transmission loss in >1 μm thick silicon-on-insulator thin films

    Science.gov (United States)

    Jiang, Puqing; Lindsay, Lucas; Huang, Xi; Koh, Yee Kan

    2018-05-01

    Scattering of phonons at boundaries of a crystal (grains, surfaces, or solid/solid interfaces) is characterized by the phonon wavelength, the angle of incidence, and the interface roughness, as historically evaluated using a specularity parameter p formulated by Ziman [Electrons and Phonons (Clarendon Press, Oxford, 1960)]. This parameter was initially defined to determine the probability of a phonon specularly reflecting or diffusely scattering from the rough surface of a material. The validity of Ziman's theory as extended to solid/solid interfaces has not been previously validated. To better understand the interfacial scattering of phonons and to test the validity of Ziman's theory, we precisely measured the in-plane thermal conductivity of a series of Si films in silicon-on-insulator (SOI) wafers by time-domain thermoreflectance (TDTR) for a Si film thickness range of 1-10 μm and a temperature range of 100-300 K. The Si /SiO2 interface roughness was determined to be 0.11 ±0.04 nm using transmission electron microscopy (TEM). Furthermore, we compared our in-plane thermal conductivity measurements to theoretical calculations that combine first-principles phonon transport with Ziman's theory. Calculations using Ziman's specularity parameter significantly overestimate values from the TDTR measurements. We attribute this discrepancy to phonon transmission through the solid/solid interface into the substrate, which is not accounted for by Ziman's theory for surfaces. The phonons that are specularly transmitted into an amorphous layer will be sufficiently randomized by the time they come back to the crystalline Si layer, the effect of which is practically equivalent to a diffuse reflection at the interface. We derive a simple expression for the specularity parameter at solid/amorphous interfaces and achieve good agreement between calculations and measurement values.

  18. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  19. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  20. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  1. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  2. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  3. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  4. Influence of germanium on thermal dewetting and agglomeration of the silicon template layer in thin silicon-on-insulator

    International Nuclear Information System (INIS)

    Zhang, P P; Yang, B; Rugheimer, P P; Roberts, M M; Savage, D E; Lagally, M G; Liu Feng

    2009-01-01

    We investigate the influence of heteroepitaxially grown Ge on the thermal dewetting and agglomeration of the Si(0 0 1) template layer in ultrathin silicon-on-insulator (SOI). We show that increasing Ge coverage gradually destroys the long-range ordering of 3D nanocrystals along the (1 3 0) directions and the 3D nanocrystal shape anisotropy that are observed in the dewetting and agglomeration of pure SOI(0 0 1). The results are qualitatively explained by Ge-induced bond weakening and decreased surface energy anisotropy. Ge lowers the dewetting and agglomeration temperature to as low as 700 0 C.

  5. A 6 device SOI new technology for mixed analog-digital and rad-hard applications

    International Nuclear Information System (INIS)

    Blanc, J.P.; Bonaime, J.; Delevoye, E.; Pontcharra, J. de; Gautier, J.; Truche, R.

    1993-01-01

    DMILL technology is being developed for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva). Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2μm thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric isolation and low temperature process. The mean feature is that six different components are fabricated on the same wafer, taking into account the 12 volts supply voltage constraint for some analog applications. The first electrical characteristics are presented in this paper. The optimization capabilities of such a hardened CBi-CJ-CMOS technology are discussed

  6. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  7. Novel Applications of a Thermally Tunable Bistable Buckling Silicon-on-Insulator (SOI) Microfabricated Membrane

    Science.gov (United States)

    2015-09-17

    sensor and disposable medical blood pressure sensor, which both hit the market in 1982 [2]. Since then, MEMS technology has undergone rapid growth and...Available: http: //digitalpicture.com.au/climate-change-slowing-trains/ 49. O. Tabata , K. Kawahata, S. Sugiyama, and I. Igarashi, “Mechanical property

  8. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  9. Ultrabroadband Hybrid III-V/SOI Grating Reflector for On-chip Lasers

    DEFF Research Database (Denmark)

    Park, Gyeong Cheol; Taghizadeh, Alireza; Chung, Il-Sug

    2016-01-01

    We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability.......We report on a new type of III-V/SOI grating reflector with a broad stopband of 350 nm. This reflector has promising prospects for applications in high-speed III-V/SOI vertical cavity lasers with an improved heat dissipation capability....

  10. Heterojunction fully depleted SOI-TFET with oxide/source overlap

    Science.gov (United States)

    Chander, Sweta; Bhowmick, B.; Baishya, S.

    2015-10-01

    In this work, a hetero-junction fully depleted (FD) Silicon-on-Insulator (SOI) Tunnel Field Effect Transistor (TFET) nanostructure with oxide overlap on the Germanium-source region is proposed. Investigations using Synopsys Technology Computer Aided Design (TCAD) simulation tools reveal that the simple oxide overlap on the Germanium-source region increases the tunneling area as well as the tunneling current without degrading the band-to-band tunneling (BTBT) and improves the device performance. More importantly, the improvement is independent of gate overlap. Simulation study shows improvement in ON current, subthreshold swing (SS), OFF current, ION/IOFF ration, threshold voltage and transconductance. The proposed device with hafnium oxide (HfO2)/Aluminium Nitride (AlN) stack dielectric material offers an average subthreshold swing of 22 mV/decade and high ION/IOFF ratio (∼1010) at VDS = 0.4 V. Compared to conventional TFET, the Miller capacitance of the device shows the enhanced performance. The impact of the drain voltage variation on different parameters such as threshold voltage, subthreshold swing, transconductance, and ION/IOFF ration are also found to be satisfactory. From fabrication point of view also it is easy to utilize the existing CMOS process flows to fabricate the proposed device.

  11. Spacer engineered Trigate SOI TFET: An investigation towards harsh temperature environment applications

    Science.gov (United States)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Artola, L.; Sahu, P. K.

    2016-09-01

    In this paper, a novel N-channel Tunnel Field Effect Transistor (TFET) i.e., Trigate Silicon-ON-Insulator (SOI) N-TFET with high-k spacer is proposed for better Sub-threshold swing (SS) and OFF-state current (IOFF) by keeping in mind the sensitivity towards temperature. The proposed model can achieve a Sub-threshold swing less than 35 mV/decade at various temperatures, which is desirable for designing low power CTFET for digital circuit applications. In N-TFET source doping has a significant effect on the ON-state current (ION) level; therefore more electrons will tunnel from source to channel region. High-k Spacer i.e., HfO2 is used to enhance the device performance and also it avoids overlapping of transistors in an integrated circuits (IC's). We have designed a reliable device by performing the temperature analysis on Transfer characteristics, Drain characteristics and also on various performance metrics like ON-state current (ION), OFF-state current (IOFF), ION/IOFF, Trans-conductance (gm), Trans-conductance Generation Factor (TGF), Sub-threshold Swing (SS) to observe the applications towards harsh temperature environment.

  12. Molecular sensing using monolayer floating gate, fully depleted SOI MOSFET acting as an exponential transducer.

    Science.gov (United States)

    Takulapalli, Bharath R

    2010-02-23

    Field-effect transistor-based chemical sensors fall into two broad categories based on the principle of signal transduction-chemiresistor or Schottky-type devices and MOSFET or inversion-type devices. In this paper, we report a new inversion-type device concept-fully depleted exponentially coupled (FDEC) sensor, using molecular monolayer floating gate fully depleted silicon on insulator (SOI) MOSFET. Molecular binding at the chemical-sensitive surface lowers the threshold voltage of the device inversion channel due to a unique capacitive charge-coupling mechanism involving interface defect states, causing an exponential increase in the inversion channel current. This response of the device is in opposite direction when compared to typical MOSFET-type sensors, wherein inversion current decreases in a conventional n-channel sensor device upon addition of negative charge to the chemical-sensitive device surface. The new sensor architecture enables ultrahigh sensitivity along with extraordinary selectivity. We propose the new sensor concept with the aid of analytical equations and present results from our experiments in liquid phase and gas phase to demonstrate the new principle of signal transduction. We present data from numerical simulations to further support our theory.

  13. Spatially resolved localized vibrational mode spectroscopy of carbon in liquid encapsulated Czochralski grown gallium arsenide wafers

    International Nuclear Information System (INIS)

    Yau, Waifan.

    1988-04-01

    Substitutional carbon on an arsenic lattice site is the shallowest and one of the most dominant acceptors in semi-insulating Liquid Encapsulated Czochralski (LEC) GaAs. However, the role of this acceptor in determining the well known ''W'' shape spatial variation of neutral EL2 concentration along the diameter of a LEC wafer is not known. In this thesis, we attempt to clarify the issue of the carbon acceptor's effect on this ''W'' shaped variation by measuring spatial profiles of this acceptor along the radius of three different as-grown LEC GaAs wafers. With localized vibrational mode absorption spectroscopy, we find that the profile of the carbon acceptor is relatively constant along the radius of each wafer. Average values of concentration are 8 x 10E15 cm -3 , 1.1 x 10E15 cm -3 , and 2.2 x 10E15 cm -3 , respectively. In addition, these carbon acceptor LVM measurements indicate that a residual donor with concentration comparable to carbon exists in these wafers and it is a good candidate for the observed neutral EL2 concentration variation. 22 refs., 39 figs

  14. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  15. Integrated programmable photonic filter on the silicon -on- insulator platform

    DEFF Research Database (Denmark)

    Liao, Shasha; Ding, Yunhong; Peucheret, Christophe

    2014-01-01

    We propose and demonstrate a silicon - on - insulator (SOI) on - chip programmable filter based on a four - tap finite impulse response structure. The photonic filter is programmable thanks to amplitude and phase modulation of each tap controlled by thermal heater s. We further demonstrate...... the tunability of the filter central wavelength, bandwidth and variable passband shape. The tuning range of the central wavelength is at least 42% of the free spectral range. The bandwidth tuning range is at least half of the free spectral range. Our scheme has distinct advantages of compactness, capability...

  16. Tank Insulation

    Science.gov (United States)

    1979-01-01

    For NASA's Apollo program, McDonnell Douglas Astronautics Company, Huntington Beach, California, developed and built the S-IVB, uppermost stage of the three-stage Saturn V moonbooster. An important part of the development task was fabrication of a tank to contain liquid hydrogen fuel for the stage's rocket engine. The liquid hydrogen had to be contained at the supercold temperature of 423 degrees below zero Fahrenheit. The tank had to be perfectly insulated to keep engine or solar heat from reaching the fuel; if the hydrogen were permitted to warm up, it would have boiled off, or converted to gaseous form, reducing the amount of fuel available to the engine. McDonnell Douglas' answer was a supereffective insulation called 3D, which consisted of a one-inch thickness of polyurethane foam reinforced in three dimensions with fiberglass threads. Over a 13-year development and construction period, the company built 30 tanks and never experienced a failure. Now, after years of additional development, an advanced version of 3D is finding application as part of a containment system for transporting Liquefied Natural Gas (LNG) by ship.

  17. Advanced ACTPol Multichroic Polarimeter Array Fabrication Process for 150 mm Wafers

    Science.gov (United States)

    Duff, S. M.; Austermann, J.; Beall, J. A.; Becker, D.; Datta, R.; Gallardo, P. A.; Henderson, S. W.; Hilton, G. C.; Ho, S. P.; Hubmayr, J.; Koopman, B. J.; Li, D.; McMahon, J.; Nati, F.; Niemack, M. D.; Pappas, C. G.; Salatino, M.; Schmitt, B. L.; Simon, S. M.; Staggs, S. T.; Stevens, J. R.; Van Lanen, J.; Vavagiakis, E. M.; Ward, J. T.; Wollack, E. J.

    2016-08-01

    Advanced ACTPol (AdvACT) is a third-generation cosmic microwave background receiver to be deployed in 2016 on the Atacama Cosmology Telescope (ACT). Spanning five frequency bands from 25 to 280 GHz and having just over 5600 transition-edge sensor (TES) bolometers, this receiver will exhibit increased sensitivity and mapping speed compared to previously fielded ACT instruments. This paper presents the fabrication processes developed by NIST to scale to large arrays of feedhorn-coupled multichroic AlMn-based TES polarimeters on 150-mm diameter wafers. In addition to describing the streamlined fabrication process which enables high yields of densely packed detectors across larger wafers, we report the details of process improvements for sensor (AlMn) and insulator (SiN_x) materials and microwave structures, and the resulting performance improvements.

  18. Wafer-Scale Gigahertz Graphene Field Effect Transistors on SiC Substrates

    Institute of Scientific and Technical Information of China (English)

    潘洪亮; 金智; 麻芃; 郭建楠; 刘新宇; 叶甜春; 李佳; 敦少博; 冯志红

    2011-01-01

    Wafer-scale graphene field-effect transistors are fabricated using benzocyclobutene and atomic layer deposition Al2O3 as the top-gate dielectric.The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate.The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found.For the intrinsic characteristic of this particular channel material,the devices cannot be switched off.The cut-off frequencies of these graphene field-effect transistors,which have a gate length of l μm,are larger than 800 MHz.The largest one can reach 1.24 GHz.There are greater than 95% active devices that can be successfully applied.We thus succeed in fabricating wafer-scale gigahertz graphene field-effect transistors,which paves the way for high-performance graphene devices and circuits.%Wafer-scale graphene Beld-effect transistors are fabricated using benzocyclobutene and atomic layer deposition AI2O3 as the top-gate dielectric. The epitaxial-graphene layer is formed by graphitization of a 2-inch-diameter Si-face semi-insulating 6H-SiC substrate. The graphene on the silicon carbide substrate is heavily n-doped and current saturation is not found. For the intrinsic characteristic of this particular channel material, the devices cannot be switched off. The cut-off frequencies of these graphene field-effect transistors, which have a gate length of l μm, are larger than 800MHz. The largest one can reach 1.24 GHz. There are greater than 95% active devices that can be successfully applied. We thus succeed in fabricating wafer-scale gigahertz graphene Geld-effect transistors, which paves the way for high-performance graphene devices and circuits.

  19. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  20. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  1. Hybrid III-V/SOI resonant cavity enhanced photodetector

    DEFF Research Database (Denmark)

    Learkthanakhachon, Supannee; Taghizadeh, Alireza; Park, Gyeong Cheol

    2016-01-01

    A hybrid III–V/SOI resonant-cavity-enhanced photodetector (RCE-PD) structure comprising a high-contrast grating (HCG) reflector, a hybrid grating (HG) reflector, and an air cavity between them, has been proposed and investigated. In the proposed structure, a light absorbing material is integrated...... as part of the HG reflector, enabling a very compact vertical cavity. Numerical investigations show that a quantum efficiency close to 100 % and a detection linewidth of about 1 nm can be achieved, which are desirable for wavelength division multiplexing applications. Based on these results, a hybrid RCE...

  2. Inverse Design of a SOI T-junction Polarization Beamsplitter

    Science.gov (United States)

    Ye, Zi; Qiu, Jifang; Meng, Chong; Zheng, Li; Dong, Zhenli; Wu, Jian

    2017-06-01

    A SOI T-junction polarization beamsplitter with an ultra-compact footprint of 2.8×2.8μm2 is designed based on the method of inverse design. Simulated results show that the conversion efficiencies for TE and TM lights are 73.34% (simulated insertion loss of 2dB) and 80.4% (simulated insertion loss of 1.7dB) at 1550nm, respectively; the simulated extinction ratios for TE and TM lights are 19.3dB and 13.99dB at 1558nm, respectively.

  3. The founder of the Friends Foundation--Tessie Soi.

    Science.gov (United States)

    Topurua, Ore

    2013-01-01

    Tessie Soi is well known in Papua New Guinea and beyond for her work with HIV/AIDS (human immunodeficiency virus/acquired immune deficiency syndrome) patients, including through the Friends Foundation, an organization that focuses on helping families affected by HIV and AIDS. This article explores Tessie's early life and childhood, providing insight into some of the values she learned from her parents. Providing details about the Friends Foundation and the Orphan Buddy Systems program, a program Tessie established to support AIDS orphans, the article offers insight into Tessie's beliefs and compassion, simultaneously highlighting the value she places on her family.

  4. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  5. Worst-Case Bias During Total Dose Irradiation of SOI Transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Colladant, T.; Paillet, P.; Leray, J.-L; Musseau, O.; Schwank, James R.; Shaneyfelt, Marty R.; Pelloie, J.L.; Du Port de Poncharra, J.

    2000-01-01

    The worst case bias during total dose irradiation of partially depleted SOI transistors (from SNL and from CEA/LETI) is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide

  6. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  7. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  8. Modeling of the Channel Thickness Influence on Electrical Characteristics and Series Resistance in Gate-Recessed Nanoscale SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2013-01-01

    Full Text Available Ultrathin body (UTB and nanoscale body (NSB SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46 nm and lower than 5 nm, respectively, were fabricated using a selective “gate-recessed” process on the same silicon wafer. Their current-voltage characteristics measured at room temperature were found to be surprisingly different by several orders of magnitude. We analyzed this result by considering the severe mobility degradation and the influence of a huge series resistance and found that the last one seems more coherent. Then the electrical characteristics of the NSB can be analytically derived by integrating a gate voltage-dependent drain source series resistance. In this paper, the influence of the channel thickness on the series resistance is reported for the first time. This influence is integrated to the analytical model in order to describe the trends of the saturation current with the channel thickness. This modeling approach may be useful to interpret anomalous electrical behavior of other nanodevices in which series resistance and/or mobility degradation is of a great concern.

  9. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  10. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  11. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  12. A graphene spin diode based on Rashba SOI

    International Nuclear Information System (INIS)

    Mohammadpour, Hakimeh

    2015-01-01

    In this paper a graphene-based two-terminal electronic device is modeled for application in spintronics. It is based on a gapped armchair graphene nanoribbon (GNR). The electron transport is considered through a scattering or channel region which is sandwiched between two lateral semi-infinite ferromagnetic leads. The two ferromagnetic leads, being half-metallic, are supposed to be in either parallel or anti-parallel magnetization. Meanwhile, the central channel region is a normal layer under the influence of the Rashba SOI, induced e.g., by the substrate. The device operation is based on modulating the (spin-) current by tuning the strength of the RSOI. The resultant current, being spin-polarized, is controlled by the RSOI in mutual interplay with the channel length. Inverting alternating bias voltage to a fully rectified spin-current is the main achievement of this paper. - Highlights: • Graphene-based electronic device is modeled with ferromagnetic leads. • The device operation is based on modulating the (spin-) current by Rashba SOI. • Inverting alternating bias voltage to rectified spin-current is the main achievement

  13. Gate Engineering in SOI LDMOS for Device Reliability

    Directory of Open Access Journals (Sweden)

    Aanand

    2016-01-01

    Full Text Available A linearly graded doping drift region with step gate structure, used for improvement of reduced surface field (RESURF SOI LDMOS transistor performance has been simulated with 0.35µm technology in this paper. The proposed device has one poly gate and double metal gate arranged in a stepped manner, from channel to drift region. The first gate uses n+ poly (near source where as other two gates of aluminium. The first gate with thin gate oxide has good control over the channel charge. The third gate with thick gate oxide at drift region reduce gate to drain capacitance. The arrangement of second and third gates in a stepped manner in drift region spreads the electric field uniformly. Using two dimensional device simulations, the proposed SOI LDMOS is compared with conventional structure and the extended metal structure. We demonstrate that the proposed device exhibits significant enhancement in linearity, breakdown voltage, on-resistance and HCI. Double metal gate reduces the impact ionization area which helps to improve the Hot Carrier Injection effect..

  14. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  15. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  16. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  17. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  18. Radiation Effects in Advanced Multiple Gate and Silicon-on-Insulator Transistors

    Science.gov (United States)

    Simoen, Eddy; Gaillardin, Marc; Paillet, Philippe; Reed, Robert A.; Schrimpf, Ron D.; Alles, Michael L.; El-Mamouni, Farah; Fleetwood, Daniel M.; Griffoni, Alessio; Claeys, Cor

    2013-06-01

    The aim of this review paper is to describe in a comprehensive manner the current understanding of the radiation response of state-of-the-art Silicon-on-Insulator (SOI) and FinFET CMOS technologies. Total Ionizing Dose (TID) response, heavy-ion microdose effects and single-event effects (SEEs) will be discussed. It is shown that a very high TID tolerance can be achieved by narrow-fin SOI FinFET architectures, while bulk FinFETs may exhibit similar TID response to the planar devices. Due to the vertical nature of FinFETs, a specific heavy-ion response can be obtained, whereby the angle of incidence becomes highly important with respect to the vertical sidewall gates. With respect to SEE, the buried oxide in the SOI FinFETs suppresses the diffusion tails from the charge collection in the substrate compared to the planar bulk FinFET devices. Channel lengths and fin widths are now comparable to, or smaller than the dimensions of the region affected by the single ionizing ions or lasers used in testing. This gives rise to a high degree of sensitivity to individual device parameters and source-drain shunting during ion-beam or laser-beam SEE testing. Simulations are used to illuminate the mechanisms observed in radiation testing and the progress and needs for the numerical modeling/simulation of the radiation response of advanced SOI and FinFET transistors are highlighted.

  19. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  20. Méditation et pratique de soi chez Malebranche.

    Directory of Open Access Journals (Sweden)

    Éric Dubreucq

    2004-04-01

    Full Text Available Une étude des Méditations pour se disposer à l’Humilité et à la pénitence qui les replace dans le cadre des pratiques de son époque, par exemple, chez François de Sales, celles de l’oraison, de la méditation et de la contemplation, permet d’apercevoir que l’une des thèses majeures du malebranchisme, la vision en Dieu, est un effet instauré dans le destinataire par un dispositif textuel. Celui-ci tire sa puissance prescriptive de l’a priori pratique où il s’inscrit. C’est à une opération de production de soi que l’exercice spirituel donne lieu : l’analyse des quatre premières Méditations chrétiennes et métaphysiques, en particulier, montre que c’est une organisation de la substance personnelle que provoque le travail spirituel sur soi. Celui-ci consiste à déterminer le rapport à soi comme relation d’une vision attentive à une activité illuminante, par un décentrement textuel du « je » vers le « tu ».One of the major Malebranche’s assertion, that we see truth in God, is not a mere theoretical thesis. I study first the Méditations pour se disposer à l’Humilité et à la pénitence and compare them with François de Sales’ spiritual exercitations, and show that prayer, meditation and contemplation constitute the practical frameworks of this period. The text of the Méditations is an apparatus which is fit to cause an effect in its target – the self of the reader : the vision in God. The practical a priori of the meditation provides the text with prescriptive power to transform the self. Then I study the Méditations chrétiennes et métaphysiques i-iv : we see that Malebranche set his textual apparatus so that it prescribes its receiver a form of « work-on-one’s-self ». The self is here produced by the organisation of relationship between attentive vision and lighting action, and this structure is built in the self by a movement, induced by the text, which leads the self from

  1. L’estime de soi : un cas particulier d’estime sociale ?

    OpenAIRE

    Santarelli, Matteo

    2016-01-01

    Un des traits plus originaux de la théorie intersubjective de la reconnaissance d’Axel Honneth, consiste dans la façon dont elle discute la relation entre estime sociale et estime de soi. En particulier, Honneth présente l’estime de soi comme un reflet de l’estime sociale au niveau individuel. Dans cet article, je discute cette conception, en posant la question suivante : l’estime de soi est-elle un cas particulier de l’estime sociale ? Pour ce faire, je me concentre sur deux problèmes crucia...

  2. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  3. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  4. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  5. Special Issue: Planar Fully-Depleted SOI technology

    Science.gov (United States)

    Allibert, F.; Hiramoto, T.; Nguyen, B. Y.

    2016-03-01

    We are in the era of mobile computing with smart handheld devices and remote data storage "in the cloud," with devices that are almost always on and driven by needs of high data transmission rate, instant access/connection and long battery life. With all the ambitious requirements for better performance with lower power consumption, the SoC solution must also be cost-effective in order to capture the large, highly-competitive consumer mobile and wearable markets. The Fully-Depleted SOI device/circuit is a unique option that can satisfy all these requirements and has made tremendous progress in development for various applications and adoption by foundries, integrated device manufacturers (IDM), and fabless companies in the last 3 years.

  6. InGaAs-OI Substrate Fabrication on a 300 mm Wafer

    Directory of Open Access Journals (Sweden)

    Sebastien Sollier

    2016-09-01

    Full Text Available In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs wafer on insulator (InGaAs-OI substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM, scanning acoustic microscopy (SAM, and HR-XRD, to insure the crystalline quality of the post transferred layer.

  7. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  8. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  9. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  10. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  11. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  12. Silicon-on-insulator-based polarization-independent 1×3 broadband beam splitter with adiabatic coupling

    Science.gov (United States)

    Gong, Yuanhao; Liu, Lei; Chang, Limin; Li, Zhiyong; Tan, Manqing; Yu, Yude

    2017-10-01

    We propose and numerically simulate a polarization-independent 1×3 broadband beam splitter based on silicon-on-insulator (SOI) technology with adiabatic coupling. The designed structure is simulated by beam-propagation-method (BPM) and gets simulated transmission uniformity of three outputs better than 0.3dB for TE-polarization and 0.8dB for TM-polarization in a broadband of 180nm.

  13. First results of a Double-SOI pixel chip for X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Yunpeng, E-mail: yplu@ihep.ac.cn [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Ouyang, Qun [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China); Arai, Yasuo [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Org., KEK, Tsukuba 305-0801 (Japan); Liu, Yi; Wu, Zhigang; Zhou, Yang [State Key Laboratory of Particle Detection and Electronics (Institute of High Energy Physics, CAS), Beijing 100049 (China)

    2016-09-21

    Aiming at low energy X-ray imaging, a prototype chip based on Double-SOI process was designed and tested. The sensor and pixel circuit were characterized. The long lasting crosstalk issue in SOI technology was understood. The operation of pixel was verified with a pulsed infrared laser beam. The depletion of sensor revealed by signal amplitudes is consistent with the one revealed by I–V curve. An s-curve fitting resulted in a sigma of 153 e{sup −} among which equivalent noise charge (ENC) contributed 113 e{sup −}. It's the first time that the crosstalk issue in SOI technology was solved and a counting type SOI pixel demonstrated the detection of low energy radiation quantitatively.

  14. New Insights into Fully-Depleted SOI Transistor Response During Total Dose Irradiation

    International Nuclear Information System (INIS)

    Burns, J.A.; Dodd, P.E.; Keast, C.L.; Schwank, J.R.; Shaneyfelt, M.R.; Wyatt, P.W.

    1999-01-01

    Worst-case bias configuration for total-dose testing fully-depleted SOI transistors was found to be process dependent. No evidence was found for total-dose induced snap back. These results have implications for hardness assurance testing

  15. A novel self-aligned oxygen (SALOX) implanted SOI MOSFET device structure

    Science.gov (United States)

    Tzeng, J. C.; Baerg, W.; Ting, C.; Siu, B.

    The morphology of the novel self-aligned oxygen implanted SOI (SALOX SOI) [1] MOSFET was studied. The channel silicon of SALOX SOI was confirmed to be undamaged single crystal silicon and was connected with the substrate. Buried oxide formed by oxygen implantation in this SALOX SOI structure was shown by a cross section transmission electron micrograph (X-TEM) to be amorphous. The source/drain silicon on top of the buried oxide was single crystal, as shown by the transmission electron diffraction (TED) pattern. The source/drain regions were elevated due to the buried oxide volume expansion. A sharp silicon—silicon dioxide interface between the source/drain silicon and buried oxide was observed by Auger electron spectroscopy (AES). Well behaved n-MOS transistor current voltage characteristics were obtained and showed no I-V kink.

  16. A PD-SOI based DTI-LOCOS combined cross isolation technique for minimizing TID radiation induced leakage in high density memory

    International Nuclear Information System (INIS)

    Qiao Fengying; Pan Liyang; Wu Dong; Liu Lifang; Xu Jun

    2014-01-01

    In order to minimize leakage current increase under total ionizing dose (TID) radiation in high density memory circuits, a new isolation technique, combining deep trench isolation (DTI) between the wells, local oxidation of silicon (LOCOS) isolation between the devices within the well, and a P-diffused area in order to limit leakage at the isolation edge is implemented in partly-depleted silicon-on-insulator (PD-SOI) technology. This radiation hardening technique can minimize the layout area by more than 60%, and allows flexible placement of the body contact. Radiation hardened transistors and 256 Kb flash memory chips are designed and fabricated in a 0.6 μm PD-SOI process. Experiments show that no obvious increase in leakage current is observed for single transistors under 1 Mrad(Si) radiation, and that the 256 Kb memory chip still functions well after a TID of 100 krad(Si), with only 50% increase of the active power consumption in read mode. (semiconductor devices)

  17. arXiv Charge collection properties in an irradiated pixel sensor built in a thick-film HV-SOI process

    CERN Document Server

    INSPIRE-00541780; Cindro, V.; Gorišek, A.; Hemperek, T.; Kishishita, T.; Kramberger, G.; Krüger, H.; Mandić, I.; Mikuž, M.; Wermes, N.; Zavrtanik, M.

    2017-10-25

    Investigation of HV-CMOS sensors for use as a tracking detector in the ATLAS experiment at the upgraded LHC (HL-LHC) has recently been an active field of research. A potential candidate for a pixel detector built in Silicon-On-Insulator (SOI) technology has already been characterized in terms of radiation hardness to TID (Total Ionizing Dose) and charge collection after a moderate neutron irradiation. In this article we present results of an extensive irradiation hardness study with neutrons up to a fluence of 1x10e16 neq/cm2. Charge collection in a passive pixelated structure was measured by Edge Transient Current Technique (E-TCT). The evolution of the effective space charge concentration was found to be compliant with the acceptor removal model, with the minimum of the space charge concentration being reached after 5x10e14 neq/cm2. An investigation of the in-pixel uniformity of the detector response revealed parasitic charge collection by the epitaxial silicon layer characteristic for the SOI design. The r...

  18. Le soi et l’estime de soi chez l’enfant: Une revue systématique de la littérature

    OpenAIRE

    Pinto, Alexandra Maria Pereira Inácio Sequeira; Gatinho, Ana Rita dos Santos; Tereno, Susana; Veríssimo, Manuela

    2016-01-01

    Cette étude vise : a) à analyser les différentes méthodes utilisées pour l’étude du Soi et chez les enfants, en ce que concerne sa qualité et son potentiel et b) à synthétiser les résultats déjà obtenus en termes de Soi/d’estime de soi/d’autoconcept, pour les enfants en âge préscolaire. Après avoir établi des critères rigoureux d’inclusion et d’exclusion, 33 articles ont été sélectionnés, dans plusieurs bases de données, nationales et international...

  19. Deep sub-micron FD-SOI for front-end application

    International Nuclear Information System (INIS)

    Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

    2007-01-01

    In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

  20. Micromachined thin-film sensors for SOI-CMOS co-integration

    CERN Document Server

    Laconte, Jean; Raskin, Jean-Pierre

    2006-01-01

    Co-integration of MEMS and MOS in SOI technology is promising and well demonstrated hereThe impact of Micromachining on SOI devices is deeply analyzed for the first timeInclude extensive TMAH etching, residual stress, microheaters, gas-flow sensors reviewResidual stresses in thin films need to be more and more monitored in MEMS designsTMAH micromachining is an attractive alternative to KOH.

  1. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  2. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    International Nuclear Information System (INIS)

    Zhang, Z.L.; Asano, T.; Uno, H.; Tero, R.; Suzui, M.; Nakao, S.; Kaito, T.; Shibasaki, K.; Tominaga, M.; Utsumi, Y.; Gao, Y.L.; Urisu, T.

    2008-01-01

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 μm diameter is formed through the top Si layer and the SiO 2 box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully

  3. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Science.gov (United States)

    Wu, Jiayang; Moein, Tania; Xu, Xingyuan; Moss, David J.

    2018-04-01

    We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI) nanowires implemented by cascaded Sagnac loop reflector (CSLR) resonators. We investigate mode splitting in these standing-wave (SW) resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs) and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  4. Fabrication of Si-based planar type patch clamp biosensor using silicon on insulator substrate

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Z.L.; Asano, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Uno, H. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Tero, R. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Suzui, M.; Nakao, S. [Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan); Kaito, T. [SII NanoTechnology Inc., 36-1, Takenoshita, Oyama-cho, Sunto-gun, Shizuoka, 410-1393 (Japan); Shibasaki, K.; Tominaga, M. [Okazaki Institute for Integrative Bioscience, 5-1, Higashiyama, Myodaiji, Okazaki, 444-8787 (Japan); Utsumi, Y. [Laboratory of Advanced Science and Technology for Industry, University of Hyogo, 3-1-2, Koto, Kamigori, Ako-gun, Hyogo, 678-1205 (Japan); Gao, Y.L. [Department of Physics and Astronomy, Rochester University, Rochester, New York 14627 (United States); Urisu, T. [Graduate University for Advanced Studies, Myodaiji, Okazaki, 444-8585 (Japan); Institute for Molecular Science, Myodaiji, Okazaki, 444-8585 (Japan)], E-mail: urisu@ims.ac.jp

    2008-03-03

    The aim of this paper is to fabricate the planar type patch clamp ion-channel biosensor, which is suitable for the high throughput screening, using silicon-on-insulator (SOI) substrate. The micropore with 1.2 {mu}m diameter is formed through the top Si layer and the SiO{sub 2} box layer of the SOI substrate by focused ion beam (FIB). Then the substrate is assembled into the microfluidic circuit. The human embryonic kidney 293 (HEK-293) cell transfected with transient receptor potential vanilloid type 1 (TRPV1) is positioned on the micropore and the whole-cell configuration is formed by the suction. Capsaicin is added to the extracellular solution as a ligand molecule, and the channel current showing the desensitization unique to TRPV1 is measured successfully.

  5. A novel double gate MOSFET by symmetrical insulator packets with improved short channel effects

    Science.gov (United States)

    Ramezani, Zeinab; Orouji, Ali A.

    2018-03-01

    In this article, we study a novel double-gate SOI MOSFET structure incorporating insulator packets (IPs) at the junction between channel and source/drain (S/D) ends. The proposed MOSFET has great strength in inhibiting short channel effects and OFF-state current that are the main problems compared with conventional one due to the significant suppressed penetrations of both the lateral electric field and the carrier diffusion from the S/D into the channel. Improvement of the hot electron reliability, the ON to OFF drain current ratio, drain-induced barrier lowering, gate-induced drain leakage and threshold voltage over conventional double-gate SOI MOSFETs, i.e. without IPs, is displayed with the simulation results. This study is believed to improve the CMOS device reliability and is suitable for the low-power very-large-scale integration circuits.

  6. Advanced photonic filters based on cascaded Sagnac loop reflector resonators in silicon-on-insulator nanowires

    Directory of Open Access Journals (Sweden)

    Jiayang Wu

    2018-04-01

    Full Text Available We demonstrate advanced integrated photonic filters in silicon-on-insulator (SOI nanowires implemented by cascaded Sagnac loop reflector (CSLR resonators. We investigate mode splitting in these standing-wave (SW resonators and demonstrate its use for engineering the spectral profile of on-chip photonic filters. By changing the reflectivity of the Sagnac loop reflectors (SLRs and the phase shifts along the connecting waveguides, we tailor mode splitting in the CSLR resonators to achieve a wide range of filter shapes for diverse applications including enhanced light trapping, flat-top filtering, Q factor enhancement, and signal reshaping. We present the theoretical designs and compare the CSLR resonators with three, four, and eight SLRs fabricated in SOI. We achieve versatile filter shapes in the measured transmission spectra via diverse mode splitting that agree well with theory. This work confirms the effectiveness of using CSLR resonators as integrated multi-functional SW filters for flexible spectral engineering.

  7. The Microwave Noise Behaviour Of Dual Material Gate Silicon On Insulator

    Science.gov (United States)

    Jafar, N.; Soin, N.

    2009-06-01

    This work presents the noise behaviour due to the applied Dual Material Gate (DMG) on the 75 nm n-channel Silicon On Insulator (SOI) device operating in the fully depletion mode, particularly for microwave circuit design. Influences of DMG properties namely the gate length ratio (L1:L2) and gate material workfunction difference (ΔΦM) as well as structural and operational parameters which are silicon thickness (TSi) and threshold voltage (VTH) setting variation on the noise performance were carried out on simulation basis using ATLAS 2D. Results show better noise performance in DMG as compare to the standard gate structure of FD-SOI devices. Higher VTH for DMG design is recommended for minimized noise figure in line with the advantage of inverse VTH roll-off characteristics for short channel effects suppression.

  8. Preliminary Investigation of an SOI-based Arrayed Waveguide Grating Demodulation Integration Microsystem

    Science.gov (United States)

    Li, Hongqiang; Zhou, Wenqian; Liu, Yu; Dong, Xiaye; Zhang, Cheng; Miao, Changyun; Zhang, Meiling; Li, Enbang; Tang, Chunxiao

    2014-05-01

    An arrayed waveguide grating (AWG) demodulation integration microsystem is investigated in this study. The system consists of a C-band on-chip LED, a 2 × 2 silicon nanowire-based coupler, a fiber Bragg grating (FBG) array, a 1 × 8 AWG, and a photoelectric detector array. The coupler and AWG are made from silicon-on-insulator wafers using electron beam exposure and response-coupled plasma technology. Experimental results show that the excess loss in the MMI coupler with a footprint of 6 × 100 μm2 is 0.5423 dB. The 1 × 8 AWG with a footprint of 267 × 381 μm2 and a waveguide width of 0.4 μm exhibits a central channel loss of -3.18 dB, insertion loss non-uniformity of -1.34 dB, and crosstalk level of -23.1 dB. The entire system is preliminarily tested. Wavelength measurement precision is observed to reach 0.001 nm. The wavelength sensitivity of each FBG is between 0.04 and 0.06 nm/dB.

  9. Economically optimal thermal insulation

    Energy Technology Data Exchange (ETDEWEB)

    Berber, J.

    1978-10-01

    Exemplary calculations to show that exact adherence to the demands of the thermal insulation ordinance does not lead to an optimal solution with regard to economics. This is independent of the mode of financing. Optimal thermal insulation exceeds the values given in the thermal insulation ordinance.

  10. Thermal processing of strained silicon-on-insulator for atomically precise silicon device fabrication

    International Nuclear Information System (INIS)

    Lee, W.C.T.; Bishop, N.; Thompson, D.L.; Xue, K.; Scappucci, G.; Cederberg, J.G.; Gray, J.K.; Han, S.M.; Celler, G.K.; Carroll, M.S.; Simmons, M.Y.

    2013-01-01

    Highlights: ► Strained silicon-on-insulator (sSOI) samples were flash-annealed at high temperature under ultra-high vacuum conditions. ► The extend of surface strain relaxation depends on the annealing temperature with no strain relaxation observed below 1020 °C. ► A 2 × 1 reconstructed surface with low defect density can be achieved. ► The annealed sSOI surface shows enhanced step undulations due to the unique energetics caused by surface strain. - Abstract: We investigate the ability to reconstruct strained silicon-on-insulator (sSOI) substrates in ultra-high vacuum for use in atomic scale device fabrication. Characterisation of the starting sSOI substrate using μRaman shows an average tensile strain of 0.8%, with clear strain modulation in a crosshatch pattern across the surface. The surfaces were heated in ultra-high vacuum from temperatures of 900 °C to 1100 °C and subsequently imaged using scanning tunnelling microscopy (STM). The initial strain modulation on the surface is observed to promote silicon migration and the formation of crosshatched surface features whose height and pitch increases with increasing annealing temperature. STM images reveal alternating narrow straight S A steps and triangular wavy S B steps attributed to the spontaneous faceting of S B and preferential adatom attachment on S B under biaxial tensile strain. Raman spectroscopy shows that despite these high temperature anneals no strain relaxation of the substrate is observed up to temperatures of 1020 °C. Above 1100 °C, strain relaxation is evident but is confined to the surface.

  11. Analytical Subthreshold Current and Subthreshold Swing Models for a Fully Depleted (FD) Recessed-Source/Drain (Re-S/D) SOI MOSFET with Back-Gate Control

    Science.gov (United States)

    Saramekala, Gopi Krishna; Tiwari, Pramod Kumar

    2017-08-01

    Two-dimensional (2D) analytical models for the subthreshold current and subthreshold swing of the back-gated fully depleted recessed-source/drain (Re-S/D) silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistor (MOSFET) are presented. The surface potential is determined by solving the 2D Poisson equation in both channel and buried-oxide (BOX) regions, considering suitable boundary conditions. To derive closed-form expressions for the subthreshold characteristics, the virtual cathode potential expression has been derived in terms of the minimum of the front and back surface potentials. The effect of various device parameters such as gate oxide and Si film thicknesses, thickness of source/drain penetration into BOX, applied back-gate bias voltage, etc. on the subthreshold current and subthreshold swing has been analyzed. The validity of the proposed models is established using the Silvaco ATLAS™ 2D device simulator.

  12. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  13. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  14. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  15. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  16. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  17. Surface electrical resistivity of insulators

    International Nuclear Information System (INIS)

    Senn, B. C.; Liesegang, J.

    1996-01-01

    A method is presented here for measuring surface charge decay, and theory has been developed so as to produce determinations of resistivity in the surface region of insulator films or wafers. This method incorporates the use of a coaxial cylindrical capacitor arrangement and an electrometer interfaced to a PC. The charge transport theory given here is based on Mott-Gurney diffusion, and allows easy interpretation of the experimental data, especially for the initial phase of surface charge decay. Resistivity measurements are presented for glass, mica, perspex and polyethylene, covering a range of 10 9 to 10 18 Ωm, as an illustration of the useful range of the instrument for static and antistatic materials, particularly in film or sheet form. Values for the surface charge diffusion constants of the materials are also presented. The charge transport theory has also been extended to allow the experimental and computational theoretical comparison of surface charge decay not only over the initial phase of charge decay, but also over longer times. The theoretical predictions show excellent agreement with experiment using the values for the diffusion constants referred to above

  18. Thermal insulating panel

    Energy Technology Data Exchange (ETDEWEB)

    Hughes, J.T.

    1985-09-11

    A panel of thermal insulation material has at least one main portion which comprises a dry particulate insulation material compressed within a porous envelope so that it is rigid or substantially rigid and at least one auxiliary portion which is secured to and extends along at least one of the edges of the main portions. The auxiliary portions comprise a substantially uncompressed dry particulate insulation material contained within an envelope. The insulation material of the auxiliary portion may be the same as or may be different from the insulation material of the main portion. The envelope of the auxiliary portion may be made of a porous or a non-porous material. (author).

  19. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  20. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  1. Nondestructive evaluation of differently doped InP wafers by time-resolved four-wave mixing technique

    International Nuclear Information System (INIS)

    Kadys, A.; Sudzius, M.; Jarasiunas, K.; Mao Luhong; Sun Niefeng

    2006-01-01

    Photoelectric properties of semi-insulating, differently doped, and undoped indium phosphide wafers, grown by the liquid encapsulation Czochralski method, have been investigated by time-resolved picosecond four-wave mixing technique. Deep defect related carrier generation, recombination, and transport properties were investigated experimentally by measuring four-wave mixing kinetics and exposure characteristics. The presence of deep donor states in undoped InP was confirmed by a pronounced effect of a space charge electric field to carrier transport. On the other hand, the recharging dynamics of electrically active residual impurities was observed in undoped and Fe-doped InP through the process of efficient trapping of excess carriers. The bipolar diffusion coefficients and mobilities were determined for the all wafers

  2. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  3. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  4. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  5. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  6. Capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator

    International Nuclear Information System (INIS)

    Kim, Tae-Hyun; Park, Jea-Gun

    2013-01-01

    We investigated the combined effect of the strained Si channel and hole confinement on the memory margin enhancement for a capacitor-less memory cell fabricated on nano-scale strained Si on a relaxed SiGe layer-on-insulator (ε-Si SGOI). The memory margin for the ε-Si SGOI capacitor-less memory cell was higher than that of the memory cell fabricated on an unstrained Si-on-insulator (SOI) and increased with increasing Ge concentration of the relaxed SiGe layer; i.e. the memory margin for the ε-Si SGOI capacitor-less memory cell (138.6 µA) at a 32 at% Ge concentration was 3.3 times higher than the SOI capacitor-less memory cell (43 µA). (paper)

  7. Panels of microporous insulation

    Energy Technology Data Exchange (ETDEWEB)

    McWilliams, J.A.; Morgan, D.E.; Jackson, J.D.J.

    1990-08-07

    Microporous thermal insulation materials have a lattice structure in which the average interstitial dimension is less than the mean free path of the molecules of air or other gas in which the material is arranged. This results in a heat flow which is less than that attributable to the molecular heat diffusion of the gas. According to this invention, a method is provided for manufacturing panels of microporous thermal insulation, in particular such panels in which the insulation material is bonded to a substrate. The method comprises the steps of applying a film of polyvinyl acetate emulsion to a non-porous substrate, and compacting powdery microporous thermal insulation material against the film so as to cause the consolidated insulation material to bond to the substrate and form a panel. The polyvinyl acetate may be applied by brushing or spraying, and is preferably allowed to dry prior to compacting the insulation material. 1 fig.

  8. Wall insulation system

    Energy Technology Data Exchange (ETDEWEB)

    Kostek, P.T.

    1987-08-11

    In a channel specially designed to fasten semi-rigid mineral fibre insulation to masonry walls, it is known to be constructed from 20 gauge galvanized steel or other suitable material. The channel is designed to have pre-punched holes along its length for fastening of the channel to the drywall screw. The unique feature of the channel is the teeth running along its length which are pressed into the surface of the butted together sections of the insulation providing a strong grip between the two adjacent pieces of insulation. Of prime importance to the success of this system is the recent technological advancements of the mineral fibre itself which allow the teeth of the channel to engage the insulation fully and hold without mechanical support, rather than be repelled or pushed back by the inherent nature of the insulation material. After the insulation is secured to the masonry wall by concrete nail fastening systems, the drywall is screwed to the channel.

  9. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  10. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  11. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  12. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  13. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  14. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  15. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  16. Broadband Silicon-On-Insulator directional couplers using a combination of straight and curved waveguide sections.

    Science.gov (United States)

    Chen, George F R; Ong, Jun Rong; Ang, Thomas Y L; Lim, Soon Thor; Png, Ching Eng; Tan, Dawn T H

    2017-08-03

    Broadband Silicon-On-Insulator (SOI) directional couplers are designed based on a combination of curved and straight coupled waveguide sections. A design methodology based on the transfer matrix method (TMM) is used to determine the required coupler section lengths, radii, and waveguide cross-sections. A 50/50 power splitter with a measured bandwidth of 88 nm is designed and fabricated, with a device footprint of 20 μm × 3 μm. In addition, a balanced Mach-Zehnder interferometer is fabricated showing an extinction ratio of >16 dB over 100 nm of bandwidth.

  17. Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

    International Nuclear Information System (INIS)

    Margail, J.

    1987-03-01

    Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

  18. Guided acoustic and optical waves in silicon-on-insulator for Brillouin scattering and optomechanics

    Directory of Open Access Journals (Sweden)

    Christopher J. Sarabalis

    2016-10-01

    Full Text Available We numerically study silicon waveguides on silica showing that it is possible to simultaneously guide optical and acoustic waves in the technologically important silicon on insulator (SOI material system. Thin waveguides, or fins, exhibit geometrically softened mechanical modes at gigahertz frequencies with phase velocities below the Rayleigh velocity in glass, eliminating acoustic radiation losses. We propose slot waveguides on glass with telecom optical frequencies and strong radiation pressure forces resulting in Brillouin gains on the order of 500 and 50 000 W−1m−1 for backward and forward Brillouin scattering, respectively.

  19. Synthesis of highly integrated optical network based on microdisk-resonator add-drop filters in silicon-on-insulator technology

    Science.gov (United States)

    Kaźmierczak, Andrzej; Dortu, Fabian; Giannone, Domenico; Bogaerts, Wim; Drouard, Emmanuel; Rojo-Romeo, Pedro; Gaffiot, Frederic

    2009-10-01

    We analyze a highly compact optical add-drop filter topology based on a pair of microdisk resonators and a bus waveguide intersection. The filter is further assessed on an integrated optical 4×4 network for optical on-chip communication. The proposed network structure, as compact as 50×50 μm, is fabricated in a CMOS-compatible process on a silicon-on-insulator (SOI) substrate. Finally, the experimental results demonstrate the proper operation of the fabricated devices.

  20. Investigation of charge-collection efficiency of Kyoto's X-ray astronomical SOI pixel sensors, XRPIX

    Energy Technology Data Exchange (ETDEWEB)

    Matsumura, Hideaki, E-mail: matumura@cr.scphys.kyoto-u.ac.jp [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa Oiwake-cho, Sakyo-ku, Kyoto 606-8502 (Japan); Tsuru, Takeshi Go; Tanaka, Takaaki; Nakashima, Shinya; Ryu, Syukyo G. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa Oiwake-cho, Sakyo-ku, Kyoto 606-8502 (Japan); Takeda, Ayaki [Department of Particle and Nuclear Physics, Graduate School of High Energy Accelerator Science, The Graduate University for Advanced Studies (SOKENDAI), High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Arai, Yasuo; Miyoshi, Toshinobu [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), Tsukuba 305-0801 (Japan)

    2014-11-21

    We are developing a monolithic active pixel sensor referred to as XRPIX for X-ray astronomy on the basis of silicon-on-insulator CMOS technology. A crucial issue in our recent development is the impact of incomplete charge collection on the spectroscopic performance. In this paper, we report the spectral responses of several devices having different intra-pixel structures or produced from different wafers. We found that an emission line spectrum exhibits large low-energy tails when the size of the buried p-well, which acts as the charge-collection node, is small. Moreover, in charge sharing events, the peak channels of the emission lines shift toward channels lower than those without charge sharing. This peak shift is more pronounced as the distance between the pixel center and the position of incident photon increases. This suggests that the charge-collection efficiency is degraded at the pixel boundary. We also found that the charge-collection efficiency depends on the strength of the electric field at the interface of the depletion and insulator layers.

  1. Sub-50 nm gate length SOI transistor development for high performance microprocessors

    International Nuclear Information System (INIS)

    Horstmann, M.; Greenlaw, D.; Feudel, Th.; Wei, A.; Frohberg, K.; Burbach, G.; Gerhardt, M.; Lenski, M.; Stephan, R.; Wieczorek, K.; Schaller, M.; Hohage, J.; Ruelke, H.; Klais, J.; Huebler, P.; Luning, S.; Bentum, R. van; Grasshoff, G.; Schwan, C.; Cheek, J.; Buller, J.; Krishnan, S.; Raab, M.; Kepler, N.

    2004-01-01

    Partial depleted (PD) SOI technologies have reached maturity for production of high speed, low power microprocessors. The paper will highlight several challenges found during the course of development for bringing 40 nm gate length (L GATE ) PD SOI transistors into volume manufacturing for high-speed microprocessors. The key innovations developed for this transistor in order to overcome classical gate oxide and L GATE scaling is an unique differential triple spacer structure, stressed overlayer films inducing strain in the Silicon channel and optimized junctions. This transistor structure yields an outstanding ring oscillator speed with an unloaded inverter delay of 5.5 ps. The found improvements are highly manufacturable and scaleable for future device technologies like FD SOI

  2. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  3. Radiation hard pixel sensors using high-resistive wafers in a 150 nm CMOS processing line

    Science.gov (United States)

    Pohl, D.-L.; Hemperek, T.; Caicedo, I.; Gonella, L.; Hügging, F.; Janssen, J.; Krüger, H.; Macchiolo, A.; Owtscharenko, N.; Vigani, L.; Wermes, N.

    2017-06-01

    Pixel sensors using 8'' CMOS processing technology have been designed and characterized offering the benefits of industrial sensor fabrication, including large wafers, high throughput and yield, as well as low cost. The pixel sensors are produced using a 150 nm CMOS technology offered by LFoundry in Avezzano. The technology provides multiple metal and polysilicon layers, as well as metal-insulator-metal capacitors that can be employed for AC-coupling and redistribution layers. Several prototypes were fabricated and are characterized with minimum ionizing particles before and after irradiation to fluences up to 1.1 × 1015 neq cm-2. The CMOS-fabricated sensors perform equally well as standard pixel sensors in terms of noise and hit detection efficiency. AC-coupled sensors even reach 100% hit efficiency in a 3.2 GeV electron beam before irradiation.

  4. Large Out-of-Plane Displacement Bistable Electromagnetic Microswitch on a Single Wafer.

    Science.gov (United States)

    Miao, Xiaodan; Dai, Xuhan; Huang, Yi; Ding, Guifu; Zhao, Xiaolin

    2016-05-05

    This paper presents a bistable microswitch fully batch-fabricated on a single glass wafer, comprising of a microactuator, a signal transformer, a microspring and a permanent magnet. The bistable mechanism of the microswitch with large displacement of 160 μm depends on the balance of the magnetic force and elastic force. Both the magnetic force and elastic force were optimized by finite-element simulation to predict the reliable of the device. The prototype was fabricated and characterized. By utilizing thick laminated photoresist sacrificial layer, the large displacement was obtained to ensure the insulation of the microswitch. The testing results show that the microswitch realized the bistable mechanism at a 3-5 V input voltage and closed in 0.96 ms, which verified the simulation.

  5. Charge collection mechanisms in MOS/SOI transistors irradiated by energetic heavy ions

    International Nuclear Information System (INIS)

    Musseau, O.; Leray, J.L.; Ferlet, V.; Umbert, A.; Coic, Y.M.; Hesto, P.

    1991-01-01

    We have investigated with both experimental and numerical methods (Monte Carlo and drift-diffusion models) various charge collection mechanisms in NMOS/SOI transistors irradiated by single energetic heavy ions. Our physical interpretations of data emphasize the influence of various parasitic structures of the device. Two charge collection mechanisms are detailed: substrate funneling in buried MOS capacitor and latching of the parasitic bipolar transistor. Based on carrier transport and charge collection, the sensitivity of future scaled down CMOS/SOI technologies is finally discussed

  6. Translucent insulating building envelope

    DEFF Research Database (Denmark)

    Rahbek, Jens Eg

    1997-01-01

    A new type of translucent insulating material has been tested. This material is made of Celulose-Acetat and have a honey-comb structure. The material has a high solar transmittance and is highly insulating. The material is relatively cheap to produce. Danish Title: Translucent isolerende klimaskærm....

  7. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  8. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  9. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  10. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  11. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  12. Investigation of the Low-Temperature Behavior of FD-SOI MOSFETs in the Saturation Regime Using Y and Z Functions

    Directory of Open Access Journals (Sweden)

    A. Karsenty

    2014-01-01

    Full Text Available The saturation regime of two types of fully depleted (FD SOI MOSFET devices was studied. Ultrathin body (UTB and gate recessed channel (GRC devices were fabricated simultaneously on the same silicon wafer through a selective “gate recessed” process. They share the same W/L ratio but have a channel film thickness of 46 nm and 2.2 nm, respectively. Their standard characteristics (IDS-VDS and IDS-VGS of the devices were measured at room temperature before cooling down to 77 K. Surprisingly, their respective temperature dependence is found to be opposite. In this paper, we focus our comparative analysis on the devices' conduction using a Y-function applied to the saturation domain. The influence of the temperature in this domain is presented for the first time. We point out the limits of the Y-function analysis and show that a new function called Z can be used to extract the series resistance in the saturation regime.

  13. Sound Insulation between Dwellings

    DEFF Research Database (Denmark)

    Rasmussen, Birgit

    2011-01-01

    Regulatory sound insulation requirements for dwellings exist in more than 30 countries in Europe. In some countries, requirements have existed since the 1950s. Findings from comparative studies show that sound insulation descriptors and requirements represent a high degree of diversity...... and initiate – where needed – improvement of sound insulation of new and existing dwellings in Europe to the benefit of the inhabitants and the society. A European COST Action TU0901 "Integrating and Harmonizing Sound Insulation Aspects in Sustainable Urban Housing Constructions", has been established and runs...... 2009-2013. The main objectives of TU0901 are to prepare proposals for harmonized sound insulation descriptors and for a European sound classification scheme with a number of quality classes for dwellings. Findings from the studies provide input for the discussions in COST TU0901. Data collected from 24...

  14. A multi-level capacitor-less memory cell fabricated on a nano-scale strained silicon-on-insulator

    International Nuclear Information System (INIS)

    Park, Jea-Gun; Kim, Seong-Je; Shin, Mi-Hee; Song, Seung-Hyun; Shim, Tae-Hun; Chung, Sung-Woong; Enomoto, Hirofumi

    2011-01-01

    A multi-level capacitor-less memory cell was fabricated with a fully depleted n-metal-oxide-semiconductor field-effect transistor on a nano-scale strained silicon channel on insulator (FD sSOI n-MOSFET). The 0.73% biaxial tensile strain in the silicon channel of the FD sSOI n-MOSFET enhanced the effective electron mobility to ∼ 1.7 times that with an unstrained silicon channel. This thereby enables both front- and back-gate cell operations, demonstrating eight-level volatile memory-cell operation with a 1 ms retention time and 12 μA memory margin. This is a step toward achieving a terabit volatile memory cell.

  15. A rugged 650 V SOI-based high-voltage half-bridge IGBT gate driver IC for motor drive applications

    Science.gov (United States)

    Hua, Qing; Li, Zehong; Zhang, Bo; Chen, Weizhong; Huang, Xiangjun; Feng, Yuxiang

    2015-05-01

    This paper proposes a rugged high-voltage N-channel insulated gate bipolar transistor (IGBT) gate driver integrated circuit. The device integrates a high-side and a low-side output stages on a single chip, which is designed specifically for motor drive applications. High-voltage level shift technology enables the high-side stage of this device to operate up to 650 V. The logic inputs are complementary metal oxide semiconductor (CMOS)/transistor transistor logic compatible down to 3.3 V. Undervoltage protection functionality with hysteresis characteristic has also been integrated to enhance the device reliability. The device is fabricated in a 1.0 μm, 650 V high-voltage bipolar CMOS double-diffused metal oxide semiconductor (BCD) on silicon-on-insulator (SOI) process. Deep trench dielectric isolation technology is employed to provide complete electrical isolation with advantages such as reduced parasitic effects, excellent noise immunity and low leakage current. Experimental results show that the isolation voltage of this device can be up to approximately 779 V at 25°C, and the leakage current is only 5 nA at 650 V, which is 15% higher and 67% lower than the conventional ones. In addition, it delivers an excellent thermal stability and needs very low quiescent current and offers a high gate driver capability which is needed to adequately drive IGBTs that have large input capacitances.

  16. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  17. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  18. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  19. Investigation of piezoresistive effect in p-channel metal–oxide–semiconductor field-effect transistors fabricated on circular silicon-on-insulator diaphragms using cost-effective minimal-fab process

    Science.gov (United States)

    Liu, Yongxun; Tanaka, Hiroyuki; Umeyama, Norio; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2018-06-01

    P-channel metal–oxide–semiconductor field-effect transistors (PMOSFETs) with the 〈110〉 or 〈100〉 channel direction have been successfully fabricated on circular silicon-on-insulator (SOI) diaphragms using a cost-effective minimal-fab process, and their electrical characteristics have been systematically investigated before and after the SOI diaphragm formation. It was found that almost the same subthreshold slope (S-slope) and threshold voltage (V t) are observed in the fabricated PMOSFETs before and after the SOI diaphragm formation, and they are independent of the channel direction. On the other hand, significant variations in drain current were observed in the fabricated PMOSFETs with the 〈110〉 channel direction after the SOI diaphragm formation owing to the residual mechanical stress-induced piezoresistive effect. It was also confirmed that electrical characteristics of the fabricated PMOSFETs with the 〈100〉 channel direction are almost the same before and after the SOI diaphragm formation, i.e., not sensitive to the mechanical stress. Moreover, the drain current variations at different directions of mechanical stress and current flow were systematically investigated and discussed.

  20. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  1. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Energy Technology Data Exchange (ETDEWEB)

    Daix, N., E-mail: dai@zurich.ibm.com; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Fompeyrine, J. [IBM Research - Zürich, Säumerstrasse 4, CH-8803 Rüschlikon (Switzerland); Hartmann, J. M. [CEA, LETI 17, rue des Martyrs, F-38054 Grenoble (France); Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D. [IBM T. J. Watson Research Center, 1101 Kitchawan Rd., Route 134 Yorktown Heights, New York 10598 (United States)

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In{sub 0.53}Ga{sub 0.47}As (InGaAs) active layer is equal to 3.5 × 10{sup 9} cm{sup −2}, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm{sup 2}/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm{sup 2}/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  2. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Science.gov (United States)

    Daix, N.; Uccelli, E.; Czornomaz, L.; Caimi, D.; Rossel, C.; Sousa, M.; Siegwart, H.; Marchiori, C.; Hartmann, J. M.; Shiu, K.-T.; Cheng, C.-W.; Krishnan, M.; Lofaro, M.; Kobayashi, M.; Sadana, D.; Fompeyrine, J.

    2014-08-01

    We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I) fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs) active layer is equal to 3.5 × 109 cm-2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000-3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  3. Heat insulation support device

    International Nuclear Information System (INIS)

    Takahashi, Hiroyuki; Koda, Tomokazu; Motojima, Osamu; Yamamoto, Junya.

    1994-01-01

    The device of the present invention comprises a plurality of heat insulation legs disposed in a circumferential direction. Each of the heat insulative support legs has a hollow shape, and comprises an outer column and an inner column as support structures having a heat insulative property (heat insulative structure), and a thermal anchor which absorbs compulsory displacement by a thin flat plate (displacement absorber). The outer column, the thermal anchor and the inner column are connected by a support so as to offset the positional change of objects to be supported due to shrinkage when they are shrunk. In addition, the portion between the superconductive coils as the objects to be supported and the inner column is connected by the support. The superconductive thermonuclear device is entirely contained in a heat insulative vacuum vessel, and the heat insulative support legs are disposed on a lower lid of the heat insulative vacuum vessel. With such a constitution, they are strengthened against lateral load and buckling, thereby enabling to reduce the amount of heat intrusion while keeping the compulsory displacement easy to be absorbed. (I.N.)

  4. Extreme group index measured and calculated in 2D SOI-based photonic crystal waveguides

    DEFF Research Database (Denmark)

    Lavrinenko, Andrei; Jacobsen, Rune Shim; Fage-Pedersen, Jacob

    2005-01-01

    lattice of air-holes in the 216-nm thick silicon layer in an SOI material. Experimental transmission spectra show a mode cut-off around 1562.5 nm for the fundamental photonic bandgap mode. In order to measure and model the group index of modes in the PCW, a time-of-flight (ToF) method is applied....

  5. Band to Band Tunneling (BBT) Induced Leakage Current Enhancement in Irradiated Fully Depleted SOI Devices

    Science.gov (United States)

    Adell, Phillipe C.; Barnaby, H. J.; Schrimpf, R. D.; Vermeire, B.

    2007-01-01

    We propose a model, validated with simulations, describing how band-to-band tunneling (BBT) affects the leakage current degradation in some irradiated fully-depleted SOI devices. The dependence of drain current on gate voltage, including the apparent transition to a high current regime is explained.

  6. Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks

    Science.gov (United States)

    Dogan, Numan S.

    2003-01-01

    The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.

  7. Juan Goytisolo: Le soi, le monde et la création littéraire

    Directory of Open Access Journals (Sweden)

    Pablo Romero Alegría

    2010-01-01

    Full Text Available Reseña de la obra: Yannick Llored. Le soi, le monde et la création littéraire. Presses Universitaires du Septentrion. Villeneuve d’Ascq (Francia. 2009. 421 págs. ISBN: 978-2-75740-0089-0

  8. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  9. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  10. Vacuum foil insulation system

    International Nuclear Information System (INIS)

    Hanson, J.P.; Sabolcik, R.E.; Svedberg, R.C.

    1976-01-01

    In a multifoil thermal insulation package having a plurality of concentric cylindrical cups, means are provided for reducing heat loss from the penetration region which extends through the cups. At least one cup includes an integral skirt extending from one end of the cup to intersection with the penetration means. Assembly of the insulation package with the skirted cup is facilitated by splitting the cup to allow it to be opened up and fitted around the other cups during assembly. The insulation is for an implantable nuclear powered artificial heart

  11. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  12. Structural and electrical evaluation for strained Si/SiGe on insulator

    International Nuclear Information System (INIS)

    Wang Dong; Ii, Seiichiro; Ikeda, Ken-ichi; Nakashima, Hideharu; Ninomiya, Masaharu; Nakamae, Masahiko; Nakashima, Hiroshi

    2006-01-01

    Three strained Si/SiGe on insulator wafers having different Ge fractions were evaluated using dual-metal-oxide-semiconductor (dual-MOS) deep level transient spectroscopy (DLTS) and transmission electron microscopy (TEM) methods. The interface of SiGe/buried oxide (BOX) shows roughness less than 1 nm by high resolution TEM observation. The interface states densities (D it ) of SiGe/BOX are approximately 1 x 10 12 cm -2 eV -1 , which is approximately one order of magnitude higher than that of Si/BOX in a Si on insulator wafer measured as reference by the same method of dual-MOS DLTS. The high D it of SiGe/BOX is not due to interface roughness but due to Ge atoms. The threading dislocations were also clearly observed by TEM and were analyzed

  13. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  14. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments.

    Science.gov (United States)

    Ngo, Ha-Duong; Mukhopadhyay, Biswaijit; Ehrmann, Oswin; Lang, Klaus-Dieter

    2015-08-18

    In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a "one-sensor-one-packaging_technology" concept. The second one uses a standard flip-chip bonding technique. The first sensor is a "floating-concept", capable of measuring pressures at temperatures up to 400 °C (constant load) with an accuracy of 0.25% Full Scale Output (FSO). A push rod (mounted onto the steel membrane) transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process). A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not "floating" but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  15. Advanced Liquid-Free, Piezoresistive, SOI-Based Pressure Sensors for Measurements in Harsh Environments

    Directory of Open Access Journals (Sweden)

    Ha-Duong Ngo

    2015-08-01

    Full Text Available In this paper we present and discuss two innovative liquid-free SOI sensors for pressure measurements in harsh environments. The sensors are capable of measuring pressures at high temperatures. In both concepts media separation is realized using a steel membrane. The two concepts represent two different strategies for packaging of devices for use in harsh environments and at high temperatures. The first one is a “one-sensor-one-packaging_technology” concept. The second one uses a standard flip-chip bonding technique. The first sensor is a “floating-concept”, capable of measuring pressures at temperatures up to 400 °C (constant load with an accuracy of 0.25% Full Scale Output (FSO. A push rod (mounted onto the steel membrane transfers the applied pressure directly to the center-boss membrane of the SOI-chip, which is placed on a ceramic carrier. The chip membrane is realized by Deep Reactive Ion Etching (DRIE or Bosch Process. A novel propertied chip housing employing a sliding sensor chip that is fixed during packaging by mechanical preloading via the push rod is used, thereby avoiding chip movement, and ensuring optimal push rod load transmission. The second sensor can be used up to 350 °C. The SOI chips consists of a beam with an integrated centre-boss with was realized using KOH structuring and DRIE. The SOI chip is not “floating” but bonded by using flip-chip technology. The fabricated SOI sensor chip has a bridge resistance of 3250 Ω. The realized sensor chip has a sensitivity of 18 mV/µm measured using a bridge current of 1 mA.

  16. An Ultra-Efficient Nonlinear Platform: AlGaAs-On-Insulator

    DEFF Research Database (Denmark)

    Pu, Minhao; Ottaviano, Luisa; Semenova, Elizaveta

    The combination of nonlinear and integrated photonics enables applications including optical signal processing, multi-wavelength lasers, metrology, spectroscopy, and quantum information science. Silicon-on-insulator (SOI) has emerged as a promising platform [1, 2] due to its high material...... nonlinearity and its compatibility with the CMOS industry. However, silicon suffers two-photon absorption (TPA) in the telecommunication wavelength band around 1.55 µm, which hampers its applications. Different platforms have been proposed to avoid TPA in the telecom wavelength range such as Si3N4 and Hydex [3...... a nonlinear index (n2) on the order of 10−17 W/m2 and a high refractive index (n ≈3.3), a large transparency window (from near- to mid-infrared), and the ability to engineer the material bandgap to mitigate TPA [5]. In this presentation, we introduce AlGaAson-insulator (AlGaAsOI) platform which combines both...

  17. Cooper Pairs in Insulators?

    International Nuclear Information System (INIS)

    Valles, James

    2008-01-01

    Nearly 50 years elapsed between the discovery of superconductivity and the emergence of the microscopic theory describing this zero resistance state. The explanation required a novel phase of matter in which conduction electrons joined in weakly bound pairs and condensed with other pairs into a single quantum state. Surprisingly, this Cooper pair formation has also been invoked to account for recently uncovered high-resistance or insulating phases of matter. To address this possibility, we have used nanotechnology to create an insulating system that we can probe directly for Cooper pairs. I will present the evidence that Cooper pairs exist and dominate the electrical transport in these insulators and I will discuss how these findings provide new insight into superconductor to insulator quantum phase transitions.

  18. Gas insulated substations

    CERN Document Server

    2014-01-01

    This book provides an overview on the particular development steps of gas insulated high-voltage switchgear, and is based on the information given with the editor's tutorial. The theory is kept low only as much as it is needed to understand gas insulated technology, with the main focus of the book being on delivering practical application knowledge. It discusses some introductory and advanced aspects in the meaning of applications. The start of the book presents the theory of Gas Insulated Technology, and outlines reliability, design, safety, grounding and bonding, and factors for choosing GIS. The third chapter presents the technology, covering the following in detail: manufacturing, specification, instrument transformers, Gas Insulated Bus, and the assembly process. Next, the book goes into control and monitoring, which covers local control cabinet, bay controller, control schemes, and digital communication. Testing is explained in the middle of the book before installation and energization. Importantly, ...

  19. Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

    OpenAIRE

    Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

    2018-01-01

    Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

  20. Peculiarities of electronic structure of silicon-on-insulator structures and their interaction with synchrotron radiation

    Directory of Open Access Journals (Sweden)

    Vladimir A. Terekhov

    2015-09-01

    Full Text Available SOI (silicon-on-insulator structures with strained and unstrained silicon layers were studied by ultrasoft X-ray emission spectroscopy and X-ray absorption near edge structure spectroscopy with the use of synchrotron radiation techniques. Analysis of X-ray data has shown a noticeable transformation of the electron energy spectrum and local partial density of states distribution in valence and conduction bands in the strained silicon layer of the SOI structure. USXES Si L2,3 spectra analysis revealed a decrease of the distance between the L2v′ и L1v points in the valence band of the strained silicon layer as well as a shift of the first two maxima of the XANES first derivation spectra to the higher energies with respect to conduction band bottom Ec. At the same time the X-ray standing waves of synchrotron radiation (λ~12–20 nm are formed in the silicon-on-insulator structure with and without strains of the silicon layer. Moreover changing the synchrotron radiation grazing angle θ by 2° leads to a change of the electromagnetic field phase to the opposite.

  1. Wrapped Multilayer Insulation

    Science.gov (United States)

    Dye, Scott A.

    2015-01-01

    New NASA vehicles, such as Earth Departure Stage (EDS), Orion, landers, and orbiting fuel depots, need improved cryogenic propellant transfer and storage for long-duration missions. Current cryogen feed line multilayer insulation (MLI) performance is 10 times worse per area than tank MLI insulation. During each launch, cryogenic piping loses approximately 150,000 gallons (equivalent to $300,000) in boil-off during transfer, chill down, and ground hold. Quest Product Development Corp., teaming with Ball Aerospace, developed an innovative advanced insulation system, Wrapped MLI (wMLI), to provide improved thermal insulation for cryogenic feed lines. wMLI is high-performance multilayer insulation designed for cryogenic piping. It uses Quest's innovative discrete-spacer technology to control layer spacing/ density and reduce heat leak. The Phase I project successfully designed, built, and tested a wMLI prototype with a measured heat leak 3.6X lower than spiral-wrapped conventional MLI widely used for piping insulation. A wMLI prototype had a heat leak of 7.3 W/m2, or 27 percent of the heat leak of conventional MLI (26.7 W/m2). The Phase II project is further developing wMLI technology with custom, molded polymer spacers and advancing the product toward commercialization via a rigorous testing program, including developing advanced vacuuminsulated pipe for ground support equipment.

  2. Survey of thermal insulation systems

    International Nuclear Information System (INIS)

    Kinoshita, Izumi

    1983-01-01

    Better thermal insulations have been developed to meet the growing demands of industry, and studies on thermal insulation at both high temperature and low temperature have been widely performed. The purpose of this survey is to summarize data on the performances and characteristics of thermal insulation materials and thermal insulation structures (for instance, gas cooled reactors, space vehicles and LNG storage tanks), and to discuss ravious problems regarding the design of thermal insulation structures of pool-type LMFBRs. (author)

  3. A radiation-hardened SOI-based FPGA

    International Nuclear Information System (INIS)

    Han Xiaowei; Wu Lihua; Zhao Yan; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Chen, Stanley L.; Liu Zhongli; Yu Fang; Zhao Kai

    2011-01-01

    A radiation-hardened SRAM-based field programmable gate array VS1000 is designed and fabricated with a 0.5 μm partial-depletion silicon-on-insulator logic process at the CETC 58th Institute. The new logic cell (LC), with a multi-mode based on 3-input look-up-table (LUT), increases logic density about 12% compared to a traditional 4-input LUT The logic block (LB), consisting of 2 LCs, can be used in two functional modes: LUT mode and distributed read access memory mode. The hierarchical routing channel block and switch block can significantly improve the flexibility and routability of the routing resource. The VS1000 uses a CQFP208 package and contains 392 reconfigurable LCs, 112 reconfigurable user I/Os and IEEE 1149.1 compatible with boundary-scan logic for testing and programming. The function test results indicate that the hardware and software cooperate successfully and the VS1000 works correctly. Moreover, the radiation test results indicate that the VS1000 chip has total dose tolerance of 100 krad(Si), a dose rate survivability of 1.5 x 10 11 rad(Si)/s and a neutron fluence immunity of 1 x 10 14 n/cm 2 . (semiconductor integrated circuits)

  4. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  5. Unified analytical threshold voltage model for non-uniformly doped dual metal gate fully depleted silicon-on-insulator MOSFETs

    Science.gov (United States)

    Rao, Rathnamala; Katti, Guruprasad; Havaldar, Dnyanesh S.; DasGupta, Nandita; DasGupta, Amitava

    2009-03-01

    The paper describes the unified analytical threshold voltage model for non-uniformly doped, dual metal gate (DMG) fully depleted silicon-on-insulator (FDSOI) MOSFETs based on the solution of 2D Poisson's equation. 2D Poisson's equation is solved analytically for appropriate boundary conditions using separation of variables technique. The solution is then extended to obtain the threshold voltage of the FDSOI MOSFET. The model is able to handle any kind of non-uniform doping, viz. vertical, lateral as well as laterally asymetric channel (LAC) profile in the SOI film in addition to the DMG structure. The analytical results are validated with the numerical simulations using the device simulator MEDICI.

  6. Reusable Surface Insulation

    Science.gov (United States)

    1997-01-01

    Advanced Flexible Reusable Surface Insulation, developed by Ames Research Center, protects the Space Shuttle from the searing heat that engulfs it on reentry into the Earth's atmosphere. Initially integrated into the Space Shuttle by Rockwell International, production was transferred to Hi-Temp Insulation Inc. in 1974. Over the years, Hi-Temp has created many new technologies to meet the requirements of the Space Shuttle program. This expertise is also used commercially, including insulation blankets to cover aircrafts parts, fire barrier material to protect aircraft engine cowlings and aircraft rescue fire fighter suits. A Fire Protection Division has also been established, offering the first suit designed exclusively by and for aircraft rescue fire fighters. Hi-Temp is a supplier to the Los Angeles City Fire Department as well as other major U.S. civil and military fire departments.

  7. Design, fabrication and characterisation of advanced substrate crosstalk suppression structures in silicon on insulator substrates with buried ground planes (GPSOI)

    International Nuclear Information System (INIS)

    Stefanou, Stefanos

    2002-07-01

    Substrate crosstalk or coupling has been acknowledged to be a limiting factor in mixed signal RF integration. Although high levels of integration and high frequencies of operation are desirable for mixed mode RF and microwave circuits, they make substrate crosstalk more pronounced and may lead to circuit performance degradation. High signal isolation is dictated by requirements for low power dissipation, reduced number of components and lower integration costs for feasible system-on-chip (SoC) solutions. Substrate crosstalk suppression in ground plane silicon-on-insulator (GPSOI) substrates is investigated in this thesis. Test structures are designed and fabricated on SOI substrates with a buried WSi 2 plane that is connected to ground; hence it is called a ground plane. A Faraday cage structure that exhibits very high degrees of signal isolation is presented and compared to other SOI isolation schemes. The Faraday cage structure is shown to achieve 20 dB increased isolation in the frequency range of 0.5-50 GHz compared to published data for high resistivity (200 Ωcm) thin film SOI substrates with no ground planes, but where capacitive guard rings were used. The measurement results are analysed with the aid of planar electromagnetic simulators and compact lumped element models of all the fabricated test structures are developed. The accuracy of the lumped models is validated against experimental measurements. (author)

  8. Micromachined Thin-Film Sensors for SOI-CMOS Co-Integration

    Science.gov (United States)

    Laconte, Jean; Flandre, D.; Raskin, Jean-Pierre

    Co-integration of sensors with their associated electronics on a single silicon chip may provide many significant benefits regarding performance, reliability, miniaturization and process simplicity without significantly increasing the total cost. Micromachined Thin-Film Sensors for SOI-CMOS Co-integration covers the challenges and interests and demonstrates the successful co-integration of gas flow sensors on dielectric membrane, with their associated electronics, in CMOS-SOI technology. We firstly investigate the extraction of residual stress in thin layers and in their stacking and the release, in post-processing, of a 1 μm-thick robust and flat dielectric multilayered membrane using Tetramethyl Ammonium Hydroxide (TMAH) silicon micromachining solution.

  9. Anomalous DIBL Effect in Fully Depleted SOI MOSFETs Using Nanoscale Gate-Recessed Channel Process

    Directory of Open Access Journals (Sweden)

    Avi Karsenty

    2015-01-01

    Full Text Available Nanoscale Gate-Recessed Channel (GRC Fully Depleted- (FD- SOI MOSFET device with a silicon channel thickness (tSi as low as 2.2 nm was first tested at room temperature for functionality check and then tested at low temperature (77 K for I-V characterizations. In spite of its FD-SOI nanoscale thickness and long channel feature, the device has surprisingly exhibited a Drain-Induced Barrier Lowering (DIBL effect at RT. However, this effect was suppressed at 77 K. If the apparition of such anomalous effect can be explained by a parasitic short channel transistor located at the edges of the channel, its suppression is explained by the decrease of the potential barrier between the drain and the channel when lowering the temperature.

  10. Insulators for fusion applications

    International Nuclear Information System (INIS)

    1987-04-01

    Design studies for fusion devices and reactors have become more detailed in recent years and with this has come a better understanding of requirements and operating conditions for insulators in these machines. Ceramic and organic insulators are widely used for many components of fusion devices and reactors namely: radio frequency (RF) energy injection systems (BeO, Al 2 O 3 , Mg Al 2 O 4 , Si 3 N 4 ); electrical insulation for the torus structure (SiC, Al 2 O 3 , MgO, Mg Al 2 O 4 , Si 4 Al 2 O 2 N 6 , Si 3 N 4 , Y 2 O 3 ); lightly-shielded magnetic coils (MgO, MgAl 2 O 4 ); the toroidal field coil (epoxies, polyimides), neutron shield (B 4 C, TiH 2 ); high efficiency electrical generation; as well as the generation of very high temperatures for high efficiency hydrogen production processes (ZrO 2 and Al 2 O 3 - mat, graphite and carbon - felt). Timely development of insulators for fusion applications is clearly necessary. Those materials to be used in fusion machines should show high resistance to radiation damage and maintain their structural integrity. Now the need is urgent for a variety of radiation resistant materials, but much effort in these areas is required for insulators to be considered seriously by the design community. This document contains 14 papers from an IAEA meeting. It was the objective of this meeting to identify existing problems in analysing various situations of applications and requirements of electrical insulators and ceramics in fusion and to recommend strategies and different stages of implementation. This meeting was endorsed by the International Fusion Research Council

  11. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  12. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  13. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  14. 300 nm bandwidth adiabatic SOI polarization splitter-rotators exploiting continuous symmetry breaking.

    Science.gov (United States)

    Socci, Luciano; Sorianello, Vito; Romagnoli, Marco

    2015-07-27

    Adiabatic polarization splitter-rotators are investigated exploiting continuous symmetry breaking thereby achieving significant device size and losses reduction in a single mask fabrication process for both SOI channel and ridge waveguides. A crosstalk lower than -25 dB is expected over 300nm bandwidth, making the device suitable for full grid CWDM and diplexer/triplexer FTTH applications at 1310, 1490 and 1550nm.

  15. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  16. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  17. Computational Modeling in Plasma Processing for 300 mm Wafers

    Science.gov (United States)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  18. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  19. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  20. A Numerical Study on Phonon Spectral Contributions to Thermal Conduction in Silicon-on-Insulator Transistor Using Electron-Phonon Interaction Model

    Energy Technology Data Exchange (ETDEWEB)

    Kang, Hyung-sun; Koh, Young Ha; Jin, Jae Sik [Chosun College of Science and Technology, Gwangju (Korea, Republic of)

    2017-06-15

    The aim of this study is to understand the phonon transfer characteristics of a silicon thin film transistor. For this purpose, the Joule heating mechanism was considered through the electron-phonon interaction model whose validation has been done. The phonon transport characteristics were investigated in terms of phonon mean free path for the variations in the device power and silicon layer thickness from 41 nm to 177 nm. The results may be used for developing the thermal design strategy for achieving reliability and efficiency of the silicon-on-insulator (SOI) transistor, further, they will increase the understanding of heat conduction in SOI systems, which are very important in the semiconductor industry and the nano-fabrication technology.

  1. Insulation Reformulation Development

    Science.gov (United States)

    Chapman, Cynthia; Bray, Mark

    2015-01-01

    The current Space Launch System (SLS) internal solid rocket motor insulation, polybenzimidazole acrylonitrile butadiene rubber (PBI-NBR), is a new insulation that replaced asbestos-based insulations found in Space Shuttle heritage solid rocket boosters. PBI-NBR has some outstanding characteristics such as an excellent thermal erosion resistance, low thermal conductivity, and low density. PBI-NBR also has some significant challenges associated with its use: Air entrainment/entrapment during manufacture and lay-up/cure and low mechanical properties such as tensile strength, modulus, and fracture toughness. This technology development attempted to overcome these challenges by testing various reformulated versions of booster insulation. The results suggest the SLS program should continue to investigate material alternatives for potential block upgrades or use an entirely new, more advanced booster. The experimental design was composed of a logic path that performs iterative formulation and testing in order to maximize the effort. A lab mixing baseline was developed and documented for the Rubber Laboratory in Bldg. 4602/Room 1178.

  2. Beyond insulation and isolation

    DEFF Research Database (Denmark)

    Højlund, Marie Koldkjær

    2016-01-01

    are insulation and isolation strategies to reduce measurable and perceptual noise levels. However, these strategies do not actively support the need to feel like an integral part of the shared hospital environment, which is a key element in creating healing environments, according to the paradigm of Evidence-Based...

  3. Self-Healing Wire Insulation

    Science.gov (United States)

    Parrish, Clyde F. (Inventor)

    2012-01-01

    A self-healing system for an insulation material initiates a self-repair process by rupturing a plurality of microcapsules disposed on the insulation material. When the plurality of microcapsules are ruptured, reactants within the plurality of microcapsules react to form a replacement polymer in a break of the insulation material. This self-healing system has the ability to repair multiple breaks in a length of insulation material without exhausting the repair properties of the material.

  4. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  5. Integrated Multilayer Insulation

    Science.gov (United States)

    Dye, Scott

    2009-01-01

    Integrated multilayer insulation (IMLI) is being developed as an improved alternative to conventional multilayer insulation (MLI), which is more than 50 years old. A typical conventional MLI blanket comprises between 10 and 120 metallized polymer films separated by polyester nets. MLI is the best thermal- insulation material for use in a vacuum, and is the insulation material of choice for spacecraft and cryogenic systems. However, conventional MLI has several disadvantages: It is difficult or impossible to maintain the desired value of gap distance between the film layers (and consequently, it is difficult or impossible to ensure consistent performance), and fabrication and installation are labor-intensive and difficult. The development of IMLI is intended to overcome these disadvantages to some extent and to offer some additional advantages over conventional MLI. The main difference between IMLI and conventional MLI lies in the method of maintaining the gaps between the film layers. In IMLI, the film layers are separated by what its developers call a micro-molded discrete matrix, which can be loosely characterized as consisting of arrays of highly engineered, small, lightweight, polymer (typically, thermoplastic) frames attached to, and placed between, the film layers. The term "micro-molded" refers to both the smallness of the frames and the fact that they are fabricated in a process that forms precise small features, described below, that are essential to attainment of the desired properties. The term "discrete" refers to the nature of the matrix as consisting of separate frames, in contradistinction to a unitary frame spanning entire volume of an insulation blanket.

  6. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  7. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  8. Prediction of thermo-mechanical reliability of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

    2004-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  9. Prediction of thermo-mechanical integrity of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

    2003-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  10. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  11. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  12. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  13. Metal-insulator transitions

    Science.gov (United States)

    Imada, Masatoshi; Fujimori, Atsushi; Tokura, Yoshinori

    1998-10-01

    Metal-insulator transitions are accompanied by huge resistivity changes, even over tens of orders of magnitude, and are widely observed in condensed-matter systems. This article presents the observations and current understanding of the metal-insulator transition with a pedagogical introduction to the subject. Especially important are the transitions driven by correlation effects associated with the electron-electron interaction. The insulating phase caused by the correlation effects is categorized as the Mott Insulator. Near the transition point the metallic state shows fluctuations and orderings in the spin, charge, and orbital degrees of freedom. The properties of these metals are frequently quite different from those of ordinary metals, as measured by transport, optical, and magnetic probes. The review first describes theoretical approaches to the unusual metallic states and to the metal-insulator transition. The Fermi-liquid theory treats the correlations that can be adiabatically connected with the noninteracting picture. Strong-coupling models that do not require Fermi-liquid behavior have also been developed. Much work has also been done on the scaling theory of the transition. A central issue for this review is the evaluation of these approaches in simple theoretical systems such as the Hubbard model and t-J models. Another key issue is strong competition among various orderings as in the interplay of spin and orbital fluctuations. Experimentally, the unusual properties of the metallic state near the insulating transition have been most extensively studied in d-electron systems. In particular, there is revived interest in transition-metal oxides, motivated by the epoch-making findings of high-temperature superconductivity in cuprates and colossal magnetoresistance in manganites. The article reviews the rich phenomena of anomalous metallicity, taking as examples Ti, V, Cr, Mn, Fe, Co, Ni, Cu, and Ru compounds. The diverse phenomena include strong spin and

  14. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  15. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  16. Heat insulating plates

    Energy Technology Data Exchange (ETDEWEB)

    Allan, J.A.F.

    1976-10-28

    Micro-porous insulation plates are dealt with, for example, how they are used in the insulation of heat storage devices. Since one side of such plates is exposed to a temperature of over 700/sup 0/C, a shrinkage of the glass texture of the covering can occur, which can exceed the shrinkage of the inner micro-porous material, so that cracks and splits in the high temperature side of the covering can come about. The task of the invention is to design the plate in such a way as to prevent this from happening. For this purpose the plate is provided, according to invention specifications, with flutes, waves, ribs, waffle or grid patterns and the covering is set into the recesses originating from this.

  17. Green insulation: hemp fibers

    Energy Technology Data Exchange (ETDEWEB)

    Anon,

    2011-09-15

    Indian hemp (Cannabis indica) is known for its psychotropic values and it is banned in most countries. However, industrial hemp (Cannabis sativa) is known for its tough fibers. Several manufactures in Europe including, small niche players, have been marketing hemp insulation products for several years. Hemp is a low environmental impact material. Neither herbicide nor pesticide is used during the growth of hemp. The fibers are extracted in a waste-free and chemical-free mechanical process. Hemp can consume CO2 during its growth. In addition, hemp fiber can be disposed of harmlessly by composting or incineration at the end of its life. Hemp fibers are processed and treated only minimally to resist rot and fungal activity. There is little health risk when producing and installing the insulation, thanks to the absence of toxic additive. Its thermal resistance is comparable to mineral wool. But the development and marketing of hemp fibers may be restricted in North America.

  18. Super-insulation

    International Nuclear Information System (INIS)

    Gerold, J.

    1985-01-01

    The invention concerns super-insulation, which also acts as spacing between two pressurized surfaces, where the crossing bars in at least two layers are provided, with interposed foil. The super-insulation is designed so that it can take compression forces and limits thermal radiation and thermal conduction sufficiently, where the total density of heat flow is usually limited to a few watts per m 2 . The solution to the problem is characterized by the fact that the bars per layer are parallel and from layer to layer they are at an angle to each other and the crossover positions of the bars of different layers are at fixed places and so form contact columns. The basic idea is that bars crossing over each other to support compression forces are used so that contact columns are formed, which are compressed to a certain extent by the load. (orig./PW) [de

  19. Compact vacuum insulation embodiments

    Science.gov (United States)

    Benson, D.K.; Potter, T.F.

    1992-04-28

    An ultra-thin compact vacuum insulation panel is comprised of two hard, but bendable metal wall sheets closely spaced apart from each other and welded around the edges to enclose a vacuum chamber. Glass or ceramic spacers hold the wall sheets apart. The spacers can be discrete spherical beads or monolithic sheets of glass or ceramic webs with nodules protruding therefrom to form essentially point' or line' contacts with the metal wall sheets. In the case of monolithic spacers that form line' contacts, two such spacers with the line contacts running perpendicular to each other form effectively point' contacts at the intersections. Corrugations accommodate bending and expansion, tubular insulated pipes and conduits, and preferred applications are also included. 26 figs.

  20. Compact vacuum insulation

    Science.gov (United States)

    Benson, D.K.; Potter, T.F.

    1993-01-05

    An ultra-thin compact vacuum insulation panel is comprised of two hard, but bendable metal wall sheets closely spaced apart from each other and welded around the edges to enclose a vacuum chamber. Glass or ceramic spacers hold the wall sheets apart. The spacers can be discrete spherical beads or monolithic sheets of glass or ceramic webs with nodules protruding therefrom to form essentially point'' or line'' contacts with the metal wall sheets. In the case of monolithic spacers that form line'' contacts, two such spacers with the line contacts running perpendicular to each other form effectively point'' contacts at the intersections. Corrugations accommodate bending and expansion, tubular insulated pipes and conduits, and preferred applications are also included.

  1. Insulating materials for optoelectronics

    International Nuclear Information System (INIS)

    Agullo-Lopez, F.

    1990-01-01

    Optoelectronics is an interdisciplinary field. Basic functions of an optoelectronic system include the generator of the optical signal, its transmission and handling and, finally, its detection, storage and display. A large variety of semiconductor and insulating materials are used or are being considered to perform those functions. The authors focus on insulating materials, mostly oxides. For signal generation, tunable solid state lasers, either vibronic or those based oon colour centres are briefly described, and their main operating parameters summarized. Reference is made to some developments on fiber and waveguide lasers. Relevant physical features of the silica fibres used for low-loss, long-band, optical transmission are reviewed, as well as present efforts to further reduce attenuation in the mid-infrared range. Particular attention is paid to photorefractive materials (LiNbO 3 , BGO, BSO, etc.), which are being investigated

  2. Super insulating aerogel glazing

    DEFF Research Database (Denmark)

    Schultz, Jørgen Munthe; Jensen, Karsten Ingerslev; Kristiansen, Finn Harken

    2004-01-01

    form the weakest part of the thermal envelope with respect to heat loss coefficient, but on the other hand also play an important role for passive solar energy utilisation. For window orientations other than south, the net energy balance will be close to or below zero. However, the properties......Monolithic silica aerogel offers the possibility of combining super insulation and high solar energy transmittance, which has been the background for a previous and a current EU project on research and development of monolithic silica aerogel as transparent insulation in windows. Generally, windows...... of aerogel glazing will allow for a positive net energy gain even for north facing vertical windows in a Danish climate during the heating season. This means that high quality daylight can be obtained even with additional energy gain. On behalf of the partners of the two EU projects, results related...

  3. Insulated pipe clamp design

    International Nuclear Information System (INIS)

    Anderson, M.J.; Hyde, L.L.; Wagner, S.E.; Severud, L.K.

    1980-01-01

    Thin wall large diameter piping for breeder reactor plants can be subjected to significant thermal shocks during reactor scrams and other upset events. On the Fast Flux Test Facility, the addition of thick clamps directly on the piping was undesired because the differential metal temperatures between the pipe wall and the clamp could have significantly reduced the pipe thermal fatigue life cycle capabilities. Accordingly, an insulated pipe clamp design concept was developed. The design considerations and methods along with the development tests are presented. Special considerations to guard against adverse cracking of the insulation material, to maintain the clamp-pipe stiffness desired during a seismic event, to minimize clamp restraint on the pipe during normal pipe heatup, and to resist clamp rotation or spinning on the pipe are emphasized

  4. Insulated pipe clamp design

    International Nuclear Information System (INIS)

    Anderson, M.J.; Hyde, L.L.; Wagner, S.E.; Severud, L.K.

    1980-01-01

    Thin wall large diameter piping for breeder reactor plants can be subjected to significant thermal shocks during reactor scrams and other upset events. On the Fast Flux Test Facility, the addition of thick clamps directly on the piping was undesired because the differential metal temperatures between the pipe wall and the clamp could have significantly reduced the pipe thermal fatigue life cycle capabilities. Accordingly, an insulated pipe clamp design concept was developed. 5 refs

  5. Pourable Foam Insulation

    Science.gov (United States)

    Harvey, James A.; Butler, John M.; Chartoff, Richard P.

    1989-01-01

    Report describes search for polyisocyanurate/polyurethane foam insulation with superior characteristics. Discusses chemistry of current formulations. Tests of formulations, of individual ingredients and or alternative new formulations described. Search revealed commercially available formulations exhibiting increased thermal stability at temperatures up to 600 degree C, pours readily before curing, presents good appearance after curing, and remains securely bonded to aluminum at cryogenic temperatures. Total of 42 different formulations investigated, 10 found to meet requirements.

  6. Radio-over-optical waveguide system-on-wafer for massive delivery capacity 5G MIMO access networks

    Science.gov (United States)

    Binh, Le N.

    2017-01-01

    Delivering maximum information capacity over MIMO antennae systems beam steering is critical so as to achieve the flexibility via beam steering, maximizing the number of users or community of users in Gb/s rate per user over distributed cloud-based optical-wireless access networks. This paper gives an overview of (i) demands of optical - wireless delivery with high flexibility, especially the beam steering of multi-Tbps information channels to information hungry community of users via virtualized beam steering MIMO antenna systems at the free-license mmW region; (ii) Proposing a novel photonic planar integrated waveguide systems composing several passive and active, passive and amplification photonic devices so as to generate mmW carrier and embedded baseband information channels to feed to antenna elements; (iii) Integration techniques to generate a radio over optical waveguide (RoOW) system-on-wafer (SoW) comprising MIMO planar antenna elements and associate photonic integrated circuits for both up- and down- links; (iv) Challenges encountered in the implementation of the SoW in both wireless and photonic domains; (v) Photonic modulation techniques to achieve maximum transmission capacity per wavelength per MIMO antenna system. (vi) A view on control-feedback systems for fast and accurate generation of phase pattern for MIMO beam steering via a bank of optical phase modulators to mmW carrier phases and their preservation in the converted mmW domain . (vi) The overall operational principles of the novel techniques and technologies based on the coherent mixing of two lightwave channels The entire SoW can be implemented on SOI Si-photonic technology or via hybrid integration. These technological developments and their pros- and cons- will be discussed to achieve 50Tera-bps over the extended 110 channel Cband single mode fiber with mmW centered at 58.6GHz and 7GHz free-license band.

  7. Adiabatic Nanofocusing in Hybrid Gap Plasmon Waveguides on the Silicon-on-Insulator Platform.

    Science.gov (United States)

    Nielsen, Michael P; Lafone, Lucas; Rakovich, Aliaksandra; Sidiropoulos, Themistoklis P H; Rahmani, Mohsen; Maier, Stefan A; Oulton, Rupert F

    2016-02-10

    We present an experimental demonstration of a new class of hybrid gap plasmon waveguides on the silicon-on-insulator (SOI) platform. Created by the hybridization of the plasmonic mode of a gap in a thin metal sheet and the transverse-electric (TE) photonic mode of an SOI slab, this waveguide is designed for efficient adiabatic nanofocusing simply by varying the gap width. For gap widths greater than 100 nm, the mode is primarily photonic in character and propagation lengths can be many tens of micrometers. For gap widths below 100 nm, the mode becomes plasmonic in character with field confinement predominantly within the gap region and with propagation lengths of a few microns. We estimate the electric field intensity enhancement in hybrid gap plasmon waveguide tapers at 1550 nm by three-photon absorption of selectively deposited CdSe/ZnS quantum dots within the gap. Here, we show electric field intensity enhancements of up to 167 ± 26 for a 24 nm gap, proving the viability of low loss adiabatic nanofocusing on a commercially relevant photonics platform.

  8. A silicon-on-insulator vertical nanogap device for electrical transport measurements in aqueous electrolyte solution

    Energy Technology Data Exchange (ETDEWEB)

    Strobel, Sebastian [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Arinaga, Kenji [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Hansen, Allan [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany); Tornow, Marc [Walter Schottky Institut, Technische Universitaet Muenchen, Am Coulombwall, D-85748 Garching (Germany)

    2007-07-25

    A novel concept for metal electrodes with few 10 nm separation for electrical conductance measurements in an aqueous electrolyte environment is presented. Silicon-on-insulator (SOI) material with 10 nm buried silicon dioxide serves as a base substrate for the formation of SOI plateau structures which, after recess-etching the thin oxide layer, thermal oxidation and subsequent metal thin film evaporation, feature vertically oriented nanogap electrodes at their exposed sidewalls. During fabrication only standard silicon process technology without any high-resolution nanolithographic techniques is employed. The vertical concept allows an array-like parallel processing of many individual devices on the same substrate chip. As analysed by cross-sectional TEM analysis the devices exhibit a well-defined material layer architecture, determined by the chosen material thicknesses and process parameters. To investigate the device in aqueous solution, we passivated the sample surface by a polymer layer, leaving a micrometre-size fluid access window to the nanogap region only. First current-voltage characteristics of a 65 nm gap device measured in 60 mM buffer solution reveal excellent electrical isolation behaviour which suggests applications in the field of biomolecular electronics in a natural environment.

  9. Light extraction from GaN-based LED structures on silicon-on-insulator substrates

    Energy Technology Data Exchange (ETDEWEB)

    Tripathy, S.; Teo, S.L.; Lin, V.K.X.; Chen, M.F. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology, and Research), 117602 (Singapore); Dadgar, A.; Krost, A. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany); AZZURRO Semiconductors AG, Universitaetsplatz 1, 39016 Magdeburg (Germany); Christen, J. [Institut fuer Exerimentelle Physik, Otto-von Guericke Universitaet Magdeburg, Universitaetsplatz 1, 39016 Magdeburg (Germany)

    2010-01-15

    Nano-patterning of GaN-based devices is a promising technology in the development of high output power devices. Recent researches have been focused on the realization of two-dimensional (2D) photonic crystal (PhC) structure to improve light extraction efficiency and to control the direction of emission. In this study, we have demonstrated improved light extraction from green light emitting diode (LED) structures on thin silicon-on-insulator (SOI) substrates using surface nanopatterning. Scanning electron microscopy (SEM) is used to probe the size, shape, and etch depth of nano-patterns on the LED surfaces. Different types of nanopatterns were created by e-beam lithography and inductively coupled plasma etching. The LED structures after post processing are studied by photoluminescence (PL) measurements. The GaN nanophotonic structures formed by ICP etching led to more than five-fold increase in the intensity of the green emission. The improved light extraction is due to the combination of SOI substrate reflectivity and photonic structures on top GaN LED surfaces. (copyright 2010 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  10. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  11. A New Nonlinear Model of Body Resistance in Nanometer PD SOI MOSFETs

    Directory of Open Access Journals (Sweden)

    Arash Daghighi

    2011-01-01

    Full Text Available In this paper, a nonlinear model for the body resistance of a 45nm PD SOI MOSFET is developed. This model verified on the base of the small signal three-dimensional simulation results. In this paper by using the three-dimensional simulation of ISE-TCAD software, the indicating factors of body resistance in nanometer transistors and then are shown, using the surface potential model. A mathematical relation to calculat the body resistance incorporating device width and body potential was derived. Excellent agreement was obtained by comparing the model outputs and three-dimensional simulation results.

  12. A three-dimensional breakdown model of SOI lateral power transistors with a circular layout

    International Nuclear Information System (INIS)

    Guo Yufeng; Wang Zhigong; Sheu Gene

    2009-01-01

    This paper presents an analytical three-dimensional breakdown model of SOI lateral power devices with a circular layout. The Poisson equation is solved in cylindrical coordinates to obtain the radial surface potential and electric field distributions for both fully- and partially-depleted drift regions. The breakdown voltages for N + N and P + N junctions are derived and employed to investigate the impact of cathode region curvature. A modified RESURF criterion is proposed to provide a design guideline for optimizing the breakdown voltage and doping concentration in the drift region in three dimensional space. The analytical results agree well with MEDICI simulation results and experimental data from earlier publications. (semiconductor devices)

  13. A monolithic pixel sensor (TRAPPISTe-2) for particle physics instrumentation in OKI 0.2μm SOI technology

    Science.gov (United States)

    Soung Yee, L.; Alvarez, P.; Martin, E.; Cortina, E.; Ferrer, C.

    2012-12-01

    A monolithic active pixel sensor for charged particle tracking has been developed within the frame of a research and development project called TRAPPISTe (Tracking Particles for Physics Instrumentation in SOI Technology). TRAPPISTe aims to study the feasibility of developing a monolithic pixel sensor with SOI technology. TRAPPISTe-2 is the second prototype in this series and was fabricated with an OKI 0.20μm fully depleted (FD-SOI) CMOS process. This device contains test transistors and amplifiers, as well as two pixel matrices with integrated 3-transistor and amplifier readout electronics. The results presented are based on the first electrical measurements performed on the test structures and laser measurements on the pixel matrices.

  14. Dimensional effects and scalability of Meta-Stable Dip (MSD) memory effect for 1T-DRAM SOI MOSFETs

    Science.gov (United States)

    Hubert, A.; Bawedin, M.; Cristoloveanu, S.; Ernst, T.

    2009-12-01

    The difficult scaling of bulk Dynamic Random Access Memories (DRAMs) has led to various concepts of capacitor-less single-transistor (1T) architectures based on SOI transistor floating-body effects. Amongst them, the Meta-Stable Dip RAM (MSDRAM), which is a double-gate Fully Depleted SOI transistor, exhibits attractive performances. The Meta-Stable Dip effect results from the reduced junction leakage current and the long carrier generation lifetime in thin silicon film transistors. In this study, various devices with different gate lengths, widths and silicon film thicknesses have been systematically explored, revealing the impact of transistor dimensions on the MSD effect. These experimental results are discussed and validated by two-dimensional numerical simulations. It is found that MSD is maintained for small dimensions even in standard SOI MOSFETs, although specific optimizations are expected to enhance MSDRAM performances.

  15. Reduction of heat insulation upon soaking of the insulation layer

    Science.gov (United States)

    Achtliger, J.

    1983-09-01

    Improved thermal protection of hollow masonry by introduction of a core insulation between the inner and outer shell is discussed. The thermal conductivity of insulation materials was determined in dry state and after soaking by water with different volume-related moisture contents. The interpolated thermal conductivity values from three measured values at 10 C average temperature are presented as a function of the pertinent moisture content. Fills of expanded polystyrene, perlite and granulated mineral fibers, insulating boards made of mineral fibers and in situ cellular plastics produced from urea-formaldehyde resin were investigated. Test results show a confirmation of thermal conductivity values for insulating materials in hollow masonry.

  16. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  17. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  18. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  19. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  20. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  1. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    International Nuclear Information System (INIS)

    Montoya, Angela C.; Maji, Arup K.

    2010-01-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  2. Electrical insulating liquid: A review

    Directory of Open Access Journals (Sweden)

    Deba Kumar Mahanta

    2017-08-01

    Full Text Available Insulating liquid plays an important role for the life span of the transformer. Petroleum-based mineral oil has become dominant insulating liquid of transformer for more than a century for its excellent dielectric and cooling properties. However, the usage of petroleum-based mineral oil, derived from a nonrenewable energy source, has affected the environment for its nonbiodegradability property. Therefore, researchers direct their attention to renewable and biodegradable alternatives. Palm fatty acid ester, coconut oil, sunflower oil, etc. are considered as alternatives to replace mineral oil as transformer insulation liquid. This paper gives an extensive review of different liquid insulating materials used in a transformer. Characterization of different liquids as an insulating material has been discussed. An attempt has been made to classify different insulating liquids-based on different properties.

  3. Simplified nonplanar wafer bonding for heterogeneous device integration

    Science.gov (United States)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  4. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  5. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    Science.gov (United States)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  6. Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

    Science.gov (United States)

    Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

    2018-04-01

    The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

  7. Physical mechanisms of copper-copper wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  8. Hot-Electron Bolometer Mixers on Silicon-on-Insulator Substrates for Terahertz Frequencies

    Science.gov (United States)

    Skalare, Anders; Stern, Jeffrey; Bumble, Bruce; Maiwald, Frank

    2005-01-01

    A terahertz Hot-Electron Bolometer (HEB) mixer design using device substrates based on Silicon-On-Insulator (SOI) technology is described. This substrate technology allows very thin chips (6 pm) with almost arbitrary shape to be manufactured, so that they can be tightly fitted into a waveguide structure and operated at very high frequencies with only low risk for power leakages and resonance modes. The NbTiN-based bolometers are contacted by gold beam-leads, while other beamleads are used to hold the chip in place in the waveguide test fixture. The initial tests yielded an equivalent receiver noise temperature of 3460 K double-sideband at a local oscillator frequency of 1.462 THz and an intermediate frequency of 1.4 GHz.

  9. Advanced TEM Characterization for the Development of 28-14nm nodes based on fully-depleted Silicon-on-Insulator Technology

    International Nuclear Information System (INIS)

    Servanton, G; Clement, L; Lepinay, K; Lorut, F; Pantel, R; Pofelski, A; Bicais, N

    2013-01-01

    The growing demand for wireless multimedia applications (smartphones, tablets, digital cameras) requires the development of devices combining both high speed performances and low power consumption. A recent technological breakthrough making a good compromise between these two antagonist conditions has been proposed: the 28-14nm CMOS transistor generations based on a fully-depleted Silicon-on-Insulator (FD-SOI) performed on a thin Si film of 5-6nm. In this paper, we propose to review the TEM characterization challenges that are essential for the development of extremely power-efficient System on Chip (SoC)

  10. Photonic bandpass filter characteristics of multimode SOI waveguides integrated with submicron gratings.

    Science.gov (United States)

    Sah, Parimal; Das, Bijoy Krishna

    2018-03-20

    It has been shown that a fundamental mode adiabatically launched into a multimode SOI waveguide with submicron grating offers well-defined flat-top bandpass filter characteristics in transmission. The transmitted spectral bandwidth is controlled by adjusting both waveguide and grating design parameters. The bandwidth is further narrowed down by cascading two gratings with detuned parameters. A semi-analytical model is used to analyze the filter characteristics (1500  nm≤λ≤1650  nm) of the device operating in transverse-electric polarization. The proposed devices were fabricated with an optimized set of design parameters in a SOI substrate with a device layer thickness of 250 nm. The pass bandwidth of waveguide devices integrated with single-stage gratings are measured to be ∼24  nm, whereas the device with two cascaded gratings with slightly detuned periods (ΔΛ=2  nm) exhibits a pass bandwidth down to ∼10  nm.

  11. Total dose induced latch in short channel NMOS/SOI transistors

    International Nuclear Information System (INIS)

    Ferlet-Cavrois, V.; Quoizola, S.; Musseau, O.; Flament, O.; Leray, J.L.; Pelloie, J.L.; Raynaud, C.; Faynot, O.

    1998-01-01

    A latch effect induced by total dose irradiation is observed in short channel SOI transistors. This effect appears on NMOS transistors with either a fully or a partially depleted structure. It is characterized by a hysteresis behavior of the Id-Vg characteristics at high drain bias for a given critical dose. Above this dose, the authors still observe a limited leakage current at low drain bias (0.1 V), but a high conduction current at high drain bias (2 V) as the transistor should be in the off-state. The critical dose above which the latch appears strongly depends on gate length, transistor structure (fully or partially depleted), buried oxide thickness and supply voltage. Two-dimensional (2D) numerical simulations indicate that the parasitic condition is due to the latch of the back gate transistor triggered by charge trapping in the buried oxide. To avoid the latch induced by the floating body effect, different techniques can be used: doping engineering, body contacts, etc. The study of the main parameters influencing the latch (gate length, supply voltage) shows that the scaling of technologies does not necessarily imply an increased latch sensitivity. Some technological parameters like the buried oxide hardness and thickness can be used to avoid latch, even at high cumulated dose, on highly integrated SOI technologies

  12. Magnetically insulated H- diodes

    International Nuclear Information System (INIS)

    Fisher, A.; Bystritskii, V.; Garate, E.; Prohaska, R.; Rostoker, N.

    1993-01-01

    At the Univ. of California, Irvine, the authors have been studying the production of intense H - beams using pulse power techniques for the past 7 years. Previously, current densities of H - ions for various diode designs at UCI have been a few A/cm 2 . Recently, they have developed diodes similar to the coaxial design of the Lebedev Physical Institute, Moscow, USSR, where current densities of up to 200 A/cm 2 were reported using nuclear activation of a carbon target. In experiments at UCI employing the coaxial diode, current densities of up to 35 A/cm 2 from a passive polyethylene cathode loaded with TiH 2 have been measured using a pinhole camera and CR-39 track recording plastic. The authors have also been working on a self-insulating, annular diode which can generate a directed beam of H - ions. In the annular diode experiments a plasma opening switch was used to provide a prepulse and a current path which self-insulated the diode. These experiments were done on the machine APEX, a 1 MV, 50 ns, 7 Ω pulseline with a unipolar negative prepulse of ∼ 100 kV and 400 ns duration. Currently, the authors are modifying the pulseline to include an external LC circuit which can generate a bipolar, 150 kV, 1 μs duration prepulse (similar prepulse characteristic as in the Lebedev Institute experiments cited above)

  13. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  14. Proton induced single event upset cross section prediction for 0.15 μm six-transistor (6T) silicon-on-insulator static random access memories

    International Nuclear Information System (INIS)

    Li Lei; Zhou Wanting; Liu Huihua

    2012-01-01

    In this paper, an efficient physics-based method to estimate the saturated proton upset cross section for six-transistor (6T) silicon-on-insulator (SOI) static random access memory (SRAM) cells using layout and technology parameters is proposed. This method calculates the effects of radiation based on device physics. The simple method handles the problem with ease by SPICE simulations, which can be divided into two stages. At first, it uses a standard SPICE program to predict the cross section for recoiling heavy ions with linear energy transfer (LET) of 14 MeV-cm 2 /mg. Then, the predicted cross section for recoiling heavy ions with LET of 14 MeV-cm 2 /mg is used to estimate the saturated proton upset cross section for 6T SOI SRAM cells with a simple model. The calculated proton induced upset cross section based on this method is in good agreement with the test results of 6T SOI SRAM cells processed using 0.15 μm technology. (author)

  15. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits; Quantification, modelisation et conception prenant en compte les etats anterieurs des signaux dans les circuits mixtes SOI/SOS

    Energy Technology Data Exchange (ETDEWEB)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S. [Southampton Univ., Dept. of Electronics and Computer Sciences (United Kingdom); Uren, M.J.; Brunson, K.M. [DERA Farnborough, GU, Hants (United Kingdom)

    1999-07-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  16. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  17. Insulation structure of thermonuclear device

    International Nuclear Information System (INIS)

    Suzuki, Takayuki; Usami, Saburo; Tsukamoto, Hideo; Kikuchi, Mitsuru

    1998-01-01

    The present invention provides an insulating structure of a thermonuclear device, in which insulation materials between toroidal coils are not broken even if superconductive toroidal coils are used. Namely, a tokamak type thermonuclear device of an insulating structure type comprises superconductive toroidal coils for confining plasmas arranged in a circular shape directing the center each at a predetermined angle, and the toroidal coils are insulated from each other. The insulation materials are formed by using a biaxially oriented fiber reinforced plastics. The contact surface of the toroidal coils and the insulating materials are arranged so that they are contact at a woven surface of the fiber reinforced plastics. Either or both of the contact surfaces of the fiber reinforced plastics and the toroidal coils are coated with a high molecular compound having a low friction coefficient. With such a constitution, since the interlayer shearing strength of the biaxially oriented fiber reinforced plastics is about 1/10 of the compression strength, the shearing stress exerted on the insulation material is reduced. Since a static friction coefficient on the contact surface is reduced to provide a structure causing slipping, shearing stress does not exceeds a predetermined limit. As a result, breakage of the insulation materials between the toroidal coils can be prevented. (I.S.)

  18. Plastic Materials for Insulating Applications.

    Science.gov (United States)

    Wang, S. F.; Grossman, S. J.

    1987-01-01

    Discusses the production and use of polymer materials as thermal insulators. Lists several materials that provide varying degrees of insulation. Describes the production of polymer foam and focuses on the major applications of polystyrene foam, polyurethane foam, and polyisocyanurate foam. (TW)

  19. Magnetically self-insulated transformers

    International Nuclear Information System (INIS)

    Novac, B.M.; Smith, I.R.; Brown, J.

    2002-01-01

    Magnetic insulation is the only practicable form of insulation for much equipment used in ultrahigh pulsed-power work, including transmission lines and plasma opening switches. It has not however so far been successfully exploited in the transformers that are necessarily involved, and the first proposed design that appeared more than 30 years ago raised apparently insuperable problems. The two novel arrangements for a magnetically insulated transformer described in this paper overcome the problems faced by the earlier designs and also offer considerable scope for development in a number of important areas. Theoretical justification is given for their insulating properties, and this is confirmed by proof-of-principle results obtained from a small-scale experimental prototype in which magnetic insulation was demonstrated at up to 100 kV. (author)

  20. Quantification, modelling and design for signal history dependent effects in mixed-signal SOI/SOS circuits

    International Nuclear Information System (INIS)

    Edwards, C.F.; Redman-White, W.; Bracey, M.; Tenbroek, B.M.; Lee, M.S.; Uren, M.J.; Brunson, K.M.

    1999-01-01

    This paper deals with how the radiation hardness of mixed signal SOI/SOS CMOS circuits is taken into account at both architectural terms as well as the the transistor level cell designs. The primary issue is to deal with divergent transistor threshold shifts, and to understand the effects of large amplitude non stationary signals on analogue cell behaviour. (authors)

  1. Research on vacuum insulation for cryocables

    International Nuclear Information System (INIS)

    Graneau, P.

    1974-01-01

    Vacuum insulation, as compared with solid insulation, simplifies the construction of both resistive or superconducting cryogenic cables. The common vacuum space in the cable can furnish thermal insulation between the environment and the cryogenic coolant, provide electrical insulation between conductors, and establish thermal isolation between go- and return-coolant streams. The differences between solid and vacuum high voltage insulation are discussed, and research on the design, materials selection, and testing of vacuum insulated cryogenic cables is described

  2. Excitons in insulators

    International Nuclear Information System (INIS)

    Grasser, R.; Scharmann, A.

    1983-01-01

    This chapter investigates absorption, reflectivity, and intrinsic luminescence spectra of free and/or self-trapped (localized) excitons in alkali halides and rare gas solids. Introduces the concepts underlying the Wannier-Mott and Frenkel exciton models, two extreme pictures of an exciton in crystalline materials. Discusses the theoretical and experimental background; excitons in alkali halides; and excitons in rare gas solids. Shows that the intrinsic optical behavior of wide gap insulators in the range of the fundamental absorption edge is controlled by modified Wannier-Mott excitons. Finds that while that alkali halides only show free and relaxed molecular-like exciton emission, in rare gas crystals luminescence due to free, single and double centered localized excitons is observed. Indicates that the simultaneous existence of free and self-trapped excitons in these solid requires an energy barrier for self-trapping

  3. Towards in-situ tem analysis of PLD Pb(Zr,Ti)O3 thin film membranes

    NARCIS (Netherlands)

    Sardan Sukas, Ö.; Berenschot, Johan W.; de Boer, Meint J.; Nguyen, Duc Minh; van Zalk, M.; Abelmann, Leon

    2011-01-01

    In this paper, a novel technique for fabricating Transmission Electron Microscopy (TEM) chips for investigating structural and piezoelectric properties of Pulse Laser Deposited (PLD) Lead Zirconium Titanate (PZT) thin films is presented. The method involves silicon-on-insulator (SOI) wafer

  4. Selective SiO2 etching in three dimensional structures using parylene-C as mask

    NARCIS (Netherlands)

    Veltkamp, Henk-Willem; Zhao, Yiyuan; de Boer, Meint J.; Wiegerink, Remco J.; Lötters, Joost Conrad

    2017-01-01

    This abstract describes an application of an easy and straightforward method for selective SiO2 etching in three dimensional structures, which is developed by our group. The application in this abstract is the protection of the buried-oxide (BOX) layer of a silicon-on-insulator (SOI) wafer against

  5. Electrostatically Tunable Nanomechanical Shallow Arches

    KAUST Repository

    Kazmi, Syed N. R.; Hajjaj, Amal Z.; Da Costa, Pedro M. F. J.; Younis, Mohammad I.

    2017-01-01

    -beam lithography and surface nanomachining of a highly conductive device layer on a silicon-on-insulator (SOI) wafer. The experimental results show good agreement with the analytical results with a maximum tunability of 108.14% for 180 nm thick arch with a

  6. Near-field characterization of photonic crystal Y-splitters

    DEFF Research Database (Denmark)

    Volkov, V. S.; Bozhevolnyi, S. I.; Borel, Peter Ingo

    2005-01-01

    A scanning near-field optical microscope (SNOM) is used to directly map the propagation of light in a specially designed 50/50 photonic crystal (PC) Y-splitter fabricated on silicon-on-insulator (SOI) wafers. SNOM images are obtained for TE- and TM-polarized light in the wavelength range 1425...

  7. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  8. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  9. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  10. Study of Si wafer surfaces irradiated by gas cluster ion beams

    International Nuclear Information System (INIS)

    Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

    2007-01-01

    The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

  11. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  12. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  13. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  14. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  15. Universal trench design method for a high-voltage SOI trench LDMOS

    Institute of Scientific and Technical Information of China (English)

    Hu Xiarong; Zhang Bo; Luo Xiaorong; Li Zhaoji

    2012-01-01

    The design method for a high-voltage SOl trench LDMOS for various trench permittivities,widths and depths is introduced.A universal method for efficient design is presented for the first time,taking the trade-off between breakdown voltage (BV) and specific on-resistance (Rs,on) into account.The high-k (relative permittivity)dielectric is suitable to fill a shallow and wide trench while the low-k dielectric is suitable to fill a deep and narrow trench.An SOI LDMOS with a vacuum trench in the drift region is also discussed.Simulation results show that the high FOM BV2/Rs,on can be achieved with a trench filled with the low-k dielectric due to its shortened cell-pitch.

  16. SOI detector with drift field due to majority carrier flow - an alternative to biasing in depletion

    International Nuclear Information System (INIS)

    Trimpl, M.; Deptuch, G.; Yarema, R.

    2010-01-01

    This paper reports on a SOI detector with drift field induced by the flow of majority carriers. It is proposed as an alternative method of detector biasing compared to standard depletion. N-drift rings in n-substrate are used at the front side of the detector to provide charge collecting field in depth as well as to improve the lateral charge collection. The concept was verified on a 2.5 x 2.5 mm 2 large detector array with 20 (micro)m and 40 (micro)m pixel pitch fabricated in August 2009 using the OKI semiconductor process. First results, obtained with a radioactive source to demonstrate spatial resolution and spectroscopic performance of the detector for the two different pixel sizes will be shown and compared to results obtained with a standard depletion scheme. Two different diode designs, one using a standard p-implantation and one surrounded by an additional BPW implant will be compared as well.

  17. Determination of wafer center position during the transfer process by using the beam-breaking method

    International Nuclear Information System (INIS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-01-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

  18. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  19. Lightweight, Thermally Insulating Structural Panels

    Science.gov (United States)

    Eisen, Howard J.; Hickey, Gregory; Wen, Liang-Chi; Layman, William E.; Rainen, Richard A.; Birur, Gajanana C.

    1996-01-01

    Lightweight, thermally insulating panels that also serve as structural members developed. Honeycomb-core panel filled with low-thermal-conductivity, opacified silica aerogel preventing convection and minimizes internal radiation. Copper coating on face sheets reduces radiation. Overall thermal conductivities of panels smaller than state-of-art commercial non-structurally-supporting foam and fibrous insulations. On Earth, panels suitable for use in low-air-pressure environments in which lightweight, compact, structurally supporting insulation needed; for example, aboard high-altitude aircraft or in partially evacuated panels in refrigerators.

  20. Reflecting variable opening insulating panel

    International Nuclear Information System (INIS)

    Nungesser, W.T.

    1976-01-01

    A description is given of a reflecting variable opening insulating panel assembly, comprising a static panel assembly of reflecting insulation sheets forming a cavity along one side of the panel and a movable panel opening out by sliding from the cavity of the static panel, and a locking device for holding the movable panel in a position extending from the cavity of the static panel. This can apply to a nuclear reactor of which the base might require maintenance and periodical checking and for which it is desirable to have available certain processes for the partial dismantling of the insulation [fr

  1. Ultrathin, wafer-scale hexagonal boron nitride on dielectric surfaces by diffusion and segregation mechanism

    Science.gov (United States)

    Sonde, Sushant; Dolocan, Andrei; Lu, Ning; Corbet, Chris; Kim, Moon J.; Tutuc, Emanuel; Banerjee, Sanjay K.; Colombo, Luigi

    2017-06-01

    Chemical vapor deposition (CVD) of two-dimensional (2D) hexagonal boron nitride (h-BN) is at the center of numerous studies for its applications in novel electronic devices. However, a clear understanding of the growth mechanism is lacking for its wider industrial adoption on technologically relevant substrates such as SiO2. Here, we demonstrate a controllable growth method of thin, wafer scale h-BN films on arbitrary substrates. We also clarify the growth mechanism to be diffusion and surface segregation (D-SS) of boron (B) and nitrogen (N) in Ni and Co thin films on SiO2/Si substrates after exposure to diborane and ammonia precursors at high temperature. The segregation was found to be independent of the cooling rates employed in this report, and to our knowledge has not been found nor reported for 2D h-BN growth so far, and thus provides an important direction for controlled growth of h-BN. This unique segregation behavior is a result of a combined effect of high diffusivity, small film thickness and the inability to achieve extremely high cooling rates in CVD systems. The resulting D-SS h-BN films exhibit excellent electrical insulating behavior with an optical bandgap of about 5.8 eV. Moreover, graphene-on-h-BN field effect transistors using the as-grown D-SS h-BN films show a mobility of about 6000 cm2 V-1 s-1 at room temperature.

  2. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  3. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  4. Improving scanner wafer alignment performance by target optimization

    Science.gov (United States)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  5. Molecular dewetting on insulators

    International Nuclear Information System (INIS)

    Burke, S A; Topple, J M; Gruetter, P

    2009-01-01

    Recent attention given to the growth and morphology of organic thin films with regard to organic electronics has led to the observation of dewetting (a transition from layer(s) to islands) of molecular deposits in many of these systems. Dewetting is a much studied phenomenon in the formation of polymer and liquid films, but its observation in thin films of the 'small' molecules typical of organic electronics requires additional consideration of the structure of the interface between the molecular film and the substrate. This review covers some key concepts related to dewetting and molecular film growth. In particular, the origins of different growth modes and the thickness dependent interactions which give rise to dewetting are discussed in terms of surface energies and the disjoining pressure. Characteristics of molecular systems which may lead to these conditions, including the formation of metastable interface structures and commensurate-incommensurate phase transitions, are also discussed. Brief descriptions of some experimental techniques which have been used to study molecular dewetting are given as well. Examples of molecule-on-insulator systems which undergo dewetting are described in some detail, specifically perylene derivatives on alkali halides, C 60 on alkali halides, and the technologically important system of pentacene on SiO 2 . These examples point to some possible predicting factors for the occurrence of dewetting, most importantly the formation of an interface layer which differs from the bulk crystal structure. (topical review)

  6. Molecular dewetting on insulators.

    Science.gov (United States)

    Burke, S A; Topple, J M; Grütter, P

    2009-10-21

    Recent attention given to the growth and morphology of organic thin films with regard to organic electronics has led to the observation of dewetting (a transition from layer(s) to islands) of molecular deposits in many of these systems. Dewetting is a much studied phenomenon in the formation of polymer and liquid films, but its observation in thin films of the 'small' molecules typical of organic electronics requires additional consideration of the structure of the interface between the molecular film and the substrate. This review covers some key concepts related to dewetting and molecular film growth. In particular, the origins of different growth modes and the thickness dependent interactions which give rise to dewetting are discussed in terms of surface energies and the disjoining pressure. Characteristics of molecular systems which may lead to these conditions, including the formation of metastable interface structures and commensurate-incommensurate phase transitions, are also discussed. Brief descriptions of some experimental techniques which have been used to study molecular dewetting are given as well. Examples of molecule-on-insulator systems which undergo dewetting are described in some detail, specifically perylene derivatives on alkali halides, C(60) on alkali halides, and the technologically important system of pentacene on SiO(2). These examples point to some possible predicting factors for the occurrence of dewetting, most importantly the formation of an interface layer which differs from the bulk crystal structure.

  7. Insulating fcc YH

    International Nuclear Information System (INIS)

    Molen, S. J. van der; Nagengast, D. G.; Gogh, A. T. M. van; Kalkman, J.; Kooij, E. S.; Rector, J. H.; Griessen, R.

    2001-01-01

    We study the structural, optical, and electrical properties of Mg z Y 1-z switchable mirrors upon hydrogenation. It is found that the alloys disproportionate into essentially pure YH 3-δ and MgH 2 with the crystal structure of YH 3-δ dependent on the Mg concentration z. For 0 3-δ are observed, whereas for z≥0.1 only cubic YH 3-δ is present. Interestingly, cubic YH 3-δ is expanded compared to YH 2 , in disagreement with theoretical predictions. From optical and electrical measurements we conclude that cubic YH 3-δ is a transparent insulator with properties similar to hexagonal YH 3-δ . Our results are inconsistent with calculations predicting fcc YH 3-δ to be metallic, but they are in good agreement with recent GW calculations on both hcp and fcc YH 3 . Finally, we find an increase in the effective band gap of the hydrided Mg z Y 1-z alloys with increasing z. Possibly this is due to quantum confinement effects in the small YH 3 clusters

  8. Topological Insulator Nanowires and Nanoribbons

    KAUST Repository

    Kong, Desheng; Randel, Jason C.; Peng, Hailin; Cha, Judy J.; Meister, Stefan; Lai, Keji; Chen, Yulin; Shen, Zhi-Xun; Manoharan, Hari C.; Cui, Yi

    2010-01-01

    Recent theoretical calculations and photoemission spectroscopy measurements on the bulk Bi2Se3 material show that it is a three-dimensional topological insulator possessing conductive surface states with nondegenerate spins, attractive

  9. Measure Guideline: Basement Insulation Basics

    Energy Technology Data Exchange (ETDEWEB)

    Aldrich, R.; Mantha, P.; Puttagunta, S.

    2012-10-01

    This guideline is intended to describe good practices for insulating basements in new and existing homes, and is intended to be a practical resources for building contractors, designers, and also to homeowners.

  10. Metal-insulator-semiconductor photodetectors.

    Science.gov (United States)

    Lin, Chu-Hsuan; Liu, Chee Wee

    2010-01-01

    The major radiation of the sun can be roughly divided into three regions: ultraviolet, visible, and infrared light. Detection in these three regions is important to human beings. The metal-insulator-semiconductor photodetector, with a simpler process than the pn-junction photodetector and a lower dark current than the MSM photodetector, has been developed for light detection in these three regions. Ideal UV photodetectors with high UV-to-visible rejection ratio could be demonstrated with III-V metal-insulator-semiconductor UV photodetectors. The visible-light detection and near-infrared optical communications have been implemented with Si and Ge metal-insulator-semiconductor photodetectors. For mid- and long-wavelength infrared detection, metal-insulator-semiconductor SiGe/Si quantum dot infrared photodetectors have been developed, and the detection spectrum covers atmospheric transmission windows.

  11. Metal-Insulator-Semiconductor Photodetectors

    Directory of Open Access Journals (Sweden)

    Chu-Hsuan Lin

    2010-09-01

    Full Text Available The major radiation of the Sun can be roughly divided into three regions: ultraviolet, visible, and infrared light. Detection in these three regions is important to human beings. The metal-insulator-semiconductor photodetector, with a simpler process than the pn-junction photodetector and a lower dark current than the MSM photodetector, has been developed for light detection in these three regions. Ideal UV photodetectors with high UV-to-visible rejection ratio could be demonstrated with III-V metal-insulator-semiconductor UV photodetectors. The visible-light detection and near-infrared optical communications have been implemented with Si and Ge metal-insulator-semiconductor photodetectors. For mid- and long-wavelength infrared detection, metal-insulator-semiconductor SiGe/Si quantum dot infrared photodetectors have been developed, and the detection spectrum covers atmospheric transmission windows.

  12. 16 CFR 460.18 - Insulation ads.

    Science.gov (United States)

    2010-01-01

    ... Commercial Practices FEDERAL TRADE COMMISSION TRADE REGULATION RULES LABELING AND ADVERTISING OF HOME INSULATION § 460.18 Insulation ads. (a) If your ad gives an R-value, you must give the type of insulation and... your ad gives a price, you must give the type of insulation, the R-value at a specific thickness, the...

  13. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  14. Cryogenic foam insulation: Abstracted publications

    Science.gov (United States)

    Williamson, F. R.

    1977-01-01

    A group of documents were chosen and abstracted which contain information on the properties of foam materials and on the use of foams as thermal insulation at cryogenic temperatures. The properties include thermal properties, mechanical properties, and compatibility properties with oxygen and other cryogenic fluids. Uses of foams include applications as thermal insulation for spacecraft propellant tanks, and for liquefied natural gas storage tanks and pipelines.

  15. Jean-Pierre Famose et Jean Bertsch, L’estime de soi : une controverse éducative, Paris, PUF, 2009, 192 p

    OpenAIRE

    Benamar, Aïcha

    2015-01-01

    L’ouvrage porte sur l’estime de soi, dans la sphère sociale en général et le monde éducatif en particulier. L’estime de soi est au cœur du comportement individuel, apportant confiance et assurance, permettant de progresser et in fine de réussir. Une faible estime de soi est fréquemment à l’origine de difficultés pour un individu : doutes, hésitations, ou à l’inverse vanité et arrogance. Un bon niveau d’estime de soi confère à la personnalité : capacité à s’affirmer et respect des autres. Cent...

  16. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  17. Correlation study of actual temperature profile and in-line metrology measurements for within-wafer uniformity improvement and wafer edge yield enhancement (Conference Presentation)

    Science.gov (United States)

    Fang, Fang; Vaid, Alok; Vinslava, Alina; Casselberry, Richard; Mishra, Shailendra; Dixit, Dhairya; Timoney, Padraig; Chu, Dinh; Porter, Candice; Song, Da; Ren, Zhou

    2018-03-01

    It is getting more important to monitor all aspects of influencing parameters in critical etch steps and utilize them as tuning knobs for within-wafer uniformity improvement and wafer edge yield enhancement. Meanwhile, we took a dive in pursuing "measuring what matters" and challenged ourselves for more aspects of signals acquired in actual process conditions. Among these factors which are considered subtle previously, we identified Temperature, especially electrostatic chuck (ESC) Temperature measurement in real etch process conditions have direct correlation to in-line measurements. In this work, we used SensArray technique (EtchTemp-SE wafer) to measure ESC temperature profile on a 300mm wafer with plasma turning on to reproduce actual temperature pattern on wafers in real production process conditions. In field applications, we observed substantial correlation between ESC temperature and in-line optical metrology measurements and since temperature is a process factor that can be tuning through set-temperature modulations, we have identified process knobs with known impact on physical profile variations. Furthermore, ESC temperature profile on a 300mm wafer is configured as multiple zones upon radius and SensArray measurements mechanism could catch such zonal distribution as well, which enables detailed temperature modulations targeting edge ring only where most of chips can be harvested and critical zone for yield enhancement. Last but not least, compared with control reference (ESC Temperature in static plasma-off status), we also get additional factors to investigate in chamber-to-chamber matching study and make process tool fleet match on the basis really matters in production. KLA-Tencor EtchTemp-SE wafer enables Plasma On wafer temperature monitoring of silicon etch process. This wafer is wireless and has 65 sensors with measurement range from 20 to 140°C. the wafer is designed to run in real production recipe plasma on condition with maximum RF power up

  18. Propagation of resist heating mask error to wafer level

    Science.gov (United States)

    Babin, S. V.; Karklin, Linard

    2006-10-01

    As technology is approaching 45 nm and below the IC industry is experiencing a severe product yield hit due to rapidly shrinking process windows and unavoidable manufacturing process variations. Current EDA tools are unable by their nature to deliver optimized and process-centered designs that call for 'post design' localized layout optimization DFM tools. To evaluate the impact of different manufacturing process variations on final product it is important to trace and evaluate all errors through design to manufacturing flow. Photo mask is one of the critical parts of this flow, and special attention should be paid to photo mask manufacturing process and especially to mask tight CD control. Electron beam lithography (EBL) is a major technique which is used for fabrication of high-end photo masks. During the writing process, resist heating is one of the sources for mask CD variations. Electron energy is released in the mask body mainly as heat, leading to significant temperature fluctuations in local areas. The temperature fluctuations cause changes in resist sensitivity, which in turn leads to CD variations. These CD variations depend on mask writing speed, order of exposure, pattern density and its distribution. Recent measurements revealed up to 45 nm CD variation on the mask when using ZEP resist. The resist heating problem with CAR resists is significantly smaller compared to other types of resists. This is partially due to higher resist sensitivity and the lower exposure dose required. However, there is no data yet showing CD errors on the wafer induced by CAR resist heating on the mask. This effect can be amplified by high MEEF values and should be carefully evaluated at 45nm and below technology nodes where tight CD control is required. In this paper, we simulated CD variation on the mask due to resist heating; then a mask pattern with the heating error was transferred onto the wafer. So, a CD error on the wafer was evaluated subject to only one term of the

  19. X-ray characterization of Ge dots epitaxially grown on nanostructured Si islands on silicon-on-insulator substrates.

    Science.gov (United States)

    Zaumseil, Peter; Kozlowski, Grzegorz; Yamamoto, Yuji; Schubert, Markus Andreas; Schroeder, Thomas

    2013-08-01

    On the way to integrate lattice mismatched semiconductors on Si(001), the Ge/Si heterosystem was used as a case study for the concept of compliant substrate effects that offer the vision to be able to integrate defect-free alternative semiconductor structures on Si. Ge nanoclusters were selectively grown by chemical vapour deposition on Si nano-islands on silicon-on-insulator (SOI) substrates. The strain states of Ge clusters and Si islands were measured by grazing-incidence diffraction using a laboratory-based X-ray diffraction technique. A tensile strain of up to 0.5% was detected in the Si islands after direct Ge deposition. Using a thin (∼10 nm) SiGe buffer layer between Si and Ge the tensile strain increases to 1.8%. Transmission electron microscopy studies confirm the absence of a regular grid of misfit dislocations in such structures. This clear experimental evidence for the compliance of Si nano-islands on SOI substrates opens a new integration concept that is not only limited to Ge but also extendable to semiconductors like III-V and II-VI materials.

  20. Maximum magnitude in bias-dependent spin accumulation signals of CoFe/MgO/Si on insulator devices

    International Nuclear Information System (INIS)

    Ishikawa, M.; Sugiyama, H.; Inokuchi, T.; Tanamoto, T.; Saito, Y.; Hamaya, K.; Tezuka, N.

    2013-01-01

    We study in detail how the bias voltage (V bias ) and interface resistance (RA) depend on the magnitude of spin accumulation signals (|ΔV| or |ΔV|/I, where I is current) as detected by three-terminal Hanle measurements in CoFe/MgO/Si on insulator (SOI) devices with various MgO layer thicknesses and SOI carrier densities. We find the apparent maximum magnitude of spin polarization as a function of V bias and the correlation between the magnitude of spin accumulation signals and the shape of differential conductance (dI/dV) curves within the framework of the standard spin diffusion model. All of the experimental results can be explained by taking into account the density of states (DOS) in CoFe under the influence of the applied V bias and the quality of MgO tunnel barrier. These results indicate that it is important to consider the DOS of the ferromagnetic materials under the influence of an applied V bias and the quality of tunnel barrier when observing large spin accumulation signals in Si

  1. A Low-Noise X-ray Astronomical Silicon-On-Insulator Pixel Detector Using a Pinned Depleted Diode Structure.

    Science.gov (United States)

    Kamehama, Hiroki; Kawahito, Shoji; Shrestha, Sumeet; Nakanishi, Syunta; Yasutomi, Keita; Takeda, Ayaki; Tsuru, Takeshi Go; Arai, Yasuo

    2017-12-23

    This paper presents a novel full-depletion Si X-ray detector based on silicon-on-insulator pixel (SOIPIX) technology using a pinned depleted diode structure, named the SOIPIX-PDD. The SOIPIX-PDD greatly reduces stray capacitance at the charge sensing node, the dark current of the detector, and capacitive coupling between the sensing node and SOI circuits. These features of the SOIPIX-PDD lead to low read noise, resulting high X-ray energy resolution and stable operation of the pixel. The back-gate surface pinning structure using neutralized p-well at the back-gate surface and depleted n-well underneath the p-well for all the pixel area other than the charge sensing node is also essential for preventing hole injection from the p-well by making the potential barrier to hole, reducing dark current from the Si-SiO₂ interface and creating lateral drift field to gather signal electrons in the pixel area into the small charge sensing node. A prototype chip using 0.2 μm SOI technology shows very low readout noise of 11.0 e - rms , low dark current density of 56 pA/cm² at -35 °C and the energy resolution of 200 eV(FWHM) at 5.9 keV and 280 eV (FWHM) at 13.95 keV.

  2. Avalanches in insulating gases

    International Nuclear Information System (INIS)

    Verhaart, H.F.A.

    1982-01-01

    Avalanches of charged particles in gases are often studied with the ''electrical method'', the measurement of the waveform of the current in the external circuit. In this thesis a substantial improvement of the time resolution of the measuring setup, to be used for the electrical method, is reported. The avalanche is started by an N 2 -laser with a pulse duration of only 0.6 ns. With this laser it is possible to release a high number of primary electrons (some 10 8 ) which makes it possible to obtain sizeable signals, even at low E/p values. With the setup it is possible to analyze current waveforms with a time resolution down to 1.4 ns, determined by both the laser and the measuring system. Furthermore it is possible to distinguish between the current caused by the electrons and the current caused by the ions in the avalanche and to monitor these currents simultaneously. Avalanche currents are measured in N 2 , CO 2 , O 2 , H 2 O, air of varying humidity, SF 6 and SF 6 /N 2 mixtures. Depending on the nature of the gas and the experimental conditions, processes as diffusion, ionization, attachment, detachment, conversion and secondary emission are observed. Values of parameters with which these processes can be described, are derived from an analysis of the current waveforms. For this analysis already published theories and new theories described in this thesis are used. The drift velocity of both the electrons and the ions could be easily determined from measured avalanche currents. Special attention is paid to avalanches in air becasue of the practical importance of air insulation. (Auth.)

  3. A Study of the Charge Trap Transistor (CTT) for Post-Fab Modification of Wafers

    Science.gov (United States)

    2018-04-01

    AFRL-RY-WP-TR-2018-0030 A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS Subramanian S. Iyer University of California...Final 13 June 2016 – 13 December 2017 4. TITLE AND SUBTITLE A STUDY OF THE CHARGE TRAP TRANSISTOR (CTT) FOR POST- FAB MODIFICATION OF WAFERS 5a. CONTRACT

  4. Wafer-level packaged RF-MEMS switches fabricated in a CMOS fab

    NARCIS (Netherlands)

    Tilmans, H.A.C.; Ziad, H.; Jansen, Henricus V.; Di Monaco, O.; Jourdain, A.; De Raedt, W.; Rottenberg, X.; De Backer, E.; Decoussernaeker, A.; Baert, K.

    2001-01-01

    Reports on wafer-level packaged RF-MEMS switches fabricated in a commercial CMOS fab. Switch fabrication is based on a metal surface micromachining process. A novel wafer-level packaging scheme is developed, whereby the switches are housed in on-chip sealed cavities using benzocyclobutene (BCB) as

  5. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  6. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  7. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  8. Fabrication of CVD graphene-based devices via laser ablation for wafer-scale characterization

    DEFF Research Database (Denmark)

    Mackenzie, David; Buron, Jonas Christian Due; Whelan, Patrick Rebsdorf

    2015-01-01

    Selective laser ablation of a wafer-scale graphene film is shown to provide flexible, high speed (1 wafer/hour) device fabrication while avoiding the degradation of electrical properties associated with traditional lithographic methods. Picosecond laser pulses with single pulse peak fluences of 140......-effect mobility, doping level, on–off ratio, and conductance minimum before and after laser ablation fabrication....

  9. A new SOI high-voltage device with a step-thickness drift region and its analytical model for the electric field and breakdown voltage

    International Nuclear Information System (INIS)

    Luo Xiaorong; Zhang Wei; Zhang Bo; Li Zhaoji; Yang Shouguo; Zhan Zhan; Fu Daping

    2008-01-01

    A new SOI high-voltage device with a step-thickness drift region (ST SOI) and its analytical model for the two-dimension electric field distribution and the breakdown voltage are proposed. The electric field in the drift region is modulated and that of the buried layer is enhanced by the variable thickness SOI layer, thereby resulting in the enhancement of the breakdown voltage. Based on the Poisson equation, the expression for the two-dimension electric field distribution is presented taking the modulation effect into account, from which the RESURF (REduced SURface Field) condition and the approximate but explicit expression for the maximal breakdown voltage are derived. The analytical model can explain the effects of the device parameters, such as the step height and the step length of the SOI layer, the doping concentration and the buried oxide thickness, on the electric field distribution and the breakdown voltage. The validity of this model is demonstrated by a comparison with numerical simulations. Improvement on both the breakdown voltage and the on-resistance (R on ) for the ST SOI is obtained due to the variable thickness SOI layer

  10. Charge accumulation in the buried oxide of SOI structures with the bonded Si/SiO2 interface under γ-irradiation: effect of preliminary ion implantation

    International Nuclear Information System (INIS)

    Naumova, O V; Fomin, B I; Ilnitsky, M A; Popov, V P

    2012-01-01

    In this study, we examined the effect of preliminary boron or phosphorous implantation on charge accumulation in the buried oxide of SOI-MOSFETs irradiated with γ-rays in the total dose range (D) of 10 5 –5 × 10 7 rad. The buried oxide was obtained by high-temperature thermal oxidation of Si, and it was not subjected to any implantation during the fabrication process of SOI structures. It was found that implantation with boron or phosphorous ions, used in fabrication technologies of SOI-MOSFETs, increases the concentration of precursor traps in the buried oxide of SOI structures. Unlike in the case of boron implantation, phosphorous implantation leads to an increased density of states at the Si/buried SiO 2 interface during subsequent γ-irradiation. In the γ-irradiated SOI-MOSFETs, the accumulated charge density and the density of surface states in the Si/buried oxide layer systems both vary in proportion to k i ln D. The coefficients k i for as-fabricated and ion-implanted Si/buried SiO 2 systems were evaluated. From the data obtained, it was concluded that a low density of precursor hole traps was a factor limiting the positive charge accumulation in the buried oxide of as-fabricated (non-implanted) SOI structures with the bonded Si/buried SiO 2 interface. (paper)

  11. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  12. Joint Research on Scatterometry and AFM Wafer Metrology

    Science.gov (United States)

    Bodermann, Bernd; Buhr, Egbert; Danzebrink, Hans-Ulrich; Bär, Markus; Scholze, Frank; Krumrey, Michael; Wurm, Matthias; Klapetek, Petr; Hansen, Poul-Erik; Korpelainen, Virpi; van Veghel, Marijn; Yacoot, Andrew; Siitonen, Samuli; El Gawhary, Omar; Burger, Sven; Saastamoinen, Toni

    2011-11-01

    Supported by the European Commission and EURAMET, a consortium of 10 participants from national metrology institutes, universities and companies has started a joint research project with the aim of overcoming current challenges in optical scatterometry for traceable linewidth metrology. Both experimental and modelling methods will be enhanced and different methods will be compared with each other and with specially adapted atomic force microscopy (AFM) and scanning electron microscopy (SEM) measurement systems in measurement comparisons. Additionally novel methods for sophisticated data analysis will be developed and investigated to reach significant reductions of the measurement uncertainties in critical dimension (CD) metrology. One final goal will be the realisation of a wafer based reference standard material for calibration of scatterometers.

  13. Coherent spin transport through a 350 micron thick silicon wafer.

    Science.gov (United States)

    Huang, Biqin; Monsma, Douwe J; Appelbaum, Ian

    2007-10-26

    We use all-electrical methods to inject, transport, and detect spin-polarized electrons vertically through a 350-micron-thick undoped single-crystal silicon wafer. Spin precession measurements in a perpendicular magnetic field at different accelerating electric fields reveal high spin coherence with at least 13pi precession angles. The magnetic-field spacing of precession extrema are used to determine the injector-to-detector electron transit time. These transit time values are associated with output magnetocurrent changes (from in-plane spin-valve measurements), which are proportional to final spin polarization. Fitting the results to a simple exponential spin-decay model yields a conduction electron spin lifetime (T1) lower bound in silicon of over 500 ns at 60 K.

  14. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  15. Comparison of short-circuit characteristics of trench gate and planar gate U-shaped channel SOI-LIGBTs

    Science.gov (United States)

    Zhang, Long; Zhu, Jing; Sun, Weifeng; Zhao, Minna; Huang, Xuequan; Chen, Jiajun; Shi, Longxing; Chen, Jian; Ding, Desheng

    2017-09-01

    Comparison of short-circuit (SC) characteristics of 500 V rated trench gate U-shaped channel (TGU) SOI-LIGBT and planar gate U-shaped channel (PGU) SOI-LIGBT is made for the first time in this paper. The on-state carrier profile of the TGU structure is reshaped by the dual trenches (a gate trench G1 and a hole barrier trench G2), which leads to a different conduction behavior from that of the PGU structure. The TGU structure exhibits a higher latchup immunity but a severer self-heating effect. At current density (JC) 640 A/cm2. Comparison of layouts and fabrication processes are also made between the two types of devices.

  16. Evaluation of COTS SiGe, SOI, and Mixed Signal Electronic Parts for Extreme Temperature Use in NASA Missions

    Science.gov (United States)

    Patterson, Richard L.; Hammoud, Ahmad

    2010-01-01

    The NASA Electronic Parts and Packaging (NEPP) Program sponsors a task at the NASA Glenn Research Center titled "Reliability of SiGe, SOI, and Advanced Mixed Signal Devices for Cryogenic Space Missions." In this task COTS parts and flight-like are evaluated by determining their performance under extreme temperatures and thermal cycling. The results from the evaluations are published on the NEPP website and at professional conferences in order to disseminate information to mission planners and system designers. This presentation discusses the task and the 2010 highlights and technical results. Topics include extreme temperature operation of SiGe and SOI devices, all-silicon oscillators, a floating gate voltage reference, a MEMS oscillator, extreme temperature resistors and capacitors, and a high temperature silicon operational amplifier.

  17. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  18. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  19. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  20. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    International Nuclear Information System (INIS)

    Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches