WorldWideScience

Sample records for inch silicon wafers

  1. Comparison of silicon strip tracker module size using large sensors from 6 inch wafers

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Two large silicon strip sensor made from 6 inch wafers are placed next to each other to simulate the size of a CMS outer silicon tracker module. On the left is a prototype 2 sensor CMS inner endcap silicon tracker module made from 4 inch wafers.

  2. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  3. Characterization of the first double-sided 3D radiation sensors fabricated at FBK on 6-inch silicon wafers

    International Nuclear Information System (INIS)

    Sultan, D.M.S.; Mendicino, R.; Betta, G.-F. Dalla; Boscardin, M.; Ronchin, S.; Zorzi, N.

    2015-01-01

    Following 3D pixel sensor production for the ATLAS Insertable B-Layer, Fondazione Bruno Kessler (FBK) fabrication facility has recently been upgraded to process 6-inch wafers. In 2014, a test batch was fabricated to check for possible issues relevant to this upgrade. While maintaining a double-sided fabrication technology, some process modifications have been investigated. We report here on the technology and the design of this batch, and present selected results from the electrical characterization of sensors and test structures. Notably, the breakdown voltage is shown to exceed 200 V before irradiation, much higher than in earlier productions, demonstrating robustness in terms of radiation hardness for forthcoming productions aimed at High Luminosity LHC upgrades

  4. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  5. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  6. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  7. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  8. The evolution of silicon wafer cleaning technology

    International Nuclear Information System (INIS)

    Kern, W.

    1990-01-01

    The purity of wafer surfaces is an essential requisite for the successful fabrication of VLSI and ULSI silicon circuits. Wafer cleaning chemistry has remained essentially unchanged in the past 25 years and is based on hot alkaline and acidic hydrogen peroxide solutions, a process known as RCA Standard Clean. This is still the primary method used in the industry. What has changed is its implementation with optimized equipment:from simple immersion to centrifugal spraying, megasonic techniques, and enclosed system processing that allow simultaneous removal of both contaminant films and particles. Improvements in wafer drying by use of isopropanol vapor or by slow-pull out of hot deionized water are being investigated. Several alternative cleaning methods are also being tested, including choline solutions, chemical vapor etching, and UV/ozone treatments. The evolution of silicon wafer cleaning processes and technology is traced and reviewed

  9. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  10. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  11. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  12. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding......Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...

  13. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  14. 1366 Direct Wafer: Demolishing the Cost Barrier for Silicon Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies

    2013-08-30

    The goal of 1366 Direct Wafer™ is to drastically reduce the cost of silicon-based PV by eliminating the cost barrier imposed by sawn wafers. The key characteristics of Direct Wafer are 1) kerf-free, 156-mm standard silicon wafers 2) high throughput for very low CAPEX and rapid scale up. Together, these characteristics will allow Direct Wafer™ to become the new standard for silicon PV wafers and will enable terawatt-scale PV – a prospect that may not be possible with sawn wafers. Our single, high-throughput step will replace the expensive and rate-limiting process steps of ingot casting and sawing, thereby enabling drastically lower wafer cost. This High-Impact PV Supply Chain project addressed the challenges of scaling Direct Wafer technology for cost-effective, high-throughput production of commercially viable 156 mm wafers. The Direct Wafer process is inherently simple and offers the potential for very low production cost, but to realize this, it is necessary to demonstrate production of wafers at high-throughput that meet customer specifications. At the start of the program, 1366 had demonstrated (with ARPA-E funding) increases in solar cell efficiency from 10% to 15.9% on small area (20cm2), scaling wafer size up to the industry standard 156mm, and demonstrated initial cell efficiency on larger wafers of 13.5%. During this program, the throughput of the Direct Wafer furnace was increased by more than 10X, simultaneous with quality improvements to meet early customer specifications. Dedicated equipment for laser trimming of wafers and measurement methods were developed to feedback key quality metrics to improve the process and equipment. Subsequent operations served both to determine key operating metrics affecting cost, as well as generating sample product that was used for developing downstream processing including texture and interaction with standard cell processing. Dramatic price drops for silicon wafers raised the bar significantly, but the

  15. Low-Cost, Manufacturable, 6-Inch Wafer Bonding Process for Next-Generation 5-Junction IMM+Ge Photovoltaic Devices Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose the development of a 6-inch wafer bonding process to allow bonding of a multi-junction inverted metamorphic (IMM) tandem solar cell structure to an...

  16. Metallization of large silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Pryor, R A

    1979-01-01

    A metallization scheme has been developed which allows selective plating of silicon solar cell surfaces. The system is comprised of three layers. Palladium, through the formation of palladium silicide at 300/sup 0/C in nitrogen, makes ohmic contact to the silicon surface. Nickel, plated on top of the palladium silicide layer, forms a solderable interface. Lead-tin solder on the nickel provides conductivity and allows a convenient means for interconnection of cells. To apply this metallization, three chemical plating baths are employed. Palladium is deposited with an immersion palladium solution and an electroless palladium solution, and nickel is deposited with an electroless nickel solution. Solder is applied with a molten solder dip. Extensive development work has been performed to achieve an effective immersion palladium solution formulation, leading to reproducible formation of the palladium silicide contact layer. This metallization system has been repeatedly demonstrated to be extremely effective. Current-voltage characteristic curve fill factors of 78% are easily achieved. This has been done while maintaining metal contact adhesion at such a strength as to fail by fracturing silicon upon perpendicular pull testing rather than be delaminating the metal system. Process specifications and procedures have been prepared.

  17. Chemical method for producing smooth surfaces on silicon wafers

    Science.gov (United States)

    Yu, Conrad

    2003-01-01

    An improved method for producing optically smooth surfaces in silicon wafers during wet chemical etching involves a pre-treatment rinse of the wafers before etching and a post-etching rinse. The pre-treatment with an organic solvent provides a well-wetted surface that ensures uniform mass transfer during etching, which results in optically smooth surfaces. The post-etching treatment with an acetic acid solution stops the etching instantly, preventing any uneven etching that leads to surface roughness. This method can be used to etch silicon surfaces to a depth of 200 .mu.m or more, while the finished surfaces have a surface roughness of only 15-50 .ANG. (RMS).

  18. Thin-film resistance thermometers on silicon wafers

    International Nuclear Information System (INIS)

    Kreider, Kenneth G; Ripple, Dean C; Kimes, William A

    2009-01-01

    We have fabricated Pt thin-film resistors directly sputtered on silicon substrates to evaluate their use as resistance thermal detectors (RTDs). This technique was chosen to achieve more accurate temperature measurements of large silicon wafers during semiconductor processing. High-purity (0.999 968 mass fraction) platinum was sputter deposited on silicon test coupons using titanium and zirconium bond coats. These test coupons were annealed, and four-point resistance specimens were prepared for thermal evaluation. Their response was compared with calibrated platinum–palladium thermocouples in a tube furnace. We evaluated the effects of furnace atmosphere, thin-film thickness, bond coats, annealing temperature and peak thermal excursion of the Pt thin films. Secondary ion mass spectrometry (SIMS) was performed to evaluate the effect of impurities on the thermal resistance coefficient, α. We present typical resistance versus temperature curves, hysteresis plots versus temperature and an analysis of the causes of uncertainties in the measurement of seven test coupons. We conclude that sputtered thin-film platinum resistors on silicon wafers can yield temperature measurements with uncertainties of less than 1 °C, k = 1 up to 600 °C. This is comparable to or better than commercially available techniques

  19. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  20. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  1. An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.; Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Visschers, J.L.

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 μm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication

  2. An electron-multiplying 'Micromegas' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.; Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Visschers, J.L.

    2005-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 μm by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication

  3. An electron-multiplying ''Micromegas'' grid made in silicon wafer post-processing technology

    NARCIS (Netherlands)

    Chefdeville, M.A.; Colas, P.; Giomataris, Y.; van der Graaf, H.; Heijne, E.H.M.; van der Putten, S.; Salm, Cora; Schmitz, Jurriaan; Smits, Sander M.; Timmermans, J.; Timmermans, J.; Visschers, J.L.

    2005-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 mm by means of insulating pillars. When some 400V are applied between the grid and (anode) wafer, gas multiplication

  4. Nanomanipulation of 2 inch wafer fabrication of vertically aligned carbon nanotube arrays by nanoimprint lithography

    DEFF Research Database (Denmark)

    Bu, Ian Y. Y.; Eichhorn, Volkmar; Carlson, Kenneth

    2011-01-01

    Carbon nanotube (CNT) arrays are typically defined by electron beam lithography (EBL), and hence limited to small areas due to the low throughput. To obtain wafer‐scale fabrication we propose large area thermal nanoimprint lithography (NIL). A 2‐inch stamp master is defined using EBL for subsequent......, efficient production of wafer‐scale/larger arrays of CNTs has been achieved. The CNTs have been deposited by wafer‐scale plasma enhanced chemical vapour deposition (PECVD) of C2H2/NH3. Substrates containing such nanotubes have been used to automate nanorobotic manipulation sequences of individual CNTs...

  5. Ambient plasma treatment of silicon wafers for surface passivation recovery

    Science.gov (United States)

    Ge, Jia; Prinz, Markus; Markert, Thomas; Aberle, Armin G.; Mueller, Thomas

    2017-08-01

    In this work, the effect of an ambient plasma treatment powered by compressed dry air on the passivation quality of silicon wafers coated with intrinsic amorphous silicon sub-oxide is investigated. While long-time storage deteriorates the effective lifetime of all samples, a short ambient plasma treatment improves their passivation qualities. By studying the influence of the plasma treatment parameters on the passivation layers, an optimized process condition was identified which even boosted the passivation quality beyond its original value obtained immediately after deposition. On the other hand, the absence of stringent requirement on gas precursors, vacuum condition and longtime processing makes the ambient plasma treatment an excellent candidate to replace conventional thermal annealing in industrial heterojunction solar cell production.

  6. Simulation Research on Micro Contact Based on Force in Silicon Wafer Rotation Grinding

    Science.gov (United States)

    Ren, Qinglei; Wei, Xin; Xie, Xiaozhu; Hu, Wei

    2017-10-01

    Silicon wafer rotation grinding with cup type diamond wheel is a typical ultra precision grinding process. In this paper, a simulation model based on force for micro contact between wheel micro unit and silicon wafer is established from the stable ductile grinding process. Micro contact process in grinding is simulated using the nonlinear explicit finite element analysis software LS-DYNA. The stress-strain results on silicon wafer and wheel micro unit are analyzed by finite element method. The results show that the critical displacement and load corresponding elastic to plastic - plastic to brittle exist on silicon wafer. In silicon plastic zone tangential sliding can produce plastic groove and uplift. Wear of wheel micro unit can be based on the simulation data to judge. The research provides support for wafer grinding and wheel wear mechanism.

  7. Comparison on mechanical properties of heavily phosphorus- and arsenic-doped Czochralski silicon wafers

    Science.gov (United States)

    Yuan, Kang; Sun, Yuxin; Lu, Yunhao; Liang, Xingbo; Tian, Daxi; Ma, Xiangyang; Yang, Deren

    2018-04-01

    Heavily phosphorus (P)- and arsenic (As)-doped Czochralski silicon (CZ-Si) wafers generally act as the substrates for the epitaxial silicon wafers used to fabricate power and communication devices. The mechanical properties of such two kinds of n-type heavily doped CZ silicon wafers are vital to ensure the quality of epitaxial silicon wafers and the manufacturing yields of devices. In this work, the mechanical properties including the hardness, Young's modulus, indentation fracture toughness and the resistance to dislocation motion have been comparatively investigated for heavily P- and As-doped CZ-Si wafers. It is found that heavily P-doped CZ-Si possesses somewhat higher hardness, lower Young's modulus, larger indentation fracture toughness and stronger resistance to dislocation motion than heavily As-doped CZ-Si. The mechanisms underlying this finding have been tentatively elucidated by considering the differences in the doping effects of P and As in silicon.

  8. Optical pressure sensor head fabrication using ultrathin silicon wafer anodic bonding

    Science.gov (United States)

    Beggans, Michael H.; Ivanov, Dentcho I.; Fu, Steven G.; Digges, Thomas G., III; Farmer, Kenneth R.

    1999-03-01

    A technology for fabricating fiber optically interrogated pressure sensors is described. This technology is based on anodic bonding of ultra-thin silicon wafers to patterned, micro-machined glass wafers, providing low-cost fabrication of optical pressure sensor heads that operate with reproducible technical characteristics in various dynamic ranges. Pressure sensors using 10, 20 and 50 micron thick silicon wafers for membranes have been fabricated on 10 cm diameter, 500-micron thick, Pyrex glass wafers. The glass wafers have been micro-machined using ultrasonic drilling in order to form cavities, optical fiber feedthrough holes and vent holes. One of the main challenges of the manufacturing process is the handling of the ultra-thin silicon wafers. Being extremely flexible, the thin silicon wafers cannot be cleaned, oxidized, or dried in the same way as normal since wafers with a thickness of the order of 400 microns. Specific handling techniques have been developed in order to achieve reproducible cleaning and oxidation processes. The anodic bonding was performed using an Electronic Visions EV501S bonder. The wafers were heated at 420 degrees C and a voltage of 1200 volts was applied in vacuum of 10-5 Torr. The bonded wafer stack was then fixed in a wax and diced. The resulting chips have been used to fabricate operating pressure sensors.

  9. Locally-enhanced light scattering by a monocrystalline silicon wafer

    Directory of Open Access Journals (Sweden)

    Li Ma

    2018-03-01

    Full Text Available We study the optical properties of light scattering by a monocrystalline silicon wafer, by using transparent material to replicate its surface structure and illuminating a fabricated sample with a laser source. The experimental results show that the scattering field contains four spots of concentrated intensity with high local energy, and these spots are distributed at the four vertices of a square with lines of intensity linking adjacent spots. After discussing simulations of and theory about the formation of this light scattering, we conclude that the scattering field is formed by the effects of both geometrical optics and physical optics. Moreover, we calculate the central angle of the spots in the light field, and the result indicates that the locally-enhanced intensity spots have a definite scattering angle. These results may possibly provide a method for improving energy efficiency within mono-Si based solar cells.

  10. Delineation of Crystalline Extended Defects on Multicrystalline Silicon Wafers

    Directory of Open Access Journals (Sweden)

    Mohamed Fathi

    2007-01-01

    Full Text Available We have selected Secco and Yang etch solutions for the crystalline defect delineation on multicrystalline silicon (mc-Si wafers. Following experimentations and optimization of Yang and Secco etching process parameters, we have successfully revealed crystalline extended defects on mc-Si surfaces. A specific delineation process with successive application of Yang and Secco agent on the same sample has proved the increased sensitivity of Secco etch to crystalline extended defects in mc-Si materials. The exploration of delineated mc-Si surfaces indicated that strong dislocation densities are localized mainly close to the grain boundaries and on the level of small grains in size (below 1 mm. Locally, we have observed the formation of several parallel dislocation lines, perpendicular to the grain boundaries. The overlapping of several dislocations lines has revealed particular forms for etched pits of dislocations.

  11. Fabrication of PIN diode detectors on thinned silicon wafers

    CERN Document Server

    Ronchin, Sabina; Dalla Betta, Gian Franco; Gregori, Paolo; Guarnieri, Vittorio; Piemonte, Claudio; Zorzi, Nicola

    2004-01-01

    Thin substrates are one of the possible choices to provide radiation hard detectors for future high-energy physics experiments. Among the advantages of thin detectors are the low full depletion voltage, even after high particle fluences, the improvement of the tracking precision and momentum resolution and the reduced material budget. In the framework of the CERN RD50 Collaboration, we have developed p-n diode detectors on membranes obtained by locally thinning the silicon substrate by means of tetra-methyl ammonium hydroxide etching from the wafer backside. Diodes of different shapes and sizes have been fabricated on 57 and 99mum thick membranes. They have been tested, showing a very low leakage current ( less than 0.4nA/cm**2) and, as expected, a very low depletion voltage ( less than 1V for the 57mum membrane). The paper describes the technological approach used for devices fabrication and reports selected results from the electrical characterization.

  12. "Silicon millefeuille": From a silicon wafer to multiple thin crystalline films in a single step

    Science.gov (United States)

    Hernández, David; Trifonov, Trifon; Garín, Moisés; Alcubilla, Ramon

    2013-04-01

    During the last years, many techniques have been developed to obtain thin crystalline films from commercial silicon ingots. Large market applications are foreseen in the photovoltaic field, where important cost reductions are predicted, and also in advanced microelectronics technologies as three-dimensional integration, system on foil, or silicon interposers [Dross et al., Prog. Photovoltaics 20, 770-784 (2012); R. Brendel, Thin Film Crystalline Silicon Solar Cells (Wiley-VCH, Weinheim, Germany 2003); J. N. Burghartz, Ultra-Thin Chip Technology and Applications (Springer Science + Business Media, NY, USA, 2010)]. Existing methods produce "one at a time" silicon layers, once one thin film is obtained, the complete process is repeated to obtain the next layer. Here, we describe a technology that, from a single crystalline silicon wafer, produces a large number of crystalline films with controlled thickness in a single technological step.

  13. Introduction of high oxygen concentrations into silicon wafers by high-temperature diffusion

    CERN Document Server

    Casse, G L; Lemeilleur, F; Ruzin, A; Wegrzecki, M

    1999-01-01

    The tolerance of silicon detectors to hadron irradiation can be improved by the introduction of a high concentration of oxygen into the starting material. High-resistivity Floating-Zone (FZ) silicon is required for detectors used in particle physics applications. A significantly high oxygen concentration (>10/sup 17/ atoms cm/sup -3 /) cannot readily be achieved during the FZ silicon refinement. The diffusion of oxygen at elevated temperatures from a SiO/sub 2/ layer grown on both sides of a silicon wafer is a simple and effective technique to achieve high and uniform concentrations of oxygen throughout the bulk of a 300 mu m thick silicon wafer. (7 refs).

  14. Electronic properties of interfaces produced by silicon wafer hydrophilic bonding

    Energy Technology Data Exchange (ETDEWEB)

    Trushin, Maxim

    2011-07-15

    The thesis presents the results of the investigations of electronic properties and defect states of dislocation networks (DNs) in silicon produced by wafers direct bonding technique. A new insight into the understanding of their very attractive properties was succeeded due to the usage of a new, recently developed silicon wafer direct bonding technique, allowing to create regular dislocation networks with predefined dislocation types and densities. Samples for the investigations were prepared by hydrophilic bonding of p-type Si (100) wafers with same small misorientation tilt angle ({proportional_to}0.5 ), but with four different twist misorientation angles Atw (being of < , 3 , 6 and 30 , respectively), thus giving rise to the different DN microstructure on every particular sample. The main experimental approach of this work was the measurements of current and capacitance of Schottky diodes prepared on the samples which contained the dislocation network at a depth that allowed one to realize all capabilities of different methods of space charge region spectroscopy (such as CV/IV, DLTS, ITS, etc.). The key tasks for the investigations were specified as the exploration of the DN-related gap states, their variations with gradually increasing twist angle Atw, investigation of the electrical field impact on the carrier emission from the dislocation-related states, as well as the establishing of the correlation between the electrical (DLTS), optical (photoluminescence PL) and structural (TEM) properties of DNs. The most important conclusions drawn from the experimental investigations and theoretical calculations can be formulated as follows: - DLTS measurements have revealed a great difference in the electronic structure of small-angle (SA) and large-angle (LA) bonded interfaces: dominating shallow level and a set of 6-7 deep levels were found in SA-samples with Atw of 1 and 3 , whereas the prevalent deep levels - in LA-samples with Atw of 6 and 30 . The critical twist

  15. Laser cleaning of silicon wafers: mechanisms and efficiencies

    Science.gov (United States)

    Mosbacher, Mario; Bertsch, M.; Muenzer, H.-J.; Dobler, V.; Runge, B.-U.; Baeuerle, Dieter; Boneberg, Johannes; Leiderer, Paul

    2002-02-01

    We report on experiments on the underlying physical mechanisms in the Dry-(DLC) and Steam Laser Cleaning (SLC) process. Using a frequency doubled, Q-switched Nd:YAG laser (FWHMequals8 ns), we removed polystyrene (PS) particles with diameters from 110-2000 nm from industrial silicon wafers by the DLC process. The experiments have been carried out both in ambient conditions as well as in high vacuum (10-6mbar) and the cleaned areas have been characterized by atomic force microscopy for damage inspection. Besides the determining the cleaning thresholds in laser fluence for a large interval of particle sizes we could show that particle removal in DLC is due to a combination of at least three effects: thermal substrate expansion, local substrate ablation due to field enhancement at the particle and explosive evaporation of absorbed humidity from the air. Which effect dominates the process is subject to the boundary conditions. For our laser parameters no damage free DLC was possible, i.e. whenever a particle was removed by DLC we damaged the substrate by local field enhancement. In our SLC experiments we determined the amount of superheating of a liquid layer adjacent to surfaces with controlled roughness that is necessary, in good agreement with theoretical predictions. Rough surfaces exhibited only a much smaller superheating.

  16. Synchrotron radiation total reflection x-ray fluorescence analysis; of polymer coated silicon wafers

    International Nuclear Information System (INIS)

    Brehm, L.; Kregsamer, P.; Pianetta, P.

    2000-01-01

    It is well known that total reflection x-ray fluorescence (TXRF) provides an efficient method for analyzing trace metal contamination on silicon wafer surfaces. New polymeric materials used as interlayer dielectrics in microprocessors are applied to the surface of silicon wafers by a spin-coating process. Analysis of these polymer coated wafers present a new challenge for TXRF analysis. Polymer solutions are typically analyzed for bulk metal contamination prior to application on the wafer using inductively coupled plasma mass spectrometry (ICP-MS). Questions have arisen about how to relate results of surface contamination analysis (TXRF) of a polymer coated wafer to bulk trace analysis (ICP-MS) of the polymer solutions. Experiments were done to explore this issue using synchrotron radiation (SR) TXRF. Polymer solutions were spiked with several different concentrations of metals. These solutions were applied to silicon wafers using the normal spin-coating process. The polymer coated wafers were then measured using the SR-TXRF instrument set-up at the Stanford Synchrotron Radiation Laboratory (SSRL). Several methods of quantitation were evaluated. The best results were obtained by developing calibration curves (intensity versus ppb) using the spiked polymer coated wafers as standards. Conversion of SR-TXRF surface analysis results (atoms/cm 2 ) to a volume related concentration was also investigated. (author)

  17. Characterization of perovskite layer on various nanostructured silicon wafer

    Science.gov (United States)

    Rostan, Nur Fairuz Mohd; Sepeai, Suhaila; Ramli, Noor Fadhilah; Azhari, Ayu Wazira; Ludin, Norasikin Ahmad; Teridi, Mohd Asri Mat; Ibrahim, Mohd Adib; Zaidi, Saleem H.

    2017-05-01

    Crystalline silicon (c-Si) solar cell dominates 90% of photovoltaic (PV) market. The c-Si is the most mature of all PV technologies and expected to remain leading the PV technology by 2050. The attractive characters of Si solar cell are stability, long lasting and higher lifetime. Presently, the efficiency of c-Si solar cell is still stuck at 25% for one and half decades. Tandem approach is one of the attempts to improve the Si solar cell efficiency with higher bandgap layer is stacked on top of Si bottom cell. Perovskite offers a big potential to be inserted into a tandem solar cell. Perovskite with bandgap of 1.6 to 1.9 eV will be able to absorb high energy photons, meanwhile c-Si with bandgap of 1.124 eV will absorb low energy photons. The high carrier mobility, high carrier lifetime, highly compatible with both solution and evaporation techniques makes perovskite an eligible candidate for perovskite-Si tandem configuration. The solution of methyl ammonium lead iodide (MAPbI3) was prepared by single step precursor process. The perovskite layer was deposited on different c-Si surface structure, namely planar, textured and Si nanowires (SiNWs) by using spin-coating technique at different rotation speeds. The nanostructure of Si surface was textured using alkaline based wet chemical etching process and SiNW was grown using metal assisted etching technique. The detailed surface morphology and absorbance of perovskite were studied in this paper. The results show that the thicknesses of MAPbI3 were reduced with the increasing of rotation speed. In addition, the perovskite layer deposited on the nanostructured Si wafer became rougher as the etching time and rotation speed increased. The average surface roughness increased from ˜24 nm to ˜38 nm for etching time range between 5-60 min at constant low rotation speed (2000 rpm) for SiNWs Si wafer.

  18. Crack detection and analyses using resonance ultrasonic vibrations in full-size crystalline silicon wafers

    International Nuclear Information System (INIS)

    Belyaev, A.; Polupan, O.; Dallas, W.; Ostapenko, S.; Hess, D.; Wohlgemuth, J.

    2006-01-01

    An experimental approach for fast crack detection and length determination in full-size solar-grade crystalline silicon wafers using a resonance ultrasonic vibrations (RUV) technique is presented. The RUV method is based on excitation of the longitudinal ultrasonic vibrations in full-size wafers. Using an external piezoelectric transducer combined with a high sensitivity ultrasonic probe and computer controlled data acquisition system, real-time frequency response analysis can be accomplished. On a set of identical crystalline Si wafers with artificially introduced periphery cracks, it was demonstrated that the crack results in a frequency shift in a selected RUV peak to a lower frequency and increases the resonance peak bandwidth. Both characteristics were found to increase with the length of the crack. The frequency shift and bandwidth increase serve as reliable indicators of the crack appearance in silicon wafers and are suitable for mechanical quality control and fast wafer inspection

  19. Improvement of surface roughness in silicon-on-insulator wafer fabrication using a neutral beam etching

    Science.gov (United States)

    Min, T. H.; Park, B. J.; Kang, S. K.; Gweon, G. H.; Kim, Y. Y.; Yeom, G. Y.

    2009-08-01

    Silicon-on-insulator (SOI) wafers were etched by an energetic chlorine neutral beam obtained by the low-angle forward reflection of an ion beam, and the surface roughness of the etched wafers was compared with that of the SOI wafers etched by an energetic chlorine ion beam. When the ion beam was used to etch the silicon layer of the SOI wafers, the surface roughness was not significantly changed even though the use of higher ion bombardment energy slightly decreased the surface roughness of the SOI wafer. However, when the chlorine neutral beam was used instead of the chlorine ion beam having a similar beam energy, the surface roughness of the SOI wafer was significantly improved compared with that etched by the chlorine ion beam. By etching about 150 nm silicon from the SOI wafer having a 300 nm-thick top silicon layer with the chlorine neutral beam at the energy of 500 eV, the rms surface roughness of 1.5 Å could be obtained with the etch rate of about 750 Å min-1.

  20. AFM study of hippocampal cells cultured on silicon wafers with nano-scale surface topograph.

    Science.gov (United States)

    Ma, J; Liu, B F; Xu, Q Y; Cui, F Z

    2005-08-01

    The rat hippocampal cells were selected as model to study the interaction between the neural cells and silicon substrates using atomic force microscopy (AFM). The hippocampal cells show tight adherence on silicon wafers with nano-scale surface topograph. The lateral friction force investigated by AFM shows significant increase on the boundary around the cellular body. It is considered to relate to the cytoskeleton and cellular secretions. After ultrasonic wash in ethanol and acetone step by step, the surface of silicon wafers was observed by AFM sequentially. We have found that the culture leftovers form tight porous networks and a monolayer on the silicon wafers. It is concluded that the leftovers overspreading on the silicon substrates are the base of cell adherence on such smooth inert surfaces.

  1. Wafer scale nano-membrane supported on a silicon microsieve using thin-film transfer technology

    NARCIS (Netherlands)

    Unnikrishnan, S.; Jansen, Henricus V.; Berenschot, Johan W.; Elwenspoek, Michael Curt

    A new micromachining method to fabricate wafer scale nano-membranes is described. The delicate thin-film nano-membrane is supported on a robust silicon microsieve fabricated by plasma etching. The silicon sieve is micromachined independently of the thin-film, which is later transferred onto it by

  2. Micropore x-ray optics using anisotropic wet etching of (110) silicon wafers

    International Nuclear Information System (INIS)

    Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Mitsuda, Kazuhisa; Hoshino, Akio; Ishisaki, Yoshitaka; Yang Zhen; Takano, Takayuki; Maeda, Ryutaro

    2006-01-01

    To develop x-ray mirrors for micropore optics, smooth silicon (111)sidewalls obtained after anisotropic wet etching of a silicon (110) wafer were studied. A sample device with 19 μm wide (111) sidewalls was fabricated using a 220 μm thick silicon (110) wafer and potassium hydroxide solution. For what we believe to be the first time,x-ray reflection on the (111) sidewalls was detected in the angular response measurement. Compared to ray-tracing simulations, the surface roughness of the sidewalls was estimated to be 3-5 nm, which is consistent with the atomic force microscope and the surface profiler measurements

  3. Silicon wafer wettability and aging behaviors: Impact on gold thin-film morphology

    KAUST Repository

    Yang, Xiaoming

    2014-10-01

    This paper reports on the wettability and aging behaviors of the silicon wafers that had been cleaned using a piranha (3:1 mixture of sulfuric acid (H2SO4, 96%) and hydrogen peroxide (H2O 2, 30%), 120 °C), SC1 (1:1:5 mixture of NH4OH, H 2O2 and H2O, at 80°C) or HF solution (6 parts of 40% NH4F and 1 part of 49% HF, at room temperature) solution, and treated with gaseous plasma. The silicon wafers cleaned using the piranha or SC1 solution were hydrophilic, and the water contact angles on the surfaces would increase along with aging time, until they reached the saturated points of around 70°. The contact angle increase rate of these wafers in a vacuum was much faster than that in the open air, because of loss of water, which was physically adsorbed on the wafer surfaces. The silicon wafers cleaned with the HF solution were hydrophobic. Their contact angle decreased in the atmosphere, while it increased in the vacuum up to 95°. Gold thin films deposited on the hydrophilic wafers were smoother than that deposited on the hydrophobic wafers, because the numerous oxygen groups formed on the hydrophilic surfaces would react with gold adatoms in the sputtering process to form a continuous thin film at the nucleation stage. The argon, nitrogen, oxygen gas plasma treatments could change the silicon wafer surfaces from hydrophobic to hydrophilic by creating a thin (around 2.5 nm) silicon dioxide film, which could be utilized to improve the roughness and adhesion of the gold thin film. © 2014 Elsevier Ltd. All rights reserved.

  4. Development of Megasonic cleaning for silicon wafers. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, A.

    1980-09-01

    The major goals to develop a cleaning and drying system for processing at least 2500 three-in.-diameter wafers per hour and to reduce the process cost were achieved. The new system consists of an ammonia-hydrogen peroxide bath in which both surfaces of 3/32-in.-spaced, ion-implanted wafers are cleaned in quartz carriers moved on a belt past two pairs of Megasonic transducers. The wafers are dried in the novel room-temperature, high-velocity air dryer in the same carriers used for annealing. A new laser scanner was used effectively to monitor the cleaning ability on a sampling basis. The following factors contribute to the improved effectiveness of the process: (1) recirculation and filtration of the cleaning solution permit it to be used for at least 100,000 wafers with only a relatively small amount of chemical make-up before discarding; (2) uniform cleanliness is achieved because both sides of the wafer are Megasonically scrubbed to remove particulate impurities; (3) the novel dryer permits wafers to be dried in a high-velocity room-temperature air stream on a moving belt in their quartz carriers; and (4) the personnel safety of such a system is excellent and waste disposal has no adverse ecological impact. With the addition of mechanical transfer arms, two systems like the one developed will produce enough cleaned wafers for a 30-MW/year production facility. A projected scale-up well within the existing technology would permit a system to be assembled that produces about 12,745 wafers per hour; about 11 such systems, each occupying about 110 square feet, would be needed for each cleaning stage of a 500-MW/year production facility.

  5. Nonequilibrium Growth of GaN/Si(1-x-y)Ge(x)C(y)/Silicon-on-Insulator

    National Research Council Canada - National Science Library

    Ho, Wilson

    2000-01-01

    ... of this growth technique. Research highlights include the successful growth of silicon carbide, gallium nitride, and aluminum nitride thin films on silicon and miscut silicon substrates, on four-inches silicon wafers...

  6. Laser cutting sandwich structure glass-silicon-glass wafer with laser induced thermal-crack propagation

    Science.gov (United States)

    Cai, Yecheng; Wang, Maolu; Zhang, Hongzhi; Yang, Lijun; Fu, Xihong; Wang, Yang

    2017-08-01

    Silicon-glass devices are widely used in IC industry, MEMS and solar energy system because of their reliability and simplicity of the manufacturing process. With the trend toward the wafer level chip scale package (WLCSP) technology, the suitable dicing method of silicon-glass bonded structure wafer has become necessary. In this paper, a combined experimental and computational approach is undertaken to investigate the feasibility of cutting the sandwich structure glass-silicon-glass (SGS) wafer with laser induced thermal-crack propagation (LITP) method. A 1064 nm semiconductor laser cutting system with double laser beams which could simultaneously irradiate on the top and bottom of the sandwich structure wafer has been designed. A mathematical model for describing the physical process of the interaction between laser and SGS wafer, which consists of two surface heating sources and two volumetric heating sources, has been established. The temperature stress distribution are simulated by using finite element method (FEM) analysis software ABAQUS. The crack propagation process is analyzed by using the J-integral method. In the FEM model, a stationary planar crack is embedded in the wafer and the J-integral values around the crack front edge are determined using the FEM. A verification experiment under typical parameters is conducted and the crack propagation profile on the fracture surface is examined by the optical microscope and explained from the stress distribution and J-integral value.

  7. Adhesion of neural cells on silicon wafer with nano-topographic surface

    Science.gov (United States)

    Fan, Y. W.; Cui, F. Z.; Chen, L. N.; Zhai, Y.; Xu, Q. Y.; Lee, I.-S.

    2002-02-01

    The adherence and subsequent viability of central neural cells (substantia nigra) on silicon wafers with different surface roughness conditions were investigated. Various roughness conditions of the silicon wafer were achieved by etching at different times. The topography was evaluated by AFM. Primary neurons were obtained from Wistar rats. The adherence and subsequent viability of the cells on the wafer were examined by scanning electronic microscopy and fluorescence immunostaining of tyrosine hydroxylase. It is found that the surface roughness affects significantly cell adhesion and viability. Cells can survive for over 5 days on the surface with average roughness in the range 20-70 nm. Such a treatment may provide a new method to make a mild interface of silicon-based electronic devices and neurons as well as other living tissues.

  8. Hermetic Encapsulation of Nanoenergetic Porous Silicon Wafer by Parylene

    Science.gov (United States)

    2014-08-01

    hygroscopic nature of the oxidizer. Parylene films are generally known to be impervious to moisture and liquids , which make them attractive for hermetic...Energetic materials that are hygroscopic in nature need to be protected from the environment during storage to improved ignition lifetime. Parylene...surfaces. Our existing deposition chamber is approximately 10 inches in diameter and 12 inches high. A liquid nitrogen cold trap, located between the

  9. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  10. Nano silver-catalyzed chemical etching of polycrystalline silicon wafer for solar cell application

    Directory of Open Access Journals (Sweden)

    S. R. Chen

    2016-03-01

    Full Text Available Silver nanoparticles were deposited on the surface of polycrystalline silicon wafer via vacuum thermal evaporation and metal-catalyzed chemical etching (MCCE was conducted in a HF-H2O2 etching system. Treatment of the etched silicon wafer with HF transformed the textured structure on the surface from nanorods into nanocones. An etching time of 30 s and treatment with HF resulted in nanocones with uniform size distribution and a reflectivity as low as 1.98% across a spectral range from 300 to 1000 nm.

  11. Bismuth onion thin film in situ grown on silicon wafer synthesized through a hydrothermal approach

    International Nuclear Information System (INIS)

    Zhao Yue; Liu Hong; Liu Jin; Hu Chenguo; Wang Jiyang

    2010-01-01

    Bismuth onion structured nanospheres with the same structure as carbon onions have been synthesized and observed. The nanospheres were synthesized through a hydrothermal method using bismuth hydroxide and silicon wafer as reactants. By controlling the heating temperature, heating time, and the pressure, nanoscale bismuth spheres can be in situ synthesized on silicon wafer, and forms a bismuth onion film on the substrate. The electronic property of the films was investigated. A formation mechanism of the formation of bismuth onions and the onion film has been proposed on the basis of experimental observations.

  12. Sheet resistance uniformity in drive-in step for different multi-crystalline silicon wafer dispositions

    Energy Technology Data Exchange (ETDEWEB)

    Moussi, A.; Bouhafs, D.; Mahiou, L. [Laboratoire des Cellules Photovoltaiques, Unite de Developpement de la Technologie du Silicium, 2 Bd, Frantz Fanon, B.P. 140, 7 Merveilles Alger (Algeria); Belkaid, M.S. [Dep. Electronique, Faculte de Genie Electrique et Informatique, UMMTO (Algeria)

    2009-09-15

    In this work, we present a study of emitters realized using different configurations of the silicon wafers in the quartz boat. The phosphorous liquid source is sprayed onto p-type multi-crystalline silicon substrates and the drive-in is made at high temperature in a muffle furnace. Three different configurations of the wafers in the boat are tested: separated, back to back and compact block of wafers. A fourth configuration is also used in source-receptor mode. The emitter phosphorous concentration profile is obtained by SIMS analysis. The resulting emitters are characterized by sheet resistance measurements and a comparison is made between the wafers within the same batch and from one batch to another. The uniformity and the standard deviation of the sheet resistance are calculated in each case. The emitter sheet resistance mapping of the wafer set in the middle of the boat for a given process gives a mean R{sub sq} 14.66 {omega}/sq with a standard deviation of 1.76% and uniformity of 18.7%. Standard deviations of 2.116% and 1.559% are obtained for wafers in the batch when using the spaced and compact configurations, respectively. The standard deviation is reduced to 0.68% when the wafers are used in source/receptor mode. A comparison is also made between wafers with different dilution of phosphorous source in ethanol. From these results we can conclude that the compact configuration offers better uniformity and lower standard deviation. Furthermore, when combined with the source-receptor configuration these parameters are significantly improved. This study allows the experimenter to identify the technological parameters of the solar cell emitter manufacturing and target precisely the desired values of the sheet resistance while limiting the number of rejected wafers. (author)

  13. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  14. Aerosol-assisted extraction of silicon nanoparticles from wafer slicing waste for lithium ion batteries.

    Science.gov (United States)

    Jang, Hee Dong; Kim, Hyekyoung; Chang, Hankwon; Kim, Jiwoong; Roh, Kee Min; Choi, Ji-Hyuk; Cho, Bong-Gyoo; Park, Eunjun; Kim, Hansu; Luo, Jiayan; Huang, Jiaxing

    2015-03-30

    A large amount of silicon debris particles are generated during the slicing of silicon ingots into thin wafers for the fabrication of integrated-circuit chips and solar cells. This results in a significant loss of valuable materials at about 40% of the mass of ingots. In addition, a hazardous silicon sludge waste is produced containing largely debris of silicon, and silicon carbide, which is a common cutting material on the slicing saw. Efforts in material recovery from the sludge and recycling have been largely directed towards converting silicon or silicon carbide into other chemicals. Here, we report an aerosol-assisted method to extract silicon nanoparticles from such sludge wastes and their use in lithium ion battery applications. Using an ultrasonic spray-drying method, silicon nanoparticles can be directly recovered from the mixture with high efficiency and high purity for making lithium ion battery anode. The work here demonstrated a relatively low cost approach to turn wafer slicing wastes into much higher value-added materials for energy applications, which also helps to increase the sustainability of semiconductor material and device manufacturing.

  15. Crystallographic Orientation Identification in Multicrystalline Silicon Wafers Using NIR Transmission Intensity

    Science.gov (United States)

    Skenes, Kevin; Kumar, Arkadeep; Prasath, R. G. R.; Danyluk, Steven

    2018-02-01

    Near-infrared (NIR) polariscopy is a technique used for the non-destructive evaluation of the in-plane stresses in photovoltaic silicon wafers. Accurate evaluation of these stresses requires correct identification of the stress-optic coefficient, a material property which relates photoelastic parameters to physical stresses. The material stress-optic coefficient of silicon varies with crystallographic orientation. This variation poses a unique problem when measuring stresses in multicrystalline silicon (mc-Si) wafers. This paper concludes that the crystallographic orientation of silicon can be estimated by measuring the transmission of NIR light through the material. The transmission of NIR light through monocrystalline wafers of known orientation were compared with the transmission of NIR light through various grains in mc-Si wafers. X-ray diffraction was then used to verify the relationship by obtaining the crystallographic orientations of these assorted mc-Si grains. Variation of transmission intensity for different crystallographic orientations is further explained by using planar atomic density. The relationship between transmission intensity and planar atomic density appears to be linear.

  16. Light coupling and light trapping in alkaline etched multicrystalline silicon wafers for solar cells

    NARCIS (Netherlands)

    Hylton, J.D.

    2006-01-01

    The reflection reducing and light trapping properties of alkaline etched multicrystalline silicon wafers are investigated experimentally. Following an overview of various chemical texturisation methods and their effect upon the surface morphology, a high concentration saw-damage etch and a low

  17. Sample pretreatment for the determination of metal impurities in silicon wafer

    International Nuclear Information System (INIS)

    Chung, H. Y.; Kim, Y. H.; Yoo, H. D.; Lee, S. H.

    1999-01-01

    The analytical results obtained by microwave digestion and acid digestion methods for sample pretreatment to determine metal impurities in silicon wafer by inductively coupled plasma--mass spectrometry(ICP-MS) were compared. In order to decompose the silicon wafer, a mixed solution of HNO 3 and HF was added to the sample and the metal elements were determined after removing the silicon matrix by evaporating silicon in the form of Si-F. The recovery percentages of Ni, Cr and Fe were found to be 95∼106% for both microwave digestion and acid digestion methods. The recovery percentage of Cu obtained by the acid digestion method was higher than that obtained by the microwave digestion method. For Zn, however, the microwave digestion method gave better result than the acid digestion method. Fe was added to a silicon wafer using a spin coater. The concentration of Fe in this sample was determined by ICP-MS, and the same results were obtained in the two pretreatment methods

  18. Silicon Wafer Fabrication and Microchannel for Cooling System in ALICE ITS

    CERN Document Server

    Pasuwan, Patrawan

    2013-01-01

    My summer student project covered details of the upgrade of Inner Tracking System (ITS) of the ALICE detector. The tasks are divided in two parts. First was on silicon wafer dicing technology and its resistivity under the supervision of Petra Riedler. Next was on silicon wafer microfabrication and cooling system in microchannel under the supervision of Andrea Francescon. ITS upgrade was proposed for better detection performance and reduction of budget. Detectors in the ITS are composed of monolithic silicon pixel chips. The thickness of the chips was proposed to be 50 μm so that particles that pass through them do not lose too much momentum. Working with very thin chips requires suitable dicing technology. Sum- mary of dicing technology is proposed for the most suitable dicing technique. Properties of the chip can be denoted by observing its resistivity. Literature reviews on surface resistivity profile measurement is represented for consideration. Cooling system is very important for the detector. Fluid t...

  19. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    1Silicon Technology Unit (UDTS), 02 Bd Frantz Fanon, BP. 140, Alger-7 Merveilles, Algiers, Algeria. 2Houari Boumediene University of Science and Technology (USTHB), Bab Ezzouar, Algiers, Algeria. 3SSN-Research Centre, Rajiv ... ally, for solar cells metallization a standard screen print- ing process is applied. Initially ...

  20. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    ... Messaoud1 B Palahouane1 N Benrekaa2. Silicon Technology Unit (UDTS), 02 Bd Frantz Fanon, BP. 140, Alger-7 Merveilles, Algiers, Algeria; Houari Boumediene University of Science and Technology (USTHB), Bab Ezzouar, Algiers, Algeria; SSN-Research Centre, Rajiv Gandhi Salai (OMR), Kalavakkam 603 110, India ...

  1. Fabrication of silicon condenser microphones using single wafer technology

    NARCIS (Netherlands)

    Scheeper, P.R.; van der Donk, A.G.H.; Olthuis, Wouter; Bergveld, Piet

    1992-01-01

    A condenser microphone design that can be fabricated using the sacrificial layer technique is proposed and tested. The microphone backplate is a 1-¿m plasma-enhanced chemical-vapor-deposited (PECVD) silicon nitride film with a high density of acoustic holes (120-525 holes/mm2), covered with a thin

  2. Silicon Alignment Pins: An Easy Way to Realize a Wafer-To-Wafer Alignment

    Science.gov (United States)

    Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Thomas, Bertrand (Inventor); Lin, Robert H. (Inventor); Peralta, Alejandro (Inventor); Gill, John J. (Inventor); Lee, Choonsup (Inventor); Siles, Jose V. (Inventor); Toda, Risaku (Inventor); Chattopadhyay, Goutam (Inventor)

    2016-01-01

    A silicon alignment pin is used to align successive layers of components made in semiconductor chips and/or metallic components to make easier the assembly of devices having a layered structure. The pin is made as a compressible structure which can be squeezed to reduce its outer diameter, have one end fit into a corresponding alignment pocket or cavity defined in a layer of material to be assembled into a layered structure, and then allowed to expand to produce an interference fit with the cavity. The other end can then be inserted into a corresponding cavity defined in a surface of a second layer of material that mates with the first layer. The two layers are in registry when the pin is mated to both. Multiple layers can be assembled to create a multilayer structure. Examples of such devices are presented.

  3. The deposition of silicon nitride films under low pressure on wafers up to 200 mm

    Directory of Open Access Journals (Sweden)

    Nalivaiko O. Yu.

    2012-12-01

    Full Text Available The influence of silicon nitride deposition condition on parameters of the obtained films has been investigated. It has been found that the deposition rate of silicon nitride films decreases with deposition temperature decreasing, and at the same time the within wafer thickness uniformity improves. It allows performing the reproducible deposition of silicon nitride films with thickness of less than 10 nm. It has been found that in order to decrease the oxidation depth of silicon nitride, it is appropriate to carry out the oxidation under 850—900°C. The developed process of silicon nitride deposition made it possible to obtain reservoir capacitors with specific capacitance of 3,8—3,9 fF/μm2 at film thickness of 7,0 nm.

  4. An electron-multiplying "Micromegas" grid made in silicon wafer post-processing technology

    CERN Document Server

    Chefdeville, M; Giomataris, Ioanis; van der Graaf, H; Heijne, Erik H M; Van der Putten, S; Salm, C; Schmitz, J; Smits, S; Timmermans, J; Visschers, J L

    2006-01-01

    A technology for manufacturing an aluminium grid onto a silicon wafer has been developed. The grid is fixed parallel and precisely to the wafer (anode) surface at a distance of 50 \\mum by means of insulating pillars. When some 400 V are applied between the grid and (anode) wafer, gas multiplication occurs : primary electrons from the drift space above the grid enter the holes and cause electron avalanches in the high-field region between the grid and the anode. Production and operational characteristics of the device are described. With this newly developed technology, CMOS (pixel) readout chips can be covered with a gas multiplication grid. Such a chip forms, together with the grid, an integrated device which can be applied as readout in a wide field of gaseous detectors.

  5. Micro-spectroscopy on silicon wafers and solar cells

    Directory of Open Access Journals (Sweden)

    Gundel Paul

    2011-01-01

    Full Text Available Abstract Micro-Raman (μRS and micro-photoluminescence spectroscopy (μPLS are demonstrated as valuable characterization techniques for fundamental research on silicon as well as for technological issues in the photovoltaic production. We measure the quantitative carrier recombination lifetime and the doping density with submicron resolution by μPLS and μRS. μPLS utilizes the carrier diffusion from a point excitation source and μRS the hole density-dependent Fano resonances of the first order Raman peak. This is demonstrated on micro defects in multicrystalline silicon. In comparison with the stress measurement by μRS, these measurements reveal the influence of stress on the recombination activity of metal precipitates. This can be attributed to the strong stress dependence of the carrier mobility (piezoresistance of silicon. With the aim of evaluating technological process steps, Fano resonances in μRS measurements are analyzed for the determination of the doping density and the carrier lifetime in selective emitters, laser fired doping structures, and back surface fields, while μPLS can show the micron-sized damage induced by the respective processes.

  6. Grain-boundary type and distribution in silicon carbide coatings and wafers

    Science.gov (United States)

    Cancino-Trejo, Felix; López-Honorato, Eddie; Walker, Ross C.; Ferrer, Romelia Salomon

    2018-03-01

    Silicon carbide is the main diffusion barrier against metallic fission products in TRISO (tristructural isotropic) coated fuel particles. The explanation of the accelerated diffusion of silver through SiC has remained a challenge for more than four decades. Although, it is now well accepted that silver diffuse through SiC by grain boundary diffusion, little is known about the characteristics of the grain boundaries in SiC and how these change depending on the type of sample. In this work five different types (coatings and wafers) of SiC produced by chemical vapor deposition were characterized by electron backscatter diffraction (EBSD). The SiC in TRISO particles had a higher concentration of high angle grain boundaries (aprox. 70%) compared to SiC wafers, which ranged between 30 and 60%. Similarly, SiC wafers had a higher concentration of low angle grain boundaries ranging between 15 and 30%, whereas TRISO particles only reached values of around 7%. The same trend remained when comparing the content of coincidence site lattice (CSL) boundaries, since SiC wafers showed a concentration of more than 30%, whilst TRISO particles had contents of around 20%. In all samples the largest fractions of CSL boundaries (3 ≤ Σ ≤ 17) were the Σ3 boundaries. We show that there are important differences between the SiC in TRISO particles and SiC wafers which could explain some of the differences observed in diffusion experiments in the literature.

  7. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Science.gov (United States)

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  8. Atomic force and confocal microscopy for the study of cortical cells cultured on silicon wafers.

    Science.gov (United States)

    Ma, J; Cui, F Z; Liu, B F; Xu, Q Y

    2007-05-01

    The primary cortical cells were selected as a model to study the adherence and neural network development on chemically roughened silicon substrates without any coatings using confocal laser scanning microscopy (CLSM) and atomic force microscopy (AFM). The silicon substrates have a nano-range roughness (RMS) achieved by chemical etching using hydrofluoric (HF) acid. After 7 days of culturing, the neurons were observed to connect together and form dense neural networks. Furthermore, AFM results revealed that some porous structures at a few micrometer range existed between the neuron cells and the silicon substrates. It is suggested that the porous structures are made of extracellular matrix (ECM) components and play an important role in the neuronal adhesion and neurite outgrowth on the inert silicon wafers.

  9. Sheet resistivity of silicon wafers implanted with a high current machine

    International Nuclear Information System (INIS)

    Steeples, K.

    1985-01-01

    Silicon wafers, as used in the integrated circuits and semiconductor device industry, have been implanted with all the common dopants using Eaton Corporation's commercially available 'NV' series of high current implanters. Most detailed studies of the implanted wafers have focused on using arsenic and boron as dopants since the transport of these dopants in silicon has been found to be more compatible with the trend towards shrinking device dimensions. Four point probe measurements have been taken on implanted wafers with subsequent annealing to indicate the quality and effect of the implant. The variation of sheet resistance with dose and energy have been studied using a machine in standard condition over the range of 10 14 -10 16 ions/cm 2 and over an energy range of 5-180 keV for arsenic and boron implants into bare wafers and wafers with screen oxides. Dose control at low doses in the Eaton High Current Implanter has been studied over a range of 10 10 -10 13 ions/cm 2 using MOS devices and other measurements. Repeatability of the machines has been obtained by tracking the manufacture of over one hundred machines for nearly three years. With the use of an Eaton Standard Test Implant Procedure for each machine before shipment, it has been shown that the dose repeatability can be as good as 2% (including furnace and four point probe variations) for machine to machine. The repeatability within a single machine was found to be better than 0.5%. Arsenic ion beams have shown excellent independence of end station pressure, as may occur during photoresist outgassing or controlled gas leaks. Boron beams have a higher electron capture cross-section than other commonly used beams and require a dose control compensation for high end station pressure implants to give agreement with the low pressure regime. (orig./TW)

  10. High Efficiency, Low Cost Solar Cells Manufactured Using 'Silicon Ink' on Thin Crystalline Silicon Wafers

    Energy Technology Data Exchange (ETDEWEB)

    Antoniadis, H.

    2011-03-01

    Reported are the development and demonstration of a 17% efficient 25mm x 25mm crystalline Silicon solar cell and a 16% efficient 125mm x 125mm crystalline Silicon solar cell, both produced by Ink-jet printing Silicon Ink on a thin crystalline Silicon wafer. To achieve these objectives, processing approaches were developed to print the Silicon Ink in a predetermined pattern to form a high efficiency selective emitter, remove the solvents in the Silicon Ink and fuse the deposited particle Silicon films. Additionally, standard solar cell manufacturing equipment with slightly modified processes were used to complete the fabrication of the Silicon Ink high efficiency solar cells. Also reported are the development and demonstration of a 18.5% efficient 125mm x 125mm monocrystalline Silicon cell, and a 17% efficient 125mm x 125mm multicrystalline Silicon cell, by utilizing high throughput Ink-jet and screen printing technologies. To achieve these objectives, Innovalight developed new high throughput processing tools to print and fuse both p and n type particle Silicon Inks in a predetermined pat-tern applied either on the front or the back of the cell. Additionally, a customized Ink-jet and screen printing systems, coupled with customized substrate handling solution, customized printing algorithms, and a customized ink drying process, in combination with a purchased turn-key line, were used to complete the high efficiency solar cells. This development work delivered a process capable of high volume producing 18.5% efficient crystalline Silicon solar cells and enabled the Innovalight to commercialize its technology by the summer of 2010.

  11. Fabrication of through-wafer 3D microfluidics in silicon carbide using femtosecond laser

    Science.gov (United States)

    Huang, Yinggang; Wu, Xiudong; Liu, Hewei; Jiang, Hongrui

    2017-06-01

    We demonstrate a prototype through-wafer microfluidic structure in bulk silicon carbide (SiC) fabricated by femtosecond laser micromachining. The effects of laser fluence and scanning speed on the laser-affected zone are also investigated. Furthermore, the wettability of the laser-affected surface for the target liquid, mineral oil, is examined. Microchannels of various cross-sectional shapes are fabricated by the femtosecond laser and their effects on the liquid flow are simulated and compared. This fabrication approach offers a fast and efficient route to implement SiC-based through-wafer micro-structures, which are not able to be realized using other methods such as chemical etching. The flexibility of manufacturing 3D structures based on this fabrication method enables more complex structures as well. Smooth liquid flow in the microchannels of the bulk SiC substrate is presented. The work shown here paves a new way for various applications such as reliable microfluidic systems in a high-temperature, high radioactivity, and corrosive environment, and could be combined with SiC wafer-to-wafer bonding to realize a plethora of novel microelectromechanical (MEMS) structures.

  12. Crack Detection in Single-Crystalline Silicon Wafer Using Laser Generated Lamb Wave

    Directory of Open Access Journals (Sweden)

    Min-Kyoo Song

    2013-01-01

    Full Text Available In the semiconductor industry, with increasing requirements for high performance, high capacity, high reliability, and compact components, the crack has been one of the most critical issues in accordance with the growing requirement of the wafer-thinning in recent years. Previous researchers presented the crack detection on the silicon wafers with the air-coupled ultrasonic method successfully. However, the high impedance mismatching will be the problem in the industrial field. In this paper, in order to detect the crack, we propose a laser generated Lamb wave method which is not only noncontact, but also reliable for the measurement. The laser-ultrasonic generator and the laser-interferometer are used as a transmitter and a receiver, respectively. We firstly verified the identification of S0 and A0 lamb wave modes and then conducted the crack detection under the thermoelastic regime. The experimental results showed that S0 and A0 modes of lamb wave were clearly generated and detected, and in the case of the crack detection, the estimated crack size by 6 dB drop method was almost equal to the actual crack size. So, the proposed method is expected to make it possible to detect the crack in the silicon wafer in the industrial fields.

  13. Geometrical Deviation and Residual Strain in Novel Silicon-on-Aluminium-Nitride Bonded Wafers

    Science.gov (United States)

    Men, Chuan-Ling; Xu, Zheng; Wu, Yan-Jun; An, Zheng-Hua; Xie, Xin-Yun; Lin, Cheng-Lu

    2002-11-01

    Aluminium nitride (AlN), with much higher thermal conductivity, is considered to be an excellent alternative to the SiO2 layer in traditional silicon-on-insulator (SOI) materials. The silicon-on-aluminium-nitride (SOAN) structure was fabricated by the smart-cut process to alleviate the self-heating effects for traditional SOI. The convergent beam Kikuchi line diffraction pattern results show that some rotational misalignment exists when two wafers are bonded, which is about 3°. The high-resolution x-ray diffraction result indicates that, before annealing at high temperature, the residual lattice strain in the top silicon layer is tensile. After annealing at 1100°C for an hour, the strain in the top Si decreases greatly and reverses from tensile to slightly compressive as a result of viscous flow of AlN.

  14. The influence of silicon wafer thickness on characteristics of multijunction solar cells with vertical p—n-junctions

    Directory of Open Access Journals (Sweden)

    Gnilenko A. B.

    2012-02-01

    Full Text Available A multijunction silicon solar cell with vertical p–n junctions consisted of four serial n+–p–p+-structures was simulated using Silvaco TCAD software package. The dependence of solar cell characteristics on the silicon wafer thickness is investigated for a wide range of values.

  15. Magnetic structure of cross-shaped permalloy arrays embedded in silicon wafers

    International Nuclear Information System (INIS)

    Machida, Kenji; Tezuka, Tomoyuki; Yamamoto, Takahiro; Ishibashi, Takayuki; Morishita, Yoshitaka; Koukitu, Akinori; Sato, Katsuaki

    2005-01-01

    This paper describes the observed magnetic structure and the micromagnetic simulation of cross-shaped, permalloy (Ni 80 Fe 20 ) arrays embedded in silicon wafers. The nano-scale-width, cross-shaped patterns were fabricated using the damascene technique, electron beam lithography, and chemical mechanical polishing. The magnetic poles were observed as two pairs of bright and dark spots at the ends of the crossed-bars using a magnetic force microscope. The force gradient distributions were simulated based on micromagnetic calculations and tip's stray field calculations using the integral equation method. This process of calculation successfully explains the appearance of the poles and complicated spin structure at the crossing region

  16. Dislocation sources and slip band nucleation from indents on silicon wafers

    International Nuclear Information System (INIS)

    Wittge, J.; Danilewsky, A.N.; Allen, D.

    2010-01-01

    The nucleation of dislocations at controlled indents in silicon during rapid thermal annealing has been studied by in situ X-ray diffraction imaging (topography). Concentric loops extending over pairs of inclined {111} planes were formed, the velocities of the inclined and parallel segments being almost equal. Following loss of the screw segment from the wafer, the velocity of the inclined segments almost doubled, owing to removal of the line tension of the screw segments. The loops acted as obstacles to slip band propagation. (orig.)

  17. Culture of neural cells on silicon wafers with nano-scale surface topograph.

    Science.gov (United States)

    Fan, Y W; Cui, F Z; Hou, S P; Xu, Q Y; Chen, L N; Lee, I-S

    2002-10-15

    The adherence and viability of central neural cells (substantia nigra) on a thin layer of SiO(2) on Si wafers with different surface roughness were investigated. Variable roughness of the Si wafer surface was achieved by etching. The nano-scale surface topography was evaluated by atomic force microscopy. The adherence and subsequent viability of the cells on the wafer were examined by scanning electron microscopy (SEM) and fluorescence immunostaining of tyrosine hydroxylase (TH). It is found that the surface roughness significantly affected cell adhesion and viability. Cells survived for over 5 days with normal morphology and expressed neuronal TH when grown on surfaces with an average roughness (Ra) ranging from 20 to 50 nm. However, cell adherence was adversely affected when surfaces with Ra less than 10 nm and rough surfaces with Ra above 70 nm were used as the substrate. Such a simple preparation procedure may provide a suitable interface surface for silicon-based devices and neurones or other living tissues.

  18. Analysis of Processing Mechanism in Stealth Dicing of Ultra Thin Silicon Wafer

    Science.gov (United States)

    Ohmura, Etsuji; Kumagai, Masayoshi; Nakano, Makoto; Kuno, Koji; Fukumitsu, Kenshi; Morita, Hideki

    In this study, “stealth dicing” (SD) was applied to ultra thin wafers 50 μm in thickness. A coupling problem composed of focused laser propagation in single crystal silicon, along with laser absorption, temperature rise and heat conduction was analyzed by considering the temperature dependence of the absorption coefficient. When the depth of the focal plane is too shallow, the laser is also absorbed at the surface as the thermal shock wave reaches the surface. As a result, not only is an internal modified layer generated but ablation occurs at the surface as well. When the laser is focused at the surface, strong ablation occurs. Ablation at the surface is unfavorable because of the debris pollution and thermal effect on the device domain. It was concluded that there is a suitable depth for the focal plane so that the thermal shock wave propagates inside the wafer only. The optimum irradiating conditions such as pulse energy, pulse width, spot radius, and depth of focal plane can be estimated theoretically also for ultra thin wafer.

  19. Detection of trace contamination of copper on a silicon wafer with TXRF

    International Nuclear Information System (INIS)

    Yamada, T.; Matsuo, M.; Kohno, H.; Mori, Y.

    2000-01-01

    The element copper on silicon wafers is one of the most important metals to be detected among the contamination in semiconductor industries. When W-Lβ 1 (9.67 keV) line is used for the excitation in TXRF instrument and when Si(Li) is used as its detector, an escape peak appears at 7.93 keV which is close to the energy of Cu-Kα line(8.04 keV). When the concentration of copper is lower than 10 10 atoms/cm 2 , accurate quantitative analysis is difficult because of the overlapping of the peaks. When Au-Lβ 1 line(11.44 keV) is used for the excitation, the escape peak appears at 9.70 keV which is far enough from the energy of Cu-Ka line. We prepared silicon wafers intentionally contaminated with copper in a low concentration range of 10 8 to 10 10 atoms/cm 2 and measured them with a TXRF instrument having Au-Lβ 1 line for excitation. The contaminated samples were made with IAP method and their Cu concentrations were calibrated with VPD-AAS method (recovery solution: 2 % HF + 2 % H 2 O 2 ). A figure shows the correlation between the results with TXRF and those with AAS. The horizontal axis is the value of concentration decided by AAS and the vertical axis is the intensity of Cu-Kα line measured with the TXRF. Six wafers of different concentration were used and five points on each wafer including the center were measured with TXRF. Five points at each concentration in the figure correspond to the results measured on one wafer. Intensities of Cu-Kα line are weak in these low concentration ranges but the background of them are also very small (less than 0.05 cps). Therefore the peak of Cu-Kα line can be distinguished from the background. It can be said that a calibration curve can be drawn to the middle range of 10 9 atoms/cm 2 . The same samples were measured with another TXRF instrument having W-Lβ 1 line for excitation. It was difficult to draw a calibration curve in this case. We will present both results taken with Au-Lβ 1 line and with W-Lβ 1 line. (author)

  20. Kerfless epitaxial silicon wafers with 7 ms carrier lifetimes and a wide lift-off process window

    Science.gov (United States)

    Gemmel, Catherin; Hensen, Jan; David, Lasse; Kajari-Schröder, Sarah; Brendel, Rolf

    2018-04-01

    Silicon wafers contribute significantly to the photovoltaic module cost. Kerfless silicon wafers that grow epitaxially on porous silicon (PSI) and are subsequently detached from the growth substrate are a promising lower cost drop-in replacement for standard Czochralski (Cz) wafers. However, a wide technological processing window appears to be a challenge for this process. This holds in particularly for the etching current density of the separation layer that leads to lift-off failures if it is too large or too low. Here we present kerfless PSI wafers of high electronic quality that we fabricate on weakly reorganized porous Si with etch current densities varying in a wide process window from 110 to 150 mA/cm2. We are able to detach all 17 out of 17 epitaxial wafers. All wafers exhibit charge carrier lifetimes in the range of 1.9 to 4.3 ms at an injection level of 1015 cm-3 without additional high-temperature treatment. We find even higher lifetimes in the range of 4.6 to 7.0 ms after applying phosphorous gettering. These results indicate that a weak reorganization of the porous layer can be beneficial for a large lift-off process window while still allowing for high carrier lifetimes.

  1. Formation of cross-cutting structures with different porosity on thick silicon wafers

    Directory of Open Access Journals (Sweden)

    Vera A. Yuzova

    2017-06-01

    The second type pass-through structures include a macroporous silicon layer with a thickness of 250 μm which interlock in the depth of the silicon wafer to form a cavity with a size of 4–8 μm. For the formation of the second type structures we only used the first one of the abovementioned stages, the etching time being longer, i.e. 210 min. All the etching procedures were carried out in a cooling chamber at 5 °C. The developed technology will provided for easier and more reliable formation of the monolithic structures of membrane-electrode assembly micro fuel cells.

  2. N-type high-performance multicrystalline and mono-like silicon wafers with lifetimes above 2 ms

    Science.gov (United States)

    Pheng Phang, Sieu; Cheong Sio, Hang; Yang, Chia-Fu; Lan, Chung-Wen; Yang, Yu-Min; Wen-Huai Yu, Andy; Sung-Lin Hsu, Bruce; Wen-Ching Hsu, Chuck; Macdonald, Daniel

    2017-08-01

    Combined with advanced crystal growth technology and reduced dislocation densities, the higher tolerance to metal contamination of n-type silicon makes n-type cast-grown silicon a potential option for low cost high quality substrates for solar cells. Using a combination of photoconductance based lifetime testing and photoluminescence imaging, we have investigated the carrier lifetime in wafers from the bottom, middle, and top parts of a n-type high-performance multicrystalline (HPM) silicon ingot, and wafers from n-type mono-like silicon ingots after each high temperature solar cell processes, including after boron diffusion, phosphorus diffusion, and hydrogenation. Although boron diffusion leads to a degradation of the sample lifetime, phosphorus diffusion and hydrogenation is effective at recovering the lifetime in the intra-grain region and at the grain boundaries respectively. Quasi-steady-state photoconductance (QSSPC) measurements show that the arithmetic average lifetime of HPM silicon wafers and mono-like silicon wafers can reach up to 1.8 and 3.3 ms respectively for a process sequence including a boron diffusion, with corresponding implied open circuit voltage of about 720 mV. If the boron diffusion can be avoided, average lifetimes up to 3.0 and 6.6 ms can be achieved respectively, highlighting the excellent potential of n-type cast-grown materials.

  3. Real-time direct and diffraction X-ray imaging of irregular silicon wafer breakage

    Directory of Open Access Journals (Sweden)

    Alexander Rack

    2016-03-01

    Full Text Available Fracture and breakage of single crystals, particularly of silicon wafers, are multi-scale problems: the crack tip starts propagating on an atomic scale with the breaking of chemical bonds, forms crack fronts through the crystal on the micrometre scale and ends macroscopically in catastrophic wafer shattering. Total wafer breakage is a severe problem for the semiconductor industry, not only during handling but also during temperature treatments, leading to million-dollar costs per annum in a device production line. Knowledge of the relevant dynamics governing perfect cleavage along the {111} or {110} faces, and of the deflection into higher indexed {hkl} faces of higher energy, is scarce due to the high velocity of the process. Imaging techniques are commonly limited to depicting only the state of a wafer before the crack and in the final state. This paper presents, for the first time, in situ high-speed crack propagation under thermal stress, imaged simultaneously in direct transmission and diffraction X-ray imaging. It shows how the propagating crack tip and the related strain field can be tracked in the phase-contrast and diffracted images, respectively. Movies with a time resolution of microseconds per frame reveal that the strain and crack tip do not propagate continuously or at a constant speed. Jumps in the crack tip position indicate pinning of the crack tip for about 1–2 ms followed by jumps faster than 2–6 m s−1, leading to a macroscopically observed average velocity of 0.028–0.055 m s−1. The presented results also give a proof of concept that the described X-ray technique is compatible with studying ultra-fast cracks up to the speed of sound.

  4. Study on chemical mechanical polishing of silicon wafer with megasonic vibration assisted.

    Science.gov (United States)

    Zhai, Ke; He, Qing; Li, Liang; Ren, Yi

    2017-09-01

    Chemical mechanical polishing (CMP) is the primary method to realize the global planarization of silicon wafer. In order to improve this process, a novel method which combined megasonic vibration to assist chemical mechanical polishing (MA-CMP) is developed in this paper. A matching layer structure of polishing head was calculated and designed. Silicon wafers are polished by megasonic assisted chemical mechanical polishing and traditional chemical mechanical polishing respectively, both coarse polishing and precision polishing experiments were carried out. With the use of megasonic vibration, the surface roughness values Ra reduced from 22.260nm to 17.835nm in coarse polishing, and the material removal rate increased by approximately 15-25% for megasonic assisted chemical mechanical polishing relative to traditional chemical mechanical polishing. Average Surface roughness values Ra reduced from 0.509nm to 0.387nm in precision polishing. The results show that megasonic assisted chemical mechanical polishing is a feasible method to improve polishing efficiency and surface quality. The material removal and finishing mechanisms of megasonic vibration assisted polishing are investigated too. Copyright © 2017 Elsevier B.V. All rights reserved.

  5. Silicon crystals: Process for manufacturing wafer-like silicon crystals with a columnar structure

    Science.gov (United States)

    Authier, B.

    1978-01-01

    Wafer-like crystals suitable for making solar cells are formed by pouring molten Si containing suitable dopants into a mold of the desired shape and allowing it to solidify in a temperature gradient, whereby the large surface of the melt in contact with the mold is kept at less than 200 D and the free surface is kept at a temperature of 200-1000 D higher, but below the melting point of Si. The mold can also be made in the form of a slit, whereby the 2 sides of the mold are kept at different temperatures. A mold was milled in the surface of a cylindrical graphite block 200 mm in diameter. The granite block was induction heated and the bottom of the mold was cooled by means of a water-cooled Cu plate, so that the surface of the mold in contact with one of the largest surfaces of the melt was held at approximately 800 D. The free surface of the melt was subjected to thermal radiation from a graphite plate located 2 mm from the surface and heated to 1500 D. The Si crystal formed after slow cooling to room temperature had a columnar structure and was cut with a diamond saw into wafers approximately 500 mm thick. Solar cells prepared from these wafers had efficiencies of 10 to 11%.

  6. Theoretical analysis of improved efficiency of silicon-wafer solar cells with textured nanotriangular grating structure

    Science.gov (United States)

    Zhang, Yaoju; Zheng, Jun; Zhao, Xuesong; Ruan, Xiukai; Cui, Guihua; Zhu, Haiyong; Dai, Yuxing

    2018-03-01

    A practical model of crystalline silicon-wafer solar cells is proposed in order to enhance the light absorption and improve the conversion efficiency of silicon solar cells. In the model, the front surface of the silicon photovoltaic film is designed to be a textured-triangular-grating (TTG) structure, and the ITO contact film and the antireflection coating (ARC) of glass are coated on the TTG surface of silicon solar cells. The optical absorption spectrum of solar cells are simulated by applying the finite difference time domain method. Electrical parameters of the solar cells are calculated using two models with and without carrier loss. The effect of structure parameters on the performance of the TTG cell is discussed in detail. It is found that the thickness (tg) of the ARC, period (p) of grating, and base angle (θ) of triangle have a crucial influence on the conversion efficiency. The optimal structure of the TTG cell is designed. The TTG solar cell can produce higher efficiency in a wide range of solar incident angle and the average efficiency of the optimal TTG cell over 7:30-16:30 time of day is 8% higher than that of the optimal plane solar cell. In addition, the study shows that the bulk recombination of carriers has an influence on the conversion efficiency of the cell, the conversion efficiency of the actual solar cell with carrier recombination is reduced by 20.0% of the ideal cell without carrier recombination.

  7. Corrugation Architecture Enabled Ultraflexible Wafer-Scale High-Efficiency Monocrystalline Silicon Solar Cell

    KAUST Repository

    Bahabry, Rabab R.

    2018-01-02

    Advanced classes of modern application require new generation of versatile solar cells showcasing extreme mechanical resilience, large-scale, low cost, and excellent power conversion efficiency. Conventional crystalline silicon-based solar cells offer one of the most highly efficient power sources, but a key challenge remains to attain mechanical resilience while preserving electrical performance. A complementary metal oxide semiconductor-based integration strategy where corrugation architecture enables ultraflexible and low-cost solar cell modules from bulk monocrystalline large-scale (127 × 127 cm) silicon solar wafers with a 17% power conversion efficiency. This periodic corrugated array benefits from an interchangeable solar cell segmentation scheme which preserves the active silicon thickness of 240 μm and achieves flexibility via interdigitated back contacts. These cells can reversibly withstand high mechanical stress and can be deformed to zigzag and bifacial modules. These corrugation silicon-based solar cells offer ultraflexibility with high stability over 1000 bending cycles including convex and concave bending to broaden the application spectrum. Finally, the smallest bending radius of curvature lower than 140 μm of the back contacts is shown that carries the solar cells segments.

  8. Bulk lifetime characterization of corona charged silicon wafers with high resistivity by means of microwave detected photoconductivity

    Science.gov (United States)

    Engst, C. R.; Rommel, M.; Bscheid, C.; Eisele, I.; Kutter, C.

    2017-12-01

    Minority carrier lifetime (lifetime) measurements are performed on corona-charged silicon wafers by means of Microwave Detected Photoconductivity (MDP). The corona charge is deposited on the front and back sides of oxidized wafers in order to adjust accumulation conditions. Once accumulation is established, interface recombination is suppressed and bulk lifetimes are obtained. Neither contacts nor non-CMOS compatible preparation techniques are required in order to achieve accumulation conditions, which makes the method ideally suited for inline characterization. The novel approach, termed ChargedMDP (CMDP), is used to investigate neutron transmutation doped (NTD) float zone silicon with resistivities ranging from 6.0 to 8.2 kΩ cm. The bulk properties of 150 mm NTD wafers are analyzed in detail by performing measurements of the carrier lifetime and the steady-state photoconductivity at various injection levels. The results are compared with MDP measurements of uncharged wafers as well as to the established charged microwave detected Photoconductance Decay (charge-PCD) method. Besides analyzing whole wafers, CMDP measurements are performed on oxide test-structures on a patterned wafer. Finally, the oxide properties are characterized by means of charge-PCD as well as capacitance-voltage measurements. With CMDP, average bulk lifetimes up to 33.1 ms are measured, whereby significant variations are observed among wafers, which are produced out of the same ingot but oxidized in different furnaces. The observed lifetime variations are assumed to be caused by contaminations, which are introduced during the oxidation process. The results obtained by CMDP were neither accessible by means of conventional MDP measurements of uncharged wafers nor with the established charge-PCD method.

  9. Investigation of the heating behavior of carbide-bonded graphene coated silicon wafer used for hot embossing

    Science.gov (United States)

    Yang, Gao; Li, Lihua; Lee, Wing Bun; Ng, Man Cheung; Chan, Chang Yuen

    2018-03-01

    A recently developed carbide-bonded graphene (CBG) coated silicon wafer was found to be an effective micro-patterned mold material for implementing rapid heating in hot embossing processes owing to its superior electrical and thermal conductivity, in addition to excellent mechanical properties. To facilitate the achievement of precision temperature control in the hot embossing, the heating behavior of a CBG coated silicon wafer sample was experimentally investigated. First, two groups of controlled experiments were conducted for quantitatively evaluating the influence of the main factors such as the vacuum pressure and gaseous environment (vacuum versus nitrogen) on its heating performance. The electrical and thermal responses of this sample under a voltage of 60 V were then intensively analyzed, and revealed that it had somewhat semi-conducting properties. Further, we compared its thermal profiles under different settings of the input voltage and current limiting threshold. Moreover, the strong temperature dependence of electrical resistance for this material was observed and determined. Ultimately, the surface temperature of CBG coated silicon wafer could be as high as 1300 ℃, but surprisingly the graphene coating did not detach from the substrate under such an elevated temperature due to its strong thermal coupling with the silicon wafer.

  10. High sensitivity detection and characterization of the chemical state of trace element contamination on silicon wafers

    CERN Document Server

    Pianetta, Piero A; Baur, K; Brennan, S; Homma, T; Kubo, N

    2003-01-01

    Increasing the speed and complexity of semiconductor integrated circuits requires advanced processes that put extreme constraints on the level of metal contamination allowed on the surfaces of silicon wafers. Such contamination degrades the performance of the ultrathin SiO sub 2 gate dielectrics that form the heart of the individual transistors. Ultimately, reliability and yield are reduced to levels that must be improved before new processes can be put into production. It should be noted that much of this metal contamination occurs during the wet chemical etching and rinsing steps required for the manufacture of integrated circuits and industry is actively developing new processes that have already brought the metal contamination to levels beyond the measurement capabilities of conventional analytical techniques. The measurement of these extremely low contamination levels has required the use of synchrotron radiation total reflection X-ray fluorescence (SR-TXRF) where sensitivities 100 times better than conv...

  11. Sidewall patterning—a new wafer-scale method for accurate patterning of vertical silicon structures

    Science.gov (United States)

    Westerik, P. J.; Vijselaar, W. J. C.; Berenschot, J. W.; Tas, N. R.; Huskens, J.; Gardeniers, J. G. E.

    2018-01-01

    For the definition of wafer scale micro- and nanostructures, in-plane geometry is usually controlled by optical lithography. However, options for precisely patterning structures in the out-of-plane direction are much more limited. In this paper we present a versatile self-aligned technique that allows for reproducible sub-micrometer resolution local modification along vertical silicon sidewalls. Instead of optical lithography, this method makes smart use of inclined ion beam etching to selectively etch the top parts of structures, and controlled retraction of a conformal layer to define a hard mask in the vertical direction. The top, bottom or middle part of a structure could be selectively exposed, and it was shown that these exposed regions can, for example, be selectively covered with a catalyst, doped, or structured further.

  12. Effect of PECVD SiNx/SiOy Nx –Si interface property on surface passivation of silicon wafer

    International Nuclear Information System (INIS)

    Jia Xiao-Jie; Zhou Chun-Lan; Zhou Su; Wang Wen-Jing; Zhu Jun-Jie

    2016-01-01

    It is studied in this paper that the electrical characteristics of the interface between SiO y N x /SiN x stack and silicon wafer affect silicon surface passivation. The effects of precursor flow ratio and deposition temperature of the SiO y N x layer on interface parameters, such as interface state density Di t and fixed charge Q f , and the surface passivation quality of silicon are observed. Capacitance–voltage measurements reveal that inserting a thin SiO y N x layer between the SiN x and the silicon wafer can suppress Q f in the film and D it at the interface. The positive Q f and D it and a high surface recombination velocity in stacks are observed to increase with the introduced oxygen and minimal hydrogen in the SiO y N x film increasing. Prepared by deposition at a low temperature and a low ratio of N 2 O/SiH 4 flow rate, the SiO y N x /SiN x stacks result in a low effective surface recombination velocity (S eff ) of 6 cm/s on a p-type 1 Ω·cm–5 Ω·cm FZ silicon wafer. The positive relationship between S eff and D it suggests that the saturation of the interface defect is the main passivation mechanism although the field-effect passivation provided by the fixed charges also make a contribution to it. (paper)

  13. Dehydration and dehydroxylation of C-S-H phases synthesized on silicon wafers

    Science.gov (United States)

    Giraudo, Nicolas; Bergdolt, Samuel; Laye, Fabrice; Krolla, Peter; Lahann, Joerg; Thissen, Peter

    2018-03-01

    In this work, the synthesis of specific ultrathin Calcium-Silicate-Hydrate (C-S-H) phases on silicon wafers and their transformation into C-S phases is achieved. Specific mineral phases are identified, and the synthesis is successful controlled. Samples are investigated by means of Fourier Transform Infrared (FTIR) spectroscopy and X-ray Diffraction (XRD) and the results are analyzed based on first-principles calculations. When C-S-H phases are transformed into C-S phases, only a few reflexes are detected on XRD, and the coherent scattering domains decrease with the increment of the temperature and time of exposure. This behavior is explained by the Ca/Si changes, which are identified by changes in the FTIR spectra. A thermodynamic analysis is performed with the help of first-principles calculations to underline the influence of the calcium-to-silicon (Ca/Si) ratio in the process of dehydroxylation. To increase the Ca/Si ratio water is partially substituted by methanol at the synthesis. This is observed in the FTIR spectra and is confirmed by lower temperatures of dehydroxylation. The catalytic nature of calcium towards the dehydroxylation is confirmed. The core of this work lies in the preparation of a model, which perfection makes possible to model reactivity, stability and mechanical properties using first-principles calculations, and is the starting point for the synthesis of many others.

  14. Tailoring the graphene/silicon carbide interface for monolithic wafer-scale electronics.

    Science.gov (United States)

    Hertel, S; Waldmann, D; Jobst, J; Albert, A; Albrecht, M; Reshanov, S; Schöner, A; Krieger, M; Weber, H B

    2012-07-17

    Graphene is an outstanding electronic material, predicted to have a role in post-silicon electronics. However, owing to the absence of an electronic bandgap, graphene switching devices with high on/off ratio are still lacking. Here in the search for a comprehensive concept for wafer-scale graphene electronics, we present a monolithic transistor that uses the entire material system epitaxial graphene on silicon carbide (0001). This system consists of the graphene layer with its vanishing energy gap, the underlying semiconductor and their common interface. The graphene/semiconductor interfaces are tailor-made for ohmic as well as for Schottky contacts side-by-side on the same chip. We demonstrate normally on and normally off operation of a single transistor with on/off ratios exceeding 10(4) and no damping at megahertz frequencies. In its simplest realization, the fabrication process requires only one lithography step to build transistors, diodes, resistors and eventually integrated circuits without the need of metallic interconnects.

  15. Reliability assessment of ultra-thin HfO2 films deposited on silicon wafer

    International Nuclear Information System (INIS)

    Fu, Wei-En; Chang, Chia-Wei; Chang, Yong-Qing; Yao, Chih-Kai; Liao, Jiunn-Der

    2012-01-01

    Highlights: ► Nano-mechanical properties on annealed ultra-thin HfO 2 film are studied. ► By AFM analysis, hardness of the crystallized HfO 2 film significantly increases. ► By nano-indention, the film hardness increases with less contact stiffness. ► Quality assessment on the annealed ultra-thin films can thus be achieved. - Abstract: Ultra-thin hafnium dioxide (HfO 2 ) is used to replace silicon dioxide to meet the required transistor feature size in advanced semiconductor industry. The process integration compatibility and long-term reliability for the transistors depend on the mechanical performance of ultra-thin HfO 2 films. The criteria of reliability including wear resistance, thermal fatigue, and stress-driven failure rely on film adhesion significantly. The adhesion and variations in mechanical properties induced by thermal annealing of the ultra-thin HfO 2 films deposited on silicon wafers (HfO 2 /SiO 2 /Si) are not fully understood. In this work, the mechanical properties of an atomic layer deposited HfO 2 (nominal thickness ≈10 nm) on a silicon wafer were characterized by the diamond-coated tip of an atomic force microscope and compared with those of annealed samples. The results indicate that the annealing process leads to the formation of crystallized HfO 2 phases for the atomic layer deposited HfO 2 . The HfSi x O y complex formed at the interface between HfO 2 and SiO 2 /Si, where the thermal diffusion of Hf, Si, and O atoms occurred. The annealing process increases the surface hardness of crystallized HfO 2 film and therefore the resistance to nano-scratches. In addition, the annealing process significantly decreases the harmonic contact stiffness (or thereafter eliminate the stress at the interface) and increases the nano-hardness, as measured by vertically sensitive nano-indentation. Quality assessments on as-deposited and annealed HfO 2 films can be thereafter used to estimate the mechanical properties and adhesion of ultra-thin HfO 2

  16. Wafer scale formation of monocrystalline silicon-based Mie resonators via silicon-on-insulator dewetting.

    Science.gov (United States)

    Abbarchi, Marco; Naffouti, Meher; Vial, Benjamin; Benkouider, Abdelmalek; Lermusiaux, Laurent; Favre, Luc; Ronda, Antoine; Bidault, Sébastien; Berbezier, Isabelle; Bonod, Nicolas

    2014-11-25

    Subwavelength-sized dielectric Mie resonators have recently emerged as a promising photonic platform, as they combine the advantages of dielectric microstructures and metallic nanoparticles supporting surface plasmon polaritons. Here, we report the capabilities of a dewetting-based process, independent of the sample size, to fabricate Si-based resonators over large scales starting from commercial silicon-on-insulator (SOI) substrates. Spontaneous dewetting is shown to allow the production of monocrystalline Mie-resonators that feature two resonant modes in the visible spectrum, as observed in confocal scattering spectroscopy. Homogeneous scattering responses and improved spatial ordering of the Si-based resonators are observed when dewetting is assisted by electron beam lithography. Finally, exploiting different thermal agglomeration regimes, we highlight the versatility of this technique, which, when assisted by focused ion beam nanopatterning, produces monocrystalline nanocrystals with ad hoc size, position, and organization in complex multimers.

  17. Characterization of a vertically movable gate field effect transistor using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Song, In-Hyouk; Forfang, William B D; Cole, Bryan; Hee You, Byoung

    2014-01-01

    The vertically movable gate field effect transistor (VMGFET) is a FET-based sensing element, whose gate moves in a vertical direction over the channel. A VMGFET gate covers the region between source and drain. A 1 μm thick air layer separates the gate and the substrate of the VMGFET. A novel fabrication process to form a VMGFET using a silicon-on-insulator (SOI) wafer provides minimal internal stress of the gate structure. The enhancement-type n-channel VMGFET is fabricated with the threshold voltage of 2.32 V in steady state. A non-inverting amplifier is designed and integrated on a printable circuit board (PCB) to characterize device sensitivity and mechanical properties. The VMGFET is mechanically coupled to a speaker membrane to apply mechanical vibration. The oscillated drain current of FET are monitored and sampled with NI LabVIEW. The frequency of the output signal correlates with that of the input stimulus. The resonance frequency of the fabricated VMGFET is measured to be 1.11 kHz. The device sensitivity linearly increases by 0.106 mV/g Hz in the range of 150 Hz and 1 kHz. (paper)

  18. Simple, Fast, and Cost-Effective Fabrication of Wafer-Scale Nanohole Arrays on Silicon for Antireflection

    Directory of Open Access Journals (Sweden)

    Di Di

    2014-01-01

    Full Text Available A simple, fast, and cost-effective method was developed in this paper for the high-throughput fabrication of nanohole arrays on silicon (Si, which is utilized for antireflection. Wafer-scale polystyrene (PS monolayer colloidal crystal was developed as templates by spin-coating method. Metallic shadow mask was prepared by lifting off the oxygen etched PS beads from the deposited chromium film. Nanohole arrays were fabricated by Si dry etching. A series of nanohole arrays were fabricated with the similar diameter but with different depth. It is found that the maximum depth of the Si-hole was determined by the diameter of the Cr-mask. The antireflection ability of these Si-hole arrays was investigated. The results show that the reflection decreases with the depth of the Si-hole. The deepest Si-hole arrays show the best antireflection ability (reflection 600 nm, which was about 28 percent of the nonpatterned silicon wafer’s reflection. The proposed method has the potential for high-throughput fabrication of patterned Si wafer, and the low reflectivity allows the application of these wafers in crystalline silicon solar cells.

  19. Low-temperature wafer direct bonding of silicon and quartz glass by a two-step wet chemical surface cleaning

    Science.gov (United States)

    Wang, Chenxi; Xu, Jikai; Zeng, Xiaorun; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2018-02-01

    We demonstrate a facile bonding process for combining silicon and quartz glass wafers by a two-step wet chemical surface cleaning. After a post-annealing at 200 °C, strong bonding interfaces with no defects or microcracks were obtained. On the basis of the detailed surface and bonding interface characterizations, the bonding mechanism was explored and discussed. The amino groups terminated on the cleaned surfaces might contribute to the bonding strength enhancement during the annealing. This cost-effective bonding process has great potentials for silicon- and glass-based heterogeneous integrations without requiring a vacuum system.

  20. Design and fabrication of a planar patch-clamp substrate using a silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Zhang Zhenlong; Liu Xiangyang; Mao Yanli

    2009-01-01

    The planar patch-clamp technique has been applied to high throughput screening in drug discovery. The key feature of this technique is the fabrication of a planar patch-clamp substrate using appropriate materials. In this study, a planar patch-clamp substrate was designed and fabricated using a silicon-on-insulator (SOI) wafer. The access resistance and capacitance of SOI-based planar patch-clamp substrates are smaller than those of bulk silicon-based planar substrates, which will reduce the distributed RC noise.

  1. Iridium-coated micropore x-ray optics using dry etching of a silicon wafer and atomic layer deposition.

    Science.gov (United States)

    Ogawa, Tomohiro; Ezoe, Yuichiro; Moriyama, Teppei; Mitsuishi, Ikuyuki; Kakiuchi, Takuya; Ohashi, Takaya; Mitsuda, Kazuhisa; Putkonen, Matti

    2013-08-20

    To enhance x-ray reflectivity of silicon micropore optics using dry etching of silicon (111) wafers, iridium coating is tested by use of atomic layer deposition. An iridium layer is successfully formed on sidewalls of tiny micropores with a pore width of 20 μm and depth of 300 μm. The film thickness is ∼20  nm. An enhanced x-ray reflectivity compared to that of silicon is confirmed at Ti Kα 4.51 keV, for what we believe to be the first time, with this type of optics. Some discrepancies from a theoretical reflectivity curve of iridium-coated silicon are noticed at small incident angles rms is consistent with atomic force microscope measurements of the sidewalls.

  2. Structure and resistivity of bismuth nanobelts in situ synthesized on silicon wafer through an ethanol-thermal method

    International Nuclear Information System (INIS)

    Gao Zheng; Qin Haiming; Yan Tao; Liu Hong; Wang Jiyang

    2011-01-01

    Bismuth nanobelts in situ grown on a silicon wafer were synthesized through an ethanol-thermal method without any capping agent. The structure of the bismuth belt–silicon composite nanostructure was characterized by scanning electron microscope, energy-dispersive X-ray spectroscopy, and high resolution transmission electron microscope. The nanobelt is a multilayered structure 100–800 nm in width and over 50 μm in length. One layer has a thickness of about 50 nm. A unique sword-like nanostructure is observed as the initial structure of the nanobelts. From these observations, a possible growth mechanism of the nanobelt is proposed. Current–voltage property measurements indicate that the resistivity of the nanobelts is slightly larger than that of the bulk bismuth material. - Graphical Abstract: TEM images, EDS, and electron diffraction pattern of bismuth nanobelts. Highlights: ► Bismuth nanobelts in situ grown on silicon wafer were achieved. ► Special bismuth–silicon nanostructure. ► Potential application in sensitive magnetic sensor and other electronic devices.

  3. High efficiency heterojunction solar cells on n-type kerfless mono crystalline silicon wafers by epitaxial growth

    Science.gov (United States)

    Kobayashi, Eiji; Watabe, Yoshimi; Hao, Ruiying; Ravi, T. S.

    2015-06-01

    We present a heterojunction (HJ) solar cell on n-type epitaxially grown kerfless crystalline-silicon (c-Si) with a conversion efficiency of 22.5%. The total cell area is 243.4 cm2. The cell has a short-circuit current density of 38.6 mA/cm2, an open-circuit voltage of 735 mV, and a fill factor of 0.791. The key advantages and technological tasks of epitaxial wafers for HJ solar cells are discussed, in comparison with conventional n-type Czockralski c-Si wafers. The combination of HJ and kerfless technology can lead to high conversion efficiency with a potential at low cost.

  4. Fabrication of a microstrip patch antenna integrated in low-resistance silicon wafer using a BCB dielectric

    Science.gov (United States)

    Tianxi, Wang; Mei, Han; Gaowei, Xu; Le, Luo

    2013-10-01

    This paper demonstrates a technique for microstrip patch antenna fabrication using a benzocyclobutene (BCB) dielectric. The most distinctive feature of this method is that the antenna is integrated on a low-resistance silicon wafer, and is fully compatible with the microwave multi-chip module packaging process. Low-permittivity dielectric BCB with excellent thermal and mechanical stability is employed to enhance the performance of the antenna. The as-fabricated antenna is characterized, and the experimental results show that the antenna resonates at 14.9 GHz with a 1.67% impedance bandwidth.

  5. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  6. Terahertz transmission properties of silicon wafers using continuous-wave terahertz spectroscopy

    International Nuclear Information System (INIS)

    Kim, Chihoon; Ahn, Jae Sung; Eom, Joo Beom; Ji, Taeksoo

    2017-01-01

    We present the spectral properties of Si wafers using continuous-wave terahertz (CW-THz) spectroscopy. By using a tunable laser source and a fixed distributed-feedback laser diode (DFB-LD), a stably tunable beat source for CW-THz spectroscopy system can be implemented. THz radiation is generated in the frequency range of 100 GHz–800 GHz by photomixing in a photoconductive antenna. We also measured CW-THz waveforms by changing the beat frequency and confirmed repeatability through repeated measurement. We calculated the peaks of the THz frequency by taking fast Fourier transforms (FFTs) of measured THz waveforms. The feasibility of CW-THz spectroscopy is demonstrated by the THz spectra of Si wafers with different resistivities, mobilities, and carrier concentrations. The results show that Si wafers with a lower resistivity absorb more THz waves. Thus, we expect our CW-THz system to have the advantage of being able to perform fast non-destructive analysis. (paper)

  7. Exploration of surface hydrophilic properties on AISI 304 stainless steel and silicon wafer against aging after atmospheric pressure plasma treatment

    Science.gov (United States)

    Chuang, Shang-I.; Duh, Jenq-Gong

    2014-11-01

    The aim of this work is to seek the enhanced surface hydrophilic properties on AISI 304 stainless steel and silicon wafer after atmospheric pressure plasma treatment using a specifically designed atmospheric pressure plasma jet. The aging tendency of surface hydrophilic property under air is highlighted. It is concluded that both of the silicon wafer and stainless steel treated with plasma generated from supply gas of argon 15 slm mixed with oxygen 40 sccm shows a better tendency on remaining high water contact angle as compared to that with pure argon and nitrogen addition. Additional peaks of O I (777, 844 nm), O II (408 nm) are detected by optical emission spectroscope indicating the presence of the oxygen radicals and ionic species, which interact with surfaces and thus contribute to low water contact angle (WCA) surfaces. Moreover, the result acquired from X-ray photoelectron spectroscopy (XPS) indicates that the increase in the oxygen-related bonding exhibits a better contribution on remaining high surface energy over a period of time.

  8. Vapor phase treatment–total reflection X-ray fluorescence for trace elemental analysis of silicon wafer surface

    Energy Technology Data Exchange (ETDEWEB)

    Takahara, Hikari, E-mail: hikari@rigaku.co.jp [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Mori, Yoshihiro [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Shibata, Harumi [SUMCO Corporation, Seavance North, 1-2-1 Shibaura, Minato-ku, Tokyo 105-8634 (Japan); Shimazaki, Ayako [Toshiba Corporation, 8, Shinsugita-cho, Isogo-ku, Yokohama 235-8522 (Japan); Shabani, Mohammad B. [Mitsubishi Material Corporation, 1-297, Kitabukuro-cho, Omiya-ku, Saitama 330-8508 (Japan); Yamagami, Motoyuki [Rigaku Corp., 14-8 Akaoji-cho, Takatsuki, Osaka 569-1146 (Japan); Yabumoto, Norikuni [Analysis Atelier Co., 4-36-4, Yoyogi, Shibuya-ku, Tokyo 151-0053 (Japan); Nishihagi, Kazuo [Horiba Ltd., 2 Miyanohigashi, Kisshoin, Minami-ku, Kyoto 601-8510 (Japan); Gohshi, Yohichi [Tsukuba University, 1-1-1, Tennodai, Tsukuba, Ibaraki 305-8571 (Japan)

    2013-12-01

    Vapor phase treatment (VPT) was under investigation by the International Organization for Standardization/Technical Committee 201/Working Group 2 (ISO/TC201/WG2) to improve the detection limit of total reflection X-ray fluorescence spectroscopy (TXRF) for trace metal analysis of silicon wafers. Round robin test results have confirmed that TXRF intensity increased by VPT for intentional contamination with 5 × 10{sup 9} and 5 × 10{sup 10} atoms/cm{sup 2} Fe and Ni. The magnification of intensity enhancement varied greatly (1.2–4.7 in VPT factor) among the participating laboratories, though reproducible results could be obtained for average of mapping measurement. SEM observation results showed that various features, sizes, and surface densities of particles formed on the wafer after VPT. The particle morphology seems to have some impact on the VPT efficiency. High resolution SEM observation revealed that a certain number of dots with SiO{sub 2}, silicate and/or carbon gathered to form a particle and heavy metals, Ni and Fe in this study were segregated on it. The amount and shape of the residue should be important to control VPT factor. - Highlights: • This paper presents a summary of study results of VPT–TXRF using ISO/TC201/WG2. • Our goal is to analyze the trace metallic contamination on silicon wafer with concentrations below 1 × 10{sup 10} atoms/cm{sup 2}. • The efficiency and mechanism of VPT are discussed under several round robin tests and systematic studies.

  9. Investigation of transparent conductive electrodes for application in heterojunction silicon wafer solar cells

    Science.gov (United States)

    Huang, Mei

    This thesis focuses on the fabrication, characterisation and analysis of high-quality transparent conductive electrodes for application in heterojunction silicon wafer solar cells. Indium tin oxide (ITO) is the material of interest, which is investigated by both the pulsed direct current (PDC) and the unbalanced radio frequency (URF) magnetron sputtering methods. The influences of deposition parameters and annealing conditions on the performance of the ITO films are studied and the optimal deposition conditions are established for both systems. The results show that ITO films with low crystallinity have degraded electrical properties after annealing at 200°C. The degradation of ITO film properties is associated with the excess scattering centres formed along with the newly crystallised regions, which significantly deteriorate the electron mobility. The relationships between the deposition conditions and the material properties are investigated by X-ray photoelectron spectroscopy (XPS). It is shown that the major electron donors in amorphous ITO films are oxygen vacancies. With the increase of the film crystallinity, the doping efficiency of Sn atoms improves. The substitutional Sn atoms contribute additional free electrons in ITO films, which improve the film's conductivity. It is also shown that the darkening of ITO films observed in PDC sputtering is due to the existence of second phase Sn3O4, which severely darken the ITO sample when it is excessively present in the surface layer and in the bulk of the film. The hydrogen gas used in the URF sputtering method is shown to effectively lower the concentration of free electrons. Benefiting from the reduced electron scattering by ionized dopant atoms, the ITO films deposited with hydrogen gas maintain a high electron mobility. Besides the ITO material properties, the sputter induced damages are also studied. It is shown that in PDC sputtering the ion bombardment damage is the primary damage contributor, while plasma

  10. Analysis and optimization of silicon wafers wire sawing; Analyse et optimisation du procede de decoupe de plaques de silicium

    Energy Technology Data Exchange (ETDEWEB)

    Rouault de Coligny, P.

    2002-09-15

    This work has been done at the Centre de Mise en Forme des Materiaux and supported by the Agence de l'Environnement et la Maitrise de l'Energie and Photowatt International SA. It concerns one of the stages of the production of photovoltaic solar cells: the cutting of multi-crystalline silicon wafers by wire sawing. A review of the literature combined with the observation of rough wafers shows that wire sawing involves 3-body abrasion and that material removal is achieved in a ductile manner and forms micro-chips. Therefore, the depth of indentation which is necessary for the ductile-fragile transition as shown by the review of the literature is not reached. The resulting abrasion can be described thanks to Archard's Law. The subsurface damage is 2.5 {mu}m deep. A thermal study has shown that the temperature of the cutting is no higher than about 50 deg. C and that it depends on how much heat can be evacuated by the wire. Analyzing the flaws of the wafers has enabled us to identify their origins and to find solutions. The study of the wire's wear has proved that its diameter can be reduced only if the wire is drawn continuously. Energy can be saved at various stages, the surface of the wafers can be improved, these three arguments plead for the suppression of the back and forth. A tribological device has been set up which allows us to study the abrasion of silicon in the same conditions as in the wire sawing. A mechanical model linking the bending of the wire to the parameters collected during the wire sawing process can predict how high the wire web will be in the transitional and permanent regimes, the contact pressure and the wire wear. Material removal by plane strain scratch tests has been numerically simulated. The orders of magnitude of wear coefficients are identical to those deduced from tribological simulations and to those measured on the saws. This approach has opened new prospects which will improve the process by optimizing the

  11. Room-temperature direct bonding of silicon and quartz glass wafers

    Science.gov (United States)

    Wang, Chenxi; Wang, Yuan; Tian, Yanhong; Wang, Chunqing; Suga, Tadatomo

    2017-05-01

    We demonstrate a facile bonding method for combining Si/Si, Si/quartz, and quartz/quartz wafers at room temperature (˜25 °C) using a one-step O2/CF4/H2O plasma treatment. The bonding strengths were significantly improved by adding a small amount of CF4 into the oxygen plasma, such that reliable and tight bonding was obtained after storage in ambient air for 24 h, even without employing heat. Moreover, by introducing water vapor during O2/CF4 plasma treatment, uniform wafer bonding was spontaneously achieved without applying an external force. The fluorinated surface asperities appear to be softened more easily by the interfacial water stress corrosion, enabling reliable bonding at room temperature. Additionally, adding an optimized amount of water vapor to the O2/CF4 plasma increases sufficiently the amount of hydroxyl groups without eliminating the CF4 effect. The additional water adsorbed on the surface may help to close the gap between the bonded wafers, resulting in better bonding efficiency.

  12. Development of an on-line isotope dilution laser ablation inductively coupled plasma mass spectrometry (LA-ICP-MS) method for determination of boron in silicon wafers.

    Science.gov (United States)

    Yang, Chao-Kai; Chi, Po-Hsiang; Lin, Yong-Chine; Sun, Yuh-Chang; Yang, Mo-Hsiung

    2010-01-15

    A method has been developed based on an on-line isotope dilution technique couple with laser ablation/inductively coupled plasma mass spectrometry (LA-ICP-MS), for the determination of boron in p-type silicon wafers. The laser-ablated sample aerosol was mixed on-line with an enriched boron aerosol supplied continuously using a conventional nebulization system. Upon mixing the two aerosol streams, the isotope ratio of boron changed rapidly and was then recorded by the ICP-MS system for subsequent quantification based on the isotope dilution principle. As an on-line solid analysis method, this system accurately quantifies boron concentrations in silicon wafers without the need for an internal or external solid reference standard material. Using this on-line isotope dilution technique, the limit of detection for boron in silicon wafers is 2.8x10(15)atomscm(-3). The analytical results obtained using this on-line methodology agree well with those obtained using wet chemical digestion methods for the analysis of p-type silicon wafers containing boron concentrations ranging from 1.0x10(16) to 9.6x10(18)atomscm(-3).

  13. Characterization of deliberately nickel-doped silicon wafers and solar cells. [microstructure, electrical properties, and energy conversion efficiency

    Science.gov (United States)

    Salama, A. M.

    1980-01-01

    Microstructural and electrical evaluation tests were performed on nickel-doped p-type silicon wafers before and after solar cell fabrication. The concentration levels of nickel in silicon were 5 x 10 to the 14th power, 4 x 10 to the 15th power, and 8 x 10 to the 15th power atoms/cu cm. It was found that nickel precipitated out during the growth process in all three ingots. Clumps of precipitates, some of which exhibited star shape, were present at different depths. If the clumps are distributed at depths approximately 20 micron apart and if they are larger than 10 micron in diameter, degradation occurs in solar cell electrical properties and cell conversion efficiency. The larger the size of the precipitate clump, the greater the degradation in solar cell efficiency. A large grain boundary around the cell effective area acted as a gettering center for the precipitates and impurities and caused improvement in solar cell efficiency. Details of the evaluation test results are given.

  14. Fabrication of a 77 GHz Rotman Lens on a High Resistivity Silicon Wafer Using Lift-Off Process

    Directory of Open Access Journals (Sweden)

    Ali Attaran

    2014-01-01

    Full Text Available Fabrication of a high resistivity silicon based microstrip Rotman lens using a lift-off process has been presented. The lens features 3 beam ports, 5 array ports, 16 dummy ports, and beam steering angles of ±10 degrees. The lens was fabricated on a 200 μm thick high resistivity silicon wafer and has a footprint area of 19.7 mm × 15.6 mm. The lens was tested as an integral part of a 77 GHz radar where a tunable X band source along with an 8 times multiplier was used as the RF source and the resulting millimeter wave signal centered at 77 GHz was radiated through a lens-antenna combination. A horn antenna with a downconverter harmonic mixer was used to receive the radiated signal and display the received signal in an Advantest R3271A spectrum analyzer. The superimposed transmit and receive signal in the spectrum analyzer showed the proper radar operation confirming the Rotman lens design.

  15. Synchrotron Radiation Total Reflection X-ray Fluorescence Spectroscopy for Microcontamination Analysis on Silicon Wafer Surfaces

    Energy Technology Data Exchange (ETDEWEB)

    Takaura, Norikatsu

    1997-10-01

    As dimensions in state-of-the-art CMOS devices shrink to less than 0.1 pm, even low levels of impurities on wafer surfaces can cause device degradation. Conventionally, metal contamination on wafer surfaces is measured using Total Reflection X-Ray Fluorescence Spectroscopy (TXRF). However, commercially available TXRF systems do not have the necessary sensitivity for measuring the lower levels of contamination required to develop new CMOS technologies. In an attempt to improve the sensitivity of TXRF, this research investigates Synchrotron Radiation TXRF (SR TXRF). The advantages of SR TXRF over conventional TXRF are higher incident photon flux, energy tunability, and linear polarization. We made use of these advantages to develop an optimized SR TXRF system at the Stanford Synchrotron Radiation Laboratory (SSRL). The results of measurements show that the Minimum Detection Limits (MDLs) of SR TXRF for 3-d transition metals are typically at a level-of 3x10{sup 8} atoms/cm{sup 2}, which is better than conventional TXRF by about a factor of 20. However, to use our SR TXRF system for practical applications, it was necessary to modify a commercially available Si (Li) detector which generates parasitic fluorescence signals. With the modified detector, we could achieve true MDLs of 3x10{sup 8} atoms/cm{sup 2} for 3-d transition metals. In addition, the analysis of Al on Si wafers is described. Al analysis is difficult because strong Si signals overlap the Al signals. In this work, the Si signals are greatly reduced by tuning the incident beam energy below the Si K edge. The results of our measurements show that the sensitivity for Al is limited by x-ray Raman scattering. Furthermore, we show the results of theoretical modeling of SR TXRF backgrounds consisting of the bremsstrahlung generated by photoelectrons, Compton scattering, and Raman scattering. To model these backgrounds, we extended conventional theoretical models by taking into account several aspects particular

  16. Damage-free polishing of monocrystalline silicon wafers without chemical additives

    International Nuclear Information System (INIS)

    Biddut, A.Q.; Zhang, L.C.; Ali, Y.M.; Liu, Z.

    2008-01-01

    This investigation explores the possibility and identifies the mechanism of damage-free polishing of monocrystalline silicon without chemical additives. Using high resolution electron microscopy and contact mechanics, the study concludes that a damage-free polishing process without chemicals is feasible. All forms of damages, such as amorphous Si, dislocations and plane shifting, can be eliminated by avoiding the initiation of the β-tin phase of silicon during polishing. When using 50 nm abrasives, the nominal pressure to achieve damage-free polishing is 20 kPa

  17. Three-dimensional numerical analysis of hybrid heterojunction silicon wafer solar cells with heterojunction rear point contacts

    Directory of Open Access Journals (Sweden)

    Zhi Peng Ling

    2015-07-01

    Full Text Available This paper presents a three-dimensional numerical analysis of homojunction/heterojunction hybrid silicon wafer solar cells, featuring front-side full-area diffused homojunction contacts and rear-side heterojunction point contacts. Their device performance is compared with conventional full-area heterojunction solar cells as well as conventional diffused solar cells featuring locally diffused rear point contacts, for both front-emitter and rear-emitter configurations. A consistent set of simulation input parameters is obtained by calibrating the simulation program with intensity dependent lifetime measurements of the passivated regions and the contact regions of the various types of solar cells. We show that the best efficiency is obtained when a-Si:H is used for rear-side heterojunction point-contact formation. An optimization of the rear contact area fraction is required to balance between the gains in current and voltage and the loss in fill factor with shrinking rear contact area fraction. However, the corresponding optimal range for the rear-contact area fraction is found to be quite large (e.g. 20-60 % for hybrid front-emitter cells. Hybrid rear-emitter cells show a faster drop in the fill factor with decreasing rear contact area fraction compared to front-emitter cells, stemming from a higher series resistance contribution of the rear-side a-Si:H(p+ emitter compared to the rear-side a-Si:H(n+ back surface field layer. Overall, we show that hybrid silicon solar cells in a front-emitter configuration can outperform conventional heterojunction silicon solar cells as well as diffused solar cells with rear-side locally diffused point contacts.

  18. Precipitation in silicon wafers after high temperature preanneal studied by X-ray diffraction methods

    Czech Academy of Sciences Publication Activity Database

    Meduňa, M.; Růžička, J.; Caha, O.; Buršík, Jiří; Svoboda, Milan

    2012-01-01

    Roč. 407, č. 15 (2012), s. 3002-3005 ISSN 0921-4526 R&D Projects: GA ČR(CZ) GA202/09/1013 Institutional research plan: CEZ:AV0Z20410507 Keywords : silicon * interstitial oxygen * precipitation Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 1.327, year: 2012

  19. IC Compatible Wafer Level Fabrication of Silicon Nanowire Field Effect Transistors for Biosensing Applications

    NARCIS (Netherlands)

    Moh, T.S.Y.

    2013-01-01

    In biosensing, nano-devices such as Silicon Nanowire Field Effect Transistors (SiNW FETs) are promising components/sensors for ultra-high sensitive detection, especially when samples are low in concentration or a limited volume is available. Current processing of SiNW FETs often relies on expensive

  20. Control of grown-in defects and oxygen precipitates in silicon wafers with DZ-IG structure by ultrahigh-temperature rapid thermal oxidation

    Science.gov (United States)

    Maeda, Susumu; Sudo, Haruo; Okamura, Hideyuki; Nakamura, Kozo; Sueoka, Koji; Izunome, Koji

    2018-04-01

    A new control technique for achieving compatibility between crystal quality and gettering ability for heavy metal impurities was demonstrated for a nitrogen-doped Czochralski silicon wafer with a diameter of 300 mm via ultra-high temperature rapid thermal oxidation (UHT-RTO) processing. We have found that the DZ-IG structure with surface denuded zone and the wafer bulk with dense oxygen precipitates were formed by the control of vacancies in UHT-RTO process at temperature exceeding 1300 °C. It was also confirmed that most of the void defects were annihilated from the sub-surface of the wafer due to the interstitial Si atoms that were generated at the SiO2/Si interface. These results indicated that vacancies corresponded to dominant species, despite numerous interstitial silicon injections. We have explained these prominent features by the degree of super-saturation for the interstitial silicon due to oxidation and the precise thermal properties of the vacancy and interstitial silicon.

  1. Relaxation of vacancy depth profiles in silicon wafers: A low apparent diffusivity of vacancy species

    OpenAIRE

    Voronkov, Vladimir V.; Falster, Robert; Pichler, Peter

    2014-01-01

    Vacancy depth profiles in silicon wafersinstalled by Rapid Thermal Annealing and monitored by Pt diffusionshow, upon subsequent annealing at 975 or 950 °C, a peculiar evolution: the concentration profile goes down without any trace of vacancy out-diffusion. The estimated apparent diffusivity is less than 1E7 cm2/s at 975 °C. The monitored vacancy species is tentatively identified as a "slow vacancy" that was recently concluded to exist along with other (highly mobile) vacancy species.

  2. Neutron activation analysis of low-level element contents in silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Goerner, W. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Berger, A. [Bundesanstalt fuer Materialforschung und -pruefung, Berlin (Germany); Niese, S. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Koehler, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Matthes, M. [Verein fuer Kernverfahrenstechnik und Analytik Rossendorf e.V. (VKTA), Dresden (Germany); Gawlik, D. [Hahn-Meitner-Institut, Berlin (Germany)

    1997-03-01

    Semiconductor silicon is among the purest materials having ever been produced by modern technology. Thus, it is quite suitable as a primary reference material validating the correctness and the detection capabilities of developed analytical methods. Among them neutron activation analysis plays a competitive role. The U.S. National Institute of Science and Technology (NIST) has initiated and carried out an interlaboratory comparison in order to study the spread of analytical results worldwide evolved by several laboratories dealing with specimens of extreme purity. The outcome of the experiment was intended to review the capabilities of NAA as well as to differentiate between bulk and surface contamination. (orig./DG)

  3. Understanding the Fundamental Properties of Transfer-Free, Wafer-Level Graphene on Silicon and its Potential for Micro- and Nanodevices

    Science.gov (United States)

    2015-06-18

    quality, uniform bilayer graphene directly was realized on silicon wafers, at temperatures compatible with conventional semiconductor processing. The...conventional semiconductor processing. We demonstrated the highest doping ever reported for graphene (~ 1015 at cm-2, in the same order of magnitude as the...compatible with conventional semiconductor processing. The sheet resistance of the graphene is about 25 ohms/square, unprecedented for Distribution A

  4. Analysis and wafer-level design of a high-order silicon vibration isolator for resonating MEMS devices

    International Nuclear Information System (INIS)

    Yoon, Sang Won; Lee, Sangwoo; Najafi, Khalil; Perkins, Noel C

    2011-01-01

    This paper presents the analysis and preliminary design, fabrication, and measurement for mechanical vibration-isolation platforms especially designed for resonating MEMS devices including gyroscopes. Important parameters for designing isolation platforms are specified and the first platform (in designs with cascaded multiple platforms) is crucial for improving vibration-isolation performance and minimizing side-effects on integrated gyroscopes. This isolation platform, made from a thick silicon wafer substrate for an environment-resistant MEMS package, incorporates the functionalities of a previous design including vacuum packaging and thermal resistance with no additional resources. This platform consists of platform mass, isolation beams, vertical feedthroughs, and bonding pads. Two isolation platform designs follow from two isolation beam designs: lateral clamped–clamped beams and vertical torsion beams. The beams function simultaneously as mechanical springs and electrical interconnects. The vibration-isolation platform can yield a multi-dimensional, high-order mechanical low pass filter. The isolation platform possesses eight interconnects within a 12.2 × 12.2 mm 2 footprint. The contact resistance ranges from 4–11 Ω depending on the beam design. Vibration measurements using a laser-Doppler vibrometer demonstrate that the lateral vibration-isolation platform suppresses external vibration having frequencies exceeding 2.1 kHz.

  5. Silicon Wafer-Based Platinum Microelectrode Array Biosensor for Near Real-Time Measurement of Glutamate in Vivo

    Directory of Open Access Journals (Sweden)

    Nigel T. Maidment

    2008-08-01

    Full Text Available Using Micro-Electro-Mechanical-Systems (MEMS technologies, we have developed silicon wafer-based platinum microelectrode arrays (MEAs modified with glutamate oxidase (GluOx for electroenzymatic detection of glutamate in vivo. These MEAs were designed to have optimal spatial resolution for in vivo recordings. Selective detection of glutamate in the presence of the electroactive interferents, dopamine and ascorbic acid, was attained by deposition of polypyrrole and Nafion. The sensors responded to glutamate with a limit of detection under 1μM and a sub-1-second response time in solution. In addition to extensive in vitro characterization, the utility of these MEA glutamate biosensors was also established in vivo. In the anesthetized rat, these MEA glutamate biosensors were used for detection of cortically-evoked glutamate release in the ventral striatum. The MEA biosensors also were applied to the detection of stress-induced glutamate release in the dorsal striatum of the freely-moving rat.

  6. Towards wafer-size graphene layers by atmospheric pressure graphitization of silicon carbide.

    Science.gov (United States)

    Emtsev, Konstantin V; Bostwick, Aaron; Horn, Karsten; Jobst, Johannes; Kellogg, Gary L; Ley, Lothar; McChesney, Jessica L; Ohta, Taisuke; Reshanov, Sergey A; Röhrl, Jonas; Rotenberg, Eli; Schmid, Andreas K; Waldmann, Daniel; Weber, Heiko B; Seyller, Thomas

    2009-03-01

    Graphene, a single monolayer of graphite, has recently attracted considerable interest owing to its novel magneto-transport properties, high carrier mobility and ballistic transport up to room temperature. It has the potential for technological applications as a successor of silicon in the post Moore's law era, as a single-molecule gas sensor, in spintronics, in quantum computing or as a terahertz oscillator. For such applications, uniform ordered growth of graphene on an insulating substrate is necessary. The growth of graphene on insulating silicon carbide (SiC) surfaces by high-temperature annealing in vacuum was previously proposed to open a route for large-scale production of graphene-based devices. However, vacuum decomposition of SiC yields graphene layers with small grains (30-200 nm; refs 14-16). Here, we show that the ex situ graphitization of Si-terminated SiC(0001) in an argon atmosphere of about 1 bar produces monolayer graphene films with much larger domain sizes than previously attainable. Raman spectroscopy and Hall measurements confirm the improved quality of the films thus obtained. High electronic mobilities were found, which reach mu=2,000 cm (2) V(-1) s(-1) at T=27 K. The new growth process introduced here establishes a method for the synthesis of graphene films on a technologically viable basis.

  7. Trap profiling at nanocavity bands in silicon wafers by means of capacitance-voltage measurements

    CERN Document Server

    Auriac, N

    2002-01-01

    Nanocavities are formed by He sup + -and H sup + -ion implantation in silicon single crystals, at the projected range R sub p , after post-implantation annealing. The present paper deals with the characterization of deep trap levels associated with such defects. P-type silicon single crystals were implanted using He sup + -and H sup + -ion beams, at an energy of 250 keV and to a dose of 3 x 10 sup 1 sup 6 cm sup - sup 2. Capacitance-voltage (C-V) profiling and deep-level transient spectroscopy (DLTS) techniques were used to determine the density profile and the energy levels of deep traps in the gap. In implanted and post-annealed samples a quasi-triangular profile of the space charge is revealed around R sub p by C-V profiling, and the space charge density reaches 10 sup 1 sup 6 cm sup - sup 3. DLTS suggests that trap levels are located at 0.4 eV above the valence band, with a maximum density around 10 sup 1 sup 5 cm sup - sup 3 at R sub p. The sign and distribution of the space charge for depletion in He su...

  8. Corporate array of micromachined dipoles on silicon wafer for 60 GHz communication systems

    KAUST Repository

    Sallam, M. O.

    2013-03-01

    In this paper, an antenna array operating at 60 GHz and realized on 0.675 mm thick silicon substrate is presented. The array is constructed using four micromachined half-wavelength dipoles fed by a corporate feeding network. Isolation between the antenna array and its feeding network is achieved via a ground plane. This arrangement leads to maximizing the broadside radiation with relatively high front-to-back ratio. Simulations have been carried out using both HFSS and CST, which showed very good agreement. Results reveal that the proposed antenna array has good radiation characteristics, where the directivity, gain, and radiation efficiency are around 10.5 dBi, 9.5 dBi, and 79%, respectively. © 2013 IEEE.

  9. Determination of ultra-trace contaminants on silicon wafer surfaces using TXRF. Present state of the art

    International Nuclear Information System (INIS)

    Pahlke, S.; Fabry, L.; Kotz, L.; Mantler, C.; Ehmann, T.

    2000-01-01

    Recently, TXRF became a standard, on-line inspection tool for controlling the cleanliness of polished Si wafers for semiconductor use now up to 300 diameter. Wafer makers strive for an all-over metallic cleanliness of 10 atoms x cm -2 . Therefore an analytical tools must cover LOD in a range 9 atoms x cm -2 or lower. The all-over cleanliness of the whole wafer surface can analyzed using VPD/TXRF. For this chemical wafer-pre-preparation under cleanroom conditions class 1 we have developed a full automatic 'Wafer Surface Preparation System' coupled with a new generation TXRF. We have also combined this system with other independent methods for Na, Al, anions and cations. Only the combination of automatic wafer handling systems, modem analytical tools, ultra-pure water, ULSI chemicals and special cleanroom conditions provides us a chance to achieve the present and the future demands for semiconductor industry. (author)

  10. New plant designs for aqueous etching and electroforming of wafers; Neues modulares Anlagenkonzept fuer nasschemische Aetzprozesse und die Wafergalvanoformung

    Energy Technology Data Exchange (ETDEWEB)

    Guttmann, Markus; Kaiser, Konradin; Muth, Stephanie [Karlsruher Institut fuer Technologie, Karlsruhe (Germany). Inst. fuer Mikrostrukturtechnik; Moritz, Hans [silicet AG, Lohfelden (Germany); Schmidt, Ralf; Zwanzig, Michael [Fraunhofer-Institut fuer Zuverlaessigkeit und Mikrointegration (IZM), Berlin (Germany); Hofmann, Lutz [TU Chemnitz (Germany). Zentrum fuer Mikrotechnologien; Schubert, Ina [Fraunhofer-Einrichtung fuer Elektronische Nanosysteme (ENAS), Chemnitz (Germany)

    2009-07-01

    In order to carry out a study of wafer patterning, equipment was developed for safe handling of silicon wafers from 2 to 8 inch diameters. The unit can be safely and relatively straightforwardly operated by personnel, using a wide range of etchants and electrochemical deposition processes. The design also allows the effects of electrolyte flowrate in the process chamber confronting the silicon wafer, to be assessed. These features were utilised to study copper and nickel electrodeposition to pattern the wafer surface. (orig.) [German] Zur Untersuchung der Strukturierung von Wafern wurde eine Prozesseinheit zur bruchsicheren Aufnahme von Siliziumwafern mit Durchmessern zwischen zwei und acht Zoll entwickelt. Die Einheit kann relativ einfach und mit hoher Sicherheit fuer die handhabenden Personen mit den unterschiedlichsten Medien zum Aetzen oder galvanotechnischen Aufbau betrieben werden. Die Anordnung ermoeglicht zudem die gezielte Beeinflussung der Stroemung im Prozessraum vor der Waferoberflaeche. Die Moeglichkeiten zur Untersuchung werden an der Nickel- und Kupferabscheidung zur Herstellung von Strukturen aufgezeigt. (orig.)

  11. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  12. Non-invasive thermal profiling of silicon wafer surface during RTP using acoustic and signal processing techniques

    Science.gov (United States)

    Syed, Ahmed Rashid

    Among the great physical challenges faced by the current front-end semiconductor equipment manufacturers is the accurate and repeatable surface temperature measurement of wafers during various fabrication steps. Close monitoring of temperature is essential in that it ensures desirable device characteristics to be reliably reproduced across various wafer lots. No where is the need to control temperature more pronounced than it is during Rapid Thermal Processing (RTP) which involves temperature ramp rates in excess of 200°C/s. This dissertation presents an elegant and practical approach to solve the wafer surface temperature estimation problem, in context of RTP, by deploying hardware that acquires the necessary data while preserving the integrity and purity of the wafer. In contrast to the widely used wafer-contacting (and hence contaminating) methods, such as bonded thermocouples, or environment sensitive schemes, such as light-pipes and infrared pyrometry, the proposed research explores the concept of utilizing Lamb (acoustic) waves to detect changes in wafer surface temperature, during RTP. Acoustic waves are transmitted to the wafer via an array of quartz rods that normally props the wafer inside an RTP chamber. These waves are generated using piezoelectric transducers affixed to the bases of the quartz rods. The group velocity of Lamb waves traversing the wafer surface undergoes a monotonic decrease with rise in wafer temperature. The correspondence of delay in phase of the received Lamb waves and the ambient temperature, along all direct paths between sending and receiving transducers, yields a psuedo real-time thermal image of the wafer. Although the custom built hardware-setup implements the above "proof-of-concept" scheme by transceiving acoustic signals at a single frequency, the real-world application will seek to enhance the data acquistion. rate (>1000 temperature measurements per seconds) by sending and receiving Lamb waves at multiple frequencies (by

  13. Stress and phase changes in a low-thermal-expansion Al-3at.%Ge alloy film on oxidized silicon wafers

    International Nuclear Information System (INIS)

    Tu, K.N.; Rodbell, K.P.; Herd, S.R.; Mikalsen, D.J.

    1993-01-01

    The alloy of Al-3at.%Ge has been found to have a low thermal expansion and contraction in the temperature range of room temperature to 400 C. The reason for the low thermal contraction (or expansion) is the precipitation (or dissolution) of Ge in the alloy. The Ge precipitates have a diamond structure in which each Ge atom occupies a much larger atomic volume than a Ge atom dissolved substitutionally in Al. The volume difference compensates for the effect of thermal expansion and contraction with changing temperature which in turn reduces the thermal stress due to thermal mismatch. The technique of wafer bending was used to determine the stress of the alloy film on oxidized silicon wafers upon thermal cycling; indeed, it is much lower than that of pure Al on identical wafers. The morphology of precipitation and dissolution of Ge in Al has been studied by transmission and scanning electron microscopy. It is found that the precipitation follows a discontinuous mode and occurs predominantly along grain boundaries. In dissolving the Ge precipitates into Al, voids are left behind because of the volume difference. It is proposed that this may explain the enhancement of nucleation of voids in the alloy film upon thermal cycling. (orig.)

  14. Linear self-assembly and grafting of gold nanorods into arrayed micrometer-long nanowires on a silicon wafer via a combined top-down/bottom-up approach.

    Science.gov (United States)

    Lestini, Elena; Andrei, Codrin; Zerulla, Dominic

    2018-01-01

    Macroscopically long wire-like arrangements of gold nanoparticles were obtained by controlled evaporation and partial coalescence of an aqueous colloidal solution of capped CTAB-Au nanorods onto a functionalised 3-mercaptopropyl trimethoxysilane (MPTMS) silicon substrate, using a removable, silicon wafer with a hydrophobic surface that serves as a "handrail" for the initial nanorods' linear self-assembly. The wire-like structures display a quasi-continuous pattern by thermal annealing of the gold nanorods when the solvent (i.e. water) is evaporated at temperatures rising from 20°C to 140°C. Formation of both single and self-replicating parallel 1D-superstructures consisting of two or even three wires is observed and explained under such conditions.

  15. The formation of an amorphous interface layer precedes the onset of the nucleation of an orderly carbon structure on a silicon wafer

    Science.gov (United States)

    Belay, Kalayu; Jackson, Jeremy; Johnson, Kevin

    2002-03-01

    A thin film was grown by plasma assisted chemical vapor deposition (PACVD) process on a heated silicon wafer substrate. The reactants in the process were 298pressure and substrate temperature were 40 Torr and 9000 C respectively. The silicon wafer was scratched with diamond dust to increase the rate of nucleation. Upon absorbing energy from microwave generated plasma the methane breaks down freeing the carbon atoms, which are deposited on the substrate. The system was run for ten hours. A seemingly uniform milky thin layer of film was formed on the substrate. Initial characterization using an X-ray diffractometer was unable to detect the presence of any orderly structure of carbon atoms forming diamond or graphite. This leads us to believe that an amorphous interlayer is formed before diamond or other diamond like structure is formed on the substrate. Results of additional investigations and interpretations will be reported. *This research was supported in part by a grant from NASA MURED to Florida A&M University.

  16. Sub-Micrometer Zeolite Films on Gold-Coated Silicon Wafers with Single-Crystal-Like Dielectric Constant and Elastic Modulus

    Energy Technology Data Exchange (ETDEWEB)

    Tiriolo, Raffaele [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Rangnekar, Neel [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Zhang, Han [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Shete, Meera [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Bai, Peng [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Nelson, John [Characterization Facility, University of Minnesota, 12 Shepherd Labs, 100 Union St. S.E. Minneapolis MN 55455 USA; Karapetrova, Evguenia [Surface Scattering and Microdiffraction, X-ray Science Division, Argonne National Laboratory, 9700 S. Cass Ave, Building 438-D002 Argonne IL 60439 USA; Macosko, Christopher W. [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA; Siepmann, Joern Ilja [Department of Chemistry and Chemistry Theory Center, University of Minnesota, 207 Pleasant St SE Minneapolis MN 55455 USA; Lamanna, Ernesto [Department of Health Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Lavano, Angelo [Department of Medical and Surgical Sciences, University Magna Graecia of Catanzaro, Viale Europa 88100 Catanzaro Italy; Tsapatsis, Michael [Department of Chemical Engineering and Materials Science, University of Minnesota, 421 Washington Ave SE Minneapolis MN 55455 USA

    2017-05-08

    A low-temperature synthesis coupled with mild activation produces zeolite films exhibiting low dielectric constant (low-k) matching the theoretically predicted and experimentally measured values for single crystals. This synthesis and activation method allows for the fabrication of a device consisting of a b-oriented film of the pure-silica zeolite MFI (silicalite-1) supported on a gold-coated silicon wafer. The zeolite seeds are assembled by a manual assembly process and subjected to optimized secondary growth conditions that do not cause corrosion of the gold underlayer, while strongly promoting in-plane growth. The traditional calcination process is replaced with a non-thermal photochemical activation to ensure preservation of an intact gold layer. The dielectric constant (k), obtained through measurement of electrical capacitance in a metal-insulator-metal configuration, highlights the ultralow k approximate to 1.7 of the synthetized films, which is among the lowest values reported for an MFI film. There is large improvement in elastic modulus of the film (E approximate to 54 GPa) over previous reports, potentially allowing for integration into silicon wafer processing technology.

  17. Through-Wafer Optical Interconnects For Multi-Wafer Wafer-Scale Integrated Architectures

    Science.gov (United States)

    Hornak, L. A.; Tewksbury, S. K.; Hatamian, M.; Ligtenberg, A.; Sugla, B.; Franzon, P.

    1986-12-01

    Hybrid mounting of optical components, combined perhaps with integrated optical waveguides and lenses on a large area silicon, wafer-scale integrated (WSI) electronic circuit provides one potential approach to combine advanced electronic and photonic functions. The desire to achieve a high degree of parallelism in multi-wafer WSI-based architectures has stimulated study of three-dimensional interconnect structures obtained by stacking wafer circuit boards and. providing interconnections vertically between wafers over the entire wafer area in addition to planar connections. While presently it is difficult for optical interconnects to compete with electrical interconnects in the wafer plane, it is appropriate to look at vertical optical interconnections between wafer planes since the corresponding conductive structures would be large in area and may impede system repairability. The ability to pass information optically between circuit planes without mechanical electrical contacts offers potential advantages for multi-wafer WSI or other dense three-dimensional architectures. However, while optical waveguides are readily fabricated in the plane of the wafer, waveguiding vertically through the wafer is difficult. If additional processing is required for waveguides or lenses, it should be compatible with standard VLSI processing. This paper presents one straightforward method of meeting this criterion. Using optical device technology operating at wavelengths beyond the ≍1.1μm Si absorption cutoff, low loss, through-wafer propagation between WSI circuit boards can be achieved over the distances of interest (≍1mm) with the interstitial Si wafers as part of the interconnect "free-space" transmission medium. The thickness of existing VLSI layers can be readily adjusted in featureless regions of the wafer to provide antireflection windows such that the transmittance can be raised to ≍77% for n-type and to ≍97% for p-type silicon. Optical interconnect source

  18. Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers

    Science.gov (United States)

    Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

    2015-12-01

    Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

  19. Silicon etching using only Oxygen at high temperature: An alternative approach to Si micro-machining on 150 mm Si wafers.

    Science.gov (United States)

    Chai, Jessica; Walker, Glenn; Wang, Li; Massoubre, David; Tan, Say Hwa; Chaik, Kien; Hold, Leonie; Iacopi, Alan

    2015-12-04

    Using a combination of low-pressure oxygen and high temperatures, isotropic and anisotropic silicon (Si) etch rates can be controlled up to ten micron per minute. By varying the process conditions, we show that the vertical-to-lateral etch rate ratio can be controlled from 1:1 isotropic etch to 1.8:1 anisotropic. This simple Si etching technique combines the main respective advantages of both wet and dry Si etching techniques such as fast Si etch rate, stiction-free, and high etch rate uniformity across a wafer. In addition, this alternative O2-based Si etching technique has additional advantages not commonly associated with dry etchants such as avoiding the use of halogens and has no toxic by-products, which improves safety and simplifies waste disposal. Furthermore, this process also exhibits very high selectivity (>1000:1) with conventional hard masks such as silicon carbide, silicon dioxide and silicon nitride, enabling deep Si etching. In these initial studies, etch rates as high as 9.2 μm/min could be achieved at 1150 °C. Empirical estimation for the calculation of the etch rate as a function of the feature size and oxygen flow rate are presented and used as proof of concepts.

  20. Robust Wafer-Level Thin-Film Encapsulation (Packaging) of Microstructures (MEMS) using Low Stress PECVD Silicon Carbide

    NARCIS (Netherlands)

    Rajaraman, V.; Pakula, L.S.; Pham, H.T.M.; Sarro, P.M.; French, P.J.

    2009-01-01

    This paper presents a new low-cost, CMOS-compatible and robust wafer-level encapsulation technique developed using a stress-optimised PECVD SiC as the capping and sealing material, imparting harsh environment capability. This technique has been applied for the fabrication and encapsulation of a wide

  1. Surface passivation at low temperature of p- and n-type silicon wafers using a double layer a-Si:H/SiNx:H

    International Nuclear Information System (INIS)

    Focsa, A.; Slaoui, A.; Charifi, H.; Stoquert, J.P.; Roques, S.

    2009-01-01

    Surface passivation of bare silicon or emitter region is of great importance towards high efficiency solar cells. Nowadays, this is usually accomplished by depositing an hydrogenated amorphous silicon nitride (a-SiNx:H) layer on n + p structures that serves also as an excellent antireflection layer. On the other hand, surface passivation of p-type silicon is better assured by an hydrogenated amorphous silicon (a-Si:H) layer but suffers from optical properties. In this paper, we reported the surface passivation of p-type and n-type silicon wafers by using an a-Si:H/SiNx:H double layer formed at low temperature (50-400 deg. C) with ECR-PECVD technique. We first investigated the optical properties (refraction index, reflectance, and absorbance) and structural properties by FTIR (bonds Si-H, N-H) of the deposited films. The hydrogen content in the layers was determined by elastic recoil detection analysis (ERDA). The passivation effect was monitored by measuring the minority carrier effective lifetime vs. different parameters such as deposition temperature and amorphous silicon layer thickness. We have found that a 10-15 nm a-Si film with an 86 nm thick SiN layer provides an optimum of the minority carriers' lifetime. It increases from an initial value of about 50-70 μs for a-Si:H to about 760 and 800 μs for a-Si:H/SiNx:H on Cz-pSi and FZ-nSi, respectively, at an injection level 2 x 10 15 cm -3 . The effective surface recombination velocity, S eff , for passivated double layer on n-type FZ Si reached 11 cm/s and for FZ-pSi-14 cm/s, and for Cz-pSi-16-20 cm/s. Effect of hydrogen in the passivation process is discussed.

  2. An experimental and theoretical study of pendellösung fringes in synchrotron section topographs of silicon wafers.

    Science.gov (United States)

    Partanen, J; Tuomi, T

    1990-01-01

    X-ray section topographs of nearly perfect Czochralski-grown wafers were made with synchrotron radiation having a continuous spectrum. An intensity curve measured from the x-ray film is compared to the calculated curve obtained using the dynamical theory of x-ray diffraction. A computer simulation of the topograph is also presented. A good agreement between theory and experiment is found except in the middle part of the topograph.

  3. Elastocapillary folding of three dimensional micro-structures using water pumped through the wafer via a silicon nitride tube

    NARCIS (Netherlands)

    Legrain, A.B.H.; Berenschot, Johan W.; Sanders, Remco G.P.; Ma, Kechun; Tas, Niels Roelof; Abelmann, Leon

    2011-01-01

    In this paper we present the first investigation of a batch method for folding of threedimensional micrometer-sized silicon nitride structures by capillary forces. Silicon nitride tubes have been designed and fabricated using DRIE at the center of the planar origami patterns of the structures. Water

  4. Serial section scanning electron microscopy (S3EM on silicon wafers for ultra-structural volume imaging of cells and tissues.

    Directory of Open Access Journals (Sweden)

    Heinz Horstmann

    Full Text Available High resolution, three-dimensional (3D representations of cellular ultrastructure are essential for structure function studies in all areas of cell biology. While limited subcellular volumes have been routinely examined using serial section transmission electron microscopy (ssTEM, complete ultrastructural reconstructions of large volumes, entire cells or even tissue are difficult to achieve using ssTEM. Here, we introduce a novel approach combining serial sectioning of tissue with scanning electron microscopy (SEM using a conductive silicon wafer as a support. Ribbons containing hundreds of 35 nm thick sections can be generated and imaged on the wafer at a lateral pixel resolution of 3.7 nm by recording the backscattered electrons with the in-lens detector of the SEM. The resulting electron micrographs are qualitatively comparable to those obtained by conventional TEM. S(3EM images of the same region of interest in consecutive sections can be used for 3D reconstructions of large structures. We demonstrate the potential of this approach by reconstructing a 31.7 µm(3 volume of a calyx of Held presynaptic terminal. The approach introduced here, Serial Section SEM (S(3EM, for the first time provides the possibility to obtain 3D ultrastructure of large volumes with high resolution and to selectively and repetitively home in on structures of interest. S(3EM accelerates process duration, is amenable to full automation and can be implemented with standard instrumentation.

  5. A simple chemical method for the separation of phosphorus interfering the trace element determinations by neutron activation analysis in high doped silicon wafers

    International Nuclear Information System (INIS)

    Wagler, H.; Flachowsky, J.

    1986-01-01

    Neutron activation analysis is one of the most available method for the determination of trace elements, but in the case of P-doped silicon wafers the 32 P-activity interferes the gamma spectrometry. It is not possible to determine the trace elements without chemical manipulations. On the other hand, time consuming chemical separations should be avoided. Therefore, a simple and rapid P-separation method has to be developed, in which the following twelve trace elements should be taken into consideration: Ag, As, Au, Co, Cr, Cu, Fe, Mo, Na, Sb, W, and Zn. After acid oxidative dissolution of the activated sample, P is present as phosphate ion. The phosphate ion is removed by precipitation as BiPO 4 . (author)

  6. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    Science.gov (United States)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-10-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W-1. The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S21) is below 0.4 dB from 0 to 40 GHz and the return loss (S11) is less than -20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S21 shifting caused by the packaging structure is below 0.5 dB, and S11 is less than -10 dB from 8 GHz to 14 GHz.

  7. A wafer-scale packaging structure with monolithic microwave integrated circuits and passives embedded in a silicon substrate for multichip modules for radio frequency applications

    International Nuclear Information System (INIS)

    Geng, Fei; Ding, Xiao-yun; Xu, Gao-wei; Luo, Le

    2009-01-01

    A wafer-level packaging structure with chips and passive components embedded in a silicon substrate for multichip modules (MCM) is proposed for radio frequency (RF) applications. The packaging structure consists of two layers of benzocyclobutene (BCB) films and three layers of metalized films, in which the monolithic microwave ICs (MMICs), thin film resistors, striplines and microstrip lines are integrated. The low resistivity silicon wafer with etched cavities is used as a substrate. The BCB films serve as interlayer dielectrics (ILDs). Wirebonding gold bumps are used as electric interconnections between different layers, which eliminate the need of preparing vias by costly procedures including dry etching, metal sputtering and electroplating. The chemical mechanical planarization (CMP) is used to uncover the gold bumps, and the BCB curing profile is optimized to obtain the appropriate BCB film for CMP process. In this work, the thermal, mechanical, electrical as well as RF properties of the packaging structure are investigated. The packaging thermal resistance can be controlled below 2 °C W −1 . The average shear strength of the gold bumps on the BCB surface is about 70 MPa. In addition, a Kelvin test structure is fabricated for resistance testing of the vertical vias. The performances of MMIC and interconnection structure at high frequency are simulated and tested. The testing results reveal that the slight shifting of S-parameter curves of the packaged MMIC indicates perfect transmission characteristics at high frequency. For the transition structure of transmission line, the experimental results are compatible with the simulation results. The insertion loss (S 21 ) is below 0.4 dB from 0 to 40 GHz and the return loss (S 11 ) is less than −20 dB from 0 to 40 GHz. For a low noise amplifier (LNA) chip, the S 21 shifting caused by the packaging structure is below 0.5 dB, and S 11 is less than −10 dB from 8 GHz to 14 GHz

  8. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  9. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y.; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K{alpha}0.28 keV and Al K{alpha}1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K{alpha} ({approx}6 nm rms) is significantly larger than {approx}1 nm at Al K{alpha}. This can be explained by different coherent lengths at two energies.

  10. Evaluation of the soft x-ray reflectivity of micropore optics using anisotropic wet etching of silicon wafers.

    Science.gov (United States)

    Mitsuishi, Ikuyuki; Ezoe, Yuichiro; Koshiishi, Masaki; Mita, Makoto; Maeda, Yoshitomo; Yamasaki, Noriko Y; Mitsuda, Kazuhisa; Shirata, Takayuki; Hayashi, Takayuki; Takano, Takayuki; Maeda, Ryutaro

    2010-02-20

    The x-ray reflectivity of an ultralightweight and low-cost x-ray optic using anisotropic wet etching of Si (110) wafers is evaluated at two energies, C K(alpha)0.28 keV and Al K(alpha)1.49 keV. The obtained reflectivities at both energies are not represented by a simple planar mirror model considering surface roughness. Hence, an geometrical occultation effect due to step structures upon the etched mirror surface is taken into account. Then, the reflectivities are represented by the theoretical model. The estimated surface roughness at C K(alpha) (approximately 6 nm rms) is significantly larger than approximately 1 nm at Al K(alpha). This can be explained by different coherent lengths at two energies.

  11. Dependency of anti-ferro-magnetic coupling strength on Ru spacer thickness of [Co/Pd]{sub n}-synthetic-anti-ferro-magnetic layer in perpendicular magnetic-tunnel-junctions fabricated on 12-inch TiN electrode wafer

    Energy Technology Data Exchange (ETDEWEB)

    Chae, Kyo-Suk [MRAM Center, Department of Electronics, Hanyang University, Seoul 133-791 (Korea, Republic of); Samsung Electronics Co., Ltd., San #16 Banwol-dong, Hwasung-City, Gyeonggi-Do 445-701 (Korea, Republic of); Shim, Tae-Hun; Park, Jea-Gun, E-mail: parkjgL@hanyang.ac.kr [MRAM Center, Department of Electronics, Hanyang University, Seoul 133-791 (Korea, Republic of)

    2014-07-21

    We investigated the Ru spacer-thickness effect on the anti-ferro-magnetic coupling strength (J{sub ex}) of a [Co/Pd]{sub n}-synthetic-anti-ferro-magnetic layer fabricated with Co{sub 2}Fe{sub 6}B{sub 2}/MgO based perpendicular-magnetic-tunneling-junction spin-valves on 12-in. TiN electrode wafers. J{sub ex} peaked at a certain Ru spacer-thickness: specifically, a J{sub ex} of 0.78 erg/cm{sup 2} at 0.6 nm, satisfying the J{sub ex} criteria for realizing the mass production of terra-bit-level perpendicular-spin-transfer-torque magnetic-random-access-memory. Otherwise, J{sub ex} rapidly degraded when the Ru spacer-thickness was less than or higher than 0.6 nm. As a result, the allowable Ru thickness variation should be controlled less than 0.12 nm to satisfy the J{sub ex} criteria. However, the Ru spacer-thickness did not influence the tunneling-magneto-resistance (TMR) and resistance-area (RA) of the perpendicular-magnetic-tunneling-junction (p-MTJ) spin-valves since the Ru spacer in the synthetic-anti-ferro-magnetic layer mainly affects the anti-ferro-magnetic coupling efficiency rather than the crystalline linearity of the Co{sub 2}Fe{sub 6}B{sub 2} free layer/MgO tunneling barrier/Co{sub 2}Fe{sub 6}B{sub 2} pinned layer, although Co{sub 2}Fe{sub 6}B{sub 2}/MgO based p-MTJ spin-valves ex-situ annealed at 275 °C achieved a TMR of ∼70% at a RA of ∼20 Ω μm{sup 2}.

  12. The development of 8 inch roll-to-plate nanoimprint lithography (8-R2P-NIL) system

    Science.gov (United States)

    Lee, Lai Seng; Mohamed, Khairudin; Ooi, Su Guan

    2017-07-01

    Growth in semiconductor and integrated circuit industry was observed in the past decennium of years for industrial technology which followed Moore's law. The line width of nanostructure to be exposed was influenced by the essential technology of photolithography. Thus, it is crucial to have a low cost and high throughput manufacturing process for nanostructures. Nanoimprint Lithography technique invented by Stephen Y. Chou was considered as major nanolithography process to be used in future integrated circuit and integrated optics. The drawbacks of high imprint pressure, high imprint temperature, air bubbles formation, resist sticking to mold and low throughput of thermal nanoimprint lithography on silicon wafer have yet to be solved. Thus, the objectives of this work is to develop a high throughput, low imprint force, room temperature UV assisted 8 inch roll to plate nanoimprint lithography system capable of imprinting nanostructures on 200 mm silicon wafer using roller imprint with flexible mold. A piece of resist spin coated silicon wafer was placed onto vacuum chuck drives forward by a stepper motor. A quartz roller wrapped with a piece of transparent flexible mold was used as imprint roller. The imprinted nanostructures were cured by 10 W, 365 nm UV LED which situated inside the quartz roller. Heat generated by UV LED was dissipated by micro heat pipe. The flexible mold detaches from imprinted nanostructures in a 'line peeling' pattern and imprint pressure was measured by ultra-thin force sensors. This system has imprinting speed capability ranging from 0.19 mm/s to 5.65 mm/s, equivalent to imprinting capability of 3 to 20 pieces of 8 inch wafers per hour. Speed synchronization between imprint roller and vacuum chuck was achieved by controlling pulse rate supplied to stepper motor which drive the vacuum chuck. The speed different ranging from 2 nm/s to 98 nm/s is achievable. Vacuum chuck height was controlled by stepper motor with displacement of 5 nm/step.

  13. Organized metamaterials comprised of gold nanoneedles in a lattice generated on silicon (100) wafer substrates by interfering femtosecond laser processing

    Science.gov (United States)

    Nakata, Yoshiki; Momoo, Kazuma; Miyanaga, Noriaki; Hiromoto, Takuya; Tsuchida, Kunio

    2013-07-01

    Interfering femtosecond (fs) laser processing has been applied to fabricate organized metamaterials on substrates. We have named the unit structures as nanowhiskers, nanoneedles, nanodrops, and nanocrowns. The processes used for formation of these structures are analogous to the motion of a liquid as captured by a high-speed CCD camera; these structures are fabricated via liquid motion of a metallic thin film on solid substrates. From the perspective of a practical, the adaptability of this technique to silicon technology, including lithography, is very important. In this paper, Au nanoneedles on nanobumps in a lattice structure were fabricated on silicon (100) substrates. In addition, the use of a zeroth-order beam, which has been excluded in past experiments, was shown to result in a low photon cost.

  14. Co-Design Method and Wafer-Level Packaging Technique of Thin-Film Flexible Antenna and Silicon CMOS Rectifier Chips for Wireless-Powered Neural Interface Systems

    Directory of Open Access Journals (Sweden)

    Kenji Okabe

    2015-12-01

    Full Text Available In this paper, a co-design method and a wafer-level packaging technique of a flexible antenna and a CMOS rectifier chip for use in a small-sized implantable system on the brain surface are proposed. The proposed co-design method optimizes the system architecture, and can help avoid the use of external matching components, resulting in the realization of a small-size system. In addition, the technique employed to assemble a silicon large-scale integration (LSI chip on the very thin parylene film (5 μm enables the integration of the rectifier circuits and the flexible antenna (rectenna. In the demonstration of wireless power transmission (WPT, the fabricated flexible rectenna achieved a maximum efficiency of 0.497% with a distance of 3 cm between antennas. In addition, WPT with radio waves allows a misalignment of 185% against antenna size, implying that the misalignment has a less effect on the WPT characteristics compared with electromagnetic induction.

  15. Influence of the organic solvents on the properties of the phosphoric acid dopant emulsion deposited on multicrystalline silicon wafers

    International Nuclear Information System (INIS)

    Bouhafs, D; Moussi, A; Boumaour, M; Abaidia, S E K; Mahiou, L; Messaoud, A

    2007-01-01

    This study is devoted to the formation of an n + p emitter for multicrystalline silicon (mc-Si) solar cells for photovoltaic (PV) application. The atomization technique has been used to make the emitter from H 3 PO 4 phosphoric acid as a doping source. The doping emulsion has been optimized using several organic solvents. H 3 PO 4 was mixed with one of these solutions: ethanol, 2-butanol, isopropanol alcohol and deionized water. The volume concentration of H 3 PO 4 does not exceed 20% of the total volume emulsion. The deposit characteristics of the emulsion change with the organic solvent. H 3 PO 4 : 2-butanol gives the best deposited layer with acceptable adherence and uniformity on silicon surface. Fourier transform infrared characterizations show the presence of organic and mineral phosphorous bonds in the formed layer. The obtained emitters are characterized by a junction depth in the range 0.2-0.75 μm and a sheet resistance of about 10-90 Ω/□. Such a low cost dopant source combined with a continuous spray process can effectively reduce the cost per Wp of the PV generator

  16. Fabrication and Characterization of Ultra-Thin Silicon Crystalline Wafers for Photovoltaic Applications using a Stress-Induced Lift-off Method (Maken en karakterizeren van ultra-dunne kristallijne silicium substraten met een spanningsgeïnduceerde kliefmethode voor fotovoltaïsche toepassingen)

    OpenAIRE

    Masolin, Alex

    2012-01-01

    In order to reduce material-related costs, there is a need to develop new wafering techniques to produce thin (< 100 µm) crystalline silicon wafers for photovoltaic applications.This work presents a new kerf-free wafering process for single crystal silicon which relies only on thermo-mechanical treatments. The process is named SLIM-Cut (Stress-Induced LIft-off Method).The process flow is as follows: a layer of a material with a coefficient of thermal expansion (metal or polymer) significantly...

  17. Silver nanocrystals of various morphologies deposited on silicon wafer and their applications in ultrasensitive surface-enhanced Raman scattering

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Limiao, E-mail: chenlimiao@csu.edu.cn; Jing, Qifeng; Chen, Jun; Wang, Bodong; Huang, Jianhan; Liu, Younian

    2013-11-15

    Silver nanostructures with dendritic, flower-like and irregular morphologies were controllably deposited on a silicon substrate in an aqueous hydrogen fluoride solution at room temperature. The morphology of the Ag nanostructures changed from dendritic to urchin-like, flowerlike and pinecone-like with increasing the concentration of polyvinyl pyrrolidone (MW = 55,000) from 2 to 10 mM. The Ag nanostructures were characterized by transmission electron microscopy, high-resolution transmission electron microscopy, scanning electron microscopy, energy-dispersive X-ray, and X-ray diffraction. Through a series of time-dependent morphological evolution studies, the growth processes of Ag nanostructures have been systematically investigated and the corresponding growth mechanisms have been discussed. In addition, the morphology-dependent surface-enhanced Raman scattering of as-synthesized Ag nanostructures were investigated. The results indicated that flower-like Ag nanostructure had the highest activity than the other Ag nanostructures for Rhodamine 6G probe molecules. Highlights: • A simple method was developed to prepare dendritic and flower-like Ag nanostructures. • The flower-like Ag nanoparticles exhibit highest SERS activity. • The SERS substrate based on flower-like Ag particles can be used to detect melamine.

  18. Wafer-Scale Integration of Inverted Nanopyramid Arrays for Advanced Light Trapping in Crystalline Silicon Thin Film Solar Cells.

    Science.gov (United States)

    Zhou, Suqiong; Yang, Zhenhai; Gao, Pingqi; Li, Xiaofeng; Yang, Xi; Wang, Dan; He, Jian; Ying, Zhiqin; Ye, Jichun

    2016-12-01

    Crystalline silicon thin film (c-Si TF) solar cells with an active layer thickness of a few micrometers may provide a viable pathway for further sustainable development of photovoltaic technology, because of its potentials in cost reduction and high efficiency. However, the performance of such cells is largely constrained by the deteriorated light absorption of the ultrathin photoactive material. Here, we report an efficient light-trapping strategy in c-Si TFs (~20 μm in thickness) that utilizes two-dimensional (2D) arrays of inverted nanopyramid (INP) as surface texturing. Three types of INP arrays with typical periodicities of 300, 670, and 1400 nm, either on front, rear, or both surfaces of the c-Si TFs, are fabricated by scalable colloidal lithography and anisotropic wet etch technique. With the extra aid of antireflection coating, the sufficient optical absorption of 20-μm-thick c-Si with a double-sided 1400-nm INP arrays yields a photocurrent density of 39.86 mA/cm(2), which is about 76 % higher than the flat counterpart (22.63 mA/cm(2)) and is only 3 % lower than the value of Lambertian limit (41.10 mA/cm(2)). The novel surface texturing scheme with 2D INP arrays has the advantages of excellent antireflection and light-trapping capabilities, an inherent low parasitic surface area, a negligible surface damage, and a good compatibility for subsequent process steps, making it a good alternative for high-performance c-Si TF solar cells.

  19. Large-area, wafer-scale epitaxial growth of germanium on silicon and integration of high-performance transistors

    Science.gov (United States)

    Ghosh, Swapnadip

    Building on a unique two-step, simple MBE growth technique, we have investigated possible dislocation locking mechanisms by dopant impurities, coupled with artificially introduced oxygen. In the case of n-type Ge grown on Si, our materials characterization indicates that the dislocation density (DD) can reach the ˜105 cm-2 level, compared to p-type and undoped Ge on Si (GoS). We note that our Ge film covers the entire underlying Si substrate at the wafer scale without mesas or limited-area growth. In this presentation, we will focus on the use of n-type impurity (phosphorus) diffusing from the Si substrate and the introduction of O at the Ge-Si interface. The O is introduced by growing a thin chemical SiO2 layer on top of the Si substrate before Ge epitaxy begins. Z-contrast cross-sectional TEM images suggest the presence of oxygen precipitates in n-type Ge, whereas these precipitates appear absent in p-type Ge. These oxygen precipitates are known to lock the dislocations. Supporting the argument of precipitate formation, the TEM shows fringes due to various phase boundaries that exist at the precipitate/Ge-crystal interface. We speculate that the formation of phosphorus (P) segregation resulting from slow diffusion of P through precipitates at the precipitate/Ge-crystal interface facilitates dislocation locking. Impurity segregations in turn suppress O concentration in n-type Ge indicating reduced magnitude of DD that appears on the top surface of n-Ge compared to p-Ge film. The O concentrations (1017 to 1018 cm-3) in the n- and p-type GoS films are measured using secondary ionization mass spectroscopy. We also demonstrate the technique to improve the Ge epitaxial quality by inserting air-gapped, SiO2-based nanoscale templates within epitaxially grown Ge on Si. We have shown that the template simultaneously filters threading dislocations propagating from Ge-Si interface and relieves the film stress caused by the TEC mismatch. The finite element modeling stress

  20. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  1. Adhesive wafer bonding

    Science.gov (United States)

    Niklaus, F.; Stemme, G.; Lu, J.-Q.; Gutmann, R. J.

    2006-02-01

    Wafer bonding with intermediate polymer adhesives is an important fabrication technique for advanced microelectronic and microelectromechanical systems, such as three-dimensional integrated circuits, advanced packaging, and microfluidics. In adhesive wafer bonding, the polymer adhesive bears the forces involved to hold the surfaces together. The main advantages of adhesive wafer bonding include the insensitivity to surface topography, the low bonding temperatures, the compatibility with standard integrated circuit wafer processing, and the ability to join different types of wafers. Compared to alternative wafer bonding techniques, adhesive wafer bonding is simple, robust, and low cost. This article reviews the state-of-the-art polymer adhesive wafer bonding technologies, materials, and applications.

  2. Comparison of aggregation behaviors between ionic liquid-type imidazolium gemini surfactant [C12-4-C12im]Br2 and its monomer [C12mim]Br on silicon wafer.

    Science.gov (United States)

    Ao, Mingqi; Xu, Guiying; Pang, Jinyu; Zhao, Taotao

    2009-09-01

    The aggregation of ionic liquid-type imidazolium gemini surfactant [C(12)-4-C(12)im]Br(2) on silicon wafer, which is compared with its monomer [C(12)mim]Br, have been studied. AFM morphology images and contact angle measurements suggest that the aggregations of [C(12)-4-C(12)im]Br(2) and [C(12)mim]Br on silicon wafer follow different mechanisms. Below the critical surface aggregation concentrations (CSAC), both surfactant molecules are adsorbed with their hydrophobic tails facing the air. But above the CSAC, [C(12)-4-C(12)im]Br(2) molecules finally form a bilayer structure with hydrophilic head groups facing the air, whereas [C(12)mim]Br molecules form a multilayer structure, and with increasing its concentration, the layer numbers increase with the hydrophobic chains and hydrophilic head groups facing the air by turns. Besides, the watery wettability of [C(12)-4-C(12)im]Br(2)-treated silica surface is lower than that of [C(12)mim]Br at the concentration of 5.0 cmc, and the infrared spectroscopy suggests that the poorer watery wettability of [C(12)-4-C(12)im]Br(2) may be relative to the less-ordered packing of methylene chains inside the aggregate. These different aggregation behaviors for the two surfactants ascribe to the different molecular structures and electrostatic interactions. This work would have certain theoretical guidance meaning on the modification of solid surface.

  3. Replacement of a photomultiplier tube in a 2-inch thallium-doped sodium iodide gamma spectrometer with silicon photomultipliers and a light guide

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Chan Kyu; Kim, Hyoung Taek; Kim, Jong Yul [Dept. of Nuclear and Quantum Engineering, Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of); and others

    2015-06-15

    The thallium-doped sodium iodide [NaI(Tl)] scintillation detector is preferred as a gamma spectrometer in many fields because of its general advantages. A silicon photomultiplier (SiPM) has recently been developed and its application area has been expanded as an alternative to photomultiplier tubes (PMTs). It has merits such as a low operating voltage, compact size, cheap production cost, and magnetic resonance compatibility. In this study, an array of SiPMs is used to develop an NaI(Tl) gamma spectrometer. To maintain detection efficiency, a commercial NaI(Tl) 2′ X 2′ scintillator is used, and a light guide is used for the transport and collection of generated photons from the scintillator to the SiPMs without loss. The test light guides were fabricated with polymethyl methacrylate and reflective materials. The gamma spectrometer systems were set up and included light guides. Through a series of measurements, the characteristics of the light guides and the proposed gamma spectrometer were evaluated. Simulation of the light collection was accomplished using the DETECT 97 code (A. Levin, E. Hoskinson, and C. Moison, University of Michigan, USA) to analyze the measurement results. The system, which included SiPMs and the light guide, achieved 14.11% full width at half maximum energy resolution at 662 keV.

  4. Replacement of a photomultiplier tube in a 2-inch thallium-doped sodium iodide gamma spectrometer with silicon photomultipliers and a light guide

    Directory of Open Access Journals (Sweden)

    Chankyu Kim

    2015-06-01

    Full Text Available The thallium-doped sodium iodide [NaI(Tl] scintillation detector is preferred as a gamma spectrometer in many fields because of its general advantages. A silicon photomultiplier (SiPM has recently been developed and its application area has been expanded as an alternative to photomultiplier tubes (PMTs. It has merits such as a low operating voltage, compact size, cheap production cost, and magnetic resonance compatibility. In this study, an array of SiPMs is used to develop an NaI(Tl gamma spectrometer. To maintain detection efficiency, a commercial NaI(Tl 2′ × 2′ scintillator is used, and a light guide is used for the transport and collection of generated photons from the scintillator to the SiPMs without loss. The test light guides were fabricated with polymethyl methacrylate and reflective materials. The gamma spectrometer systems were set up and included light guides. Through a series of measurements, the characteristics of the light guides and the proposed gamma spectrometer were evaluated. Simulation of the light collection was accomplished using the DETECT 97 code (A. Levin, E. Hoskinson, and C. Moison, University of Michigan, USA to analyze the measurement results. The system, which included SiPMs and the light guide, achieved 14.11% full width at half maximum energy resolution at 662 keV.

  5. View of silicon disc to be left on moon by Apollo 11 astronauts

    Science.gov (United States)

    1969-01-01

    Closeup view of the one and one-half inch silicon disc which will be left on the moon by the Apollo 11 astronauts. The disc bears meassages of goodwill from heads of state of many nations. The process used to make this wafer is the same as that used to manufacture integrated circuits for electronic equipment. The Kennedy half-dollar illustrates the relative size of the memorial disc.

  6. Materials preparation and fabrication of pyroelectric polymer/silicon MOSFET detector arrays. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Bloomfield, P. [Drexel Univ., Philadelphia, PA (United States). Dept. of Materials Engineering

    1992-03-27

    The authors have delivered several 64-element linear arrays of pyroelectric elements fully integrated on silicon wafers with MOS readout devices. They have delivered detailed drawings of the linear arrays to LANL. They have processed a series of two inch wafers per submitted design. Each two inch wafer contains two 64 element arrays. After spin-coating copolymer onto the arrays, vacuum depositing the top electrodes, and polarizing the copolymer films so as to make them pyroelectrically active, each wafer was split in half. The authors developed a thicker oxide coating separating the extended gate electrode (beneath the polymer detector) from the silicon. This should reduce its parasitic capacitance and hence improve the S/N. They provided LANL three processed 64 element sensor arrays. Each array was affixed to a connector panel and selected solder pads of the common ground, the common source voltage supply connections, the 64 individual drain connections, and the 64 drain connections (for direct pyroelectric sensing response rather than the MOSFET action) were wire bonded to the connector panel solder pads. This entails (64 + 64 + 1 + 1) = 130 possible bond connections per 64 element array. This report now details the processing steps and the progress of the individual wafers as they were carried through from beginning to end.

  7. Influence of high temperature processing of sol-gel derived barium titanate thin films deposited on platinum and strontium ruthenate coated silicon wafers

    NARCIS (Netherlands)

    Stawski, Tomasz; Vijselaar, Wouter Jan, Cornelis; Göbel, Ole; Veldhuis, Sjoerd; Smith, B.F.; Blank, David H.A.; ten Elshof, Johan E.

    2012-01-01

    Thin films of barium titanate (BTO) of 200 nm thickness, derived from an alkoxide¿carboxylate sol¿gel process, were deposited on Pt/Ti and SrRuO3/ZrO2¿8%Y2O3 coated Si wafers. Films with a dense columnar microstructure were obtained by repeated deposition of thin amorphous layers from

  8. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  9. Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

    Directory of Open Access Journals (Sweden)

    Xiao Li

    2018-03-01

    Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

  10. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  11. Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

    Directory of Open Access Journals (Sweden)

    Guoyou Liu

    2015-09-01

    Full Text Available Based on the construction of the 8-inch fabrication line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor (DMOS+ insulated-gate bipolar transistor (IGBT technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

  12. Metal-induced rapid transformation of diamond into single and multilayer graphene on wafer scale.

    Science.gov (United States)

    Berman, Diana; Deshmukh, Sanket A; Narayanan, Badri; Sankaranarayanan, Subramanian K R S; Yan, Zhong; Balandin, Alexander A; Zinovev, Alexander; Rosenmann, Daniel; Sumant, Anirudha V

    2016-07-04

    The degradation of intrinsic properties of graphene during the transfer process constitutes a major challenge in graphene device fabrication, stimulating the need for direct growth of graphene on dielectric substrates. Previous attempts of metal-induced transformation of diamond and silicon carbide into graphene suffers from metal contamination and inability to scale graphene growth over large area. Here, we introduce a direct approach to transform polycrystalline diamond into high-quality graphene layers on wafer scale (4 inch in diameter) using a rapid thermal annealing process facilitated by a nickel, Ni thin film catalyst on top. We show that the process can be tuned to grow single or multilayer graphene with good electronic properties. Molecular dynamics simulations elucidate the mechanism of graphene growth on polycrystalline diamond. In addition, we demonstrate the lateral growth of free-standing graphene over micron-sized pre-fabricated holes, opening exciting opportunities for future graphene/diamond-based electronics.

  13. Experimental Evaluation of Incorporating Digital and Analog Integrated Circuit Die on a Common Substrate Utilizing Silicon-Hybrid Wafer-Scale Integration Technology

    Science.gov (United States)

    1992-03-01

    an uncoated optical alignment flat surface ... ............. . 5-4 5.2. Profilometer measurement of a polished Teflon coating on the optical...as interlevel dielectrics. The most common examples are: silicon dioxide, silicon nitride, spin- on glass (SOG), benzocyclobutene ( BCB ), and the...Glass 3.0 0.2-0.5 - 0.9 BCB 2.75 2.5 30-60 0.2-0.3 Polyimide 3.4 3 5-60 0.5-1.5 the area of vias tend to absorb moisture which adversely affects metal

  14. Coupling of an electrodialyzer with inductively coupled plasma mass spectrometry for the on-line determination of trace impurities in silicon wafers after surface metal extraction.

    Science.gov (United States)

    Chang, I-long; Hsu, I-hsiang; Yang, Mo-hsiung; Sun, Yun-chang

    2010-02-19

    Understanding the properties that determine the distribution and behavior of trace impurities in Si wafers is critical to defining and controlling the performance, reliability, and yields of integrated microelectronic devices. It remains, however, an intrinsically difficult task to determine trace impurities in Si because of the minute concentrations and extremely high levels of matrix involved. In this study, we used an electrodialyzer for the simultaneous on-line removal of the silicate and acid matrices through the neutralization of the excessive hydrogen ion and selectively separation of acid and silicate ions by the combination of electrode reaction as a source of hydroxide ions with the anion exchange membrane separation. To retain the analyte ions in the sample stream, we found that the presence of moderate amounts of nitric acid and hydrazine were necessary to improve the retention efficiency, not only for Zn(2+), Ni(2+), Cu(2+), and Co(2+) ions but also for CrO(4)(2-) ion. Under the optimized conditions, the interference that resulted from the sample matrix was suppressed significantly to provide satisfactory analytical signals. The precision of this method was ca. 5% when we used an electrodialyzer equipped with an anion exchange membrane to remove the sample matrix prior to performing inductively coupled plasma mass spectrometry (ICP-MS); the good agreement between the data obtained using our proposed method and those obtained using a batchwise wet chemical technique confirmed its accuracy. Our method permits the determination of Zn, Ni, Cu, Co, and Cr in Si wafers at detection limits within the range from 2.2 x 10(15) to 9.0 x 10(15) atoms cm(-3). Copyright 2009 Elsevier B.V. All rights reserved.

  15. H+ ion-implantation energy dependence of electronic transport properties in the MeV range in n-type silicon wafers using frequency-domain photocarrier radiometry

    International Nuclear Information System (INIS)

    Wang Chinhua; Mandelis, Andreas; Tolev, Jordan; Burchard, Bernd; Meijer, Jan

    2007-01-01

    Industrial n-type Si wafers (resistivity of 5-10 Ω cm) were H + ion implanted with energies between 0.75 and 2.00 MeV, and the electronic transport properties of the implanted layer (recombination lifetime, carrier diffusion coefficient, and front-surface and implanted-interface recombination velocities s 1 and s 2 ) were studied using photocarrier radiometry (PCR). A quantitative fitting procedure to the diffusing photoexcited free-carrier density wave was introduced using a relatively simple two-layer PCR model in lieu of the more realistic but substantially more complicated three-layer model. The experimental trends in the transport properties of H + -implanted Si layers extracted from the PCR amplitude and phase data as functions of implantation energy corroborate a physical model of the implanted layer in which (a) overlayer damage due to the light H + ions decreases with increased depth of implantation at higher energies (b) the implanted region damage close to the interface is largely decoupled from the overlayer crystallinity, and (c) the concentration of implanted H + ions decreases at higher implantation energies at the interface, thus decreasing the degree of implantation damage at the interface proper

  16. Wafer-bonded 2-D CMUT arrays incorporating through-wafer trench-isolated interconnects with a supporting frame.

    Science.gov (United States)

    Zhuang, Xuefeng; Wygant, Ira O; Lin, Der-Song; Kupnik, Mario; Oralkan, Omer; Khuri-Yakub, Butrus T

    2009-01-01

    This paper reports on wafer-bonded, fully populated 2-D capacitive micromachined ultrasonic transducer (CMUT) arrays. To date, no successful through-wafer via fabrication technique has been demonstrated that is compatible with the wafer-bonding method of making CMUT arrays. As an alternative to through-wafer vias, trench isolation with a supporting frame is incorporated into the 2-D arrays to provide through-wafer electrical connections. The CMUT arrays are built on a silicon-on-insulator (SOI) wafer, and all electrical connections to the array elements are brought to the back side of the wafer through the highly conductive silicon substrate. Neighboring array elements are separated by trenches on both the device layer and the bulk silicon. A mesh frame structure, providing mechanical support, is embedded between silicon pillars, which electrically connect to individual elements. We successfully fabricated a 16 x 16-element 2-D CMUT array using wafer bonding with a yield of 100%. Across the array, the pulse-echo amplitude distribution is uniform (rho = 6.6% of the mean amplitude). In one design, we measured a center frequency of 7.6 MHz, a peak-to-peak output pressure of 2.9 MPa at the transducer surface, and a 3-dB fractional bandwidth of 95%. Volumetric ultrasound imaging was demonstrated by chip-to-chip bonding one of the fabricated 2-D arrays to a custom-designed integrated circuit (IC). This study shows that through-wafer trench-isolation with a supporting frame is a viable solution for providing electrical interconnects to CMUT elements and that 2-D arrays fabricated using waferbonding deliver good performance.

  17. Development of AC-coupled, poly-silicon biased, p-on-n silicon strip detectors in India for HEP experiments

    Science.gov (United States)

    Jain, Geetika; Dalal, Ranjeet; Bhardwaj, Ashutosh; Ranjan, Kirti; Dierlamm, Alexander; Hartmann, Frank; Eber, Robert; Demarteau, Marcel

    2018-02-01

    P-on-n silicon strip sensors having multiple guard-ring structures have been developed for High Energy Physics applications. The study constitutes the optimization of the sensor design, and fabrication of AC-coupled, poly-silicon biased sensors of strip width of 30 μm and strip pitch of 55 μm. The silicon wafers used for the fabrication are of 4 inch n-type, having an average resistivity of 2-5 k Ω cm, with a thickness of 300 μm. The electrical characterization of these detectors comprises of: (a) global measurements of total leakage current, and backplane capacitance; (b) strip and voltage scans of strip leakage current, poly-silicon resistance, interstrip capacitance, interstrip resistance, coupling capacitance, and dielectric current; and (c) charge collection measurements using ALiBaVa setup. The results of the same are reported here.

  18. Silicon trench photodiodes on a wafer for efficient X-ray-to-current signal conversion using side-X-ray-irradiation mode

    Science.gov (United States)

    Ariyoshi, Tetsuya; Takane, Yuta; Iwasa, Jumpei; Sakamoto, Kenji; Baba, Akiyoshi; Arima, Yutaka

    2018-04-01

    In this paper, we report a direct-conversion-type X-ray sensor composed of trench-structured silicon photodiodes, which achieves a high X-ray-to-current conversion efficiency under side X-ray irradiation. The silicon X-ray sensor with a length of 22.6 mm and a trench depth of 300 µm was fabricated using a single-poly single-metal 0.35 µm process. X-rays with a tube voltage of 80 kV were irradiated along the trench photodiode from the side of the test chip. The theoretical limit of X-ray-to-current conversion efficiency of 83.8% was achieved at a low reverse bias voltage of 25 V. The X-ray-to-electrical signal conversion efficiency of conventional indirect-conversion-type X-ray sensors is about 10%. Therefore, the developed sensor has a conversion efficiency that is about eight times higher than that of conventional sensors. It is expected that the developed X-ray sensor will be able to markedly lower the radiation dose required for X-ray diagnoses.

  19. Temperature Uniformity of Wafer on a Large-Sized Susceptor for a Nitride Vertical MOCVD Reactor

    International Nuclear Information System (INIS)

    Li Zhi-Ming; Jiang Hai-Ying; Han Yan-Bin; Li Jin-Ping; Yin Jian-Qin; Zhang Jin-Cheng

    2012-01-01

    The effect of coil location on wafer temperature is analyzed in a vertical MOCVD reactor by induction heating. It is observed that the temperature distribution in the wafer with the coils under the graphite susceptor is more uniform than that with the coils around the outside wall of the reactor. For the case of coils under the susceptor, we find that the thickness of the susceptor, the distance from the coils to the susceptor bottom and the coil turns significantly affect the temperature uniformity of the wafer. An optimization process is executed for a 3-inch susceptor with this kind of structure, resulting in a large improvement in the temperature uniformity. A further optimization demonstrates that the new susceptor structure is also suitable for either multiple wafers or large-sized wafers approaching 6 and 8 inches

  20. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    of wafer through-holes the main challenge is to protect the CMOS wafer during etching. In the case of DRIE etching of the wafer through-holes the main challenges are proper insulation of the wafer through-holes, conformal deposition of via metal and structuring of the deposited metal. This thesis discusses...

  1. Stable wafer-carrier system

    Energy Technology Data Exchange (ETDEWEB)

    Rozenzon, Yan; Trujillo, Robert T; Beese, Steven C

    2013-10-22

    One embodiment of the present invention provides a wafer-carrier system used in a deposition chamber for carrying wafers. The wafer-carrier system includes a base susceptor and a top susceptor nested inside the base susceptor with its wafer-mounting side facing the base susceptor's wafer-mounting side, thereby forming a substantially enclosed narrow channel. The base susceptor provides an upward support to the top susceptor.

  2. Genesis of nanostructured, magnetically tunable ceramics from the pyrolysis of cross-linked polyferrocenylsilane networks and formation of shaped macroscopic objects and micron scale patterns by micromolding inside silicon wafers.

    Science.gov (United States)

    Ginzburg, Madlen; MacLachlan, Mark J; Yang, San Ming; Coombs, Neil; Coyle, Thomas W; Raju, Nandyala P; Greedan, John E; Herber, Rolfe H; Ozin, Geoffrey A; Manners, Ian

    2002-03-20

    The ability to form molded or patterned metal-containing ceramics with tunable properties is desirable for many applications. In this paper we describe the evolution of a ceramic from a metal-containing polymer in which the variation of pyrolysis conditions facilitates control of ceramic structure and composition, influencing magnetic and mechanical properties. We have found that pyrolysis under nitrogen of a well-characterized cross-linked polyferrocenylsilane network derived from the ring-opening polymerization (ROP) of a spirocyclic [1]ferrocenophane precursor gives shaped macroscopic magnetic ceramics consisting of alpha-Fe nanoparticles embedded in a SiC/C/Si(3)N(4) matrix in greater than 90% yield up to 1000 degrees C. Variation of the pyrolysis temperature and time permitted control over the nucleation and growth of alpha-Fe particles, which ranged in size from around 15 to 700 A, and the crystallization of the surrounding matrix. The ceramics contained smaller alpha-Fe particles when prepared at temperatures lower than 900 degrees C and displayed superparamagnetic behavior, whereas the materials prepared at 1000 degrees C contained larger alpha-Fe particles and were ferromagnetic. This flexibility may be useful for particular materials applications. In addition, the composition of the ceramic was altered by changing the pyrolysis atmosphere to argon, which yielded ceramics that contain Fe(3)Si(5). The ceramics have been characterized by a combination of physical techniques, including powder X-ray diffraction, TEM, reflectance UV-vis/near-IR spectroscopy, elemental analysis, XPS, SQUID magnetometry, Mössbauer spectroscopy, nanoindentation, and SEM. Micromolding of the spirocyclic [1]ferrocenophane precursor within soft lithographically patterned channels housed inside silicon wafers followed by thermal ROP and pyrolysis enabled the formation of predetermined micron scale designs of the magnetic ceramic.

  3. 8-inch IBM floppy disk

    CERN Multimedia

    1971-01-01

    The 8-inch floppy disk was a magnetic storage disk for the data introduced commercially by IBM in 1971. It was designed by an IBM team as an inexpensive way to load data into the IBM System / 370. Plus it was a read-only bare disk containing 80 KB of data. The first read-write version was introduced in 1972 by Memorex and could contain 175 KB on 50 tracks (with 8 sectors per track). Other improvements have led to various coatings and increased capacities. Finally, it was surpassed by the mini diskette of 5.25 inches introduced in 1976.

  4. One step automated unpatterned wafer defect detection and classification

    International Nuclear Information System (INIS)

    Dou Lie; Kesler, Daniel; Bruno, William; Monjak, Charles; Hunt, Jim

    1998-01-01

    Automated detection and classification of crystalline defects on micro-grade silicon wafers is extremely important for integrated circuit (IC) device yield. High training cost, limited capability of classifying defects, increasing possibility of contamination, and unexpected human mistakes necessitate the need to replace the human visual inspection with automated defect inspection. The Laser Scanning Surface Inspection Systems (SSISs) equipped with the Reconvergent Specular Detection (RSD) apparatus are widely used for final wafer inspection. RSD, more commonly known as light channel detection (LC), is capable of detecting and classifying material defects by analyzing information from two independent phenomena, light scattering and reflecting. This paper presents a new technique including a new type of light channel detector to detect and classify wafer surface defects such as slipline dislocation, Epi spikes, Pits, and dimples. The optical system to study this technique consists of a particle scanner to detect and quantify light scattering events from contaminants on the wafer surface and a RSD apparatus (silicon photo detector). Compared with the light channel detector presently used in the wafer fabs, this new light channel technique provides higher sensitivity for small defect detection and more defect scattering signatures for defect classification. Epi protrusions (mounds and spikes), slip dislocations, voids, dimples, and some other common defect features and contamination on silicon wafers are studied using this equipment. The results are compared quantitatively with that of human visual inspection and confirmed by microscope or AFM. This new light channel technology could provide the real future solution to the wafer manufacturing industry for fully automated wafer inspection and defect characterization

  5. 1366 Project Automate: Enabling Automation for <$0.10/W High-Efficiency Kerfless Wafers Manufactured in the US

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2017-05-10

    For photovoltaic (PV) manufacturing to thrive in the U.S., there must be an innovative core to the technology. Project Automate builds on 1366’s proprietary Direct Wafer® kerfless wafer technology and aims to unlock the cost and efficiency advantages of thin kerfless wafers. Direct Wafer is an innovative, U.S.-friendly (efficient, low-labor content) manufacturing process that addresses the main cost barrier limiting silicon PV cost-reductions – the 35-year-old grand challenge of manufacturing quality wafers (40% of the cost of modules) without the cost and waste of sawing. This simple, scalable process will allow 1366 to manufacture “drop-in” replacement wafers for the $10 billion silicon PV wafer market at 50% of the cost, 60% of the capital, and 30% of the electricity of conventional casting and sawing manufacturing processes. This SolarMat project developed the Direct Wafer processes’ unique capability to tailor the shape of wafers to simultaneously make thinner AND stronger wafers (with lower silicon usage) that enable high-efficiency cell architectures. By producing wafers with a unique target geometry including a thick border (which determines handling characteristics) and thin interior regions (which control light capture and electron transport and therefore determine efficiency), 1366 can simultaneously improve quality and lower cost (using less silicon).

  6. Design, fabrication and characterization of the first AC-coupled silicon microstrip sensors in India

    CERN Document Server

    Aziz, T; Mohanty, G.B.; Patil, M.R.; Rao, K.K.; Rani, Y.R.; Rao, Y.P.P.; Behnamian, H.; Mersi, S.; Naseri, M.

    2014-01-01

    This paper reports the design, fabrication and characterization of single-sided silicon microstrip sensors with integrated biasing resistors and coupling capacitors, produced for the first time in India. We have first developed a prototype sensor with different width and pitch combinations on a single 4-inch wafer. After finding test procedures for characterizing these AC coupled sensors, we have chosen an optimal width-pitch combination and also fine-tuned various process parameters in order to produce sensors with the desired specifications.

  7. Future application of Czochralski crystal pulling for silicon

    Science.gov (United States)

    Matlcok, J. H.

    1985-08-01

    Czochralski (Cz) crystal pulling has been the predominant method used for preparing silicon single crystal for the past twenty years. The fundamental technology used has changed little. However, great strides have been made in learning how to make the crystals bigger and of better quality at ever increasing productivity rates. Currently charge sizes of 50 kg of polycrystal silicon are being used for production and crystals up to ten inches in diameter have been grown without major difficulty. The largest material actually being processed in silicon wafer form is 150 mm (6 inches) in diameter. Growing of crystals in a magnetic field has proved to be particularly useful for microscopic impurity control. Major developments in past years on equipment for Cz crystal pulling have included the automatic growth control of the diameter as well as the starting core of the crystal, the use of magnetic fields and around the crystal puller to supress convection, various recharging schemes for dopant control and the use of continuous liquid feed in the crystal puller. The latter, while far from being a reliable production process, is ideal in concept for major improvement in Cz crystal pulling. The Czochralski process will maintain its dominance of silicon crystal production for many years.

  8. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  9. Capacitive micromachined ultrasonic transducers with through-wafer interconnects

    Science.gov (United States)

    Zhuang, Xuefeng

    Capacitive micromachined ultrasonic transducer (CMUT) is a promising candidate for making ultrasound transducer arrays for applications such as 3D medical ultrasound, non-destructive evaluation and chemical sensing. Advantages of CMUTs over traditional piezoelectric transducers include low-cost batch fabrication, wide bandwidth, and ability to fabricate arrays with broad operation frequency range and different geometric configurations on a single wafer. When incorporated with through-wafer interconnects, a CMUT array can be directly integrated with a front-end integrated circuit (IC) to achieve compact packaging and to mitigate the effects of the parasitic capacitance from the connection cables. Through-wafer via is the existing interconnect scheme for CMUT arrays, and many other types of micro-electro-mechanical system (MEMS) devices. However, to date, no successful through-wafer via fabrication technique compatible with the wafer-bonding method of making CMUT arrays has been demonstrated. The through-wafer via fabrication steps degrade the surface conditions of the wafer, reduce the radius of curvature, thus making it difficult to bond. This work focuses on new through-wafer interconnect techniques that are compatible with common MEMS fabrication techniques, including both surface-micromachining and direct wafer-to-wafer fusion bonding. In this dissertation, first, a through-wafer via interconnect technique with improved characteristics is presented. Then, two implementations of through-wafer trench isolation are demonstrated. The through-wafer trench methods differ from the through-wafer vias in that the electrical conduction is through the bulk silicon instead of the conductor in the vias. In the first implementation, a carrier wafer is used to provide mechanical support; in the second, mechanical support is provided by a silicon frame structure embedded inside the isolation trenches. Both implementations reduce fabrication complexity compared to the through-wafer

  10. Charge carrier Density Imaging / IR lifetime mapping of Si wafers by Lock-In Thermography

    NARCIS (Netherlands)

    Van der Tempel, L.

    2012-01-01

    ABSTRACT Minority carrier lifetime imaging by lock-in thermography of passivated silicon wafers for photovoltaic cells has been developed for the public Pieken in de Delta project geZONd. CONCLUSIONS Minority carrier lifetime imaging by lock-in thermography of passivatedsilicon wafers is released

  11. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  12. High-precision drop shape analysis (HPDSA) of quasistatic contact angles on silanized silicon wafers with different surface topographies during inclining-plate measurements: Influence of the surface roughness on the contact line dynamics

    International Nuclear Information System (INIS)

    Heib, F.; Hempelmann, R.; Munief, W.M.; Ingebrandt, S.; Fug, F.; Possart, W.; Groß, K.; Schmitt, M.

    2015-01-01

    Highlights: • Analysis of the triple line motion on surfaces with nanoscale surface topographies. • Analysis of the triple line motion is performed in sub-pixel resolution. • A special fitting and statistical approach for contact angle analysis is applied. • The analyses result set of contact angle data which is independent of “user-skills”. • Characteristically density distributions in dependence on the surface properties. - Abstract: Contact angles and wetting of solid surfaces are strongly influenced by the physical and chemical properties of the surfaces. These influence quantities are difficult to distinguish from each other if contact angle measurements are performed by measuring only the advancing θ a and the receding θ r contact angle. In this regard, time-dependent water contact angles are measured on two hydrophobic modified silicon wafers with different physical surface topographies. The first surface is nearly atomically flat while the second surface is patterned (alternating flat and nanoscale rough patterns) which is synthesized by a photolithography and etching procedure. The different surface topographies are characterized with atomic force microscopy (AFM), Fourier transform infrared reflection absorption spectroscopy (FTIRRAS) and Fourier transform infrared attenuated total reflection spectroscopy (FTIR-ATR). The resulting set of contact angle data obtained by the high-precision drop shape analysis approach is further analyzed by a Gompertzian fitting procedure and a statistical counting procedure in dependence on the triple line velocity. The Gompertzian fit is used to analyze overall properties of the surface and dependencies between the motion on the front and the back edge of the droplets. The statistical counting procedure results in the calculation of expectation values E(p) and standard deviations σ(p) for the inclination angle φ, contact angle θ, triple line velocity vel and the covered distance of the triple line dis

  13. Wafer-Scale Aluminum Nanoplasmonic Resonators with Optimized Metal Deposition

    Science.gov (United States)

    2016-01-04

    plasmonics. Unlike plasmonic devices based on coinage metals , such as gold and silver , which are effectively banned from silicon semiconductor fabrication...necessarily represent the view of the United States Government. Wafer-scale Aluminum Nanoplasmonic Resonators with Optimized Metal Deposition...method of aluminum deposition. Three-layer metal -dielectric- metal nanopillar arrays were fabricated in a complementary metal -oxide semiconductor (CMOS

  14. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  15. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  16. Silicon Hybrid Wafer Scale Integration Interconnect Evaluation

    Science.gov (United States)

    1989-12-01

    for both tiIhe test anid referer c lar rr ’I) was accessedl throuigh a BNC connector on lie friit panel of thle HP 4~ 19 1A. F’or all gaini- phase...rrforturnatelv. nonie 4fthle alpriolnriate stakl~ ardl calibrations suppId with other mi- cro)wave p~rob~es ( sh as thle Cascade lprAlws described! in (78...made through cables from the probes to the BNC connectors on the front, panel of the lip 4191A. 3. Volt-ohm meter, for continuity verification. 4. Z-248

  17. Silicon Wafer X-ray Mirror Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  18. Silicon Wafer X-ray Mirror

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to undertake the initial development of a Kirkpatrick-Baez (K-B) type X-ray mirror using the relatively recent availability of high quality, inexpensive,...

  19. High-throughput characterization of stresses in thin film materials libraries using Si cantilever array wafers and digital holographic microscopy

    International Nuclear Information System (INIS)

    Lai, Y. W.; Ludwig, A.; Hamann, S.; Ehmann, M.

    2011-01-01

    We report the development of an advanced high-throughput stress characterization method for thin film materials libraries sputter-deposited on micro-machined cantilever arrays consisting of around 1500 cantilevers on 4-inch silicon-on-insulator wafers. A low-cost custom-designed digital holographic microscope (DHM) is employed to simultaneously monitor the thin film thickness, the surface topography and the curvature of each of the cantilevers before and after deposition. The variation in stress state across the thin film materials library is then calculated by Stoney's equation based on the obtained radii of curvature of the cantilevers and film thicknesses. DHM with nanometer-scale out-of-plane resolution allows stress measurements in a wide range, at least from several MPa to several GPa. By using an automatic x-y translation stage, the local stresses within a 4-inch materials library are mapped with high accuracy within 10 min. The speed of measurement is greatly improved compared with the prior laser scanning approach that needs more than an hour of measuring time. A high-throughput stress measurement of an as-deposited Fe-Pd-W materials library was evaluated for demonstration. The fast characterization method is expected to accelerate the development of (functional) thin films, e.g., (magnetic) shape memory materials, whose functionality is greatly stress dependent.

  20. Wafer thinning for high-density, through-wafer interconnects

    Science.gov (United States)

    Wang, Lianwei; Visser, Cassan C. G.; de Boer, Charles R.; Laros, M.; van der Vlist, W.; Groeneweg, J.; Craciun, G.; Sarro, Pasqualina M.

    2003-01-01

    Thinning of micromachined wafers containing trenches and cavities to realize through-chip interconnects is presented. Successful thinning of wafers by lapping and polishing until the cavities previously etched by deep reactive ion etching are reached is demonstrated. The possible causes of damage to the etched structures are investigated. The trapping of particles in the cavities and suitable cleaning procedures to address this issue are studied. The results achieved so far allow further processing of the thinned wafers to form through wafer interconnections by copper electroplating. Further improvement of the quality of thinned surfaces can be achieved by alternative cleaning procedures.

  1. Ion beam studies of hydrogen implanted Si wafers

    International Nuclear Information System (INIS)

    Nurmela, A.; Henttinen, K.; Suni, T.; Tolkki, A.; Suni, I.

    2004-01-01

    We have studied silicon-on-insulator (SOI) materials with two different ion beam analysis methods. The SOI samples were implanted with boron and hydrogen ions. After implantation the wafers were annealed, and some of them were bonded to thermally oxidized silicon wafers. The damage in silicon single crystal due to ion implantations has been studied by Rutherford Backscattering in the channeling mode (RBS/C). The content of the ion-implanted hydrogen has been studied by elastic recoil detection analysis (ERDA) method. The strength of the implanted region after thermal annealings were measured with the crack opening method. The boron implantation before hydrogen implantation resulted to shallower implantation depth and lower splitting temperature than in samples implanted with hydrogen only. The boron implantation after hydrogen implantation did not influence the splitting temperature and RBS spectra showed that B implantation drove the H deeper to the sample

  2. Wafer-shape based in-plane distortion predictions using superfast 4G metrology

    Science.gov (United States)

    van Dijk, Leon; Mileham, Jeffrey; Malakhovsky, Ilja; Laidler, David; Dekkers, Harold; Van Elshocht, Sven; Anberg, Doug; Owen, David M.; van Haren, Richard

    2017-03-01

    With the latest immersion scanners performing at the sub-2 nm overlay level, the non-lithography contributors to the OnProduct-Overlay budget become more and more dominant. Examples of these contributors are etching, thin film deposition, Chemical-Mechanical Planarization and thermal anneal. These processes can introduce stress or stress changes in the thin films on top of the silicon wafers, resulting in significant wafer grid distortions. High-order wafer alignment (HOWA) is the current ASML solution for correcting wafers with a high order grid distortion introduced by non-lithographic processes, especially when these distortions vary from wafer-to-wafer. These models are currently successfully applied in high volume production at several semiconductor device manufacturers. An important precondition is that the wafer distortions remain global as the polynomial-based HOWA models become less effective for very local distortions. Wafer-shape based feed forward overlay corrections can be a possible solution to overcome this challenge. Thin film stress typically has an impact on the unclamped, free-form shape of the wafers. When an accurate relationship between the wafer shape and in-plane distortion (IPD) after clamping is established then feedforward overlay control can be enabled. In this work we assess the capability of wafer-shape based IPD predictions via a controlled experiment. The processinduced IPDs are accurately measured on the ASML TWINSCANTM system using its SMASH alignment system and the wafer shapes are measured on the Superfast 4G inspection system. In order to relate the wafer shape to the IPD we have developed a prediction model beyond the standard Stoney approximation. The match between the predicted and measured IPD is excellent ( 1-nm), indicating the feasibility of using wafer shape for feed-forward overlay control.

  3. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  4. Ten inch Planar Optic Display

    Energy Technology Data Exchange (ETDEWEB)

    Beiser, L. [Beiser (Leo) Inc., Flushing, NY (United States); Veligdan, J. [Brookhaven National Lab., Upton, NY (United States)

    1996-04-01

    A Planar Optic Display (POD) is being built and tested for suitability as a high brightness replacement for the cathode ray tube, (CRT). The POD display technology utilizes a laminated optical waveguide structure which allows a projection type of display to be constructed in a thin (I to 2 inch) housing. Inherent in the optical waveguide is a black cladding matrix which gives the display a black appearance leading to very high contrast. A Digital Micromirror Device, (DMD) from Texas Instruments is used to create video images in conjunction with a 100 milliwatt green solid state laser. An anamorphic optical system is used to inject light into the POD to form a stigmatic image. In addition to the design of the POD screen, we discuss: image formation, image projection, and optical design constraints.

  5. 10-inch planar optic display

    Science.gov (United States)

    Beiser, Leo; Veligdan, James T.

    1996-05-01

    A planar optic display (POD) is being built and tested for suitability as a high brightness replacement for the cathode ray tube, (CRT). The POD display technology utilizes a laminated optical waveguide structure which allows a projection type of display to be constructed in a thin (1 to 2 inch) housing. Inherent in the optical waveguide is a black cladding matrix which gives the display a black appearance leading to very high contrast. A digital micromirror device, (DMD) from Texas Instruments is used to create video images in conjunction with a 100 milliwatt green solid state laser. An anamorphic optical system is used to inject light into the POD to form a stigmatic image. In addition to the design of the POD screen, we discuss: image formation, image projection, and optical design constraints.

  6. Transformational silicon electronics

    KAUST Repository

    Rojas, Jhonathan Prieto

    2014-02-25

    In today\\'s traditional electronics such as in computers or in mobile phones, billions of high-performance, ultra-low-power devices are neatly integrated in extremely compact areas on rigid and brittle but low-cost bulk monocrystalline silicon (100) wafers. Ninety percent of global electronics are made up of silicon. Therefore, we have developed a generic low-cost regenerative batch fabrication process to transform such wafers full of devices into thin (5 μm), mechanically flexible, optically semitransparent silicon fabric with devices, then recycling the remaining wafer to generate multiple silicon fabric with chips and devices, ensuring low-cost and optimal utilization of the whole substrate. We show monocrystalline, amorphous, and polycrystalline silicon and silicon dioxide fabric, all from low-cost bulk silicon (100) wafers with the semiconductor industry\\'s most advanced high-κ/metal gate stack based high-performance, ultra-low-power capacitors, field effect transistors, energy harvesters, and storage to emphasize the effectiveness and versatility of this process to transform traditional electronics into flexible and semitransparent ones for multipurpose applications. © 2014 American Chemical Society.

  7. MOVPE growth of GaN on 6-inch SOI-substrates: effect of substrate parameters on layer quality and strain

    Science.gov (United States)

    Lemettinen, J.; Kauppinen, C.; Rudzinski, M.; Haapalinna, A.; Tuomi, T. O.; Suihkonen, S.

    2017-04-01

    We demonstrate that higher crystalline quality, lower strain and improved electrical characteristics can be achieved in gallium nitride (GaN) epitaxy by using a silicon-on-insulator (SOI) substrate compared to a bulk silicon (Si) substrate. GaN layers were grown by metal-organic vapor phase epitaxy on 6-inch bulk Si and SOI wafers using the standard step graded AlGaN and AlN approach. The GaN layers grown on SOI exhibited lower strain according to x-ray diffraction analysis. Defect selective etching measurements suggested that the use of SOI substrate for GaN epitaxy reduces the dislocation density approximately by a factor of two. Furthermore, growth on SOI substrate allows one to use a significantly thinner AlGaN buffer compared to bulk Si. Synchrotron radiation x-ray topography analysis confirmed that the stress relief mechanism in GaN on SOI epitaxy is the formation of a dislocation network to the SOI device Si layer. In addition, the buried oxide layer significantly improves the vertical leakage characteristics as the onset of the breakdown is delayed by approximately 400 V. These results show that the GaN on the SOI platform is promising for power electronics applications.

  8. Performance characterization of silicon pore optics

    Science.gov (United States)

    Collon, M. J.; Kraft, S.; Günther, R.; Maddox, E.; Beijersbergen, M.; Bavdaz, M.; Lumb, D.; Wallace, K.; Krumrey, M.; Cibik, L.; Freyberg, M.

    2006-06-01

    The characteristics of the latest generation of assembled silicon pore X-ray optics are discussed in this paper. These very light, stiff and modular high performance pore optics (HPO) have been developed [1] for the next generation of astronomical X-ray telescopes, which require large collecting areas whilst achieving angular resolutions better than 5 arcseconds. The suitability of 12 inch silicon wafers as high quality optical mirrors and the automated assembly process are discussed elsewhere in this conference. HPOs with several tens of ribbed silicon plates are assembled by bending the plates into an accurate cylindrical shape and directly bonding them on top of each other. The achievable figure accuracy is measured during assembly and in test campaigns at X-ray testing facilities like BESSY-II and PANTER. Pencil beam measurements allow gaining information on the quality achieved by the production process with high spatial resolution. In combination with full beam illumination a complete picture of the excellent performance of these optics can be derived. Experimental results are presented and discussed in detail. The results of such campaigns are used to further improve the production process in order to match the challenging XEUS requirements [2] for imaging resolution and mass.

  9. Multi-wafer growth of highly uniform InGaP/GaAs by low pressure MOVPE

    Science.gov (United States)

    McKee, M. A.; McGivney, T.; Walker, D.; Capuder, K.; Norris, P. E.; Stall, R. A.; Rose, B. C.

    1992-03-01

    This paper reports on the large area growth of InGaP/GaAs heterostructures for short wavelength applications (λ ˜ 650 nm) by low pressure MOVPE in a vertical, high speed, rotating disk reactor. Highly uniform films were obtained both on a single 50 mm diam wafer at the center of a 5 inch diam wafer platter and on three, 50 mm diameter GaAs wafers symmetrically placed on a 5 inch diam platter. Characterization was performed by x-ray diffraction, SEM, and room temperature photoluminescence (PL) mapping. For the single wafer growth, PL mapping results show that the total range on wavelength was ±2 nm with a 2 mm edge exclusion. The standard deviation of the peak wavelength, σ w , is 0.7 nm. Thickness uniformity, measured by SEM, is less than 2%. Similar results were obtained for the multi-wafer runs. Each individual wafer has a σ w of 1.1 nm. The wafers have nearly identical PL maps with the variation of the average wavelength from the three wafers within ±0.1 nm.

  10. Proposed method of assembly for the BCD silicon strip vertex detector modules

    International Nuclear Information System (INIS)

    Lindenmeyer, C.

    1989-01-01

    The BCD Silicon strip Vertex Detector is constructed of 10 identical central region modules and 18 similar forward region modules. This memo describes a method of assembling these modules from individual silicon wafers. Each wafer is fitted with associated front end electronics and cables and has been tested to insure that only good wafers reach the final assembly stage. 5 figs

  11. Characterisation of micro-strip and pixel silicon detectors before and after hadron irradiation

    CERN Document Server

    Allport, P.P

    2012-01-01

    The use of segmented silicon detectors for tracking and vertexing in particle physics has grown substantially since their introduction in 1980. It is now anticipated that roughly 50,000 six inch wafers of high resistivity silicon will need to be processed into sensors to be deployed in the upgraded experiments in the future high luminosity LHC (HL-LHC) at CERN. These detectors will also face an extremely severe radiation environment, varying with distance from the interaction point. The volume of required sensors is large and their delivery is required during a relatively short time, demanding a high throughput from the chosen suppliers. The current situation internationally, in this highly specialist market, means that security of supply for large orders can therefore be an issue and bringing additional potential vendors into the field can only be an advantage. Semiconductor companies that could include planar sensors suitable for particle physics in their product lines will, however, need to prove their pro...

  12. Fabrication of capacitive absolute pressure sensor using Si-Au eutectic bonding in SOI wafer

    International Nuclear Information System (INIS)

    Lee, Kang Ryeol; Kim, Kunnyun; Park, Hyo-Derk; Kim, Yong Kook; Choi, Seung-Woo; Choi, Woo-Beom

    2006-01-01

    A capacitive absolute pressure sensor was fabricated using a large deflected diaphragm with a sealed vacuum cavity formed by removing handling silicon wafer and oxide layers from a SOI wafer after eutectic bonding of a silicon wafer to the SOI wafer. The deflected displacements of the diaphragm formed by the vacuum cavity in the fabricated sensor were similar to simulation results. Initial capacitance values were about 2.18pF and 3.65pF under normal atmosphere, where the thicknesses of the diaphragm used to fabricate the vacuum cavity were 20 μm and 30 μm, respectively. Also, it was confirmed that the differences of capacitance value from 1000hPa to 5hPa were about 2.57pF and 5.35pF, respectively

  13. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  14. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  15. Hybrid Integrated Platforms for Silicon Photonics

    Science.gov (United States)

    Liang, Di; Roelkens, Gunther; Baets, Roel; Bowers, John E.

    2010-01-01

    A review of recent progress in hybrid integrated platforms for silicon photonics is presented. Integration of III-V semiconductors onto silicon-on-insulator substrates based on two different bonding techniques is compared, one comprising only inorganic materials, the other technique using an organic bonding agent. Issues such as bonding process and mechanism, bonding strength, uniformity, wafer surface requirement, and stress distribution are studied in detail. The application in silicon photonics to realize high-performance active and passive photonic devices on low-cost silicon wafers is discussed. Hybrid integration is believed to be a promising technology in a variety of applications of silicon photonics.

  16. Silicon sensor prototypes for the Phase II upgrade of the CMS tracker

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, Thomas, E-mail: thomas.bergauer@oeaw.ac.at

    2016-09-21

    The High-Luminosity LHC (HL-LHC) has been identified as the highest priority program in High Energy Physics in the mid-term future. It will provide the experiments an additional integrated luminosity of about 2500 fb{sup −1} over 10 years of operation, starting in 2025. In order to meet the experimental challenges of unprecedented p–p luminosity, especially in terms of radiation levels and occupancy, the CMS collaboration will need to replace its entire strip tracker by a new one. In this paper the baseline layout option for this new Phase-II tracker is shown, together with two variants using a tilted barrel geometry or larger modules from 8-inch silicon wafers. Moreover, the two module concepts are discussed, which consist either of two strip sensors (2S) or of one strip and one pixel sensor (PS). These two designs allow p{sub T} discrimination at module level enabling the tracker to contribute to the L1 trigger decision. The paper presents testing results of the macro-pixel-light sensor for the PS module and shows the first electrical characterization of unirradiated, full-scale strip sensor prototypes for the 2S module concept, both on 6- and 8-inch wafers.

  17. Surface Passivation for Silicon Heterojunction Solar Cells

    NARCIS (Netherlands)

    Deligiannis, D.

    2017-01-01

    Silicon heterojunction solar cells (SHJ) are currently one of the most promising solar cell technologies in the world. The SHJ solar cell is based on a crystalline silicon (c-Si) wafer, passivated on both sides with a thin intrinsic hydrogenated amorphous silicon (a-Si:H) layer. Subsequently, p-type

  18. Porous Silicon Nanowires

    Science.gov (United States)

    Qu, Yongquan; Zhou, Hailong; Duan, Xiangfeng

    2011-01-01

    In this minreview, we summarize recent progress in the synthesis, properties and applications of a new type of one-dimensional nanostructures — single crystalline porous silicon nanowires. The growth of porous silicon nanowires starting from both p- and n-type Si wafers with a variety of dopant concentrations can be achieved through either one-step or two-step reactions. The mechanistic studies indicate the dopant concentration of Si wafers, oxidizer concentration, etching time and temperature can affect the morphology of the as-etched silicon nanowires. The porous silicon nanowires are both optically and electronically active and have been explored for potential applications in diverse areas including photocatalysis, lithium ion battery, gas sensor and drug delivery. PMID:21869999

  19. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  20. Special Issue: The Silicon Age

    Science.gov (United States)

    Kittler, Martin; Yang, Deren

    2006-03-01

    The present issue of physica status solidi (a) contains a collection of articles about different aspects of current silicon research and applications, ranging from basic investigations of mono- and polycrystalline silicon materials and nanostructures to technologies for device fabrication in silicon photovoltaics, micro- and optoelectronics. Guest Editors are Martin Kittler and Deren Yang, the organizers of a recent Sino-German symposium held in Cottbus, Germany, 19-24 September 2005.The cover picture shows four examples of The Silicon Age: the structure of a thin film solar cell on low-cost SSP (silicon sheet from powder) substrate (upper left image) [1], a high-resolution transmission electron microscopy image and diffraction pattern of a single-crystalline Si nanowire (upper right) [2], a carrier lifetime map from an n-type multicrystalline silicon wafer after gettering by a grain boundary (lower left) [3], and a scanning acoustic microscopy image of a bonded 150 mm diameter wafer pair (upper right) [4].

  1. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  2. An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

    Science.gov (United States)

    Liu, Yongxun; Koga, Kazuhiro; Khumpuang, Sommawan; Nagao, Masayoshi; Matsukawa, Takashi; Hara, Shiro

    2017-06-01

    Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

  3. Fabrication of thick silicon nitride blocks embedded in low-resistivity silicon substrates for radio frequency applications

    NARCIS (Netherlands)

    Fernandez, L.J.; Berenschot, Johan W.; Wiegerink, Remco J.; Flokstra, Jakob; Flokstra, Jan; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2006-01-01

    Thick silicon nitride blocks embedded in silicon wafers were recently proposed as a substrate for RF devices. In this paper we show that deep trenches filled with silicon nitride—having thin slices of monocrystalline silicon in between—already result in a significantly improved RF behavior.

  4. Silicon/Porous Silicon Composite Membrane for High Sensitivity Pressure Sensor

    Science.gov (United States)

    2009-07-21

    for integrating with other processes on silicon wafer. The fabrication of silicone rubber membranes for making microvalves has been reported [5...alcohol (IPA) is used along with HF to increase the wettability of the silicon surface and to remove the bubbles formed during the reaction. Aluminium ...Report for AOARD funded Project No. AOARD-074061 Title: Silicon /Porous Silicon composite membrane for high sensitivity pressure sensor PI

  5. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  6. Muon decay channeling in silicon

    International Nuclear Information System (INIS)

    Bosshard, A.; Patterson, B.D.; Straumann, U.; Truoel, P.; Wichert, Th.

    1984-01-01

    This experiment employs the channeling effect of the host lattice on the trajectories of decay positrons in order to determine the position of positive muons implanted into silicon crystals. Low-momentum ( 0 ). In order to achieve sufficient angular resolution, the Si wafer is bent to a spherical shape, thereby focussing a particular crystal axis to a point at the center of the MWPC (located 3.4 m from the wafer). (Auth.)

  7. Wafering economies for industrialization from a wafer manufacturer's viewpoint

    Science.gov (United States)

    Rosenfield, T. P.; Fuerst, F. P.

    1982-01-01

    The key technical limitations which inhibit the lowering of value-added costs for state-of-the-art wafering techniques are assessed. From the best experimental results to date, a projection was made to identify those parts of each system which need to be developed in order to meet or improve upon the value-added cost reduction necessary for $0.70/Wp photovoltaics modules.

  8. Boron implant profile variation across a single wafer due to electrostatic scanning

    International Nuclear Information System (INIS)

    Park, Changhae; Klein, K.M.; Tasch, A.F.; Simonton, R.B.; Kamenitsa, D.E.; Novak, S.

    1991-01-01

    The implanted impurity profile variation across a wafer due to an electrostatic scanning system has been studied for boron implants into (100) silicon wafers. The variation of the actual tilt and rotation angles across a wafer has been precisely determined for the implanter used in this study. The sensitivity of the impurity profiles to this angular variation has been studied through both a theoretical prediction based on an improved calculation of critical angles for channeling, and a qualitative analysis using the thermal wave measurement technique. A quantitative study of the profile variation across a wafer has also been performed using extensive secondary ion mass spectrometry (SIMS) profile measurements. For the energy range (15-80 keV) and angle range (0-10deg tilt angle, 0-360deg rotation angle) used in this study, we have identified the ranges of tilt and rotation angles that should be used for minimum channeling and minimum profile variation. (orig.)

  9. Vertically Conductive Single-Crystal SiC-Based Bragg Reflector Grown on Si Wafer

    Science.gov (United States)

    Massoubre, David; Wang, Li; Hold, Leonie; Fernandes, Alanna; Chai, Jessica; Dimitrijev, Sima; Iacopi, Alan

    2015-11-01

    Single-crystal silicon carbide (SiC) thin-films on silicon (Si) were used for the fabrication and characterization of electrically conductive distributed Bragg reflectors (DBRs) on 100 mm Si wafers. The DBRs, each composed of 3 alternating layers of SiC and Al(Ga)N grown on Si substrates, show high wafer uniformity with a typical maximum reflectance of 54% in the blue spectrum and a stopband (at 80% maximum reflectance) as large as 100 nm. Furthermore, high vertical electrical conduction is also demonstrated resulting to a density of current exceeding 70 A/cm2 above 1.5 V. Such SiC/III-N DBRs with high thermal and electrical conductivities could be used as pseudo-substrate to enhance the efficiency of SiC-based and GaN-based optoelectronic devices on large Si wafers.

  10. Wafer-Scale Leaning Silver Nanopillars for Molecular Detection at Ultra-Low Concentrations

    DEFF Research Database (Denmark)

    Wu, Kaiyu; Rindzevicius, Tomas; Schmidt, Michael Stenbæk

    2015-01-01

    Wafer-scale surface-enhanced Raman scattering (SERS) substrates fabricated using maskless lithography are important for scalable production targets. Large-area, leaning silver-capped silicon nanopillar (Ag NP) structures suitable for SERS molecular detection at extremely low analyte concentrations...

  11. Low temperature sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, V.L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    1994-01-01

    A new technique, at temperatures of 150°C or 450°C, that provides planarization after a very deep etching step in silicon is presented. Resist spinning and layer patterning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique

  12. Investigation of optical properties of benzocyclobutene wafer bonding layer used for 3D interconnects via infrared spectroscopic ellipsometry

    International Nuclear Information System (INIS)

    Kamineni, Vimal K.; Singh, Pratibha; Kong, LayWai; Hudnall, John; Qureshi, Jamal; Taylor, Chris; Rudack, Andy; Arkalgud, Sitaram; Diebold, Alain C.

    2011-01-01

    Benzocyclobutene (BCB) used for bonding silicon wafers to enable 3D interconnect technology is characterized using spectroscopic ellipsometry (SE). SE is a non-destructive technique that has been used to characterize the thickness and dielectric properties of BCB. The infrared (IR) absorption spectrum was used to calculate the percentage of curing of BCB on 300 mm bare and bonded wafers. The percentage of curing in BCB is a key parameter that impacts the bond strength and bond quality. This study presents the potential application of IRSE for measurements on bonded wafers to characterize the chemical information, curing percentage, bond quality and thickness of the BCB bonding layer. One of the key issues in the process development and characterization of BCB bonding for 3D interconnects of 300 mm wafers is the presence of dendrites and voids between the bonded wafers. The presence of dendrites and voids was identified by using scanning acoustic microscopy (SAM) and imaged by scanning electron microscope (SEM).

  13. Investigation of optical properties of benzocyclobutene wafer bonding layer used for 3D interconnects via infrared spectroscopic ellipsometry

    Energy Technology Data Exchange (ETDEWEB)

    Kamineni, Vimal K., E-mail: vkamineni@uamail.albany.ed [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); Singh, Pratibha [GLOBALFOUNDRIES Inc., Albany, NY 12203 (United States); SEMATECH, Albany, NY 12203 (United States); Kong, LayWai [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); Hudnall, John [SEMATECH, Albany, NY 12203 (United States); Qureshi, Jamal [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States); SEMATECH, Albany, NY 12203 (United States); Taylor, Chris [SEMATECH, Albany, NY 12203 (United States); Hewlett-Packard Company, Corvallis, OR (United States); Rudack, Andy; Arkalgud, Sitaram [SEMATECH, Albany, NY 12203 (United States); Diebold, Alain C. [College of Nanoscale Science and Engineering, University at Albany, Albany, NY 12203 (United States)

    2011-02-28

    Benzocyclobutene (BCB) used for bonding silicon wafers to enable 3D interconnect technology is characterized using spectroscopic ellipsometry (SE). SE is a non-destructive technique that has been used to characterize the thickness and dielectric properties of BCB. The infrared (IR) absorption spectrum was used to calculate the percentage of curing of BCB on 300 mm bare and bonded wafers. The percentage of curing in BCB is a key parameter that impacts the bond strength and bond quality. This study presents the potential application of IRSE for measurements on bonded wafers to characterize the chemical information, curing percentage, bond quality and thickness of the BCB bonding layer. One of the key issues in the process development and characterization of BCB bonding for 3D interconnects of 300 mm wafers is the presence of dendrites and voids between the bonded wafers. The presence of dendrites and voids was identified by using scanning acoustic microscopy (SAM) and imaged by scanning electron microscope (SEM).

  14. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  15. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  16. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  17. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  18. Split-Capacitance and Conductance-Frequency Characteristics of SOI Wafers in Pseudo-MOSFET Configuration

    KAUST Repository

    Pirro, Luca

    2015-09-01

    Recent experimental results have demonstrated the possibility of characterizing silicon-on-insulator (SOI) wafers through split C-V measurements in the pseudo-MOSFET configuration. This paper analyzes the capacitance and conductance versus frequency characteristics. We discuss the conditions under which it is possible to extract interface trap density in bare SOI wafers. The results indicate, through both measurements and simulations, that the signature due to interface trap density is present in small-area samples, but is masked by the RC response of the channel in regular, large-area ones, making the extraction in standard samples problematic. © 1963-2012 IEEE.

  19. Wafer-scale growth of highly textured piezoelectric thin films by pulsed laser deposition for micro-scale sensors and actuators

    NARCIS (Netherlands)

    Nguyen, M. D.; Tiggelaar, R.; Aukes, Thomas; Rijnders, G.; Roelof, G.

    2017-01-01

    Piezoelectric lead-zirconate-Titanate (PZT) thin films were deposited on 4-inch (111)Pt/Ti/SiO2/Si(001) wafers using large-Area pulsed laser deposition (PLD). This study was focused on the homogeneity in film thickness, microstructure, ferroelectric and piezoelectric properties of PZT thin films.

  20. Recycling of silicon: from industrial waste to biocompatible nanoparticles for nanomedicine

    Science.gov (United States)

    Kozlov, N. K.; Natashina, U. A.; Tamarov, K. P.; Gongalsky, M. B.; Solovyev, V. V.; Kudryavtsev, A. A.; Sivakov, V.; Osminkina, L. A.

    2017-09-01

    The formation of photoluminescent porous silicon (PSi) nanoparticles (NPs) is usually based on an expensive semiconductor grade wafers technology. Here, we report a low-cost method of PSi NPs synthesis from the industrial silicon waste remained after the wafer production. The proposed method is based on metal-assisted wet-chemical etching (MACE) of the silicon surface of cm-sized metallurgical grade silicon stones which leads to a nanostructuring of the surface due to an anisotropic etching, with subsequent ultrasound fracturing in water. The obtained PSi NPs exhibit bright red room temperature photoluminescence (PL) and demonstrate similar microstructure and physical characteristics in comparison with the nanoparticles synthesized from semiconductor grade Si wafers. PSi NPs prepared from metallurgical grade silicon stones, similar to silicon NPs synthesized from high purity silicon wafer, show low toxicity to biological objects that open the possibility of using such type of NPs in nanomedicine.

  1. Microstructure and Mechanical Aspects of Multicrystalline Silicon Solar Cells

    NARCIS (Netherlands)

    Popovich, V.A.

    2013-01-01

    Due to pressure from the photovoltaic industry to decrease the cost of solar cell production, there is a tendency to reduce the thickness of silicon wafers. Unfortunately, wafers contain defects created by the various processing steps involved in solar cell production, which significantly reduce the

  2. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  3. 1366 Project Silicon: Reclaiming US Silicon PV Leadership

    Energy Technology Data Exchange (ETDEWEB)

    Lorenz, Adam [1366 Technologies, Bedford, MA (United States)

    2016-02-16

    1366 Technologies’ Project Silicon addresses two of the major goals of the DOE’s PV Manufacturing Initiative Part 2 program: 1) How to reclaim a strong silicon PV manufacturing presence and; 2) How to lower the levelized cost of electricity (“LCOE”) for solar to $0.05-$0.07/kWh, enabling wide-scale U.S. market adoption. To achieve these two goals, US companies must commercialize disruptive, high-value technologies that are capable of rapid scaling, defensible from foreign competition, and suited for US manufacturing. These are the aims of 1366 Technologies Direct Wafer ™ process. The research conducted during Project Silicon led to the first industrial scaling of 1366’s Direct Wafer™ process – an innovative, US-friendly (efficient, low-labor content) manufacturing process that destroys the main cost barrier limiting silicon PV cost-reductions: the 35-year-old grand challenge of making quality wafers (40% of the cost of modules) without the cost and waste of sawing. The SunPath program made it possible for 1366 Technologies to build its demonstration factory, a key and critical step in the Company’s evolution. The demonstration factory allowed 1366 to build every step of the process flow at production size, eliminating potential risk and ensuring the success of the Company’s subsequent scaling for a 1 GW factory to be constructed in Western New York in 2016 and 2017. Moreover, the commercial viability of the Direct Wafer process and its resulting wafers were established as 1366 formed key strategic partnerships, gained entry into the $8B/year multi-Si wafer market, and installed modules featuring Direct Wafer products – the veritable proving grounds for the technology. The program also contributed to the development of three Generation 3 Direct Wafer furnaces. These furnaces are the platform for copying intelligently and preparing our supply chain – large-scale expansion will not require a bigger machine but more machines. SunPath filled the

  4. Internal alignement of the BABAR silicon vertex tracking detector

    CERN Document Server

    Brown, D; Roberts, D

    2007-01-01

    The BABAR Silicon Vertex Tracker (SVT ) is a five-layer double-sided silicon detector designed to provide precise measurements of the position and direction of primary tracks, and to fully reconstruct low-momentum tracks produced in e+e¡ collisions at the PEP-II asymmetric collider at Stanford Linear Accelerator Center. This paper describes the design, implementation, performance and validation of the local alignment procedure used to determine the relative positions and orientations of the 340 Silicon Vertex Trackerwafers. This procedure uses a tuned mix of lab-bench measurements and complementary in-situ experimental data to control systematic distortions. Wafer positions and orientations are determined by minimizing a Â2 computed using these data for each wafer individually, iterating to account for between-wafer correlations. A correction for aplanar distortions of the silicon wafers is measured and applied. The net effect of residual mis-alignments on relevant physical variables evaluated in special co...

  5. Evaluation of water based intelligent fluids for resist stripping in single wafer cleaning tools

    Science.gov (United States)

    Rudolph, Matthias; Esche, Silvio; Hohle, Christoph; Schumann, Dirk; Steinke, Philipp; Thrun, Xaver; von Sonntag, Justus

    2016-03-01

    The application of phasefluid based intelligent fluids® in the field of photoresist stripping was studied. Due to their highly dynamic inner structure, phasefluids penetrate into the polymer network of photoresists and small gaps between resist layer and substrate and lift off the material from the surface. These non-aggressive stripping fluids were investigated regarding their efficiency in various resist stripping applications including initial results on copper metallization. Furthermore intelligent fluids® have been evaluated on an industry standard high volume single wafer cleaner. A baseline process on 300 mm wafers has been developed and characterized in terms of metallic and ionic impurities and defect level. Finally a general proof of concept for removal of positive tone resist from 300 mm silicon wafers is demonstrated.

  6. Development of ultra-low impedance Through-wafer Micro-vias

    Energy Technology Data Exchange (ETDEWEB)

    Finkbeiner, F.M. E-mail: fmf@lheapop.gsfc.nasa.gov; Adams, C.; Apodaca, E.; Chervenak, J.A.; Fischer, J.; Doan, N.; Li, M.J.; Stahle, C.K.; Brekosky, R.P.; Bandler, S.R.; Figueroa-Feliciano, E.; Lindeman, M.A.; Kelley, R.L.; Saab, T.; Talley, D.J

    2004-03-11

    Concurrent with our microcalorimeter array fabrication for Constellation-X technology development, we are developing ultra-low impedance Through-Wafer Micro-Vias (TWMV) as electrical interconnects for superconducting circuits. The TWMV will enable the electrical contacts of each detector to be routed to contacts on the backside of the array. There, they can be bump-bonded to a wiring fan-out board which interfaces with the front-end Superconducting Quantum Interference Device readout. We are concentrating our developmental efforts on ultra-low impedance copper and superconducting aluminum TWMV in 300-400 micron thick silicon wafers. For both schemes, a periodic pulse-reverse electroplating process is used to fill or coat micron-scale through-wafer holes of aspect ratios up to 20. Here we discuss the design, fabrication process, and recent electro-mechanical test results of Al and Cu TWMV at room and cryogenic temperatures.

  7. CMOS-analogous wafer-scale nanotube-on-insulator approach for submicrometer devices and integrated circuits using aligned nanotubes.

    Science.gov (United States)

    Ryu, Koungmin; Badmaev, Alexander; Wang, Chuan; Lin, Albert; Patil, Nishant; Gomez, Lewis; Kumar, Akshay; Mitra, Subhasish; Wong, H-S Philip; Zhou, Chongwu

    2009-01-01

    Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO(2) wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5 mum, with high current density approximately 20 muA/mum and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain approximately 5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

  8. Photon response of silicon diode neutron detectors

    International Nuclear Information System (INIS)

    McCall, R.C.; Jenkins, T.M.; Oliver, G.D. Jr.

    1976-07-01

    The photon response of silicon diode neutron detectors was studied to solve the problem on detecting neutrons in the presence of high energy photons at accelerator neutron sources. For the experiment Si diodes, Si discs, and moderated activation foil detectors were used. The moderated activation foil detector consisted of a commercial moderator and indium foils 2'' in diameter and approximately 2.7 grams each. The moderator is a cylinder of low-density polyethylene 6 1 / 4 '' in diameter by 6 1 / 16 '' long covered with 0.020'' of cadmium. Neutrons are detected by the reaction 115 In (n,γ) 116 In(T/sub 1 / 2 / = 54 min). Photons cannot be detected directly but photoneutrons produced in the moderator assembly can cause a photon response. The Si discs were thin slices of single-crystal Si about 1.4 mils thick and 1'' in diameter which were used as activation detectors, subsequently being counted on a thin-window pancake G.M. counter. The Si diode fast neutron dosimeter 5422, manufactured by AB Atomenergi in Studsvik, Sweden, consists of a superdoped silicon wafer with a base width of 0.050 inches between two silver contacts coated with 2 mm of epoxy. For this experiment, the technique of measuring the percent change of voltage versus dose was used. Good precision was obtained using both unirradiated and preirradiated diodes. All diodes, calibrated against 252 CF in air,were read out 48 hours after irradiation to account for any room temperature annealing. Results are presented and discussed

  9. Single crystalline silicon solar cells with rib structure

    Directory of Open Access Journals (Sweden)

    Shuhei Yoshiba

    2017-02-01

    Full Text Available To improve the conversion efficiency of Si solar cells, we have developed a thin Si wafer-based solar cell that uses a rib structure. The open-circuit voltage of a solar cell is known to increase with deceasing wafer thickness if the cell is adequately passivated. However, it is not easy to handle very thin wafers because they are brittle and are subject to warpage. We fabricated a lattice-shaped rib structure on the rear side of a thin Si wafer to improve the wafer’s strength. A silicon nitride film was deposited on the Si wafer surface and patterned to form a mask to fabricate the lattice-shaped rib, and the wafer was then etched using KOH to reduce the thickness of the active area, except for the rib region. Using this structure in a Si heterojunction cell, we demonstrated that a high open-circuit voltage (VOC could be obtained by thinning the wafer without sacrificing its strength. A wafer with thickness of 30 μm was prepared easily using this structure. We then fabricated Si heterojunction solar cells using these rib wafers, and measured their implied VOC as a function of wafer thickness. The measured values were compared with device simulation results, and we found that the measured VOC agrees well with the simulated results. To optimize the rib and cell design, we also performed device simulations using various wafer thicknesses and rib dimensions.

  10. GeSn-on-insulator substrate formed by direct wafer bonding

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Lee, Kwang Hong; Wang, Bing [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); Bao, Shuyu [Low Energy Electronic Systems (LEES), Singapore MIT Alliance for Research and Technology (SMART), 1 CREATE Way, #10-01 CREATE Tower, Singapore 138602 (Singapore); School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore); Tan, Chuan Seng [School of Electrical and Electronic Engineering, Nanyang Technological University, 50 Nanyang Avenue, Singapore 639798 (Singapore)

    2016-07-11

    GeSn-on-insulator (GeSnOI) on Silicon (Si) substrate was realized using direct wafer bonding technique. This process involves the growth of Ge{sub 1-x}Sn{sub x} layer on a first Si (001) substrate (donor wafer) followed by the deposition of SiO{sub 2} on Ge{sub 1-x}Sn{sub x}, the bonding of the donor wafer to a second Si (001) substrate (handle wafer), and removal of the Si donor wafer. The GeSnOI material quality is investigated using high-resolution transmission electron microscopy, high-resolution X-ray diffraction (HRXRD), atomic-force microscopy, Raman spectroscopy, and spectroscopic ellipsometry. The Ge{sub 1-x}Sn{sub x} layer on GeSnOI substrate has a surface roughness of 1.90 nm, which is higher than that of the original Ge{sub 1-x}Sn{sub x} epilayer before transfer (surface roughness is 0.528 nm). The compressive strain of the Ge{sub 1-x}Sn{sub x} film in the GeSnOI is as low as 0.10% as confirmed using HRXRD and Raman spectroscopy.

  11. Study of irradiation induced defects in silicon

    International Nuclear Information System (INIS)

    Pal, Gayatri; Sebastian, K.C.; Somayajulu, D.R.S.; Chintalapudi, S.N.

    2000-01-01

    Pure high resistivity (6000 ohm-cm) silicon wafers were recoil implanted with 1.8 MeV 111 In ions. As-irradiated wafers showed a 13 MHz quadrupole interaction frequency, which was not observed earlier. The annealing behaviour of these defects in the implanted wafers was studied between room temperature and 1073 K. At different annealing temperatures two more interaction frequencies corresponding to defect complexes D2 and D3 are observed. Even though the experimental conditions were different, these are identical to the earlier reported ones. Based on an empirical point charge model calculation, an attempt is made to identify the configuration of these defect complexes. (author)

  12. Modelling deformation and fracture in confectionery wafers

    Science.gov (United States)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John

    2015-01-01

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  13. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  14. Switchable static friction of piezoelectric composite-silicon wafer contacts

    NARCIS (Netherlands)

    Ende, D.A. van den; Fischer, H.R.; Groen, W.A.; Zwaag, S. van der

    2013-01-01

    The meso-scale surface roughness of piezoelectric fiber composites can be manipulated by applying an electric field to a piezocomposite with a polished surface. In the absence of an applied voltage, the tips of the embedded piezoelectric ceramic fibers are below the surface of the piezocomposite and

  15. Improvement of multicrystalline silicon wafer solar cells by post ...

    Indian Academy of Sciences (India)

    Administrator

    microelectronic and optoelectronic devices (Ino et al. 1994). It is used as gate dielectric in MOS components. (Tsividis 1999) and also applied in the fabrication of micro- electromechanical systems (MEMS) (Kaushik et al. 2005). In photovoltaic field, SiN has the function of defects passivation (Sopori et al 1996) and light anti-.

  16. New overlay measurement technique with an i-line stepper using embedded standard field image alignment marks for wafer bonding applications

    Science.gov (United States)

    Kulse, P.; Sasai, K.; Schulz, K.; Wietstruck, M.

    2017-06-01

    In the last decades the semiconductor technology has been driven by Moore's law leading to high performance CMOS technologies with feature sizes of less than 10 nm [1]. It has been pointed out that not only scaling but also the integration of novel components and technology modules into CMOS/BiCMOS technologies is becoming more attractive to realize smart and miniaturized systems [2]. Driven by new applications in the area of communication, health and automation, new components and technology modules such as BiCMOS embedded RF-MEMS, high-Q passives, Sibased microfluidics and InP-SiGe BiCMOS heterointegration have been demonstrated [3-6]. In contrast to standard VLSI processes fabricated on front side of the silicon wafer, these new technology modules require addition backside processing of the wafer; thus an accurate alignment between the front and backside of the wafer is mandatory. In previous work an advanced back to front side alignment technique and implementation into IHP's 0.25/0.13 μm high performance SiGe:C BiCMOS backside process module has been presented [7]. The developed technique enables a high resolution and accurate lithography on the backside of BiCMOS wafer for additional backside processing. In addition to the aforementioned back side process technologies, new applications like Through-Silicon Vias (TSV) for interposers and advanced substrate technologies for 3D heterogeneous integration demand not only single wafer fabrication but also processing of wafer stacks provided by temporary and permanent wafer bonding [8]. Therefore, the available overlay measurement techniques are not suitable if overlay and alignment marks are realized at the bonding interface of a wafer stack which consists of both a silicon device and a silicon carrier wafer. The former used EVG 40NT automated overlay measurement system, which use two opposite positioned microscopes inspecting simultaneous the wafer back and front side, is not capable measuring embedded overlay

  17. Nanodiamond resonators fabricated on 8″ Si substrates using adhesive wafer bonding

    Science.gov (United States)

    Lebedev, V.; Lisec, T.; Yoshikawa, T.; Reusch, M.; Iankov, D.; Giese, C.; Žukauskaitė, A.; Cimalla, V.; Ambacher, O.

    2017-06-01

    In this work, the adhesive wafer bonding of diamond thin films onto 8″ silicon substrates is reported. In order to characterize bonded nano-crystalline diamond layers, vibrometry and interferometry studies of micro-fabricated flexural beam and disk resonators were carried out. In particular, surface topology along with resonant frequencies, eigenmodes and mechanical quality factors were recorded and analyzed in order to obtain physical parameters of the transferred films. The vibration properties of the bonded resonators were compared to those fabricated directly on 3″ silicon substrates.

  18. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  19. Wafer-scale fabrication of uniform Si nanowire arrays using the Si wafer with UV/Ozone pretreatment

    International Nuclear Information System (INIS)

    Bai, Fan; Li, Meicheng; Huang, Rui; Yu, Yue; Gu, Tiansheng; Chen, Zhao; Fan, Huiyang; Jiang, Bing

    2013-01-01

    The electroless etching technique combined with the process of UV/Ozone pretreatment is presented for wafer-scale fabrication of the silicon nanowire (SiNW) arrays. The high-level uniformity of the SiNW arrays is estimated by the value below 0.2 of the relative standard deviation of the reflection spectra on the 4-in. wafer. Influence of the UV/Ozone pretreatment on the formation of SiNW arrays is investigated. It is seen that a very thin SiO 2 produced by the UV/Ozone pretreatment improves the uniform nucleation of Ag nanoparticles (NPs) on the Si surface because of the effective surface passivation. Meanwhile, the SiO 2 located among the adjacent Ag NPs can obstruct the assimilation growth of Ag NPs, facilitating the deposition of the uniform and dense Ag NPs catalysts, which induces the formation of the SiNW arrays with good uniformity and high filling ratio. Furthermore, the remarkable antireflective and hydrophobic properties are observed for the SiNW arrays which display great potential in self-cleaning antireflection applications

  20. SCIL nanoimprint solutions: high-volume soft NIL for wafer scale sub-10nm resolution

    Science.gov (United States)

    Voorkamp, R.; Verschuuren, M. A.; van Brakel, R.

    2016-10-01

    Nano-patterning materials and surfaces can add unique functionalities and properties which cannot be obtained in bulk or micro-structured materials. Examples range from hetro-epitaxy of semiconductor nano-wires to guiding cell expression and growth on medical implants. [1] Due to the cost and throughput requirements conventional nano-patterning techniques such as deep UV lithography (cost and flat substrate demands) and electron-beam lithography (cost, throughput) are not an option. Self-assembly techniques are being considered for IC manufacturing, but require nano-sized guiding patterns, which have to be fabricated in any case.[2] Additionally, the self-assembly process is highly sensitive to the environment and layer thickness, which is difficult to control on non-flat surfaces such as PV silicon wafers or III/V substrates. Laser interference lithography can achieve wafer scale periodic patterns, but is limited by the throughput due to intensity of the laser at the pinhole and only regular patterns are possible where the pattern fill fraction cannot be chosen freely due to the interference condition.[3] Nanoimprint lithography (NIL) is a promising technology for the cost effective fabrication of sub-micron and nano-patterns on large areas. The challenges for NIL are related to the technique being a contact method where a stamp which holds the patterns is required to be brought into intimate contact with the surface of the product. In NIL a strong distinction is made between the type of stamp used, either rigid or soft. Rigid stamps are made from patterned silicon, silica or plastic foils and are capable of sub-10nm resolution and wafer scale patterning. All these materials behave similar at the micro- to nm scale and require high pressures (5 - 50 Bar) to enable conformal contact to be made on wafer scales. Real world conditions such as substrate bow and particle contaminants complicate the use of rigid stamps for wafer scale areas, reducing stamp lifetime and

  1. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  2. Flexible Thermoelectric Generators on Silicon Fabric

    KAUST Repository

    Sevilla, Galo T.

    2012-11-01

    In this work, the development of a Thermoelectric Generator on Flexible Silicon Fabric is explored to extend silicon electronics for flexible platforms. Low cost, easily deployable plastic based flexible electronics are of great interest for smart textile, wearable electronics and many other exciting applications. However, low thermal budget processing and fundamentally limited electron mobility hinders its potential to be competitive with well established and highly developed silicon technology. The use of silicon in flexible electronics involve expensive and abrasive materials and processes. In this work, high performance flexible thermoelectric energy harvesters are demonstrated from low cost bulk silicon (100) wafers. The fabrication of the micro- harvesters was done using existing silicon processes on silicon (100) and then peeled them off from the original substrate leaving it for reuse. Peeled off silicon has 3.6% thickness of bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. The demonstrated generic batch processing shows a pragmatic way of peeling off a whole silicon circuitry after conventional fabrication on bulk silicon wafers for extremely deformable high performance integrated electronics. In summary, by using a novel, low cost process, this work has successfully integrated existing and highly developed fabrication techniques to introduce a flexible energy harvester for sustainable applications.

  3. Low temperature spalling of silicon: A crack propagation study

    Energy Technology Data Exchange (ETDEWEB)

    Bertoni, Mariana; Uberg Naerland, Tine; Stoddard, Nathan; Guimera Coll, Pablo

    2017-06-08

    Spalling is a promising kerfless method for cutting thin silicon wafers while doubling the yield of a silicon ingot. The main obstacle in this technology is the high total thickness variation of the spalled wafers, often as high as 100% of the wafer thickness. It has been suggested before that a strong correlation exists between low crack velocities and a smooth surface, but this correlation has never been shown during a spalling process in silicon. The reason lies in the challenge associated to measuring such velocities. In this contribution, we present a new approach to assess, in real time, the crack velocity as it propagates during a low temperature spalling process. Understanding the relationship between crack velocity and surface roughness during spalling can pave the way to attain full control on the surface quality of the spalled wafer.

  4. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  5. Floating Silicon Method

    Energy Technology Data Exchange (ETDEWEB)

    Kellerman, Peter

    2013-12-21

    The Floating Silicon Method (FSM) project at Applied Materials (formerly Varian Semiconductor Equipment Associates), has been funded, in part, by the DOE under a “Photovoltaic Supply Chain and Cross Cutting Technologies” grant (number DE-EE0000595) for the past four years. The original intent of the project was to develop the FSM process from concept to a commercially viable tool. This new manufacturing equipment would support the photovoltaic industry in following ways: eliminate kerf losses and the consumable costs associated with wafer sawing, allow optimal photovoltaic efficiency by producing high-quality silicon sheets, reduce the cost of assembling photovoltaic modules by creating large-area silicon cells which are free of micro-cracks, and would be a drop-in replacement in existing high efficiency cell production process thereby allowing rapid fan-out into the industry.

  6. Analysis Of Factors Affecting Gravity-Induced Deflection For Large And Thin Wafers In Flatness Measurement Using Three-Point-Support Method

    Directory of Open Access Journals (Sweden)

    Liu Haijun

    2015-12-01

    Full Text Available Accurate flatness measurement of silicon wafers is affected greatly by the gravity-induced deflection (GID of the wafers, especially for large and thin wafers. The three-point-support method is a preferred method for the measurement, in which the GID uniquely determined by the positions of the supports could be calculated and subtracted. The accurate calculation of GID is affected by the initial stress of the wafer and the positioning errors of the supports. In this paper, a finite element model (FEM including the effect of initial stress was developed to calculate GID. The influence of the initial stress of the wafer on GID calculation was investigated and verified by experiment. A systematic study of the effects of positioning errors of the support ball and the wafer on GID calculation was conducted. The results showed that the effect of the initial stress could not be neglected for ground wafers. The wafer positioning error and the circumferential error of the support were the most influential factors while the effect of the vertical positioning error was negligible in GID calculation.

  7. Fabrication of a mechanically aligned single-wafer MEMS turbine with turbocharger

    Science.gov (United States)

    Pelekies, S. O.; Schuhmann, T.; Gardner, W. G.; Camacho, A.; Protz, J. M.

    2010-10-01

    We describe the fabrication of a turbocharged, microelectromechanical system (MEMS) turbine. The turbine will be part of a standalone power unit and includes extra layers to connect the turbine to a generator. The project goal is to demonstrate the successful combination of several features, namely: silicon fusion bonding (SFB), a micro turbocharger [2], two rotors, mechanical alignment between two wafers [1], and the use of only one 5" silicon wafer. The dimension of the actual turbine casing will be 14mm. The turbine rotor will have a diameter of 8mm. Given these dimensions, MEMS processes are an adequate way to fabricate the device, but it will be necessary to stack up seven different layers to build the turbine, as it is not possible to construct it out of one thick wafer. SFB will be used for bonding because it permits the great precision necessary for high quality alignment. Yet a more precise alignment will be necessary between the layers that contain the turbine rotor, to decrease imbalance and guarantee operation at a very high rpm. To achieve these tight tolerances, a mechanical alignment feature announced by Liudi Jiang [1] is used. The alignment accuracy is expected to be around 200nm. Despite the fact that the turbine consists of multiple layers, it will be fabricated on only one silicon-on-insulator (SOI) wafer. As a result, all layers are exposed to the same process flow. The fabrication process includes MEMS technology as photolithography, nine deep reactive ion etching (DRIE) steps, and six SFB operations. A total of 14 masks are necessary for the fabrication.

  8. Wafer fab mask qualification techniques and limitations

    Science.gov (United States)

    Poock, Andre; Maelzer, Stephanie; Spence, Chris; Tabery, Cyrus; Lang, Michael; Schnasse, Guido; Peikert, Milko; Bhattacharyya, Kaustuve

    2006-10-01

    Mask inspection and qualification is a must for wafer fabs to ensure and guarantee high and stable yields. Single defect events can easily cause a million dollar loss through a defect duplicating onto the wafer. Several techniques and methods for mask qualification within a wafer fab are known but not all of them are neither used nor understood regarding their limitations. Increasing effort on existing tool platforms is necessary to detect the defects of interest which are at the limit of the tools specification - On the other hand next generation tools are very sensitive and therefore consume only a negligible amount of time for recipe optimization. Knowing the limits of each inspection tool helps to balance between effort and benefit. Masks with programmed defects of 90nm and 65nm design rule were used in order to compare the different available inspection techniques. During the course of this technical work, the authors concentrate mainly on two inspection techniques. The first one inspects the reticle itself using KLA-Tencor's SLF27 (TeraStar) and SL536 (TeraScan) tools. As the reticle gets inspected itself this is the so called "direct" mask defect inspection. The second inspection technique discussed is the "indirect" mask defect inspection which consists of printing the pattern on a blank wafer and use KLA-Tencor's bright-field wafer inspection tool (2xxx series) to inspect the wafer. Data of this work will include description of the techniques, inspection results, defect maps, sensitivity analysis, effort estimation as well as limitations for both techniques for the used design rule.

  9. Correction of Dopant Concentration Fluctuation Effects in Silicon Drift Detectors

    CERN Document Server

    Nouais, D; Bonvicini, V; Cerello, P G; Crescio, E; Giubellino, P; Hernández-Montoya, R; Kolojvari, A A; Montaño-Zetina, L M; Nilsen, B S; Piemonte, C; Rachevsky, A; Tosello, F; Vacchi, A; Wheadon, R

    2001-01-01

    Dopant fluctuations in silicon wafers are responsible for systematic errors in the determination of the particle crossing point in silicon drift detectors. In this paper, we report on the first large scale measurement of this effect by means of a particle beam. A significant improvement of the anodic resolution has been obtained by correcting for these systematic deviations.

  10. Light management in thin-film silicon solar cells

    NARCIS (Netherlands)

    Isabella, O.

    2013-01-01

    Solar energy can fulfil mankind’s energy needs and secure a more balanced distribution of primary sources of energy. Wafer-based and thin-film silicon solar cells dominate todays’ photovoltaic market because silicon is a non-toxic and abundant material and high conversion efficiencies are achieved

  11. Design, fabrication, testing and packaging of a silicon ...

    Indian Academy of Sciences (India)

    In this paper, we describe the fabrication, wafer level test- ing and packaging of a silicon on glass based RF MEMS switch fabricated using DRIE. The device is a SPST direct contact series switch. The silicon on glass fabrication process has been suc- cessfully adapted by a number of groups to fabricate MEMS devices such ...

  12. The impact of silicon feedstock on the PV module cost

    NARCIS (Netherlands)

    del Coso, G.; del Cañizo, C.; Sinke, W.C.

    2010-01-01

    The impact of the use of new (solar grade) silicon feedstock materials on the manufacturing cost of wafer-based crystalline silicon photovoltaic modules is analyzed considering effects of material cost, efficiency of utilisation, and quality. Calculations based on data provided by European industry

  13. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  14. A novel kerf-free wafering process combining stress-induced spalling and low energy hydrogen implantation

    Energy Technology Data Exchange (ETDEWEB)

    Pingault, Timothee; Pokam-Kuisseu, Pauline Sylvia; Ntsoenzok, Esidor [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Blondeau, Jean-Philippe [CEMTHI - CNRS, Site Cyclotron, 3 A rue de la Ferollerie, 45071 Orleans (France); Universite d' Orleans, Chateau de la Source, 45100 Orleans (France); Ulyashin, Alexander [SINTEF, Forskningsveien 1, 0314 Oslo (Norway); Labrim, Hicham; Belhorma, Bouchra [CNESTEN, B.P. 1382 R.P., 10001 Rabat (Morocco)

    2016-12-15

    In this work, we studied the potential use of low-energy hydrogen implantation as a guide for the stress-induced cleavage. Low-energy, high fluence hydrogen implantation in silicon leads, in the right stiffening conditions, to the detachment of a thin layer, around a few hundreds nm thick, of monocrystalline silicon. We implanted monocrystalline silicon wafers with low-energy hydrogen, and then glued them on a cheap metal layer. Upon cooling down, the stress induced by the stressor layers (hardened glue and metal) leads to the detachment of a thin silicon layer, which thickness is determined by the implantation energy. We were then able to clearly demonstrate that, as expected, hydrogen oversaturation layer is very efficient to guide the stress. Using such process, thin silicon layers of around 710 nm-thick were successfully detached from low-energy implanted silicon wafers. Such layers can be used for the growth of very good quality monocrystalline silicon of around 50 μm-thick or less. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  15. A new cleaning process for the metallic contaminants on a post-CMP wafer's surface

    International Nuclear Information System (INIS)

    Gao Baohong; Liu Yuling; Wang Chenwei; Wang Shengli; Zhou Qiang; Tan Baimei; Zhu Yadong

    2010-01-01

    This paper presents a new cleaning process using boron-doped diamond (BDD) film anode electrochemical oxidation for metallic contaminants on polished silicon wafer surfaces. The BDD film anode electrochemical oxidation can efficiently prepare pyrophosphate peroxide, pyrophosphate peroxide can oxidize organic contaminants, and pyrophosphate peroxide is deoxidized into pyrophosphate. Pyrophosphate, a good complexing agent, can form a metal complex, which is a structure consisting of a copper ion, bonded to a surrounding array of two pyrophosphate anions. Three polished wafers were immersed in the 0.01 mol/L CuSO 4 solution for 2 h in order to make comparative experiments. The first one was cleaned by pyrophosphate peroxide, the second by RCA (Radio Corporation of America) cleaning, and the third by deionized (DI) water. The XPS measurement result shows that the metallic contaminants on wafers cleaned by the RCA method and by pyrophosphate peroxide is less than the XPS detection limits of 1 ppm. And the wafer's surface cleaned by pyrophosphate peroxide is more efficient in removing organic carbon residues than RCA cleaning. Therefore, BDD film anode electrochemical oxidation can be used for microelectronics cleaning, and it can effectively remove organic contaminants and metallic contaminants in one step. It also achieves energy saving and environmental protection. (semiconductor technology)

  16. The preparation and thermoelectric properties of molten salt electrodeposited boron wafers

    International Nuclear Information System (INIS)

    Kumashiro, Y.; Ozaki, S.; Sato, K.; Kataoka, Y.; Hirata, K.; Yokoyama, T.; Nagatani, S.; Kajiyama, K.

    2004-01-01

    We have prepared electrodeposited boron wafer by molten salts with KBF 4 -KF at 680 deg. C using graphite crucible for anode and silicon wafer and nickel plate for cathodes. Experiments were performed by various molar ratios KBF 4 /KF and current densities. Amorphous p-type boron wafers with purity 87% was deposited on nickel plate for 1 h. Thermal diffusivity by ring-flash method and heat capacity by DSC method produced thermal conductivity showing amorphous behavior in the entire temperature range. The systematical results on thermoelectric properties were obtained for the wafers prepared with KBF 4 -KF (66-34 mol%) under various current densities in the range 1-2 A/cm 2 . The temperature dependencies of electrical conductivity showed thermal activated type with activation energy of 0.5 eV. Thermoelectric power tended to increase with increasing temperature up to high temperatures with high values of (1-10) mV/K. Thermoelectric figure-of-merit was 10 -4 /K at high temperatures. Estimated efficiency of thermoelectric energy conversion would be calculated to be 4-5%

  17. Silicon microphotonic waveguides

    International Nuclear Information System (INIS)

    Ta'eed, V.; Steel, M.J.; Grillet, C.; Eggleton, B.; Du, J.; Glasscock, J.; Savvides, N.

    2004-01-01

    Full text: Silicon microphotonic devices have been drawing increasing attention in the past few years. The high index-difference between silicon and its oxide (Δn = 2) suggests a potential for high-density integration of optical functions on to a photonic chip. Additionally, it has been shown that silicon exhibits strong Raman nonlinearity, a necessary property as light interaction can occur only by means of nonlinearities in the propagation medium. The small dimensions of silicon waveguides require the design of efficient tapers to couple light to them. We have used the beam propagation method (RSoft BeamPROP) to understand the principles and design of an inverse-taper mode-converter as implemented in several recent papers. We report on progress in the design and fabrication of silicon-based waveguides. Preliminary work has been conducted by patterning silicon-on-insulator (SOI) wafers using optical lithography and reactive ion etching. Thus far, only rib waveguides have been designed, as single-mode ridge-waveguides are beyond the capabilities of conventional optical lithography. We have recently moved to electron beam lithography as the higher resolutions permitted will provide the flexibility to begin fabricating sub-micron waveguides

  18. A micromachined silicon valve driven by a miniature bi-stable electro-magnetic actuator

    NARCIS (Netherlands)

    Bohm, S.; Burger, G.J.; Burger, G.J.; Korthorst, M.T.; Roseboom, F.

    2000-01-01

    In this paper a novel combination of a micromachined silicon valve with low dead volume and a bi-stable electromagnetic actuator produced by conventional machining is presented. The silicon valve part, 7×7×1 mm3 in dimensions, is a sandwich construction of two KOH etched silicon wafers with a layer

  19. Silicon bulk growth for solar cells: Science and technology

    Science.gov (United States)

    Kakimoto, Koichi; Gao, Bing; Nakano, Satoshi; Harada, Hirofumi; Miyamura, Yoshiji

    2017-02-01

    The photovoltaic industry is in a phase of rapid expansion, growing by more than 30% per annum over the last few decades. Almost all commercial solar cells presently use single-crystalline or multicrystalline silicon wafers similar to those used in microelectronics; meanwhile, thin-film compounds and alloy solar cells are currently under development. The laboratory performance of these cells, at 26% solar energy conversion efficiency, is now approaching thermodynamic limits, with the challenge being to incorporate these improvements into low-cost commercial products. Improvements in the optical design of cells, particularly in their ability to trap weakly absorbed light, have also led to increasing interest in thin-film cells based on polycrystalline silicon; these cells have advantages over other thin-film photovoltaic candidates. This paper provides an overview of silicon-based solar cell research, especially the development of silicon wafers for solar cells, from the viewpoint of growing both single-crystalline and multicrystalline wafers.

  20. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  1. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging

    International Nuclear Information System (INIS)

    Esposito, M; Evans, P M; Wells, K; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Allinson, N M

    2014-01-01

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  2. Performance of a novel wafer scale CMOS active pixel sensor for bio-medical imaging.

    Science.gov (United States)

    Esposito, M; Anaxagoras, T; Konstantinidis, A C; Zheng, Y; Speller, R D; Evans, P M; Allinson, N M; Wells, K

    2014-07-07

    Recently CMOS active pixels sensors (APSs) have become a valuable alternative to amorphous silicon and selenium flat panel imagers (FPIs) in bio-medical imaging applications. CMOS APSs can now be scaled up to the standard 20 cm diameter wafer size by means of a reticle stitching block process. However, despite wafer scale CMOS APS being monolithic, sources of non-uniformity of response and regional variations can persist representing a significant challenge for wafer scale sensor response. Non-uniformity of stitched sensors can arise from a number of factors related to the manufacturing process, including variation of amplification, variation between readout components, wafer defects and process variations across the wafer due to manufacturing processes. This paper reports on an investigation into the spatial non-uniformity and regional variations of a wafer scale stitched CMOS APS. For the first time a per-pixel analysis of the electro-optical performance of a wafer CMOS APS is presented, to address inhomogeneity issues arising from the stitching techniques used to manufacture wafer scale sensors. A complete model of the signal generation in the pixel array has been provided and proved capable of accounting for noise and gain variations across the pixel array. This novel analysis leads to readout noise and conversion gain being evaluated at pixel level, stitching block level and in regions of interest, resulting in a coefficient of variation ⩽1.9%. The uniformity of the image quality performance has been further investigated in a typical x-ray application, i.e. mammography, showing a uniformity in terms of CNR among the highest when compared with mammography detectors commonly used in clinical practice. Finally, in order to compare the detection capability of this novel APS with the technology currently used (i.e. FPIs), theoretical evaluation of the detection quantum efficiency (DQE) at zero-frequency has been performed, resulting in a higher DQE for this

  3. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  4. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  5. The Six-Inch Lunar Atlas A Pocket Field Guide

    CERN Document Server

    Spain, Don

    2009-01-01

    The Six-Inch Lunar Atlas has been designed specifically for use in the field by lunar observers so it’s perfect for fitting into an observer’s pocket! The author’s own lunar photographs were taken with a 6-inch (150mm) telescope and CCD camera, and closely match the visual appearance of the Moon when viewed through 3-inch to 8-inch telescopes. Each picture is shown oriented "as the Moon really is" when viewed from the northern hemisphere, and is supplemented by exquisite computer sketches that list the main features. Two separate computer sketches are provided to go with each photograph, one oriented to appear as seen through an SCT telescope (e.g. the Meade and Celestron ranges), the other oriented for Newtonian and refracting telescopes. Observers using the various types telescopes will find it extremely helpful to identify lunar features as the human brain is very poor at making "mirror-image" visual translations.

  6. Aerosol Research Branch (ARB) 48 inch Lidar Data

    Data.gov (United States)

    National Aeronautics and Space Administration — The ARB_48_IN_LIDAR data set contains data collected from a 48-inch lidar system located at NASA Langley Research Center. Each granule consists of one year of data....

  7. Micromachining of buried micro channels in silicon

    NARCIS (Netherlands)

    de Boer, Meint J.; Tjerkstra, R.W.; Berenschot, Johan W.; Jansen, Henricus V.; Burger, G.J.; Burger, G.J.; Gardeniers, Johannes G.E.; Elwenspoek, Michael Curt; van den Berg, Albert

    A new method for the fabrication of micro structures for fluidic applications, such as channels, cavities, and connector holes in the bulk of silicon wafers, called buried channel technology (BCT), is presented in this paper. The micro structures are constructed by trench etching, coating of the

  8. 16 CFR 500.19 - Conversion of SI metric quantities to inch/pound quantities and inch/pound quantities to SI...

    Science.gov (United States)

    2010-01-01

    .../pound quantities and inch/pound quantities to SI metric quantities. 500.19 Section 500.19 Commercial... LABELING ACT § 500.19 Conversion of SI metric quantities to inch/pound quantities and inch/pound quantities to SI metric quantities. (a) For calculating the conversion of SI metric quantities to inch/pound...

  9. Study of silicon pixel sensor for synchrotron radiation detection

    Science.gov (United States)

    Li, Zhen-Jie; Jia, Yun-Cong; Hu, Ling-Fei; Liu, Peng; Yin, Hua-Xiang

    2016-03-01

    The silicon pixel sensor (SPS) is one of the key components of hybrid pixel single-photon-counting detectors for synchrotron radiation X-ray detection (SRD). In this paper, the design, fabrication, and characterization of SPSs for single beam X-ray photon detection is reported. The designed pixel sensor is a p+-in-n structure with guard-ring structures operated in full-depletion mode and is fabricated on 4-inch, N type, 320 μm thick, high-resistivity silicon wafers by a general Si planar process. To achieve high energy resolution of X-rays and obtain low dark current and high breakdown voltage as well as appropriate depletion voltage of the SPS, a series of technical optimizations of device structure and fabrication process are explored. With optimized device structure and fabrication process, excellent SPS characteristics with dark current of 2 nA/cm2, full depletion voltage 150 V are achieved. The fabricated SPSs are wire bonded to ASIC circuits and tested for the performance of X-ray response to the 1W2B synchrotron beam line of the Beijing Synchrotron Radiation Facility. The measured S-curves for SRD demonstrate a high discrimination for different energy X-rays. The extracted energy resolution is high (10 keV) and the linear properties between input photo energy and the equivalent generator amplitude are well established. It confirmed that the fabricated SPSs have a good energy linearity and high count rate with the optimized technologies. The technology is expected to have a promising application in the development of a large scale SRD system for the Beijing Advanced Photon Source. Supported by Prefabrication Research of Beijing Advanced Photon Source (R&D for BAPS) and National Natural Science Foundation of China (11335010)

  10. Development of 52 inches last stage blade for steam turbines

    International Nuclear Information System (INIS)

    Suzuki, Atsuhide; Hisa, Shoichi; Nagao, Shinichiro; Ogata, Hisao

    1986-01-01

    The last stage blades of steam turbines are the important component controlling the power output and performance of plants. In order to realize a unit of large capacity and high efficiency, the proper exhaust area and the last stage blades having good performance are indispensable. Toshiba Corp. has completed the development of the 52 inch last stage blades for 1500 and 1800 rpm steam turbines. The 52 inch last stage blades are the longest in the world, which have the annular exhaust area nearly 1.5 times as much as that of 41 inch blades used for 1100 MW, 1500 rpm turbines in nuclear power stations. By adopting these 52 inch blades, the large capacity nuclear power plants up to 1800 MW can be economically constructed, the rate of heat consumption of 1350 MW plants is improved by 3 ∼ 4 % as compared with 41 inch blades, and in the plants up to 1100 MW, LP turbines can be reduced from three sets to two. The features of 52 inch blades, the flow pattern and blade form design, the structural strength analysis and the erosion withstanding property, and the verification by the rotation test of the actual blades, the performance test using a test turbine, the vibration analysis of the actually loaded blades and the analysis of wet steam behavior are reported. (Kako, I.)

  11. Organization of silicon nanocrystals by localized electrochemical etching

    International Nuclear Information System (INIS)

    Ayari-Kanoun, Asma; Drouin, Dominique; Beauvais, Jacques; Lysenko, Vladimir; Nychyporuk, Tetyana; Souifi, Abdelkader

    2009-01-01

    An approach to form a monolayer of organized silicon nanocrystals on a monocrystalline Si wafer is reported. Ordered arrays of nanoholes in a silicon nitride layer were obtained by combining electron beam lithography and plasma etching. Then, a short electrochemical etching current pulse led to formation of a single Si nanocrystal per each nanohole. As a result, high quality silicon nanocrystal arrays were formed with well controlled and reproducible morphologies. In future, this approach can be used to fabricate single electron devices.

  12. Lifetime of Nano-Structured Black Silicon for Photovoltaic Applications

    DEFF Research Database (Denmark)

    Plakhotnyuk, Maksym; Davidsen, Rasmus Schmidt; Schmidt, Michael Stenbæk

    2016-01-01

    properties. We applied reactive ion etching technology at -20ºC to create nano-structures on silicon samples and obtained an average reflectance below 0.5%. For passivation purposes, we used 37 nm ALD Al2O3 films. Lifetime measurements resulted in 1220 µs and to 4170 µs for p- and ntype CZ silicon wafers......, respectively. This is promising for use of black silicon RIE nano-structuring in a solar cell process flow...

  13. TXRF analysis of trace metals in thin silicon nitride films

    International Nuclear Information System (INIS)

    Vereecke, G.; Arnauts, S.; Verstraeten, K.; Schaekers, M.; Heyrts, M.M.

    2000-01-01

    As critical dimensions of integrated circuits continue to decrease, high dielectric constant materials such as silicon nitride are being considered to replace silicon dioxide in capacitors and transistors. The achievement of low levels of metal contamination in these layers is critical for high performance and reliability. Existing methods of quantitative analysis of trace metals in silicon nitride require high amounts of sample (from about 0.1 to 1 g, compared to a mass of 0.2 mg for a 2 nm thick film on a 8'' silicon wafer), and involve digestion steps not applicable to films on wafers or non-standard techniques such as neutron activation analysis. A novel approach has recently been developed to analyze trace metals in thin films with analytical techniques currently used in the semiconductor industry. Sample preparation consists of three steps: (1) decomposition of the silicon nitride matrix by moist HF condensed at the wafer surface to form ammonium fluosilicate. (2) vaporization of the fluosilicate by a short heat treatment at 300 o C. (3) collection of contaminants by scanning the wafer surface with a solution droplet (VPD-DSC procedure). The determination of trace metals is performed by drying the droplet on the wafer and by analyzing the residue by TXRF, as it offers the advantages of multi-elemental analysis with no dilution of the sample. The lower limits of detection for metals in 2 nm thick films on 8'' silicon wafers range from about 10 to 200 ng/g. The present study will focus on the matrix effects and the possible loss of analyte associated with the evaporation of the fluosilicate salt, in relation with the accuracy and the reproducibility of the method. The benefits of using an internal standard will be assessed. Results will be presented from both model samples (ammonium fluoride contaminated with metallic salts) and real samples (silicon nitride films from a production tool). (author)

  14. Devices using resin wafers and applications thereof

    Science.gov (United States)

    Lin, YuPo J [Naperville, IL; Henry, Michael P [Batavia, IL; Snyder, Seth W [Lincolnwood, IL; Martin, Edward [Libertyville, IL; Arora, Michelle [Woodridge, IL; de la Garza, Linda [Woodridge, IL

    2009-03-24

    Devices incorporating a thin wafer of electrically and ionically conductive porous material made by the method of introducing a mixture of a thermoplastic binder and one or more of anion exchange moieties or cation exchange moieties or mixtures thereof and/or one or more of a protein capture resin and an electrically conductive material into a mold. The mixture is subjected to temperatures in the range of from about 60.degree. C. to about 170.degree. C. at pressures in the range of from about 0 to about 500 psig for a time in the range of from about 1 to about 240 minutes to form thin wafers. Devices include electrodeionization and separative bioreactors in the production of organic and amino acids, alcohols or esters for regenerating cofactors in enzymes and microbial cells.

  15. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  16. Carbon dioxide capture using resin-wafer electrodeionization

    Energy Technology Data Exchange (ETDEWEB)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  17. NTD Silicon; Product Characteristics, Main Uses and Growth Potential

    International Nuclear Information System (INIS)

    Hansen, M. G.; Bjorling, C. F.

    2013-01-01

    Topsil is a specialised manufacturer of ultrapure float zone silicon since 1959, headquartered in Denmark. Topsil co-pioneered the invention of Neutron Transmutation Doped (NTD) monocrystalline silicon with research institute Risoe in the 1970s and has since then been world leading manufacturer of NTD silicon for the power market. This presentation will focus on NTD silicon; its characteristics, invention and main uses. It will address the trends of the power market and market projections for NTD, and discuss the growth potential in the years ahead, including larger silicon wafers and management of the NTD supply chain

  18. Two inch large area patterning on a vertical light-emitting diode by nano-imprinting technology

    International Nuclear Information System (INIS)

    Byeon, Kyeong-Jae; Hong, Eun-Ju; Park, Hyoungwon; Yoon, Kyung-Min; Lee, Heon; Song, Hyun Don; Lee, Jin Wook; Kim, Sun-Kyung; Cho, Hyun Kyong; Kwon, Ho Ki

    2010-01-01

    A vertical light-emitting diode (LED) with a chip size of 500 × 500 µm 2 was fabricated by the laser lift-off (LLO) process of an InGaN-based blue LED wafer. After the LLO process, photonic crystal patterns by UV nano-imprint lithography were formed on the n-GaN top layer of the vertical LED over the entire area with a diameter of 2 inches. As the result of n-GaN patterning, light output power of the vertical LED with photonic crystals was increased by up to 44% compared to that of the vertical LED without a photonic crystal at a driving current of 1000 mA

  19. Rinsing of wafers after wet processing: Simulation and experiments

    Science.gov (United States)

    Chiang, Chieh-Chun

    In semiconductor manufacturing, a large amount (50 billion gallons for US semiconductor fabrication plants in 2006) of ultrapure water (UPW) is used to rinse wafers after wet chemical processing to remove ionic contaminants on surfaces. Of great concern are the contaminants left in narrow (tens of nm), high-aspect-ratio (5:1 to 20:1) features (trenches, vias, and contact holes). The International Technology Roadmap for Semiconductors (ITRS) stipulates that ionic contaminant levels be reduced to below ˜ 10 10 atoms/cm2. Understanding the bottlenecks in the rinsing process would enable conservation of rinse water usage. A comprehensive process model has been developed on the COMSOL platform to predict the dynamics of rinsing of narrow structures on patterned SiO 2 substrates initially cleaned with NH4OH. The model considers the effect of various mass-transport mechanisms, including convection and diffusion/dispersion, which occur simultaneously with various surface phenomena, such as adsorption and desorption of impurities. The influences of charged species in the bulk and on the surface, and their induced electric field that affect both transport and surface interactions, have been addressed. Modeling results show that the efficacy of rinsing is strongly influenced by the rate of desorption of adsorbed contaminants, mass transfer of contaminants from the mouth of the feature to the bulk liquid, and the trench aspect ratio. Detection of the end point of rinsing is another way to conserve water used for rinsing after wet processing. The applicability of electrochemical impedance spectroscopy (EIS) to monitor rinsing of Si processed in HF with and without copper contaminant was explored. In the first study, the effect of the nature of surface state (flat band, depletion, or accumulation) of silicon on rinsing rate was investigated. The experimental results show that the state of silicon could affect rinsing kinetics through modulation of ion adsorption. In the second

  20. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  1. Wafer level test solutions for IR sensors

    Science.gov (United States)

    Giessmann, Sebastian; Werner, Frank-Michael

    2014-05-01

    Wafer probers provide an established platform for performing electrical measurements at wafer level for CMOS and similar process technologies. For testing IR sensors, the requirements are beyond the standard prober capabilities. This presentation will give an overview about state of the art IR sensor probing systems reaching from flexible engineering solutions to automated production needs. Cooled sensors typically need to be tested at a target temperature below 80 K. Not only is the device temperature important but also the surrounding environment is required to prevent background radiation from reaching the device under test. To achieve that, a cryogenic shield is protecting the movable chuck. By operating that shield to attract residual gases inside the chamber, a completely contamination-free test environment can be guaranteed. The use of special black coatings are furthermore supporting the removal of stray light. Typically, probe card needles are operating at ambient (room) temperature when connecting to the wafer. To avoid the entrance of heat, which can result in distorted measurements, the probe card is fully embedded into the cryogenic shield. A shutter system, located above the probe field, is designed to switch between the microscope view to align the sensor under the needles and the test relevant setup. This includes a completely closed position to take dark current measurements. Another position holds a possible filter glass with the required aperture opening. The necessary infrared sources to stimulate the device are located above.

  2. On the evolution of wafer level cameras

    Science.gov (United States)

    Welch, H.

    2011-02-01

    The introduction of small cost effective cameras based on CMOS image sensor technology has played an important role in the revolution in mobile devices of the last 10 years. Wafer-based optics manufacturing leverages the same fabrication equipment used to produce CMOS sensors. The natural integration of these two technologies allows the mass production of very low cost surface mount cameras that can fit into ever thinner mobile devices. Nano Imprint Lithography (NIL) equipment has been adapted to make precision aspheres that can be stacked using wafer bonding techniques to produce multi-element lens assemblies. This, coupled with advances in mastering technology, allows arrays of lenses with prescriptions not previously possible. A primary motivation for these methods is that it allows the consolidation of the supply chain. Image sensor manufacturers envision creating optics by simply adding layers to their existing sensor fabrication lines. Results thus far have been promising. The current alternative techniques for creating VGA cameras are discussed as well as the prime cost drivers for lens to sensor integration. Higher resolution cameras face particularly difficult challenges, but can greatly simplify the critical tilt and focus steps needed to assemble cameras that produce quality images. Finally, we discuss the future of wafer-level cameras and explore several of the novel concepts made possible by the manufacturing advantages of photolithography.

  3. Signal development in irradiated silicon detectors

    CERN Document Server

    Kramberger, Gregor; Mikuz, Marko

    2001-01-01

    This work provides a detailed study of signal formation in silicon detectors, with the emphasis on detectors with high concentration of irradiation induced defects in the lattice. These defects give rise to deep energy levels in the band gap. As a consequence, the current induced by charge motion in silicon detectors is signifcantly altered. Within the framework of the study a new experimental method, Charge correction method, based on transient current technique (TCT) was proposed for determination of effective electron and hole trapping times in irradiated silicon detectors. Effective carrier trapping times were determined in numerous silicon pad detectors irradiated with neutrons, pions and protons. Studied detectors were fabricated on oxygenated and non-oxygenated silicon wafers with different bulk resistivities. Measured effective carrier trapping times were found to be inversely proportional to fuence and increase with temperature. No dependence on silicon resistivity and oxygen concentration was observ...

  4. Room temperature wafer direct bonding of smooth Si surfaces recovered by Ne beam surface treatments

    Science.gov (United States)

    Kurashima, Yuichi; Maeda, Atsuhiko; Takagi, Hideki

    2013-06-01

    We examined the applicability of a Ne fast atom beam (FAB) to surface activated bonding of Si wafers at room temperature. With etching depth more than 1.5 nm, the bonding strength comparable to Si bulk strength was attained. Moreover, we found the improvement of the bonding strength by surface smoothing effect of the Ne FAB. Silicon surface roughness decreased from 0.40 to 0.17 nm rms by applying a Ne FAB of 30 nm etching depth. The bonding strength between surfaces recovered by Ne FAB surface smoothing was largely improved and finally became equivalent to Si bulk strength.

  5. Mechanically flexible optically transparent porous mono-crystalline silicon substrate

    KAUST Repository

    Rojas, Jhonathan Prieto

    2012-01-01

    For the first time, we present a simple process to fabricate a thin (≥5μm), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon <100> wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates. © 2012 IEEE.

  6. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  7. Bias-assisted KOH etching of macroporous silicon membranes

    International Nuclear Information System (INIS)

    Mathwig, K; Geilhufe, M; Müller, F; Gösele, U

    2011-01-01

    This paper presents an improved technique to fabricate porous membranes from macroporous silicon as a starting material. A crucial step in the fabrication process is the dissolution of silicon from the backside of the porous wafer by aqueous potassium hydroxide to open up the pores. We improved this step by biasing the silicon wafer electrically against the KOH. By monitoring the current–time characteristics a good control of the process is achieved and the yield is improved. Also, the etching can be stopped instantaneously and automatically by short-circuiting Si and KOH. Moreover, the bias-assisted etching allows for the controlled fabrication of silicon dioxide tube arrays when the silicon pore walls are oxidized and inverted pores are released.

  8. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  9. Silicon Nanowire Field-effect Chemical Sensor

    OpenAIRE

    Chen, S.

    2011-01-01

    This thesis describes the work that has been done on the project “Design and optimization of silicon nanowire for chemical sensing‿, including Si-NW fabrication, electrical/electrochemical modeling, the application as ISFET, and the build-up of Si- NW/LOC system for automatic sample delivery. A novel top-down fabrication technique was presented for single-crystal Si-NW fabrication realized with conventional microfabrication technique. High quality triangular Si-NWs were made with high wafer-s...

  10. High Throughput Nanofabrication of Silicon Nanowire and Carbon Nanotube Tips on AFM Probes by Stencil-Deposited Catalysts

    DEFF Research Database (Denmark)

    Engstrøm, Daniel Southcott; Savu, Veronica; Zhu, Xueni

    2011-01-01

    A new and versatile technique for the wafer scale nanofabrication of silicon nanowire (SiNW) and multiwalled carbon nanotube (MWNT) tips on atomic force microscope (AFM) probes is presented. Catalyst material for the SiNW and MWNT growth was deposited on prefabricated AFM probes using aligned wafer...

  11. Particle precipitation in connection with KOH etching of silicon

    DEFF Research Database (Denmark)

    Nielsen, Christian Bergenstof; Christensen, Carsten; Pedersen, Casper

    2004-01-01

    This paper considers the precipitation of iron oxide particles in connection with the KOH etching of cavities in silicon wafers. The findings presented in this paper suggest that the source to the particles is the KOH pellets used for making the etching solution. Experiments show...... that the precipitation is independent of KOH etching time, but that the amount of deposited material varies with dopant type and dopant concentration. The experiments also suggest that the precipitation occurs when the silicon wafers are removed from the KOH etching solution and not during the etching procedure. When...

  12. Wafer-Scale Nanopillars Derived from Block Copolymer Lithography for Surface-Enhanced Raman Spectroscopy

    DEFF Research Database (Denmark)

    Li, Tao; Wu, Kaiyu; Rindzevicius, Tomas

    2016-01-01

    We report a novel nanofabrication process via block copolymer lithography using solvent vapor annealing. The nanolithography process is facile and scalable, enabling fabrication of highly ordered periodic patterns over entire wafers as substrates for surface-enhanced Raman spectroscopy (SERS......). Direct silicon etching with high aspect ratio templated by the block copolymer mask is realized without any intermediate layer or external precursors. Uniquely, an atomic layer deposition (ALD)-assisted method is introduced to allow reversing of the morphology relative to the initial pattern. As a result......, highly ordered silicon nanopillar arrays are fabricated with controlled aspect ratios. After metallization, the resulting nanopillar arrays are suitable for SERS applications. These structures readily exhibit an average SERS enhancement factor of above 108, SERS uniformities of 8.5% relative standard...

  13. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  14. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  15. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  16. Silicon crystal growth using a liquid-feeding Czochralski method

    Science.gov (United States)

    Shiraishi, Yutaka; Kurosaka, Shoei; Imai, Masato

    1996-09-01

    Silicon single crystals with uniformity along the growth direction were grown using a new continuous Czochralski (CCZ) method. Polycrystalline silicon rods used as charge materials are melted by carbon heaters over a crucible without contact between the raw material and other substances. Using this method, silicon crystals with diameters as large as 6 or 8 inch and good uniformity along the growth direction were grown.

  17. Silicone metalization

    Energy Technology Data Exchange (ETDEWEB)

    Maghribi, Mariam N. (Livermore, CA); Krulevitch, Peter (Pleasanton, CA); Hamilton, Julie (Tracy, CA)

    2008-12-09

    A system for providing metal features on silicone comprising providing a silicone layer on a matrix and providing a metal layer on the silicone layer. An electronic apparatus can be produced by the system. The electronic apparatus comprises a silicone body and metal features on the silicone body that provide an electronic device.

  18. Anodic bonding using SOI wafer for fabrication of capacitive micromachined ultrasonic transducers

    International Nuclear Information System (INIS)

    Bellaredj, M; Bourbon, G; Walter, V; Moal, P Le; Berthillier, M

    2014-01-01

    In medical ultrasound imaging, mostly piezoelectric crystals are used as ultrasonic transducers. Capacitive micromachined ultrasonic transducers (CMUTs) introduced around 1994 have been shown to be a good alternative to conventional piezoelectric transducers in various aspects, such as sensitivity, transduction efficiency or bandwidth. This paper focuses on a fabrication process for CMUTs using anodic bonding of a silicon on insulator wafer on a glass wafer. The processing steps are described leading to a good control of the mechanical response of the membrane. This technology makes possible the fabrication of large membranes and can extend the frequency range of CMUTs to lower frequencies of operation. Silicon membranes having radii of 50, 70, 100 and 150 µm and a 1.5 µm thickness are fabricated and electromechanically characterized using an auto-balanced bridge impedance analyzer. Resonant frequencies from 0.6 to 2.3 MHz and an electromechanical coupling coefficient around 55% are reported. The effects of residual stress in the membranes and uncontrolled clamping conditions are clearly responsible for the discrepancies between experimental and theoretical values of the first resonance frequency. The residual stress in the membranes is determined to be between 90 and 110 MPa. The actual boundary conditions are between the clamped condition and the simply supported condition and can be modeled with a torsional stiffness of 2.10 −7  Nm rad –1  in the numerical model. (paper)

  19. A continuous Czochralski silicon crystal growth system

    Science.gov (United States)

    Wang, C.; Zhang, H.; Wang, T. H.; Ciszek, T. F.

    2003-03-01

    Demand for large silicon wafers has driven the growth of silicon crystals from 200 to 300 mm in diameter. With the increasing silicon ingot sizes, melt volume has grown dramatically. Melt flow becomes more turbulent as melt height and volume increase. To suppress turbulent flow in a large silicon melt, a new Czochralski (CZ) growth furnace has been designed that has a shallow melt. In this new design, a crucible consists of a shallow growth compartment in the center and a deep feeding compartment around the periphery. Two compartments are connected with a narrow annular channel. A long crystal may be continuously grown by feeding silicon pellets into the dedicated feeding compartment. We use our numerical model to simulate temperature distribution and velocity field in a conventional 200-mm CZ crystal growth system and also in the new shallow crucible CZ system. By comparison, advantages and disadvantages of the proposed system are observed, operating conditions are determined, and the new system is improved.

  20. Development of advanced methods for continuous Czochralski growth. Silicon sheet growth development for the large area silicon sheet task of the low cost silicon solar array project

    Science.gov (United States)

    Wolfson, R. G.; Sibley, C. B.

    1978-01-01

    The three components required to modify the furnace for batch and continuous recharging with granular silicon were designed. The feasibility of extended growth cycles up to 40 hours long was demonstrated by a recharge simulation experiment; a 6 inch diameter crystal was pulled from a 20 kg charge, remelted, and pulled again for a total of four growth cycles, 59-1/8 inch of body length, and approximately 65 kg of calculated mass.

  1. Realize multiple hermetic chamber pressures for system-on-chip process by using the capping wafer with diverse cavity depths

    Science.gov (United States)

    Cheng, Shyh-Wei; Weng, Jui-Chun; Liang, Kai-Chih; Sun, Yi-Chiang; Fang, Weileun

    2018-04-01

    Many mechanical and thermal characteristics, for example the air damping, of suspended micromachined structures are sensitive to the ambient pressure. Thus, micromachined devices such as the gyroscope and accelerometer have different ambient pressure requirements. Commercially available process platforms could be used to fabricate and integrate devices of various functions to reduce the chip size. However, it remains a challenge to offer different ambient pressures for micromachined devices after sealing them by wafer level capping (WLC). This study exploits the outgassing characteristics of the CMOS chip to fabricate chambers of various pressures after the WLC of the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform. The pressure of the sealed chamber can be modulated by the chamber volume after the outgassing. In other words, the pressure of hermetic sealed chambers can be easily and properly defined by the etching depth of the cavity on an Si capping wafer. In applications, devices sealed with different cavity depths are implemented using the Si-above-CMOS (TSMC 0.18 µm 1P5M CMOS process) MEMS process platform to demonstrate the present approach. Measurements show the feasibility of this simple chamber pressure modulation approach on eight-inch wafers.

  2. A monolithic silicon-based membrane-electrode assembly for micro fuel cells

    Science.gov (United States)

    Yuzova, V. A.; Merkushev, F. F.; Semenova, O. V.

    2017-08-01

    We report the basic possibility of creating a micro fuel cell (MFC) with a monolithic silicon-based membrane-electrode assembly (MEA), which employs a porous three-layer framework structure manufactured by two-sided anodic etching of a 500-μm-thick silicon wafer. A technology of MEAs for MFCs is described.

  3. Micro filtration membrane sieve with silicon micro machining for industrial and biomedical applications

    NARCIS (Netherlands)

    van Rijn, C.J.M.; Elwenspoek, Michael Curt

    1995-01-01

    With the use of silicon micromachining an inorganic membrane sieve for microfiltration is constructed, having a siliconnitride membrane layer with thickness typically 1 pm and perforations typically between 0.5 pm and 10 pm in diameter. As a support a -silicon wafer with openings of loo0 pm in

  4. Porous silicon in solar cell structures : a review of achievements and modern directions of further use

    NARCIS (Netherlands)

    Yerokhov, VY; Melnyk, [No Value

    1999-01-01

    Porous silicon, which is being obtained by electrochemical etching of silicon wafers in electrolytes on the base of hydrofluoric acid, recently attracted the attention of specialists in photovoltaics even more due to a number of its unique properties. However, at present, acceptable results are

  5. Direct chemical vapour deposited grapheme synthesis on silicon oxide by controlled copper dewettting

    NARCIS (Netherlands)

    van den Beld, Wesley Theodorus Eduardus; van den Berg, Albert; Eijkel, Jan C.T.

    2015-01-01

    In this paper we present a novel method for direct uniform graphene synthesis onto silicon oxide in a controlled manner. On a grooved silicon oxide wafer is copper deposited under a slight angle and subsequently the substrate is treated by a typical graphene synthesis process. During this process

  6. Lifetime of ALD Al2O3 Passivated Black Silicon Nanostructured for Photovoltaic Applications

    DEFF Research Database (Denmark)

    Plakhotnyuk, Maksym; Davidsen, Rasmus Schmidt; Schmidt, Michael Stenbæk

    .5%. For passivation purposes we used 37 nm ALD Al2O3 films and conducted lifetime measurements and found 1220 µs and to 4170 µs, respectively, for p- and n-type CZ silicon wafers. Such results are promising results to introduce for black silicon RIE nano-structuring in solar cell process flow....

  7. Patterned wafer geometry grouping for improved overlay control

    Science.gov (United States)

    Lee, Honggoo; Han, Sangjun; Woo, Jaeson; Park, Junbeom; Song, Changrock; Anis, Fatima; Vukkadala, Pradeep; Jeon, Sanghuck; Choi, DongSub; Huang, Kevin; Heo, Hoyoung; Smith, Mark D.; Robinson, John C.

    2017-03-01

    Process-induced overlay errors from outside the litho cell have become a significant contributor to the overlay error budget including non-uniform wafer stress. Previous studies have shown the correlation between process-induced stress and overlay and the opportunity for improvement in process control, including the use of patterned wafer geometry (PWG) metrology to reduce stress-induced overlay signatures. Key challenges of volume semiconductor manufacturing are how to improve not only the magnitude of these signatures, but also the wafer to wafer variability. This work involves a novel technique of using PWG metrology to provide improved litho-control by wafer-level grouping based on incoming process induced overlay, relevant for both 3D NAND and DRAM. Examples shown in this study are from 19 nm DRAM manufacturing.

  8. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  9. Production of silicon disks for PV systems; Herstellung von Siliciumscheiben fuer die Photovoltaik

    Energy Technology Data Exchange (ETDEWEB)

    Woditsch, P. [Bayer Solar GmbH, Freiberg (Germany)

    1999-07-01

    The contribution describes the production of silicon wafers in all stages: Melting and crystallisation, production of wafers and columns, careful cleaning and quality control of every single silicon wafer. The initial material is pure silicon as used in the production of electronic chips. Bayer Solar GmbH are producers of monocrystalline and multicrystalline silicon wafers. By the end of 1999, their two works at Uerdingen and Freiberg had a total capacity of about 36 MWp, i.e. about 25% of the world demand. [German] Im Beitrag wird der Werdegang vom Silicium bis zum photovoltaischen System kurz dargestellt, wobei, bedingt durch eine teilweise Arbeitsteilung, die Si-Wafer und Zellen als Zwischenstufen auftreten. Die Bayer Solar GmbH hat sich dabei bis heute auf die Herstellung von mono- und multikristallinen Siliciumscheiben konzentriert, wobei Werke in Uerdingen und Freiberg Ende 1999 eine Gesamtkapazitaet von etwa 36 MWp bereit halten, was ca. 25% des weltweiten Bedarfs entspricht. Der Weg vom Silicium zum Wafer umfasst das Schmelzen und Kristallisieren, die Saeulen- und Scheibenherstellung, eine sorgfaeltige Scheibenreinigung und anschliessende Qualitaetskontrolle jeder einzelnen Siliciumscheibe. Ausgangsmaterial ist ein hochreines Silicium, wie es aehnlich auch fuer die Chipherstellung in der Elektronik verwendet wird. (orig.)

  10. Design Study of Wafer Seals for Future Hypersonic Vehicles

    Science.gov (United States)

    Dunlap, Patrick H.; Finkbeiner, Joshua R.; Steinetz, Bruce M.; DeMange, Jeffrey J.

    2005-01-01

    Future hypersonic vehicles require high temperature, dynamic seals in advanced hypersonic engines and on the vehicle airframe to seal the perimeters of movable panels, flaps, and doors. Current seals do not meet the demanding requirements of these applications, so NASA Glenn Research Center is developing improved designs to overcome these shortfalls. An advanced ceramic wafer seal design has shown promise in meeting these needs. Results from a design of experiments study performed on this seal revealed that several installation variables played a role in determining the amount of leakage past the seals. Lower leakage rates were achieved by using a tighter groove width around the seals, a higher seal preload, a tighter wafer height tolerance, and a looser groove length. During flow testing, a seal activating pressure acting behind the wafers combined with simulated vibrations to seat the seals more effectively against the sealing surface and produce lower leakage rates. A seal geometry study revealed comparable leakage for full-scale wafers with 0.125 and 0.25 in. thicknesses. For applications in which lower part counts are desired, fewer 0.25-in.-thick wafers may be able to be used in place of 0.125-in.-thick wafers while achieving similar performance. Tests performed on wafers with a rounded edge (0.5 in. radius) in contact with the sealing surface resulted in flow rates twice as high as those for wafers with a flat edge. Half-size wafers had leakage rates approximately three times higher than those for full-size wafers.

  11. Silicon-Rich Silicon Carbide Hole-Selective Rear Contacts for Crystalline-Silicon-Based Solar Cells.

    Science.gov (United States)

    Nogay, Gizem; Stuckelberger, Josua; Wyss, Philippe; Jeangros, Quentin; Allebé, Christophe; Niquille, Xavier; Debrot, Fabien; Despeisse, Matthieu; Haug, Franz-Josef; Löper, Philipp; Ballif, Christophe

    2016-12-28

    The use of passivating contacts compatible with typical homojunction thermal processes is one of the most promising approaches to realizing high-efficiency silicon solar cells. In this work, we investigate an alternative rear-passivating contact targeting facile implementation to industrial p-type solar cells. The contact structure consists of a chemically grown thin silicon oxide layer, which is capped with a boron-doped silicon-rich silicon carbide [SiC x (p)] layer and then annealed at 800-900 °C. Transmission electron microscopy reveals that the thin chemical oxide layer disappears upon thermal annealing up to 900 °C, leading to degraded surface passivation. We interpret this in terms of a chemical reaction between carbon atoms in the SiC x (p) layer and the adjacent chemical oxide layer. To prevent this reaction, an intrinsic silicon interlayer was introduced between the chemical oxide and the SiC x (p) layer. We show that this intrinsic silicon interlayer is beneficial for surface passivation. Optimized passivation is obtained with a 10-nm-thick intrinsic silicon interlayer, yielding an emitter saturation current density of 17 fA cm -2 on p-type wafers, which translates into an implied open-circuit voltage of 708 mV. The potential of the developed contact at the rear side is further investigated by realizing a proof-of-concept hybrid solar cell, featuring a heterojunction front-side contact made of intrinsic amorphous silicon and phosphorus-doped amorphous silicon. Even though the presented cells are limited by front-side reflection and front-side parasitic absorption, the obtained cell with a V oc of 694.7 mV, a FF of 79.1%, and an efficiency of 20.44% demonstrates the potential of the p + /p-wafer full-side-passivated rear-side scheme shown here.

  12. A comparison of buried oxide characteristics of single and multiple implant SIMOX and bond and etch back wafers

    International Nuclear Information System (INIS)

    Annamalai, N.K.; Bockman, J.F.; McGruer, N.E.; Chapski, J.

    1990-01-01

    The current through the buried oxides of single and multiple implant SIMOX and bond and etch back silicon-on-insulator (BESOI) wafers were measured as a function of radiation dose. From these measurements, conductivity and static capacitances were derived. High frequency capacitances were also measured. Leakage current through the buried oxide of multiple implant SIMOX is considerably less than that of single implant SIMOX (more than an order of magnitude). High frequency and static capacitances, as a function of total dose, were used to study the buried oxide---top silicon interface and the buried oxide---bottom silicon interface. Multiple implant had fewer interface traps than single implant at pre-rad and after irradiation

  13. Principle and modelling of Transient Current Technique for interface traps characterization in monolithic pixel detectors obtained by CMOS-compatible wafer bonding

    CERN Document Server

    Bronuzzi, J.; Moll, M.; Sallese, J.M.

    2016-01-01

    In the framework of monolithic silicon radiation detectors, a fabrication process based on a recently developed silicon wafer bonding technique at low temperature was proposed. Ideally, this new process would enable direct bonding of a read-out electronic chip wafer on a highly resistive silicon substrate wafer, which is expected to present many advantages since it would combine high performance IC's with high sensitive ultra-low doped bulk silicon detectors. But electrical properties of the bonded interface are critical for this kind of application since the mobile charges generated by radiation inside the bonded bulk are expected to transit through the interface in order to be collected by the read-out electronics. In this work, we propose to explore and develop a model for the so-called Transient Current Technique (TCT) to identify the presence of deep traps at the bonded interface. For this purpose, we consider a simple PIN diode reversely biased where the ultra-low doped active region of interest is set ...

  14. SOI silicon on glass for optical MEMS

    DEFF Research Database (Denmark)

    Larsen, Kristian Pontoppidan; Ravnkilde, Jan Tue; Hansen, Ole

    2003-01-01

    A newly developed fabrication method for fabrication of single crystalline Si (SCS) components on glass, utilizing Deep Reactive Ion Etching (DRIE) of a Silicon On Insulator (SOI) wafer is presented. The devices are packaged at wafer level in a glass-silicon-glass (GSG) stack by anodic bonding...... and a final sealing at the interconnects can be performed using a suitable polymer. Packaged MEMS on glass are advantageous within Optical MEMS and for sensitive capacitive devices. We report on experiences with bonding SOI to Pyrex. Uniform DRIE shallow and deep etching was achieved by a combination...... of an optimized device layout and an optimized process recipe. The behavior of the buried oxide membrane when used as an etch stop for the through-hole etch is described. No harmful buckling or fracture of the membrane is observed for an oxide thickness below 1 μm, but larger and more fragile released structures...

  15. Low surface damage dry etched black silicon

    DEFF Research Database (Denmark)

    Plakhotnyuk, Maksym M.; Gaudig, Maria; Davidsen, Rasmus Schmidt

    2017-01-01

    Black silicon (bSi) is promising for integration into silicon solar cell fabrication flow due to its excellent light trapping and low reflectance, and a continuously improving passivation. However, intensive ion bombardment during the reactive ion etching used to fabricate bSi induces surface...... power, during reactive ion etching at non-cryogenic temperature (-20°C), preserves the reflectivity below 1% and improves the effective minority carrier lifetime due to reduced ion energy. We investigate the effect of the etching process on the surface morphology, light trapping, reflectance......, transmittance, and effective lifetime of bSi. Additional surface passivation using atomic layer deposition of Al2O3 significantly improves the effective lifetime. For n-type wafers, the lifetime reaches 12 ms for polished and 7.5 ms for bSi surfaces. For p-type wafers, the lifetime reaches 800 ls for both...

  16. Atomic and electronic structures of novel silicon surface structures

    Energy Technology Data Exchange (ETDEWEB)

    Terry, J.H. Jr.

    1997-03-01

    The modification of silicon surfaces is presently of great interest to the semiconductor device community. Three distinct areas are the subject of inquiry: first, modification of the silicon electronic structure; second, passivation of the silicon surface; and third, functionalization of the silicon surface. It is believed that surface modification of these types will lead to useful electronic devices by pairing these modified surfaces with traditional silicon device technology. Therefore, silicon wafers with modified electronic structure (light-emitting porous silicon), passivated surfaces (H-Si(111), Cl-Si(111), Alkyl-Si(111)), and functionalized surfaces (Alkyl-Si(111)) have been studied in order to determine the fundamental properties of surface geometry and electronic structure using synchrotron radiation-based techniques.

  17. Silicon photonics: some remaining challenges

    Science.gov (United States)

    Reed, G. T.; Topley, R.; Khokhar, A. Z.; Thompson, D. J.; Stanković, S.; Reynolds, S.; Chen, X.; Soper, N.; Mitchell, C. J.; Hu, Y.; Shen, L.; Martinez-Jimenez, G.; Healy, N.; Mailis, S.; Peacock, A. C.; Nedeljkovic, M.; Gardes, F. Y.; Soler Penades, J.; Alonso-Ramos, C.; Ortega-Monux, A.; Wanguemert-Perez, G.; Molina-Fernandez, I.; Cheben, P.; Mashanovich, G. Z.

    2016-03-01

    This paper discusses some of the remaining challenges for silicon photonics, and how we at Southampton University have approached some of them. Despite phenomenal advances in the field of Silicon Photonics, there are a number of areas that still require development. For short to medium reach applications, there is a need to improve the power consumption of photonic circuits such that inter-chip, and perhaps intra-chip applications are viable. This means that yet smaller devices are required as well as thermally stable devices, and multiple wavelength channels. In turn this demands smaller, more efficient modulators, athermal circuits, and improved wavelength division multiplexers. The debate continues as to whether on-chip lasers are necessary for all applications, but an efficient low cost laser would benefit many applications. Multi-layer photonics offers the possibility of increasing the complexity and effectiveness of a given area of chip real estate, but it is a demanding challenge. Low cost packaging (in particular, passive alignment of fibre to waveguide), and effective wafer scale testing strategies, are also essential for mass market applications. Whilst solutions to these challenges would enhance most applications, a derivative technology is emerging, that of Mid Infra-Red (MIR) silicon photonics. This field will build on existing developments, but will require key enhancements to facilitate functionality at longer wavelengths. In common with mainstream silicon photonics, significant developments have been made, but there is still much left to do. Here we summarise some of our recent work towards wafer scale testing, passive alignment, multiplexing, and MIR silicon photonics technology.

  18. Porous silicon: Synthesis and optical properties

    International Nuclear Information System (INIS)

    Naddaf, M.; Awad, F.

    2006-06-01

    Formation of porous silicon by electrochemical etching method of both p and n-type single crystal silicon wafers in HF based solutions has been performed by using three different modes. In addition to DC and pulsed voltage, a novel etching mode is developed to prepare light-emitting porous silicon by applying and holding-up a voltage in gradient steps form periodically, between the silicon wafer and a graphite electrode. Under same equivalent etching conditions, periodic gradient steps voltage etching can yield a porous silicon layer with stronger photoluminescence intensity and blue shift than the porous silicon layer prepared by DC or pulsed voltage etching. It has been found that the holding-up of the applied voltage during the etching process for defined interval of time is another significant future of this method, which highly affects the blue shift. This can be used for tailoring a porous layer with novel properties. The actual mechanism behind the blue shift is not clear exactly, even the experimental observation of atomic force microscope and purist measurements in support with quantum confinement model. It has been seen also from Fourier Transform Infrared study that interplays between O-Si-H and Si-H bond intensities play key role in deciding the efficiency of photoluminescence emission. Study of relative humidity sensing and photonic crystal properties of pours silicon samples has confirmed the advantages of the new adopted etching mode. The sensitivity at room temperature of porous silicon prepared by periodic gradient steps voltage etching was found to be about 70% as compared to 51% and 45% for the porous silicon prepared by DC and pulsed voltage etching, respectively. (author)

  19. VCSELs and silicon light sources exploiting SOI grating mirrors

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Mørk, Jesper

    2012-01-01

    In this talk, novel vertical-cavity laser structure consisting of a dielectric Bragg reflector, a III-V active region, and a high-index-contrast grating made in the Si layer of a silicon-on-insulator (SOI) wafer will be presented. In the Si light source version of this laser structure, the SOI gr...

  20. Quality Tests of Double-Sided Silicon Strip Detectors

    CERN Document Server

    Cambon, T; CERN. Geneva; Fintz, P; Guillaume, G; Jundt, F; Kuhn, C; Lutz, Jean Robert; Pagès, P; Pozdniakov, S; Rami, F; Sparavec, K; Dulinski, W; Arnold, L

    1997-01-01

    The quality of the SiO2 insulator (AC coupling between metal and implanted strips) of double-sided Silicon strip detectors has been studied by using a probe station. Some tests performed on 23 wafers are described and the results are discussed. Remark This note seems to cause problems with ghostview but it can be printed without any problem.

  1. Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, Kuno

    2009-11-06

    The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

  2. Denuded Zone Formation in Germanium Codoped Heavily Phosphorus-Doped Czochralski Silicon

    Science.gov (United States)

    Lin, Li-Xia; Chen, Jia-He; Wu, Peng; Zeng, Yu-Heng; Ma, Xiang-Yang; Yang, De-Ren

    2011-03-01

    The formation of a denuded zone (DZ) by conventional furnace annealing (CFA) and rapid thermal annealing (RTA) based denudation processing is investigated and the gettering of copper (Cu) atoms in germanium co-doped heavily phosphorus-doped Czochralski (GHPCZ) silicon wafers is evaluated. It is suggested that both a good quality defect-free DZ with a suitable width in the sub-surface area and a high density bulk micro-defect (BMD) region could be formed in heavily phosphorus-doped Czochralski (HPCZ) silicon and GHPCZ silicon wafers. This is ascribed to the formation of phosphorus-vacancy (P-V) related complexes and germanium-vacancy (GeV) related complexes. Compared with HPCZ silicon, the DZ width is wider in the GHPCZ silicon sample with CFA-based denudation processing but narrower in the one with two-step RTA pretreatments. These phenomena are ascribed to the enhancing effect of germanium on oxygen out-diffusion movement and oxygen precipitate nucleation, respectively. Furthermore, fairly clean DZs near the surface remain in both the HPCZ and GHPCZ silicon wafers after Cu in-diffusion, except for the HPCZ silicon wafer which underwent denudation processing with a CFA pretreatment, suggesting that germanium doping could improve the gettering of Cu contamination.

  3. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  4. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  5. Silicon fabric for multi-functional applications

    KAUST Repository

    Sevilla, Galo T.

    2013-06-01

    This paper reports a generic process flow to fabricate mechanically flexible and optically semi-transparent thermoelectric generators (TEGs), micro lithium-ion batteries (μLIB) and metal-oxide-semiconductor capacitors (MOSCAPs) on mono-crystalline silicon fabric platforms from standard bulk silicon (100) wafers. All the fabricated devices show outstanding mechanical flexibility and performance, making an important step towards monolithic integration of Energy Chip (self-powered devices) including energy harvesters and electronic devices on flexible platforms. We also report a recyclability process for the remaining bulk substrate after release, allowing us to achieve a low cost flexible platform for high performance applications. © 2013 IEEE.

  6. Microelectronic temperature sensor; silicon temperature sensor

    International Nuclear Information System (INIS)

    Beitner, M.; Kanert, W.; Reichert, H.

    1982-01-01

    The goal of this work was to develop a silicon temperature sensor with a sensitivity and a reliability as high and a tolerance as small as possible, for use in measurement and control. By employing the principle of spreading-resistance, using silicon doped by neutron transmutation, and trimming of the single wafer tolerances of resistance less than +- 5% can be obtained; overstress tests yielded a long-term stability better than 0.2%. Some applications show the advantageous use of this sensor. (orig.) [de

  7. Production of medical radioisotopes in ORNL 86-Inch Cyclotron

    International Nuclear Information System (INIS)

    Skidmore, M.R.

    1975-01-01

    Procedures, targets, and costs are discussed for the production of iodine-123 at the ORNL 86-Inch Cyclotron. The cyclotron is a fixed frequency machine producing 22-MeV proton beams with currents of 3 mA. Flat plate targets are used in the bombardment of readily fabricated metals when highest production rates are necessary, while capsule targets are used when flat plate coatings are difficult or when high production rates are not required. Window targets with metal foils or powders, inorganic compounds, or isotopically enriched materials are also used. (PMA)

  8. Tuning Optical Nonlinearity of Laser-Ablation-Synthesized Silicon Nanoparticles via Doping Concentration

    Directory of Open Access Journals (Sweden)

    Lianwei Chen

    2014-01-01

    Full Text Available Silicon nanoparticles at different doping concentrations are investigated for tuning their optical nonlinear performance. The silicon nanoparticles are synthesized from doped silicon wafers by pulsed laser ablation. Their dispersions in water are studied for both nonlinear absorption and nonlinear refraction properties. It is found that the optical nonlinear performance can be modified by the doping concentration. Nanoparticles at a higher doping concentration exhibit better saturable absorption performance for femtosecond laser pulse, which is ascribed to the free carrier absorption mechanism.

  9. Multi-Step Deep Reactive Ion Etching Fabrication Process for Silicon-Based Terahertz Components

    Science.gov (United States)

    Jung-Kubiak, Cecile (Inventor); Reck, Theodore (Inventor); Chattopadhyay, Goutam (Inventor); Perez, Jose Vicente Siles (Inventor); Lin, Robert H. (Inventor); Mehdi, Imran (Inventor); Lee, Choonsup (Inventor); Cooper, Ken B. (Inventor); Peralta, Alejandro (Inventor)

    2016-01-01

    A multi-step silicon etching process has been developed to fabricate silicon-based terahertz (THz) waveguide components. This technique provides precise dimensional control across multiple etch depths with batch processing capabilities. Nonlinear and passive components such as mixers and multipliers waveguides, hybrids, OMTs and twists have been fabricated and integrated into a small silicon package. This fabrication technique enables a wafer-stacking architecture to provide ultra-compact multi-pixel receiver front-ends in the THz range.

  10. Feature extraction of the wafer probe marks in IC packaging

    Science.gov (United States)

    Tsai, Cheng-Yu; Lin, Chia-Te; Kao, Chen-Ting; Wang, Chau-Shing

    2017-12-01

    This paper presents an image processing approach to extract six features of the probe mark on semiconductor wafer pads. The electrical characteristics of the chip pad must be tested using a probing needle before wire-bonding to the wafer. However, this test leaves probe marks on the pad. A large probe mark area results in poor adhesion forces at the bond ball of the pad, thus leading to undesirable products. In this paper, we present a method to extract six features of the wafer probe marks in IC packaging for further digital image processing.

  11. Silicon-micromachined microchannel plates

    Energy Technology Data Exchange (ETDEWEB)

    Beetz, Charles P. E-mail: NanoSystem@aol.com; Boerstler, Robert; Steinbeck, John; Lemieux, Bryan; Winn, David R. E-mail: winn@fair1.fairfield.edu

    2000-03-11

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of {approx}0.5 to {approx}25 {mu}m, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposited or nucleated in the channels or the first strike surface. Results on resistivity, secondary emission and gain are presented.

  12. Silicon-micromachined microchannel plates

    Science.gov (United States)

    Beetz, Charles P.; Boerstler, Robert; Steinbeck, John; Lemieux, Bryan; Winn, David R.

    2000-03-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of ˜0.5 to ˜25 μm, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200°C, also compatible with high-temperture brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposited or nucleated in the channels or the first strike surface. Results on resistivity, secondary emission and gain are presented.

  13. Silicon-micromachined microchannel plates

    International Nuclear Information System (INIS)

    Beetz, Charles P.; Boerstler, Robert; Steinbeck, John; Lemieux, Bryan; Winn, David R.

    2000-01-01

    Microchannel plates (MCP) fabricated from standard silicon wafer substrates using a novel silicon micromachining process, together with standard silicon photolithographic process steps, are described. The resulting SiMCP microchannels have dimensions of ∼0.5 to ∼25 μm, with aspect ratios up to 300, and have the dimensional precision and absence of interstitial defects characteristic of photolithographic processing, compatible with positional matching to silicon electronics readouts. The open channel areal fraction and detection efficiency may exceed 90% on plates up to 300 mm in diameter. The resulting silicon substrates can be converted entirely to amorphous quartz (qMCP). The strip resistance and secondary emission are developed by controlled depositions of thin films, at temperatures up to 1200 deg. C, also compatible with high-temperature brazing, and can be essentially hydrogen, water and radionuclide-free. Novel secondary emitters and cesiated photocathodes can be high-temperature deposited or nucleated in the channels or the first strike surface. Results on resistivity, secondary emission and gain are presented

  14. Improved surface quality of anisotropically etched silicon {111} planes for mm-scale optics

    International Nuclear Information System (INIS)

    Cotter, J P; Hinds, E A; Zeimpekis, I; Kraft, M

    2013-01-01

    We have studied the surface quality of millimetre-scale optical mirrors produced by etching CZ and FZ silicon wafers in potassium hydroxide to expose the {111} planes. We find that the FZ surfaces have four times lower noise power at spatial frequencies up to 500 mm −1 . We conclude that mirrors made using FZ wafers have higher optical quality. (technical note)

  15. Crack Propagation Modeling in Silicon: A Comprehensive Thermomechanical Finite-Element Model Approach for Power Devices

    OpenAIRE

    Calvez, D.; Roqueta, F.; Jacques, S.; Bechou, L.; Ousten, Y.; Ducret, S.

    2014-01-01

    International audience; Wafer handling during the manufacturing process introduces microcracks and flaws at the wafer edge. This paper aims at determining whether an initial crack would be able to propagate through the silicon active region of power devices when it is subjected to high electrothermal loads during operating conditions or accelerated thermal cycling tests. Failure analysis performed on these power devices has revealed some typical propagation paths. The most critical crack prop...

  16. A Radiation-Tolerant, Low-Power Non-Volatile Memory Based on Silicon Nanocrystal Quantum Dots

    Science.gov (United States)

    Bell, L. D.; Boer, E. A.; Ostraat, M. L.; Brongersma, M. L.; Flagan, R. C.; Atwater, H. A.; deBlauwe, J.; Green, M. L.

    2001-01-01

    Nanocrystal nonvolatile floating-gate memories are a good candidate for space applications - initial results suggest they are fast, more reliable and consume less power than conventional floating gate memories. In the nanocrystal based NVM device, charge is not stored on a continuous polysilicon layer (so-called floating gate), but instead on a layer of discrete nanocrystals. Charge injection and storage in dense arrays of silicon nanocrystals in SiO2 is a critical aspect of the performance of potential nanocrystal flash memory structures. The ultimate goal for this class of devices is few- or single-electron storage in a small number of nanocrystal elements. In addition, the nanocrystal layer fabrication technique should be simple, 8-inch wafer compatible and well controlled in program/erase threshold voltage swing was seen during 100,000 program and erase cycles. Additional near-term goals for this project include extensive testing for radiation hardness and the development of artificial layered tunnel barrier heterostructures which have the potential for large speed enhancements for read/write of nanocrystal memory elements, compared with conventional flash devices. Additional information is contained in the original extended abstract.

  17. Integrated optical MEMS using through-wafer vias and bump-bonding.

    Energy Technology Data Exchange (ETDEWEB)

    McCormick, Frederick Bossert; Frederick, Scott K.

    2008-01-01

    This LDRD began as a three year program to integrate through-wafer vias, micro-mirrors and control electronics with high-voltage capability to yield a 64 by 64 array of individually controllable micro-mirrors on 125 or 250 micron pitch with piston, tip and tilt movement. The effort was a mix of R&D and application. Care was taken to create SUMMiT{trademark} (Sandia's ultraplanar, multilevel MEMS technology) compatible via and mirror processes, and the ultimate goal was to mate this MEMS fabrication product to a complementary metal-oxide semiconductor (CMOS) electronics substrate. Significant progress was made on the via and mirror fabrication and design, the attach process development as well as the electronics high voltage (30 volt) and control designs. After approximately 22 months, the program was ready to proceed with fabrication and integration of the electronics, final mirror array, and through wafer vias to create a high resolution OMEMS array with individual mirror electronic control. At this point, however, mission alignment and budget constraints reduced the last year program funding and redirected the program to help support the through-silicon via work in the Hyper-Temporal Sensors (HTS) Grand Challenge (GC) LDRD. Several months of investigation and discussion with the HTS team resulted in a revised plan for the remaining 10 months of the program. We planned to build a capability in finer-pitched via fabrication on thinned substrates along with metallization schemes and bonding techniques for very large arrays of high density interconnects (up to 2000 x 2000 vias). Through this program, Sandia was able to build capability in several different conductive through wafer via processes using internal and external resources, MEMS mirror design and fabrication, various bonding techniques for arrayed substrates, and arrayed electronics control design with high voltage capability.

  18. High Performance Wafer-Based Capillary Electrochromatography, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Los Gatos Research proposes to develop wafer-based capillary electrochromatography for lab-on-a-chip (LOC) applications. These microfluidic devices will be...

  19. Effects of Laser Energy Density on Silicon Nanoparticles Produced Using Laser Ablation in Liquid

    Science.gov (United States)

    Kobayashi, Hiroki; Chewchinda, Pattarin; Ohtani, Hiroyuki; Odawara, Osamu; Wada, Hiroyuki

    2013-06-01

    We investigated the morphology of silicon nanoparticles prepared using laser ablation in liquid through varying the energy density and laser irradiation time. Silicon nanoparticles were prepared using laser ablation in liquid. A silicon wafer was irradiated in ethanol using a laser beam (Nd: YAG/second harmonic generation, 532 nm). Crystalline silicon nanoparticles approximately 6 nm in size were observed by TEM observation. The quantity of silicon nanoparticles proportionally increased with an increase in energy density greater than the laser ablation threshold. This quantity also increased with an increase in laser irradiation time without saturation due to absorption of the nanoparticles in liquid in the light path.

  20. Charge on luminous bodies resembling natural ball lightning produced via electrical arcs through lump silicon

    Science.gov (United States)

    Porter, Christina L.; Miley, Galen P.; Griffiths, David J.; Sánchez, Erik

    2014-12-01

    A phenomenon resembling natural ball lightning can be produced via electrical arcing through silicon. We use lump silicon instead of silicon wafers to achieve higher production rates and larger, longer-lived luminous balls than previously reported. The luminous balls consist of a silicon core surrounded by a porous network of loosely bound silicon dioxide nanoparticles. We find that the balls carry a small net charge on the order of 10-12 C and propose that the nanoparticles are electrostatically bound to the core due to this charge.

  1. Fabrication and Characterization of Capacitive Micromachined Ultrasonic Transducers with Low-Temperature Wafer Direct Bonding

    Directory of Open Access Journals (Sweden)

    Xiaoqing Wang

    2016-12-01

    Full Text Available This paper presents a fabrication method of capacitive micromachined ultrasonic transducers (CMUTs by wafer direct bonding, which utilizes both the wet chemical and O2plasma activation processes to decrease the bonding temperature to 400 °C. Two key surface properties, the contact angle and surface roughness, are studied in relation to the activation processes, respectively. By optimizing the surface activation parameters, a surface roughness of 0.274 nm and a contact angle of 0° are achieved. The infrared images and static deflection of devices are assessed to prove the good bonding effect. CMUTs having silicon membranes with a radius of 60 μm and a thickness of 2 μm are fabricated. Device properties have been characterized by electrical and acoustic measurements to verify their functionality and thus to validate this low-temperature process. A resonant frequency of 2.06 MHz is obtained by the frequency response measurements. The electrical insertion loss and acoustic signal have been evaluated. This study demonstrates that the CMUT devices can be fabricated by low-temperature wafer direct bonding, which makes it possible to integrate them directly on top of integrated circuit (IC substrates.

  2. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  3. Advanced single-wafer sequential multiprocessing techniques for semiconductor device fabrication

    International Nuclear Information System (INIS)

    Moslehi, M.M.; Davis, C.

    1989-01-01

    Single-wafer integrated in-situ multiprocessing (SWIM) is recognized as the future trend for advanced microelectronics production in flexible fast turn- around computer-integrated semiconductor manufacturing environments. The SWIM equipment technology and processing methodology offer enhanced equipment utilization, improved process reproducibility and yield, and reduced chip manufacturing cost. They also provide significant capabilities for fabrication of new and improved device structures. This paper describes the SWIM techniques and presents a novel single-wafer advanced vacuum multiprocessing technology developed based on the use of multiple process energy/activation sources (lamp heating and remote microwave plasma) for multilayer epitaxial and polycrystalline semiconductor as well as dielectric film processing. Based on this technology, multilayer in-situ-doped homoepitaxial silicon and heteroepitaxial strained layer Si/Ge x Si 1 - x /Si structures have been grown and characterized. The process control and the ultimate interfacial abruptness of the layer-to-layer transition widths in the device structures prepared by this technology will challenge the MBE techniques in multilayer epitaxial growth applications

  4. Wafer level fabrication of single cell dispenser chips with integrated electrodes for particle detection

    International Nuclear Information System (INIS)

    Schoendube, Jonas; Yusof, Azmi; Kalkandjiev, Kiril; Zengerle, Roland; Koltay, Peter

    2015-01-01

    This work presents the microfabrication and experimental evaluation of a dispenser chip, designed for isolation and printing of single cells by combining impedance sensing and drop-on-demand dispensing. The dispenser chip features 50  ×  55 µm (width × height) microchannels, a droplet generator and microelectrodes for impedance measurements. The chip is fabricated by sandwiching a dry film photopolymer (TMMF) between a silicon and a Pyrex wafer. TMMF has been used to define microfluidic channels, to serve as low temperature (75 °C) bonding adhesive and as etch mask during 300 µm deep HF etching of the Pyrex wafer. Due to the novel fabrication technology involving the dry film resist, it became possible to fabricate facing electrodes at the top and bottom of the channel and to apply electrical impedance sensing for particle detection with improved performance. The presented microchip is capable of dispensing liquid and detecting microparticles via impedance measurement. Single polystyrene particles of 10 µm size could be detected with a mean signal amplitude of 0.39  ±  0.13 V (n=439) at particle velocities of up to 9.6 mm s −1 inside the chip. (paper)

  5. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  6. Optical simulations for design, alignment, and performance prediction of silicon pore optics for the ATHENA x-ray telescope

    DEFF Research Database (Denmark)

    Spiga, D.; Della Monica Ferreira, Desiree; Shortt, B.

    2017-01-01

    The ATHENA X-ray observatory is a large-class ESA approved mission, with launch scheduled in 2028. The technology of silicon pore optics (SPO) was selected as baseline to assemble ATHENA’s optic with hundreds of mirror modules, obtained by stacking wedged and ribbed silicon wafer plates onto si...

  7. Silicon-based metallic micro grid for electron field emission

    International Nuclear Information System (INIS)

    Kim, Jaehong; Jeon, Seok-Gy; Kim, Jung-Il; Kim, Geun-Ju; Heo, Duchang; Shin, Dong Hoon; Sun, Yuning; Lee, Cheol Jin

    2012-01-01

    A micro-scale metal grid based on a silicon frame for application to electron field emission devices is introduced and experimentally demonstrated. A silicon lattice containing aperture holes with an area of 80 × 80 µm 2 and a thickness of 10 µm is precisely manufactured by dry etching the silicon on one side of a double-polished silicon wafer and by wet etching the opposite side. Because a silicon lattice is more rigid than a pure metal lattice, a thin layer of Au/Ti deposited on the silicon lattice for voltage application can be more resistant to the geometric stress caused by the applied electric field. The micro-fabrication process, the images of the fabricated grid with 88% geometric transparency and the surface profile measurement after thermal feasibility testing up to 700 °C are presented. (paper)

  8. Output blue light evaluation for phosphor based smart white LED wafer level packages.

    Science.gov (United States)

    Kolahdouz, Zahra; Rostamian, Ali; Kolahdouz, Mohammadreza; Ma, Teng; van Zeijl, Henk; Zhang, Kouchi

    2016-02-22

    This study presents a blue light detector for evaluating the output light of phosphor based white LED package. It is composed of a silicon stripe-shaped photodiode designed and implemented in a 2 μm BiCMOS process which can be used for wafer level integration of different passive and active devices all in just 5 lithography steps. The final device shows a high selectivity to blue light. The maximum responsivity at 480 nm is matched with the target blue LED illumination. The designed structure have better responsivity compared to simple photodiode structure due to reducing the effect of dead layer formation close to the surface because of implantation. It has also a two-fold increase in the responsivity and quantum efficiency compared to previously similar published sensors.

  9. Micro-characterisation of Si wafers by high-pressure thermopower technique

    International Nuclear Information System (INIS)

    Ovsyannikov, Sergey V.; Shchennikov Jr, Vsevolod V.; Shaydarova, Nadezda A.; Shchennikov, Vladimir V.; Misiuk, Andrzej; Yang Deren; Antonova, Irina V.; Shamin, Sergey N.

    2006-01-01

    In the present work a set of Czochralski-grown silicon wafers (Cz-Si) differently pre-treated (annealed at high temperatures in pressure medium, doped with nitrogen, implanted with high-energy hydrogen ions) has been characterised by high-pressure thermopower S technique in the phase transitions region (0-20GPa). The shifts were observed in pressure of semiconductor-metal phase transition P t determined from the S(P) under pre-treatments. For the first time, correlation dependence has been established between high-pressure thermoelectric properties on the one hand and concentration of residual interstitial oxygen c O (which is always present in Cz-Si) on the other hand. The dependence exhibited a maximum of P t near c O ∼9x10 17 cm -3

  10. Unveiling the Formation Pathway of Single Crystalline Porous Silicon Nanowires

    Science.gov (United States)

    Zhong, Xing; Qu, Yongquan; Lin, Yung-Chen; Liao, Lei; Duan, Xiangfeng

    2011-01-01

    Porous silicon nanowire is emerging as an interesting material system due to its unique combination of structural, chemical, electronic, and optical properties. To fully understand their formation mechanism is of great importance for controlling the fundamental physical properties and enabling potential applications. Here we present a systematic study to elucidate the mechanism responsible for the formation of porous silicon nanowires in a two-step silver-assisted electroless chemical etching method. It is shown that silicon nanowire arrays with various porosities can be prepared by varying multiple experimental parameters such as the resistivity of the starting silicon wafer, the concentration of oxidant (H2O2) and the amount of silver catalyst. Our study shows a consistent trend that the porosity increases with the increasing wafer conductivity (dopant concentration) and oxidant (H2O2) concentration. We further demonstrate that silver ions, formed by the oxidation of silver, can diffuse upwards and re-nucleate on the sidewalls of nanowires to initiate new etching pathways to produce porous structure. The elucidation of this fundamental formation mechanism opens a rational pathway to the production of wafer-scale single crystalline porous silicon nanowires with tunable surface areas ranging from 370 m2·g−1 to 30 m2·g−1, and can enable exciting opportunities in catalysis, energy harvesting, conversion, storage, as well as biomedical imaging and therapy. PMID:21244020

  11. Fast determination of impurities in metallurgical grade silicon for photovoltaics by instrumental neutron activation analysis

    International Nuclear Information System (INIS)

    Hampel, J.; Boldt, F.M.; Gerstenberg, H.; Hampel, G.; Kratz, J.V.; Reber, S.; Wiehl, N.

    2011-01-01

    Standard wafer solar cells are made of near-semiconductor quality silicon. This high quality material makes up a significant part of the total costs of a solar module. Therefore, new concepts with less expensive so called solar grade silicon directly based on physiochemically upgraded metallurgical grade silicon are investigated. Metallurgical grade silicon contains large amounts of impurities, mainly transition metals like Fe, Cr, Mn, and Co, which degrade the minority carrier lifetime and thus the solar cell efficiency. A major reduction of the transition metal content occurs during the unidirectional crystallization due to the low segregation coefficient between the solid and liquid phase. A further reduction of the impurity level has to be done by gettering procedures applied to the silicon wafers. The efficiency of such cleaning procedures of metallurgical grade silicon is studied by instrumental neutron activation analysis (INAA). Small sized silicon wafers of approximately 200 mg with and without gettering step were analyzed. To accelerate the detection of transition metals in a crystallized silicon ingot, experiments of scanning whole vertical silicon columns with a diameter of approximately 1 cm by gamma spectroscopy were carried out. It was demonstrated that impurity profiles can be obtained in a comparably short time. Relatively constant transition metal ratios were found throughout an entire silicon ingot. This led to the conclusion that the determination of several metal profiles might be possible by the detection of only one 'leading element'. As the determination of Mn in silicon can be done quite fast compared to elements like Fe, Cr, and Co, it could be used as a rough marker for the overall metal concentration level. Thus, a fast way to determine impurities in photovoltaic silicon material is demonstrated. - Highlights: → We demonstrate a fast way to determine impurities in photovoltaic silicon by NAA. → We make first experiments of locally

  12. Effect of Subgrains on the Performance of Mono-Like Crystalline Silicon Solar Cells

    Directory of Open Access Journals (Sweden)

    Su Zhou

    2013-01-01

    Full Text Available The application of Czochralski (Cz monocrystalline silicon material in solar cells is limited by its high cost and serious light-induced degradation. The use of cast multicrystalline silicon is also hindered by its high dislocation densities and high surface reflectance after texturing. Mono-like crystalline silicon is a promising material because it has the advantages of both mono- and multicrystalline silicon. However, when mono-like wafers are made into cells, the efficiencies of a batch of wafers often fluctuate within a wide range of >1% (absolute. In this work, mono-like wafers are classified by a simple process and fabricated into laser doping selective emitter cells. The effect and mechanism of subgrains on the performance of mono-like crystalline silicon solar cells are studied. The results show that the efficiency of mono-like crystalline silicon solar cells significantly depends on material defects that appear as subgrains on an alkaline textured surface. These subgrains have an almost negligible effect on the optical performance, shunt resistance, and junction recombination but significantly affect the minority carrier diffusion length and quantum efficiency within a long wavelength range. Finally, an average efficiency of 18.2% is achieved on wafers with hardly any subgrain but with a small-grain band.

  13. Impurity gettering in silicon using cavities formed by helium implantation and annealing

    Science.gov (United States)

    Myers, Jr., Samuel M.; Bishop, Dawn M.; Follstaedt, David M.

    1998-01-01

    Impurity gettering in silicon wafers is achieved by a new process consisting of helium ion implantation followed by annealing. This treatment creates cavities whose internal surfaces are highly chemically reactive due to the presence of numerous silicon dangling bonds. For two representative transition-metal impurities, copper and nickel, the binding energies at cavities were demonstrated to be larger than the binding energies in precipitates of metal silicide, which constitutes the basis of most current impurity gettering. As a result the residual concentration of such impurities after cavity gettering is smaller by several orders of magnitude than after precipitation gettering. Additionally, cavity gettering is effective regardless of the starting impurity concentration in the wafer, whereas precipitation gettering ceases when the impurity concentration reaches a characteristic solubility determined by the equilibrium phase diagram of the silicon-metal system. The strong cavity gettering was shown to induce dissolution of metal-silicide particles from the opposite side of a wafer.

  14. Wafer-Level Packaging Method for RF MEMS Applications Using Pre-Patterned BCB Polymer

    Directory of Open Access Journals (Sweden)

    Zhuhao Gong

    2018-02-01

    Full Text Available A radio-frequency micro-electro-mechanical system (RF MEMS wafer-level packaging (WLP method using pre-patterned benzo-cyclo-butene (BCB polymers with a high-resistivity silicon cap is proposed to achieve high bonding quality and excellent RF performance. In this process, the BCB polymer was pre-defined to form the sealing ring and bonding layer by the spin-coating and patterning of photosensitive BCB before the cavity formation. During anisotropic wet etching of the silicon wafer to generate the housing cavity, the BCB sealing ring was protected by a sputtered Cr/Au (chromium/gold layer. The average measured thickness of the BCB layer was 5.9 μm. In contrast to the conventional methods of spin-coating BCB after fabricating cavities, the pre-patterned BCB method presented BCB bonding layers with better quality on severe topography surfaces in terms of increased uniformity of thickness and better surface flatness. The observation of the bonded layer showed that no void or gap formed on the protruding coplanar waveguide (CPW lines. A shear strength test was experimentally implemented as a function of the BCB widths in the range of 100–400 μm. The average shear strength of the packaged device was higher than 21.58 MPa. A RF MEMS switch was successfully packaged using this process with a negligible impact on the microwave characteristics and a significant improvement in the lifetime from below 10 million to over 1 billion. The measured insertion loss of the packaged RF MEMS switch was 0.779 dB and the insertion loss deterioration caused by the package structure was less than 0.2 dB at 30 GHz.

  15. Black silicon with black bus-bar strings

    DEFF Research Database (Denmark)

    Davidsen, Rasmus Schmidt; Tang, Peter Torben; Mizushima, Io

    2016-01-01

    We present the combination of black silicon texturing and blackened bus-bar strings as a potential method for obtaining all-black solar panels, while using conventional, front-contacted solar cells. Black silicon was realized by mask-less reactive ion etching resulting in total, average reflectance...... below 0.5% across a 156x156 mm2 silicon wafer. Black bus-bars were realized by oxidized copper resulting in reflectance below 3% in the entire visible wavelength range. The combination of these two technologies may result in aesthetic, all-black panels based on conventional, front-contacted solar cells...

  16. Silicon strip sensor R and D activities in Korea

    International Nuclear Information System (INIS)

    Park, H.

    2004-01-01

    We report on the development of the double sided silicon, DC-coupled detectors (DSSD) for tracking applications. The DSSD are being fabricated with experience of producing the Silicon Charge Detector (SCD) which consists of 182 silicon PIN diode sensors for the charge identification of the incoming particles in the CREAM (Cosmic Ray Energetics And Mass) experiment. A DSSD consists of 512 readout channels and the implanted strips are orthogonal to each other on opposite sides of the detector wafer. The design of the DSSD and its various components are presented. Very preliminary measurement results from the first batch run are also discussed. (author)

  17. Rapid diffusion of molybdenum trace contamination in silicon

    International Nuclear Information System (INIS)

    Tobin, S.P.; Greenwald, A.C.; Wolfson, R.G.; Meier, D.L.; Drevinsky, P.J.

    1985-01-01

    Molybdenum contamination has been detected in silicon epitaxial layers and substrate wafers after processing in any one of several epitaxial silicon reactors. Greatly reduced minority carrier diffusion lengths and lifetimes are consistent with Mo concentrations measured by DLTS in the 10 12 and 10 13 cm -3 ranges. Depth profiling of diffusion length and the Mo deep level show much greater penetration than expected from previous reports of Mo as a slow diffuser. The data indicate a lower limit of 10 -8 cm 2 /sec for the diffusion coefficient of Mo in silicon at 1200 0 C, consistent with high diffusivities measured for other transition metals

  18. Remote target removal for the Oak Ridge 86-inch Cyclotron

    International Nuclear Information System (INIS)

    Walls, A.A.

    1982-01-01

    A remotely operated target remover has been plaed in operation at the 86-Inch Cyclotron located in Oak Ridge. The system provides for the remote removal of a target from inside the cyclotron, loading it into a cask, and the removal of the cask from the 1.5 m (5-ft) shielding walls. The remote system consists of multiple electrical and pneumatically operated equipment which is designed for controlled step-by-step operation, operated with an electrical control panel, and monitored by a television system. The target remover has reduced the radiation exposures to operating personnel at the facility and has increased the effective operating time. The system is fast, requires a minimum of skill to operate, and has demonstrated both reliability and durability

  19. Seismic fragility test of a 6-inch diameter pipe system

    International Nuclear Information System (INIS)

    Chen, W.P.; Onesto, A.T.; DeVita, V.

    1987-02-01

    This report contains the test results and assessments of seismic fragility tests performed on a 6-inch diameter piping system. The test was funded by the US Nuclear Regulatory Commission (NRC) and conducted by ETEC. The objective of the test was to investigate the ability of a representative nuclear piping system to withstand high level dynamic seismic and other loadings. Levels of loadings achieved during seismic testing were 20 to 30 times larger than normal elastic design evaluations to ASME Level D limits would permit. Based on failure data obtained during seismic and other dynamic testing, it was concluded that nuclear piping systems are inherently able to withstand much larger dynamic seismic loadings than permitted by current design practice criteria or predicted by the probabilistic risk assessment (PRA) methods and several proposed nonlinear methods of failure analysis

  20. Controlling the transmission of ultrahigh frequency bulk acoustic waves in silicon by 45° mirrors.

    Science.gov (United States)

    Wang, Shengxiang; Gao, Jiaming; Carlier, Julien; Campistron, Pierre; NDieguene, Assane; Guo, Shishang; Matar, Olivier Bou; Dorothee, Debavelaere-Callens; Nongaillard, Bertrand

    2011-07-01

    In this paper, we present a feasible microsystem in which the direction of localized ultrahigh frequency (∼1GHz) bulk acoustic wave can be controlled in a silicon wafer. Deep etching technology on the silicon wafer makes it possible to achieve high aspect ratio etching patterns which can be used to control bulk acoustic wave to transmit in the directions parallel to the surface of the silicon wafer. Passive 45° mirror planes obtained by wet chemical etching were employed to reflect the bulk acoustic wave. Zinc oxide (ZnO) thin film transducers were deposited by radio frequency sputtering with a thickness of about 1μm on the other side of the wafer, which act as emitter/receptor after aligned with the mirrors. Two opponent vertical mirrors were inserted between the 45° mirrors to guide the transmission of the acoustic waves. The propagation of the bulk acoustic wave was studied with simulations and the characterization of S(21) scattering parameters, indicating that the mirrors were efficient to guide bulk acoustic waves in the silicon wafer. Copyright © 2011 Elsevier B.V. All rights reserved.

  1. Light Enhanced Hydrofluoric Acid Passivation: A Sensitive Technique for Detecting Bulk Silicon Defects

    Science.gov (United States)

    Grant, Nicholas E.

    2016-01-01

    A procedure to measure the bulk lifetime (>100 µsec) of silicon wafers by temporarily attaining a very high level of surface passivation when immersing the wafers in hydrofluoric acid (HF) is presented. By this procedure three critical steps are required to attain the bulk lifetime. Firstly, prior to immersing silicon wafers into HF, they are chemically cleaned and subsequently etched in 25% tetramethylammonium hydroxide. Secondly, the chemically treated wafers are then placed into a large plastic container filled with a mixture of HF and hydrochloric acid, and then centered over an inductive coil for photoconductance (PC) measurements. Thirdly, to inhibit surface recombination and measure the bulk lifetime, the wafers are illuminated at 0.2 suns for 1 min using a halogen lamp, the illumination is switched off, and a PC measurement is immediately taken. By this procedure, the characteristics of bulk silicon defects can be accurately determined. Furthermore, it is anticipated that a sensitive RT surface passivation technique will be imperative for examining bulk silicon defects when their concentration is low (<1012 cm-3). PMID:26779939

  2. PV Cz silicon manufacturing technology improvements

    Science.gov (United States)

    Jester, T.

    1995-09-01

    This describes work done in the final phase of a 3-y, 3-phase contract to demonstrate cost reductions and improvements in manufacturing technology. The work focused on near-term projects in the SSI (Siemens Solar Industries) Czochralski (Cz) manufacturing facility in Camarillo, CA; the final phase was concentrated in areas of crystal growth, wafer technology, and environmental, safety, and health issues. During this period: (1) The crystal-growing operation improved with increased growth capacity; (2) Wafer processing with wire saws continued to progress; the wire saws yielded almost 50 percent more wafers per inch in production. The wire saws needs less etching, too; (3) Cell processing improvements focused on better handling and higher mechanical yield. The cell electrical distribution improved with a smaller standard deviation in the distribution; and (4) Module designs for lower material and labor costs continued, with focus on a new junction box, larger modules with larger cells, and less costly framing techniques. Two modules demonstrating these cost reductions were delivered during this phase.

  3. Towards large size substrates for III-V co-integration made by direct wafer bonding on Si

    Directory of Open Access Journals (Sweden)

    N. Daix

    2014-08-01

    Full Text Available We report the first demonstration of 200 mm InGaAs-on-insulator (InGaAs-o-I fabricated by the direct wafer bonding technique with a donor wafer made of III-V heteroepitaxial structure grown on 200 mm silicon wafer. The measured threading dislocation density of the In0.53Ga0.47As (InGaAs active layer is equal to 3.5 × 109 cm−2, and it does not degrade after the bonding and the layer transfer steps. The surface roughness of the InGaAs layer can be improved by chemical-mechanical-polishing step, reaching values as low as 0.4 nm root-mean-square. The electron Hall mobility in 450 nm thick InGaAs-o-I layer reaches values of up to 6000 cm2/Vs, and working pseudo-MOS transistors are demonstrated with an extracted electron mobility in the range of 2000–3000 cm2/Vs. Finally, the fabrication of an InGaAs-o-I substrate with the active layer as thin as 90 nm is achieved with a Buried Oxide of 50 nm. These results open the way to very large scale production of III-V-o-I advanced substrates for future CMOS technology nodes.

  4. Effect of microstructure on the arsenic profile in implanted silicon

    International Nuclear Information System (INIS)

    Coghlan, W.A.; Rhee, M.H.; Williams, J.M.; Streit, L.A.; Williams, P.

    1985-10-01

    According to an irradiation damage model, the profile of an implanted ion at temperature great enough for diffusion to occur will depend on the sink density in the material. To test this model, pure silicon wafers were prepared with high and low dislocation densities. These wafers were implanted with about 5 x 10 19 As +2 /m 2 at 77 0 K, 300 0 C, and 600 0 C. After implanting the profiles were measured using Rutherford backscattering spectroscopy and secondary ion mass spectroscopy. The observed spreading of the As-profile contradicts initial theoretical predictions. Further speculation is presented to explain the differences

  5. Excellent Silicon Surface Passivation Achieved by Industrial Inductively Coupled Plasma Deposited Hydrogenated Intrinsic Amorphous Silicon Suboxide

    Directory of Open Access Journals (Sweden)

    Jia Ge

    2014-01-01

    Full Text Available We present an alternative method of depositing a high-quality passivation film for heterojunction silicon wafer solar cells, in this paper. The deposition of hydrogenated intrinsic amorphous silicon suboxide is accomplished by decomposing hydrogen, silane, and carbon dioxide in an industrial remote inductively coupled plasma platform. Through the investigation on CO2 partial pressure and process temperature, excellent surface passivation quality and optical properties are achieved. It is found that the hydrogen content in the film is much higher than what is commonly reported in intrinsic amorphous silicon due to oxygen incorporation. The observed slow depletion of hydrogen with increasing temperature greatly enhances its process window as well. The effective lifetime of symmetrically passivated samples under the optimal condition exceeds 4.7 ms on planar n-type Czochralski silicon wafers with a resistivity of 1 Ωcm, which is equivalent to an effective surface recombination velocity of less than 1.7 cms−1 and an implied open-circuit voltage (Voc of 741 mV. A comparison with several high quality passivation schemes for solar cells reveals that the developed inductively coupled plasma deposited films show excellent passivation quality. The excellent optical property and resistance to degradation make it an excellent substitute for industrial heterojunction silicon solar cell production.

  6. Integrated Arrays on Silicon at Terahertz Frequencies

    Science.gov (United States)

    Chattopadhayay, Goutam; Lee, Choonsup; Jung, Cecil; Lin, Robert; Peralta, Alessandro; Mehdi, Imran; Llombert, Nuria; Thomas, Bertrand

    2011-01-01

    In this paper we explore various receiver font-end and antenna architecture for use in integrated arrays at terahertz frequencies. Development of wafer-level integrated terahertz receiver front-end by using advanced semiconductor fabrication technologies and use of novel integrated antennas with silicon micromachining are reported. We report novel stacking of micromachined silicon wafers which allows for the 3-dimensional integration of various terahertz receiver components in extremely small packages which easily leads to the development of 2- dimensioanl multi-pixel receiver front-ends in the terahertz frequency range. We also report an integrated micro-lens antenna that goes with the silicon micro-machined front-end. The micro-lens antenna is fed by a waveguide that excites a silicon lens antenna through a leaky-wave or electromagnetic band gap (EBG) resonant cavity. We utilized advanced semiconductor nanofabrication techniques to design, fabricate, and demonstrate a super-compact, low-mass submillimeter-wave heterodyne frontend. When the micro-lens antenna is integrated with the receiver front-end we will be able to assemble integrated heterodyne array receivers for various applications such as multi-pixel high resolution spectrometer and imaging radar at terahertz frequencies.

  7. Low-Cost, Manufacturable, 6-Inch Wafer Bonding Process for Next-Generation 5-Junction IMM+Ge Photovoltaic Devices, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — To continue the trend towards ever more efficient photovoltaic devices, next-generation multi-junction cells will be based on increasingly complex structures. These...

  8. Critical dimension control for prevention of wafer-to-wafer and module-to-module difference

    Science.gov (United States)

    Deguchi, Masatoshi; Tanaka, Kouichirou; Nagatani, Naohiko; Miyata, Yuichiro; Yamashita, Mitsuo; Minami, Yoshiaki; Matsuyama, Yuji

    2004-05-01

    In recent years, the worldwide semiconductor market has changed drastically, and it is expected that the digital device market will continue to expand towards general consumer electronics and away from the personal computers that have been the core of the market. To accommodate this shift, the new devices will be diversified with improved productivity, higher process yield, and higher precision. Clean Track (LITHIUS) design also has been changed drastically to maintain equal productivity with new high throughput exposure equipment. Design changes include increasing the number of processing chambers by stacking reduced size modules in order to meet high throughput and small footprint requirements. However, this design change concept raises concerns about increased wafer-to-wafer difference (WtW) and module-to-module different (MtM). These variations can result in lower process yield and have a negative effect on design rule shrinkage. The primary causes of WtW difference and MtM difference stem from minute module hardware variations, module height differences, and module parameter adjustment differences during the installation of the tool. Previous Clean Track development focused mainly on reduction of module hardware difference as an approach to reduce WtW variation. However, to further improve lot level uniformity, it is necessary to reduce module height difference factors within the system and module adjustment disparities such as plate temperature calibrations. Highly temperature sensitive ArF processes have necessitated precise manual PEB temperature adjustments. These calibrations are labor intensive and require many field hours to ensure optimal CD uniformity. Therefore, an auto temperature measurement and adjustment tool is developed to eliminate the human error due to manual adjustment and minimize adjustment time. In order to meet demands for design rules shrinkage and increased process uniformity we minimized the WtW and MtM difference by using thermal

  9. Suppression of interfacial voids formation during silane (SiH4)-based silicon oxide bonding with a thin silicon nitride capping layer

    Science.gov (United States)

    Lee, Kwang Hong; Bao, Shuyu; Wang, Yue; Fitzgerald, Eugene A.; Seng Tan, Chuan

    2018-01-01

    The material properties and bonding behavior of silane-based silicon oxide layers deposited by plasma-enhanced chemical vapor deposition were investigated. Fourier transform infrared spectroscopy was employed to determine the chemical composition of the silicon oxide films. The incorporation of hydroxyl (-OH) groups and moisture absorption demonstrates a strong correlation with the storage duration for both as-deposited and annealed silicon oxide films. It is observed that moisture absorption is prevalent in the silane-based silicon oxide film due to its porous nature. The incorporation of -OH groups and moisture absorption in the silicon oxide films increase with the storage time (even in clean-room environments) for both as-deposited and annealed silicon oxide films. Due to silanol condensation and silicon oxidation reactions that take place at the bonding interface and in the bulk silicon, hydrogen (a byproduct of these reactions) is released and diffused towards the bonding interface. The trapped hydrogen forms voids over time. Additionally, the absorbed moisture could evaporate during the post-bond annealing of the bonded wafer pair. As a consequence, defects, such as voids, form at the bonding interface. To address the problem, a thin silicon nitride capping film was deposited on the silicon oxide layer before bonding to serve as a diffusion barrier to prevent moisture absorption and incorporation of -OH groups from the ambient. This process results in defect-free bonded wafers.

  10. Atomic layer lithography of wafer-scale nanogap arrays for extreme confinement of electromagnetic waves.

    Science.gov (United States)

    Chen, Xiaoshu; Park, Hyeong-Ryeol; Pelton, Matthew; Piao, Xianji; Lindquist, Nathan C; Im, Hyungsoon; Kim, Yun Jung; Ahn, Jae Sung; Ahn, Kwang Jun; Park, Namkyoo; Kim, Dai-Sik; Oh, Sang-Hyun

    2013-01-01

    Squeezing light through nanometre-wide gaps in metals can lead to extreme field enhancements, nonlocal electromagnetic effects and light-induced electron tunnelling. This intriguing regime, however, has not been readily accessible to experimentalists because of the lack of reliable technology to fabricate uniform nanogaps with atomic-scale resolution and high throughput. Here we introduce a new patterning technology based on atomic layer deposition and simple adhesive-tape-based planarization. Using this method, we create vertically oriented gaps in opaque metal films along the entire contour of a millimetre-sized pattern, with gap widths as narrow as 9.9 Å, and pack 150,000 such devices on a 4-inch wafer. Electromagnetic waves pass exclusively through the nanogaps, enabling background-free transmission measurements. We observe resonant transmission of near-infrared waves through 1.1-nm-wide gaps (λ/1,295) and measure an effective refractive index of 17.8. We also observe resonant transmission of millimetre waves through 1.1-nm-wide gaps (λ/4,000,000) and infer an unprecedented field enhancement factor of 25,000.

  11. Through-glass copper via using the glass reflow and seedless electroplating processes for wafer-level RF MEMS packaging

    International Nuclear Information System (INIS)

    Lee, Ju-Yong; Lee, Sung-Woo; Lee, Seung-Ki; Park, Jae-Hyoung

    2013-01-01

    We present a novel method for the fabrication of void-free copper-filled through-glass-vias (TGVs), and their application to the wafer-level radio frequency microelectromechanical systems (RF MEMS) packaging scheme. By using the glass reflow process with a patterned silicon mold, a vertical TGV with smooth sidewall and fine pitch could be achieved. Bottom-up void-free filling of the TGV is successfully demonstrated through the seedless copper electroplating process. In addition, the proposed process allows wafer-level packaging with glass cap encapsulation using the anodic bonding process, since the reflowed glass interposer is only formed in the device area surrounded with silicon substrate. A simple coplanar waveguide (CPW) line was employed as the packaged device to evaluate the electrical characteristics and thermo-mechanical reliability of the proposed packaging structure. The fabricated packaging structure showed a low insertion loss of 0.116 dB and a high return loss of 35.537 dB at 20 GHz, which were measured through the whole electrical path, including the CPW line, TGVs and contact pads. An insertion loss lower than 0.1 dB and a return loss higher than 30 dB could be achieved at frequencies of up to 15 GHz, and the resistance of the single copper via was measured to be 36 mΩ. Furthermore, the thermo-mechanical reliability of the proposed packaging structure was also verified through thermal shock and pressure cooker test. (paper)

  12. Black Silicon Solar Cells with Black Ribbons

    DEFF Research Database (Denmark)

    Davidsen, Rasmus Schmidt; Tang, Peter Torben; Mizushima, Io

    2016-01-01

    We present the combination of mask-less reactive ion etch (RIE) texturing and blackened interconnecting ribbons as a method for obtaining all-black solar panels, while using conventional, front-contacted solar cells. Black silicon made by mask-less reactive ion etching has total, average...... reflectance below 0.5% across a 156x156 mm2 silicon (Si) wafer. Black interconnecting ribbons were realized by oxidizing copper resulting in reflectance below 3% in the visible wavelength range. Screen-printed Si solar cells were realized on 156x156 mm2 black Si substrates with resulting efficiencies...... in the range 15.7-16.3%. The KOH-textured reference cell had an efficiency of 17.9%. The combination of black Si and black interconnecting ribbons may result in aesthetic, all-black panels based on conventional, front-contacted silicon solar cells....

  13. Fabrication of silicon molds for polymer optics

    DEFF Research Database (Denmark)

    Nilsson, Daniel; Jensen, Søren; Menon, Aric Kumaran

    2003-01-01

    A silicon mold used for structuring polymer microcavities for optical applications is fabricated, using a combination of DRIE (deep reactive ion etching) and anisotropic chemical wet etching with KOH + IPA. For polymer optical microcavities, low surface roughness and vertical sidewalls are often...... needed. This is achieved by aligning the mold precisely to the [110] direction of a silicon (100) wafer and etching very close to the (110) surfaces using a DRIE Bosch process. The surface roughness of the sidewalls is then removed with a short etch in KOH + IPA. To achieve this, the parameters for DRIE...... and KOH + IPA etch have been optimized. To reduce stiction between the silicon mold and the polymers used for molding, the mold is coated with a teflon-like material using the DRIE system. Released polymer microstructures characterized with AFM and SEM are also presented....

  14. Black Silicon Solar Cells with Black Ribbons

    DEFF Research Database (Denmark)

    Davidsen, Rasmus Schmidt; Tang, Peter Torben; Mizushima, Io

    2016-01-01

    We present the combination of mask-less reactive ion etch (RIE) texturing and blackened interconnecting ribbons as a method for obtaining all-black solar panels, while using conventional, front-contacted solar cells. Black silicon made by mask-less reactive ion etching has total, average...... in the range 15.7-16.3%. The KOH-textured reference cell had an efficiency of 17.9%. The combination of black Si and black interconnecting ribbons may result in aesthetic, all-black panels based on conventional, front-contacted silicon solar cells....... reflectance below 0.5% across a 156x156 mm2 silicon (Si) wafer. Black interconnecting ribbons were realized by oxidizing copper resulting in reflectance below 3% in the visible wavelength range. Screen-printed Si solar cells were realized on 156x156 mm2 black Si substrates with resulting efficiencies...

  15. Silicon Micromachining for Terahertz Component Development

    Science.gov (United States)

    Chattopadhyay, Goutam; Reck, Theodore J.; Jung-Kubiak, Cecile; Siles, Jose V.; Lee, Choonsup; Lin, Robert; Mehdi, Imran

    2013-01-01

    Waveguide component technology at terahertz frequencies has come of age in recent years. Essential components such as ortho-mode transducers (OMT), quadrature hybrids, filters, and others for high performance system development were either impossible to build or too difficult to fabricate with traditional machining techniques. With micromachining of silicon wafers coated with sputtered gold it is now possible to fabricate and test these waveguide components. Using a highly optimized Deep Reactive Ion Etching (DRIE) process, we are now able to fabricate silicon micromachined waveguide structures working beyond 1 THz. In this paper, we describe in detail our approach of design, fabrication, and measurement of silicon micromachined waveguide components and report the results of a 1 THz canonical E-plane filter.

  16. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  17. Optical evaluation of ingot fixity in semiconductor wafer slicing

    Science.gov (United States)

    Ng, T. W.; Nallathamby, R.

    2004-11-01

    The fixity of an ingot may greatly affect the quality of wafers produced during a wire saw process and improved mechanical clamping is a means for improving ingot fixity. Here, an optical technique that is based on laser beam deflection is described. The technique was demonstrated on ingot assemblies subjected to impulse loads within a prescribed range using an original and improved clamping system. The technique revealed that the ingot assembly had lower degrees of mean displacement and standard displacement deviation under the improved clamping system. The data on warp obtained from the actual production of wafers corroborates this finding. The technique described is an effective method of quantitatively evaluating the fixity of ingots in a wafer wire saw process.

  18. Structured Antireflective Coating for Silicon at Submillimeter Frequencies

    Science.gov (United States)

    Padilla, Estefania

    2018-01-01

    Observations at millimeter and submillimeter wavelengths are useful for many astronomical studies, such as the polarization of the cosmic microwave background or the formation and evolution of galaxy clusters. In order to allow observations over a broad spectral bandwidth (approximatively from 70 to 420 GHz), innovative broadband anti-reflective (AR) optics must be utilized in submillimeter telescopes. Due to its low loss and high refractive index, silicon is a fine optical material at these frequencies, but an AR coating with multiple layers is required to maximize its transmission over a wide bandwidth. Structured multilayer AR coatings for silicon are currently being developed at Caltech and JPL. The development process includes the design of the structured layers with commercial electromagnetic simulation software, the fabrication by using deep reactive ion etching, and the test of the transmission and reflection of the patterned wafers. Geometrical 3D patterns have successfully been etched at the surface of the silicon wafers creating up to 2 layers with different effective refractive indices. The transmission and reflection of single AR layer wafers, measured between 75 and 330 GHz, are close to the simulation predictions. These results allow the development of new designs with 5 or 6 AR layers in order to improve the bandwidth and transmission of the silicon AR coatings.

  19. (Preoxidation cleaning optimization for crystalline silicon)

    Energy Technology Data Exchange (ETDEWEB)

    1991-01-01

    A series of controlled experiments has been performed in Sandia's Photovoltaic Device Fabrication Laboratory to evaluate the effect of various chemical surface treatments on the recombination lifetime of crystalline silicon wafers subjected to a high-temperature dry oxidation. From this series of experiments we have deduced a relatively simple yet effective cleaning sequence. We have also evaluated the effect of different chemical damage-removal etches for improving the recombination lifetime and surface smoothness of mechanically lapped wafers. This paper presents the methodology used, the experimental results obtained, and our experience with using this process on a continuing basis over a period of many months. 7 refs., 4 figs., 1 tab.

  20. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  1. New insight into the discharge mechanism of silicon-air batteries using electrochemical impedance spectroscopy.

    Science.gov (United States)

    Cohn, Gil; Eichel, Rüdiger A; Ein-Eli, Yair

    2013-03-07

    The mechanism of discharge termination in silicon-air batteries, employing a silicon wafer anode, a room-temperature fluorohydrogenate ionic liquid electrolyte and an air cathode membrane, is investigated using a wide range of tools. EIS studies indicate that the interfacial impedance between the electrolyte and the silicon wafer increases upon continuous discharge. In addition, it is shown that the impedance of the air cathode-electrolyte interface is several orders of magnitude lower than that of the anode. Equivalent circuit fitting parameters indicate the difference in the anode-electrolyte interface characteristics for different types of silicon wafers. Evolution of porous silicon surfaces at the anode and their properties, by means of estimated circuit parameters, is also presented. Moreover, it is found that the silicon anode potential has the highest negative impact on the battery discharge voltage, while the air cathode potential is actually stable and invariable along the whole discharge period. The discharge capacity of the battery can be increased significantly by mechanically replacing the silicon anode.

  2. In-line high-rate evaporation of aluminum for the metallization of silicon solar cells

    Energy Technology Data Exchange (ETDEWEB)

    Mader, Christoph Paul

    2012-07-11

    This work focuses on the in-line high-rate evaporation of aluminum for contacting rear sides of silicon solar cells. The substrate temperature during the deposition process, the wafer bow after deposition, and the electrical properties of evaporated contacts are investigated. Furthermore, this work demonstrates for the first time the formation of aluminum-doped silicon regions by the in-line high-rate evaporation of aluminum without any further temperature treatment. The temperature of silicon wafers during in-line high-rate evaporation of aluminum is investigated in this work. The temperatures are found to depend on the wafer thickness W, the aluminum layer thickness d, and on the wafer emissivity {epsilon}. Two-dimensional finite-element simulations reproduce the measured peak temperatures with an accuracy of 97%. This work also investigates the wafer bow after in-line high-rate evaporation and shows that the elastic theory overestimates the wafer bow of planar Si wafers. The lower bow is explained with plastic deformation in the Al layer. Due to the plastic deformation only the first 79 K in temperature decrease result in a bow formation. Furthermore the electrical properties of evaporated point contacts are examined in this work. Parameterizations for the measured saturation currents of contacted p-type Si wafers and of contacted boron-diffused p{sup +}-type layers are presented. The contact resistivity of the deposited Al layers to silicon for various deposition processes and silicon surface concentrations are presented and the activation energy of the contact formation is determined. The measured saturation current densities and contact resistivities of the evaporated contacts are used in one-dimensional numerical Simulations and the impact on energy conversion efficiency of replacing a screen-printed rear side by an evaporated rear side is presented. For the first time the formation of aluminum-doped p{sup +}-type (Al-p{sup +}) silicon regions by the in

  3. Crystalline Silicon Interconnected Strips (XIS). Introduction to a New, Integrated Device and Module Concept

    Energy Technology Data Exchange (ETDEWEB)

    Van Roosmalen, J.; Bronsveld, P.; Mewe, A.; Janssen, G.; Stodolny, M.; Cobussen-Pool, E.; Bennett, I.; Weeber, A.; Geerligs, B. [ECN Solar Energy, P.O. Box 1, NL-1755 ZG, Petten (Netherlands)

    2012-06-15

    A new device concept for high efficiency, low cost, wafer based silicon solar cells is introduced. To significantly lower the costs of Si photovoltaics, high efficiencies and large reductions of metals and silicon costs are required. To enable this, the device architecture was adapted into low current devices by applying thin silicon strips, to which a special high efficiency back-contact heterojunction cell design was applied. Standard industrial production processes can be used for our fully integrated cell and module design, with a cost reduction potential below 0.5 euro/Wp. First devices have been realized demonstrating the principle of a series connected back contact hybrid silicon heterojunction module concept.

  4. Flexible and semi-transparent thermoelectric energy harvesters from low cost bulk silicon (100)

    KAUST Repository

    Sevilla, Galo T.

    2013-07-09

    Flexible and semi-transparent high performance thermoelectric energy harvesters are fabricated on low cost bulk mono-crystalline silicon (100) wafers. The released silicon is only 3.6% as thick as bulk silicon reducing the thermal loss significantly and generating nearly 30% more output power than unpeeled harvesters. This generic batch processing is a pragmatic way of transforming traditional silicon circuitry for extremely deformable high-performance integrated electronics. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  5. MOS structures containing silicon nanoparticles for memory device applications

    Energy Technology Data Exchange (ETDEWEB)

    Nedev, N; Zlatev, R [Instituto de IngenierIa, Universidad Autonoma de Baja California, Benito Juarez Blvd., s/n, C.P. 21280, Mexicali, Baja California (Mexico); Nesheva, D; Manolov, E; Levi, Z [Georgi Nadjakov Institute of Solid State Physics, Bulgarian Academy of Sciences, 72 Tzarigradsko Chaussee, 1784 Sofia (Bulgaria); Brueggemann, R; Meier, S [Institute of Physics, Carl von Ossietzky University, Oldenburg, D-26111 Oldenburg (Germany)], E-mail: nicola@iing.mxl.uabc.mx

    2008-05-01

    Metal-oxide-silicon structures containing layers with amorphous or crystalline silicon nanoparticles in a silicon oxide matrix are fabricated by sequential physical vapour deposition of SiO{sub x} (x = 1.15) and RF sputtering of SiO{sub 2} on n-type crystalline silicon, followed by high temperature annealing in an inert gas ambient. Depending on the annealing temperature, 700 deg. C or 1000 deg. C, amorphous or crystalline silicon nanoparticles are formed in the silicon oxide matrix. The annealing process is used not only for growing nanoparticles but also to form a dielectric layer with tunnelling thickness at the silicon/insulator interface. High frequency C-V measurements demonstrate that both types of structures can be charged negatively or positively by applying a positive or negative voltage on the gate. The structures with amorphous silicon nanoparticles show several important advantages compared to the nanocrystal ones, such as lower defect density at the interface between the crystalline silicon wafer and the tunnel silicon oxide, better retention characteristics and better reliability.

  6. Lowell Observatory's 24-inch Clark Refractor: Its History and Renovation

    Science.gov (United States)

    Schindler, Kevin; Nye, Ralph; Rosenthal, Peter

    2016-01-01

    In 1895, Percival Lowell hired eminent telescope maker Alvan G. Clark to build a 24-inch refractor. Lowell intended the telescope intitally for observing Mars in support of his controversial theories about life on that planet. Clark finished the telescope within a year and at a cost of $20,000. Lowell and his staff of assistants and astronomers began observing through it on July 23, 1896, setting off a long and productive career for the telescope.While Lowell's Mars studies dominated early work with the Clark, V.M. Slipher by the 1910s was using it to observe planetary rotations and atmospheric compositions. He soon revolutionized spectroscopic studies, gathering excruciatingly long spectra - some in excess of 40 hours - of the so-called white nebula and determining startling radial velocities, evidence of an expanding universe. In the 1960s, scientists and artists teamed up on the Clark and created detailed lunar maps in support of the Apollo program.In recent decades, the Clark has played a central role in the education programs at Lowell, with general public audiences, students, and private groups all taking advantage of this unique resource.With this nearly 120 years of contant use, the Clark had been wearing down in recent years. The telescope was becoming more difficult to move, old electrical wiring in the dome was a fire hazard, and many of the telescope's parts needed to be repaired or replaced.In 2013, Lowell Observatory began a fundraising campaign, collecting $291,000 to cover the cost of dome and telescope renovation. Workers removed the entire telescope mount and tube assembly from the dome, examining every part from tube sections to individuals screws. They also stabilized the dome, adding a water vapor barrier and new outer wall while reinforcing the upper dome. The project lasted from January, 2014 through August, 2015. The facility reopened for daytime tours in September, 2015 and evening viewing the following month.

  7. 25-Gb/s Transmission Over 2.5-km SSMF by Silicon MRR Enhanced 1.55-mu m III-V/SOI DML

    DEFF Research Database (Denmark)

    Cristofori, Valentina; Da Ros, Francesco; Ozolins, Oskars

    2017-01-01

    -GHz 1.55-mu m directly modulated hybrid III-V/SOI DFB laser realized by bonding III-V materials (InGaAlAs) on a silicon-on-insulator (SOI) wafer and a silicon MRR also fabricated on SOI. Such a transmitter enables error-free transmission (BER

  8. Hybrid III-V/silicon lasers

    Science.gov (United States)

    Kaspar, P.; Jany, C.; Le Liepvre, A.; Accard, A.; Lamponi, M.; Make, D.; Levaufre, G.; Girard, N.; Lelarge, F.; Shen, A.; Charbonnier, P.; Mallecot, F.; Duan, G.-H.; Gentner, J.-.; Fedeli, J.-M.; Olivier, S.; Descos, A.; Ben Bakir, B.; Messaoudene, S.; Bordel, D.; Malhouitre, S.; Kopp, C.; Menezo, S.

    2014-05-01

    The lack of potent integrated light emitters is one of the bottlenecks that have so far hindered the silicon photonics platform from revolutionizing the communication market. Photonic circuits with integrated light sources have the potential to address a wide range of applications from short-distance data communication to long-haul optical transmission. Notably, the integration of lasers would allow saving large assembly costs and reduce the footprint of optoelectronic products by combining photonic and microelectronic functionalities on a single chip. Since silicon and germanium-based sources are still in their infancy, hybrid approaches using III-V semiconductor materials are currently pursued by several research laboratories in academia as well as in industry. In this paper we review recent developments of hybrid III-V/silicon lasers and discuss the advantages and drawbacks of several integration schemes. The integration approach followed in our laboratory makes use of wafer-bonded III-V material on structured silicon-on-insulator substrates and is based on adiabatic mode transfers between silicon and III-V waveguides. We will highlight some of the most interesting results from devices such as wavelength-tunable lasers and AWG lasers. The good performance demonstrates that an efficient mode transfer can be achieved between III-V and silicon waveguides and encourages further research efforts in this direction.

  9. Advanced process control and novel test methods for PVD silicon and elastomeric silicone coatings utilized on ion implant disks, heatsinks and selected platens

    Science.gov (United States)

    Springer, J.; Allen, B.; Wriggins, W.; Kuzbyt, R.; Sinclair, R.

    2012-11-01

    Coatings play multiple key roles in the proper functioning of mature and current ion implanters. Batch and serial implanters require strategic control of elemental and particulate contamination which often includes scrutiny of the silicon surface coatings encountering direct beam contact. Elastomeric Silicone Coatings must accommodate wafer loading and unloading as well as direct backside contact during implant plus must maintain rigid elemental and particulate specifications. The semiconductor industry has had a significant and continuous effort to obtain ultra-pure silicon coatings with sustained process performance and long life. Low particles and reduced elemental levels for silicon coatings are a major requirement for process engineers, OEM manufacturers, and second source suppliers. Relevant data will be presented. Some emphasis and detail will be placed on the structure and characteristics of a relatively new PVD Silicon Coating process that is very dense and homogeneous. Wear rate under typical ion beam test conditions will be discussed. The PVD Silicon Coating that will be presented here is used on disk shields, wafer handling fingers/fences, exclusion zones of heat sinks, beam dumps and other beamline components. Older, legacy implanters can now provide extended process capability using this new generation PVD silicon - even on implanter systems that were shipped long before the advent of silicon coating for contamination control. Low particles and reduced elemental levels are critical performance criteria for the silicone elastomers used on disk heatsinks and serial implanter platens. Novel evaluation techniques and custom engineered tools are used to investigate the surface interaction characteristics of multiple Elastomeric Silicone Coatings currently in use by the industry - specifically, friction and perpendicular stiction. These parameters are presented as methods to investigate the critical wafer load and unload function. Unique tools and test

  10. TEM investigation of aluminium containing precipitates in high aluminium doped silicon carbide

    International Nuclear Information System (INIS)

    Wong-Leung, J.; FitzGerald, J.D.

    2002-01-01

    Full text: Silicon carbide is a promising semiconductor material for applications in high temperature and high power devices. The successful growth of good quality epilayers in this material has enhanced its potential for device applications. As a novel semiconductor material, there is a need for studying its basic physical properties and the role of dopants in this material. In this study, silicon carbide epilayers were grown on 4H-SiC wafers of (0001) orientation with a miscut angle of 8 deg at a temperature of 1550 deg C. The epilayers contained regions of high aluminium doping well above the solubility of aluminium in silicon carbide. High temperature annealing of this material resulted in the precipitation of aluminium in the wafers. The samples were analysed by secondary ion mass spectrometry and transmission electron microscopy. Selected area diffraction studies show the presence of aluminium carbide and aluminium silicon carbide phases. Copyright (2002) Australian Society for Electron Microscopy Inc

  11. Improvement of silicon direct bonding using surfaces activated by hydrogen plasma treatment

    CERN Document Server

    Choi, W B; Lee Jae Sik; Sung, M Y

    2000-01-01

    The plasma surface treatment, using hydrogen gas, of silicon wafers was studied as a pretreatment for silicon direct bonding. Chemical reactions of the hydrogen plasma with the surfaces were used for both surface activation and removal of surface contaminants. Exposure of the silicon wafers to the plasma formed an active oxide layer on the surface. This layer was hydrophilic. The surface roughness and morphology were examined as functions of the plasma exposure time and power. The surface became smoother with shorter plasma exposure time and lower power. In addition, the plasma surface treatment was very efficient in removing the carbon contaminants on the silicon surface. The value of the initial surface energy, as estimated by using the crack propagation method, was 506 mJ/M sup 2 , which was up to about three times higher than the value for the conventional direct bonding method using wet chemical treatments.

  12. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  13. Influence of the wafer biasing frequency upon etching of polymide

    International Nuclear Information System (INIS)

    Sauve, G.; Arnal, Y.; Grenier, R.; Moisan, M.

    1989-01-01

    In the commonly used RF capacitive discharge, the biasing voltage appearing on the wafer results from the discharge operating conditions and cannot be set independently, for example, from the plasma density. In electrodeless high frequency (HF) produced plasmas, independent biasing of the wafer is possible. In particular, one can set the biasing voltage at a frequency different from that of the HF field sustaining the plasma. In that respect, it has been shown that biasing the wafer at 13.56 MHz in a 2.45 GHz microwave sustained plasma can lead to a substantial increase in the etch rate. The influence on etch rate when biasing the wafer at frequencies f that are below and above the ion plasma frequency p i . This experiment is performed in a reactor that was recently developed for the study of the influence of the plasma stimulating frequency (13.56-2450 MHz) upon the etching of polyimide. In such a device, the plasma is sustained by a surface wave. In the present work, the authors are concerned with the etch rate of Ciba-Geigy XU-287 polyimide in an O 2 -CF 4 discharge sustained at a fixed frequency of 200 MHz

  14. 3D Align overlay verification using glass wafers

    NARCIS (Netherlands)

    Smeets, E.M.J.; Bijnen, F.C.G.; Slabbekoorn, J.; Van Zeijl, H.W.

    2004-01-01

    In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other.

  15. Wafer scale coating of polymer cantilever fabricated by nanoimprint lithography

    DEFF Research Database (Denmark)

    Greve, Anders; Dohn, Søren; Keller, Stephan Urs

    2010-01-01

    Microcantilevers can be fabricated in TOPAS by nanoimprint lithography, with the dimensions of 500 ¿m length 4.5 ¿m thickness and 100 ¿m width. By using a plasma polymerization technique it is possible to selectively functionalize individually cantilevers with a polymer coating, on wafer scale...

  16. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  17. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  18. Method for reuse of wafers for growth of vertically-aligned wire arrays

    Science.gov (United States)

    Spurgeon, Joshua M; Plass, Katherine E; Lewis, Nathan S; Atwater, Harry A

    2013-06-04

    Reusing a Si wafer for the formation of wire arrays by transferring the wire arrays to a polymer matrix, reusing a patterned oxide for several array growths, and finally polishing and reoxidizing the wafer surface and reapplying the patterned oxide.

  19. 16 CFR 460.20 - R-value per inch claims.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 1 2010-01-01 2010-01-01 false R-value per inch claims. 460.20 Section 460.20 Commercial Practices FEDERAL TRADE COMMISSION TRADE REGULATION RULES LABELING AND ADVERTISING OF HOME INSULATION § 460.20 R-value per inch claims. In labels, fact sheets, ads, or other promotional...

  20. Orthopedic stretcher with average-sized person can pass through 18-inch opening

    Science.gov (United States)

    Lothschuetz, F. X.

    1966-01-01

    Modified Robinson stretcher for vertical lifting and carrying, will pass through an opening 18 inches in diameter, while containing a person of average height and weight. A subject 6 feet tall and weighing 200 pounds was lowered and raised out of an 18 inch diameter opening in a tank to test the stretcher.

  1. Torque expression of 0.018 and 0.022 inch conventional brackets

    NARCIS (Netherlands)

    Sifakakis, I.; Pandis, N.; Makou, M.; Eliades, T.; Katsaros, C.; Bourauel, C.

    2013-01-01

    The aim of this study was to assess the effect of the moments generated with low- and high-torque brackets. Four different bracket prescription-slot combinations of the same bracket type (Mini Diamond(R) Twin) were evaluated: high-torque 0.018 and 0.022 inch and low-torque 0.018 and 0.022 inch.

  2. Porous silicon technology for integrated microsystems

    Science.gov (United States)

    Wallner, Jin Zheng

    With the development of micro systems, there is an increasing demand for integrable porous materials. In addition to those conventional applications, such as filtration, wicking, and insulating, many new micro devices, including micro reactors, sensors, actuators, and optical components, can benefit from porous materials. Conventional porous materials, such as ceramics and polymers, however, cannot meet the challenges posed by micro systems, due to their incompatibility with standard micro-fabrication processes. In an effort to produce porous materials that can be used in micro systems, porous silicon (PS) generated by anodization of single crystalline silicon has been investigated. In this work, the PS formation process has been extensively studied and characterized as a function of substrate type, crystal orientation, doping concentration, current density and surfactant concentration and type. Anodization conditions have been optimized for producing very thick porous silicon layers with uniform pore size, and for obtaining ideal pore morphologies. Three different types of porous silicon materials: meso porous silicon, macro porous silicon with straight pores, and macro porous silicon with tortuous pores, have been successfully produced. Regular pore arrays with controllable pore size in the range of 2mum to 6mum have been demonstrated as well. Localized PS formation has been achieved by using oxide/nitride/polysilicon stack as masking materials, which can withstand anodization in hydrofluoric acid up to twenty hours. A special etching cell with electrolytic liquid backside contact along with two process flows has been developed to enable the fabrication of thick macro porous silicon membranes with though wafer pores. For device assembly, Si-Au and In-Au bonding technologies have been developed. Very low bonding temperature (˜200°C) and thick/soft bonding layers (˜6mum) have been achieved by In-Au bonding technology, which is able to compensate the potentially

  3. Design and Fabrication of Silicon-on-Silicon-Carbide Substrates and Power Devices for Space Applications

    Directory of Open Access Journals (Sweden)

    Gammon P.M.

    2017-01-01

    Full Text Available A new generation of power electronic semiconductor devices are being developed for the benefit of space and terrestrial harsh-environment applications. 200-600 V lateral transistors and diodes are being fabricated in a thin layer of silicon (Si wafer bonded to silicon carbide (SiC. This novel silicon-on-silicon-carbide (Si/SiC substrate solution promises to combine the benefits of silicon-on-insulator (SOI technology (i.e device confinement, radiation tolerance, high and low temperature performance with that of SiC (i.e. high thermal conductivity, radiation hardness, high temperature performance. Details of a process are given that produces thin films of silicon 1, 2 and 5 μm thick on semi-insulating 4H-SiC. Simulations of the hybrid Si/SiC substrate show that the high thermal conductivity of the SiC offers a junction-to-case temperature ca. 4× less that an equivalent SOI device; reducing the effects of self-heating, and allowing much greater power density. Extensive electrical simulations are used to optimise a 600 V laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOSFET implemented entirely within the silicon thin film, and highlight the differences between Si/SiC and SOI solutions.

  4. Electrochemical isotropic texturing of mc-Si wafers in KOH solution

    International Nuclear Information System (INIS)

    Abburi, M.; Boström, T.; Olefjord, I.

    2013-01-01

    Boron doped multicrystalline Si-wafers were anodically polarized in 2 M KOH and 4 M KOH at 40 °C and 50 °C. The applied potentials were 25 V, 30 V, 40 V and 50 V. The morphology of the textured surfaces, the surface products and the light reflectivity were analyzed by utilizing SEM, XPS and Lambda UV/Vis/NIR spectrophotometer, respectively. Isotropic texturing was obtained. The lowest average reflectivity, 17%, was achieved after pre-etching for 10 min and polarization at 40 V for 10 min in 4 M KOH at 50 °C. That reflection value is half of that measured on a chemical pre-etched surface, 34%. By increasing the voltage to 50 V the reflectivity rises to 28%. Polarizations to 25 V and 30 V at 50 °C in both solutions give local pores in the μm-range. The etch attack initiation is located at protrusions on the surface. At 40 V and 50 V in both solutions the pores are extended onto the entire surface. The width of the pores is about 10 μm. Inside the micro-pores, nm-pores are formed; their lateral size is in the range 100 nm–200 nm. A mechanism for the anodic dissolution reactions is discussed. - Highlights: ► A method to form isotropic textures on mc-Si wafers in KOH solution is presented. ► The method is based on anodic polarization of silicon in KOH at high potentials. ► Evolution of surface morphology is studied by varying the etch parameters. ► Isotropic textures with lowest average reflectivity are obtained at 40 V. ► A reaction model for texturing mechanism is discussed in the light of XPS data

  5. Nanoscale x-ray imaging of circuit features without wafer etching.

    Science.gov (United States)

    Deng, Junjing; Hong, Young Pyo; Chen, Si; Nashed, Youssef S G; Peterka, Tom; Levi, Anthony J F; Damoulakis, John; Saha, Sayan; Eiles, Travis; Jacobsen, Chris

    2017-03-01

    Modern integrated circuits (ICs) employ a myriad of materials organized at nanoscale dimensions, and certain critical tolerances must be met for them to function. To understand departures from intended functionality, it is essential to examine ICs as manufactured so as to adjust design rules, ideally in a non-destructive way so that imaged structures can be correlated with electrical performance. Electron microscopes can do this on thin regions, or on exposed surfaces, but the required processing alters or even destroys functionality. Microscopy with multi-keV x-rays provides an alternative approach with greater penetration, but the spatial resolution of x-ray imaging lenses has not allowed one to see the required detail in the latest generation of ICs. X-ray ptychography provides a way to obtain images of ICs without lens-imposed resolution limits, with past work delivering 20-40 nm resolution on thinned ICs. We describe a simple model for estimating the required exposure, and use it to estimate the future potential for this technique. Here we show for the first time that this approach can be used to image circuit detail through an unprocessed 300 μ m thick silicon wafer, with sub-20 nm detail clearly resolved after mechanical polishing to 240 μ m thickness was used to eliminate image contrast caused by Si wafer surface scratches. By using continuous x-ray scanning, massively parallel computation, and a new generation of synchrotron light sources, this should enable entire non-etched ICs to be imaged to 10 nm resolution or better while maintaining their ability to function in electrical tests.

  6. Test procedure for the Master-Lee and the modified Champion four inch hydraulic cutters

    International Nuclear Information System (INIS)

    Crystal, J.B.

    1995-01-01

    The Master-Lee and the modified Champion 4 Inch hydraulic cutters are being retested to gather and document information related to the following: determine if the Master-Lee cutters will cut the trunnions of an Aluminum fuel canister and a Stainless Steel fuel canister; determine if the Master-Lee cutters will cut 1 1/2 inch diameter fire hose; determine if the modified Champion 4 inch blade will cut sections of piping; and determine the effectiveness of the centering device for the Champion 4 Inch cutters. Determining the limitations of the hydraulic cutter will aid in the process of debris removal in the K-Basin. Based on a previous test, the cutters were returned to the manufacturer for modifications. The modifications to the Champion 4 Inch Cutter and further testing of the Master-Lee Cutter are the subjects of these feature tests

  7. Wafer based mask characterization for double patterning lithography

    Science.gov (United States)

    de Kruif, Robert; Bubke, Karsten; Janssen, Gert-Jan; van der Heijden, Eddy; Fochler, Jörg; Dusa, Mircea; Peters, Jan Hendrik; de Haas, Paul; Connolly, Brid

    2008-04-01

    Double Patterning Technology (DPT) is considered the most acceptable solution for 32nm node lithography. Apart from the obvious drawbacks of additional exposure and processing steps and therefore reduced throughput, DPT possesses a number of additional technical challenges. This relates to exposure tool capability, the actual applied process in the wafer fab but also to mask performance. This paper will focus on the latter. We will report on the performance of a two-reticle set based on a design developed to study the impact of mask global and local placement errors on a DPT dual line process. For 32 nm node lithography using DPT a reticle to reticle overlay contribution target of data resulting from the earlier mentioned reticle set. The reticles contain a 13x19 array of modules comprising various standard overlay features such as ASML overlay gratings and bar-in-bar overlay targets. Furthermore the modules contain split 40nm half pitch DPT features. The reticles have been exposed on an ASML XT:1700i on several wafers in multiple fields. Reticle to reticle overlay contribution has been studied in resist (double exposure) and using the IMEC dual line process (DPT). We will show that the reticle to reticle overlay contribution on the wafer is smaller than 1.5nm (1x). We will compare the wafer data with the reticle data, study the correlation and show that reticle to reticle overlay contribution based single mask registration measurements can be used to qualify the reticle to reticle overlay contribution on wafer.

  8. Formation of array microstructures on silicon by multibeam interfered femtosecond laser pulses

    International Nuclear Information System (INIS)

    Zhao Quanzhong; Qiu Jianrong; Zhao Chongjun; Jiang Xiongwei; Zhu Congshan

    2005-01-01

    We report on an optical interference method to fabricate array microstructures on the surface of silicon wafers by means of five-beam interference of femtosecond laser pulses. Optical microscope and scanning electron microscope observations revealed microstructures with micrometer-order were fabricated. The diffraction characteristics of the fabricated structures were evaluated. The present technique allows one-step realization of functional optoelectronic devices on silicon surface

  9. Scaling of black silicon processing time by high repetition rate femtosecond lasers

    Directory of Open Access Journals (Sweden)

    Nava Giorgio

    2013-11-01

    Full Text Available Surface texturing of silicon substrates is performed by femtosecond laser irradiation at high repetition rates. Various fabrication parameters are optimized in order to achieve very high absorptance in the visible region from the micro-structured silicon wafer as compared to the unstructured one. A 70-fold reduction of the processing time is demonstrated by increasing the laser repetition rate from 1 kHz to 200 kHz. Further scaling up to 1 MHz can be foreseen.

  10. Design of large sample silicon ingots irradiation facilities using MCNP

    International Nuclear Information System (INIS)

    Abd EL - Latif, S.S.M.

    2012-01-01

    When silicon is irradiated the objective is to produce number of phosphorus atoms in the target sample in order to obtain a given resistivity after the treatment. The resistivity of the sample is decreased by the transmutation of the silicon, by neutrons to phosphorus. Irradiation is carried out by thermal neutrons. The irradiation of silicon ingot large diameter has been carried out in heavy water research reactor since the thermal neutron flux to the fast neutron flux in order of 1000:1. The neutron spectrum is highly thermalized and some of these neutrons can reach the center of the silicon ingot and gives the radial resistivity gradient in accept range. Due to the disadvantages of heavy water research reactor such as tritium generation as a result of the neutron capture by deuterium. The tritium is radioactive emitting beta particles with a half life of 12.3 years so the heavy water research reactor is closed to avoid the intake of bete particles. The new trend in light water research reactor to design a neutron filter from heavy water or graphite to moderate the neutron to offer neutron spectrum like heavy water reactors, and keep the advantages of light water research reactors such as open pool. In this work we try to use graphite, heavy water and light water to design a neutron filter using the MCNP for different silicon ingot diameter.The light water research reactors can irradiate silicon ingot up to 10 inches diameter with accepted radial resistivity gradient (RRG). Graphite is the best filter in case of 10 inch with maximum radial variation (MRV) 7.564%; Light water is the best filter in case of 6 and 8 inch with MRV 2.197% and 4.85% respectively. In case of 6 and 10 inch Heavy water is the second choice.

  11. Method for rapid, controllable growth and thickness, of epitaxial silicon films

    Science.gov (United States)

    Wang, Qi [Littleton, CO; Stradins, Paul [Golden, CO; Teplin, Charles [Boulder, CO; Branz, Howard M [Boulder, CO

    2009-10-13

    A method of producing epitaxial silicon films on a c-Si wafer substrate using hot wire chemical vapor deposition by controlling the rate of silicon deposition in a temperature range that spans the transition from a monohydride to a hydrogen free silicon surface in a vacuum, to obtain phase-pure epitaxial silicon film of increased thickness is disclosed. The method includes placing a c-Si substrate in a HWCVD reactor chamber. The method also includes supplying a gas containing silicon at a sufficient rate into the reaction chamber to interact with the substrate to deposit a layer containing silicon thereon at a predefined growth rate to obtain phase-pure epitaxial silicon film of increased thickness.

  12. Method using laser irradiation for the production of atomically clean crystalline silicon and germanium surfaces

    Science.gov (United States)

    Ownby, Gary W.; White, Clark W.; Zehner, David M.

    1981-01-01

    This invention relates to a new method for removing surface impurities from crystalline silicon or germanium articles, such as off-the-shelf p- or n-type wafers to be doped for use as junction devices. The principal contaminants on such wafers are oxygen and carbon. The new method comprises laser-irradiating the contaminated surface in a non-reactive atmosphere, using one or more of Q-switched laser pulses whose parameters are selected to effect melting of the surface without substantial vaporization thereof. In a typical application, a plurality of pulses is used to convert a surface region of an off-the-shelf silicon wafer to an automatically clean region. This can be accomplished in a system at a pressure below 10.sup.-8 Torr, using Q-switched ruby-laser pulses having an energy density in the range of from about 60 to 190 MW/cm.sup.2.

  13. Deep level transient spectroscopy and minority carrier lifetime study on Ga-doped continuous Czochralski silicon

    Science.gov (United States)

    Yoon, Yohan; Yan, Yixin; Ostrom, Nels P.; Kim, Jinwoo; Rozgonyi, George

    2012-11-01

    Continuous-Czochralski (c-Cz) crystal growth has been suggested as a viable technique for the fabrication of photovoltaic Si wafers due to its low resistivity variation of any dopant, independent of segregation, compared to conventional Cz. In order to eliminate light induced degradation due to boron-oxygen traps in conventional p-type silicon wafers, gallium doped wafers have been grown by c-Cz method and investigated using four point probe, deep level transient spectroscopy (DLTS), and microwave-photoconductance decay. Iron-gallium related electrically active defects were identified using DLTS as the main lifetime killers responsible for reduced non-uniform lifetimes in radial and axial positions of the c-Cz silicon ingot. A direct correlation between minority carrier lifetime and the concentration of electrically active Fe-Ga pairs was established.

  14. Low-background instrumental neutron activation analysis of silicon semiconductor materials

    International Nuclear Information System (INIS)

    Smith, A.R.; McDonald, R.J.; Manini, H.; Hurley, D.L.; Norman, E.B.; Vella, M.C.; Odom, R.W.

    1996-01-01

    Samples of silicon wafers, some implanted with zinc, some with memory circuits fabricated on them, and some with oxide coatings were activated with neutrons and analyzed for trace element impurities with low-background germanium gamma-ray spectrometers. Results are presented for these samples as well as for a reference material. Because the silicon matrix activation is so small, reduced spectrometer system background permits the detection of significantly lower impurity concentrations than would otherwise be possible. For the highest efficiency and lowest background system, limits on the lowest levels of trace element concentrations have been measured for wafer sized (1 to 10 g) samples and inferred for bulk sized (365 g) samples. For wafer-sized samples, part-per-trillion detection capabilities are demonstrated for a variety of elemental contaminants important in semiconductor fabrication

  15. IR and UV laser-induced morphological changes in silicon surface under oxygen atmosphere

    Energy Technology Data Exchange (ETDEWEB)

    Jimenez-Jarquin, J.; Fernandez-Guasti, M.; Haro-Poniatowski, E.; Hernandez-Pozos, J.L. [Laboratorio de Optica Cuantica, Departamento de Fisica, Universidad Autonoma Metropolitana-Iztapalapa, Av. San Rafael Atlixco No. 186, Col. Vicentina, C.P. 09340, Mexico D.F. (Mexico)

    2005-08-01

    We irradiated silicon (100) wafers with IR (1064 nm) and UV (355 nm) nanosecond laser pulses with energy densities within the ablation regime and used scanning electron microscopy to analyze the morphological changes induced on the Si surface. The changes in the wafer morphology depend both on the incident radiation wavelength and the environmental atmosphere. We have patterned Si surfaces with a single focused laser spot and, in doing the experiments with IR or UV this reveals significant differences in the initial surface cracking and pattern formation, however if the experiment is carried out in O{sub 2} the final result is an array of microcones. We also employed a random scanning technique to irradiate the silicon wafer over large areas, in this case the microstructure patterns consist of a ''semi-ordered'' array of micron-sized cones. (copyright 2005 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  16. Silicon Nanowires for Solar Thermal Energy Harvesting: an Experimental Evaluation on the Trade-off Effects of the Spectral Optical Properties.

    Science.gov (United States)

    Sekone, Abdoul Karim; Chen, Yu-Bin; Lu, Ming-Chang; Chen, Wen-Kai; Liu, Chia-An; Lee, Ming-Tsang

    2016-12-01

    Silicon nanowire possesses great potential as the material for renewable energy harvesting and conversion. The significantly reduced spectral reflectivity of silicon nanowire to visible light makes it even more attractive in solar energy applications. However, the benefit of its use for solar thermal energy harvesting remains to be investigated and has so far not been clearly reported. The purpose of this study is to provide practical information and insight into the performance of silicon nanowires in solar thermal energy conversion systems. Spectral hemispherical reflectivity and transmissivity of the black silicon nanowire array on silicon wafer substrate were measured. It was observed that the reflectivity is lower in the visible range but higher in the infrared range compared to the plain silicon wafer. A drying experiment and a theoretical calculation were carried out to directly evaluate the effects of the trade-off between scattering properties at different wavelengths. It is clearly seen that silicon nanowires can improve the solar thermal energy harnessing. The results showed that a 17.8 % increase in the harvest and utilization of solar thermal energy could be achieved using a silicon nanowire array on silicon substrate as compared to that obtained with a plain silicon wafer.

  17. Procedure for the ion implantation of semiconductor wafers coated with insulating layers

    International Nuclear Information System (INIS)

    Baumann, K.; Tunnat, K.

    1987-01-01

    This invention is directed to the ion implantation of semiconductor wafers coated with insulating layers. The aim is to limit the spark puncturing by the ion beam due to electric charge and thus to protect the component structures. A conductive contact between semiconductor wafer and wafer carrier of the ion implantation facility is established by the partial removal of the insulating layer. 4 figs

  18. Doping optimization of solar grade (SOG silicon ingots for increasing ingot yield and cell efficiency

    Directory of Open Access Journals (Sweden)

    Azat A. Betekbaev

    2016-09-01

    Full Text Available In the near future, SoG will become the principal material for photovoltaic ingot production as it requires much less energy for purification compared to silicon grades using gas transformation and purification (usually Siemens process or equivalent also used for electronic-grade preparation. In this study, several kinds of silicon have been compared with different dopant contents (mainly boron and phosphorus. Ingot yield and cell efficiency have been optimized for each source of silicon at a commercial level (450 kg ingots using boron or gallium doping. Starting from the resistivity specification given by the cell process, the doping level has been adjusted in order to maximize the ingot silicon yield (weight of silicon bricks used for wafer cutting/weight of silicon ingot. After doping adjustment, ingot quality has been checked, i.e. brick resistivity and lifetime of minority carriers, and wafers have been processed to solar cells. Doping optimization has led to comparable ingot yields and cell efficiencies using SoG and silicon purified by Siemens process or equivalent. The study has been implemented at the Kazakhstan Solar Silicon Plant in Ust-Kamenogorsk using Kazakhstan SoG, SoG has been received from a European manufacturer and polycrystalline silicon has been purified using the Siemens process. Directional solidification furnaces have been manufactured by ECM Technologies, France.

  19. The structure of ferrofluids in the vicinity of an interface with silicon

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiev, A. [Max-Planck-Institut fuer Metallforschung, Heisenbergstr. 1, 70569 Stuttgart (Germany); Petersburg Nuclear Physics Institute, 188350 Gatchina, St. Petersburg (Russian Federation); Gordeev, G. [Petersburg Nuclear Physics Institute, 188350 Gatchina, St. Petersburg (Russian Federation); Major, J.; Dosch, H. [Max-Planck-Institut fuer Metallforschung, Heisenbergstr. 1, 70569 Stuttgart (Germany); Toperverg, B.P. [Petersburg Nuclear Physics Institute, 188350 Gatchina, St. Petersburg (Russian Federation); Forschungszentrum Juelich, IFF, 52425 Juelich (Germany)

    2002-07-01

    Neutron reflectometry and off-specular scattering is used for studying the ordering in colloidal solutions of ferromagnetic nanoparticles in the vicinity of a flat monocrystalline silicon wafer. The experiments reveal layering whose morphology and kinetics depend strongly on the colloidal parameters and the applied magnetic field. (orig.)

  20. Performance Study of Non-Irradiated Prototype Silicon Preshower Samplers for CMS

    CERN Document Server

    Bloch, Philippe; Chen, A E; Cheremouhine, A; Hou, Suen; Lin, Willis; Peisert, Anna; Zamiatin, Nikolai

    2000-01-01

    The performance of the prototype silicon preshower detectors for the CMS experiment has been studied at CERN-PS. The charge collection efficiency for different regions of the geometrical wafer layout is examined. The lateral shower profile and spatial resolution are investigated for electrons with energies between 1 and 12 GeV.

  1. MEMS silicon-based micro-evaporator with diamond-shaped fins

    NARCIS (Netherlands)

    Mihailovic, M.; Rops, C.; Creemer, J.F.; Sarro, P.M.

    2010-01-01

    A new design of micro-evaporators, with 45 channels (100 μm deep) and diamond-shaped fins (40μm wide, 160μm long, 20μm separation), is fabricated by anodic bonding of silicon and glass wafers, in a five masks process. This new design improves stability of the working conditions, and has a localized

  2. Development of Novel Front Contract Pastes for Crystalline Silicon Solar Cells

    Energy Technology Data Exchange (ETDEWEB)

    Duty, C.; Jellison, D. G.E. P.; Joshi, P.

    2012-04-05

    In order to improve the efficiencies of silicon solar cells, paste to silicon contact formation mechanisms must be more thoroughly understood as a function of paste chemistry, wafer properties and firing conditions. Ferro Corporation has been involved in paste development for over 30 years and has extensive expertise in glass and paste formulations. This project has focused on the characterization of the interface between the top contact material (silver paste) and the underlying silicon wafer. It is believed that the interface between the front contact silver and the silicon wafer plays a dominant role in the electrical performance of the solar cell. Development of an improved front contact microstructure depends on the paste chemistry, paste interaction with the SiNx, and silicon (“Si”) substrate, silicon sheet resistivity, and the firing profile. Typical front contact ink contains silver metal powders and flakes, glass powder and other inorganic additives suspended in an organic medium of resin and solvent. During fast firing cycles glass melts, wets, corrodes the SiNx layer, and then interacts with underlying Si. Glass chemistry is also a critical factor in the development of an optimum front contact microstructure. Over the course of this project, several fundamental characteristics of the Ag/Si interface were documented, including a higher-than-expected distribution of voids along the interface, which could significantly impact electrical conductivity. Several techniques were also investigated for the interfacial analysis, including STEM, EDS, FIB, EBSD, and ellipsometry.

  3. The determination of gold depth distribution in semiconductor silicon-potential interferences inherent in NAA by radiation damages

    International Nuclear Information System (INIS)

    Rudolph, P.; Lange, A.; Flachowsky, J.

    1986-01-01

    Gold is used quite extensively to control the charge storage time of high speed diodes and transistors. Therefore, the diffusion of gold into silicon wafers of finite thickness is important in the design and fabrication of these devices. Therefore it is necessary to estimate exactly concentration and depth distribution of gold formed by gold doping. Usually, gold content and depth distribution has been estimate by neutron activation analysis with step by step etching techniques. But during the irradiation in a nuclear fuel reactor the silicon wafers undergo minute or pronounced radiation damages which may affect the depth profiles of gold concentration. (author)

  4. Ultrahigh-speed hybrid laser for silicon photonic integrated chips

    DEFF Research Database (Denmark)

    Chung, Il-Sug; Park, Gyeong Cheol; Ran, Qijiang

    2013-01-01

    and light-emitting diode (LED) structures have been proposed so far. Our hybrid laser is one of these efforts [2]. The hybrid laser consists of a dielectric reflector, a III-V semiconductor active material, and a high-index-contrast grating (HCG) reflector formed in the silicon layer of a silicon......-oninsulator (SOI) wafer. ‘Hybrid’ indicates that a III-V active material is wafer-bonded to a silicon SOI wafer. In the hybrid laser, light is vertically amplified between the dielectric and the HCG reflectors, while the light output is laterally emitted to a normal Si ridge waveguide that is connected to the HCG...... reflector. The HCG works as a vertical mirror as well as a vertical-to-lateral coupler. Very small field penetration into the HCG allows for 3-4 times smaller modal volume than typical vertical-cavity surface-emitting lasers (VCSELs). This leads to high direct modulation speed. Details on device operating...

  5. Silicon pore optics for future x-ray telescopes

    DEFF Research Database (Denmark)

    Wille, Eric; Bavdaz, Marcos; Wallace, Kotska

    2017-01-01

    Lightweight X-ray Wolter optics with a high angular resolution will enable the next generation of X-ray telescopes in space. The candidate mission ATHENA (Advanced Telescope for High Energy Astrophysics) required a mirror assembly of 1 m2 effective area (at 1 keV) and an angular resolution of 10...... arcsec or better. These specifications can only be achieved with a novel technology like Silicon Pore Optics, which is being developed by ESA together with a consortium of European industry. Silicon Pore Optics are made of commercial Si wafers using process technology adapted from the semiconductor...

  6. Pixels detectors and silicon X-rays detectors

    OpenAIRE

    Delpierre, P.

    1994-01-01

    Silicon pixel detectors are beginning to be used in large particle physics experiments. The hybrid technique (detector and electronics on two separate wafers) allows large surfaces to be built. For ATLAS at LHC it is proposed to cover areas of more than 1 m2 with 5000 to 10000 pixels/cm2. Each pixel has a full electronic chain directly connected which means very low input capacitance and no integration of dark current. Furthermore, silicon strip detectors and CCD's have been successfully test...

  7. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  8. Microtextured Silicon Surfaces for Detectors, Sensors & Photovoltaics

    Energy Technology Data Exchange (ETDEWEB)

    Carey, JE; Mazur, E

    2005-05-19

    With support from this award we studied a novel silicon microtexturing process and its application in silicon-based infrared photodetectors. By irradiating the surface of a silicon wafer with intense femtosecond laser pulses in the presence of certain gases or liquids, the originally shiny, flat surface is transformed into a dark array of microstructures. The resulting microtextured surface has near-unity absorption from near-ultraviolet to infrared wavelengths well below the band gap. The high, broad absorption of microtextured silicon could enable the production of silicon-based photodiodes for use as inexpensive, room-temperature multi-spectral photodetectors. Such detectors would find use in numerous applications including environmental sensors, solar energy, and infrared imaging. The goals of this study were to learn about microtextured surfaces and then develop and test prototype silicon detectors for the visible and infrared. We were extremely successful in achieving our goals. During the first two years of this award, we learned a great deal about how microtextured surfaces form and what leads to their remarkable optical properties. We used this knowledge to build prototype detectors with high sensitivity in both the visible and in the near-infrared. We obtained room-temperature responsivities as high as 100 A/W at 1064 nm, two orders of magnitude higher than standard silicon photodiodes. For wavelengths below the band gap, we obtained responsivities as high as 50 mA/W at 1330 nm and 35 mA/W at 1550 nm, close to the responsivity of InGaAs photodiodes and five orders of magnitude higher than silicon devices in this wavelength region.

  9. Interdigitated design of a thermoelectric microgenerator based on silicon nanowire arrays

    Science.gov (United States)

    Donmez, I.; Salleras, M.; Calaza, C.; Santos, J. D.; Gadea, G.; Morata, A.; Dávila, D.; Tarancón, A.; Fonseca, L.

    2015-05-01

    Silicon nanowires thermoelectric properties are much better than those of silicon bulk. Taking advantage of silicon microfabrication techniques and compatibilizing the device fabrication with the CVD-VLS silicon nanowire growth, we present a thermoelectric microgenerator based on silicon nanowire arrays with interdigitated structures which enhance the power density compared to previous designs presented by the authors. The proposed design features a thermally isolated silicon platform on the silicon device layer of an SOI silicon wafer. This silicon platform has vertical walls exposing thermoelectric generator is unileg, which means that only one type of semiconductor is used, and the second connection is made through a metal. In addition, to improve the thermal isolation of the silicon platform, multiple trenches of silicon nanowire arrays are used, up to a maximum of nine. After packaging the device with nanowires, we are able to measure the Seebeck voltage and the power obtained with different operation modes: harvesting mode, where the bottom device is heated up, and the silicon platform is cooled down by natural or forced convection, and test mode, where a heater integrated on the silicon platform is used to produce a thermal gradient.

  10. Slim edges in double-sided silicon 3D detectors

    International Nuclear Information System (INIS)

    Povoli, M; Dalla Betta, G-F; Bagolini, A; Boscardin, M; Giacomini, G; Vianello, E; Zorzi, N

    2012-01-01

    Minimization of the insensitive edge area is one of the key requirements for silicon radiation detectors to be used in future silicon trackers. In 3D detectors this goal can be achieved with the active edge, at the expense of a high fabrication process complexity. In the framework of the ATLAS 3D sensor collaboration, we produced modified 3D silicon sensors with a double-sided technology. While this approach is not suitable to obtain active edges, because it does not use a support wafer, it allows for a new type of edge termination, the slim edge. In this paper we report on the development of the slim edge, from numerical simulations to design and testing, proving that it works effectively without increasing the fabrication complexity of silicon 3D detectors, and that it could be further optimized to reduce the insensitive edge region to less than 100 μm.

  11. Black silicon solar cells with black bus-bar strings

    DEFF Research Database (Denmark)

    Davidsen, Rasmus Schmidt; Tang, Peter Torben; Mizushima, Io

    2016-01-01

    We present the combination of black silicon texturing and blackened bus-bar strings as a potential method for obtaining all-black solar panels, while using conventional, front-contacted solar cells. Black silicon was realized by maskless reactive ion etching resulting in total, average reflectance...... below 0.5% across a 156x156 mm2 silicon wafer. Four different methods to obtain blackened bus-bar strings were compared with respect to reflectance, and two of these methods (i.e., oxidized copper and etched solder) were used to fabricate functional allblack solar 9-cell panels. The black bus-bars (e.......g., by oxidized copper) have a reflectance below 3% in the entire visible wavelength range. The combination of black silicon cells and blackened bus-bars results in aesthetic, all-black panels based on conventional, front-contacted solar cells without compromising efficiency....

  12. Silicon Solar Cell Process Development, Fabrication and Analysis, Phase 1

    Science.gov (United States)

    Yoo, H. I.; Iles, P. A.; Tanner, D. P.

    1979-01-01

    Solar cells from RTR ribbons, EFG (RF and RH) ribbons, dendritic webs, Silso wafers, cast silicon by HEM, silicon on ceramic, and continuous Czochralski ingots were fabricated using a standard process typical of those used currently in the silicon solar cell industry. Back surface field (BSF) processing and other process modifications were included to give preliminary indications of possible improved performance. The parameters measured included open circuit voltage, short circuit current, curve fill factor, and conversion efficiency (all taken under AM0 illumination). Also measured for typical cells were spectral response, dark I-V characteristics, minority carrier diffusion length, and photoresponse by fine light spot scanning. the results were compared to the properties of cells made from conventional single crystalline Czochralski silicon with an emphasis on statistical evaluation. Limited efforts were made to identify growth defects which will influence solar cell performance.

  13. Solar cell fabricated on welded thin flexible silicon

    Directory of Open Access Journals (Sweden)

    Hessmann Maik Thomas

    2015-01-01

    Full Text Available We present a thin-film crystalline silicon solar cell with an AM1.5 efficiency of 11.5% fabricated on welded 50 μm thin silicon foils. The aperture area of the cell is 1.00 cm2. The cell has an open-circuit voltage of 570 mV, a short-circuit current density of 29.9 mA cm-2 and a fill factor of 67.6%. These are the first results ever presented for solar cells on welded silicon foils. The foils were welded together in order to create the first thin flexible monocrystalline band substrate. A flexible band substrate offers the possibility to overcome the area restriction of ingot-based monocrystalline silicon wafers and the feasibility of a roll-to-roll manufacturing. In combination with an epitaxial and layer transfer process a decrease in production costs can be achieved.

  14. A solvent extraction approach to recover acetic acid from mixed waste acids produced during semiconductor wafer process.

    Science.gov (United States)

    Shin, Chang-Hoon; Kim, Ju-Yup; Kim, Jun-Young; Kim, Hyun-Sang; Lee, Hyang-Sook; Mohapatra, Debasish; Ahn, Jae-Woo; Ahn, Jong-Gwan; Bae, Wookeun

    2009-03-15

    Recovery of acetic acid (HAc) from the waste etching solution discharged from silicon wafer manufacturing process has been attempted by using solvent extraction process. For this purpose 2-ethylhexyl alcohol (EHA) was used as organic solvent. In the pre-treatment stage >99% silicon and hydrofluoric acid was removed from the solution by precipitation. The synthesized product, Na(2)SiF(6) having 98.2% purity was considered of commercial grade having good market value. The waste solution containing 279 g/L acetic acid, 513 g/L nitric acid, 0.9 g/L hydrofluoric acid and 0.030 g/L silicon was used for solvent extraction study. From the batch test results equilibrium conditions for HAc recovery were optimized and found to be 4 stages of extraction at an organic:aqueous (O:A) ratio of 3, 4 stages of scrubbing and 4 stages of stripping at an O:A ratio of 1. Deionized water (DW) was used as stripping agent to elute HAc from organic phase. In the whole batch process 96.3% acetic acid recovery was achieved. Continuous operations were successfully conducted for 100 h using a mixer-settler to examine the feasibility of the extraction system for its possible commercial application. Finally, a complete process flowsheet with material balance for the separation and recovery of HAc has been proposed.

  15. Optical coating uniformity of 200mm (8") diameter precut wafers

    Science.gov (United States)

    Burt, Travis C.; Fisher, Mark; Brown, Dean; Troiani, David

    2017-02-01

    Automated spectroscopic profiling (mapping) of a 200 mm diameter near infrared high reflector (centered at 1064 nm) are presented. Spatial resolution at 5 mm or less was achieved using a 5 mm × 1.5 mm monochromatic beam. Reflection changes of 1.0% across the wafer diameter were observed under s-polarized and p- polarized conditions. Redundancy was established for each chord by re-measuring the center of the wafer and reproducibility of approximately used to measure the reflectance and transmittance of a sample across a range of angles (θi) at near normal angles of incidence (AOI). A recent development by Agilent Technologies, the Cary 7000 Universal Measurement Spectrophotometer (UMS) combines both reflection and transmission measurements from the same patch of a sample's surface in a single automated platform for angles of incidence in the range 5°use of MPS on the Cary 7000 UMS with rotational (Φ) and vertical (z) sample positioning control. MPS(θi,Φ,z) provides for automated unattended multi-angle R/T analysis of at 200 mm diameter samples with the goal to provide better spectroscopic measurement feedback into large wafer manufacturing to ensure yields are maximized, product quality is better controlled and waste is reduced before further down-stream processing.

  16. Metal adsorbent for alkaline etching aqua solutions of Si wafer

    International Nuclear Information System (INIS)

    Tamada, Masao; Ueki, Yuji; Seko, Noriaki; Takeda, Toshihide; Kawano, Shin-ichi

    2012-01-01

    High performance adsorbent is expected to be synthesized for the removal of Ni and Cu ions from strong alkaline solution used in the surface etching process of Si wafer. Fibrous adsorbent was synthesized by radiation-induce emulsion graft polymerization onto polyethylene nonwoven fabric and subsequent amination. The reaction condition was optimized using 30 L reaction vessel and nonwoven fabric, 0.3 m width and 18 m long. The resulting fibrous adsorbent was evaluated by 48 wt% NaOH and KOH contaminated with Ni and Cu ions, respectively. The concentration levels of Ni and Cu ions was reduced to less than 1 μg/kg (ppb) at the flow rate of 10 h −1 in space velocity. The life of adsorbent was 30 times higher than that of the commercialized resin. This novel adsorbent was commercialized as METOLATE ® since the ability of adsorption is remarkably higher than that of commercial resin used practically in Si wafer processing. - Highlights: ► Adsorbent was synthesized by radiation-induced emulsion graft polymerization. ► Degree of grafting reached 120% at the pre-irradiation of 50 kGy. ► The resulting adsorbent removed Ni and Cu ion in strong alkaline solution. ► Adsorbent was commercialized for filter of Si wafer etchant.

  17. Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias

    International Nuclear Information System (INIS)

    Dixit, Pradeep; Vehmas, Tapani; Vähänen, Sami; Monnoyer, Philippe; Henttinen, Kimmo

    2012-01-01

    This paper presents the fabrication and the electrical characterization of poly-Si filled through-silicon vias, which were etched in a 180 µm thin silicon device wafer, bonded to a handle wafer by plasma activated oxide-to-silicon bonding. Heavily doped poly-Si was used as interconnection material, which was deposited by low-pressure chemical vapor deposition. Two different via geometries, i.e. stadium shaped, and circular shaped, were tried. Sputtered aluminum metallization layers as double-side redistribution lines and contact pads, were used. Both Kelvin structures and daisy chains were fabricated and their electrical resistances were measured. The electrical resistance of a single stadium-shaped via was measured to be about 24 Ω. The electrical resistance was varying from 60 Ω to 90 Ω for two-vias daisy chains. Measured results indicate that this via-first technology can be used for varying range of sensor applications like microphone, oscillator, resonator, etc where CMOS compatibility and high temperature processing are the prime requirements. (paper)

  18. A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

    Science.gov (United States)

    Tang, Jiajie; Sun, Xiaowei; Luo, Le

    2011-06-01

    A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz.

  19. A wafer-level multi-chip module process with thick photosensitive benzocyclobutene as the dielectric for microwave application

    International Nuclear Information System (INIS)

    Tang, Jiajie; Sun, Xiaowei; Luo, Le

    2011-01-01

    A wafer-level microwave multi-chip module (MMCM) packaging process is presented. Thick photosensitive-benzocyclobutene (photo-BCB) polymer (about 25 µm/layer) is used as the dielectric for its simplified process and the capability of obtaining desirable electrical, chemical and mechanical properties at high frequencies. The MMCM packaging structure contains a monolithic microwave integrated circuit (MMIC) chip embedded in a lossy-silicon wafer, a microwave band-pass filter (BPF) and two layers of BCB/Au interconnection. Key processes of fabrication are described in detail. The non-uniformity of BCB film and the sidewall angle of the via-holes for inter-layer connection are tested. Via-chains prepared by metal/BCB multilayer structures are tested through the Kelvin test structure to investigate the resistances of inter-layer connection. The average value is measured to be 73.5 mΩ. The electrical characteristic of this structure is obtained by a microwave transmission performance test from 15 to 30 GHz. The measurement results show good consistency between the bare MMIC die and the packaged die in the test frequency band. The gain of the MMIC chip after packaging is better than 18 dB within the designed operating frequency range (from 23 to 25 GHz). When the packaged MMIC chip is connected to a BPF, the maximum gain is still measured to reach 11.95 dB at 23.8 GHz

  20. MT. BIGELOW 61-INCH IMAGES OF 9P/TEMPEL 1

    Data.gov (United States)

    National Aeronautics and Space Administration — This data set contains 6 images of 9P/Tempel 1 obtained on five nights in 1994 using a visual CCD mounted on the 61-inch Kuiper telescope of the Mt. Bigelow...

  1. Project W320 52-inch diameter equipment container load test: Test report

    International Nuclear Information System (INIS)

    Bellomy, J.R.

    1995-01-01

    This test report summarizes testing activities and documents the results of the load tests performed on-site and off-site to structural qualify the 52-inch equipment containers designed and fabricated under Project W-320

  2. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    Science.gov (United States)

    Makihata, M.; Tanaka, S.; Muroyama, M.; Matsuzaki, S.; Yamada, H.; Nakayama, T.; Yamaguchi, U.; Mima, K.; Nonomura, Y.; Fujiyoshi, M.; Esashi, M.

    2011-08-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N2. After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits.

  3. Adhesive wafer bonding using a molded thick benzocyclobutene layer for wafer-level integration of MEMS and LSI

    International Nuclear Information System (INIS)

    Makihata, M; Tanaka, S; Muroyama, M; Matsuzaki, S; Esashi, M; Yamada, H; Nakayama, T; Yamaguchi, U; Mima, K; Nonomura, Y; Fujiyoshi, M

    2011-01-01

    This paper describes a wafer bonding process using a 50 µm thick benzocyclobutene (BCB) layer which has vias and metal electrodes. The vias were fabricated by molding BCB using a glass mold. During the molding, worm-like voids grew between BCB and the mold due to the shrinkage of polymerizing BCB. They were completely removed by subsequent reflowing in N 2 . After patterning Al on the reflowed BCB for the electrodes and via connections, bonding with a glass substrate was performed. Voidless bonding without damage in the vias and electrodes was achieved. Through the process, the control of the polymerization degree of BCB is important, and thus the polymerization degree was evaluated by Fourier transform infrared spectroscopy. The developed process is useful for the wafer-bonding-based integration of different devices, e.g. micro electro mechanical systems and large-scale integrated circuits

  4. Silicon Wafer Advanced Packaging (SWAP). Multichip Module (MCM) Foundry Study. Version 2

    Science.gov (United States)

    1991-04-08

    microelectronics AOQ - average outgoing quality ATE - automated test equipment ATPG - automatic test pattern generation BCB - benzocyclobutenes BILBO - Built-In...evaluation include benzocyclobutenes ( BCB ), polyquinolines and low stress polyimides and generally offer lower dielectric constants, 2.0 to 2.7, lower... polished stainless steel (EPSS) tubing. Copper is not used because over time the fluxes used and the tin-lead solder can leach out and produce damaging

  5. Reaction of isocyanate-functionalised silicon wafers with complex amino compounds

    Czech Academy of Sciences Publication Activity Database

    Perzyna, A.; Zotto, Ch. D.; Durand, J. O.; Granier, M.; Smietana, M.; Melnyk, O.; Stará, Irena G.; Starý, Ivo; Klepetářová, Blanka; Šaman, David

    -, č. 24 (2007), s. 4032-4037 ISSN 1434-193X R&D Projects: GA MŠk LC512 Grant - others:FMFA(FR) 2005-06-041-1 Institutional research plan: CEZ:AV0Z40550506 Keywords : surface chemistry * monolayers * peptides * DNA * helicene Subject RIV: CC - Organic Chemistry Impact factor: 2.914, year: 2007

  6. High-reflectivity high-contrast grating focusing reflector on silicon-on-insulator wafer

    International Nuclear Information System (INIS)

    Fang Wenjing; Huang Yongqing; Duan Xiaofeng; Liu Kai; Fei Jiarui; Ren Xiaomin

    2016-01-01

    A high-contrast grating (HCG) focusing reflector providing phase front control of reflected light and high reflectivity is proposed and fabricated. Basic design rules to engineer this category of structures are given in detail. A 1550 nm TM polarized incident light of 11.86 mm in focal length and 0.8320 in reflectivity is obtained in experiment. The wavelength dependence of the fabricated HCGs from 1530 nm to 1580 nm is also tested. The test results show that the focal length is in the range of 11.81–12 mm, which is close to the designed focal length of 15 mm. The reflectivity is almost above 0.56 within a bandwidth of 50 nm. At a distance of 11.86 mm, the light is focused to a round spot with the highest concentration, which is much smaller than the size of the incident beam. The FWHM of the reflected light beam decreases to 120 nm, and the intensity increases to 1.18. (paper)

  7. Secondary ion mass spectrometry characterization of indium-implanted silicon wafers

    Science.gov (United States)

    Blackmer-Krasinski, C.; Morinville, W. R.

    2004-06-01

    Indium is a key element in the formation of well, channel, and halo profiles in semiconductor fabrication. Indium has the advantage of being a large atom with a small projected range, creating a steeper implant profile than the boron implant used in the past [Proceedings of the 14th International Conference on Ion Implantation Technology, ITT, 2002]. Typically, secondary ion mass spectrometry (SIMS) is used to provide implant profiles; however, when a set of indium-implanted samples were analyzed on the Cameca IMS-6F, non-repeatability of the implant profile was observed in the samples that had not received an oxide spacer prior to implantation. This non-repeatability was not observed when the same samples were analyzed on the Perkin-Elmer 6300 quadrupole secondary ion mass spectrometer. Several reasons for this were hypothesized: (1) an amorphous layer was being created due to the large size of the indium atom; (2) increased damage and surface roughening occurred on the samples that did not receive an oxide layer prior to implantation; (3) Gibbsian segregation similar to that of Cu in SiO 2 was being observed [Secondary Ion Mass Spectrometry, Wiley, New York, 1989, p. 2.2-1]; and (4) sample heating was changing the thermodynamic properties of the samples. To explore these possibilities, two sets of indium-implanted samples—with and without spacer oxide—were analyzed with atomic force microscopy (AFM) for surface roughness and with transmission electron microscopy (TEM) for differences in amorphization. SIMS analysis was also conducted on both types of dynamic SIMS instruments to develop an analytical protocol for determining the indium implant profile. Repeatable results, consistent with analysis on the quadrupole SIMS, were obtained by utilizing the cold finger on the Cameca 6F.

  8. High-reflectivity high-contrast grating focusing reflector on silicon-on-insulator wafer

    Science.gov (United States)

    Fang, Wenjing; Huang, Yongqing; Duan, Xiaofeng; Liu, Kai; Fei, Jiarui; Ren, Xiaomin

    2016-11-01

    A high-contrast grating (HCG) focusing reflector providing phase front control of reflected light and high reflectivity is proposed and fabricated. Basic design rules to engineer this category of structures are given in detail. A 1550 nm TM polarized incident light of 11.86 mm in focal length and 0.8320 in reflectivity is obtained in experiment. The wavelength dependence of the fabricated HCGs from 1530 nm to 1580 nm is also tested. The test results show that the focal length is in the range of 11.81-12 mm, which is close to the designed focal length of 15 mm. The reflectivity is almost above 0.56 within a bandwidth of 50 nm. At a distance of 11.86 mm, the light is focused to a round spot with the highest concentration, which is much smaller than the size of the incident beam. The FWHM of the reflected light beam decreases to 120 nm, and the intensity increases to 1.18. Project supported by the National Natural Science Foundation of China (Grant Nos. 61274044, 61574019 and 61020106007), the National Basic Research Program of China (Grant No. 2010CB327600), the Specialized Research Fund for the Doctoral Program of Higher Education of China (Grant No. 20130005130001), the Natural Science Foundation of Beijing, China (Grant No. 4132069), the Key International Science and Technology Cooperation Project of China (Grant No. 2011RR000100), the 111 Project of China (Grant No. B07005), and the Program for Changjiang Scholars and Innovative Research Team in Universities of China (Grant No. IRT0609).

  9. Attachment of trianglamines to silicon wafers, chiral recognition by chemical force microscopy

    Czech Academy of Sciences Publication Activity Database

    Hlinka, J.; Hodačová, Jana; Raehm, L.; Granier, M.; Ramonda, M.; Durand, J. O.

    2010-01-01

    Roč. 13, č. 4 (2010), s. 481-485 ISSN 1631-0748 R&D Projects: GA MŠk MEB020748 Institutional research plan: CEZ:AV0Z40550506 Keywords : trianglamines * chemical force microscopy * chiral recognition Subject RIV: CC - Organic Chemistry Impact factor: 1.600, year: 2010

  10. Metallization of large silicon wafers. Quarterly technical report No. 3, April 1--June 30, 1978

    Energy Technology Data Exchange (ETDEWEB)

    Pryor, R.A.; Sparks, T.G.

    1978-01-01

    Tests of numerous cleaning processes have been performed and evaluated for enhancement of the nickel--palladium metallization system (NPMS). An improved formulation for the NPMS immersion palladium bath has been developed and is discussed. NPMS heat treatment cycles have been refined and re-defined. Updated IPEG price analysis figures are presented.

  11. Effect of silicon nitride layers on the minority carrier diffusion length in c-Si wafers

    Czech Academy of Sciences Publication Activity Database

    Toušek, J.; Toušková, J.; Poruba, A.; Hlídek, P.; Lorinčík, Jan

    2006-01-01

    Roč. 100, č. 11 (2006), s. 113716.1-113716.6 ISSN 0021-8979 Institutional research plan: CEZ:AV0Z20670512 Keywords : solar cells * hydrogen * plasma Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 2.316, year: 2006

  12. Laser process for extended silicon thin film solar cells

    International Nuclear Information System (INIS)

    Hessmann, M.T.; Kunz, T.; Burkert, I.; Gawehns, N.; Schaefer, L.; Frick, T.; Schmidt, M.; Meidel, B.; Auer, R.; Brabec, C.J.

    2011-01-01

    We present a large area thin film base substrate for the epitaxy of crystalline silicon. The concept of epitaxial growth of silicon on large area thin film substrates overcomes the area restrictions of an ingot based monocrystalline silicon process. Further it opens the possibility for a roll to roll process for crystalline silicon production. This concept suggests a technical pathway to overcome the limitations of silicon ingot production in terms of costs, throughput and completely prevents any sawing losses. The core idea behind these thin film substrates is a laser welding process of individual, thin silicon wafers. In this manuscript we investigate the properties of laser welded monocrystalline silicon foils (100) by micro-Raman mapping and spectroscopy. It is shown that the laser beam changes the crystalline structure of float zone grown silicon along the welding seam. This is illustrated by Raman mapping which visualizes compressive stress as well as tensile stress in a range of - 147.5 to 32.5 MPa along the welding area.

  13. High aspect ratio nano-fabrication of photonic crystal structures on glass wafers using chrome as hard mask.

    Science.gov (United States)

    Hossain, Md Nazmul; Justice, John; Lovera, Pierre; McCarthy, Brendan; O'Riordan, Alan; Corbett, Brian

    2014-09-05

    Wafer-scale nano-fabrication of silicon nitride (Si x N y ) photonic crystal (PhC) structures on glass (quartz) substrates is demonstrated using a thin (30 nm) chromium (Cr) layer as the hard mask for transferring the electron beam lithography (EBL) defined resist patterns. The use of the thin Cr layer not only solves the charging effect during the EBL on the insulating substrate, but also facilitates high aspect ratio PhCs by acting as a hard mask while deep etching into the Si x N y . A very high aspect ratio of 10:1 on a 60 nm wide grating structure has been achieved while preserving the quality of the flat top of the narrow lines. The presented nano-fabrication method provides PhC structures necessary for a high quality optical response. Finally, we fabricated a refractive index based PhC sensor which shows a sensitivity of 185 nm per RIU.

  14. Stabilisation of a thin crystalline Si wafer solar cell using glass substrate; Duenne kristalline Silizium Wafer-Solarzelle mit Glastraeger stabilisiert

    Energy Technology Data Exchange (ETDEWEB)

    Muehlbauer, Maria

    2009-07-01

    An attempt was made to stabilise ultrathin crystalline silicon wafers (< 100 {mu}m) by a support material (BOROFLOAT33 by Schott Glas). It was found that the total serial resistance results mainly from the specific resistance of the back contact, and that especially the ultrathin solar cells have high recombination in the back. The ultrathin Si wafers also are slightly corrugated, which results in uneven joining of the Si wafer with the glass support. For optimisation, the solar cells of this specific types, with different thicknesses, were modelled in the one-dimensional simulation code PC1D, including all material-specific and electric properties. It was found that a slight reduction of the serial resistance will be enough for a significant improvement of the efficiency of the stabilized solar cell. With this knowledge, selective optimisation of the stabilised solar cells was possible, with the following results: 1. The improved temperature-time profile of the RTP step will improve the solar cell parameters for all Si thicknesses, which is assumed to be the result of better quality of the Al/Si back contact. 2. Thicker aluminium layers improved passivation on the back of solar cells with a thickness of 300 {mu}m and 120 {mu}m. In thinner stabilised solar cells, this measure resulted in enhanced formation of shunts and did not reduce the recombination rate on the back of the solar cell. 3. An additional optimisation step was the introduction of the so-called 'combined method' in which part of the aluminium layer is replaced by silkscreen paste. This combination, with adequate preparation, ensures uniform joining of the ultrathin silicon to the glass carrier. The resulting intermediate layers are highly homogeneous and have good fill factors and current densities for thin solar cells with a si thickness of 60 {mu}m. A decisive argument for the combined method is its near-100% reproducibility. [German] Ziel dieser Arbeit ist es sehr duenne kristalline

  15. Compositional analysis of silicon oxide/silicon nitride thin films

    Directory of Open Access Journals (Sweden)

    Meziani Samir

    2016-06-01

    Full Text Available Hydrogen, amorphous silicon nitride (SiNx:H abbreviated SiNx films were grown on multicrystalline silicon (mc-Si substrate by plasma enhanced chemical vapour deposition (PECVD in parallel configuration using NH3/SiH4 gas mixtures. The mc-Si wafers were taken from the same column of Si cast ingot. After the deposition process, the layers were oxidized (thermal oxidation in dry oxygen ambient environment at 950 °C to get oxide/nitride (ON structure. Secondary ion mass spectroscopy (SIMS, Rutherford backscattering spectroscopy (RBS, Auger electron spectroscopy (AES and energy dispersive X-ray analysis (EDX were employed for analyzing quantitatively the chemical composition and stoichiometry in the oxide-nitride stacked films. The effect of annealing temperature on the chemical composition of ON structure has been investigated. Some species, O, N, Si were redistributed in this structure during the thermal oxidation of SiNx. Indeed, oxygen diffused to the nitride layer into Si2O2N during dry oxidation.

  16. Effects of laser fluence on silicon modification by four-beam laser interference

    International Nuclear Information System (INIS)

    Zhao, Le; Li, Dayou; Wang, Zuobin; Yue, Yong; Zhang, Jinjin; Yu, Miao; Li, Siwei

    2015-01-01

    This paper discusses the effects of laser fluence on silicon modification by four-beam laser interference. In this work, four-beam laser interference was used to pattern single crystal silicon wafers for the fabrication of surface structures, and the number of laser pulses was applied to the process in air. By controlling the parameters of laser irradiation, different shapes of silicon structures were fabricated. The results were obtained with the single laser fluence of 354 mJ/cm 2 , 495 mJ/cm 2 , and 637 mJ/cm 2 , the pulse repetition rate of 10 Hz, the laser exposure pulses of 30, 100, and 300, the laser wavelength of 1064 nm, and the pulse duration of 7–9 ns. The effects of the heat transfer and the radiation of laser interference plasma on silicon wafer surfaces were investigated. The equations of heat flow and radiation effects of laser plasma of interfering patterns in a four-beam laser interference distribution were proposed to describe their impacts on silicon wafer surfaces. The experimental results have shown that the laser fluence has to be properly selected for the fabrication of well-defined surface structures in a four-beam laser interference process. Laser interference patterns can directly fabricate different shape structures for their corresponding applications

  17. Low surface damage dry etched black silicon

    Science.gov (United States)

    Plakhotnyuk, Maksym M.; Gaudig, Maria; Davidsen, Rasmus Schmidt; Lindhard, Jonas Michael; Hirsch, Jens; Lausch, Dominik; Schmidt, Michael Stenbæk; Stamate, Eugen; Hansen, Ole

    2017-10-01

    Black silicon (bSi) is promising for integration into silicon solar cell fabrication flow due to its excellent light trapping and low reflectance, and a continuously improving passivation. However, intensive ion bombardment during the reactive ion etching used to fabricate bSi induces surface damage that causes significant recombination. Here, we present a process optimization strategy for bSi, where surface damage is reduced and surface passivation is improved while excellent light trapping and low reflectance are maintained. We demonstrate that reduction of the capacitively coupled plasma power, during reactive ion etching at non-cryogenic temperature (-20 °C), preserves the reflectivity below 1% and improves the effective minority carrier lifetime due to reduced ion energy. We investigate the effect of the etching process on the surface morphology, light trapping, reflectance, transmittance, and effective lifetime of bSi. Additional surface passivation using atomic layer deposition of Al2O3 significantly improves the effective lifetime. For n-type wafers, the lifetime reaches 12 ms for polished and 7.5 ms for bSi surfaces. For p-type wafers, the lifetime reaches 800 μs for both polished and bSi surfaces.

  18. Wafer-level fabrication of GaN-based vertical light-emitting diodes using a multi-functional bonding material system

    International Nuclear Information System (INIS)

    Lee, Sang Youl; Choi, Kwang Ki; Jeong, Hwan-Hee; Choi, Hee Seok; Oh, Tchang-Hun; Song, June O; Seong, Tae-Yeon

    2009-01-01

    We first report on the fabrication of 2 inch wafer-level GaN-based vertical light-emitting diodes (LEDs) by using a multi-functional bonding material system, which is composed of a thick Cu diffusion barrier and a bonding layer. The bonding material system superbly absorbs laser-induced stress and also effectively serves as a barrier to the indiffusion of Sn to the active region. Fully packaged vertical LEDs fabricated with indium tin oxide (ITO)/AgCu contact and the bonding material system give an operating voltage of 3.35 V at 350 mA. After over 1800 h, the operating voltages remain stable, and the reverse currents are in the range 3–8 × 10 −7 A at −5 V. (rapid communication)

  19. Silicon Qubits

    Energy Technology Data Exchange (ETDEWEB)

    Ladd, Thaddeus D. [HRL Laboratories, LLC, Malibu, CA (United States); Carroll, Malcolm S. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2018-02-28

    Silicon is a promising material candidate for qubits due to the combination of worldwide infrastructure in silicon microelectronics fabrication and the capability to drastically reduce decohering noise channels via chemical purification and isotopic enhancement. However, a variety of challenges in fabrication, control, and measurement leaves unclear the best strategy for fully realizing this material’s future potential. In this article, we survey three basic qubit types: those based on substitutional donors, on metal-oxide-semiconductor (MOS) structures, and on Si/SiGe heterostructures. We also discuss the multiple schema used to define and control Si qubits, which may exploit the manipulation and detection of a single electron charge, the state of a single electron spin, or the collective states of multiple spins. Far from being comprehensive, this article provides a brief orientation to the rapidly evolving field of silicon qubit technology and is intended as an approachable entry point for a researcher new to this field.

  20. Identification and long term stability of DNA captured on a dental impression wafer.

    Science.gov (United States)

    Kim, Maile; Siegler, Kate; Tamariz, Jeannie; Caragine, Theresa; Fernandez, Jill; Daronch, Marcia; Moursi, Amr

    2012-01-01

    The purpose of this study was to determine the quantity and quality of DNA extracted from a dental bite impression wafer immediately after impression and after 12 months of home storage. The authors' hypothesis was that the wafer would retain sufficient DNA with appropriate genetic markers to make an identification match. Two impression wafers (Toothprints(®) brand) were administered to 100 3- to 26-year-olds. A cotton swab was used as a control. DNA from wafers stored for 12 months at home were compared to DNA collected at time 0 and compared to swabs at specific sites to determine quality and accuracy. The amount of DNA captured and recovered was analyzed using MagAttract technology and a quantitative real-time polymerase chain reaction. Capillary gel electrophoresis was performed to determine the quality of the DNA profiles obtained from the wafers vs those generated from the swabs of each subject. Average DNA concentration was: 480 pg/μL (wafer at time 0); 392 pg/μL (wafer after 12 months kept by subjects); and 1,041 pg/μL (buccal swab). Sufficient DNA for human identification was recovered from all sets of wafers, producing clear DNA profiles and accurate matches to buccal swabs. No inhibitors were found that could interfere with DNA profiling. Toothprints® impression wafers can be useful for DNA collection and child identification. After 12 months, the wafer was still usable for DNA capture and identification match.

  1. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  2. Trace detection of herbicides by SERS technique, using SERS-active substrates fabricated from different silver nanostructures deposited on silicon

    International Nuclear Information System (INIS)

    Dao, Tran Cao; Luong, Truc Quynh Ngan; Nguyen, Ngoc Hai; Kieu, Ngoc Minh; Luong, Thi Thuy; Cao, Tuan Anh; Le, Van Vu

    2015-01-01

    In this report we present the initial results of the use of different silver nanostructures deposited on silicon for trace detection of paraquat (a commonly used herbicide) using the surface-enhanced Raman scattering (SERS) effect. More specifically, the SERS-active substrates were fabricated from silver nanoparticles (AgNPs) deposited onto the flat surface of a silicon wafer (AgNPs@Si substrate), as well as on the surface of an obliquely aligned silicon nanowire (SiNW) array (AgNPs@SiNWs substrate), and from silver nanodendrites (AgNDs) deposited onto the flat surface of a silicon wafer (AgNDs@Si substrate). Results showed that with the change of the structure of the SERS-active substrate, higher levels of SERS enhancement have been achieved. Specifically, with the fabricated AgNDs@Si substrate, paraquat concentration as low as 1 ppm can be detected. (paper)

  3. Stationary Optical Concentrator Designs and Wafer Scale Monolithic Integration of Semiconductor Devices for Next Generation Photovoltaic Panels

    Science.gov (United States)

    Kim, Jung Min

    A major barrier in utilizing solar energy for large scale deployment is the cost of the photovoltaic (PV) systems. Several approaches have been used for the cost reduction such as by modifying PV system designs in addition to enhancing the efficiency of solar cells. Due to the high cost of materials, minimizing the use of solar cells such as in concentrator type systems is highly attractive for reducing the cost of the PV modules by focusing the incident light onto the PV cell. However concentrator PV systems (CPV) require constant tracking of the sun and hence are complex in design and expensive to operate, except in limited situations such as large scale PV power plants. It is desirable to design new concentrator type systems that do not require continuous tracking of the sun. These systems could ultimately reduce the PV system cost to a minimum while maximizing the power conversion efficiency. In this thesis we propose a simple design for a stationary concentrator photovoltaic (SCPV) system that could significantly reduce the cost of generating electricity using PV devices. Using optical ray tracing simulations, we have been able to design SCPV systems that could reduce the PV module cost by 2--10 times without compromising on the power conversion efficiency of the system. Another alternative approach for sustainable high efficiency PV system design is to develop low cost PV cells for terrestrial applications. To meet the demands of low cost and large scale production, larger and thinner (or flexible) substrates are required. We demonstrated the feasibility of fabricating monolithic interconnected PV devices at the wafer scale (2 inch wafers). In this study, GaSb PV cells grown on semi-insulating GaAs were used as the model material. Crucial device fabrication steps such as a selective etching process have been developed that is necessary for isolating individual devices on the wafer and interconnecting them with sub-micron scale accuracy. Selective etching of

  4. Fabrication of silicon micro heat pipes for cooling electronics; Realisation de microcaloducs en silicium pour le refroidissement de l'electronique

    Energy Technology Data Exchange (ETDEWEB)

    Launay, St.; Sartre, V.; Lallemand, M. [Institut National des Sciences Appliquees (INSA), Centre Thermique de Lyon (UMR CNRS 5008), 69 - Lyon (France); Le Berre, M.; Barbier, D. [Institut National des Sciences Appliquees (INSA), Lab. de Physique de la Matiere, 69 - Villeurbanne (France); Morfouli, P.; Boussey, J. [Institut National Polytechnique, Lab. de Microelectronique, Electromagnetisme et Photonique (UMR 5130) 38 - Grenoble (France)

    2003-07-01

    In this study, micro heat pipe arrays etched into silicon wafers were investigated, for electronic cooling purposes. Micro heat pipes of triangular cross-section (230 {mu}m width) and with liquid arteries were fabricated by wet anisotropic etching in a KOH solution. The microchannels were closed by molecular bonding of a plain wafer with the grooved one. Two test benches were developed for the micro heat pipe filling and thermal characterisation. The temperature profile at the silicon surface was deduced from experimental measurements and a 3D numerical simulation. The results have shown that with the artery micro heat pipe array, the effective thermal conductivity of the silicon wafer was improved by 330 %. (authors)

  5. Fully-depleted, back-illuminated charge-coupled devices fabricated on high-resistivity silicon

    Energy Technology Data Exchange (ETDEWEB)

    Holland, Stephen E.; Groom, Donald E.; Palaio, Nick P.; Stover, Richard J.; Wei, Mingzhi

    2002-03-28

    Charge-coupled devices (CCD's) have been fabricated on high-resistivity silicon. The resistivity, on the order of 10,000 {Omega}-cm, allows for depletion depths of several hundred microns. Fully-depleted, back-illuminated operation is achieved by the application of a bias voltage to a ohmic contact on the wafer back side consisting of a thin in-situ doped polycrystalline silicon layer capped by indium tin oxide and silicon dioxide. This thin contact allows for good short wavelength response, while the relatively large depleted thickness results in good near-infrared response.

  6. Laser desorption ionization and peptide sequencing on laser induced silicon microcolumn arrays

    Science.gov (United States)

    Vertes, Akos [Reston, VA; Chen, Yong [San Diego, CA

    2011-12-27

    The present invention provides a method of producing a laser-patterned silicon surface, especially silicon wafers for use in laser desorption ionization (LDI-MS) (including MALDI-MS and SELDI-MS), devices containing the same, and methods of testing samples employing the same. The surface is prepared by subjecting a silicon substrate to multiple laser shots from a high-power picosecond or femtosecond laser while in a processing environment, e.g., underwater, and generates a remarkable homogenous microcolumn array capable of providing an improved substrate for LDI-MS.

  7. Flat-plate solar array project. Task 1: Silicon material: Investigation of the hydrochlorination of SiC1sub4

    Science.gov (United States)

    Mui, J. Y. P.

    1981-01-01

    A two inch-diameter stainless steel reactor was designed to operate at pressure up to 500 psig and at temperature up to 600 C in order to study the hydrochlorination of silicon tetrachloride and metallurgical grade (m.g.) silicon metal to trichlorosilane. The hydrochlorination apparatus is described and operation safety and pollution control are discussed.

  8. The doping concentration and physical properties measurement of silicon water using tera hertz wave

    Energy Technology Data Exchange (ETDEWEB)

    Park, Sung Hyeon; Oh, Gyung Hwan; Kim, Hak Sung [Dept. of Mechanical Convergence Engineering, Hanyang University, Seoul(Korea, Republic of)

    2017-02-15

    In this study, a tera hertz time domain spectroscopy (THz-TDS) imaging technique was used to measure doping concentration and physical properties (such as refractive index and permittivity) of the doped silicon (Si) wafers. The transmission and reflection modes with an incidence angle of 30° were employed to determine the physical properties of the doped Si wafers. The doping concentrations of the prepared Si wafers were varied from 10{sup 14} to 10{sup 18} in both N-type and P-type cases. Finally, the correlation between the doping concentration and the power of the THz wave was determined by measuring the powers of the transmitted and reflected THz waves of the doped Si wafers. Additionally, the doped thickness, the refractive index, and permittivity of each doped Si wafer were calculated using the THz time domain waveform. The results indicate that the THz-TDS imaging technique is potentially a promising technique to measure the doping concentration as well as other optical properties (such as the refractive index and permittivity) of the doped Si wafer.

  9. Risk assessment of K Basin twelve-inch and four-inch drain valve failure from a postulated seismic initiating event

    Energy Technology Data Exchange (ETDEWEB)

    MORGAN, R.G.

    1999-06-23

    The Spent Nuclear Fuel (SNF) Project will transfer metallic SNF from the Hanford 105 K-East and 105 K-West Basins to safe interim storage in the Canister Storage Building in the 200 Area. The initial basis for design, fabrication, installation, and operation of the fuel removal systems was that the basin leak rate which could result from a postulated accident condition would not be excessive relative to reasonable recovery operations. However, an additional potential K Basin water leak path is through the K Basin drain valves. Three twelve-inch drain valves are located in the main basin bays along the north wall. Five four-inch drain valves are located in the north and south loadout pits (NLOP and SLOP), the weasel pit, the technical viewing pit, and the discharge chute pit. The sumps containing the valves are filled with concrete which covers the drain valve body. Visual observations indicate that only the valve's bonnet and stem are exposed above the basin concrete floor for the twelve-inch drain valve and that much less of the valve's bonnet and stem are exposed above the basin concrete floor for the five four-inch drain valves. It was recognized, however, that damage of the drain valve bonnet or stem during a seismic initiating event could provide a potential K Basin water leak path. The objectives of this analysis are to: (1) evaluate the likelihood of damaging the three twelve-inch drain valves located along the north wall of the main basin and the five four-inch drain valves located in the pits from a seismic initiating event, and (2) determine the likelihood of exceeding a specific consequence (initial leak rate) from a damaged valve. The analysis process is a risk-based uncertainty analysis where each variable is modeled using available information and engineering judgement. The uncertainty associated with each variable is represented by a probability distribution (probability density function). Uncertainty exists because of the inherent

  10. Persentase Karkas Itik Peking yang Diberi Pakan dalam Bentuk Wafer Ransum Komplit Mengandung Limbah Kopi

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2016-04-01

    Full Text Available ABSTRAK. Penggunaan wafer ransum komplit mengandung limbah kopi pada itik peking dilakukan dengan tujuan untuk mengetahui berat akhir dan persentase karkas. Materi penelitian yang digunakan adalah itik peking umur 1 hari (DOD sebanyak 96 ekor dibagi dalam 4 perlakuan dan 3 ulangan. Ransum yang digunakan satu bulan pertama adalah ransum komersil, dan satu bulan terakhir wafer ransum komplit mengandung limbah kopi. Ransum perlakuan yang diberikan adalah: P0 = Wafer ransum komplit 0% limbah kopi (kontrol, P1 = Wafer ransum komplit 2,5% limbah kopi, P2 = Wafer ransum komplit 5% limbah kopi, dan P3 = Wafer ransum komplit 7,5% limbah kopi. Parameter yang diamati: bobot hidup, bobot karkas, bobot potongan karkas, persentase karkas, dan persentase potongan karkas. Penelitian ini menggunakan Rancangan Acak Lengkap. Data dianalisis dengan analysis of variance dan dilanjutkan dengan Uji Duncan. Hasil penelitian menunjukkan penggunaan limbah kulit kopi sebagai bahan penyusun ransum itik peking dalam bentuk wafer ransum komplit berpengaruh nyata terhadap bobot akhir. Penggunaan limbah kulit kopi 2,5% dalam ransum secara signifikan (P<0.05 meningkatkan bobot karkas dan potongan karkas. Dapat disimpulkan penggunaan limbah kulit kopi sebanyak 2,5% sebagai bahan penyusun wafer ransum komplit tidak memberi pengaruh negatif terhadap bobot badan akhir, persentase karkas dan potongan karkas itik peking.    (Carcass percentage of peking duck feed wafer complete ration containing of coffee waste  ABSTRACT. This research was conducted to study the effectiveness of wafer complete ration containing coffee waste on the final body weight and carcass percentage. The study used 96 DOD Peking duck. Completely Randomized Design (CRD consisting of 4 treatments and 3 replications. Rations used during the first month was a commercial ration, and then subsequently wafer complete ration of coffee waste given as treatments; P0 = wafer complete ration contained 0% of coffee waste

  11. Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

    Science.gov (United States)

    Kim, M. S.; Kim, G.; Cho, G.; Kim, D.

    2016-11-01

    A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ~ 50 μm pitch and ~ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

  12. Electro-optical properties of dislocations in silicon and their possible application for light emitters

    Energy Technology Data Exchange (ETDEWEB)

    Arguirov, Tzanimir Vladimirov

    2007-10-14

    This thesis addresses the electro-optical properties of silicon, containing dislocations. The work demonstrates that dislocation specific radiation may provide a means for optical diagnostics of solar cell grade silicon. It provides insight into the mechanisms governing the dislocation recombination activity, their radiation, and how are they influenced by other defects present in silicon. We demonstrate that photoluminescence mapping is useful for monitoring the recombination activity in solar cell grade silicon and can be applied for identification of contaminants, based on their photoluminescence signatures. It is shown that the recombination at dislocations is strongly influenced by the presence of metals at the dislocation sites. The dislocation radiation activity correlates with their electrical activity. It is shown that the dislocation and band-to-band luminescence are essentially anti-correlated. {beta}FeSi{sub 2} precipitates, with a luminescence at 0.8 eV, were detected within the grains of block cast materials. They exhibit a characteristic feature of quantum dots, namely blinking. The second aspect of the thesis concerns the topic of silicon based light emitters for on-chip optical interconnects. The goal is an enhancement of sub-band-gap or band-to-band radiation by controlled formation of dislocation-rich areas in microelectronics-grade silicon as well as understanding of the processes governing such enhancement. For light emitters based on band-to-band emission it is shown, that internal quantum efficiency of nearly 2 % can be achieved, but the emission is essentially generated in the bulk of the wafer. On the other hand, light emitters utilizing the emission from dislocation-rich areas of a well localized wafer depth were explored. Three different methods for reproducible formation of a dislocation-rich region beneath the wafer surface were investigated and evaluated in view of their room temperature sub-band-gap radiation: (1) silicon implantation

  13. Optimizing shape uniformity and increasing structure heights of deep reactive ion etched silicon x-ray lenses

    DEFF Research Database (Denmark)

    Stöhr, Frederik; Wright, Jonathan; Simons, Hugh

    2015-01-01

    Line-focusing compound silicon x-ray lenses with structure heights exceeding 300 μm were fabricated using deep reactive ion etching. To ensure profile uniformity over the full height, a new strategy was developed in which the perimeter of the structures was defined by trenches of constant width....... The remaining sacrificial material inside the lens cavities was removed by etching through the silicon wafer. Since the wafers become fragile after through-etching, they were then adhesively bonded to a carrier wafer. Individual chips were separated using laser micro machining and the 3D shape of fabricated...... analysis, where a slight bowing of the lens sidewalls and an insufficiently uniform apex region are identified as resolution-limiting factors. Despite these, the proposed fabrication route proved a viable approach for producing x-ray lenses with large structure heights and provides the means to improve...

  14. Characterization of Local Strain around Through-Silicon Via Interconnects by Using X-ray Microdiffraction

    Science.gov (United States)

    Nakatsuka, Osamu; Kitada, Hideki; Kim, Youngsuk; Mizushima, Yoriko; Nakamura, Tomoji; Ohba, Takayuki; Zaima, Shigeaki

    2011-05-01

    We have demonstrated the characterization of the local strain structure in thinned Si layers for wafer-on-a-wafer (WOW) applications by using X-ray microdiffraction with a synchrotron radiation source. The microdiffraction reveals the fluctuation of strains in the thin Si layer around through-silicon via (TSV) interconnects with a sub-micrometer scale. We can separately estimated the in-plane and out-of-plane strain structures in the Si layer, and found that the anisotropic strain is induced in the Si layer between the TSV interconnects.

  15. Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Annual Subcontract Report, 1 October 2003--30 September 2004

    Energy Technology Data Exchange (ETDEWEB)

    Wohlgemuth, J.; Narayanan, M.

    2005-03-01

    The major objectives of this program are to continue the advancement of BP Solar polycrystalline silicon manufacturing technology. The program includes work in the following areas: Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations; developing wire saws to slice 100- m-thick silicon wafers on 290- m centers; developing equipment for demounting and subsequent handling of very thin silicon wafers; developing cell processes using 100- m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%; expanding existing in-line manufacturing data reporting systems to provide active process control; establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology; facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock.

  16. Large-Scale PV Module Manufacturing Using Ultra-Thin Polycrystalline Silicon Solar Cells: Final Subcontract Report, 1 April 2002--28 February 2006

    Energy Technology Data Exchange (ETDEWEB)

    Wohlgemuth, J.; Narayanan, M.

    2006-07-01

    The major objectives of this program were to continue advances of BP Solar polycrystalline silicon manufacturing technology. The Program included work in the following areas. (1) Efforts in the casting area to increase ingot size, improve ingot material quality, and improve handling of silicon feedstock as it is loaded into the casting stations. (2) Developing wire saws to slice 100-..mu..m-thick silicon wafers on 290-..mu..m-centers. (3) Developing equipment for demounting and subsequent handling of very thin silicon wafers. (4) Developing cell processes using 100-..mu..m-thick silicon wafers that produce encapsulated cells with efficiencies of at least 15.4% at an overall yield exceeding 95%. (5) Expanding existing in-line manufacturing data reporting systems to provide active process control. (6) Establishing a 50-MW (annual nominal capacity) green-field Mega-plant factory model template based on this new thin polycrystalline silicon technology. (7) Facilitating an increase in the silicon feedstock industry's production capacity for lower-cost solar-grade silicon feedstock..

  17. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  18. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  19. Conoscopic interferometry of wafers for surface-acoustic wave devices

    OpenAIRE

    Äyräs, Pekka; Friberg, Ari T.; Kaivola, Matti; Salomaa, Martti M.

    1997-01-01

    We show that in interpreting the conoscopic interference fringes, one should exercise care in employing approximate expressions which fail for certain crystal cuts. In this paper, we study 64°- and 128°-rotated Y-cut and Z-cut LiNbO3 wafers. We show that the error made in using the approximate formulae for the samples is more than 25% and that one has to use exact formulae in order to attain quantitative agreement with the experimental data. Peer reviewed

  20. Development of gamma spectroscopy employing NaI(Tl) detector 3 inch x 3 inch and readout electronic of flash-ADC/FPGA-based technology

    Energy Technology Data Exchange (ETDEWEB)

    Hai, Vo Hong [HCMC-National Univ., Hochiminh City (Viet Nam). Inst. of Nuclear Physics; Ton Duc Thang Univ., Ho Chi Minh City (Viet Nam). Div. of Nuclear Physics; Hung, Nguyen Quoc [HCMC-National Univ., Hochiminh City (Viet Nam). Inst. of Nuclear Physics; Khai, Bui Tuan [Osaka Univ. (Japan). Dept. of Physics

    2015-05-15

    n this article the development of a gamma spectroscopy system is described using a scintillation detector NaI(Tl) of 3 inch x 3 inch. The readout electronic for the spectroscopy is built from the fast analog-digital conversion of Flash Analog-Digital Converter (Flash-ADC) 250 MHz - 8 bits resolution, and the embedded Field-Programmable Gate Array (FPGA) technology. The embedded VHSIC Hardware Description Language (VHDL) code for FPGA is built in such a way that it works as a multi channel analyser (MCA) with 4096 Digital Charge Integration (DCI) channels. A pulse generator with frequency varying from Hz up to 12 kHz is used to evaluate the time response of the system. Two standard radioisotope sources of {sup 133}Ba and {sup 152}Eu with multi gamma energies ranging from several tens keV to MeV are used to evaluate the linearity and energy resolution of the system.