WorldWideScience

Sample records for implantable cmos amplifier

  1. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  2. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  3. Chopper amplifier circuit with CMOS switches and amplifier FETs

    NARCIS (Netherlands)

    Huijsing, J.H.; Bakker, A.

    1997-01-01

    Abstract of NL 1001231 (C2) The input voltage is fed to the inputs of an operational amplifier via a chopping reversal switchThe CMOS operational amplifier has a current source and a current mirror. The operational amplifier output is fed to an output circuit. The possible offset voltage is supp

  4. A CMOS current-mode operational amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1993-01-01

    A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...... current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2...

  5. CMOS Current-mode Operational Amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1992-01-01

    A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...... current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-range ±700¿A) and a (theoretically) unlimited slew-rate. The amplifier is realized in a standard CMOS 2...

  6. CMOS current amplifiers : speed versus nonlinearity

    OpenAIRE

    2000-01-01

    This work deals with analogue integrated circuit design using various types of current-mode amplifiers. These circuits are analysed and realised using modern CMOS integration technologies. The dynamic nonlinearities of these circuits are discussed in detail as in the literature only linear nonidealities and static nonlinearities are conventionally considered. For the most important open-loop current-mode amplifier, the second-generation current-conveyor (CCII), a macromodel is derived tha...

  7. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique...

  8. Analysis of bipolar and CMOS amplifiers

    CERN Document Server

    Sodagar, Amir M

    2007-01-01

    The classical approach to analog circuit analysis is a daunting prospect to many students, requiring tedious enumeration of contributing factors and lengthy calculations. Most textbooks apply this cumbersome approach to small-signal amplifiers, which becomes even more difficult as the number of components increases. Analysis of Bipolar and CMOS Amplifiers offers students an alternative that enables quick and intuitive analysis and design: the analysis-by-inspection method.This practical and student-friendly text demonstrates how to achieve approximate results that fall within an acceptable ran

  9. CMOS SiPM with integrated amplifier

    Science.gov (United States)

    Schwinger, Alexander; Brockherde, Werner; Hosticka, Bedrich J.; Vogt, Holger

    2017-02-01

    The integration of silicon photomultiplier (SiPM) and frontend electronics in a suitable optoelectronic CMOS process is a promising approach to increase the versatility of single-photon avalanche diode (SPAD)-based singlephoton detectors. By integrating readout amplifiers, the device output capacitance can be reduced to minimize the waveform tail, which is especially important for large area detectors (>10 × 10mm2). Possible architectures include a single readout amplifier for the whole detector, which reduces the output capacitance to 1:1 pF at minimal reduction in detector active area. On the other hand, including a readout amplifier in every SiPM cell would greatly improve the total output capacitance by minimizing the influence of metal routing parasitic capacitance, but requiring a prohibitive amount of detector area. As tradeoff, the proposed detector features one readout amplifier for each column of the detector matrix to allow for a moderate reduction in output capacitance while allowing the electronics to be placed in the periphery of the active detector area. The presented detector with a total size of 1.7 ♢ 1.0mm2 features 400 cells with a 50 μm pitch, where the signal of each column of 20 SiPM cells is summed in a readout channel. The 20 readout channels are subsequently summed into one output channel, to allow the device to be used as a drop-in replacement for commonly used analog SiPMs.

  10. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  11. Design of 2.1 GHz CMOS Low Noise Amplifier

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    This paper discusses the design of a fully differential 2.1 GHz CMOS low noise amplifier using the TSMC0.25 μm CMOS process. Intended for use in 3G, the low noise amplifier is fully integrated and without off-chip components. The design uses an LC tank to replace a large inductor to achieve a smaller die area, and uses shielded pad capacitances to improve the noise performance. This paper also presents evaluation results of the design.

  12. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...

  13. A New CMOS Current-Mode Folding Amplifier

    Directory of Open Access Journals (Sweden)

    M.A Al-Absi

    2013-09-01

    Full Text Available In this paper, a new CMOS current-mode folding amplifier is proposed. The circuit is designed using MOSFETs operating in strong inversion. The design produces a nearly ideal saw-tooth input-output characteristic which is a mandatory requirement in folding analog-to-digital converters. The functionality of the proposed circuit was confirmed using Tanner simulation tools in 0.35 µm CMOS technology. Simulation results are in excellent agreement with the theory.

  14. Power amplifiers in CMOS technology : a contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, Mustafa

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers(PAs) in the mainstream CMOS technology is essential. In general, CMOS PAs require high supply-voltage to decrease the matching network losses and for high output pow

  15. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  16. A CMOS low-noise instrumentation amplifier using chopper modulation

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2005-01-01

    This paper describes a low-power, low-noise chopper stabilized CMOS instrumentation amplifier for biomedical applications. Low thermal noise is achieved by employing MOSTs biased in the weak/moderate inversion region, whereas chopper stabilization is utilized to shift 1/f-noise out of the signal...

  17. Design and Analysis of Hybrid CMOS SRAM Sense Amplifier

    Directory of Open Access Journals (Sweden)

    Karishma Bajaj

    2012-03-01

    Full Text Available Sense amplifiers are one of the very important peripheral components of CMOS memories. In a Hybrid Sense amplifier both current and voltage sensing techniques are used which makes it a better selection than a conventional current or voltage sense amplifiers. The hybrid sense amplifier works in three phases-Offset cancellation (200ps, Access phase (500ps and Evaluation phase. The offset cancellation is done simultaneously with word line decoding, so as to speed up the process. The sensing range of the hybrid sense amplifier is improved from 1.18mV to 92mV. Also hybrid sense amplifier consumes very low energy of about 6.84fj. This sense amplifier is analyzed with a column of 512 SRAM cells at 180nm technology node and compared to CMOS conventional voltage sense amplifier. The circuit consumes an average power of 1.57 µW with a negligible offset of 149.3µV.

  18. Design procedure for optimizing CMOS low noise operational amplifiers

    Institute of Scientific and Technical Information of China (English)

    Li Zhiyuan; Ye Yizheng; Ma Jianguo

    2009-01-01

    This paper presents and experimentally verifies an optimized design procedure for a CMOS low noise operational amplifier.The design procedure focuses on the noise performance,which is the key requirement for low noise operational amplifiers.Based on the noise level and other specifications such as bandwidth,signal swing,slew rate,and power consumption,the device sizes and the biasing conditions are derived.In order to verify the proposed design procedure,a three-stage operational amplifier has been designed.The device parameters obtained from the proposed design procedure closely agree with the simulated results obtained by using HSPICE.

  19. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  20. A CMOS single-supply logarithmic amplifier for hearing aids

    Science.gov (United States)

    Jarng, Soon Suck; Chen, Lingfeng; Kwon, You Jung

    2005-12-01

    The Log Amplifier described in this paper is designed for hearing aids (HA) application. It works on a low single-supply voltage (1.3V). The input signal varies between 0.01mV and 100mV. To give enough compensation to the hearing impairment, the amplifier provides a very large gain. The output swing is limited because of the low supply voltage and the large gain. Therefore, the logarithmic amplifier introduced into the design of HA to compress input signal so that the output distortion can be avoid. Another factor we use it here is that the amplifier has enough sensitivity and gain to deal with the compressed input signal without getting extra distortion coursed by the pre-process on input signal. The short channel CMOS devices play an important role in reduction of the supply voltage. DONG-BU ANAM 0.18 μm process is selected.

  1. Design of a high frequency low voltage CMOS operational amplifier

    Directory of Open Access Journals (Sweden)

    Priyanka Kakoty

    2011-03-01

    Full Text Available A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMPdesigned is a two-stage CMOS OPAMP followed by an output buffer. This Operational Transconductance Amplifier (OTA employs a Miller capacitor and is compensated with a current buffer compensation technique. The unique behaviour of the MOS transistors in saturation region not only allows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-ampsis a multi-dimensional-optimization problem where optimization of one or more parameters may easily result into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHzand exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, the proposed compensation method results in a higher unity gain frequency under the same load condition.Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

  2. Design of a high frequency low voltage CMOS operational amplifier

    Directory of Open Access Journals (Sweden)

    Priyanka Kakoty

    2011-03-01

    Full Text Available A method is presented in this paper for the design of a high frequency CMOS operational amplifier (Op-Amp which operates at 3V power supply using tsmc 0.18 micron CMOS technology. The OPAMPdesigned is a two-stage CMOS OPAMP followed by an output buffer. This OperationalTransconductance Amplifier (OTA employs a Miller capacitor and is compensated with a current buffercompensation technique. The unique behaviour of the MOS transistors in saturation region not onlyallows a designer to work at a low voltage, but also at a high frequency. Designing of two-stage op-ampsis a multi-dimensional-optimization problem where optimization of one or more parameters may easilyresult into degradation of others. The OPAMP is designed to exhibit a unity gain frequency of 2.02GHzand exhibits a gain of 49.02dB with a 60.50 phase margin. As compared to the conventional approach, theproposed compensation method results in a higher unity gain frequency under the same load condition.Design has been carried out in Tanner tools. Simulation results are verified using S-edit and W-edit.

  3. A compact nanopower low output impedance CMOS operational amplifier for wireless intraocular pressure recordings.

    Science.gov (United States)

    Dresher, Russell P; Irazoqui, Pedro P

    2007-01-01

    Wireless sensing has shown potential benefits for the continuous-time measurement of physiological data. One such application is the recording of intraocular pressure (IOP) for patients with glaucoma. Ultra-low-power circuits facilitate the use of inductively-coupled power for implantable wireless systems. Compact circuit size is also desirable for implantable systems. As a first step towards the realization of such circuits, we have designed a compact, ultra-low-power operational amplifier which can be used to record IOP. This paper presents the measured results of a CMOS operational amplifier that can be incorporated with a wireless IOP monitoring system or other low-power application. It has a power consumption of 736 nW, chip area of 0.023 mm2, and output impedance of 69 Omega to drive low-impedance loads.

  4. OperationalAmplifier Analysis when Migrating from 0.18 µm to 65 µm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Karolis Kiela

    2013-05-01

    Full Text Available The article offers the analysis of operational amplifier parameter changes, when circuits are scaled from 0.18 μm to 65 nm CMOS technology. Two two-stage operational amplifiers were designed for this purpose: first uses n-MOS input differential pair; second uses cascaded active loads structure and p-MOS type input differential pair. The operational amplifiers were designed in 0.18 μm CMOS technology and scaled to 65 nm CMOS. Other scaling methods were also analysed when redesigning circuits from one IC technology to another. Results of the original and scaled operational amplifier parameters are presented and analysed.Article in Lithuanian

  5. Performance Analysis of Low Power, High Gain Operational Amplifier Using CMOS VLSI Design

    Directory of Open Access Journals (Sweden)

    Ankush S. Patharkar

    2014-07-01

    Full Text Available The operational amplifier is one of the most useful and important component of analog electronics. They are widely used in popular electronics. Their primary limitation is that they are not especially fast. The typical performance degrades rapidly for frequencies greater than about 1 MHz, although some models are designed specifically to handle higher frequencies. The primary use of op-amps in amplifier and related circuits is closely connected to the concept of negative feedback. The operational amplifier has high gain, high input impedance and low output impedance. Here the operational amplifier designed by using CMOS VLSI technology having low power consumption and high gain.

  6. 高精度CMOS DEM-CCⅡ放大器%High-Precision CMOS DEM-CC Ⅱ Amplifier

    Institute of Scientific and Technical Information of China (English)

    张雷; 成立; 周洋; 张静; 倪雪梅; 王振宇

    2009-01-01

    采用动态元件匹配二代电流传输器(DEM-CCⅡ)技术,设计了一种0.35 μm标准工艺的高精度CMOS放大器.通过比较传统的CMOS运放可知,所设计的CMOS放大器既增大了输出摆幅又减小了输出阻抗,且有效地限制了有限的运放增益对电路性能的影响.仿真实验结果表明,该CMOS放大器增益误差比传统运放的增益误差小38~50倍,精度等级明显提高,因而特别适用于各类检测和信号调理放大器的设计中.%CMOS amplifiers with high-precision was designed in a standard 0.35 μm CMOS process by properly applying dynamic element matching to a second generation current conveyor. Compared with traditional CMOS circuits, the proposed approach alleviates the tradeoff between output swing and output resistance and is more robust against the finite operational amplifier gain. The simulation results show that the gain error is reduced 38~50 times than the gain error of operational amplifiers, and the precision is improved, it is very suitable for the design of various detections and signal conditioning amplifiers.

  7. Automatic Frequency Controller for Power Amplifiers Used in Bio-Implanted Applications: Issues and Challenges

    Directory of Open Access Journals (Sweden)

    Mahammad A. Hannan

    2014-12-01

    Full Text Available With the development of communication technologies, the use of wireless systems in biomedical implanted devices has become very useful. Bio-implantable devices are electronic devices which are used for treatment and monitoring brain implants, pacemakers, cochlear implants, retinal implants and so on. The inductive coupling link is used to transmit power and data between the primary and secondary sides of the biomedical implanted system, in which efficient power amplifier is very much needed to ensure the best data transmission rates and low power losses. However, the efficiency of the implanted devices depends on the circuit design, controller, load variation, changes of radio frequency coil’s mutual displacement and coupling coefficients. This paper provides a comprehensive survey on various power amplifier classes and their characteristics, efficiency and controller techniques that have been used in bio-implants. The automatic frequency controller used in biomedical implants such as gate drive switching control, closed loop power control, voltage controlled oscillator, capacitor control and microcontroller frequency control have been explained. Most of these techniques keep the resonance frequency stable in transcutaneous power transfer between the external coil and the coil implanted inside the body. Detailed information including carrier frequency, power efficiency, coils displacement, power consumption, supplied voltage and CMOS chip for the controllers techniques are investigated and summarized in the provided tables. From the rigorous review, it is observed that the existing automatic frequency controller technologies are more or less can capable of performing well in the implant devices; however, the systems are still not up to the mark. Accordingly, current challenges and problems of the typical automatic frequency controller techniques for power amplifiers are illustrated, with a brief suggestions and discussion section concerning

  8. Automatic frequency controller for power amplifiers used in bio-implanted applications: issues and challenges.

    Science.gov (United States)

    Hannan, Mahammad A; Hussein, Hussein A; Mutashar, Saad; Samad, Salina A; Hussain, Aini

    2014-12-11

    With the development of communication technologies, the use of wireless systems in biomedical implanted devices has become very useful. Bio-implantable devices are electronic devices which are used for treatment and monitoring brain implants, pacemakers, cochlear implants, retinal implants and so on. The inductive coupling link is used to transmit power and data between the primary and secondary sides of the biomedical implanted system, in which efficient power amplifier is very much needed to ensure the best data transmission rates and low power losses. However, the efficiency of the implanted devices depends on the circuit design, controller, load variation, changes of radio frequency coil's mutual displacement and coupling coefficients. This paper provides a comprehensive survey on various power amplifier classes and their characteristics, efficiency and controller techniques that have been used in bio-implants. The automatic frequency controller used in biomedical implants such as gate drive switching control, closed loop power control, voltage controlled oscillator, capacitor control and microcontroller frequency control have been explained. Most of these techniques keep the resonance frequency stable in transcutaneous power transfer between the external coil and the coil implanted inside the body. Detailed information including carrier frequency, power efficiency, coils displacement, power consumption, supplied voltage and CMOS chip for the controllers techniques are investigated and summarized in the provided tables. From the rigorous review, it is observed that the existing automatic frequency controller technologies are more or less can capable of performing well in the implant devices; however, the systems are still not up to the mark. Accordingly, current challenges and problems of the typical automatic frequency controller techniques for power amplifiers are illustrated, with a brief suggestions and discussion section concerning the progress of

  9. A CMOS class-AB transconductance amplifier for switched-capacitor applications

    NARCIS (Netherlands)

    Rijns, J.J.F.; Rijns, J.J.F.; Wallinga, Hans

    1990-01-01

    A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high

  10. A CMOS class-AB transconductance amplifier for switched-capacitor applications

    NARCIS (Netherlands)

    Rijns, J.J.F.; Rijns, J.J.F.; Wallinga, Hans

    1990-01-01

    A CMOS operational transconductance amplifier (OTA) using a fully differential single-stage core OTA as the input stage and a differential to single current converter as the output stage, each biased at a separate current level, is presented. A large gain-bandwidth product (2.7 MHz) and a high slew-

  11. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R. [Oak Ridge National Lab., TN (United States); Moscone, C.G. [Tennessee Univ., Knoxville, TN (United States)

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 {micro}m Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results.

  12. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Institute of Scientific and Technical Information of China (English)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  13. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  14. New Simple CMOS Realization of Voltage Differencing Transconductance Amplifier and Its RF Filter Application

    Directory of Open Access Journals (Sweden)

    A. Yeşil

    2011-09-01

    Full Text Available The voltage differencing transconductance amplifier (VDTA is a recently introduced active element for analog signal processing. However, the realization of VDTA is not given by any author yet. In this work, a new and simple CMOS realization of VDTA is presented. The proposed block has two voltage inputs and two kinds of current output, so it is functional for voltage- and transconductance-mode operation. Furthermore, VDTA exhibits two different values of transconductance so that there is no need to external resistors for VDTA based applications which seems to be a good advantage for analog circuit designer. A CMOS implementation of VDTA and a voltage-mode VDTA based filter are proposed and simulated. An application example of fourth order flat-band band-pass amplifier is given and the performance of the circuit is demonstrated by comparing the theory and simulation.

  15. Fixed-gain CMOS differential amplifiers with no external feedback for a wide temperature range

    Science.gov (United States)

    Michal, Vratislav; Klisnick, Geoffroy; Sou, Gérard; Redon, Michel; Kreisler, Alain J.; Dégardin, Annick F.

    2009-11-01

    We present original CMOS amplifiers designed for the DC to 10 MHz frequency range and operating in the 70-380 K temperature range. Aimed applications concern readout circuitry to be associated with THz bolometric pixels (either high- Tc superconducting or uncooled semiconducting), which require accuracy, low noise and low power consumption. Two designs are described that both exhibit high fixed-gain (40 dB) in a feedback-free architecture, which is based on a new low-transconductance composite transistor for an accurate control of this gain. Both amplifiers have been realized in a regular 0.35 μm CMOS process and tested in the 4.2-380 K temperature range, exhibiting good agreement between designed and measured characteristics.

  16. Analysis of CMOS Transconductance Amplifiers for Sampling Mixers

    Science.gov (United States)

    Li, Ning; Chaivipas, Win; Okada, Kenichi; Matsuzawa, Akira

    In this paper the transfer function of a system with windowed current integration is discussed. This kind of integration is usually used in a sampling mixer and the current is generated by a transconductance amplifier (TA). The parasitic capacitance (Cp) and the output resistance of the TA (Ro,TA) before the sampling mixer heavily affect the performance. Calculations based on a model including the parasitic capacitance and the output resistance of the TA is carried out. Calculation results show that due to the parasitic capacitance, a notch at the sampling frequency appears, which is very harmful because it causes the gain near the sampling frequency to decrease greatly. The output resistance of the TA makes the depth of the notches shallow and decreases the gain near the sampling frequency. To suppress the effect of Cp and Ro,TA, an operational amplifier is introduced in parallel with the sampling capacitance (Cs). Simulation results show that there is a 17dB gain increase while Cs is 1pF, gm is 9mS, N is 8 with a clock rate of 800MHz.

  17. Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

    OpenAIRE

    Akshay Kumar Kansal; Asst Prof. Gayatri Sakya

    2015-01-01

    CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V, the power consumption, slew rate and settling t...

  18. Design of an Operational Amplifier for High Performance Pipelined ADCs in 65nm CMOS

    OpenAIRE

    Payami, Sima

    2012-01-01

    In this work, a fully differential Operational Amplifier (OpAmp) with high Gain-Bandwidth (GBW), high linearity and Signal-to-Noise ratio (SNR) has been designed in 65nm CMOS technology with 1.1v supply voltage. The performance of the OpAmp is evaluated using Cadence and Matlab simulations and it satisfies the stringent requirements on the amplifier to be used in a 12-bit pipelined ADC. The open-loop DC-gain of the OpAmp is 72.35 dB with unity-frequency of 4.077 GHz. Phase-Margin (PM) of the ...

  19. Low Power and Fast Transient High Swing CMOS Telescopic Operational Amplifier

    Directory of Open Access Journals (Sweden)

    Akshay Kumar Kansal

    2015-12-01

    Full Text Available CMOS telescopic operational amplifier with high-swing and high-performance is described in this paper. The swing is attained by using the tail and current source-transistors in deep-linear region. The resultant deprivation in parameters like differential gain, CMRR and added characteristics are recompensed by using regulatedcascode differential gain enhancement and a replica-tail feedback technique. Operating at power supply of 3.3V, the power consumption, slew rate and settling time are improved using transmission controlled pass circuitry and level amplifier. It is shown through simulations that the Op-Amp preserves its high CMRR and unity gain frequency.

  20. Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

    Science.gov (United States)

    Ming Gu; Chakrabartty, Shantanu

    2014-06-01

    This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

  1. A high efficiency PWM CMOS class-D audio power amplifier

    Institute of Scientific and Technical Information of China (English)

    朱樟明; 刘帘曦; 杨银堂; 雷晗

    2009-01-01

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  2. A high efficiency PWM CMOS class-D audio power amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Zhu Zhangming; Liu Lianxi; Yang Yintang [Institute of Microelectronics, Xidian University, Xi' an 710071 (China); Lei Han, E-mail: zmyh@263.ne [Xi' an Power-Rail Micro Co., Ltd, Xi' an 710075 (China)

    2009-02-15

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 mum CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 muA. The active area of the class-D audio power amplifier is about 1.47 x 1.52 mm{sup 2}. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  3. High-gain cryogenic amplifier assembly employing a commercial CMOS operational amplifier.

    Science.gov (United States)

    Proctor, J E; Smith, A W; Jung, T M; Woods, S I

    2015-07-01

    We have developed a cryogenic amplifier for the measurement of small current signals (10 fA-100 nA) from cryogenic optical detectors. Typically operated with gain near 10(7) V/A, the amplifier performs well from DC to greater than 30 kHz and exhibits noise level near the Johnson limit. Care has been taken in the design and materials to control heat flow and temperatures throughout the entire detector-amplifier assembly. A simple one-board version of the amplifier assembly dissipates 8 mW to our detector cryostat cold stage, and a two-board version can dissipate as little as 17 μW to the detector cold stage. With current noise baseline of about 10 fA/(Hz)(1/2), the cryogenic amplifier is generally useful for cooled infrared detectors, and using blocked impurity band detectors operated at 10 K, the amplifier enables noise power levels of 2.5 fW/(Hz)(1/2) for detection of optical wavelengths near 10 μm.

  4. Continuous-Time ΣΔ ADC with Implicit Variable Gain Amplifier for CMOS Image Sensor

    Directory of Open Access Journals (Sweden)

    Fang Tang

    2014-01-01

    amplifier (OTA, for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  5. A CMOS variable gain amplifier for PHENIX electromagnetic calorimeter and RICH energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Simpson, M.L.; Young, G.R. [Oak Ridge National Lab., TN (United States); Palmer, R.L.; Moscone, C.G.; Jackson, R.G. [Tennessee Univ., Knoxville, TN (United States)

    1996-12-31

    A variable gain amplifier (VGA) has been developed equalizing the gains of integrating amplifier channels used with multiple photomultiplier tubes operating from common high-voltage supplies. The PHENIX lead-scintillator electromagnetic calorimeter will operate in that manner, and gain equalization is needed to preserve the dynamic range of the analog memory and ADC following the integrating amplifier. The VGA is also needed for matching energy channel gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5-bit digital control, and the risetime is held between 15 and 23 ns using switched compensation in the VGA. An additional feature is gated baseline restoration. Details of the design and results from several prototype devices fabricated in 1.2-{mu}m Orbit CMOS are presented.

  6. An integrated low 1/f noise and high-sensitivity CMOS instrumentation amplifier for TMR sensors

    Science.gov (United States)

    Gao, Zhiqiang; Luan, Bo; Zhao, Jincai; Liu, Xiaowei

    2017-03-01

    In this paper, a very low 1/f noise integrated Wheatstone bridge magnetoresistive sensor ASIC based on magnetic tunnel junction (MTJ) technology is presented for high sensitivity measurements. The present CMOS instrumentation amplifier employs the gain-boost folded-cascode structure based on the capacitive-feedback chopper-stabilized technique. By chopping both the input and the output of the amplifier, combined with MTJ magnetoresistive sensitive elements, a noise equivalent magnetoresistance 1 nT/Hz1/2 at 2 Hz, the equivalent input noise spectral density 17 nV/Hz1/2(@2Hz) is achieved. The chip-scale package of the TMR sensor and the instrumentation amplifier is only about 5 mm × 5 mm × 1 mm, while the whole DC current dissipates only 2 mA.

  7. Design Considerations for CMOS Current Mode Operational Amplifiers and Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    This dissertation is about CMOS current conveyors and current mode operational amplifiers (opamps). They are generic devices for continuous time signal processing in circuits and systems where signals are represented by currents.Substantial advancements are reported in the dissertation, both...... implementations of current mode opamps in CMOS technology are described. Also, current conveyor configurations with multiple outputs and flexible feedback connections from outputs to inputs are introduced. The dissertation includes several examples of circuit configurations ranging from simple class A and class...... AB conveyor implementations to implementations based on purely digital circuit structures and on more complex analog subsystems such as a voltage mode opamp with feedback to provide a voltage follower action. An important by-product of the investigation of current mode structures is the definition...

  8. Design Considerations for CMOS Current Mode Operational Amplifiers and Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    This dissertation is about CMOS current conveyors and current mode operational amplifiers (opamps). They are generic devices for continuous time signal processing in circuits and systems where signals are represented by currents.Substantial advancements are reported in the dissertation, both...... related to circuit implementations and system configurations and to an analysis of the fundamental limitations of the current mode technique.In the field of system configurations and circuit implementations different configurations of high gain current opamps are introduced and some of the first...... implementations of current mode opamps in CMOS technology are described. Also, current conveyor configurations with multiple outputs and flexible feedback connections from outputs to inputs are introduced. The dissertation includes several examples of circuit configurations ranging from simple class A and class...

  9. A highly linear fully integrated CMOS power amplifier with an analog predistortion technique

    Energy Technology Data Exchange (ETDEWEB)

    Jin Boshi; Li Lewei; Wu Qun; Yang Guohui; Zhang Kuang, E-mail: boshijin@rdamicro.com [Department of Electronic and Communications Engineering, Harbin Institute of Technology, Harbin 150001 (China)

    2011-05-15

    A transformer-based CMOS power amplifier (PA) is linearized using an analog predistortion technique for a 2.5-GHz m-WiMAX transmitter. The third harmonic of the power stage and driver stage can be cancelled out in a specific power region. The two-stage PA fabricated in a standard 0.18-{mu}m CMOS process delivers 27.5 dBm with 27% PAE at the 1-dB compression point (P{sub 1dB}) and offers 21 dB gain. The PA achieves 5.5 % EVM and meets the spectrum mask at 20.5 dBm average power. Another conventional PA with a zero-cross-point of g{sub m3} bias is also fabricated and compared to prove its good linearity and efficiency. (semiconductor devices)

  10. Design and Characterization of two stage High-Speed CMOS Operational Amplifier

    Directory of Open Access Journals (Sweden)

    Rahul Chaudhari

    2014-03-01

    Full Text Available A method described in this paper is to design a Two Stage CMOS operational amplifier and analyze the effect of various aspect ratios on the characteristics of this Op-Amp, which operates at 1.8V power supply using tsmc 0.18μm CMOS technology. In this paper trade-off curves are computed between all characteristics such as Gain, PM, GBW, ICMRR, CMRR, Slew Rate etc. The OPAMP designed is a two-stage CMOS OPAMP. The OPAMP is designed to exhibit a unity gain frequency of 14MHz and exhibits a gain of 59.98dB with a 61.235 phase margin. Design has been carried out in Mentor graphics tools. Simulation results are verified using Model Sim Eldo and Design Architect IC. The task of CMOS operational amplifiers (Op-Amps design optimization is investigated in this work. This Paper focused on the optimization of various aspect ratios, which gave the result of different parameter. When this task is analyzed as a search problem, it can be translated into a multi-objective optimization application in which various Op-Amps’ specifications have to be taken into account, i.e., Gain, GBW (gain-bandwidth product, phase margin and others. The results are compared with respect to standard characteristics of the op-amp with the help of graph and table. Simulation results agree with theoretical predictions. Simulations confirm that the settling time can be further improved by increasing the value of GBW, the settling time is achieved 19ns. It has been demonstrated that when W/L increases the parameters GBW increases and settling time reduces.

  11. Continuous-time ΣΔ ADC with implicit variable gain amplifier for CMOS image sensor.

    Science.gov (United States)

    Tang, Fang; Bermak, Amine; Abbes, Amira; Benammar, Mohieddine Amor

    2014-01-01

    This paper presents a column-parallel continuous-time sigma delta (CTSD) ADC for mega-pixel resolution CMOS image sensor (CIS). The sigma delta modulator is implemented with a 2nd order resistor/capacitor-based loop filter. The first integrator uses a conventional operational transconductance amplifier (OTA), for the concern of a high power noise rejection. The second integrator is realized with a single-ended inverter-based amplifier, instead of a standard OTA. As a result, the power consumption is reduced, without sacrificing the noise performance. Moreover, the variable gain amplifier in the traditional column-parallel read-out circuit is merged into the front-end of the CTSD modulator. By programming the input resistance, the amplitude range of the input current can be tuned with 8 scales, which is equivalent to a traditional 2-bit preamplification function without consuming extra power and chip area. The test chip prototype is fabricated using 0.18 μm CMOS process and the measurement result shows an ADC power consumption lower than 63.5 μW under 1.4 V power supply and 50 MHz clock frequency.

  12. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    Energy Technology Data Exchange (ETDEWEB)

    Herve, C. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France)]. E-mail: herve@esrf.fr; Dzahini, D. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Le Caer, T. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France); Richer, J.-P. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Torki, K. [Laboratoire TIMA, Grenoble (France)

    2005-03-21

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 K{omega}), bandwidth (25 MHz) and noise (1570 e{sup -}+95 e{sup -}/pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements.

  13. Wideband high efficiency CMOS envelope amplifiers for 4G LTE handset envelope tracking RF power amplifiers

    OpenAIRE

    Hassan, Muhammad

    2012-01-01

    Fourth generation cellular networks offer performance similar to cable modems while allowing wide mobility. Although the use of orthogonal frequency division multiplexing in fourth generation increases its spectral efficiency but it also increases the peak-to-average power ratio of the transmitted signal. If a conventional power amplifier is used to transmit a high peak-to-average power ratio signal, then to meet the stringent linearity requirements, it will be operating 6 to 10 dB back-off f...

  14. An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

    Science.gov (United States)

    DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

    2016-01-01

    This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

  15. Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

    Directory of Open Access Journals (Sweden)

    Ler Chun Lee

    2008-01-01

    Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

  16. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  17. Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

    Directory of Open Access Journals (Sweden)

    Abdelhamid Benazzouz

    2013-09-01

    Full Text Available Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA with the capability of recording local field potentials (LFP and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µVRMS. Ability of the NA to perform spike recording in test-bench experiments is presented. Additionally, an awake and freely moving rodent setup was used to illustrate the integrated NA ability to record LFPs, paving the pathway for future implantable systems for neuromodulation.

  18. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  19. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    Science.gov (United States)

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  20. Low Power CMOS Operational Amplifier with Integrated Common-Mode Feedback for Data Converter

    Directory of Open Access Journals (Sweden)

    Murad S.A.Z

    2017-01-01

    Full Text Available The development a high-performance design of analog circuits becomes increasingly challenging with the continuous trend towards reducing the voltage supply and low power consumption without neglecting the trade-off among other performance parameters. This paper presents the design and implementation of CMOS operational amplifier (op-amp with integrated common-mode feedback (CMFB circuit for data converter using 0.13-μm Silterra CMOS technology. The folded cascode topology is employed as a main op-amp design because it provides high gain and high bandwidth besides low power consumption. The simulation results indicate that the DC gain of 64.5 dB along 133.1 MHz unity gain bandwidth (UGB is achieved for a 1 pF load capacitor. The slew rate of 22.6 V/μs, the phase margin (PM of 68.4° with settling time of 72.4 ns are obtained. The power consumption of this op-amp is 0.3 mW through voltage supply of 1.8 V.

  1. Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

    Science.gov (United States)

    Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

    2009-05-01

    This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

  2. A 3-5 GHz CMOS UWB power amplifier with {+-}8 ps group delay ripple

    Energy Technology Data Exchange (ETDEWEB)

    Xi Tianzuo; Huang Lu; Zheng Zhong; Feng Lisong, E-mail: xitianzuo@hotmail.co [Department of Electronic Science and Technology, University of Science and Technology of China, Hefei 230027 (China)

    2010-04-15

    A differential power amplifier (PA), designed using the linear-phase filter model, for a BPSK modulated ultra-wideband (UWB) system operating in the 3-5 GHz frequency range is presented. The proposed PA was fabricated using 0.18 {mu}m SMIC CMOS technology. To achieve sufficient linearity and efficiency, this PA operates in the class-AB region, delivering an output power of 8.5 dBm at an input-1 dB compression point of -0.5 dBm. It consumes 28.8 mW, realizing a flat gain of 9.11 {+-} 0.39 dB and a very low group delay ripple of {+-}8 ps across the whole band of operation. (semiconductor integrated circuits)

  3. A High Performance CMOS Current Mirror Circuit with Neuron MOSFETs and a Transimpedance Amplifier

    Science.gov (United States)

    Shimizu, Akio; Ishikawa, Yohei; Fukai, Sumio; Aikawa, Masayoshi

    In this paper, we propose a high accuracy current mirror circuit suitable for a low-voltage operation. The proposed circuit has a novel negative feedback that is composed of neuron MOSFETs and a transimpedance amplifier. As a result, the proposed circuit achieves a high accuracy current mirror circuit. At the same time, the proposed circuit monitors an error current by a low voltage because the negative feedback operates in a current-mode. The performance of the proposed circuit is evaluated using HSPICE simulation with On-Semiconductor 1.48μm CMOS device parameters. Simulation results show that the output resistance of the proposed circuit is 5.79[GΩ] and minimum operating range is 0.3[V].

  4. 0.18μm CMOS Low Voltage Power Amplifier For WSN Application

    Directory of Open Access Journals (Sweden)

    Wu Chenjian

    2013-08-01

    Full Text Available This paper presents the design of a Class A/B power amplifier (PA for 2.4-2.4835GHz Wireless Sensor Network (WSN system in 0.18μm CMOS technology. The PA adopts the single-stage differential structure and the output power of the PA can be controlled by switching the sizes of transistors. Seven different level of output power can be obtained through a three- bit control code. The tested results shows that the proposed PA achieves power added efficiency (PAE of 26.73% while delivering an output power of 6.35dBm at 1dB compression point. Its power gain is 15.87dB. With a low DC voltage supply of 1V, its power consumption is 15.3mW. The PA die size is 1070×610μm2.

  5. A fully integrated 3.5 GHz CMOS differential power amplifier driver

    Science.gov (United States)

    Xiaodong, Xu; Haigang, Yang; Tongqiang, Gao; Hongfeng, Zhang

    2013-07-01

    A fully integrated CMOS differential power amplifier driver (PAD) is proposed for WiMAX applications. In order to fulfill the differential application requirements, a transmission line transformer is used as the output matching network. A differential inductance constitutes an inter-stage matching network. Meanwhile, an on chip balun realizes input matching as well as single-end to differential conversion. The PAD is fabricated in a 0.13 μm RFCMOS process. The chip size is 1.1 × 1.1 mm2 with all of the matching network integrated on chip. The saturated power is around 10 dBm and power gain is about 12 dB.

  6. A Low-Power 9-bit Pipelined CMOS ADC with Amplifier and Comparator Sharing Technique

    CERN Document Server

    Bocharov, Yuri; Osipov, Dmitry

    2012-01-01

    This paper describes a pipelined analog-to-digital converter (ADC) employing a power and area efficient architecture. The adjacent stages of a pipeline share operational amplifiers. In order to keep accuracy of the amplifiers in the first stages, they use a partially sharing technique. The feature of the proposed scheme is that it also shares the comparators. The capacitors of the first stages of a pipeline are scaled down along a pipeline for a further reducing the chip area and its power consumption. A 9-bit 20-MSamples/s ADC, intended for use in multi-channel mixed-signal chips, has been fabricated via Europractice in a 180-nm CMOS process from UMC. The prototype ADC shows a spurious-free dynamic range of 58.5 dB at a sample rate of 20 MSamples/s, when a 400 kHz input signal with a swing of 1 dB below full scale is applied. The effective number of bits is 8.0 at the same conditions. ADC occupies an active area of 0.4 mm2 and dissipates 8.6 mW at a 1.8 V supply.

  7. Self-amplified CMOS image sensor using a current-mode readout circuit

    Science.gov (United States)

    Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

    2014-05-01

    The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

  8. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  9. Wireless power transmission for biomedical implants: The role of near-zero threshold CMOS rectifiers.

    Science.gov (United States)

    Mohammadi, Ali; Redoute, Jean-Michel; Yuce, Mehmet R

    2015-01-01

    Biomedical implants require an electronic power conditioning circuitry to provide a stable electrical power supply. The efficiency of wireless power transmission is strongly dependent on the power conditioning circuitry specifically the rectifier. A cross-connected CMOS bridge rectifier is implemented to demonstrate the impact of thresholds of rectifiers on wireless power transfer. The performance of the proposed rectifier is experimentally compared with a conventional Schottky diode full wave rectifier over 9 cm distance of air and tissue medium between the transmitter and receiver. The output voltage generated by the CMOS rectifier across a 1 KΩ resistive load is around twice as much as the Schottky rectifier.

  10. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    Science.gov (United States)

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

  11. Enhancement in open-circuit voltage of implantable CMOS-compatible glucose fuel cell by improving the anodic catalyst

    Science.gov (United States)

    Niitsu, Kiichi; Ando, Takashi; Kobayashi, Atsuki; Nakazato, Kazuo

    2017-01-01

    This paper presents an implantable CMOS-compatible glucose fuel cell that generates an open-circuit voltage (OCV) of 880 mV. The developed fuel cell is solid-catalyst-based and manufactured from biocompatible materials; thus, it can be implanted to the human body. Additionally, since the cell can be manufactured using a semiconductor (CMOS) fabrication process, it can also be manufactured together with CMOS circuits on a single silicon wafer. In the literature, an implantable CMOS-compatible glucose fuel cell has been reported. However, its OCV is 192 mV, which is insufficient for CMOS circuit operation. In this work, we have enhanced the performance of the fuel cell by improving the electrocatalytic ability of the anode. The prototype with the newly proposed Pt/carbon nanotube (CNT) anode structure successfully achieved an OCV of 880 mV, which is the highest ever reported.

  12. Optimization of Cmos 0.18 µM Low Noise Amplifier Using Nsga-Ii for UWB Applications

    OpenAIRE

    2014-01-01

    A design and optimization of 3-5 GHz single ended R adio Frequency (RF) Low Noise Amplifier (LNA) for ultra-wide-band (UWB) applications using standard U MC 0.18 μ m CMOS technology is reported. Designing of RF circuit components is a challenging job, since even after performing lengthy calculati ons and finding parameter values it is less guarantee t hat the design performs as expected. In view of thi s the optimization tool; Elitist Non-Domin...

  13. CMOS low noise amplifiers for 1.575 GHz GPS applications

    Directory of Open Access Journals (Sweden)

    M. Isikhan

    2009-05-01

    Full Text Available This paper presents Low Noise Amplifier (LNA versions designed for 1.575 GHz L1 Band Global Positioning System (GPS applications. A 0.35 μm standard CMOS process is used for implementation of these design versions. Different versions are designed to compare the results, analyze some effects and optimize some critical performance criteria. On-chip inductors with different quality factors and a slight topology change are utilized to achieve this variety. It is proven through both on-wafer and on-PCB measurements that the LNA versions operate at a supply voltage range varying from 2.1 V to 3.6 V drawing a current of 10 mA and achieve a gain of 13 dB to 17 dB with a Noise Figure (NF of 1.5 dB. Input referred 1 dB compression point (ICP is measured as −5.5 dBm and −10 dBm for different versions.

  14. An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

    Institute of Scientific and Technical Information of China (English)

    Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

    2009-01-01

    One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a twostage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 X 200 μm2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

  15. A 180-Vpp Integrated Linear Amplifier for Ultrasonic Imaging Applications in a High-Voltage CMOS SOI Technology.

    Science.gov (United States)

    Sun, Kexu; Gao, Zheng; Gui, Ping; Wang, Rui; Oguzman, Ismail; Xu, Xiaochen; Vasanth, Karthik; Zhou, Qifa; Shung, K Kirk

    2015-02-01

    This brief presents a monolithically integrated fully differential linear HV amplifier as the driver of an ultrasonic transducer. The linear amplifier is capable of transmitting HV arbitrary signals with a very low harmonic distortion, which is suitable for tissue harmonic imaging and other ultrasonic modes for enhanced imaging quality. The amplifier is designed and implemented using the 0.7-μm CMOS silicon-on-insulator process with 120-V devices. The amplifier, when driving a load of 300 pF in parallel with 100 Ω, is capable of transmitting a sine-wave signal with a frequency of up to 4.4 MHz, a maximum signal swing of 180 Vpp, and a second-order harmonic distortion (HD2) of -56 dBc but only dissipating an average power of 62 mW with a 0.1% duty cycle.

  16. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Science.gov (United States)

    Liang, Z.; Affolder, A.; Arndt, K.; Bates, R.; Benoit, M.; Di Bello, F.; Blue, A.; Bortoletto, D.; Buckland, M.; Buttar, C.; Caragiulo, P.; Das, D.; Dopke, J.; Dragone, A.; Ehrler, F.; Fadeyev, V.; Galloway, Z.; Grabas, H.; Gregor, I. M.; Grenier, P.; Grillo, A.; Hoeferkamp, M.; Hommels, L. B. A.; Huffman, B. T.; John, J.; Kanisauskas, K.; Kenney, C.; Kramberger, J.; Mandić, I.; Maneuski, D.; Martinez-Mckinney, F.; McMahon, S.; Meng, L.; Mikuž, M.; Muenstermann, D.; Nickerson, R.; Peric, I.; Phillips, P.; Plackett, R.; Rubbo, F.; Segal, J.; Seidel, S.; Seiden, A.; Shipsey, I.; Song, W.; Stanitzki, M.; Su, D.; Tamma, C.; Turchetta, R.; Vigani, L.; Volk, J.; Wang, R.; Warren, M.; Wilson, F.; Worm, S.; Xiu, Q.; Zhang, J.; Zhu, H.

    2016-09-01

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  17. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

    2016-09-21

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  18. Flexible multi-electrode array with integrated bendable CMOS-chip for implantable systems.

    Science.gov (United States)

    Winkin, N; Mokwa, W

    2012-01-01

    Micro-electrodes and micro-electrode arrays (MEAs) for stimulating neurons or recording action potentials are widely used in medical applications or biological research. For medical implants in many applications like brain implants or retinal implants there is a need for flexible MEAs with a large area and a large number of stimulation electrodes. In this work a flexible MEA with an embedded flexible silicon dummy CMOS-chip facing these challenges has been designed, manufactured and characterized. This approach offers the possibility by connecting and addressing several of these MEAs via a bus system, to increase the number and the density of electrodes significantly. This paper describes the design and fabrication process. Results on the mechanical and electrical behavior will be given and possible improvements for medical applications by this novel approach will be discussed.

  19. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    Science.gov (United States)

    Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

    2015-10-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

  20. SEMICONDUCTOR INTEGRATED CIRCUITS A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    Science.gov (United States)

    Kefeng, Han; Shengguo, Cao; Xi, Tan; Na, Yan; Junyu, Wang; Zhangwen, Tang; Hao, Min

    2010-12-01

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 × 0.55 mm2. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader.

  1. Area-Efficient 60 GHz +18.9 dBm Power Amplifier with On-Chip Four-Way Parallel Power Combiner in 65-nm CMOS

    Science.gov (United States)

    Farahabadi, Payam Masoumi; Basaligheh, Ali; Saffari, Parvaneh; Moez, Kambiz

    2017-02-01

    This paper presents a compact 60-GHz power amplifier utilizing a four-way on-chip parallel power combiner and splitter. The proposed topology provides the capability of combining the output power of four individual power amplifier cores in a compact die area. Each power amplifier core consists of a three-stage common-source amplifier with transformer-coupled impedance matching networks. Fabricated in 65-nm CMOS process, the measured gain of the 0.19-mm2 power amplifier at 60 GHz is 18.8 and 15 dB utilizing 1.4 and 1.0 V supply. Three-decibel band width of 4 GHz and P1dB of 16.9 dBm is measured while consuming 424 mW from a 1.4-V supply. A maximum saturated output power of 18.3 dBm is measured with the 15.9% peak power added efficiency at 60 GHz. The measured insertion loss is 1.9 dB at 60 GHz. The proposed power amplifier achieves the highest power density (power/area) compared to the reported 60-GHz CMOS power amplifiers in 65 nm or older CMOS technologies.

  2. Simulations of a typical CMOS amplifier circuit using the Monte Carlo method

    OpenAIRE

    Borges, Jacques Cousteau da Silva

    2016-01-01

    In the present paper of Microelectronics, some simulations of a typical circuit of amplification, using a CMOS transistor, through the computational tools were performed. At that time, PSPICE® was used, where it was possible to observe the results, which are detailed in this work. The imperfections of the component due to manufacturing processes were obtained from simulations using the Monte Carlo method. The circuit operating point, mean and standard deviation were obtained and the influence...

  3. Concentric Parallel Combining Balun for Millimeter-Wave Power Amplifier in Low-Power CMOS with High-Power Density

    Science.gov (United States)

    Han, Jiang-An; Kong, Zhi-Hui; Ma, Kaixue; Yeo, Kiat Seng; Lim, Wei Meng

    2016-11-01

    This paper presents a novel balun for a millimeter-wave power amplifier (PA) design to achieve high-power density in a 65-nm low-power (LP) CMOS process. By using a concentric winding technique, the proposed parallel combining balun with compact size accomplishes power combining and unbalance-balance conversion concurrently. For calculating its power combination efficiency in the condition of various amplitude and phase wave components, a method basing on S-parameters is derived. Based on the proposed parallel combining balun, a fabricated 60-GHz industrial, scientific, and medical (ISM) band PA with single-ended I/O achieves an 18.9-dB gain and an 8.8-dBm output power at 1-dB compression and 14.3-dBm saturated output power ( P sat) at 62 GHz. This PA occupying only a 0.10-mm2 core area has demonstrated a high-power density of 269.15 mW/mm2 in 65 nm LP CMOS.

  4. UHF power amplifier design in 0.35μm SiGe BiCMOS

    Institute of Scientific and Technical Information of China (English)

    Song Jiayou; Li Zhiqun; Wang Zhigon

    2009-01-01

    A two-stage power amplifier operated at 925 MHz was designed and fabricated in Jazz's 0.35μm SiGe BiCMOS process. It was fully integrated excluding the inductors and the output matching network. Under a single 3.3V supply voltage, the off-chip bonding test results indicated that the circuit has a small signal gain of more than 24dB, the input and output reflectance are less than -24dB and -10dB, respectively, and the maximal output power is 23.5 dBm. At output power of 23.1 dBm, the PAE (power added efficiency) is 30.2%, the IMD2 and IMD3 are less than -32 dBc and -46 dBc, respectively. The chip size is 1.27mm×0.9mm.

  5. Design and analysis of a UWB low-noise amplifier in the 0.18 μm CMOS process

    Institute of Scientific and Technical Information of China (English)

    Yang Yi; Gao Zhuo; Yang Liqiong; Huang Lingyi; Hu Weiwu

    2009-01-01

    An ultra-wideband (3.1-10.6 GHz) low-noise amplifier using the 0.18 μm CMOS process is presented. It employs a wideband filter for impedance matching. The current-reused technique is adopted to lower the power consumption. The noise contributions of the second-order and third-order Chebyshev fliers for input matching are analyzed and compared in detail. The measured power gain is 12.4-14.5 dB within the bandwidth. NF ranged from 4.2 to 5.4 dB in 3.1-10.6 GHz. Good input matching is achieved over the entire bandwidth. The test chip consumes 9 mW (without output buffer for measurement) with a 1.8 V power supply and occupies 0.88 mm2.

  6. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier

    Directory of Open Access Journals (Sweden)

    De Xing Lioe

    2016-04-01

    Full Text Available A complementary metal-oxide semiconductor (CMOS lock-in pixel to observe stimulated Raman scattering (SRS using a high speed lateral electric field modulator (LEFM for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF and switched-capacitor (SC integrator with a fully CMOS differential amplifier. AC (modulated components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  7. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

    Science.gov (United States)

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-04-13

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  8. Simulations of a typical CMOS amplifier circuit using the Monte Carlo method

    Directory of Open Access Journals (Sweden)

    Borges, Jacques Cousteau da Silva

    2016-11-01

    Full Text Available In the present paper of Microelectronics, some simulations of a typical circuit of amplification, using a CMOS transistor, through the computational tools were performed. At that time, PSPICE® was used, where it was possible to observe the results, which are detailed in this work. The imperfections of the component due to manufacturing processes were obtained from simulations using the Monte Carlo method. The circuit operating point, mean and standard deviation were obtained and the influence of the threshold voltage Vth was analyzed.

  9. Digital standard cells and operational amplifiers for operation up to 250 degrees C using low-cost CMOS technology

    Science.gov (United States)

    Stemmer, Jens; Ackermann, Joerg; Uffmann, Dirk; Aderhold, Jochen

    1996-09-01

    There is an increasing demand from automotive, aircraft and space industry for reliable high temperature resistant electronics. Circuits with reliable functionality up to temperatures of 250 degree(s)C would be sufficient for most of these applications. Digital standard cells and operational amplifiers are the basic building blocks of these circuits. Commercially available digital standard cell libraries and operational amplifiers are normally specified for operation up to a maximum temperature of 125 degree(s)C. Hence, the purpose of this work was the design and characterization of digital standard cells and operational amplifiers for operation up to 250 degree(s)C using a low-cost 1.0 micrometers epi-CMOS process. Several design measures were applied to the cells in order to further improve latch-up resistivity and to limit leakage currents, respectively. The transfer curves of all digital cells for all input signal combinations have been recorded in the temperature range from 30 to 250 degree(s)C. Significant results are very low temperature shifts of the noise margins and of the switching point, respectively. Furthermore, the low (0 V) and high (5 V) levels are reached exactly over the entire temperature range. Outstanding characteristics of the operational amplifier comprise low open-loop gain temperature drift as well as low offset and offset temperature drift, respectively. The open-loop gain was greater than 83 dB at room temperature with a drift of less than 0.02 dB/ degree(s)C. The offset voltage amounted to -1 mV at room temperature and 1 mV at 250 degree(s)C, respectively. The long-term behavior of these cells is currently under investigation.

  10. CMOS工艺射频功率放大器的实现与验证%Realization and verification of the CMOS technology RF power amplifier

    Institute of Scientific and Technical Information of China (English)

    谢君

    2011-01-01

    RF power amplifiers are key components in wireless devices, CaAs technology is widely used in the design and manufacture of RF power amplifier. But the CMOS technology has the very big superiority in the production maturity and the cost, this paper focuses on the problems that using CMOS technology to do the RF power amplifier, introduces the world's first mass product CMOS power amplifier and the special techniques used. Using a mature handset product, it replaces this power amplifier and the peripheral components, and finally carries on the contrast test with the original product.%射频功率放大器是无线设备的关键器件,GaAs工艺被广泛使用在射频功放的设计制造上.而CMOS工艺在生产成熟度和成本上有很大优势,主要关注用CMOS工艺来做射频功放的问题,介绍世界上第一颗量产的CMOS功放及其所使用的特殊技术.利用一款成熟的手机产品,替换这颗功放及外围器件,最后与原产品进行对比测试.

  11. CMOS 60-GHz and E-band power amplifiers and transmitters

    CERN Document Server

    Zhao, Dixian

    2015-01-01

    This book focuses on the development of design techniques and methodologies for 60-GHz and E-band power amplifiers and transmitters at device, circuit and layout levels. The authors show the recent development of millimeter-wave design techniques, especially of power amplifiers and transmitters, and presents novel design concepts, such as “power transistor layout” and “4-way parallel-series power combiner”, that can enhance the output power and efficiency of power amplifiers in a compact silicon area. Five state-of-the-art 60-GHz and E-band designs with measured results are demonstrated to prove the effectiveness of the design concepts and hands-on methodologies presented. This book serves as a valuable reference for circuit designers to develop millimeter-wave building blocks for future 5G applications.

  12. CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

    Institute of Scientific and Technical Information of China (English)

    Wu Zhaohui; Zhang Xu; Liang Zhiming; Li Bin

    2012-01-01

    A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW.The test results show that it can work correctly.

  13. CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

    Science.gov (United States)

    Zhaohui, Wu; Xu, Zhang; Zhiming, Liang; Bin, Li

    2012-05-01

    A new BPSK demodulator was presented. By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator, the circuit structure of the demodulator became simpler and hence its power consumption became lower. Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system. The proposed BPSK demodulator was implemented by Global Foundries 0.35 μm CMOS technology with a 3.3 V power supply. The designed chip area is only 0.07 mm2 and the power consumption is 0.5 mW. The test results show that it can work correctly.

  14. A current to voltage converter for cryogenics using a CMOS operational amplifier

    Science.gov (United States)

    Hayashi, K.; Saitoh, K.; Shibayama, Y.; Shirahama, K.

    2009-02-01

    We have constructed a versatile current to voltage (I-V) converter operating at liquid helium temperature, using a commercially available all-CMOS OPamp. It is valuable for cryogenic measurements of electrical current of nano-pico amperes, for example, in scanning probe microscopy. The I-V converter is thermally linked to liquid helium bath and self-heated up to 10.7 K. We have confirmed its capability of a transimpedance gain of 106 V/A and a bandwidth from DC to 200 kHz. In order to test the practical use for a frequency-modulation atomic force microscope, we have measured the resonance frequency shift of a quartz tuning fork at 32 kHz. In the operation of the I-V converter close to the sensor at liquid helium temperature, the signal-to-noise ratio has been improved to a factor of 13.6 compared to the operation at room temperature.

  15. Wide-band CMOS low-noise amplifier exploiting thermal-noise canceling

    NARCIS (Netherlands)

    Bruccoleri, Federico; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contra

  16. A current to voltage converter for cryogenics using a CMOS operational amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, K; Saitoh, K; Shibayama, Y; Shirahama, K [Department of Physics, Keio University, Yokohama 223-8522 (Japan)], E-mail: khayashi@a2.keio.jp

    2009-02-01

    We have constructed a versatile current to voltage (I-V) converter operating at liquid helium temperature, using a commercially available all-CMOS OPamp. It is valuable for cryogenic measurements of electrical current of nano-pico amperes, for example, in scanning probe microscopy. The I-V converter is thermally linked to liquid helium bath and self-heated up to 10.7 K. We have confirmed its capability of a transimpedance gain of 10{sup 6} V/A and a bandwidth from DC to 200 kHz. In order to test the practical use for a frequency-modulation atomic force microscope, we have measured the resonance frequency shift of a quartz tuning fork at 32 kHz. In the operation of the I-V converter close to the sensor at liquid helium temperature, the signal-to-noise ratio has been improved to a factor of 13.6 compared to the operation at room temperature.

  17. Dual-Polarized Antenna Arrays with CMOS Power Amplifiers for SiP Integration at W-Band

    Science.gov (United States)

    Giese, Malte; Vehring, Sönke; Böck, Georg; Jacob, Arne F.

    2017-08-01

    This paper presents requirements and front-end solutions for low-cost communication systems with data rates of 100 Gbit/s. Link budget analyses in different mass-market applications are conducted for that purpose. It proposes an implementation of the front-end as an active antenna array with support for beam steering and polarization multiplexing over the full W-band. The critical system components are investigated and presented. This applies to a transformer coupled power amplifier (PA) in 40 nm bulk CMOS. It shows saturated output power of more than 10 dBm and power-added-efficiency of more than 10 % over the full W-band. Furthermore, the performance of microstrip-to-waveguide transitions is shown exemplarily as an important part of the active antenna as it interfaces active circuitry and antenna in a polymer-and-metal process. The transition test design shows less than 0.9 dB insertion loss and more than 12 dB return loss for the differential transition over the full W-band.

  18. Current mirror reset for low-power BiCMOS charge amplifier

    CERN Document Server

    Sampietro, M; Fasoli, L

    2000-01-01

    We present a circuit solution to provide DC feedback and signal reset in charge amplifiers that overcomes the difficulty to integrate high value resistors in VLSI technology. The feedback resistor is substituted by a MOSFET current conveyor that re-direct to the input node the current already available at the output follower. The lower noise of this 'active resistor' with respect to a physical resistor of equal value makes possible a first shaping within the preamplifier. The circuit has been implemented for a fast shaping time system (20 ns peaking time) using a BJT as input transistor for best noise performance. The circuit has been powered with single supply as low as 1.6 V with a total power consumption down to 220 mu W/ch and has shown a measured noise of 660 electrons rms, in accordance with the theoretical expectation.

  19. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

    Energy Technology Data Exchange (ETDEWEB)

    Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

    2010-12-15

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  20. High-gain, high-bandwidth, rail-to-rail, constant-gm CMOS operational amplifier

    Science.gov (United States)

    Huang, Hong-Yi; Wang, Bo-Ruei

    2013-01-01

    This study presents a high-gain, high-bandwidth, constant-gm , rail-to-rail operational amplifier (op-amp). The constant transconductance is improved with a source-to-bulk bias control of an input pair. A source degeneration scheme is also adapted to the output stage for receiving wide input range without degradation of the gain. Additionally, several compensation schemes are employed to enhance the stability. A test chip is fabricated in a 0.18 µm complementary metal-oxide semiconductor process. The active area of the op-amp is 181 × 173 µm2 and it consumes a power of 2.41 mW at a supply voltage of 1.8 V. The op-amp achieves a dc gain of 94.3 dB and a bandwidth of 45 MHz when the output capacitive load is connected to an effective load of 42.5 pF. A class-AB output stage combining a slew rate (SR) boost circuit provides a sinking current of 6 mA and an SR of 17 V/µs.

  1. A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

    Science.gov (United States)

    Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

    2017-02-01

    This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

  2. Influence of ion-implanted profiles on the performance of GaAs MESFET's and MMIC amplifiers

    Energy Technology Data Exchange (ETDEWEB)

    Pavlidis, D.; Cazaux, J.L.; Graffeuil, J.

    1988-04-01

    The RF small-signal performance of GaAs MESFET's and MMIC amplifiers as a function of various ion-implanted profiles is theoretically and experimentally investigated. Implantation energy, dose, and recess depth influence are theoretically analyzed with the help of a specially developed device simulator. The performance of MMIC amplifiers processed with various energies, doses, recess depths, and bias conditions is discussed and compared to experimental characteristics. Some criteria are finally proposed for the choice of implantation conditions and process in order to optimize the characteristics of ion-implanted FET's and to realize process-tolerant MMIC amplifiers.

  3. A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

    Science.gov (United States)

    Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

    2013-04-01

    In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

  4. Optimization of the close-to-carrier Phase Noise in a CMOS-MEMS oscillator using a Phase Tunable Sustaining-Amplifier.

    Science.gov (United States)

    Sobreviela, Guillermo; Riverola, Martin; Canals, Francesc; Del Monte, Arantxa; Beumala, Nuria

    2017-02-13

    In this paper, the phase noise of a 24-MHz CMOSMEMS oscillator with zero-level vacuum package is studied. We characterize and analyze the nonlinear regime of each one of the modules that compose the oscillator (CMOS sustaining-amplifier and MEMS resonator). As we show, the presented resonator exhibits a high nonlinear behavior. Such fact is exploited as a mechanism to stabilize the oscillation amplitude, allowing to maintain the sustaining-amplifier working in the linear regime. Consequently, the nonlinear resonator becomes the main closeto- carrier phase noise source. The sustaining amplifier, which functions as a phase shifter, was developed such that MEMS operation point optimization could be achieved without an increase in circuitry modules. Therefore, the system saves on area and power, and is able to improve the phase noise 26 dBc/Hz (@1 kHz carrier frequency offset).

  5. Real-time, continuous, fluorescence sensing in a freely-moving subject with an implanted hybrid VCSEL/CMOS biosensor

    Science.gov (United States)

    O’Sullivan, Thomas D.; Heitz, Roxana T.; Parashurama, Natesh; Barkin, David B.; Wooley, Bruce A.; Gambhir, Sanjiv S.; Harris, James S.; Levi, Ofer

    2013-01-01

    Performance improvements in instrumentation for optical imaging have contributed greatly to molecular imaging in living subjects. In order to advance molecular imaging in freely moving, untethered subjects, we designed a miniature vertical-cavity surface-emitting laser (VCSEL)-based biosensor measuring 1cm3 and weighing 0.7g that accurately detects both fluorophore and tumor-targeted molecular probes in small animals. We integrated a critical enabling component, a complementary metal-oxide semiconductor (CMOS) read-out integrated circuit, which digitized the fluorescence signal to achieve autofluorescence-limited sensitivity. After surgical implantation of the lightweight sensor for two weeks, we obtained continuous and dynamic fluorophore measurements while the subject was un-anesthetized and mobile. The technology demonstrated here represents a critical step in the path toward untethered optical sensing using an integrated optoelectronic implant. PMID:24009996

  6. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  7. Characterization of a CMOS sensing core for ultra-miniature wireless implantable temperature sensors with application to cryomedicine.

    Science.gov (United States)

    Khairi, Ahmad; Thaokar, Chandrajit; Fedder, Gary; Paramesh, Jeyanandh; Rabin, Yoed

    2014-09-01

    In effort to improve thermal control in minimally invasive cryosurgery, the concept of a miniature, wireless, implantable sensing unit has been developed recently. The sensing unit integrates a wireless power delivery mechanism, wireless communication means, and a sensing core-the subject matter of the current study. The current study presents a CMOS ultra-miniature PTAT temperature sensing core and focuses on design principles, fabrication of a proof-of-concept, and characterization in a cryogenic environment. For this purpose, a 100 μm × 400 μm sensing core prototype has been fabricated using a 130 nm CMOS process. The senor has shown to operate between -180°C and room temperature, to consume power of less than 1 μW, and to have an uncertainty range of 1.4°C and non-linearity of 1.1%. Results of this study suggest that the sensing core is ready to be integrated in the sensing unit, where system integration is the subject matter of a parallel effort.

  8. A 0.18 {mu}m CMOS dual-band low power low noise amplifier for a global navigation satellite system

    Energy Technology Data Exchange (ETDEWEB)

    Li Bing; Zhuang Yiqi; Li Zhenrong; Jin Gang, E-mail: waxmax@126.com [Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2010-12-15

    This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 {mu}m 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver. (semiconductor integrated circuits)

  9. A 0.4V, 790µW CMOS Low Noise Amplifier in the Sub-Threshold Region at 1.5GHz

    Directory of Open Access Journals (Sweden)

    Amin Zafarian

    2014-12-01

    Full Text Available A fully integrated low-noise amplifier (LNA with 0.4V supply voltage and ultra-low power consumption at 1.5GHz by folded cascode structure is presented. The proposed LNA is designed in a TSMC 0.18 µm CMOS technology, in which the all transistors are biased in sub-threshold region. Through the use of the proposed circuit for the gain enhancement in this structure and using forward body bias technique, a very high figure of merit is achieved, in comparison to the similar structures. The LNA provides a power gain of 14.7bB with a noise figure of 2.9dB while consuming only 790µW dc power. Also, the impedance matching of the input and output circuit in its operating frequency is desirable and in the whole circuit bandwidth, input and output isolation is below -33dB.

  10. SEMICONDUCTOR INTEGRATED CIRCUITS A 0.18 μm CMOS dual-band low power low noise amplifier for a global navigation satellite system

    Science.gov (United States)

    Bing, Li; Yiqi, Zhuang; Zhenrong, Li; Gang, Jin

    2010-12-01

    This paper presents a dual-band low noise amplifier for the receiver of a global navigation satellite system. The differences between single band and multi-band design methods are discussed. The relevant parameter analysis and the details of circuit design are presented. The test chip was implemented in a TSMC 0.18 μm 1P4M RF CMOS process. The LNA achieves a gain of 16.8 dB/18.9 dB on 1.27 GHz/1.575 GHz. The measured noise figure is around 1.5-1.7 dB on both bands. The LNA consumes less than 4.3 mA of current from a 1.8 V power supply. The measurement results show consistency with the design. And the LNA can fully satisfy the demands of the GNSS receiver.

  11. An implantable CMOS signal conditioning system for recording nerve signals with cuff electrodes

    DEFF Research Database (Denmark)

    Papathanasiou, Konstantinos; Lehmann, Torsten

    2000-01-01

    We propose a system architecture for recording nerve signals with cuff electrodes and develop the key component in this system, the small-input, low-noise, low-power, high-gain amplifier. The amplifier is implemented using a mixture of weak- and strong-inversion transistors and a special off...

  12. Design of a 0.5 V CMOS cascode low noise amplifier for multi-gigahertz applications

    Institute of Scientific and Technical Information of China (English)

    Liu Baohong; Zhou Jianjun; Mao Junfa

    2012-01-01

    This paper presents the design of 0.5 V multi-gigahertz cascode CMOS LNA for low power wireless communication.By splitting the direct current through conventional cascode topology,the constraint of stackingMOS structure for supply voltage has been removed and based on forward-body-bias technology,the circuit can operate at 0.5 V supply voltage.Design details and RF characteristics have been investigated in this paper.To verify the investigation,a 0.5 V 5.4 GHz LNA has been fabricated through 0.18μm CMOS technology and measured.Measured results show that it obtains 9.1 dB gain,3 dB NF with 0.5 V voltage and 2.5 mW power dissipation.The measured (II)P3 is -3.5 dBm.Compared with previously published cascode LNA,it achieves the lowest supply voltage and lowest power dissipation with competitive RF performances.

  13. Proximity gettering of C3H5 carbon cluster ion-implanted silicon wafers for CMOS image sensors: Gettering effects of transition metal, oxygen, and hydrogen impurities

    Science.gov (United States)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko

    2016-12-01

    A new technique is described for manufacturing silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication. It is demonstrated that this technique can implant wafers simultaneously with carbon and hydrogen elements that form the projection range by using hydrocarbon compounds. Furthermore, these wafers can getter oxygen impurities out-diffused from the silicon substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as dark current and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly reduce dark current in advanced CMOS image sensors.

  14. Analysis and Compensation of the AM-AM and AM-PM Distortion for CMOS Cascode Class-E Power Amplifier

    Directory of Open Access Journals (Sweden)

    Wen An Tsou

    2009-01-01

    Full Text Available Analysis and compensation methodology of the AM-AM and AM-PM distortion of cascode class-E power amplifiers are presented. A physical-based model is proposed to illustrate that the nonlinear capacitance and transconductance cause the AM-AM and AM-PM distortion when modulating the supply voltage of the PA. A novel methodology that can reduce the distortion is also proposed. By degenerating common-gate transistor into a resistor, the constant equivalent impedance is obtained so that the AM-AM and AM-PM distortion is compensated. An experimental prototype of 2.6 GHz cascode class-E power amplifier with the AM-AM and AM-PM compensation has been integrated in a 0.18 μm CMOS technology, occupies a total die area of 1.6 mm2. It achieves a drain efficiency of 17.8% and a power-added efficiency of 16.6% while delivering 12 dBm of linear output power and drawing 31 mA from a 1.8 V supply. Finally, a co-simulation result demonstrated that, when the distortion of the PA has been compensated, the EVM is improved from −17 dB to −19 dB with an IEEE802.11a-like signal source.

  15. Pain Control on Demand Based on Pulsed Radio-Frequency Stimulation of the Dorsal Root Ganglion Using a Batteryless Implantable CMOS SoC.

    Science.gov (United States)

    Hung-Wei Chiu; Mu-Lien Lin; Chii-Wann Lin; I-Hsiu Ho; Wei-Tso Lin; Po-Hsiang Fang; Yi-Chin Lee; Yeong-Ray Wen; Shey-Shi Lu

    2010-12-01

    This paper presents the implementation of a batteryless CMOS SoC with low voltage pulsed radio-frequency (PRF) stimulation. This implantable SoC uses 402 MHz command signals following the medical implanted communication system (MICS) standard and a low frequency (1 MHz) for RF power transmission. A body floating type rectifier achieves 84% voltage conversion ratio. A bi-phasic pulse train of 1.4 V and 500 kHz is delivered by a PRF driver circuit. The PRF parameters include pulse duration, pulse frequency and repetition rate, which are controllable via 402 MHz RF receiver. The minimal required 3 V RF Vin and 2.2 V VDDr is achieved at 18 mm gap. The SoC chip is fabricated in a 0.35 μm CMOS process and mounted on a PCB with a flexible spiral antenna. The packaged PRF SoC was implanted into rats for the animal study. Von Frey was applied to test the mechanical allodynia in a blinded manner. This work has successfully demonstrated that implanted CMOS SoC stimulating DRG with 1.4 V, 500 kHz PRF could significantly reduce spinal nerve ligation (SNL) induced mechanical allodynia for 3-7 days.

  16. BiCMOS operational amplifier with precise and stable dc gain for high-frequency switched capacitor circuits

    Science.gov (United States)

    Baschirotto, A.; Alini, R.; Castello, R.

    1991-07-01

    A novel approach in the design of high-frequency switched capacitor (SC) circuits is presented. It is based on the use of simple and fast amplifiers with low but precisely controlled gain value. The effect of the precisely known and stable opamp gain is compensated for by changing the capacitor values during the synthesis of the SC cell. An example of an opamp with these features and the synthesis of a biquadratic filter based on this approach are given.

  17. A 300-mV ΔΣ Modulator Using a Gain-Enhanced, Inverter-Based Amplifier for Medical Implant Devices

    Directory of Open Access Journals (Sweden)

    Ali Fazli Yeknami

    2016-03-01

    Full Text Available An ultra-low-voltage low-power switched-capacitor (SC delta-sigma (ΔΣ modulator running at a supply voltage as low as 300 mV is presented for biomedical implant devices, e.g., cardiac pacemakers. To reduce the supply voltage, an inverter-based amplifier is used in the integrators, whose DC gain and gain-bandwidth (GBW are boosted by a simple current-mirror output stage. The full input-feedforward loop topology offers low integrators internal swing, supporting ultra-low-voltage operation. To demonstrate the concept, a second-order loop topology was chosen. The entire modulator operates reliably against process, voltage and temperature (PVT variations from a 300 mV ± 10% supply voltage only, while the switches are driven by a charge pump clock boosting scheme. Designed in a 65 nm CMOS technology and clocked at 256 kHz, the simulation results show that the modulator can achieve a 64.4 dB signal-to-noise ratio (SNR and a 60.7 dB signal-to-noise and distortion ratio (SNDR over a 1.0 kHz signal bandwidth while consuming 0.85 μW of power.

  18. A novel design of ultra-broadband, high-gain and high-linearity variable gain distributed amplifier in 0.13 μm CMOS technology

    Science.gov (United States)

    Baharvand, Zainab; Hakimi, Ahmad; Rashedi, Esmat

    2016-12-01

    A high-gain, high-linearity and ultra-broadband variable gain distributed amplifier (VGDA) based on employing multiple techniques is presented to substantially increase the gain. The complete design is composed of two major parts including a VGDA part followed by a single stage distributed amplifier (SSDA) part. The VGDA part makes it possible to achieve different gain settings. For high gain considerations, the SSDA part cascades with the VGDA part that takes the benefits of the multiplicative gain mechanism. A theory is presented to enhance the linearity without imposing further DC power consumption. This idea has been validated by simulation results as expected. The design is analysed and simulated in the standard 0.13 μm CMOS technology. It presents the large gain tuning range of 35 dB, from -5 dB attenuation gain up to +30 dB maximum amplification gain, in relation to the control voltage (Vctr) that varies between 0.42 and 1.1 V. At the maximum amplification gain setting, it presents a DC up to 16 GHz 3 dB bandwidth, an average noise figure of 3.2 dB and an IIP3 of -2 dB m. Furthermore, it dissipates 46.42 mW from 0.7 and 0.9 V power supplies of the drain lines of VGDA and SSDA parts, respectively. Additionally, the Monte Carlo (MC) simulation has been performed to predict an estimate of the accuracy of performance of the proposed design under various conditions.

  19. CMOS temperature sensor using a resistively degenerated common-source amplifier biased by an adjustable proportional-to-absolute-temperature voltage

    Science.gov (United States)

    Wang, Ruey-Lue; Fu, Chien-Cheng; Yu, Chi; Hao, Yi-Fan; Shi, Jian-Liang; Lin, Chen-Fu; Liao, Hsin-Hao; Tsai, Hann-Huei; Juang, Ying-Zong

    2014-01-01

    A high-linearity CMOS temperature sensor with pulse output is presented. The temperature core is a resistively degenerated common-source amplifier which gate is biased by a proportional-to-absolute-temperature (PTAT) voltage generator. The source resistor is made of polysilicon which resistance has a PTAT characteristic. The current flowing through the resistor exhibits a PTAT characteristic with high linearity of 99.99% at least for a temperature range from 0 to 125 °C. The PTAT voltage generator can be adjusted by a bias voltage Vb and hence the PTAT current can also be adjusted by the Vb. The PTAT current is mirrored to an added current controlled oscillator which output pulse frequencies also exhibit a PTAT characteristic. For the chip using the 0.35 µm process, the plots of measured pulse frequencies against temperature exhibit the sensitivity of 2.30 to 2.24 kHz/°C with linearity of more than 99.99% at the Vb of 1 to 1.2 V.

  20. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

    Science.gov (United States)

    Zhixiong, Ren; Kefeng, Zhang; Lanqi, Liu; Cong, Li; Xiaofei, Chen; Dongsheng, Liu; Zhenglin, Liu; Xuecheng, Zou

    2015-09-01

    Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE. Project supported by the National Natural Science Foundation of China (No. 61076030).

  1. 一款低噪声CMOS运算放大器的改进与设计%Improvement and Design of the Low-Noise CMOS Operational Amplifier

    Institute of Scientific and Technical Information of China (English)

    郭虎

    2012-01-01

    采用台积电(TSMC)0.1gum标准RFCMOS工艺进行仿真验证;改进了器件的噪声模型,给出了在功耗和阻抗匹配条件下噪声性能优化的设计方法。在遵守模拟电路设计的八边形法则的基础上,对参数进行折衷考虑(trade—o国和整体优化处理。仿真结果表明,此运算放大器的各项主要参数均满足预期要求,性能优异。%This paper completes the simulation verification using RF CMOS process of Taiwan Semiconductor Manufacturing (TSMC) 0.18 um standard. It improves the device noise model, proposes the design method of noise performance optimization under the power consumption and impedance matching condition. Abiding by the octagon rule of analog circuit design, all the parameters are made a compromise and optimized. The simulation results show that the key parameters of the operational amplifier meet the expected requirement, and the performance is excellent.

  2. 一种应用匹配技术的CMOS放大器版图设计%A CMOS Amplifier Layout Design Based on Matching Technology

    Institute of Scientific and Technical Information of China (English)

    李亮

    2012-01-01

    模拟集成电路的精度和性能通常取决于元件匹配精度,匹配度直接影响了最终电路的性能,而匹配精度是靠制造工艺和版图来保证的.在分析CMOS模拟版图设计匹配机理和研究常用匹配手段的基础上,深入探讨MOS管叉指结构的共质心版图设计方法,设计一个基本放大器版图,给出详细的放大器输入差分对管和电流镜匹配版图.%The accuracy and performance of analog integrated circuits often depends on the accuracy of component matching. Matching accuracy is guaranteed by the manufacturing process and layout design, which directly affect the performance of the final circuit. Based on analysis of CMOS analog layout design matching mechanism and study of common matching methods in paper, design methods is deeply discussed on the MOS transistor's common-centroid layout of interdigitated structure, a basic amplifier layout is designed, and the detailed matching of input differential transistors and the current mirror are designed.

  3. A 10 dBm-25 dBm, 0.363 mm2 Two Stage 130 nm RF CMOS Power Amplifier

    Directory of Open Access Journals (Sweden)

    Shridhar R. Sahu

    2013-10-01

    Full Text Available This paper proposes a 2.4 GHz RF CMOS Power amplifier and variation in its main performance parameters i.e, output power, S-parameters and power added efficiency with respect to change in supply voltage and size of the power stage transistor. The supply voltage was varied form 1 V to 5 V and the range of output power at 1dB compression point was found to be from 10.684 dBm to 25.08 dBm respectively. The range of PAE is 16.65 % to 48.46 %. The width of the power stage transistor was varied from 150 µm to 500 µm to achieve output power of range 15.47 dBm to 20.338 dBm. The range of PAE obtained here is 29.085 % to 45.439 %. The total dimension of the layout comes out to be 0.714 * 0.508 mm2 .

  4. A 0.8V, 7μA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18μm CMOS

    DEFF Research Database (Denmark)

    Citakovic, J; Nielsen, I. Riis; Nielsen, Jannik Hammel

    2005-01-01

    A two-stage amplifier, operational at 0.8V and drawing 7μA, has been integrated in a standard digital 0.18μm CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with gm control. The efficient rail-to-rail output stage is biased in class AB. The measured...... DC gain of the amplifier is 75dB, and the unity-gain frequency is 870kHz with a 12pF, 100kΩload. Both input and output stage transistors are biased in weak inversion....

  5. 基于0.5μm CMOS工艺的一款新型BiCMOS集成运算放大器设计%Design of New BiCMOS Integrated Operational Amplifier Based on 0.5 μm CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    赵俊霞; 陆雅明

    2011-01-01

    为了提高运算放大器的驱动能力,依据现有CMOS集成电路生产线,介绍一款新型BiCMOS集成运算放大电路设计,探讨BiCMOS工艺的特点.在S-Edit中进行"BiCMOS运放设计"电路设计,并对其电路各个器件参数进行调整,包括MOS器件的宽长比和电容电阻的值.完成电路设计后,在T-spice中进行电路的瞬态仿真,插入CMOS,PNP和NPN的工艺库,对电路所需的电源电压和输入信号幅度和频率进行设定调整,最终在W-Edit输出波形图.在MCNC 0.5μm工艺平台上完成由MOS、双极型晶体管和电容构成的运算放大器版图设计.根据设计的版图,设计出BiCMOS相应的工艺流程,并提取各光刻工艺的掩模版.%In order to improve the drive capability of operational amplifier, a new circuit of BiCMOS integrated operational amplifier is designed on the basis of available CMOS integrated circuit production line.The technique characteristics of BiCMOS is discussed.The BiCMOS operational amplifier is designed in S-Edit.The parameters of various devices in the circuit is adjusted, including width to length ratio of MOS device and capacitance values of resistors.After the circuit design, the transient simulation is performed in T-spice, and the CMOS, PNP and NPN bipolar technology library are used to set the supply voltage, the amplitude and frequency of the input signal, and then send out the final waveform diagram in W-Edit.The layout design of the operational amplifier composed of MOS, bipolar transistors and capacitors on the MCNC 0.5 μm IC Process Line is completed.According to the designed layout, the corresponding BiCMOS process flows are designed, and the masks of lithography process are extracted.

  6. Functional brain fluorescence plurimetry in rat by implantable concatenated CMOS imaging system.

    Science.gov (United States)

    Kobayashi, Takuma; Masuda, Hiroyuki; Kitsumoto, Chikara; Haruta, Makito; Motoyama, Mayumi; Ohta, Yasumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Shiosaka, Sadao; Ohta, Jun

    2014-03-15

    Measurement of brain activity in multiple areas simultaneously by minimally invasive methods contributes to the study of neuroscience and development of brain machine interfaces. However, this requires compact wearable instruments that do not inhibit natural movements. Application of optical potentiometry with voltage-sensitive fluorescent dye using an implantable image sensor is also useful. However, the increasing number of leads required for the multiple wired sensors to measure larger domains inhibits natural behavior. For imaging broad areas by numerous sensors without excessive wiring, a web-like sensor that can wrap the brain was developed. Kaleidoscopic potentiometry is possible using the imaging system with concatenated sensors by changing the alignment of the sensors. This paper describes organization of the system, evaluation of the system by a fluorescence imaging, and finally, functional brain fluorescence plurimetry by the sensor. The recorded data in rat somatosensory cortex using the developed multiple-area imaging system compared well with electrophysiology results.

  7. CAOS-CMOS camera.

    Science.gov (United States)

    Riza, Nabeel A; La Torre, Juan Pablo; Amin, M Junaid

    2016-06-13

    Proposed and experimentally demonstrated is the CAOS-CMOS camera design that combines the coded access optical sensor (CAOS) imager platform with the CMOS multi-pixel optical sensor. The unique CAOS-CMOS camera engages the classic CMOS sensor light staring mode with the time-frequency-space agile pixel CAOS imager mode within one programmable optical unit to realize a high dynamic range imager for extreme light contrast conditions. The experimentally demonstrated CAOS-CMOS camera is built using a digital micromirror device, a silicon point-photo-detector with a variable gain amplifier, and a silicon CMOS sensor with a maximum rated 51.3 dB dynamic range. White light imaging of three different brightness simultaneously viewed targets, that is not possible by the CMOS sensor, is achieved by the CAOS-CMOS camera demonstrating an 82.06 dB dynamic range. Applications for the camera include industrial machine vision, welding, laser analysis, automotive, night vision, surveillance and multispectral military systems.

  8. Low Noise Amplifier for 2.45 GHz Frequency Band at 0.18 μm CMOS Technology for IEEE Standard 802.11 b/g WLAN

    Directory of Open Access Journals (Sweden)

    Viranjay M. Srivastava

    2012-08-01

    Full Text Available This paper presents the design of low noise amplifier (LNA at 2.45 GHz and integrated at 0.18 µm RF CMOS process technology. This type of LNA at 2.45 GHz is use in the Bluetooth receiver. The proposed method is useful to optimize noise performance and power gain while maintaining good input and output matching. The amplifier is designed to be used as first stage of a receiver for wireless communication. The main aim of designer is to achieve low noise figure with improved gain with the help of CMOS technology by using single stage n-MOS amplifier. The simulation results show a forward gain of 14.0 dB, a noise-figure of 0.5 dB and stability factor is approximate unity, in which the circuit operates at 14.2 mA drain current with supply voltage of 3.5 V and biasing voltage of 1.5 V.

  9. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  10. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  11. Pushing the limits of CMOS optical parametric amplifiers with USRN:Si7N3 above the two-photon absorption edge

    Science.gov (United States)

    Ooi, K. J. A.; Ng, D. K. T.; Wang, T.; Chee, A. K. L.; Ng, S. K.; Wang, Q.; Ang, L. K.; Agarwal, A. M.; Kimerling, L. C.; Tan, D. T. H.

    2017-01-01

    CMOS platforms operating at the telecommunications wavelength either reside within the highly dissipative two-photon regime in silicon-based optical devices, or possess small nonlinearities. Bandgap engineering of non-stoichiometric silicon nitride using state-of-the-art fabrication techniques has led to our development of USRN (ultra-silicon-rich nitride) in the form of Si7N3, that possesses a high Kerr nonlinearity (2.8 × 10−13 cm2 W−1), an order of magnitude larger than that in stoichiometric silicon nitride. Here we experimentally demonstrate high-gain optical parametric amplification using USRN, which is compositionally tailored such that the 1,550 nm wavelength resides above the two-photon absorption edge, while still possessing large nonlinearities. Optical parametric gain of 42.5 dB, as well as cascaded four-wave mixing with gain down to the third idler is observed and attributed to the high photon efficiency achieved through operating above the two-photon absorption edge, representing one of the largest optical parametric gains to date on a CMOS platform. PMID:28051064

  12. Based on the EWB 0.6μm CMOS Operational Amplifier Design%基于EWB 0.6μm CMOS运放设计

    Institute of Scientific and Technical Information of China (English)

    陈添兰

    2013-01-01

    根据运放的结构原理及理论指标要求设计一个基于0.6μm CMOS运算放大器.并采用EWB仿真软件仿真运放的各主要指标.指标包括运放的静/动态仿真分析、共/差模抑制比仿真分析.最后参考设计指标要求将仿真结果与理论计算结果相比对,设计出稳定的运放电路.%according to the structure principle and the theory of operational requirement design based on a 0.6μm CMOS opera?tional amplifier. And the use of EWB simulation software simulate OPAMP major indicators, indicators include the static / dy?namic simulation analysis, Co / differential mode rejection ratio. Finally,the reference design requirements the simulation results with the theoretical calculation results compared to design amplifier circuit.

  13. Nano CMOS

    Directory of Open Access Journals (Sweden)

    Malay Ranjan Tripathy

    2009-05-01

    Full Text Available Complementary metal-oxide-semiconductor (CMOS has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discussed in this article. The challenges and opportunities of nano CMOS technology are outlined here.

  14. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  15. Nano CMOS

    OpenAIRE

    2009-01-01

    Complementary metal-oxide-semiconductor (CMOS) has become major challenge to scaling and integration. However, innovation in transistor structures and integration of novel materials are needed to sustain this performance trend. CMOS variability in the scaling technology becoming very important concern because of limitation of process control over statistical variability related to the fundamental discreteness of charge and matter. Different aspects responsible for device variability are discu...

  16. ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

    Science.gov (United States)

    Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

    2001-01-01

    To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

  17. 一种带有增益提高技术的高速CMOS运算放大器设计%Design of a high speed CMOS operational amplifier with gain boosting technique

    Institute of Scientific and Technical Information of China (English)

    宋奇伟; 陆安江; 张正平

    2012-01-01

    设计了一种用于高速ADC中的高速高增益的全差分CMOS运算放大器。主运放采用带开关电容共模反馈的折叠式共源共栅结构,利用增益提高和三支路电流基准技术实现一个可用于12~14 bit精度,100 MS/s采样频率的高速流水线(Pipelined)ADC的运放。设计基于SMIC 0.25μm CMOS工艺,在Cadence环境下对电路进行Spectre仿真。仿真结果表明,在2.5 V单电源电压下驱动2 pF负载时,运放的直流增益可达到124 dB,单位增益带宽720 MHz,转换速率高达885 V/μs,达到0.1%的稳定精度的建立时间只需4 ns,共模抑制比153 dB。%A fully differential opamp used in a high speed ADC was designed.The main amplifier is a folded cascode amplifier with SC CMFB.The opamp can be used in a 12 bit、100MS/s high speed Pipelined ADC with gain boosting and the triple-branch current reference technique.The operational amplifier is implemented in a standard 0.25 μm CMOS process,simulated with Spectre under Cadence.With 2.5 V power supply and 2 pF load capacitance has a DC gain of 124 dB,a unity gain bandwidth of 720 MHz,Slew Rate of 885 V/μs,4 ns settling time and 153dB CMRR.

  18. Design of Low Voltage Low Power CMOS OP-AMP

    OpenAIRE

    2014-01-01

    Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipa...

  19. 应用于D类功率放大器的新型可调式CMOSPOP噪音抑制系统%A Novel Tunable CMOS Pop Noise Suppression Systems Applied to Class-D Power Amplifier

    Institute of Scientific and Technical Information of China (English)

    唐宁; 张腾

    2014-01-01

    介绍了一种新型可调POP噪音抑制系统,在集成于芯片内部的同时,提供了稳定的POP噪音抑制,采用SMIC 0.18μm CMOS工艺制作,重点采用了时序控制的方法,使得D类功率放大器中的运放和比较器在不同时刻分别开启,达到了抑制噪音的目的。通过理论分析及仿真结果表明,该POP噪声抑制系统可以在电压刚开启时,1.5 ms、2 ms通过开关控制完成运放和比较器的开启,减小运放的噪声系数,起到了良好的POP噪声抑制作用。%An new type of adjustable POP noise suppression system is designed for integrating in the chip, and providing a stable POP noise suppression. By using SMIC 0. 18 μm CMOS fabrication,this device is focusing on the use of a timing control method to make the Class D power amplifier op amps and comparators open at different times to achieve the purpose of suppressing noise. Through theoretical analysis and simulation results show that the POP noise suppression system can control the op amp and comparator at the beginning,1. 5ms and 2ms,by the switch to open up,reduce the noise figure and obtain a good POP noise suppression results.

  20. 1.5 V低功耗CMOS恒跨导轨对轨运算放大器%A 1.5 V Low-power Rail-to-Rail CMOS Operational Amplifier with Constant-gm

    Institute of Scientific and Technical Information of China (English)

    邓红辉; 尹勇生; 高明伦

    2009-01-01

    运算放大器是模拟集成电路中用途最广、最基本的部件.随着系统功耗及电源电压的降低,传统的运算放大器已经不能满足低压下大共模输入范围及宽输出摆幅的要求.轨对轨运算放大器可以有效解决这一问题,然而传统的轨对轨运算放大器存在跨导不恒定的缺点.本文设计一种1.5V低功耗CMOS恒跨导轨对轨运算放大器,输入级采用最小电流选择电路,不仅实现了跨导的恒定,而且具有跨导不依赖于理想平方律模型、MOS管可以工作于所有区域、移植性好的优点.输出级采用前馈式AB类输出级,不仅能够精确控制输出晶体管电流,而且使输出达到轨对轨全摆幅.所设计的运算放大器采用了改进的级联结构,以减小运算放大器的噪声和失调.基于SMIC 0.18 μm工艺模型.利用Hspice软件对电路进行仿真,仿真结果表明,当电路驱动2 pF的电容负载以及10 KΩ的电阻负载时,直流增益达到83.2 dB,单位增益带宽为7.76 MHz,相位裕度为63°;输入输出均达到轨对轨全摆幅;在整个共模输入变化范围内跨导变化率仅为2.49%;具有较高的共模抑制比和电源抑制比;在1.5V低压下正常工作,静态功耗仅为0.24mW.%Operational amplifier is a basic device, most widely used in the analog integrated circuits. With the reduction of the system power consumption and with a low power supply voltage, the traditional operational amplifier can not meet the requirements of the large input common-mode range and the wide output swing under a low voltage. The rail-to-rail operational amplifier can meet these requirements. But the trans -conductance of the traditionalrail-to-rail operational amplifier is not constant. A 1.5 V low-power CMOS rail-to-rail operational amplifier is designed in this paper. A minimum current selection circuit is adopted in the input stage to achieve constant-g_m so that the trans-conductance is not independent of the ideal square

  1. Graphene/Si CMOS hybrid hall integrated circuits.

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-07

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  2. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    Science.gov (United States)

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-07-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal amplifying/process ICs are manufactured via commercial 0.18 um silicon CMOS technology, and graphene Hall elements (GHEs) are fabricated on top of the passivation layer of the CMOS chip via a low-temperature micro-fabrication process. The sensitivity of the GHE on CMOS chip is further improved by integrating the GHE with the CMOS amplifier on the Si chip. This work not only paves the way to fabricate graphene/Si CMOS Hall ICs with much higher performance than that of conventional Hall ICs, but also provides a general method for scalable integration of graphene devices with silicon CMOS ICs via a low-temperature process.

  3. 3GHz~5GHz CMOS超宽带低噪声放大器设计%Design of a 3 GHz~5 GHz CMOS ultra-wideband low noise amplifier

    Institute of Scientific and Technical Information of China (English)

    王宁章; 唐江波; 秦国宾; 卢安栋; 罗婕思

    2011-01-01

    提出了一个低噪声、高线性的超宽带低噪声放大器(UWB LNA).电路由窄带PCSNIM LNA拓扑结构和并联低Q负载结构组成,采用TSMC 0.18 μm RFCMOS工艺,并在其输入输出端引入了高阶带通滤波器.仿真结果表明,在1.8V直流电压下LNA的功耗约为10.6 mW.在3 GHz~5 GHz 的超宽带频段内,增益约为13.5 dB,输入、输出回波损耗S11、S22均小于-14 dB,噪声系数(NF)为0.875 dB~4.072 dB,三阶交调点IIP3均值为5.35 dB.%A low noise, high linearity ultra-wideband low noise amplifier(UWB LNA)is presented. The circuit is constituted by PCSNIM LNA circuit topology and parallel low-Q load structure in TSMC 0.18 μm RF CMOS technology, and the high-order band-pass filters are introduced at the input and output ports. Simulation results show that at 1.8 V supply voltage the consumption of LNA is about 10.6 mW. In the 3 GHz~5 GHz UWB frequency band, gain is about 13.5 dB, input and output return loss S11、S22 is less than -14 dB, noise figure(NF) 0.875 dB~4.072 dB, third-order intercept point ⅡP3 is the average of 5.35 dB.

  4. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  5. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  6. Nanosecond monolithic CMOS readout cell

    Science.gov (United States)

    Souchkov, Vitali V.

    2004-08-24

    A pulse shaper is implemented in monolithic CMOS with a delay unit formed of a unity gain buffer. The shaper is formed of a difference amplifier having one input connected directly to an input signal and a second input connected to a delayed input signal through the buffer. An elementary cell is based on the pulse shaper and a timing circuit which gates the output of an integrator connected to the pulse shaper output. A detector readout system is formed of a plurality of elementary cells, each connected to a pixel of a pixel array, or to a microstrip of a plurality of microstrips, or to a detector segment.

  7. Fiber Amplifiers

    DEFF Research Database (Denmark)

    Rottwitt, Karsten

    2017-01-01

    The chapter provides a discussion of optical fiber amplifiers and through three sections provides a detailed treatment of three types of optical fiber amplifiers, erbium doped fiber amplifiers (EDFA), Raman amplifiers, and parametric amplifiers. Each section comprises the fundamentals including t...

  8. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... these issues and presents the development leading to applicable technological solutions. The via technology developed in this work enable effective utilization of the available surface area on both sides of the amplifier chip for redistribution as well as placement of passive components and external...... connections. A process for wafer level packaging and assembly of chips with vias is presented in this thesis. Discrete components, capacitors and resistors, are assembled on the backside of the amplifier chips by screen printing of solder paste, pick and place of components, and reflow soldering. Since...

  9. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  10. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...... poor performance compared to the bipolar designs, but CMOS has a potential for CFB op-amp design if more ingenious circuit configurations are applied...

  11. Reliability engineering in RF CMOS

    OpenAIRE

    2008-01-01

    In this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies.

  12. Applying Time-sharing technique in a multimodal compact low-power CMOS neurochip for simultaneous neurochemical and action potential recording.

    Science.gov (United States)

    Poustinchi, Mohammad; Stacey, R Greg; Musallam, Sam

    2014-01-01

    Brain is an electrochemical system and recent studies suggest simultaneous measurement of interrelated brain's electrical and neurochemical activity may lead to better understanding of brain function in addition to developing optimal neural prosthetics. By exploiting opamp Time-sharing technique to minimized power dissipation and silicon area, we have fabricated a power efficient implantable CMOS microsystem for simultaneous measurement of Action Potential (AP) and neurotransmitter concentration. Both AP-recording and neurotransmitter sensing subsystems share a single 653 nW amplifier which senses picoscale to microscale current that corresponds to micromolar neurotransmitter concentration and microscale AP voltage. This microsystem is fabricated in CMOS 0.18 μm technology and tested using recorded signals from dorsal premotor cortex (PMd) area of a macaque monkey in our lab.

  13. Design of Low Voltage Low Power CMOS OP-AMP

    Directory of Open Access Journals (Sweden)

    Shahid Khan,

    2014-11-01

    Full Text Available Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.

  14. A CMOS OTA for HF filters with programmable transfer function

    NARCIS (Netherlands)

    van de Zwan, Eric J.; Klumperink, Eric A.M.; Seevinck, E.; Seevinck, Evert

    1991-01-01

    A CMOS operational transconductance amplifier (OTA) for programmable HF filters is presented. When used in an OTA-C integrator, the unity-gain frequency phase error remains less than 0.3° for frequencies up to more than one tenth of the OTA bandwidth. The OTA has built-in phase compensation, which

  15. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  16. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  17. DESIGN AND IMPLEMETTATION OF CMOS IMAGE SENSOR

    Institute of Scientific and Technical Information of China (English)

    Liu Yu; Wang Guoyu

    2007-01-01

    A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35 μm process along with its design and implementation is introduced in this paper. The pixel architecture of Active Pixel Sensor (APS) is used in the chip, which comprises a 256×256 pixel array together with column amplifiers, scan array circuits, series interface, control logic and Analog-Digital Converter (ADC). With the use of smart layout design, fill factor of pixel cell is 43%. Moreover, a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used.The CMOS image sensor chip is implemented based on the 0.35 μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.

  18. Realization of OFCC based Transimpedance Mode Instrumentation Amplifier

    Directory of Open Access Journals (Sweden)

    Neeta Pandey

    2016-01-01

    Full Text Available The paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three Operational Floating Current Conveyors (OFCCs and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematicThe paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three operational floating current conveyors (OFCCs and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematic.

  19. Operational amplifiers

    CERN Document Server

    Dostal, Jiri

    1993-01-01

    This book provides the reader with the practical knowledge necessary to select and use operational amplifier devices. It presents an extensive treatment of applications and a practically oriented, unified theory of operational circuits.Provides the reader with practical knowledge necessary to select and use operational amplifier devices. Presents an extensive treatment of applications and a practically oriented, unified theory of operational circuits

  20. Operational Amplifiers.

    Science.gov (United States)

    Foxcroft, G. E.

    1986-01-01

    Addresses the introduction of low cost equipment into high school and college physical science classes. Examines the properties of an "ideal" operational amplifier and discusses how it might be used under saturated and non-saturated conditions. Notes the action of a "real" operational amplifier. (TW)

  1. An Electronically Tunable Transconductance Amplifier for Use in Auditory Prostheses

    Directory of Open Access Journals (Sweden)

    FARAGO, P.

    2015-11-01

    Full Text Available Low-voltage and low-power trends in analog electronics enable novel features in modern bio-medical devices, such as extensive portability, autonomy and even battery-less operation. One specific example is the cochlear implant (CI, which emulates the physiology of hearing to produce auditory sensations via neural stimulation. Besides low-voltage and low-power operation, a key feature in modern CIs is wide-range programmability of the speech processing parameters. This paper proposes an operational transconductance amplifier (OTA for use in CIs, with wide-range electronic tuning of the transconductance value. The proposed OTA is developed around a cascade of two transconductor stages, making the transconductance dependent on the bias current ratio. A combination of linearization techniques: bulk input, parallel differential pairs and feedback, is used to achieve sufficient linear range for CI speech processing. Wide-range parameter tuning of the speech processing sections is illustrated on a variable gain amplifier, a bandpass Tow-Thomas biquad and an envelope detector. Finally, the complete CI speech processing chain is illustrated. The proposed OTA and its employment in CI analog speech processing are validated on a 350 nm CMOS process.

  2. 基于0.18μm CMOS工艺2.5Gb/s宽动态范围光接收机前端放大电路设计%Design of 2.5 Gb/s Wide Dynamic Range Optical Receiver Front-End Amplifier in 0.18 μm CMOS

    Institute of Scientific and Technical Information of China (English)

    韩良; 孙骏毅; 张颖

    2011-01-01

    基于0.18μm CMOS工艺设计了适用于2.5Gb/s传输速率的宽动态范围光接收机前端放大电路(包括前置放大器和限幅放大器).前置放大器采用了RGC输入级的跨阻放大器,并且应用了消直流电路和自动增益控制电路扩展输入动态范围.限幅放大器采用了按比例缩小尺寸、并联峰化和带有有源负反馈的Cherry-Hooper放大器等方法扩展带宽.仿真结果表明:前端放大电路的中频增益为116dBΩ,-3dB带宽为2.13GHz,输入信号动态范围为40dB(0.01~1mA).%A front-end amplifier circuit which can be applied to wide-dynamic-range optical receiver with 2.5Gb/s data rate has been designed based on 0.18 μm CMOS technology.Pre-amplifier utilizes Regulated Cascode(RGC) architecture as Transimpedance Amplifier(TIA),meanwhile,DC-cancellation and Auto Gain Controlling(AGC) circuits are employed to expand its dynamic range.Limiting Amplifier(LA) makes the use of several approaches like scaling-down,shunt peaking and Cherry-Hooper amplifier with active feedback,to enlarge its bandwidth.Simulation result has manifested that the gain at medium frequency of the front-end amplifier(including pre-amp and limiting amp) is 116 dBΩ,-3 dB bandwidth is 2.13 GHz,input dynamic range is 40 dB(0.01~1 mA).

  3. MicroCMOS design

    CERN Document Server

    Song, Bang-Sup

    2011-01-01

    MicroCMOS Design covers key analog design methodologies with an emphasis on analog systems that can be integrated into systems-on-chip (SoCs). Starting at the transistor level, this book introduces basic concepts in the design of system-level complementary metal-oxide semiconductors (CMOS). It uses practical examples to illustrate circuit construction so that readers can develop an intuitive understanding rather than just assimilate the usual conventional analytical knowledge. As SoCs become increasingly complex, analog/radio frequency (RF) system designers have to master both system- and tran

  4. Vertical Isolation for Photodiodes in CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata

    2008-01-01

    In a proposed improvement in complementary metal oxide/semi conduct - or (CMOS) image detectors, two additional implants in each pixel would effect vertical isolation between the metal oxide/semiconductor field-effect transistors (MOSFETs) and the photodiode of the pixel. This improvement is expected to enable separate optimization of the designs of the photodiode and the MOSFETs so as to optimize their performances independently of each other. The purpose to be served by enabling this separate optimization is to eliminate or vastly reduce diffusion cross-talk, thereby increasing sensitivity, effective spatial resolution, and color fidelity while reducing noise.

  5. Linearisation of RF Power Amplifiers

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck

    2001-01-01

    This thesis deals with linearisation techniques of RF power amplifiers (PA), PA design techniques and integration of the necessary building blocks in a CMOS technology. The opening chapters introduces the theory of transmitter architectures, RF-signal representation and the principles of digital...... modulation. Furthermore different types of power amplifiers, models and measures of non-linearities are presented. A chapter is also devoted to different types of linearisation systems. The work carried out and described in this thesis can be divided into a more theoretical and system oriented treatment...... the polar loop architecture and it’s suitability to modern digital transmitters is discussed. A proposal of an architecture that is suitable for digital transmitters, which means that it has an interface to the digital back-end, defined by low-pass signals in polar form, is presented. Simulation guidelines...

  6. Comparative Study of CMOS Op-Amp In 45nm And 180 Nm Technology

    Directory of Open Access Journals (Sweden)

    Siddharth

    2014-07-01

    Full Text Available In this paper we have provided a method for designing a Two Stage CMOS Operational Amplifier which operates at 1.8V power supply using Cadence Virtuoso 45nm CMOS technology. Further, designing the two stage op-amp for the same power supply using Cadence Virtuoso 180nm CMOS Technology, keeping the slew rate of the op-amp same as that 45nm technology. The trade-off curves are computed between various characteristics such as Gain, Phase Margin,GBW,3db Gain etc. and the results obtained for 45n CMOS Technology is compared with those obtained for 180nm CMOS Technology It has been demonstrated that on lowering the technology and keeping the slew rate constant, the Power dissipation decreases.

  7. A linear stepping PGA used in CMOS image sensors

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 李斌桥; 赵士彬; 李红乐; 姚素英

    2009-01-01

    A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine. The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.

  8. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  9. High-speed polysilicon CMOS photodetector for telecom and datacom

    Science.gov (United States)

    Atabaki, Amir H.; Meng, Huaiyu; Alloatti, Luca; Mehta, Karan K.; Ram, Rajeev J.

    2016-09-01

    Absorption by mid-bandgap states in polysilicon or heavily implanted silicon has been previously utilized to implement guided-wave infrared photodetectors in CMOS compatible photonic platforms. Here, we demonstrate a resonant guided-wave photodetector based on the polysilicon layer that is used for the transistor gate in a microelectronic SOI CMOS process without any change to the foundry process flow ("zero-change" CMOS). Through a combination of doping mask layers, a lateral pn junction diode in the polysilicon is demonstrated with a strong electric field to enable efficient photo-carrier extraction and high-speed operation. This photodetector has a responsivity of more than 0.14 A/W from 1300 to 1600 nm, a 10 GHz bandwidth, and 80 nA dark current at 15 V reverse bias.

  10. Improved Space Object Observation Techniques Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Hinze, A.; Schlatter, P.; Silha, J.; Peltonen, J.; Santti, T.; Flohrer, T.

    2013-08-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contain their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. Presently applied and proposed optical observation strategies for space debris surveys and space surveillance applications had to be analyzed. The major design drivers were identified and potential benefits from using available and future CMOS sensors were assessed. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, the characteristics of a particular CMOS sensor available at the Zimmerwald observatory were analyzed by performing laboratory test measurements.

  11. Building strong partnerships with CMOs.

    Science.gov (United States)

    Dye, Carson F

    2014-07-01

    CFOs and chief medical officers (CMOs) can build on common traits to form productive partnerships in guiding healthcare organizations through the changes affecting the industry. CFOs can strengthen bonds with CMOs by taking steps to engage physicians on their own turf--by visiting clinical locations and attending medical-executive committee meetings, for example. Steps CFOs can take to help CMOs become more acquainted with the financial operations of health systems include demonstrating the impact of clinical decisions on costs and inviting CMOs to attend finance-related meetings.

  12. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  13. Wideband CMOS low noise amplifier including an active balun

    NARCIS (Netherlands)

    Blaakmeer, S.C.; Klumperink, Eric A.M.; Leenaerts, D.M.W.; Nauta, Bram

    2007-01-01

    An inductorless LNA with active balun is proposed for multi-standard radio applications between 100MHz and 6GHz [1]. It exploits a combination of a common-gate (CG) stage and an common-source (CS) stage with replica biasing to maximize balanced operation, while simultaneously canceling the noise and

  14. Wide-Temperature-Range Integrated Operational Amplifier

    Science.gov (United States)

    Mojarradi, Mohammad; Levanas, Greg; Chen, Yuan; Kolawa, Elizabeth; Cozy, Raymond; Blalock, Benjamin; Greenwell, Robert; Terry, Stephen

    2007-01-01

    A document discusses a silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) integrated- circuit operational amplifier to be replicated and incorporated into sensor and actuator systems of Mars-explorer robots. This amplifier is designed to function at a supply potential less than or equal to 5.5 V, at any temperature from -180 to +120 C. The design is implemented on a commercial radiation-hard SOI CMOS process rated for a supply potential of less than or equal to 3.6 V and temperatures from -55 to +110 C. The design incorporates several innovations to achieve this, the main ones being the following: NMOS transistor channel lengths below 1 m are generally not used because research showed that this change could reduce the adverse effect of hot carrier injection on the lifetimes of transistors at low temperatures. To enable the amplifier to withstand the 5.5-V supply potential, a circuit topology including cascade devices, clamping devices, and dynamic voltage biasing was adopted so that no individual transistor would be exposed to more than 3.6 V. To minimize undesired variations in performance over the temperature range, the transistors in the amplifier are biased by circuitry that maintains a constant inversion coefficient over the temperature range.

  15. Structured Analog CMOS Design

    CERN Document Server

    Stefanovic, Danica

    2008-01-01

    Structured Analog CMOS Design describes a structured analog design approach that makes it possible to simplify complex analog design problems and develop a design strategy that can be used for the design of large number of analog cells. It intentionally avoids treating the analog design as a mathematical problem, developing a design procedure based on the understanding of device physics and approximations that give insight into parameter interdependences. The proposed transistor-level design procedure is based on the EKV modeling approach and relies on the device inversion level as a fundament

  16. Noise Properties of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1996-01-01

    The definition of the current conveyor is presented and it is shown how different generations of current conveyors can all be combined into a single definition of a multiple-output second generation current conveyor (CCII). Next, noise sources are introduced into the model, and a general noise...... model for the current conveyor is established. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the relative merits with respect to the noise performance of these configurations are discussed. Finally, the noise model...... is developed for a CMOS current conveyor implementation, and optimization strategies for noise reduction are discussed. It is concluded that a class AB implementation provides more flexibility than does a class A configuration. In both cases it is essential to design low noise current mirrors and current...

  17. Analog CMOS design for optical coherence tomography signal detection and processing.

    Science.gov (United States)

    Xu, Wei; Mathine, David L; Barton, Jennifer K

    2008-02-01

    A CMOS circuit was designed and fabricated for optical coherence tomography (OCT) signal detection and processing. The circuit includes a photoreceiver, differential gain stage and lock-in amplifier based demodulator. The photoreceiver consists of a CMOS photodetector and low noise differential transimpedance amplifier which converts the optical interference signal into a voltage. The differential gain stage further amplifies the signal. The in-phase and quadrature channels of the lock-in amplifier each include an analog mixer and switched-capacitor low-pass filter with an external mixer reference signal. The interferogram envelope and phase can be extracted with this configuration, enabling Doppler OCT measurements. A sensitivity of -80 dB is achieved with faithful reproduction of the interferometric signal envelope. A sample image of finger tip is presented.

  18. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  19. Wideband pulse amplifiers for the NECTAr chip

    Science.gov (United States)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

    2012-12-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  20. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  1. Design of Low-Power CMOS OTA Using Bulk-Drive Technique

    OpenAIRE

    2015-01-01

    This paper presents the design of low power CMOS- OTA (operational transconductance amplifier) using bulk drive (BD) technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV),low pow...

  2. Reducing crosstalk in vertically integrated CMOS image sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2010-01-01

    Image sensors can benefit from 3D IC fabrication methods because photodetectors and electronic circuits may be fabricated using significantly different processes. When fabricating the die that contains the photodetectors, it is desirable to avoid pixel level patterning of the light sensitive semiconductor. But without a physical border between adjacent photodetectors, lateral currents may flow between neighboring devices, which is called "crosstalk". This work introduces circuits that can be used to reduce crosstalk in vertically-integrated (VI) CMOS image sensors with an unpatterned photodetector array. It treats the case of a VI-CMOS image sensor composed of a silicon die with CMOS read-out circuits and a transparent die with an unpatterned array of photodetectors. A reduction in crosstalk can be achieved by maintaining a constant electric potential at all nodes, at which the photodetector array connects with the readout circuit array. This can be implemented by designing a pixel circuit that uses an operational amplifier with a logarithmic feedback to control the voltage at the input node. The work presents several optional circuit configurations for the pixel circuit, and indicates the one that is the most power efficient. Afterwards, it uses a simplified small-signal model of the pixel circuit to address stability and compensation issues. Lastly, the method is validated through circuit simulation for a standard CMOS process.

  3. Optimization and Performance Analysis of Bulk-Driven Differential Amplifier

    Directory of Open Access Journals (Sweden)

    Antarpreet kaur

    2014-04-01

    Full Text Available In recent years, there has been an increasing demand for high-speed digital circuits at low power consumption. This paper presents a design of input stage of Operational Amplifier i.e cascode differential amplifier using a standard 65nm CMOS Technology.A comparison betweem gate-driven, bulk-driven and cascode bulk driven bulk-driven differential amplifier is described. The Results demonstrate that CMMR is 83.98 dB, 3-dB Bandwidth is 1.04 MHz. The circuit dissipate power of 28uWunder single supply of 1.0V.

  4. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  5. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  6. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...

  7. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...

  8. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  9. CMOS-Based Biosensor Arrays

    CERN Document Server

    Thewes, R; Schienle, M; Hofmann, F; Frey, A; Brederlow, R; Augustyniak, M; Jenkner, M; Eversmann, B; Schindler-Bauer, P; Atzesberger, M; Holzapfl, B; Beer, G; Haneder, T; Hanke, H -C

    2011-01-01

    CMOS-based sensor array chips provide new and attractive features as compared to today's standard tools for medical, diagnostic, and biotechnical applications. Examples for molecule- and cell-based approaches and related circuit design issues are discussed.

  10. Comparators in nanometer CMOS technology

    CERN Document Server

    Goll, Bernhard

    2015-01-01

    This book covers the complete spectrum of the fundamentals of clocked, regenerative comparators, their state-of-the-art, advanced CMOS technologies, innovative comparators inclusive circuit aspects, their characterization and properties. Starting from the basics of comparators and the transistor characteristics in nanometer CMOS, seven high-performance comparators developed by the authors in 120nm and 65nm CMOS are described extensively. Methods and measurement circuits for the characterization of advanced comparators are introduced. A synthesis of the largely differing aspects of demands on modern comparators and the properties of devices being available in nanometer CMOS, which are posed by the so-called nanometer hell of physics, is accomplished. The book summarizes the state of the art in integrated comparators. Advanced measurement circuits for characterization will be introduced as well as the method of characterization by bit-error analysis usually being used for characterization of optical receivers. ...

  11. CMOS array design automation techniques

    Science.gov (United States)

    Lombardi, T.; Feller, A.

    1976-01-01

    The design considerations and the circuit development for a 4096-bit CMOS SOS ROM chip, the ATL078 are described. Organization of the ATL078 is 512 words by 8 bits. The ROM was designed to be programmable either at the metal mask level or by a directed laser beam after processing. The development of a 4K CMOS SOS ROM fills a void left by available ROM chip types, and makes the design of a totally major high speed system more realizable.

  12. CMOS Nonlinear Signal Processing Circuits

    OpenAIRE

    2010-01-01

    The chapter describes various nonlinear signal processing CMOS circuits, including a high reliable WTA/LTA, simple MED cell, and low-voltage arbitrary order extractor. We focus the discussion on CMOS analog circuit design with reliable, programmable capability, and low voltage operation. It is a practical problem when the multiple identical cells are required to match and realized within a single chip using a conventional process. Thus, the design of high-reliable circuit is indeed needed. Th...

  13. Low Power CMOS Analog Multiplier

    Directory of Open Access Journals (Sweden)

    Shipra Sachan

    2015-12-01

    Full Text Available In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it consumes only 31.8µW quiescent power and 110MHZ bandwidth.

  14. Low noise Millimeter-wave and THz Receivers, Imaging Arrays, Switches in Advanced CMOS and SiGe Processes /

    OpenAIRE

    Uzunkol, Mehmet

    2013-01-01

    The thesis presents advanced millimeter-wave and THz receivers, imaging arrays, switches and detectors in CMOS and SiGe BiCMOS technologies. First, an in-depth analysis of a SiGe BiCMOS on-off keying (OOK) receiver composed of a low noise SiGe amplifier and an OOK detector is presented. The analysis indicates that the bias circuit and bias current have a substantial impact on the receiver and should be optimized for best performance. Also, the LO leakage from the transmitter can have a detrim...

  15. A novel noise optimization technique for inductively degenerated CMOS LNA

    Institute of Scientific and Technical Information of China (English)

    Geng Zhiqing; Wang Haiyong; Wu Nanjian

    2009-01-01

    This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 pan CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

  16. A novel noise optimization technique for inductively degenerated CMOS LNA

    Science.gov (United States)

    Zhiqing, Geng; Haiyong, Wang; Nanjian, Wu

    2009-10-01

    This paper proposes a novel noise optimization technique. The technique gives analytical formulae for the noise performance of inductively degenerated CMOS low noise amplifier (LNA) circuits with an ideal gate inductor for a fixed bias voltage and nonideal gate inductor for a fixed power dissipation, respectively, by mathematical analysis and reasonable approximation methods. LNA circuits with required noise figure can be designed effectively and rapidly just by using hand calculations of the proposed formulae. We design a 1.8 GHz LNA in a TSMC 0.25 μm CMOS process. The measured results show a noise figure of 1.6 dB with a forward gain of 14.4 dB at a power consumption of 5 mW, demonstrating that the designed LNA circuits can achieve low noise figure levels at low power dissipation.

  17. CMOS mm-wave transceivers for Gbps wireless communication

    Science.gov (United States)

    Baoyong, Chi; Zheng, Song; Lixue, Kuang; Haikun, Jia; Xiangyu, Meng; Zhihua, Wang

    2016-07-01

    The challenges in the design of CMOS millimeter-wave (mm-wave) transceiver for Gbps wireless communication are discussed. To support the Gbps data rate, the link bandwidth of the receiver/transmitter must be wide enough, which puts a lot of pressure on the mm-wave front-end as well as on the baseband circuit. This paper discusses the effects of the limited link bandwidth on the transceiver system performance and overviews the bandwidth expansion techniques for mm-wave amplifiers and IF programmable gain amplifier. Furthermore, dual-mode power amplifier (PA) and self-healing technique are introduced to improve the PA's average efficiency and to deal with the process, voltage, and temperature variation issue, respectively. Several fully-integrated CMOS mm-wave transceivers are also presented to give a short overview on the state-of-the-art mm-wave transceivers. Project supported in part by the National Natural Science Foundation of China (No. 61331003).

  18. CMOS upconversion mixer with filterless carrier feedthrough cancelation and output power tuning

    NARCIS (Netherlands)

    Sanchez Gaspariano, Luis Abraham; Annema, Anne-Johan; Muniz Montero, Carlos; Diaz Sanchez, Alejandro

    2014-01-01

    The synthesis, design and implementation of a CMOS upconversion mixer that both can adjust, by means of a DC voltage control, its output power and that cancels the carrier feedthrough is presented. Aiming at very low cost medical implant applications, a prototype of the architecture was implemented

  19. A New Compensation Technique for Stable The Gain of Sub-Micron Amplifiers

    Directory of Open Access Journals (Sweden)

    Billu.balaji

    2014-12-01

    Full Text Available Process variation is an difficulty in designing reliable CMOS mixed signal systems with high yield. To minimize the variation in voltage gain due to variations in process, supply voltage, and temperature for common trans conductance-based amplifiers, we present a new compensation method based on statistical feedback of process information. We further apply our scheme to two well known amplifier topologies in the sun-micron CMOS process as design examples—an inductive degenerated low-noise amplifier (LNA and a common source amplifier (CSA. The proposed method improves the variation in S21 of an inductively degenerated cascade LNA from 8.75% to 1.27%, which is a reduction in variation of 85%. The presented scheme is also robust over variations in supply voltage, temperature, and process conditions. The compensation method presented can be utilized to stabilize the gain of a wide variety of amplifiers.

  20. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  1. Large area CMOS image sensors

    Science.gov (United States)

    Turchetta, R.; Guerrini, N.; Sedgwick, I.

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  2. CMOS bulk-metal design handbook

    Science.gov (United States)

    Edge, T. M.

    1978-01-01

    User's guide describes techniques for generating precision mask artwork for complex CMOS integrated circuits, starting from logic diagram. Techniques are based on standard-cell approach. Guide also includes user guidelines for designing efficient CMOS arrays.

  3. Cochlear Implant

    Directory of Open Access Journals (Sweden)

    Mehrnaz Karimi

    1992-04-01

    Full Text Available People with profound hearing loss are not able to use some kinds of conventional amplifiers due to the nature of their loss . In these people, hearing sense is stimulated only when the auditory nerve is activated via electrical stimulation. This stimulation is possible through cochlear implant. In fact, for the deaf people who have good mental health and can not use surgical and medical treatment and also can not benefit from air and bone conduction hearing aids, this device is used if they have normal central auditory system. The basic parts of the device included: Microphone, speech processor, transmitter, stimulator and receiver, and electrode array.

  4. High Gain Amplifier with Enhanced Cascoded Compensation

    Directory of Open Access Journals (Sweden)

    J. Lemus-Lopez

    2014-04-01

    Full Text Available A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT the supply requirements, the number of capacitors and the size of the compensation capacitors respect to other Miller schemes are reduced. A prototype was fabricated using a 0.5 μm technology, resulting, for a load of 45 pF and supply voltage of 1.65 V, in open-loop-gain of 129 dB, 23 MHz of gain-bandwidth product, 60o phase margin, 675 μW power consumption and 1% settling time of 28 ns.

  5. A Full CMOS Integration Including ISFET Microsensors and Interface Circuit for Biochemical Applications

    Institute of Scientific and Technical Information of China (English)

    Jinbao Wei; Haigang Yang; Hongguang Sun; Zengjin Lin; Shanhong Xia

    2006-01-01

    One of today's challenges is the integration of ISFETs in chemical and biochemical Microsystems. This article presents a full integration of ISFET chip containing the ISFET/REFET (reference FET) pair, ISFET/REFET amplifiers, bias current generator, as well as a reference electrode structure, all integrated on the same chip based on CMOS technology. The sensor chip was fabricated in a standard 0.35 μm CMOS process (Chartered Semiconductor, Singapore). The extra post processing steps have been developed and added for depositing membranes. Finally, the pH response of the integrated sensor was measured with the interface circuit.

  6. A CMOS current-mode log(x) and log(1/x) functions generator

    Science.gov (United States)

    Al-Absi, Munir A.; Al-Tamimi, Karama M.

    2014-08-01

    A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

  7. A CMOS floating point multiplier

    Science.gov (United States)

    Uya, M.; Kaneko, K.; Yasui, J.

    1984-10-01

    This paper describes a 32-bit CMOS floating point multiplier. The chip can perform 32-bit floating point multiplication (based on the proposed IEEE Standard format) and 24-bit fixed point multiplication (two's complement format) in less than 78.7 and 71.1 ns, respectively, and the typical power dissipation is 195 mW at 10 million operations per second. High-speed multiplication techniques - a modified Booth's allgorithm, a carry save adder scheme, a high-speed CMOS full adder, and a modified carry select adder - are used to achieve the above high performance. The chip is designed for compatibility with 16-bit microcomputer systems, and is fabricated in 2 micron n-well CMOS technology; it contains about 23000 transistors of 5.75 x 5.67 sq mm in size.

  8. A 8.9-ENOB 2.5-εW 150-KS/s non-binary redundant successive approximation ADC in 0.18-microm CMOS for bio-implanted devices.

    Science.gov (United States)

    Chan, Kok Lim; Lee, Andreas Astuti; Yuan, Xiaojun; Krishna, Kotlanka R; Je, Minkyu

    2010-01-01

    A successive approximation analog-to-digital converter (SAR ADC) with a split-capacitor switching scheme implementing the generalized non-binary redundant SAR algorithm and an energy efficient level shifter is proposed for bio-implanted applications. The generalized non-binary redundant SAR algorithm removes the radix constraint in conventional non-binary redundant SAR algorithm, and the energy efficient level shifter allows optimal power supplies to be chosen independently for the analog and digital blocks. A FOM of 34.7fJ/step has been achieved.

  9. Improved Signal Chains for Readout of CMOS Imagers

    Science.gov (United States)

    Pain, Bedabrata; Hancock, Bruce; Cunningham, Thomas

    2009-01-01

    An improved generic design has been devised for implementing signal chains involved in readout from complementary metal oxide/semiconductor (CMOS) image sensors and for other readout integrated circuits (ICs) that perform equivalent functions. The design applies to any such IC in which output signal charges from the pixels in a given row are transferred simultaneously into sampling capacitors at the bottoms of the columns, then voltages representing individual pixel charges are read out in sequence by sequentially turning on column-selecting field-effect transistors (FETs) in synchronism with source-follower- or operational-amplifier-based amplifier circuits. The improved design affords the best features of prior source-follower-and operational- amplifier-based designs while overcoming the major limitations of those designs. The limitations can be summarized as follows: a) For a source-follower-based signal chain, the ohmic voltage drop associated with DC bias current flowing through the column-selection FET causes unacceptable voltage offset, nonlinearity, and reduced small-signal gain. b) For an operational-amplifier-based signal chain, the required bias current and the output noise increase superlinearly with size of the pixel array because of a corresponding increase in the effective capacitance of the row bus used to couple the sampled column charges to the operational amplifier. The effect of the bus capacitance is to simultaneously slow down the readout circuit and increase noise through the Miller effect.

  10. DESIGN OF LOW NOISE AMPLIFIER FOR UWB RADIO RECEIVER.

    Directory of Open Access Journals (Sweden)

    Alpana Adsul

    2011-10-01

    Full Text Available An Ultra Wide Band CMOS Low Noise Amplifier (LNA design is presented in this paper. Due to low power consumption and extremely high data rates the UWB system is bound to be popular in the end user market. The LNA is the first stage after antenna in an UWB transceiver. The LNA is accountable for providing enough gain to the signal with the bare minimum distortion. In this work we have designed and evaluated the performance of a complementary metal oxide semiconductor (CMOS low noise amplifier (LNA for 3.1-10.6 GHZ frequency band. Agilent's ADS tool has been used to simulate the designed LNA and is proved to have better noise figure as well as input matching. The designed LNA provides the low S11, S22, and noise figure. The gain achieved is 6dB and the response over the band of interest is almost flat.

  11. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  12. Single event effects in 0.18μm CMOS image sensors

    Science.gov (United States)

    Rushton, Joseph E.; Stefanov, Konstantin D.; Holland, Andrew D.; Bugnet, Henri; Mayer, Frederic; Cordrey-Gale, Matthew; Endicott, James

    2016-08-01

    CMOS image sensors are widely used on Earth and are becoming increasingly favourable for use in space. Advantages, such as low power consumption, and ever-improving imaging peformance make CMOS an attractive option. The ability to integrate camera functions on-chip, such as biasing and sequencing, simplifies designing with CMOS sensors and can improve system reliability. One potential disadvantage to the use of CMOS is the possibility of single event effects, such as single event latchup (SEL), which can cause malfunctions or even permanent destruction of the sensor. These single event effects occur in the space environment due to the high levels of radiation incident on the sensor. This work investigates the ocurrence of SEL in CMOS image sensors subjected to heavy-ion irradiation. Three devices are investigated, two of which have triple-well doping implants. The resulting latchup cross-sections are presented. It is shown that using a deep p well on 18 μm epitaxial silicon increases the radiation hardness of the sensor against latchup. The linear energy transfer (LET) threshold for latchup is increased when using this configuration. Our findings suggest deep p wells can be used to increase the radiation tolerance of CMOS image sensors for use in future space missions.

  13. An integrated CMOS detection system for optical short-pulse

    Science.gov (United States)

    Kim, Chang-Gun; Hong, Nam-Pyo; Choi, Young-Wan

    2014-03-01

    We present design of a front-end readout system consisting of charge sensitive amplifier (CSA) and pulse shaper for detection of stochastic and ultra-small semiconductor scintillator signal. The semiconductor scintillator is double sided silicon detector (DSSD) or avalanche photo detector (APD) for high resolution and peak signal reliability of γ-ray or X-ray spectroscopy. Such system commonly uses low noise multichannel CSA. Each CSA in multichannel includes continuous reset system based on tens of MΩ and charge-integrating capacitor in feedback loop. The high value feedback resistor requires large area and huge power consumption for integrated circuits. In this paper, we analyze these problems and propose a CMOS short pulse detection system with a novel CSA. The novel CSA is composed of continuous reset system with combination of diode connected PMOS and 100 fF. This structure has linearity with increased input charge quantity from tens of femto-coulomb to pico-coulomb. Also, the front-end readout system includes both slow and fast shapers for detecting CSA output and preventing pile-up distortion. Shaping times of fast and slow shapers are 150 ns and 1.4 μs, respectively. Simulation results of the CMOS detection system for optical short-pulse implemented in 0.18 μm CMOS technology are presented.

  14. Third Order Universal Filter Using Single Operational Transresistance Amplifier

    Directory of Open Access Journals (Sweden)

    Mourina Ghosh

    2013-01-01

    Full Text Available This paper proposes a multi-input single-output (MISO third order voltage mode (VM universal filter using only one operational transresistance amplifier (OTRA. The proposed circuit realizes low-pass, high-pass, all-pass, band-pass, and notch responses from the same topology. The PSPICE Simulation results using 0.5 μm CMOS technology agree well with the theoretical design.

  15. Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

    CERN Document Server

    Oliveira, João P

    2012-01-01

    This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC).  Experimental results are shown to validate the overall design technique. Provides the complete theoretical analysis, supported by electrical simulations, of the parametric amplification technique in both continuous time and discrete time domains; Describes the design flow of an ADC fully based on discrete-time parametric amplification in CMOS technology; Presents a high speed time-interleaved pipeline ADC, based on parametric MOS amplification techniques described, complementing theory discussed with experimental results.

  16. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  17. A novel fully differential telescopic operational transconductance amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Li Tianwang; Jiang Jinguang [Department of Integrated Circuits and Communication Software, International School of Software, Wuhan University, Wuhan 430079 (China); Ye Bo, E-mail: jgjiang95@yahoo.com.c [Faculty of Computer and Information Engineering, Shanghai University of Electric Power, Shanghai 200090 (China)

    2009-08-15

    A novel fully differential telescopic operational transconductance amplifier (OTA) is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18{mu}m CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced. (semiconductor integrated circuits)

  18. Cross-differential amplifier

    Science.gov (United States)

    Hajimiri, Seyed-Ali (Inventor); Kee, Scott D. (Inventor); Aoki, Ichiro (Inventor)

    2013-01-01

    A cross-differential amplifier is provided. The cross-differential amplifier includes an inductor connected to a direct current power source at a first terminal. A first and second switch, such as transistors, are connected to the inductor at a second terminal. A first and second amplifier are connected at their supply terminals to the first and second switch. The first and second switches are operated to commutate the inductor between the amplifiers so as to provide an amplified signal while limiting the ripple voltage on the inductor and thus limiting the maximum voltage imposed across the amplifiers and switches.

  19. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  20. A CMOS Switched Transconductor Mixer

    NARCIS (Netherlands)

    Klumperink, Eric A.M.; Louwsma, S.M.; Wienk, Gerhardus J.M.; Nauta, Bram

    A new CMOS active mixer topology can operate at low supply voltages by the use of switches exclusively connected to the supply voltages. Such switches require less voltage headroom and avoid gate-oxide reliability problems. Mixing is achieved by exploiting two transconductors with cross-coupled

  1. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis descri...

  2. 2.5 GHz integrated graphene RF power amplifier on SiC substrate

    Science.gov (United States)

    Hanna, T.; Deltimple, N.; Khenissa, M. S.; Pallecchi, E.; Happy, H.; Frégonèse, S.

    2017-01-01

    In this work, we report the design of 2.5 GHz integrated power amplifier based on a graphene FET fabricated with thermal deposition on SiC. In this first large signal study of graphene radiofrequency power amplifiers, a power gain of 8.9 dB is achieved, the maximum reported output power and power added efficiency are 5.1 dBm and 2.2% respectively. Furthermore, graphene and Si CMOS amplifiers are compared; conclusions are drawn towards the technology enhancements to optimize the amplifiers figures of merit.

  3. Common source cascode amplifiers for integrating IR-FPA applications

    Science.gov (United States)

    Woolaway, James T.; Young, Erick T.

    1989-01-01

    Space based astronomical infrared measurements present stringent performance requirements on the infrared detector arrays and their associated readout circuitry. To evaluate the usefulness of commercial CMOS technology for astronomical readout applications a theoretical and experimental evaluation was performed on source follower and common-source cascode integrating amplifiers. Theoretical analysis indicates that for conditions where the input amplifier integration capacitance is limited by the detectors capacitance the input referred rms noise electrons of each amplifier should be equivalent. For conditions of input gate limited capacitance the source follower should provide lower noise. Measurements of test circuits containing both source follower and common source cascode circuits showed substantially lower input referred noise for the common-source cascode input circuits. Noise measurements yielded 4.8 input referred rms noise electrons for an 8.5 minute integration. The signal and noise gain of the common-source cascode amplifier appears to offer substantial advantages in acheiving predicted noise levels.

  4. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  5. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  6. Simple BiCMOS CCCTA design and resistorless analog function realization.

    Science.gov (United States)

    Tangsrirat, Worapong

    2014-01-01

    The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  7. Design of a CMOS-based multichannel integrated biosensor chip for bioelectronic interface with neurons.

    Science.gov (United States)

    Zhang, Xin; Wong, Wai Man; Zhang, Yulong; Zhang, Yandong; Gao, Fei; Nelson, Richard D; Larue, John C

    2009-01-01

    In this paper we present the design and prototyping of a 24-channel mixed signal full-customized CMOS integrated biosensor chip for in vitro extracellular recording of neural signals. Design and implementation of hierarchical modules including microelectrode electrophysiological sensors, analog signal buffers, high gain amplifier and control/interface units are presented in detail. The prototype chip was fabricated by MOSIS with AMI C5 0.5 microm, double poly, triple metal layer CMOS technology. The electroless gold plating process is used to replace the aluminum material obtained from the standard CMOS process with biocompatible metal gold in the planner microelectrode array sensors to prevent cell poisoning and undesirable electrochemical corrosion. The biosensor chip provides a satisfactory signal-to-noise ratio for neural signals with amplitudes and frequencies within the range of 600microV - 2mV and 100 Hz to 10KHz, respectively.

  8. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

  9. Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

    Directory of Open Access Journals (Sweden)

    Worapong Tangsrirat

    2014-01-01

    Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  10. Portable musical instrument amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Christian, David E. (Danbury, CT)

    1990-07-24

    The present invention relates to a musical instrument amplifier which is particularly useful for electric guitars. The amplifier has a rigid body for housing both the electronic system for amplifying and processing signals from the guitar and the system's power supply. An input plug connected to and projecting from the body is electrically coupled to the signal amplifying and processing system. When the plug is inserted into an output jack for an electric guitar, the body is rigidly carried by the guitar, and the guitar is operatively connected to the electrical amplifying and signal processing system without use of a loose interconnection cable. The amplifier is provided with an output jack, into which headphones are plugged to receive amplified signals from the guitar. By eliminating the conventional interconnection cable, the amplifier of the present invention can be used by musicians with increased flexibility and greater freedom of movement.

  11. A CMOS readout circuit for microstrip detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.

    2015-03-01

    In this work, we present the design and the results of a CMOS analog channel for silicon microstrips detectors. The readout circuit was initially conceived for the outer layers of the SuperB silicon vertex tracker (SVT), but can serve more generally other microstrip-based detection systems. The strip detectors considered show a very high stray capacitance and high series resistance. Therefore, the noise optimization was the first priority design concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been investigated. The ASIC is composed by a preamplifier, shaping amplifier and a Time over Threshold (T.o.T) block for the digitalization of the signals. The chosen shaping function is the third-order semi-Gaussian function implemented with complex poles. An inverter stage is employed in the analog channel in order to operate with signals delivered from both p and n strips. The circuit includes the possibility to select the peaking time of the shaper output from four values: 250 ns, 375 ns, 500 ns and 750 ns. In this way, the noise performances and the signal occupancy can be optimized according to the real background during the experiment. The ASIC prototype has been fabricated in the 130 nm IBM technology which is considered intrinsically radiation hard. The results of the experimental characterization of a produced prototype are satisfactorily matched with simulation.

  12. Characterization of 4 K CMOS devices and circuits for hybrid Josephson-CMOS systems

    OpenAIRE

    Yoshikawa, Nobuyuki; Tomida, T.; Tokuda, A.; Liu, Q.; Meng, X.(Institute of High Energy Physics, Beijing, China); Whiteley, SR.; VanDuzer, T.

    2005-01-01

    Characterization and modeling of CMOS devices at 4.2 K are carried out in order to simulate low-temperature operation of CMOS circuits for Josephson-CMOS hybrid systems. CMOS devices examined in this study have been fabricated by using 0.18 mu m, 0.25 mu m, and 0.35 mu m commercial CMOS processes. Their static IN characteristics and capacitances are measured at 4.2 K to establish the low-temperature device model based on the BSIM3 SPICE model. The propagation delays of CMOS inverters measured...

  13. The impact of CMOS scaling projected on a 6b full-Nyquist non-calibrated flash ADC

    NARCIS (Netherlands)

    Veldhorst, Paul; Guksun, George; Annema, Anne-Johan; Nauta, Bram; Buter, Berry; Vertregt, Maarten

    2009-01-01

    A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performanc

  14. A fast large dynamic range shaping amplifier for particle detector front-end

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo [INFN-Sezione di Turin (Italy)]. E-mail: rivetti@to.infn.it; Delaurenti, Paolo [Dipartimento di Fisica Sperimentale-Universita di Turin (Italy)

    2007-03-01

    The paper describes a fast shaping amplifier with rail-to-rail output swing. The circuit is based on a CMOS operational amplifier with a class AB output stage. A baseline holder, incorporating a closed-loop unity gain buffer with slew rate limitation, performs the AC coupling with the preamplifier and guarantees a baseline shift smaller than 3 mV for unipolar output pulses of 3 V and 10 MHz rate.

  15. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  16. Design and Fabrication of a Monolithic Optoelectronic Integrated Circuit Chip Based on CMOS Compatible Technology

    Institute of Scientific and Technical Information of China (English)

    GUO Wei-Feng; ZHAO Yong; WANG Wan-Jun; SHAO Hai-Feng; YANG Jian-Yi; JIANG Xiao-Qing

    2012-01-01

    A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology.The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function.Test results show that the extinction ratio of the MZM is close to 20dB and the small-signal gain of the CMOS driving circuit is about 26.9dB.A 50m V 10 MHz sine wave signal is amplified by the driving circuit,and then drives the MZM successfully.%A monolithic optoelectronic integrated circuit chip on a silicon-on-insulator is designed and fabricated based on complementary metal oxide semiconductor compatible technology. The chip integrates an optical Mach-Zehnder modulator (MZM) and a CMOS driving circuit with the amplification function. Test results show that the extinction ratio of the MZM is close to 20 dB and the small-signal gain of the CMOS driving circuit is about 26.9dB. A 50mV 10MHz sine wave signal is amplified by the driving circuit, and then drives the MZM successfully.

  17. Breast Implants

    Science.gov (United States)

    ... Medical Procedures Implants and Prosthetics Breast Implants Breast Implants Share Tweet Linkedin Pin it More sharing options Linkedin Pin it Email Print Breast implants are medical devices that are implanted under the ...

  18. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Science.gov (United States)

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  19. Two stage dual gate MESFET monolithic gain control amplifier for Ka-band

    Science.gov (United States)

    Sokolov, V.; Geddes, J.; Contolatis, A.

    A monolithic two stage gain control amplifier has been developed using submicron gate length dual gate MESFETs fabricated on ion implanted material. The amplifier has a gain of 12 dB at 30 GHz with a gain control range of over 30 dB. This ion implanted monolithic IC is readily integrable with other phased array receiver functions such as low noise amplifiers and phase shifters.

  20. A low noise, low residial offset chopped amplifier for mixed level applications

    NARCIS (Netherlands)

    Sanduleanu, M.A.T.; van Tuijl, Adrianus Johannes Maria; Wassenaar, R.F.; Lammers, M.C.; Wallinga, Hans

    1998-01-01

    This paper describes the principle and the design of a CMOS low noise, low residual offset, chopped amplifier with a class AB output stage for noise and offset reduction in mixed analog digital applications. The operation is based on chopping and dynamic element matching to reduce noise and offset,

  1. An audio FIR-DAC in a BCD process for high power Class-D amplifiers

    NARCIS (Netherlands)

    Doorn, T.S.; Tuijl, van E.; Schinkel, D.; Annema, A.J.; Berkhout, M.; Nauta, B.

    2005-01-01

    A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant natur

  2. An audio FIR-DAC in a BCD process for high power Class-D amplifiers

    NARCIS (Netherlands)

    Doorn, T.S.; van Tuijl, Adrianus Johannes Maria; Schinkel, Daniel; Annema, Anne J.; Berkhout, M.; Berkhout, M.; Nauta, Bram

    A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant

  3. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  4. Portable design rules for bulk CMOS

    Science.gov (United States)

    Griswold, T. W.

    1982-01-01

    It is pointed out that for the past several years, one school of IC designers has used a simplified set of nMOS geometric design rules (GDR) which is 'portable', in that it can be used by many different nMOS manufacturers. The present investigation is concerned with a preliminary set of design rules for bulk CMOS which has been verified for simple test structures. The GDR are defined in terms of Caltech Intermediate Form (CIF), which is a geometry-description language that defines simple geometrical objects in layers. The layers are abstractions of physical mask layers. The design rules do not presume the existence of any particular design methodology. Attention is given to p-well and n-well CMOS processes, bulk CMOS and CMOS-SOS, CMOS geometric rules, and a description of the advantages of CMOS technology.

  5. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence, the proc......This paper presents a technique for batch fabrication of electrical feedthroughs in CMOS wafers. The presented process is designed with specific attention on industrial applicability. The electrical feedthroughs are processed entirely by low temperature, CMOS compatible processes. Hence....... The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...

  6. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  7. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  8. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  9. An Implantable Cardiovascular Pressure Monitoring System with On-Chip Antenna and RF Energy Harvesting

    Directory of Open Access Journals (Sweden)

    Yu-Chun Liu

    2015-08-01

    Full Text Available An implantable wireless system with on-chip antenna for cardiovascular pressure monitor is studied. The implantable device is operated in a batteryless manner, powered by an external radio frequency (RF power source. The received RF power level can be sensed and wirelessly transmitted along with blood pressure signal for feedback control of the external RF power. The integrated electronic system, consisting of a capacitance-to-voltage converter, an adaptive RF powering system, an RF transmitter and digital control circuitry, is simulated using a TSMC 0.18 μm CMOS technology. The implanted RF transmitter circuit is combined with a low power voltage-controlled oscillator resonating at 5.8 GHz and a power amplifier. For the design, the simulation model is setup using ADS and HFSS software. The dimension of the antenna is 1 × 0.6 × 4.8 mm3 with a 1 × 0.6 mm2 on-chip circuit which is small enough to place in human carotid artery.

  10. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  11. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  12. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  13. CMOS Law-jitter Clock Driver Design

    OpenAIRE

    2012-01-01

    [ANGLÈS] Design of a low-jitter, low-phase noise clock driver in 40 nm CMOS technology. The work is in the field of analog integrated circuit (IC) design in nanometer CMOS technologies. [CASTELLÀ] Diseño de un circuito integrado "clock driver" de bajo jitter y bajo ruido de fase en tecnología CMOS 40 nm. El trabajo se contextualiza en el campo del diseño de circuitos integrados analógicos en tecnologías CMOS nanométricas. [CATALÀ] Disseny d'un circuit "clock driver" de baix jitter i bai...

  14. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  15. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  16. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    赵士彬; 姚素英; 聂凯明; 徐江涛

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN) cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sampleand-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp) sharing is also introduced to decrease the power dissi...

  17. A low-noise current preamplifier in 120 nm CMOS technology

    Directory of Open Access Journals (Sweden)

    H. Uhrmann

    2008-05-01

    Full Text Available In this paper we examine the impact of deep sub-micron CMOS technology on analog circuit design with a special focus on the noise performance and the ability to design low-noise preamplifiers. To point out, why CMOS technology can grow to a key technology in low-noise and high-speed applications, various amplifier stages, applied in literature, are compared. One, that fits as a current preamplifier for low-noise applications, is the current mirror. Starting from the basic current mirror, an enhanced current preamplifier is developed, that offers low-noise and high-speed operation. The suggested chip is realized in 0.12 μm CMOS technology and needs a chip area of 100 μm×280 μm. It consumes about 15 mW at a supply voltage of 1.5 V. The presented current preamplifier has a bandwidth of 750 MHz and a gain of 36 dB. The fields of application for current preamplifiers are, for instance, charge amplifiers, amplifiers for low-voltage differential signaling (LVDS based point-to-point data links or preamplifiers for photodetectors.

  18. Low-power realization in main blocks of CMOS APS image sensor

    Science.gov (United States)

    Gao, Wei; Shen, Edward; Hornsey, Richard I.

    2005-09-01

    This paper addresses the optimization of power at the circuit level in the main blocks of CMOS APS image sensors. A pixel bias current of zero during the readout period is shown to reduce the static power and enhance the settling time of the pixel. A balanced operational transconductance amplifier (OTA) has been demonstrated to be a better candidate as an amplifier when employed in a correlated double sampling (CDS) circuit or as a comparator in an analog-to-digital (A/D) converter, as compared to a Miller two-stage amplifier. Using common-mode feedback (CMFB) in an OTA can further reduce the quiescent power of the amplifier. The low power capability of a CMFB OTA is discussed in this paper by performing a comparison with a conventional OTA using a 0.18 μm technology.

  19. Wireless Josephson amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Narla, A.; Sliwa, K. M.; Hatridge, M.; Shankar, S.; Frunzio, L.; Schoelkopf, R. J.; Devoret, M. H. [Department of Applied Physics, Yale University, New Haven, Connecticut 06511 (United States)

    2014-06-09

    Josephson junction parametric amplifiers are playing a crucial role in the readout chain in superconducting quantum information experiments. However, their integration with current 3D cavity implementations poses the problem of transitioning between waveguide, coax cables, and planar circuits. Moreover, Josephson amplifiers require auxiliary microwave components, like directional couplers and/or hybrids, that are sources of spurious losses and impedance mismatches that limit measurement efficiency and amplifier tunability. We have developed a wireless architecture for these parametric amplifiers that eliminates superfluous microwave components and interconnects. This greatly simplifies their assembly and integration into experiments. We present an experimental realization of such a device operating in the 9–11 GHz band with about 100 MHz of amplitude gain-bandwidth product, on par with devices mounted in conventional sample holders. The simpler impedance environment presented to the amplifier also results in increased amplifier tunability.

  20. Challenges of VDD scaling for analog circuits: an amplifier

    Science.gov (United States)

    Bargagli-Stoffi, A.; Sauerbrey, J.; Wang, J.; Schmitt-Landsiedel, D.

    2005-05-01

    With the shrinking of the device dimensions, the power supply voltage value is continuously decreasing. Since the threshold voltage value does not decrease as much as the power supply and the drain source saturation voltage becomes an important fraction of the power supply, many amplifier architectures are no more suitable for modern processes. A transconductance amplifier based on current mirrors is analyzed highlighting the main challenges of a low-voltage analog design. Among the many proposed amplifier architectures, a topology based on current mirrors has been chosen as the most promising to operate with low voltages. Simulations with 90nm CMOS prove the feasibility of circuit operation with satisfactory performance at an operating power supply voltage as low as 0.6V.

  1. Using MEMS Capacitive Switches in Tunable RF Amplifiers

    Directory of Open Access Journals (Sweden)

    Danson John

    2006-01-01

    Full Text Available A MEMS capacitive switch suitable for use in tunable RF amplifiers is described. A MEMS switch is designed, fabricated, and characterized with physical and RF measurements for inclusion in simulations. Using the MEMS switch models, a dual-band low-noise amplifier (LNA operating at GHz and GHz, and a tunable power amplifier (PA at GHz are simulated in m CMOS. MEMS switches allow the LNA to operate with 11 dB of isolation between the two bands while maintaining dB of gain and sub- dB noise figure. MEMS switches are used to implement a variable matching network that allows the PA to realize up to 37% PAE improvement at low input powers.

  2. Current feedback operational amplifiers and their applications

    CERN Document Server

    Senani, Raj; Singh, A K; Singh, V K

    2013-01-01

    This book describes a variety of current feedback operational amplifier (CFOA) architectures and their applications in analog signal processing/generation. Coverage includes a comprehensive survey of commercially available, off-the-shelf integrated circuit CFOAs, as well as recent advances made on the design of CFOAs, including design innovations for bipolar and CMOS CFOAs.  This book serves as a single-source reference to the topic, as well as a catalog of over 200 application circuits which would be useful not only for students, educators and researchers in apprising them about the recent developments in the area but would also serve as a comprehensive repertoire of useful circuits for practicing engineers who might be interested in choosing an appropriate CFOA-based topology for use in a given application.

  3. A digitally assisted, signal folding neural recording amplifier.

    Science.gov (United States)

    Chen, Yi; Basu, Arindam; Liu, Lei; Zou, Xiaodan; Rajkumar, Ramamoorthy; Dawe, Gavin Stewart; Je, Minkyu

    2014-08-01

    A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

  4. CMOS circuits for analog signal processing

    NARCIS (Netherlands)

    Wallinga, Hans

    1988-01-01

    Design choices in CMOS analog signal processing circuits are presented. Special attention is focussed on continuous-time filter technologies. The basics of MOSFET-C continuous-time filters and CMOS Square Law Circuits are explained at the hand of a graphical MOST characteristics representation.

  5. Oscillators and operational amplifiers

    DEFF Research Database (Denmark)

    Lindberg, Erik

    2005-01-01

    A generalized approach to the design of oscillators using operational amplifiers as active elements is presented. A piecewise-linear model of the amplifier is used so that it make sense to investigate the eigenvalues of the Jacobian of the differential equations. The characteristic equation...

  6. Penile Implants

    Science.gov (United States)

    ... the discussion with your doctor. Types of penile implants There are two main types of penile implants: ... might help reduce the risk of infection. Comparing implant types When choosing which type of penile implant ...

  7. Integration of solid-state nanopores in a 0.5 μm CMOS foundry process.

    Science.gov (United States)

    Uddin, A; Yemenicioglu, S; Chen, C-H; Corigliano, E; Milaninia, K; Theogarajan, L

    2013-04-19

    High-bandwidth and low-noise nanopore sensor and detection electronics are crucial in achieving single-DNA-base resolution. A potential way to accomplish this goal is to integrate solid-state nanopores within a CMOS platform, in close proximity to the biasing electrodes and custom-designed amplifier electronics. Here we report the integration of solid-state nanopore devices in a commercial complementary metal-oxide-semiconductor (CMOS) potentiostat chip implemented in On-Semiconductor's 0.5 μm technology. Nanopore membranes incorporating electrodes are fabricated by post-CMOS micromachining utilizing the n+ polysilicon/SiO2/n+ polysilicon capacitor structure available in the aforementioned process. Nanopores are created in the CMOS process by drilling in a transmission electron microscope and shrinking by atomic layer deposition. We also describe a batch fabrication method to process a large of number of electrode-embedded nanopores with sub-10 nm diameter across CMOS-compatible wafers by electron beam lithography and atomic layer deposition. The CMOS-compatibility of our fabrication process is verified by testing the electrical functionality of on-chip circuitry. We observe high current leakage with the CMOS nanopore devices due to the ionic diffusion through the SiO2 membrane. To prevent this leakage, we coat the membrane with Al2O3, which acts as an efficient diffusion barrier against alkali ions. The resulting nanopore devices also exhibit higher robustness and lower 1/f noise as compared to SiO2 and SiNx. Furthermore, we propose a theoretical model for our low-capacitance CMOS nanopore devices, showing good agreement with the experimental value. In addition, experiments and theoretical models of translocation studies are presented using 48.5 kbp λ-DNA in order to prove the functionality of on-chip pores coated with Al2O3.

  8. Analysis of the Noise Characteristics of CMOS Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1997-01-01

    The definition of the current conveyor is reviewed and a multiple-output second generation current conveyor (CCII) is shown to combine the different generations of current conveyors presently existing. Next, noise sources are introduced, and a general noise model for the current conveyor...... is described. This model is used for the analysis of selected examples of current conveyor based operational amplifier configurations and the noise performance of these configurations is compared. Finally, the noise model is developed for a CMOS current conveyor implementation, and approaches...... to an optimization of the noise performance are discussed. It is concluded that a class AB implementation can yield a lower noise output for the same dynamic range than a class A implementation. For both the class A implementation and the class AB implementation it is essential to design low noise current mirrors...

  9. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf; Kurt O.

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  10. Design Of High Performance CMOS Dynamic Latch Comparator

    Directory of Open Access Journals (Sweden)

    G.Saroja

    2016-10-01

    Full Text Available High performance analog to digital converters (ADC, memory sense amplifiers, and Radio Frequency identification applications, data receivers with less area and power efficient designs has attracted a broad range of dynamic comparators. This paper presents an ameliorate design for a dynamic latch based comparator in attaining high performance. The comparators accuracyis mainly defined by two factors they are speed and power consumption. The latch based comparator has two different stages encompassing of a dynamic differential input gain stage and an output latch.The output node in the differential gain stage of proposed comparator requires lesser time to regain higher charge potential. The proposed comparator hasbeen designed and simulated using 130nm CMOS 1P2M technology by using mentor graphics tools with a supply voltage of 1V. Proposed dynamic latch comparator iscompared with existing conventional dynamic latch comparator and with other comparators and the results are discussed in detail.

  11. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  12. Auto-Zero Differential Amplifier

    Science.gov (United States)

    Quilligan, Gerard T. (Inventor); Aslam, Shahid (Inventor)

    2017-01-01

    An autozero amplifier may include a window comparator network to monitor an output offset of a differential amplifier. The autozero amplifier may also include an integrator to receive a signal from a latched window comparator network, and send an adjustment signal back to the differential amplifier to reduce an offset of the differential amplifier.

  13. BiCMOS-integrated photodiode exploiting drift enhancement

    Science.gov (United States)

    Swoboda, Robert; Schneider-Hornstein, Kerstin; Wille, Holger; Langguth, Gernot; Zimmermann, Horst

    2014-08-01

    A vertical pin photodiode with a thick intrinsic layer is integrated in a 0.5-μm BiCMOS process. The reverse bias of the photodiode can be increased far above the circuit supply voltage, enabling a high-drift velocity. Therefore, a highly efficient and very fast photodiode is achieved. Rise/fall times down to 94 ps/141 ps at a bias of 17 V were measured for a wavelength of 660 nm. The bandwidth was increased from 1.1 GHz at 3 V to 2.9 GHz at 17 V due to the drift enhancement. A quantum efficiency of 85% with a 660-nm light was verified. The technological measures to avoid negative effects on an NPN transistor due to the Kirk effect caused by the low-doped I-layer epitaxy are described. With a high-energy collector implant, the NPN transit frequency is held above 20 GHz. CMOS devices are unaffected. This photodiode is suitable for a wide variety of high-sensitivity optical sensor applications, for optical communications, for fiber-in-the-home applications, and for optical interconnects.

  14. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-06-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-tech electronics industries from consumer products to telecommunications and computers. As CMOS technologies are scaled down into the nano meter range, analog and mixed integrated circuit (IC design and testing have become a real challenge to ensure the functionality and quality of the product. The first part of the paper presents the CMOS technology scaling impact on design and reliability for consumer and critical applications. We then propose a discussion on the role and challenges of testing analog and mixed devices in the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects of bridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistive path between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layout simulation results.

  15. A CMOS millimeter-wave transceiver embedded in a semi-confocal Fabry-Perot cavity for molecular spectroscopy

    Science.gov (United States)

    Drouin, Brian J.; Tang, Adrian; Schlecht, Erich; Brageot, Emily; Gu, Q. Jane; Ye, Y.; Shu, R.; Frank Chang, Mau-chung; Kim, Y.

    2016-08-01

    The extension of radio frequency complementary metal oxide semiconductor (CMOS) circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now beginning to use CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in situ detection of gas composition during space missions. We have chosen to develop a Flygare-Balle type spectrometer, with a semi-confocal Fabry-Perot cavity to amplify the pump power of a mm-wavelength CMOS transmitter that is directly coupled to the planar mirror of the cavity. We have built a pulsed transceiver system at 92-105 GHz inside a 3 cm base length cavity and demonstrated quality factor up to 4680, allowing for modes with 20 MHz bandwidth, with a sufficient cavity amplification factor for mW class transmitters. This work describes the initial gas measurements and outlines the challenges and next steps.

  16. A CMOS millimeter-wave transceiver embedded in a semi-confocal Fabry-Perot cavity for molecular spectroscopy.

    Science.gov (United States)

    Drouin, Brian J; Tang, Adrian; Schlecht, Erich; Brageot, Emily; Gu, Q Jane; Ye, Y; Shu, R; Frank Chang, Mau-Chung; Kim, Y

    2016-08-21

    The extension of radio frequency complementary metal oxide semiconductor (CMOS) circuitry into millimeter wavelengths promises the extension of spectroscopic techniques in compact, power efficient systems. We are now beginning to use CMOS millimeter devices for low-mass, low-power instrumentation capable of remote or in situ detection of gas composition during space missions. We have chosen to develop a Flygare-Balle type spectrometer, with a semi-confocal Fabry-Perot cavity to amplify the pump power of a mm-wavelength CMOS transmitter that is directly coupled to the planar mirror of the cavity. We have built a pulsed transceiver system at 92-105 GHz inside a 3 cm base length cavity and demonstrated quality factor up to 4680, allowing for modes with 20 MHz bandwidth, with a sufficient cavity amplification factor for mW class transmitters. This work describes the initial gas measurements and outlines the challenges and next steps.

  17. Integrated RF MEMS/CMOS Devices

    CERN Document Server

    Mansour, R R; Bakeri-Kassem, M

    2008-01-01

    A maskless post-processing technique for CMOS chips is developed that enables the fabrication of RF MEMS parallel-plate capacitors with a high quality factor and a very compact size. Simulations and measured results are presented for several MEMS/CMOS capacitors. A 2-pole coupled line tunable bandpass filter with a center frequency of 9.5 GHz is designed, fabricated and tested. A tuning range of 17% is achieved using integrated variable MEMS/CMOS capacitors with a quality factor exceeding 20. The tunable filter occupies a chip area of 1.2 x 2.1 mm2.

  18. Spectrometry with consumer-quality CMOS cameras.

    Science.gov (United States)

    Scheeline, Alexander

    2015-01-01

    Many modern spectrometric instruments use diode arrays, charge-coupled arrays, or CMOS cameras for detection and measurement. As portable or point-of-use instruments are desirable, one would expect that instruments using the cameras in cellular telephones and tablet computers would be the basis of numerous instruments. However, no mass market for such devices has yet developed. The difficulties in using megapixel CMOS cameras for scientific measurements are discussed, and promising avenues for instrument development reviewed. Inexpensive alternatives to use of the built-in camera are also mentioned, as the long-term question is whether it is better to overcome the constraints of CMOS cameras or to bypass them.

  19. Nanopore-CMOS Interfaces for DNA Sequencing.

    Science.gov (United States)

    Magierowski, Sebastian; Huang, Yiyun; Wang, Chengjie; Ghafar-Zadeh, Ebrahim

    2016-08-06

    DNA sequencers based on nanopore sensors present an opportunity for a significant break from the template-based incumbents of the last forty years. Key advantages ushered by nanopore technology include a simplified chemistry and the ability to interface to CMOS technology. The latter opportunity offers substantial promise for improvement in sequencing speed, size and cost. This paper reviews existing and emerging means of interfacing nanopores to CMOS technology with an emphasis on massively-arrayed structures. It presents this in the context of incumbent DNA sequencing techniques, reviews and quantifies nanopore characteristics and models and presents CMOS circuit methods for the amplification of low-current nanopore signals in such interfaces.

  20. Harmonic Distortion in CMOS Current Mirrors

    DEFF Research Database (Denmark)

    Bruun, Erik

    1998-01-01

    One of the origins of harmonic distortion in CMOS current mirrors is the inevitable mismatch between the MOS transistors involved. In this paper we examine both single current mirrors and complementary class AB current mirrors and develop an analytical model for the mismatch induced harmonic...... distortion. This analytical model is verified through simulations and is used for a discussion of the impact of mismatch on harmonic distortion properties of CMOS current mirrors. It is found that distortion levels somewhat below 1% can be attained by carefully matching the mirror transistors but ultra low...... distortion is not achievable with CMOS current mirrors...

  1. Bridging faults in BiCMOS circuits

    Science.gov (United States)

    Menon, Sankaran M.; Malaiya, Yashwant K.; Jayasumana, Anura P.

    1993-01-01

    Combining the advantages of CMOS and bipolar, BiCMOS is emerging as a major technology for many high performance digital and mixed signal applications. Recent investigations revealed that bridging faults can be a major failure mode in IC's. Effects of bridging faults in BiCMOS circuits are presented. Bridging faults between logical units without feedback and logical units with feedback are considered. Several bridging faults can be detected by monitoring the power supply current (I(sub DDQ) monitoring). Effects of bridging faults and bridging resistance on output logic levels were examined along with their effects on noise immunity.

  2. Carbon Nanotube Integration with a CMOS Process

    OpenAIRE

    Perez, Maximiliano S.; Betiana Lerner; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Pedro M. Julian; Pablo S. Mandolesi; Fabian A. Buffa; Alfredo Boselli; Alberto Lamagna

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new rout...

  3. Carbon nanotube integration with a CMOS process.

    Science.gov (United States)

    Perez, Maximiliano S; Lerner, Betiana; Resasco, Daniel E; Pareja Obregon, Pablo D; Julian, Pedro M; Mandolesi, Pablo S; Buffa, Fabian A; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  4. Carbon Nanotube Integration with a CMOS Process

    Directory of Open Access Journals (Sweden)

    Maximiliano S. Perez

    2010-04-01

    Full Text Available This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture.

  5. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  6. Optoisolators simplify amplifier design

    Science.gov (United States)

    Ting, Joseph Wee

    2007-09-01

    Simplicity and low parts count are key virtues to this high voltage amplifier. Optoisolators replace complex high voltage transistor biasing schemes. This amplifier employs only 2 optoisolators, 16 high voltage mosfets transistors, 2 low voltage ones, 6 linear IC's and a score of passive components. Yet it can amplify opamp signals to 5 kV peak-to-peak from DC to sine waves up to 20 kHz. Resistor feedback guarantees the fidelity of the signal. It can source and sink 10 mA of output current. This amplifier was conceived to power ion traps for biological whole cell mass measurements. It is a versatile tool for a variety of applications.

  7. A combined noise analysis and power supply current based testing of CMOS analog integrated circuits

    Science.gov (United States)

    Srivastava, Ashok; Pulendra, Vani K.; Yellampalli, Siva

    2005-05-01

    A technique integrating the noise analysis based testing and the conventional power supply current testing of CMOS analog integrated circuits is presented for bridging type faults due to manufacturing defects. The circuit under test (CUT) is a CMOS amplifier designed for operation at +/- 2.5 V and implemented in 1.5 μm CMOS process. The faults simulating possible manufacturing defects have been introduced using the fault injection transistors. The amplifier circuit is analyzed and simulated in SPICE for its performance with and without fault injections. The faults in the CUT are identified by observing the variation in the equivalent noise voltage at the output of CUT. In power supply current testing, the current (IPS) through the power supply voltage, VDD is measured under the application of an AC input stimulus. The effect of parametric variation is taken into consideration by determining the tolerance limit using the Monte-Carlo analysis. The fault is identified if the power supply current, IPS lies outside the deviation given by Monte-Carlo analysis. Simulation results are in close agreement with the corresponding experimental values.

  8. Design of Low-Power CMOS OTA Using Bulk-Drive Technique

    Directory of Open Access Journals (Sweden)

    Maryam Ghadiri Modarres

    2015-10-01

    Full Text Available This paper presents the design of low power CMOS- OTA (operational transconductance amplifier using bulk drive (BD technique with broad band. This technique is used for design of low power circuits with broad band for high frequency users, for example communication systems, mobile communication and communication forming of medical electronics. OTA is the base of amplifier .It is a fundamental building part of analog systems. Recently analog designer has been paid to low voltage (LV,low power (LP integrated circuits. Many techniques are used for the design of LV LP circuits, the bulk driven offers principle this designs. This paper suggests a bulk driven OTA in standard CMOS processes and supply voltage 0.8 volt DC. It used of improved wilson current mirror. The simulation results have been carried out by the HSPICE simulator in 180 nm CMOS technology. The open loop gain is enhanced to 17.4dB at unity gain band with (UGB of 26.1 MHZ with sufficient output swing. Power consumption of the OTA is in range of few hundreds of nanowatts (6%.

  9. Low noise CMOS readout for CdZnTe detector arrays

    Energy Technology Data Exchange (ETDEWEB)

    Jakobson, C.G.; Asa, G.; Lev, S. Bar; Nemirovsky, Y. E-mail: nemirov@ee.technion.ac.il

    1999-06-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 {mu}m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing function incorporated in the shaper provides low power and reduces chip area. The system is partitioned into a chip containing the charge amplifiers and a chip containing the semi-Gaussian pulse shaper and multiplexer. This architecture minimizes coupling from multiplexer switches as well as shaper output to the input of the charge sensitive preamplifiers.

  10. Integrated on-chip 0.35 μm BiCMOS current-mode DC-DC buck converter

    Science.gov (United States)

    Lee, Chan-Soo; Kim, Nam-Soo; Gendensuren, Munkhsuld; Choi, Jae-Ho; Choi, Joong-Ho

    2012-12-01

    A current-mode DC-DC buck converter with a fully integrated power module is presented in this article. The converter is implemented using BiCMOS technology in amplifier and power MOSFET in a current sensor. The current sensor is realised by the power lateral double-diffused MOSFET with the aspect ratio much larger than that of a matched p-MOSFET. In addition, BiCMOS technology is applied in the error amplifier for an accurate current sensing and a fast transient response. The DC-DC converter is fabricated with 0.35 µm BiCMOS process. Experimental results show that the fully integrated converter operates at 1.3 MHz switching frequency with a supply voltage of 5 V. The output DC voltage is obtained as expected and the output ripple is controlled to be within 2% with a 30 µH off-chip inductor and 100 µF off-chip capacitor.

  11. Charge-sensitive amplifier

    Directory of Open Access Journals (Sweden)

    Startsev V. I.

    2008-02-01

    Full Text Available The authors consider design and circuit design techniques of reduction of the influence of the pyroelectric effect on operation of the charge sensitive amplifiers. The presented experimental results confirm the validity of the measures taken to reduce the impact of pyroelectric currents. Pyroelectric currents are caused by the influence of the temperature gradient on the piezoelectric sensor and on the output voltage of charge sensitive amplifiers.

  12. RF Power Amplifier Analysis

    Directory of Open Access Journals (Sweden)

    M. Lokay

    1993-04-01

    Full Text Available The special program is presented for the demonstration of RF power transistor amplifiers for the purposes of the high-school education in courses of radio transmitters. The program is written in Turbo Pascal 6. 0 and enables to study the waveforms in selected points of the amplifier and to draw the trajectories of the working point in a plot of output transistor characteristics.

  13. OFCC based voltage and transadmittance mode instrumentation amplifier

    Science.gov (United States)

    Nand, Deva; Pandey, Neeta; Pandey, Rajeshwari; Tripathi, Prateek; Gola, Prashant

    2017-07-01

    The operational floating current conveyor (OFCC) is a versatile active block due to the availability of both low and high input and output impedance terminals. This paper addresses the realization of OFCC based voltage and transadmittance mode instrumentation amplifiers (VMIA and TAM IA). It employs three OFCCs and seven resistors. The transadmittance mode operation can easily be obtained by simply connecting an OFCC based voltage to current converter at the output. The effect of non-idealities of OFCC, in particular finite transimpedance and tracking error, on system performance is also dealt with and corresponding mathematical expressions are derived. The functional verification is performed through SPICE simulation using CMOS based implementation of OFCC.

  14. Analog CMOS contrastive Hebbian networks

    Science.gov (United States)

    Schneider, Christian; Card, Howard

    1992-09-01

    CMOS VLSI circuits implementing an analog neural network with on-chip contrastive Hebbian learning and capacitive synaptic weight storage have been designed and fabricated. Weights are refreshed by periodic repetition of the training data. To evaluate circuit performance in a medium-sized system, these circuits were used to build a 132 synapse neural network. An adaptive neural system, such as the one described in this paper, can compensate for imperfections in the components from which it is constructed, and thus it is possible to build this type of system using simple, silicon area-efficient analog circuits. Because these analog VLSI circuits are far more compact than their digital counterparts, analog VLSI neural network implementations are potentially more efficient than digital ones.

  15. Ultralow-loss CMOS copper plasmonic waveguides

    DEFF Research Database (Denmark)

    Fedyanin, Dmitry Yu.; Yakubovsky, Dmitry I.; Kirtaev, Roman V.

    2016-01-01

    with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which...

  16. CMOS circuits for passive wireless microsystems

    CERN Document Server

    Yuan, Fei

    2011-01-01

    Here is a comprehensive examination of CMOS circuits for passive wireless microsystems. Covers design challenges, fundamental issues of ultra-low power wireless communications, radio-frequency power harvesting, and advanced design techniques, and more.

  17. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  18. Depletion-mode carrier-plasma optical modulator in zero-change advanced CMOS.

    Science.gov (United States)

    Shainline, Jeffrey M; Orcutt, Jason S; Wade, Mark T; Nammari, Kareem; Moss, Benjamin; Georgas, Michael; Sun, Chen; Ram, Rajeev J; Stojanović, Vladimir; Popović, Miloš A

    2013-08-01

    We demonstrate the first (to the best of our knowledge) depletion-mode carrier-plasma optical modulator fabricated in a standard advanced complementary metal-oxide-semiconductor (CMOS) logic process (45 nm node SOI CMOS) with no process modifications. The zero-change CMOS photonics approach enables this device to be monolithically integrated into state-of-the-art microprocessors and advanced electronics. Because these processes support lateral p-n junctions but not efficient ridge waveguides, we accommodate these constraints with a new type of resonant modulator. It is based on a hybrid microring/disk cavity formed entirely in the sub-90 nm thick monocrystalline silicon transistor body layer. Electrical contact of both polarities is made along the inner radius of the multimode ring cavity via an array of silicon spokes. The spokes connect to p and n regions formed using transistor well implants, which form radially extending lateral junctions that provide index modulation. We show 5 Gbps data modulation at 1265 nm wavelength with 5.2 dB extinction ratio and an estimated 40 fJ/bit energy consumption. Broad thermal tuning is demonstrated across 3.2 THz (18 nm) with an efficiency of 291 GHz/mW. A single postprocessing step to remove the silicon handle wafer was necessary to support low-loss optical confinement in the device layer. This modulator is an important step toward monolithically integrated CMOS photonic interconnects.

  19. CMOS Compatible Ultra-Compact Modulator

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.

    2014-01-01

    A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss <1dB at telecommunication wavelengths.......A planar layout for an ultra-compact plasmonic modulator is proposed and numerically investigated. Our device utilizes potentially CMOS compatible materials and can achieve 3-dB modulation in just 65nm and insertion loss

  20. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  1. A dynamic CMOS multiplier for analog VLSI based on exponential pulse-decay modulation

    Science.gov (United States)

    Massengill, Lloyd W.

    1991-03-01

    A clocked, charge-based, CMOS modulator circuit is presented. The circuit, which performs a semilinear multiplication function, has applications in arrayed analog VLSI architectures such as parallel filters and neural network systems. The design presented is simple in structure, uses no operational amplifiers for the actual multiplication function, and uses no power in the static mode. Two-quadrant weighting of an input signal is accomplished by control of the magnitude and decay time of an exponential current pulse, resulting in the delivery of charge packets to a shared capacitive summing bus. The cell is modular in structure and can be fabricated in a standard CMOS process. An analytical derivation of the operation of the circuit, SPICE simulations, and MOSIS fabrication results are presented. The simulation studies indicate that the circuit is inherently tolerant to temperature effects, absolute device sizing errors, and clock-feedthrough transients.

  2. A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering

    Science.gov (United States)

    Lioe, DeXing; Mars, Kamel; Takasawa, Taishi; Yasutomi, Keita; Kagawa, Keiichiro; Hashimoto, Mamoru; Kawahito, Shoji

    2016-03-01

    A CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering (SRS) spectroscopy is presented in this paper. The effective SRS signal from the stimulated emission of SRS mechanism is very small in contrast to the offset of a probing laser source, which is in the ratio of 10-4 to 10-5. In order to extract this signal, the common offset component is removed, and the small difference component is sampled using switched-capacitor integrator with a fully differential amplifier. The sampling is performed over many integration cycles to achieve appropriate amplification. The lock-in pixels utilizes high-speed lateral electric field charge modulator (LEFM) to demodulate the SRS signal which is modulated at high-frequency of 20MHz. A prototype chip is implemented using 0.11μm CMOS image sensor technology.

  3. Electrospun amplified fiber optics.

    Science.gov (United States)

    Morello, Giovanni; Camposeo, Andrea; Moffa, Maria; Pisignano, Dario

    2015-03-11

    All-optical signal processing is the focus of much research aiming to obtain effective alternatives to existing data transmission platforms. Amplification of light in fiber optics, such as in Erbium-doped fiber amplifiers, is especially important for efficient signal transmission. However, the complex fabrication methods involving high-temperature processes performed in a highly pure environment slow the fabrication process and make amplified components expensive with respect to an ideal, high-throughput, room temperature production. Here, we report on near-infrared polymer fiber amplifiers working over a band of ∼20 nm. The fibers are cheap, spun with a process entirely carried out at room temperature, and shown to have amplified spontaneous emission with good gain coefficients and low levels of optical losses (a few cm(-1)). The amplification process is favored by high fiber quality and low self-absorption. The found performance metrics appear to be suitable for short-distance operations, and the large variety of commercially available doping dyes might allow for effective multiwavelength operations by electrospun amplified fiber optics.

  4. Four-quadrant analogue multiplier using operational amplifier

    Science.gov (United States)

    Riewruja, Vanchai; Rerkratn, Apinai

    2011-04-01

    A method to realise a four-quadrant analogue multiplier using general-purpose operational amplifiers (opamps) as only the active elements is described in this article. The realisation method is based on the quarter-square technique, which utilises the inherent square-law characteristic of class AB output stage of the opamp. The multiplier can be achieved from the proposed structure with using either bipolar or complementary metal-oxide-semiconductor (CMOS) opamps. The operation principle of the proposed multiplier has been confirmed by PSPICE analogue simulation program. Simulation results reveal that the principle of proposed scheme provides an adequate performance for a four-quadrant analogue multiplier. Experimental implementations of the proposed multiplier using bipolar and CMOS opamps are performed to verify the circuit performances. Measured results of the experimental proposed schemes based on the use of bipolar and CMOS opamps with supply voltage ±2.4 V show the worst-case relative errors of 0.32% and 0.47%, and the total harmonic distortions of 0.47% and 0.98%, respectively.

  5. A Novel Frequency Compensation Technique for Three-Stage Amplifier

    Institute of Scientific and Technical Information of China (English)

    LI Qiang; YI Jun; LI Zhao-ji; ZHANG Bo; FANG Jian; LUO Ping

    2005-01-01

    A novel frequency compensation technique for three-stage amplifier with dual complex pole-zero (DCP) cancellation is proposed. It uses one pair of complex zeros to cancel one pair of complex poles, resulting in feature that frequency response of the three-stage amplifier exhibits that of a single-pole system. Thus the gain-bandwidth (GBW) is expected to be increased several times compared to the conventional nested miller compensation (NMC) approach. Moreover, this technique requires only one very small compensation capacitor even when driving a big load capacitor. A GBW 4.63 MHz, DC gain 100 dB, PM 90o and power dissipation 0.87 mW can be achieved for a load capacitor 100 pF with a single Miller compensation capacitor 2 pF at a ±1V supply in a standard 0.6-μm CMOS technology.

  6. Design of an operational transconductance amplifier applying multiobjective optimization techniques

    Directory of Open Access Journals (Sweden)

    Roberto Pereira-Arroyo

    2014-02-01

    Full Text Available In this paper, the problem at hand consists in the sizing of an Operational Transconductance Amplifier (OTA. The Pareto front is introduced as a useful analysis concept in order to explore the design space of such analog circuit. A genetic algorithm (GA is employed to automatically detect this front in a process that efficiently finds optimal parameteriza­tions and their corresponding values in an aggregate fitness space. Since the problem is treated as a multi-objective optimization task, different measures of the amplifier like the transconductance, the slew rate, the linear range and the input capacitance are used as fitness functions. Finally, simulation results are pre­sented, using a standard 0,5μm CMOS technology.

  7. Dental Implants.

    Science.gov (United States)

    Griggs, Jason A

    2017-10-01

    Systematic reviews of literature over the period between 2008 and 2017 are discussed regarding clinical evidence for the factors affecting survival and failure of dental implants. The factors addressed include publication bias, tooth location, insertion torque, collar design, implant-abutment connection design, implant length, implant width, bone augmentation, platform switching, surface roughness, implant coatings, and the use of ceramic materials in the implant body and abutment. Copyright © 2017 Elsevier Inc. All rights reserved.

  8. Electroabsorption modulators for CMOS compatible optical interconnects in III-V and group IV materials

    Science.gov (United States)

    Roth, Jonathan Edgar

    device is compatible with both the voltage swing of modern CMOS circuits, and long-distance telecommunications technologies including low-loss optical fiber and erbium-doped fiber amplifiers.

  9. A CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging

    Science.gov (United States)

    Li, Zhuo; Yasutomi, Keita; Takasawa, Taishi; Itoh, Shinya; Kawahito, Shoji

    2011-03-01

    Fluorescence lifetime imaging is becoming a powerful tool in biology. A charge-domain CMOS Fluorescence Lifetime Imaging Microscopy (FLIM) chip using a pinned photo diode (PPD) and the pinned storage diode (PSD) with different depth of potential wells has been previously developed by the authors. However, a transfer gate between PPD and PSD causes charge transfer noise due to traps at the channel surface. This paper presents a time-resolved CMOS image sensor with draining only modulation pixels for fluorescence lifetime imaging, which removes the transfer gate between PPD and PSD. The time windowing is done by draining with a draining gate only, which is attached along the carrier path from PPD to PSD. This allows us to realize a trapping less charge transfer between PPD and PSD, leading to a very low-noise time-resolved signal detection. A video-rate CMOS FLIM chip has been fabricated using 0.18μm standard CMOS pinned diode image sensor process. The pixel consists of a PPD, a PSD, a charge draining gate (TD), a readout transfer gate (TX) between the PSD and the floating diffusion (FD), a reset transistor and a source follower amplifier transistor. The pixel array has 200(Row) x 256(Column) pixels and the pixel pitch is 7.5μm. Fundamental characteristics of the implemented CMOS FLIM chip are measured. The signal intensity of the PSD as a function of the TD gate voltage is also measured. The ratio of the signal for the TD off to the signal for the TD on is 212 : 1.

  10. A CURRENT MIRROR BASED TWO STAGE CMOS CASCODE OP-AMP FOR HIGH FREQUENCY APPLICATION

    Directory of Open Access Journals (Sweden)

    RAMKRISHNA KUNDU

    2017-03-01

    Full Text Available This paper presents a low power, high slew rate, high gain, ultra wide band two stage CMOS cascode operational amplifier for radio frequency application. Current mirror based cascoding technique and pole zero cancelation technique is used to ameliorate the gain and enhance the unity gain bandwidth respectively, which is the novelty of the circuit. In cascading technique a common source transistor drive a common gate transistor. The cascoding is used to enhance the output resistance and hence improve the overall gain of the operational amplifier with less complexity and less power dissipation. To bias the common gate transistor, a current mirror is used in this paper. The proposed circuit is designed and simulated using Cadence analog and digital system design tools of 45 nanometer CMOS technology. The simulated results of the circuit show DC gain of 63.62 dB, unity gain bandwidth of 2.70 GHz, slew rate of 1816 V/µs, phase margin of 59.53º, power supply of the proposed operational amplifier is 1.4 V (rail-to-rail ±700 mV, and power consumption is 0.71 mW. This circuit specification has encountered the requirements of radio frequency application.

  11. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Meier, Christian; Csaba, György; Breitkreutz-von Gamm, Stephan

    2017-05-01

    Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF) receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz) signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA). Then, it is down-converted by a mixer to Intermediate Frequency (IF). Finally, an Operational Amplifier (OpAmp) brings the IF signal to higher voltages (50-300 mV). The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO) is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  12. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  13. A digitally controlled power amplifier with neutralization capacitors for Zigbee™ applications

    Science.gov (United States)

    Fei, Jia; Shengxi, Diao; Xuejuan, Zhang; Zhongqian, Fu; Fujiang, Lin

    2012-12-01

    This paper presents a single chip CMOS power amplifier with neutralization capacitors for Zigbee™ system according to IEEE 802.15.4. A novel structure with digital interface is adopted, which allows the output power of a PA to be controlled by baseband signal directly, so there is no need for DAC. The neutralization capacitors will increase reverse isolation. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed power amplifier has a 13.5 dB power gain, 3.48 dBm output power and 35.1% PAE at P1dB point. The core area is 0.73 × 0.55 mm2.

  14. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  15. New package for CMOS sensors

    Science.gov (United States)

    Diot, Jean-Luc; Loo, Kum Weng; Moscicki, Jean-Pierre; Ng, Hun Shen; Tee, Tong Yan; Teysseyre, Jerome; Yap, Daniel

    2004-02-01

    Cost is the main drawback of existing packages for C-MOS sensors (mainly CLCC family). Alternative packages are thus developed world-wide. And in particular, S.T.Microelectronics has studied a low cost alternative packages based on QFN structure, still with a cavity. Intensive work was done to optimize the over-molding operation forming the cavity onto a metallic lead-frame (metallic lead-frame is a low cost substrate allowing very good mechanical definition of the final package). Material selection (thermo-set resin and glue for glass sealing) was done through standard reliability tests for cavity packages (Moisture Sensitivity Level 3 followed by temperature cycling, humidity storage and high temperature storage). As this package concept is new (without leads protruding the molded cavity), the effect of variation of package dimensions, as well as board lay-out design, are simulated on package life time (during temperature cycling, thermal mismatch between board and package leads to thermal fatigue of solder joints). These simulations are correlated with an experimental temperature cycling test with daisy-chain packages.

  16. Design of a Tunable All-Digital UWB Pulse Generator CMOS Chip for Wireless Endoscope.

    Science.gov (United States)

    Chul Kim; Nooshabadi, S

    2010-04-01

    A novel tunable all-digital, ultrawideband pulse generator (PG) has been implemented in a standard 0.18-¿ m complementary metal-oxide semiconductor (CMOS) process for implantable medical applications. The chip shows that an ultra-low dynamic energy consumption of 27 pJ per pulse without static current flow at a 200-MHz pulse repetition frequency (PRF) with a 1.8-V power supply and low area of 90 × 50 ¿m(2). The PG generates tunable pulsewidth, amplitude, and transmit (Tx) power by using simple circuitry, through precise timing control of the H-bridge output stage. The all-digital architecture allows easy integration into a standard CMOS process, thus making it the most suitable candidate for in-vivo biotelemetry applications.

  17. Analysis of incomplete charge transfer effects in a CMOS image sensor

    Institute of Scientific and Technical Information of China (English)

    Han Liqiang; Yao Suying; Xu Jiangtao; Xu Chao; Gao Zhiyuan

    2013-01-01

    A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size.Based on the emission current theory,a qualitative photoresponse model is established to the preliminary prediction.Further analysis of noise for incomplete charge transfer predicts the noise variation.The test pixels were fabricated in a specialized 0.18μm CMOS image sensor process and two different processes of buried N layer implantation are compared.The trend prediction corresponds with the test results,especially as it can distinguish an unobvious incomplete charge transfer.The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.

  18. Fourier plane image amplifier

    Science.gov (United States)

    Hackel, L.A.; Hermann, M.R.; Dane, C.B.; Tiszauer, D.H.

    1995-12-12

    A solid state laser is frequency tripled to 0.3 {micro}m. A small portion of the laser is split off and generates a Stokes seed in a low power oscillator. The low power output passes through a mask with the appropriate hole pattern. Meanwhile, the bulk of the laser output is focused into a larger stimulated Brillouin scattering (SBS) amplifier. The low power beam is directed through the same cell in the opposite direction. The majority of the amplification takes place at the focus which is the fourier transform plane of the mask image. The small holes occupy large area at the focus and thus are preferentially amplified. The amplified output is now imaged onto the multichip module where the holes are drilled. Because of the fourier plane amplifier, only about 1/10th the power of a competitive system is needed. This concept allows less expensive masks to be used in the process and requires much less laser power. 1 fig.

  19. Fourier plane image amplifier

    Science.gov (United States)

    Hackel, Lloyd A.; Hermann, Mark R.; Dane, C. Brent; Tiszauer, Detlev H.

    1995-01-01

    A solid state laser is frequency tripled to 0.3 .mu.m. A small portion of the laser is split off and generates a Stokes seed in a low power oscillator. The low power output passes through a mask with the appropriate hole pattern. Meanwhile, the bulk of the laser output is focused into a larger stimulated Brillouin scattering (SBS) amplifier. The low power beam is directed through the same cell in the opposite direction. The majority of the amplification takes place at the focus which is the fourier transform plane of the mask image. The small holes occupy large area at the focus and thus are preferentially amplified. The amplified output is now imaged onto the multichip module where the holes are drilled. Because of the fourier plane amplifier, only .about.1/10th the power of a competitive system is needed. This concept allows less expensive masks to be used in the process and requires much less laser power.

  20. Design and Experimental Evaluation of a 3rd Generation Addressable CMOS Piezoresistive Stress Sensing Test Chip

    Energy Technology Data Exchange (ETDEWEB)

    Sweet, J.N.; Peterson, D.W.; Hsia, A.H.

    1999-04-13

    Piezoresistive stress sensing chips have been used extensively for measurement of assembly related die surface stresses. Although many experiments can be performed with resistive structures which are directly bonded, for extensive stress mapping it is necessary to have a large number of sensor cells which can be addressed using CMOS logic circuitry. Our previous test chip, the ATC04, has 100 cells, each approximately 0.012 in. on a side, on a chip with a side dimension of 0.45 in. When a cell resistor is addressed, it is connected to a four terminal measurement bus through CMOS transmission gates. In theory, the gate resistances do not affect the measurement. In practice, there may be subtle effects which appear when very high accuracy is required. At high temperatures, gate leakage can increase to a point at which the resistor measurement becomes inaccurate. For ATC04 this occurred at or above 50 C. Here, we report on the first measurements obtained with a new prototype test chip, the ATC06. This prototype was fabricated in a 0.5 micron feature size silicided CMOS process using the MOSIS prototyping facility. The cell size was approximately 0.004 in. on a side. In order to achieve piezoresistive behavior for the implanted resistors it was necessary to employ a non-standard silicide ''blocking'' process. The stress sensitivity of both implanted and polysilicon blocked resistors is discussed. Using a new design strategy for the CMOS logic, it was possible to achieve a design in which only 5 signals had to be routed to a cell for addressing vs. 9 for ATC04. With our new design, the resistor under test is more effectively electrically isolated from other resistors on the chip, thereby improving high temperature performance. We present data showing operation up to 140 C.

  1. Packaging commercial CMOS chips for lab on a chip integration.

    Science.gov (United States)

    Datta-Chaudhuri, Timir; Abshire, Pamela; Smela, Elisabeth

    2014-05-21

    Combining integrated circuitry with microfluidics enables lab-on-a-chip (LOC) devices to perform sensing, freeing them from benchtop equipment. However, this integration is challenging with small chips, as is briefly reviewed with reference to key metrics for package comparison. In this paper we present a simple packaging method for including mm-sized, foundry-fabricated dies containing complementary metal oxide semiconductor (CMOS) circuits within LOCs. The chip is embedded in an epoxy handle wafer to yield a level, large-area surface, allowing subsequent photolithographic post-processing and microfluidic integration. Electrical connection off-chip is provided by thin film metal traces passivated with parylene-C. The parylene is patterned to selectively expose the active sensing area of the chip, allowing direct interaction with a fluidic environment. The method accommodates any die size and automatically levels the die and handle wafer surfaces. Functionality was demonstrated by packaging two different types of CMOS sensor ICs, a bioamplifier chip with an array of surface electrodes connected to internal amplifiers for recording extracellular electrical signals and a capacitance sensor chip for monitoring cell adhesion and viability. Cells were cultured on the surface of both types of chips, and data were acquired using a PC. Long term culture (weeks) showed the packaging materials to be biocompatible. Package lifetime was demonstrated by exposure to fluids over a longer duration (months), and the package was robust enough to allow repeated sterilization and re-use. The ease of fabrication and good performance of this packaging method should allow wide adoption, thereby spurring advances in miniaturized sensing systems.

  2. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  3. Detailed study of particle detectors OTA-based CMOS Semi-Gaussian shapers

    Science.gov (United States)

    Noulis, T.; Deradonis, C.; Siskos, S.; Sarrabayrouse, G.

    2007-12-01

    An analysis of readout front-end electronics Semi-Gaussian (S-G) shapers is carried out. An innovative design methodology is proposed and advanced filter design techniques based on Operational Transconductance Amplifiers (OTA) are used. Five CMOS shaper topologies are designed using OTAs and compared in terms of noise performance, total harmonic distortion, dynamic range and power consumption in order to examine which is the most preferable in readout applications. Although all shaper architectures are fully integrated, they exhibit a large peaking time. The results are obtained from SPICE simulations for implementations in a 0.6 μm process of Austria Mikro Systeme (AMS).

  4. A high-speed CMOS current op amp for very low supply voltage operation

    DEFF Research Database (Denmark)

    Bruun, Erik

    1994-01-01

    A CMOS implementation of a high-gain current mode operational amplifier (op amp) with a single-ended input and a differential output is described. This configuration is the current mode counterpart of the traditional voltage mode op amp. In order to exploit the inherent potential for high speed......, low voltage operation normally associated with current mode analog signal processing, the op amp has been designed to operate off a supply voltage of 1.5 V, and the signal path has been confined to N-channel transistors. With this design, a gain of 94 dB and a gain-bandwidth product of 65 MHz has been...

  5. Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

    Directory of Open Access Journals (Sweden)

    D. Arbet

    2014-09-01

    Full Text Available In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC based on digitally compensated input offset of the operational amplifier (OPAMP is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.

  6. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  7. Linearization and efficiency enhancement techniques for silicon power amplifiers from RF to mmW

    CERN Document Server

    Kerhervé, Eric

    2015-01-01

    This book provides an overview of current efficiency enhancement and linearization techniques for silicon power amplifier designs. It examines the latest state of the art technologies and design techniques to address challenges for RF cellular mobile, base stations, and RF and mmW WLAN applications. Coverage includes material on current silicon (CMOS, SiGe) RF and mmW power amplifier designs, focusing on advantages and disadvantages compared with traditional GaAs implementations. With this book you will learn: The principles of linearization and efficiency improvement techniquesThe arch

  8. Dynamic Floating Output Stage for Low Power Buffer Amplifier for LCD Application

    Directory of Open Access Journals (Sweden)

    Hari Shanker Srivastava

    2015-02-01

    Full Text Available This topic proposes low-power buffer means low quiescent current buffer amplifier. A dynamic floating current node is used at the output of two-stage amplifier to increase the charging and discharging of output capacitor as well as settling time of buffer. It is designed for 10 bit digital analog converter to support for LCD column driver it is implemented in 180 nm CMOS technology with the quiescent current of 5 µA for 30 pF capacitance, the settling time calculated as 4.5µs, the slew rate obtained as 5V/µs and area on chip is 30×72µ

  9. SEMICONDUCTOR INTEGRATED CIRCUITS: A novel fully differential telescopic operational transconductance amplifier

    Science.gov (United States)

    Tianwang, Li; Bo, Ye; Jinguang, Jiang

    2009-08-01

    A novel fully differential telescopic operational transconductance amplifier (OTA) is proposed. An additional PMOS differential pair is introduced to improve the unit-gain bandwidth of the telescopic amplifier. At the same time, the slew rate is enhanced by the auxiliary slew rate boost circuits. The proposed OTA is designed in a 0.18μm CMOS process. Simulation results show that there is a 49% improvement in the unit-gain bandwidth compared to that of a conventional OTA; moreover, the DC gain and the slew rate are also enhanced.

  10. SEMICONDUCTOR DEVICES: Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

    Science.gov (United States)

    Junting, Yu; Binqiao, Li; Pingping, Yu; Jiangtao, Xu; Cun, Mou

    2010-09-01

    Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 1012 cm-2, an implant tilt of -2°, a transfer gate channel doping dose of 3.0 × 1012 cm-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.

  11. Implantable intraocular pressure monitoring systems: Design considerations

    KAUST Repository

    Arsalan, Muhammad

    2013-12-01

    Design considerations and limitations of implantable Intraocular Pressure Monitoring (IOPM) systems are presented in this paper. Detailed comparison with the state of the art is performed to highlight the benefits and challenges of the proposed design. The system-on-chip, presented here, is battery free and harvests energy from incoming RF signals. This low-cost design, in standard CMOS process, does not require any external components or bond wires to function. This paper provides useful insights to the designers of implantable wireless sensors in terms of design choices and associated tradeoffs. © 2013 IEEE.

  12. High-performance VGA-resolution digital color CMOS imager

    Science.gov (United States)

    Agwani, Suhail; Domer, Steve; Rubacha, Ray; Stanley, Scott

    1999-04-01

    This paper discusses the performance of a new VGA resolution color CMOS imager developed by Motorola on a 0.5micrometers /3.3V CMOS process. This fully integrated, high performance imager has on chip timing, control, and analog signal processing chain for digital imaging applications. The picture elements are based on 7.8micrometers active CMOS pixels that use pinned photodiodes for higher quantum efficiency and low noise performance. The image processing engine includes a bank of programmable gain amplifiers, line rate clamping for dark offset removal, real time auto white balancing, per column gain and offset calibration, and a 10 bit pipelined RSD analog to digital converter with a programmable input range. Post ADC signal processing includes features such as bad pixel replacement based on user defined thresholds levels, 10 to 8 bit companding and 5 tap FIR filtering. The sensor can be programmed via a standard I2C interface that runs on 3.3V clocks. Programmable features include variable frame rates using a constant frequency master clock, electronic exposure control, continuous or single frame capture, progressive or interlace scanning modes. Each pixel is individually addressable allowing region of interest imaging and image subsampling. The sensor operates with master clock frequencies of up to 13.5MHz resulting in 30FPS. A total programmable gain of 27dB is available. The sensor power dissipation is 400mW at full speed of operation. The low noise design yields a measured 'system on a chip' dynamic range of 50dB thus giving over 8 true bits of resolution. Extremely high conversion gain result in an excellent peak sensitivity of 22V/(mu) J/cm2 or 3.3V/lux-sec. This monolithic image capture and processing engine represent a compete imaging solution making it a true 'camera on a chip'. Yet in its operation it remains extremely easy to use requiring only one clock and a 3.3V power supply. Given the available features and performance levels, this sensor will be

  13. Wavelength dependence of silicon avalanche photodiode fabricated by CMOS process

    Science.gov (United States)

    Mohammed Napiah, Zul Atfyi Fauzan; Hishiki, Takuya; Iiyama, Koichi

    2017-07-01

    Avalanche photodiodes fabricated by CMOS process (CMOS-APDs) have features of high avalanche gain below 10 V, wide bandwidth over 5 GHz, and easy integration with electronic circuits. In CMOS-APDs, guard ring structure is introduced for high-speed operation by canceling photo-generated carriers in the substrate at the sacrifice of the responsivity. We describe here wavelength dependence of the responsivity and the bandwidth of the CMOS-APDs with shorted and opened guard ring structure.

  14. Graphene/Si CMOS Hybrid Hall Integrated Circuits

    OpenAIRE

    Huang, Le; Xu, Huilong; Zhang, Zhiyong; Chen, Chengying; Jiang, Jianhua; Ma, Xiaomeng; Chen, Bingyan; Li, Zishen; Zhong, Hua; Peng, Lian-Mao

    2014-01-01

    Graphene/silicon CMOS hybrid integrated circuits (ICs) should provide powerful functions which combines the ultra-high carrier mobility of graphene and the sophisticated functions of silicon CMOS ICs. But it is difficult to integrate these two kinds of heterogeneous devices on a single chip. In this work a low temperature process is developed for integrating graphene devices onto silicon CMOS ICs for the first time, and a high performance graphene/CMOS hybrid Hall IC is demonstrated. Signal a...

  15. An integrated, low noise patch-clamp amplifier for biological nanopore applications.

    Science.gov (United States)

    Wang, Gang; Dunbar, William B

    2010-01-01

    We present an integrated, low noise patch-clamp amplifier for biological nanopore applications. Our amplifier consists of an integrator-differentiator architecture coupled with a novel opamp design in the CMOS 0.35 µm process. The post-layout full-chip simulation shows the input referred noise of the amplifier is 0.49 pA RMS over a 5 kHz bandwidth using a verified electrical model for the biological nanopore system. In our biological nanopore experiments studying protein-DNA interactions, we encounter capacitive transients with a nominal settling time of 5 ms. Our amplifier design reduces the settling time to 0.2 ms, without requiring any compensation circuitry.

  16. Delay estimation for CMOS functional cells

    DEFF Research Database (Denmark)

    Madsen, Jan

    1991-01-01

    Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis on arbitr......Presents a new RC tree network model for delay estimation of CMOS functional cells. The model is able to reflect topological changes within a cell, which is of particular interest when doing performance driven layout synthesis. Further, a set of algorithms to perform worst case analysis...... on arbitrary CMOS functional cells using the proposed delay model, is presented. Both model and algorithms have been implemented as a part of a cell compiler (CELLO) working in an experimental silicon compiler environment....

  17. CMOS Integrated Capacitive DC-DC Converters

    CERN Document Server

    Van Breussegem, Tom

    2013-01-01

    This book provides a detailed analysis of all aspects of capacitive DC-DC converter design: topology selection, control loop design and noise mitigation. Readers will benefit from the authors’ systematic overview that starts from the ground up, in-depth circuit analysis and a thorough review of recently proposed techniques and design methodologies.  Not only design techniques are discussed, but also implementation in CMOS is shown, by pinpointing the technological opportunities of CMOS and demonstrating the implementation based on four state-of-the-art prototypes.  Provides a detailed analysis of all aspects of capacitive DC-DC converter design;  Analyzes the potential of this type of DC-DC converter and introduces a number of techniques to unleash their full potential; Combines system theory with practical implementation techniques; Includes unique analysis of CMOS technology for this application; Provides in-depth analysis of four fabricated prototypes.

  18. CMOS-compatible LVOF-based visible microspectrometer

    NARCIS (Netherlands)

    Emadi, A.; Wu, H.; De Graaf, G.; Wolffenbuttel, R.F.

    2010-01-01

    This paper reports on a CMOS-Compatible Linear Variable Optical Filter (LVOF) visible micro-spectrometer. The CMOS-compatible post process for fabrication of the LVOF has been used for integration of the LVOF with a CMOS chip containing a 128-element photodiode array and readout circuitry. Fabricati

  19. Noise in sub-micron CMOS image sensors

    NARCIS (Netherlands)

    Wang, X.

    2008-01-01

    CMOS image sensors are devices that convert illumination signals (light intensity) into electronic signals. The goal of this thesis has been to analyze dominate noise sources in CMOS imagers and to improve the image quality by reducing the noise generated in the CMOS image sensor pixels.

  20. An RF (R) MS Power Detector in Standard CMOS

    NARCIS (Netherlands)

    Aa, van der F.H.J.

    2006-01-01

    This Master thesis describes the research towards the integration of RF power detectors for 3G cellular phones and base stations in CMOS technology1. It is a feasibility study with the emphasis on the identification of fundamental limitations of CMOS (particularly CMOS9) and of a number of squaring

  1. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  2. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  3. Optimization of plasma amplifiers

    Science.gov (United States)

    Sadler, James D.; Trines, Raoul M. Â. G. Â. M.; Tabak, Max; Haberberger, Dan; Froula, Dustin H.; Davies, Andrew S.; Bucht, Sara; Silva, Luís O.; Alves, E. Paulo; Fiúza, Frederico; Ceurvorst, Luke; Ratan, Naren; Kasim, Muhammad F.; Bingham, Robert; Norreys, Peter A.

    2017-05-01

    Plasma amplifiers offer a route to side-step limitations on chirped pulse amplification and generate laser pulses at the power frontier. They compress long pulses by transferring energy to a shorter pulse via the Raman or Brillouin instabilities. We present an extensive kinetic numerical study of the three-dimensional parameter space for the Raman case. Further particle-in-cell simulations find the optimal seed pulse parameters for experimentally relevant constraints. The high-efficiency self-similar behavior is observed only for seeds shorter than the linear Raman growth time. A test case similar to an upcoming experiment at the Laboratory for Laser Energetics is found to maintain good transverse coherence and high-energy efficiency. Effective compression of a 10 kJ , nanosecond-long driver pulse is also demonstrated in a 15-cm-long amplifier.

  4. STABILIZED TRANSISTOR AMPLIFIER

    Science.gov (United States)

    Noe, J.B.

    1963-05-01

    A temperature stabilized transistor amplifier having a pair of transistors coupled in cascade relation that are capable of providing amplification through a temperature range of - 100 un. Concent 85% F to 400 un. Concent 85% F described. The stabilization of the amplifier is attained by coupling a feedback signal taken from the emitter of second transistor at a junction between two serially arranged biasing resistances in the circuit of the emitter of the second transistor to the base of the first transistor. Thus, a change in the emitter current of the second transistor is automatically corrected by the feedback adjustment of the base-emitter potential of the first transistor and by a corresponding change in the base-emitter potential of the second transistor. (AEC)

  5. High-energy ion implantation for ULSI

    Energy Technology Data Exchange (ETDEWEB)

    Tsukamoto, K.; Komori, S.; Kuroi, T.; Akasaka, Y. (LSI R and D Lab., Mitsubishi Electric Corp., Itami (Japan))

    1991-07-01

    The ''well engineering'' of a retrograde twin well formed by high-energy ion implantation for 0.5 {mu}m CMOS is demonstrated to be quite useful in improving many device characteristics, such as leakage current reduction, soft-error immunity, low latchup susceptibility, smaller device isolation dimensions, etc. In forming a heavily doped buried layer by high-energy ion implantation, a drastic reduction in leakage current has been found. This would be caused by gettering of impurities or microdefects by secondary defects which are induced either by implantation of dopant itself (''self-gettering'') or by an additional implantation of oxygen, carbon or fluorine (''proximity gettering''). (orig.).

  6. 60-GHz CMOS phase-locked loops

    CERN Document Server

    Cheema, Hammad M; van Roermund, Arthur HM

    2010-01-01

    The promising high data rate wireless applications at millimeter wave frequencies in general and 60 GHz in particular have gained much attention in recent years. However, challenges related to circuit, layout and measurements during mm-wave CMOS IC design have to be overcome before they can become viable for mass market. ""60-GHz CMOS Phase-Locked Loops"" focusing on phase-locked loops for 60 GHz wireless transceivers elaborates these challenges and proposes solutions for them. The system level design to circuit level implementation of the complete PLL, along with separate implementations of i

  7. Scaling CMOS devices through alternative structures

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    The conventional wisdom holds that CMOS devices cannot be scaled much further from where they are today because of several device physics limitations such as the large tunneling current in very thin gate dielectrics. It is shown that alternative device structures can allow CMOS transistors to scale by another 20 times. That is as large a factor of scaling as what the semiconductor industry accomplished in the past 25 years. There will be many opportunities and challenges in finding novel device structures and new processing techniques, and in understanding the physics of future devices.

  8. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  9. Modeling of Amperometric Immunosensor for CMOS Integration

    Institute of Scientific and Technical Information of China (English)

    Ce Li; Haigang Yang; Shanhong Xia; Chao Bian

    2006-01-01

    A circuit model of the Amperometric immunosensor for use in the biosensor system-on-chip simulation is proposed in this paper. The model parameters are extracted with several methods and verified by MATLAB and SPICE simulation. A CMOS potentiostat circuit required for conditioning the Amperometric immunosensor is also included in the circuit model. The mean square error norm of the simulated curve against the measured one is 8.65 × 10-17. The whole circuit has been fabricated in a 0.35am CMOS process.

  10. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  11. Principal modes in fiber amplifiers

    CERN Document Server

    Fridman, Moti; Dubinskii, Mark; Friesem, Asher A; Davidson, Nir

    2010-01-01

    The dynamics of the state of polarization in single mode and multimode fiber amplifiers are presented. The experimental results reveal that although the state of polarizations at the output can vary over a large range when changing the temperatures of the fiber amplifiers, the variations are significantly reduced when resorting to the principal states of polarization in single mode fiber amplifiers and principal modes in multimode fiber amplifiers.

  12. Alternative Post-Processing on a CMOS Chip to Fabricate a Planar Microelectrode Array

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L.; Estrada-López, Johan J.; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S.

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+-type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications. PMID:22346681

  13. Design and test challenges in Nano-scale analog and mixed CMOS technology

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-07-01

    Full Text Available The continuous increase of integration densities in Complementary Metal–Oxide–Semiconductor (CMOStechnology has driven the rapid growth of very large scale integrated (VLSI circuit for today's high-techelectronics industries from consumer products to telecommunications and computers. As CMOStechnologies are scaled down into the nanometer range, analog and mixed integrated circuit (IC design andtesting have become a real challenge to ensure the functionality and quality of the product. The first part ofthe paper presents the CMOS technology scaling impact on design and reliability for consumer and criticalapplications. We then propose a discussion on the role and challenges of testing analog and mixed devicesin the nano-scale era. Finally we present the IDDQ testing technique used to detect the most likely defects ofbridging type occurring in analog CMOS circuits during the manufacturing process and creating a resistivepath between VDD supply and the ground.To prove the efficiency of the proposed technique we design a CMOS 90nm operational amplifier (Opamp and a Built in Current Sensor (BICS to validate the technique and correlate it with post layoutsimulation results.

  14. A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    Institute of Scientific and Technical Information of China (English)

    Liu Nan; Chen Guoping; Hong Zhiliang

    2009-01-01

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a "contact imaging" detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodi-ode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

  15. Alternative post-processing on a CMOS chip to fabricate a planar microelectrode array.

    Science.gov (United States)

    López-Huerta, Francisco; Herrera-May, Agustín L; Estrada-López, Johan J; Zuñiga-Islas, Carlos; Cervantes-Sanchez, Blanca; Soto, Enrique; Soto-Cruz, Blanca S

    2011-01-01

    We present an alternative post-processing on a CMOS chip to release a planar microelectrode array (pMEA) integrated with its signal readout circuit, which can be used for monitoring the neuronal activity of vestibular ganglion neurons in newborn Wistar strain rats. This chip is fabricated through a 0.6 μm CMOS standard process and it has 12 pMEA through a 4 × 3 electrodes matrix. The alternative CMOS post-process includes the development of masks to protect the readout circuit and the power supply pads. A wet etching process eliminates the aluminum located on the surface of the p+ -type silicon. This silicon is used as transducer for recording the neuronal activity and as interface between the readout circuit and neurons. The readout circuit is composed of an amplifier and tunable bandpass filter, which is placed on a 0.015 mm2 silicon area. The tunable bandpass filter has a bandwidth of 98 kHz and a common mode rejection ratio (CMRR) of 87 dB. These characteristics of the readout circuit are appropriate for neuronal recording applications.

  16. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Directory of Open Access Journals (Sweden)

    Shoji Kawahito

    2010-10-01

    Full Text Available For low-noise complementary metal-oxide-semiconductor (CMOS image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e- for the simple integration CMS and 75 dB and 2.2 e- for the folding integration CMS, respectively, are obtained.

  17. Low noise CMOS readout for CdZnTe detector arrays

    CERN Document Server

    Jakobson, C G; Lev, S B; Nemirovsky, Y

    1999-01-01

    A low noise CMOS readout for CdTe and CdZnTe X- and gamma-ray detector arrays has been designed and implemented in the CMOS 2 mu m low noise analog process provided by the multi-chip program of Metal Oxide Semiconductor Implementation Service. The readout includes CMOS low noise charge sensitive preamplifier and a multiplexed semi-Gaussian pulse shaper. Thus, each detector has a dedicated charge sensitive preamplifier that integrates its signal, while a single shaping amplifier shapes the pulses after the multiplexer. Low noise and low-power operation are achieved by optimizing the input transistor of the charge sensitive preamplifier. Two optimization criteria are used to reduce noise. The first criterion is based on capacitance matching between the input transistor and the detector. The second criterion is based on bandwidth optimization, which is obtained by tailoring the shaper parameters to the particular noise mechanisms of the MOS transistor and the CdZnTe detector. Furthermore, the multiplexing functi...

  18. A New Automated Design Method Based on Machine Learning for CMOS Analog Circuits

    Science.gov (United States)

    Moradi, Behzad; Mirzaei, Abdolreza

    2016-11-01

    A new simulation based automated CMOS analog circuit design method which applies a multi-objective non-Darwinian-type evolutionary algorithm based on Learnable Evolution Model (LEM) is proposed in this article. The multi-objective property of this automated design of CMOS analog circuits is governed by a modified Strength Pareto Evolutionary Algorithm (SPEA) incorporated in the LEM algorithm presented here. LEM includes a machine learning method such as the decision trees that makes a distinction between high- and low-fitness areas in the design space. The learning process can detect the right directions of the evolution and lead to high steps in the evolution of the individuals. The learning phase shortens the evolution process and makes remarkable reduction in the number of individual evaluations. The expert designer's knowledge on circuit is applied in the design process in order to reduce the design space as well as the design time. The circuit evaluation is made by HSPICE simulator. In order to improve the design accuracy, bsim3v3 CMOS transistor model is adopted in this proposed design method. This proposed design method is tested on three different operational amplifier circuits. The performance of this proposed design method is verified by comparing it with the evolutionary strategy algorithm and other similar methods.

  19. Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

    Science.gov (United States)

    Suh, Sungho; Itoh, Shinya; Aoyama, Satoshi; Kawahito, Shoji

    2010-01-01

    For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained. PMID:22163400

  20. Multiple pass laser amplifier system

    Science.gov (United States)

    Brueckner, Keith A.; Jorna, Siebe; Moncur, N. Kent

    1977-01-01

    A laser amplification method for increasing the energy extraction efficiency from laser amplifiers while reducing the energy flux that passes through a flux limited system which includes apparatus for decomposing a linearly polarized light beam into multiple components, passing the components through an amplifier in delayed time sequence and recombining the amplified components into an in phase linearly polarized beam.

  1. Radio Frequency Solid State Amplifiers

    CERN Document Server

    Jacob, J

    2015-01-01

    Solid state amplifiers are being increasingly used instead of electronic vacuum tubes to feed accelerating cavities with radio frequency power in the 100 kW range. Power is obtained from the combination of hundreds of transistor amplifier modules. This paper summarizes a one hour lecture on solid state amplifiers for accelerator applications.

  2. Polarization effect in parametric amplifier

    Institute of Scientific and Technical Information of China (English)

    Junhe Zhou; Jianping Chen; Xinwan Li; Guiling Wu; Yiping Wang

    2005-01-01

    @@ Polarization effect in parametric amplifiers is studied. Coupled equations are derived from the basic propagation equations and numerical solutions are given for both one-wavelength-pump and two-wavelengthpump systems. Several parametric amplifiers driven by pumps at one wavelength and two wavelengths are analyzed and the polarization independent parametric amplifier is proposed.

  3. Improved-Bandwidth Transimpedance Amplifier

    Science.gov (United States)

    Chapsky, Jacob

    2009-01-01

    The widest available operational amplifier, with the best voltage and current noise characteristics, is considered for transimpedance amplifier (TIA) applications where wide bandwidth is required to handle fast rising input signals (as for time-of-flight measurement cases). The added amplifier inside the TIA feedback loop can be configured to have slightly lower voltage gain than the bandwidth reduction factor.

  4. A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

    Directory of Open Access Journals (Sweden)

    Hanie Ghaedrahmati

    2012-12-01

    Full Text Available A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC using a novel mirror telescopic operational amplifiers (opamp with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA into the first multiplying digital-to-analog converter (MDAC using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved

  5. A 10-bit, 200MS/s CMOS Pipeline ADC using new shared opamp architecture

    Directory of Open Access Journals (Sweden)

    Hanie Ghaedrahmat

    2013-01-01

    Full Text Available A 10 bit opamp-sharing pipeline analog-to-digital converter (ADC using a novel mirror telescopic operational amplifiers (opamp with dual nmos differential inputs is presented. Reduction of power and area is achieved by completely merging the front-end sample-and-hold amplifier (SHA into the first multiplying digital-to-analog converter (MDAC using the proposed opamp. Transistors in the opamp are always biased in saturation to avoid increase of settling time due to opamp turn-on delays. The design targets 0.18um CMOS process for operation, at 200MS/s from a 1.8V supply. The simulation results show the SNDR and SFDR of 59.45dB and 68.69dB, respectively, and the power consumption of 35.04mW is achieved

  6. Evaluation of a scientific CMOS camera for astronomical observations

    Institute of Scientific and Technical Information of China (English)

    Peng Qiu; Yong-Na Mao; Xiao-Meng Lu; E Xiang; Xiao-Jun Jiang

    2013-01-01

    We evaluate the performance of the first generation scientific CMOS (sCMOS) camera used for astronomical observations.The sCMOS camera was attached to a 25 cm telescope at Xinglong Observatory,in order to estimate its photometric capabilities.We further compared the capabilities of the sCMOS camera with that of full-frame and electron multiplying CCD cameras in laboratory tests and observations.The results indicate the sCMOS camera is capable of performing photometry of bright sources,especially when high spatial resolution or temporal resolution is desired.

  7. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  8. Design of a CMOS Adaptive Charge Pump with Dynamic Current Matching

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    A novel structure for a charge pump circuit is proposed, in which the charge-pump (CP) current can adaptively regulated according to phase-locked loops (PLL) frequency synthesis demand. The current follow technology is used to make perfect current matching characteristics, and the two differential inverters are implanted to increase the speed of charge pump and decrease output spur due to theory of low voltage difference signal. Simulation results, with 1st silicon 0.25 μm 2.5 V complementary metal-oxide-semiconductor (CMOS) mixed-signal process, show the good current matching characteristics regardless of the charge pump output voltages.

  9. Modulation Techniques for Biomedical Implanted Devices and Their Challenges

    Directory of Open Access Journals (Sweden)

    Salina A. Samad

    2011-12-01

    Full Text Available Implanted medical devices are very important electronic devices because of their usefulness in monitoring and diagnosis, safety and comfort for patients. Since 1950s, remarkable efforts have been undertaken for the development of bio-medical implanted and wireless telemetry bio-devices. Issues such as design of suitable modulation methods, use of power and monitoring devices, transfer energy from external to internal parts with high efficiency and high data rates and low power consumption all play an important role in the development of implantable devices. This paper provides a comprehensive survey on various modulation and demodulation techniques such as amplitude shift keying (ASK, frequency shift keying (FSK and phase shift keying (PSK of the existing wireless implanted devices. The details of specifications, including carrier frequency, CMOS size, data rate, power consumption and supply, chip area and application of the various modulation schemes of the implanted devices are investigated and summarized in the tables along with the corresponding key references. Current challenges and problems of the typical modulation applications of these technologies are illustrated with a brief suggestions and discussion for the progress of implanted device research in the future. It is observed that the prime requisites for the good quality of the implanted devices and their reliability are the energy transformation, data rate, CMOS size, power consumption and operation frequency. This review will hopefully lead to increasing efforts towards the development of low powered, high efficient, high data rate and reliable implanted devices.

  10. Design of Low Power CMOS Circuits using Leakage Control Transistor and Multi-Threshold CMOS Techniques

    OpenAIRE

    2012-01-01

    The scaling down of technology in CMOS circuits, results in the down scaling of threshold voltage thereby increasing the sub-threshold leakage current. An IC consists of many circuits of which some circuits consists critical path like full adder, whereas some circuits like multiplexer and decoder has no specified critical path. LECTOR is a technique for designing leakage power reduced CMOS circuits without affecting the dynamic power dissipation, which can be used for circuits with no specifi...

  11. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  12. Electronic amplifiers for automatic compensators

    CERN Document Server

    Polonnikov, D Ye

    1965-01-01

    Electronic Amplifiers for Automatic Compensators presents the design and operation of electronic amplifiers for use in automatic control and measuring systems. This book is composed of eight chapters that consider the problems of constructing input and output circuits of amplifiers, suppression of interference and ensuring high sensitivity.This work begins with a survey of the operating principles of electronic amplifiers in automatic compensator systems. The succeeding chapters deal with circuit selection and the calculation and determination of the principal characteristics of amplifiers, as

  13. Simplified design of IC amplifiers

    CERN Document Server

    Lenk, John

    1996-01-01

    Simplified Design of IC Amplifiers has something for everyone involved in electronics. No matter what skill level, this book shows how to design and experiment with IC amplifiers. For experimenters, students, and serious hobbyists, this book provides sufficient information to design and build IC amplifier circuits from 'scratch'. For working engineers who design amplifier circuits or select IC amplifiers, the book provides a variety of circuit configurations to make designing easier.Provides basics for all phases of practical design.Covers the most popular forms for amplif

  14. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  15. Low power SEU immune CMOS memory circuits

    Science.gov (United States)

    Liu, M. N.; Whitaker, Sterling

    1992-01-01

    The authors report a design improvement for CMOS static memory circuits hardened against single event upset (SEU) using a recently proposed logic/circuit design technique. This improvement drastically reduces static power consumption, reduces the number of transistors required in a D flip-flop design, and eliminates the possibility of capturing an upset state in the slave section during a clock transition.

  16. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern mul

  17. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  18. RF Circuit Design in Nanometer CMOS

    NARCIS (Netherlands)

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern

  19. Fully CMOS-compatible titanium nitride nanoantennas

    Science.gov (United States)

    Briggs, Justin A.; Naik, Gururaj V.; Petach, Trevor A.; Baum, Brian K.; Goldhaber-Gordon, David; Dionne, Jennifer A.

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  20. A 24GHz Radar Receiver in CMOS

    NARCIS (Netherlands)

    Kwok, K.C.

    2015-01-01

    This thesis investigates the system design and circuit implementation of a 24GHz-band short-range radar receiver in CMOS technology. The propagation and penetration properties of EM wave offer the possibility of non-contact based remote sensing and through-the-wall imaging of distance stationary or

  1. Design and realization of CMOS image sensor

    Science.gov (United States)

    Xu, Jian; Xiao, Zexin

    2008-02-01

    A project was presented that instrumental design of an economical CMOS microscope image sensor. A high performance, low price, black-white camera chip OV5116P was used as the core of the sensor circuit; Designing and realizing peripheral control circuit of sensor; Through the control on dial switch to realize different functions of the sensor chip in the system. For example: auto brightness level descending function on or off; gamma correction function on or off; auto and manual backlight compensation mode conversion and so on. The optical interface of sensor is designed for commercialization and standardization. The images of sample were respectively gathered with CCD and CMOS. Result of the experiment indicates that both performances were identical in several aspects as follows: image definition, contrast control, heating degree and the function can be adjusted according to the demand of user etc. The imperfection was that the CMOS with smaller field and higher noise than CCD; nevertheless, the maximal advantage of choosing the CMOS chip is its low cost. And its imaging quality conformed to requirement of the economical microscope image sensor.

  2. Analog IC reliability in nanometer CMOS

    CERN Document Server

    Maricau, Elie

    2013-01-01

    This book focuses on modeling, simulation and analysis of analog circuit aging. First, all important nanometer CMOS physical effects resulting in circuit unreliability are reviewed. Then, transistor aging compact models for circuit simulation are discussed and several methods for efficient circuit reliability simulation are explained and compared. Ultimately, the impact of transistor aging on analog circuits is studied. Aging-resilient and aging-immune circuits are identified and the impact of technology scaling is discussed.   The models and simulation techniques described in the book are intended as an aid for device engineers, circuit designers and the EDA community to understand and to mitigate the impact of aging effects on nanometer CMOS ICs.   ·         Enables readers to understand long-term reliability of an integrated circuit; ·         Reviews CMOS unreliability effects, with focus on those that will emerge in future CMOS nodes; ·         Provides overview of models for...

  3. Plasmonic Modulator Using CMOS Compatible Material Platform

    DEFF Research Database (Denmark)

    Babicheva, Viktoriia; Kinsey, Nathaniel; Naik, Gururaj V.;

    2014-01-01

    In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device l ayout utilizes alternative plas monic materials such as tr ansparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation...

  4. CMOS VHF transconductance-C lowpass filter

    NARCIS (Netherlands)

    Nauta, B.

    1990-01-01

    Experimental results of a VHF CMOS transconductance-C lowpass filter are described. The filter is built with transconductors as published earlier. The cutoff frequency can be tuned from 22 to 98 MHz and the measured filter response is very close to the ideal response

  5. Linear CMOS transconductance element for VHF filters

    NARCIS (Netherlands)

    Nauta, B.; Seevinck, E.

    1989-01-01

    A differential transconductance element based on CMOS inverters is presented. With this circuit a linear, tunable integrator for very high-frequency continuous-time integrated filters can be made. This integrator has good linearity properties (THD<0.04%, Vipp=1.8 V), nondominant poles in the gigaher

  6. Method and circuitry for CMOS transconductor linearization

    NARCIS (Netherlands)

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transisto

  7. Wideband amplifier design

    CERN Document Server

    Hollister, Allen L

    2007-01-01

    In this book, the theory needed to understand wideband amplifier design using the simplest models possible will be developed. This theory will be used to develop algebraic equations that describe particular circuits used in high frequency design so that the reader develops a ""gut level"" understanding of the process and circuit. SPICE and Genesys simulations will be performed to show the accuracy of the algebraic models. By looking at differences between the algebraic equations and the simulations, new algebraic models will be developed that include parameters originally left out of the model

  8. Building valve amplifiers

    CERN Document Server

    Jones, Morgan

    2013-01-01

    Building Valve Amplifiers is a unique hands-on guide for anyone working with tube audio equipment--as an electronics hobbyist, audiophile or audio engineer. This 2nd Edition builds on the success of the first with technology and technique revisions throughout and, significantly, a major new self-build project, worked through step-by-step, which puts into practice the principles and techniques introduced throughout the book. Particular attention has been paid to answering questions commonly asked by newcomers to the world of the valve, whether audio enthusiasts tackling their first build or

  9. REGENERATIVE TRANSISTOR AMPLIFIER

    Science.gov (United States)

    Kabell, L.J.

    1958-11-25

    Electrical circults for use in computers and the like are described. particularly a regenerative bistable transistor amplifler which is iurned on by a clock signal when an information signal permits and is turned off by the clock signal. The amplifier porforms the above function with reduced power requirements for the clock signal and circuit operation. The power requirements are reduced in one way by employing transformer coupling which increases the collector circuit efficiency by eliminating the loss of power in the collector load resistor.

  10. A Low-Power Voltage Limiter/Regulator IC in Standard Thick-Oxide 130 nm CMOS for Inductive Power Transfer Application

    Directory of Open Access Journals (Sweden)

    Stepan Lapshev

    2014-01-01

    Full Text Available This paper presents a novel CMOS low-power voltage limiter/regulator circuit with hysteresis for inductive power transfer in an implanted telemetry application. The circuit controls its rail voltage to the maximum value of 3 V DC employing 100 mV of comparator hysteresis. It occupies a silicon area of only 127 µm × 125 µm using the 130 nm IBM CMOS process. In addition, the circuit dissipated less than 1 mW and was designed using thick-oxide 3.6 V NMOS and PMOS devices available in the process library.

  11. Cochlear Implants

    Science.gov (United States)

    A cochlear implant is a small, complex electronic device that can help to provide a sense of sound. People who are ... of-hearing can get help from them. The implant consists of two parts. One part sits on ...

  12. Cochlear Implants

    Science.gov (United States)

    ... imaging (MRI) scans, to evaluate your inner ear anatomy. Cochlear implant surgery Cochlear implant surgery is usually performed as an outpatient procedure under general anesthesia. An incision is made behind the ear ...

  13. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  14. CMOS MEMS capacitive absolute pressure sensor

    Science.gov (United States)

    Narducci, M.; Yu-Chia, L.; Fang, W.; Tsai, J.

    2013-05-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal-oxide-semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa-1 in the pressure range of 0-300 kPa.

  15. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  16. Multifunctional Platform with CMOS-Compatible Tungsten Microhotplate for Pirani, Temperature, and Gas Sensor

    Directory of Open Access Journals (Sweden)

    Jiaqi Wang

    2015-10-01

    Full Text Available A multifunctional platform based on the microhotplate was developed for applications including a Pirani vacuum gauge, temperature, and gas sensor. It consisted of a tungsten microhotplate and an on-chip operational amplifier. The platform was fabricated in a standard complementary metal oxide semiconductor (CMOS process. A tungsten plug in standard CMOS process was specially designed as the serpentine resistor for the microhotplate, acting as both heater and thermister. With the sacrificial layer technology, the microhotplate was suspended over the silicon substrate with a 340 nm gap. The on-chip operational amplifier provided a bias current for the microhotplate. This platform has been used to develop different kinds of sensors. The first one was a Pirani vacuum gauge ranging from 1-1 to 105 Pa. The second one was a temperature sensor ranging from -20 to 70 °C. The third one was a thermal-conductivity gas sensor, which could distinguish gases with different thermal conductivities in constant gas pressure and environment temperature. In the fourth application, with extra fabrication processes including the deposition of gas-sensitive film, the platform was used as a metal-oxide gas sensor for the detection of gas concentration.

  17. 新型高精度CMOS电流比较器%New High-distinguish CMOS Current Comparator

    Institute of Scientific and Technical Information of China (English)

    程亮

    2015-01-01

    分析了当前几种高性能CMOS电流比较器的优缺点,并设计了一种新颖的电流比较器电路。该电路由3部分组成,具有负反馈电阻的CMOS反相放大器、1组乙类推挽放大器和1组甲乙类推挽放大器。由于CMOS反相放大器的负反馈电阻有效地减小了输入级电路的输入、输出阻抗,从而使得电流比较器的瞬态响应时间变短,反应速度加快。在CSMC 0.35μm模拟CMOS工艺模型下,使用HSPICE仿真器对电路进行仿真,结果表明设计的CMOS电流比较器与目前报导的最快的电流比较器延时几近相等,而且可识别的电流精度高于常见的几种高精度电流比较器。%Advantages and disadvantages of several high performance CMOS current comparator were analyzed and a new CMOS current comparator structure was designed in the paper. The circuit was composed of three parts, a CMOS inverting amplifier with negative feedback resistor, a group of class B push-pull amplifier and a group of class A B push-pull amplifier. Because the CMOS inverting amplifier with negative feedback resistance effectively reduces the input, the output impedance of input stage circuit, so that the transient response time of the current comparator was shorted. Based on CSMC 0.35μm analog CMOS model, the circuit was simulated by Hspice. The results show that its delay time compared with the fast current comparator reported at parent is almost equal and current accuracy is higher than several high precision current comparator common.

  18. Design of A Low Power Low Voltage CMOS Opamp

    CERN Document Server

    Baruah, Ratul Kr

    2010-01-01

    In this paper a CMOS operational amplifier is presented which operates at 2V power supply and 1microA input bias current at 0.8 micron technology using non conventional mode of operation of MOS transistors and whose input is depended on bias current. The unique behaviour of the MOS transistors in subthreshold region not only allows a designer to work at low input bias current but also at low voltage. While operating the device at weak inversion results low power dissipation but dynamic range is degraded. Optimum balance between power dissipation and dynamic range results when the MOS transistors are operated at moderate inversion. Power is again minimised by the application of input dependant bias current using feedback loops in the input transistors of the differential pair with two current substractors. In comparison with the reported low power low voltage opamps at 0.8 micron technology, this opamp has very low standby power consumption with a high driving capability and operates at low voltage. The opamp ...

  19. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  20. Noise limits of CMOS current interfaces for biosensors: a review.

    Science.gov (United States)

    Crescentini, Marco; Bennati, Marco; Carminati, Marco; Tartagni, Marco

    2014-04-01

    Current sensing readout is one of the most frequent techniques used in biosensing due to the charge-transfer phenomena occurring at solid-liquid interfaces. The development of novel nanodevices for biosensing determines new challenges for electronic interface design based on current sensing, especially when compact and efficient arrays need to be organized, such as in recent trends of rapid label-free electronic detection of DNA synthesis. This paper will review the basic noise limitations of current sensing interfaces with particular emphasis on integrated CMOS technology. Starting from the basic theory, the paper presents, investigates and compares charge-sensitive amplifier architectures used in both continuous-time and discrete-time approaches, along with their design trade-offs involving noise floor, sensitivity to stray capacitance and bandwidth. The ultimate goal of this review is providing analog designers with helpful design rules and analytical tools. Also, in order to present a comprehensive overview of the state-of-the-art, the most relevant papers recently appeared in the literature about this topic are discussed and compared.

  1. Accurate geometry scalable complementary metal oxide semiconductor modelling of low-power 90 nm amplifier circuits

    Directory of Open Access Journals (Sweden)

    Apratim Roy

    2014-05-01

    Full Text Available This paper proposes a technique to accurately estimate radio frequency behaviour of low-power 90 nm amplifier circuits with geometry scalable discrete complementary metal oxide semiconductor (CMOS modelling. Rather than characterising individual elements, the scheme is able to predict gain, noise and reflection loss of low-noise amplifier (LNA architectures made with bias, active and passive components. It reduces number of model parameters by formulating dependent functions in symmetric distributed modelling and shows that simple fitting factors can account for extraneous (interconnect effects in LNA structure. Equivalent-circuit model equations based on physical structure and describing layout parasites are developed for major amplifier elements like metal–insulator–metal (MIM capacitor, spiral symmetric inductor, polysilicon (PS resistor and bulk RF transistor. The models are geometry scalable with respect to feature dimensions, i.e. MIM/PS width and length, outer-dimension/turns of planar inductor and channel-width/fingers of active device. Results obtained with the CMOS models are compared against measured literature data for two 1.2 V amplifier circuits where prediction accuracy for RF parameters (S(21, noise figure, S(11, S(22 lies within the range of 92–99%.

  2. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

    Directory of Open Access Journals (Sweden)

    Marco Crescentini

    2016-05-01

    Full Text Available High-throughput screening (HTS using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i design of scalable microfluidic devices; (ii design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

  3. A 0.45pJ/conv-step 1.2Gs/s 6b full-Nyquist non-calibrated flash ADC in 45nm CMOS and its scaling behavior

    NARCIS (Netherlands)

    Veldhorst, Paul; Goksun, George; Buter, Berry; Vertregt, Maarten; Annema, Anne-Johan; Nauta, Bram

    2009-01-01

    A 6-bit 1.2 Gs/s non-calibrated flash ADC in a standard 45nm CMOS process, that achieves 0.45pJ/conv-step at full Nyquist bandwidth, is presented. Power efficient operation is achieved by a full optimization of amplifier blocks, and by innovations in the comparator and encoding stage. The performanc

  4. Ways to suppress click and pop for class D amplifiers

    Institute of Scientific and Technical Information of China (English)

    Wang Haishi; Zhang Bo; Sun Jiang

    2012-01-01

    Undesirable audio click and pop may be generated in a speaker or headphone.Compared to linear (class A/B/AB) amplifiers,class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop.This article analyzes sources that generate click and pop in class D amplifiers,and corresponding ways to suppress them.For a class D amplifier with a single-ended input,click and pop is likely to be due to two factors.One is from a voltage difference (VDIF) between the voltage of an input capacitance (VCIN)and a reference voltage (VREF) of the input stage,and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage.In this article,a fast charging loop is introduced into the input stage to charge VCIN to roughly near VREF.Then a correction loop further charges or discharges VCIN,substantially equalizing it with VREF.Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC,and the power switches are disabled until the BFVC are set up successfully.A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process.Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.

  5. System on chip thermal vacuum sensor based on standard CMOS process

    Institute of Scientific and Technical Information of China (English)

    Li Jinfeng; Tang Zhen'an; Wang Jiaqi

    2009-01-01

    An on-chip microelectromechanical system was fabricated in a 0.5μm standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 105 Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 Ω resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  6. Noise calculation model and analysis of high-gain readout circuits for CMOS image sensors

    Science.gov (United States)

    Kawahito, Shoji; Itoh, Shinya

    2008-02-01

    A thermal noise calculation model of high-gain switched-capacitor column noise cancellers for CMOS image sensors is presented. In the high-gain noise canceller with a single noise cancelling stage, the reset noise of the readout circuits dominates the noise at high gain. Using the double-stage architecture using a switched-capacitor gain stage and a sample-and-hold stage using two sampling capacitors, the reset noise of the gain stage can be cancelled. The resulting input referred thermal noise power of high-gain double-stage switched-capacitor noise canceller is revealed to be proportional to (g_a/g_s)/GC_L where g_a, G and C_L are the transconductance, gain and output capacitance of the amplifier, respectively, and g_s is the output conductance of an in-pixel source follower. An important contribution of the proposed noise calculation formula is the inclusion of the influence of the transconductance ratio of the amplifier to that of the source follower. For low-noise design, it is important that the transconductance of the amplifier used in the noise canceller is minimized under the condition of meeting the required response time of the switched capacitor amplifier which is inversely proportional to the cutoff angular frequency.

  7. The Biolink Implantable Telemetry System

    Science.gov (United States)

    Betancourt-Zamora, Rafael J.

    1999-01-01

    Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS

  8. Nanoscale electromechanical parametric amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Aleman, Benjamin Jose; Zettl, Alexander

    2016-09-20

    This disclosure provides systems, methods, and apparatus related to a parametric amplifier. In one aspect, a device includes an electron source electrode, a counter electrode, and a pumping electrode. The electron source electrode may include a conductive base and a flexible conductor. The flexible conductor may have a first end and a second end, with the second end of the flexible conductor being coupled to the conductive base. A cross-sectional dimension of the flexible conductor may be less than about 100 nanometers. The counter electrode may be disposed proximate the first end of the flexible conductor and spaced a first distance from the first end of the flexible conductor. The pumping electrode may be disposed proximate a length of the flexible conductor and spaced a second distance from the flexible conductor.

  9. Nanoscale electromechanical parametric amplifier

    Science.gov (United States)

    Aleman, Benjamin Jose; Zettl, Alexander

    2016-09-20

    This disclosure provides systems, methods, and apparatus related to a parametric amplifier. In one aspect, a device includes an electron source electrode, a counter electrode, and a pumping electrode. The electron source electrode may include a conductive base and a flexible conductor. The flexible conductor may have a first end and a second end, with the second end of the flexible conductor being coupled to the conductive base. A cross-sectional dimension of the flexible conductor may be less than about 100 nanometers. The counter electrode may be disposed proximate the first end of the flexible conductor and spaced a first distance from the first end of the flexible conductor. The pumping electrode may be disposed proximate a length of the flexible conductor and spaced a second distance from the flexible conductor.

  10. Dental Implant Surgery

    Science.gov (United States)

    ... here to find out more. Dental Implant Surgery Dental Implant Surgery Dental implant surgery is, of course, surgery, ... here to find out more. Dental Implant Surgery Dental Implant Surgery Dental implant surgery is, of course, surgery, ...

  11. Low noise and high CMRR front-end amplifier dedicated to portable EEG acquisition system.

    Science.gov (United States)

    Chebli, Robert; Sawan, Mohamad

    2013-01-01

    This paper concerns the design and implementation of a fully integrated low noise and high CMRR rail-to-rail preamplifier dedicated to EEG acquisition channel. The preamplification technique is based on two complementary CMOS True Logarithmic Amplifier (TLA) stages connected in parallel. The TLA largely amplifies small amplitude of EEG signals, and moderately the large amplitude ones created during epileptic. A chopper stabilization technique is used to filter the 1/ƒ noise and the DC offset voltage of the input CMOS transistors and to increase the common-mode rejection ratio (CMRR). Due to the TLA structure, a high CMRR and high power supply rejection ratio are achieved and the signal-to-noise ratio (of the channel is better enhanced). To snugly fit the ADC input window to the EEG signal magnitude a new programming gain approach is implemented. Also, a chopper spike filter is used to cancel the spike voltages generated by the charge injections of modulator/demodulator switches. The proposed preamplifier is implemented in 0.18 µm CMOS technology. Post-layout simulation results exhibit 253 dB @50/60 Hz as CMRR, 500 nVrms @100 Hz as input-referred noise while consuming 55 µA from a 1.8 V supply.

  12. CLARO-CMOS, an ASIC for single photon counting with Ma-PMTs, MCPs and SiPMs

    Science.gov (United States)

    Carniti, P.; Cibinetto, G.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Maino, M.; Malaguti, R.; Pessina, G.

    2013-01-01

    An ASIC named CLARO-CMOS was designed for fast photon counting with MaPMTs, MCPs and SiPMs. The prototype was realized in a .35 μm CMOS technology and has four channels, each with a fast amplifier and a discriminator. The main features of the design are the high speed of operation and the low power dissipation, below 1 mW per channel. This paper focuses on the use of the CLARO for SiPM readout. The ASIC was tested with several SiPMs of various sizes, connected to the input of the chip both directly and through a coaxial cable about one meter long. In the latter case the ASIC is still fully functional although the speed of response is affected by the cable capacitance. The threshold could be set just above the single photoelectron level, and with 1 ×1 mm2 SiPMs the discrete photoelectron peaks could be well resolved.

  13. A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 µm CMOS Process

    Directory of Open Access Journals (Sweden)

    Noor A.B.A. Taib

    2013-03-01

    Full Text Available Digital to (DAC is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 µm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 µm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

  14. Charge pump-based MOSFET-only 1.5-bit pipelined ADC stage in digital CMOS technology

    Science.gov (United States)

    Singh, Anil; Agarwal, Alpana

    2016-10-01

    A simple low-power and low-area metal-oxide-semiconductor field-effect transistor-only fully differential 1.5-bit pipelined analog-to-digital converter stage is proposed and designed in Taiwan Semiconductor Manufacturing Company 0.18 μm-technology using BSIM3v3 parameters with supply voltage of 1.8 V in inexpensive digital complementary metal-oxide semiconductor (CMOS) technology. It is based on charge pump technique to achieve the desired voltage gain of 2, independent of capacitor mismatch and avoiding the need of power hungry operational amplifier-based architecture to reduce the power, Si area and cost. Various capacitances are implemented by metal-oxide semiconductor capacitors, offering compatibility with cheaper digital CMOS process in order to reduce the much required manufacturing cost.

  15. Modeling of semiconductor optical amplifiers

    DEFF Research Database (Denmark)

    Mørk, Jesper; Bischoff, Svend; Berg, Tommy Winther

    We discuss the modelling of semiconductor optical amplifiers with emphasis on their high-speed properties. Applications in linear amplification as well as ultrafast optical signal processing are reviewed. Finally, the possible role of quantum-dot based optical amplifiers is discussed.......We discuss the modelling of semiconductor optical amplifiers with emphasis on their high-speed properties. Applications in linear amplification as well as ultrafast optical signal processing are reviewed. Finally, the possible role of quantum-dot based optical amplifiers is discussed....

  16. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    Science.gov (United States)

    Liu, Yu-Chia; Tsai, Ming-Han; Tang, Tsung-Lin; Fang, Weileun

    2011-10-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  17. A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

    Science.gov (United States)

    Zhou, Zhijun; Warr, Paul A

    2016-12-01

    Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

  18. CMOS compatible nanoscale nonvolatile resistance switching memory.

    Science.gov (United States)

    Jo, Sung Hyun; Lu, Wei

    2008-02-01

    We report studies on a nanoscale resistance switching memory structure based on planar silicon that is fully compatible with CMOS technology in terms of both materials and processing techniques employed. These two-terminal resistance switching devices show excellent scaling potential well beyond 10 Gb/cm2 and exhibit high yield (99%), fast programming speed (5 ns), high on/off ratio (10(3)), long endurance (10(6)), retention time (5 months), and multibit capability. These key performance metrics compare favorably with other emerging nonvolatile memory techniques. Furthermore, both diode-like (rectifying) and resistor-like (nonrectifying) behaviors can be obtained in the device switching characteristics in a controlled fashion. These results suggest that the CMOS compatible, nanoscale Si-based resistance switching devices may be well suited for ultrahigh-density memory applications.

  19. Spatio-temporal simulation in subthreshold CMOS

    Science.gov (United States)

    Neeley, John; Harris, John G.

    1997-05-01

    This paper reports on the design and chip measurements from a CMOS chaotic oscillator operating by itself and connected in a ring of four similar oscillators. The oscillator is autonomous and generates signals with three state variables analogous to Chua's circuit. For commensurate bandwidth, this design utilizes currents and capacitors over 200 times smaller than above threshold CMOS realizations. Also, all circuit elements are on chip. The resulting voltage-controlled bifurcation parameters simplify exploration of the circuit's dynamics, alleviating the need to interchange physical components. This combination of reduced size and variable parameters make the design suitable for single-chip VLSI synthesis of higher dimensional chaotic circuits, including coupled maps generating spatio-temporal chaos and systems exploiting chaos synchronization.

  20. Ultralow-Loss CMOS Copper Plasmonic Waveguides.

    Science.gov (United States)

    Fedyanin, Dmitry Yu; Yakubovsky, Dmitry I; Kirtaev, Roman V; Volkov, Valentyn S

    2016-01-13

    Surface plasmon polaritons can give a unique opportunity to manipulate light at a scale well below the diffraction limit reducing the size of optical components down to that of nanoelectronic circuits. At the same time, plasmonics is mostly based on noble metals, which are not compatible with microelectronics manufacturing technologies. This prevents plasmonic components from integration with both silicon photonics and silicon microelectronics. Here, we demonstrate ultralow-loss copper plasmonic waveguides fabricated in a simple complementary metal-oxide semiconductor (CMOS) compatible process, which can outperform gold plasmonic waveguides simultaneously providing long (>40 μm) propagation length and deep subwavelength (∼λ(2)/50, where λ is the free-space wavelength) mode confinement in the telecommunication spectral range. These results create the backbone for the development of a CMOS plasmonic platform and its integration in future electronic chips.

  1. Noise in a CMOS digital pixel sensor

    Institute of Scientific and Technical Information of China (English)

    Zhang Chi; Yao Suying; Xu Jiangtao

    2011-01-01

    Based on the study of noise performance in CMOS digital pixel sensor (DPS),a mathematical model of noise is established with the pulse-width-modulation (PWM) principle.Compared with traditional CMOS image sensors,the integration time is different and A/D conversion is implemented in each PWM DPS pixel.Then,the quantitative calculating formula of system noise is derived.It is found that dark current shot noise is the dominant noise source in low light region while photodiode shot noise becomes significantly important in the bright region.In this model,photodiode shot noise does not vary with luminance,but dark current shot noise does.According to increasing photodiode capacitance and the comparator's reference voltage or optimizing the mismatch in the comparator,the total noise can be reduced.These results serve as a guideline for the design of PWM DPS.

  2. Ion sources for ion implantation technology (invited)

    Energy Technology Data Exchange (ETDEWEB)

    Sakai, Shigeki, E-mail: sakai-shigeki@nissin.co.jp; Hamamoto, Nariaki; Inouchi, Yutaka; Umisedo, Sei; Miyamoto, Naoki [Nissin Ion Equipment co., ltd, 575 Kuze-Tonoshiro-cho Minami-ku, Kyoto 601-8205 (Japan)

    2014-02-15

    Ion sources for ion implantation are introduced. The technique is applied not only to large scale integration (LSI) devices but also to flat panel display. For LSI fabrication, ion source scheduled maintenance cycle is most important. For CMOS image sensor devices, metal contamination at implanted wafer is most important. On the other hand, to fabricate miniaturized devices, cluster ion implantation has been proposed to make shallow PN junction. While for power devices such as silicon carbide, aluminum ion is required. For doping processes of LCD fabrication, a large ion source is required. The extraction area is about 150 cm × 10 cm, and the beam uniformity is important as well as the total target beam current.

  3. Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

    Science.gov (United States)

    Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

    2016-02-01

    Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

  4. Cantilever-Based Biosensors in CMOS Technology

    CERN Document Server

    Kirstein, K -U; Zimmermann, M; Vancura, C; Volden, T; Song, W H; Lichtenberg, J; Hierlemannn, A

    2011-01-01

    Single-chip CMOS-based biosensors that feature microcantilevers as transducer elements are presented. The cantilevers are functionalized for the capturing of specific analytes, e.g., proteins or DNA. The binding of the analyte changes the mechanical properties of the cantilevers such as surface stress and resonant frequency, which can be detected by an integrated Wheatstone bridge. The monolithic integrated readout allows for a high signal-to-noise ratio, lowers the sensitivity to external interference and enables autonomous device operation.

  5. CMOS Design of Ternary Arithmetic Devices

    Institute of Scientific and Technical Information of China (English)

    吴训威; F.Prosser

    1991-01-01

    This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.

  6. CMOS-array design-automation techniques

    Science.gov (United States)

    Feller, A.; Lombardt, T.

    1979-01-01

    Thirty four page report discusses design of 4,096-bit complementary metal oxide semiconductor (CMOS) read-only memory (ROM). CMOSROM is either mask or laser programable. Report is divided into six sections; section one describes background of ROM chips; section two presents design goals for chip; section three discusses chip implementation and chip statistics; conclusions and recommendations are given in sections four thru six.

  7. CMOS Camera Array With Onboard Memory

    Science.gov (United States)

    Gat, Nahum

    2009-01-01

    A compact CMOS (complementary metal oxide semiconductor) camera system has been developed with high resolution (1.3 Megapixels), a USB (universal serial bus) 2.0 interface, and an onboard memory. Exposure times, and other operating parameters, are sent from a control PC via the USB port. Data from the camera can be received via the USB port and the interface allows for simple control and data capture through a laptop computer.

  8. Advanced CMOS Radiation Effects Testing and Analysis

    Science.gov (United States)

    Pellish, J. A.; Marshall, P. W.; Rodbell, K. P.; Gordon, M. S.; LaBel, K. A.; Schwank, J. R.; Dodds, N. A.; Castaneda, C. M.; Berg, M. D.; Kim, H. S.; Phan, A. M.; Seidleck, C. M.

    2014-01-01

    Presentation at the annual NASA Electronic Parts and Packaging (NEPP) Program Electronic Technology Workshop (ETW). The material includes an update of progress in this NEPP task area over the past year, which includes testing, evaluation, and analysis of radiation effects data on the IBM 32 nm silicon-on-insulator (SOI) complementary metal oxide semiconductor (CMOS) process. The testing was conducted using test vehicles supplied by directly by IBM.

  9. CMOS imagers from phototransduction to image processing

    CERN Document Server

    Etienne-Cummings, Ralph

    2004-01-01

    The idea of writing a book on CMOS imaging has been brewing for several years. It was placed on a fast track after we agreed to organize a tutorial on CMOS sensors for the 2004 IEEE International Symposium on Circuits and Systems (ISCAS 2004). This tutorial defined the structure of the book, but as first time authors/editors, we had a lot to learn about the logistics of putting together information from multiple sources. Needless to say, it was a long road between the tutorial and the book, and it took more than a few months to complete. We hope that you will find our journey worthwhile and the collated information useful. The laboratories of the authors are located at many universities distributed around the world. Their unifying theme, however, is the advancement of knowledge for the development of systems for CMOS imaging and image processing. We hope that this book will highlight the ideas that have been pioneered by the authors, while providing a roadmap for new practitioners in this field to exploit exc...

  10. Efficient design of CMOS TSC checkers

    Science.gov (United States)

    Biddappa, Anita; Shamanna, Manjunath K.; Maki, Gary; Whitaker, Sterling

    1990-01-01

    This paper considers the design of an efficient, robustly testable, CMOS Totally Self-Checking (TSC) Checker for k-out-of-2k codes. Most existing implementations use primitive gates and assume the single stuck-at fault model. The self-testing property has been found to fail for CMOS TSC checkers under the stuck-open fault model due to timing skews and arbitrary delays in the circuit. A new four level design using CMOS primitive gates (NAND, NOR, INVERTERS) is presented. This design retains its properties under the stuck-open fault model. Additionally, this method offers an impressive reduction (greater than 70 percent) in gate count, gate inputs, and test set size when compared to the existing method. This implementation is easily realizable and is based on Anderson's technique. A thorough comparative study has been made on the proposed implementation and Kundu's implementation and the results indicate that the proposed one is better than Kundu's in all respects for k-out-of-2k codes.

  11. A logarithmic low dark current CMOS pixel

    Science.gov (United States)

    Brunetti, Alessandro Michel; Choubey, Bhaskar

    2016-04-01

    High dynamic range pixels are required in a number of automotive and scientific applications. CMOS pixels provide different approaches to achieve this. However, these suffer from poor performance under low light conditions due to inherently high leakage current that is present in CMOS processes, also known as dark current. The typical approach to reduce this dark current involves process modifications. Nevertheless, energy considerations suggest that the leakage current will be close to zero at a close to zero voltage on the photodiode. Hence, the reduction in dark current can be achieved by forcing a zero voltage across the photodiode. In this paper, a novel logarithmic CMOS pixel design capable of reducing dark current without any process modifications is proposed. This pixel is also able to produce a wide dynamic range response. This circuit utilizes two current mirrors to force the in-pixel photodiode at a close to zero voltage. Additionally, a bias voltage is used to reduce a higher order effect known as Drain Induced Barrier Lowering (DIBL). In fact, the contribution of this effect can be compensated by increasing the body effect. In this paper, we studied the consequences of a negative bias voltage applied to the body of the current mirror pair to compensate for the DIBL effect thereby achieving a very small voltage drop on the photodiode and consequently, a higher sensitivity in low light conditions.

  12. Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design.

    Science.gov (United States)

    Shin, Sanghak; Choi, Jun-Myung; Cho, Seongik; Min, Kyeong-Sik

    2013-11-01

    In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.

  13. Implantable Microimagers

    Directory of Open Access Journals (Sweden)

    Jun Ohta

    2008-05-01

    Full Text Available Implantable devices such as cardiac pacemakers, drug-delivery systems, and defibrillators have had a tremendous impact on the quality of live for many disabled people. To date, many devices have been developed for implantation into various parts of the human body. In this paper, we focus on devices implanted in the head. In particular, we describe the technologies necessary to create implantable microimagers. Design, fabrication, and implementation issues are discussed vis-à-vis two examples of implantable microimagers; the retinal prosthesis and in vivo neuro-microimager. Testing of these devices in animals verify the use of the microimagers in the implanted state. We believe that further advancement of these devices will lead to the development of a new method for medical and scientific applications.

  14. Optical design of microlens array for CMOS image sensors

    Science.gov (United States)

    Zhang, Rongzhu; Lai, Liping

    2016-10-01

    The optical crosstalk between the pixel units can influence the image quality of CMOS image sensor. In the meantime, the duty ratio of CMOS is low because of its pixel structure. These two factors cause the low detection sensitivity of CMOS. In order to reduce the optical crosstalk and improve the fill factor of CMOS image sensor, a microlens array has been designed and integrated with CMOS. The initial parameters of the microlens array have been calculated according to the structure of a CMOS. Then the parameters have been optimized by using ZEMAX and the microlens arrays with different substrate thicknesses have been compared. The results show that in order to obtain the best imaging quality, when the effect of optical crosstalk for CMOS is the minimum, the best distance between microlens array and CMOS is about 19.3 μm. When incident light successively passes through microlens array and the distance, obtaining the minimum facula is around 0.347 um in the active area. In addition, when the incident angle of the light is 0o 22o, the microlens array has obvious inhibitory effect on the optical crosstalk. And the anti-crosstalk distance between microlens array and CMOS is 0 μm 162 μm.

  15. CMOS多通道芯片%CMOS Multi-Channel Chips

    Institute of Scientific and Technical Information of China (English)

    康凯; 高宗智

    2016-01-01

    In order to overcome a number of challenges in CMOS millimeter-wave integrated circuit design, the millimeter-wave device modeling, antenna design, circuit block, and multi-channel transceiver system are introduced in this paper. The equivalent-circuit models of millimeter-wave on-chip interconnected lines, multiple-coupled inductors, six-portM:N transformers, and the model of terahertz active device are studied and proposed, respectively. Moreover, a low noise amplifier with noise canceling and a power amplifier with a fully symmetrical distributed active transformer are introduced in this paper. Furthermore, the CMOS 60 GHz receiver with on-chip antenna and the multi-channel phase array transceiver are described, respectively.%针对互补金属氧化物半导体(CMOS)工艺在毫米波集成电路设计中存在的诸多挑战,分别从毫米波器件建模和天线设计,毫米波电路模块设计和多通道收发系统设计方面进行介绍,以克服相应挑战。该文研究和建立了毫米波频段片上互连线,耦合电感和六端口M:N变压器的等效模型和太赫兹有源器件模型,并对毫米波片上天线进行设计;介绍了基于噪声抵消的低噪声放大器电路和基于全对称平衡分布式有源变压器的功率放大器电路、毫米波移相器电路以及集成片上天线的CMOS 60 GHz接收机和多通道相控阵收发系统。

  16. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  17. Chaotic behaviors of operational amplifiers.

    Science.gov (United States)

    Yim, Geo-Su; Ryu, Jung-Wan; Park, Young-Jai; Rim, Sunghwan; Lee, Soo-Young; Kye, Won-Ho; Kim, Chil-Min

    2004-04-01

    We investigate nonlinear dynamical behaviors of operational amplifiers. When the output terminal of an operational amplifier is connected to the inverting input terminal, the circuit exhibits period-doubling bifurcation, chaos, and periodic windows, depending on the voltages of the positive and the negative power supplies. We study these nonlinear dynamical characteristics of this electronic circuit experimentally.

  18. Integrated VCOs for Medical Implant Transceivers

    Directory of Open Access Journals (Sweden)

    Ahmet Tekin

    2008-01-01

    Full Text Available The 402–405 MHz medical implant communication service (MICS band has recently been allocated by the US Federal Communication Commission (FCC with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.

  19. Functional outcome of auditory implants in hearing loss.

    Science.gov (United States)

    Di Girolamo, S; Saccoccio, A; Giacomini, P G; Ottaviani, F

    2007-01-01

    The auditory implant provides a new mechanism for hearing when a hearing aid is not enough. It is the only medical technology able to functionally restore a human sense i.e. hearing. The auditory implant is very different from a hearing aid. Hearing aids amplify sound. Auditory implants compensate for damaged or non-working parts of the inner ear because they can directly stimulate the acoustic nerve. There are two principal types of auditory implant: the cochlear implant and the auditory brainstem implant. They have common basic characteristics, but different applications. A cochlear implant attempts to replace a function lost by the cochlea, usually due to an absence of functioning hair cells; the auditory brainstem implant (ABI) is a modification of the cochlear implant, in which the electrode array is placed directly into the brain when the acoustic nerve is not anymore able to carry the auditory signal. Different types of deaf or severely hearing-impaired patients choose auditory implants. Both children and adults can be candidates for implants. The best age for implantation is still being debated, but most children who receive implants are between 2 and 6 years old. Earlier implantation seems to perform better thanks to neural plasticity. The decision to receive an implant should involve a discussion with many medical specialists and an experienced surgeon.

  20. Capacities of quantum amplifier channels

    Science.gov (United States)

    Qi, Haoyu; Wilde, Mark M.

    2017-01-01

    Quantum amplifier channels are at the core of several physical processes. Not only do they model the optical process of spontaneous parametric down-conversion, but the transformation corresponding to an amplifier channel also describes the physics of the dynamical Casimir effect in superconducting circuits, the Unruh effect, and Hawking radiation. Here we study the communication capabilities of quantum amplifier channels. Invoking a recently established minimum output-entropy theorem for single-mode phase-insensitive Gaussian channels, we determine capacities of quantum-limited amplifier channels in three different scenarios. First, we establish the capacities of quantum-limited amplifier channels for one of the most general communication tasks, characterized by the trade-off between classical communication, quantum communication, and entanglement generation or consumption. Second, we establish capacities of quantum-limited amplifier channels for the trade-off between public classical communication, private classical communication, and secret key generation. Third, we determine the capacity region for a broadcast channel induced by the quantum-limited amplifier channel, and we also show that a fully quantum strategy outperforms those achieved by classical coherent-detection strategies. In all three scenarios, we find that the capacities significantly outperform communication rates achieved with a naive time-sharing strategy.

  1. CMOS Imager Has Better Cross-Talk and Full-Well Performance

    Science.gov (United States)

    Pain, Bedabrata; Cunningham, Thomas J.

    2011-01-01

    A complementary metal oxide/semiconductor (CMOS) image detector now undergoing development is designed to exhibit less cross-talk and greater full-well capacity than do prior CMOS image detectors of the same type. Imagers of the type in question are designed to operate from low-voltage power supplies and are fabricated by processes that yield device features having dimensions in the deep submicron range. Because of the use of low supply potentials, maximum internal electric fields and depletion widths are correspondingly limited. In turn, these limitations are responsible for increases in cross-talk and decreases in charge-handling capacities. Moreover, for small pixels, lateral depletion cannot be extended. These adverse effects are even more accentuated in a back-illuminated CMOS imager, in which photogenerated charge carriers must travel across the entire thickness of the device. The figure shows a partial cross section of the structure in the device layer of the present developmental CMOS imager. (In a practical imager, the device layer would sit atop either a heavily doped silicon substrate or a thin silicon oxide layer on a silicon substrate, not shown here.) The imager chip is divided into two areas: area C, which contains readout circuits and other electronic circuits; and area I, which contains the imaging (photodetector and photogenerated-charge-collecting) pixel structures. Areas C and I are electrically isolated from each other by means of a trench filled with silicon oxide. The electrical isolation between areas C and I makes it possible to apply different supply potentials to these areas, thereby enabling optimization of the supply potential and associated design features for each area. More specifically, metal oxide semiconductor field-effect transistors (MOSFETs) that are typically included in CMOS imagers now reside in area C and can remain unchanged from established designs and operated at supply potentials prescribed for those designs, while the

  2. Small signal microwave amplifier design

    CERN Document Server

    Grosch, Theodore

    2000-01-01

    This book explains techniques and examples for designing stable amplifiers for high-frequency applications in which the signal is small and the amplifier circuit is linear. An in-depth discussion of linear network theory provides the foundation needed to develop actual designs. Examples throughout the book will show you how to apply the knowledge gained in each chapter leading to the complex design of low noise amplifiers. Many exercises at the end of each chapter will help students to practice their skills. The solutions to these design problems are available in an accompanying solutions book

  3. Scaling and Pixel Crosstalk Considerations for CMOS Image Sensor

    Institute of Scientific and Technical Information of China (English)

    JIN Xiang-liang; CHEN Jie(member,IEEE); QIU Yu-lin

    2003-01-01

    With the scaling development of the minimum lithographic size,the scaling trend of CMOS imager pixel size and fill factor has been computed according to the Moore rule.When the CMOS minimum lithographic feature scales down to 0.35 μm,the CCD image pixel size is not so easy to be reduced and but the CMOS image pixel size benefits from the scaling minimum lithographic feature. However, when the CMOS technology is downscaled to or under 0.35 μm,the fabrication of CMOS image sensors will be limited by the standard CMOS process in both ways of shallow trench isolation and source/drain junction,which results in pixel crosstalk.The impact of the crosstalk on the active pixel CMOS image sensor is analyzed based on the technology scaling.Some suppressed crosstalk methods have been reviewed.The best way is that combining the advantages of CMOS and SOI technology to fabricate the image sensors will reduce the pixel crosstalk.

  4. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  5. Lab-on-CMOS integration of microfluidics and electrochemical sensors.

    Science.gov (United States)

    Huang, Yue; Mason, Andrew J

    2013-10-07

    This paper introduces a CMOS-microfluidics integration scheme for electrochemical microsystems. A CMOS chip was embedded into a micro-machined silicon carrier. By leveling the CMOS chip and carrier surface to within 100 nm, an expanded obstacle-free surface suitable for photolithography was achieved. Thin film metal planar interconnects were microfabricated to bridge CMOS pads to the perimeter of the carrier, leaving a flat and smooth surface for integrating microfluidic structures. A model device containing SU-8 microfluidic mixers and detection channels crossing over microelectrodes on a CMOS integrated circuit was constructed using the chip-carrier assembly scheme. Functional integrity of microfluidic structures and on-CMOS electrodes was verified by a simultaneous sample dilution and electrochemical detection experiment within multi-channel microfluidics. This lab-on-CMOS integration process is capable of high packing density, is suitable for wafer-level batch production, and opens new opportunities to combine the performance benefits of on-CMOS sensors with lab-on-chip platforms.

  6. Charge-Transfer CMOS Image Sensors: Device and Radiation Aspects

    NARCIS (Netherlands)

    Ramachandra Rao, P.

    2009-01-01

    The aim of this thesis was twofold: investigating the effect of ionizing radiation on 4-T CMOS image sensors and the possibility of realizing a CCD like sensor in standard 0.18-μm CMOS technology (for medical applications). Both the aims are complementary; borrowing and lending many aspects of radia

  7. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.;

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process...

  8. A novel CMOS transducer for giant magnetoresistance sensors

    Science.gov (United States)

    Luong, Van Su; Lu, Chih-Cheng; Yang, Jing-Wen; Jeng, Jen-Tzong

    2017-02-01

    In this work, an ASIC (application specific integrated circuits) transducer circuit for field modulated giant magnetoresistance (GMR) sensors was designed and fabricated using a 0.18-μ m CMOS process. The transducer circuits consist of a frequency divider, a digital phase shifter, an instrument amplifier, and an analog mixer. These comprise a mix of analog and digital circuit techniques. The compact chip size of 1.5 mm × 1.5 mm for both analog and digital parts was achieved using the TSMC18 1P6M (1-polysilicon 6-metal) process design kit, and the characteristics of the system were simulated using an HSpice simulator. The output of the transducer circuit is the result of the first harmonic detection, which resolves the modulated field using a phase sensitive detection (PSD) technique and is proportional to the measured magnetic field. When the dual-bridge GMR sensor is driven by the transducer circuit with a current of 10 mA at 10 kHz, the observed sensitivity of the field sensor is 10.2 mV/V/Oe and the nonlinearity error was 3% in the linear range of ±1 Oe. The performance of the system was also verified by rotating the sensor system horizontally in earth's magnetic field and recording the sinusoidal output with respect to the azimuth angle, which exhibits an error of less than ±0.04 Oe. These results prove that the ASIC transducer is suitable for driving the AC field modulated GMR sensors applied to geomagnetic measurement.

  9. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  10. CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

    Science.gov (United States)

    Qianqian, Lei; Zhiming, Chen; Yin, Shi; Xiaojie, Chu; Zheng, Gong

    2011-10-01

    A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed. The proposed VGA uses the differential-ramp based technique, a digitally programmable gain amplifier (PGA) can be converted to an analog controlled dB-linear VGA. An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design. The proposed VGA shows a 57 dB linear range. The DC offset cancellation (DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem, respectively. The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement. Fabricated using SMIC 0.13 μm CMOS technology, this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm2 of chip area including bondpads. In addition, the DCOC circuit shows 500 Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.

  11. Area-Efficient Low Power CMOS Image Sensor Readout Circuit with Fixed Pattern Noise Cancellation

    Institute of Scientific and Technical Information of China (English)

    ZHAO Shibin; YAO Suying; NIE Kaiming; XU Jiangtao

    2010-01-01

    A low cost of die area and power consumption CMOS image sensor readout circuit with fixed pattern noise(FPN)cancellation is proposed.By using only one coupling capacitor and switch in the double FPN cancelling correlative double sampling(CDS),pixel FPN is cancelled and column FPN is stored and eliminated by the sample-and-hold operation of digitally programmable gain amplifier(DPGA).The bandwidth balance technology based on operational amplifier(op-amp)sharing is also introduced to decrease the power dissipation of traditional multi-stage switched capacitor DPGA.The circuit is designed and simulated using 1P6M 0.18 μm 1.8 V/3.3 V process.Simulation results indicate that the proposed CDS scheme can achieve an FPN of less than 1 mV.The total sampling capacitor per column is 0.9 pF and no column-wise power is dissipated.The die area and FPN value are cut by 70% and 41% respectively compared with amplifier-based CDS.The op-amp sharing gain stage can achieve a 12-bit precision and also implement an 8-bit gain controlling within a gain range of 24 dB.Its power consumption is 1.4 mW,which is reduced by 57% compared with traditional schemes.The proposed readout circuit is suitable for the application of low power cost-sensitive imaging systems.

  12. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  13. CMOS-compatible InP/InGaAs digital photoreceiver

    Science.gov (United States)

    Lovejoy, Michael L.; Rose, Benny H.; Craft, David C.; Enquist, Paul M.; Slater, Jr., David B.

    1997-01-01

    A digital photoreceiver is formed monolithically on an InP semiconductor substrate and comprises a p-i-n photodetector formed from a plurality of InP/InGaAs layers deposited by an epitaxial growth process and an adjacent heterojunction bipolar transistor (HBT) amplifier formed from the same InP/InGaAs layers. The photoreceiver amplifier operates in a large-signal mode to convert a detected photocurrent signal into an amplified output capable of directly driving integrated circuits such as CMOS. In combination with an optical transmitter, the photoreceiver may be used to establish a short-range channel of digital optical communications between integrated circuits with applications to multi-chip modules (MCMs). The photoreceiver may also be used with fiber optic coupling for establishing longer-range digital communications (i.e. optical interconnects) between distributed computers or the like. Arrays of digital photoreceivers may be formed on a common substrate for establishing a plurality of channels of digital optical communication, with each photoreceiver being spaced by less than about 1 mm and consuming less than about 20 mW of power, and preferably less than about 10 mW. Such photoreceiver arrays are useful for transferring huge amounts of digital data between integrated circuits at bit rates of up to about 1000 Mb/s or more.

  14. A 65 nm CMOS analog processor with zero dead time for future pixel detectors

    Science.gov (United States)

    Gaioni, L.; Braga, D.; Christian, D. C.; Deptuch, G.; Fahim, F.; Nodari, B.; Ratti, L.; Re, V.; Zimmerman, T.

    2017-02-01

    Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×1034 cm-2 s-1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

  15. CMOS linear-in-dB VGA with DC offset cancellation for direct-conversion receivers

    Institute of Scientific and Technical Information of China (English)

    Lei Qianqian; Chen Zhiming; Shi Yin; Chu Xiaojie; Gong Zheng

    2011-01-01

    A low-power high-linearity linear-in-dB variable gain amplifier (VGA) with novel DC offset calibration loop for direct-conversion receiver (DCR) is proposed.The proposed VGA uses the differential-ramp based technique,a digitally programmable gain amplifier (PGA) can be converted to an analog controlled dB-linear VGA.An operational amplifier (OPAMP) utilizing an improved Miller compensation approach is adopted in this VGA design.The proposed VGA shows a 57 dB linear range.The DC offset cancellation (DCOC) loop is based on a continuous-time feedback that includes the Miller effect and a linear range operation MOS transistor to realize high-value capacitors and resistors to solve the DC offset problem,respectively.The proposed approach requires no external components and demonstrates excellent DCOC capability in measurement.Fabricated using SMIC 0.13 μm CMOS technology,this VGA dissipates 4.5 mW from a 1.2 V supply voltage while occupying 0.58 mm2 of chip area including bondpads.In addition,the DCOC circuit shows 500 Hz high pass cutoff frequency (HPCF) and the measured residual DC offset at the output of VGA is less than 2 mV.

  16. CMOS biomicrosystems where electronics meets biology

    CERN Document Server

    2011-01-01

    "The book will address the-state-of-the-art in integrated Bio-Microsystems that integrate microelectronics with fluidics, photonics, and mechanics. New exciting opportunities in emerging applications that will take system performance beyond offered by traditional CMOS based circuits are discussed in detail. The book is a must for anyone serious about microelectronics integration possibilities for future technologies. The book is written by top notch international experts in industry and academia. The intended audience is practicing engineers with electronics background that want to learn about integrated microsystems. The book will be also used as a recommended reading and supplementary material in graduate course curriculum"--

  17. An Approach for Low Power CMOS Design

    Directory of Open Access Journals (Sweden)

    Ravindra kumar chejara

    2015-03-01

    Full Text Available Power dissipation has emerged an important parameter in design of Low Power CMOS circuits. For this level converter and dual supply voltage assignments are used to reduce the power dissipation and propagation delay. In this paper, variable supply-voltage scheme (dual-VS scheme for dual power supplies along with voltage level converter is presented. Also paper presents an overall comparative analysis among various methods to achieve voltage level shifter even in lower technology comparative to higher ones and help user to select the best methods for same at this technology.

  18. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  19. RF Circuit Design in Nanometer CMOS

    OpenAIRE

    Nauta, Bram

    2007-01-01

    With CMOS technology entering the nanometer regime, the design of analog and RF circuits is complicated by low supply voltages, very non-linear (and nonquadratic) devices and large 1/f noise. At the same time, circuits are required to operate over increasingly wide bandwidths to implement modern multi-band communication systems as these systems move toward software-defined radio. These trends in technology and system design call for a re-thinking of analog and RF circuit design in nanometer C...

  20. Method and circuitry for CMOS transconductor linearization

    OpenAIRE

    Kundur Subramaniyan, Harish; Klumperink, Eric; Srinivasan, Venkatesh; Kiaei, Ali; Nauta, Bram

    2016-01-01

    Third order distortion is reduced in a CMOS transconductor circuit that includes a first N-channel transistor and a first P-channel transistor, gates of the first N-channel transistor and the first P-channel transistor being coupled to receive an input signal. Drains of the first N-channel transistor and first P-channel transistor are coupled to an output conductor. A first degeneration resistor is coupled between a source of the first P-channel transistor and a first supply voltage and a sec...

  1. Silicon Light Emitting Devices in CMOS Technology

    Institute of Scientific and Technical Information of China (English)

    CHEN Hong-Da; LIU Hai-Jun; LIU Jin-Bin; GU Ming; HUANG Bei-Ju

    2007-01-01

    @@ Two silicon light emitting devices with different structures are realized in standard 0.35 μm complementary metal-oxide-semiconductor (CMOS) technology. They operate in reverse breakdown mode and can be turned on at 8.3 V. Output optical powers of 13.6nW and 12.1 nW are measured at 10 V and 100 mA, respectively, and both the calculated light emission intensities are more than 1 mW/cm2. The optical spectra of the two devices are between 600-790 nm with a clear peak near 760 nm.

  2. International Standardization Activities for Optical Amplifiers

    Institute of Scientific and Technical Information of China (English)

    Haruo Okamura

    2003-01-01

    International standardization activities for Optical Amplifiers at IECTC86 and ITU-T SG15 are reviewed. Current discussions include Optical Amplifier safety guideline, Reliability standard, Rest methods of Noise and PMD, Definitions of Raman amplifier parameters and OA classification.

  3. Single ion implantation in semiconductor nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Niepelt, Raphael; Johannes, Andreas; Gnauck, Martin; Slowik, Irma; Geburt, Sebastian; Ronning, Carsten [Institut fuer Festkoerperphysik, Friedrich-Schiller-Universitaet, Jena (Germany)

    2011-07-01

    Ion implantation is well established as a standard doping technique for semiconductor nanowires. The concentration of dopant atoms per area is typically determined by total beam current monitoring during the irradiation. However, at extremely low ion fluencies, it is not possible to distinguish the exact number of implanted ions in a nanometer sized structure, as the ions are distributed statistically over the irradiated area that is usually far wider than the nanostructure of interest. In our experiments we implanted electrically contacted semiconductor nanostructures that were connected to a preamplifier/amplifier setup. As with every impinging ion a certain amount of energy is deposited inside the material, one can detect signals directly induced by the ion implantation and the nanostructures themselves can act as a radiation sensor. This leads to a countable and very precisely adjustable ion dose during the implantation down to doping with single ions.

  4. Relationship between settling time and pole-zero placements for three-stage CMOS opamp

    Science.gov (United States)

    Bhanu Singh Chandrawat, Uday; Mishra, D. K.

    2011-07-01

    In this article, the effect of pole-zero placements on settling time has been analysed for a three-stage CMOS operational amplifier (opamp) with nested Miller compensation (NMC) and reversed nested Miller compensation (RNMC) schemes. In this study, optimised balancing of speed and power is done for a three-stage CMOS opamp for a given load condition (on-chip opamp). Optimum values of circuit parameters have been derived for power efficient shifting of poles and zeros. The effect of placement of poles and zeros on dynamic settling error (DSE) is analysed by means of numerical simulation using MATLAB. This analysis will be useful to ascertain the relationship between pole-zero placements and settling time. The study of the effects of compensation elements on pole-zero placements has been done to assist the circuit designers to achieve better performance. Analysis of the effect of capacitive load on pole-zero placements and DSE has been done in this study. A technique has been developed to find out the upper and lower limits of compensation capacitor that allows fast settling with low power. The validity of the analytical work has been checked by simulation using Tanner tool in 0.35-µm CMOS technology. In the case of RNMC scheme, a power dissipation of 60.17 µw and a settling time of 340 ns are achieved; the results obtained are better than the earlier reported design technique. In the case of NMC, the simulation has been done to validate the analytical analysis.

  5. CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

    Science.gov (United States)

    Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

    2016-06-01

    Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

  6. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  7. Design of high speed camera based on CMOS technology

    Science.gov (United States)

    Park, Sei-Hun; An, Jun-Sick; Oh, Tae-Seok; Kim, Il-Hwan

    2007-12-01

    The capacity of a high speed camera in taking high speed images has been evaluated using CMOS image sensors. There are 2 types of image sensors, namely, CCD and CMOS sensors. CMOS sensor consumes less power than CCD sensor and can take images more rapidly. High speed camera with built-in CMOS sensor is widely used in vehicle crash tests and airbag controls, golf training aids, and in bullet direction measurement in the military. The High Speed Camera System made in this study has the following components: CMOS image sensor that can take about 500 frames per second at a resolution of 1280*1024; FPGA and DDR2 memory that control the image sensor and save images; Camera Link Module that transmits saved data to PC; and RS-422 communication function that enables control of the camera from a PC.

  8. Operational amplifiers theory and design

    CERN Document Server

    Huijsing, Johan

    2017-01-01

    This proven textbook guides readers to a thorough understanding of the theory and design of operational amplifiers (OpAmps). The core of the book presents systematically the design of operational amplifiers, classifying them into a periodic system of nine main overall configurations, ranging from one gain stage up to four or more stages. This division enables circuit designers to recognize quickly, understand, and choose optimal configurations. Characterization of operational amplifiers is given by macro models and error matrices, together with measurement techniques for their parameters. Definitions are given for four types of operational amplifiers depending on the grounding of their input and output ports. Many famous designs are evaluated in depth, using a carefully structured approach enhanced by numerous figures. In order to reinforce the concepts introduced and facilitate self-evaluation of design skills, the author includes problems with detailed solutions, as well as simulation exercises. Provides te...

  9. Characterization of SLUG microwave amplifiers

    Science.gov (United States)

    Hoi, I.-C.; Zhu, S.; Thorbeck, T.; McDermott, R.; Mutus, J.; Jeffrey, E.; Barends, R.; Chen, Y.; Roushan, P.; Fowler, A.; Sank, D.; White, T.; Campbell, B.; Chen, Z.; Chiaro, B.; Dunsworth, A.; Kelly, J.; Megrant, A.; Neill, C.; O'Malley, P. J. J.; Quintana, C.; Vainsencher, A.; Wenner, J.; Martinis, J. M.

    2015-03-01

    With the rapid growth of superconducting circuits quantum technology, a near quantum-limited amplifier at GHz frequency is needed to enable high fidelity measurements. We describe such an amplifier, the SQUID based, superconducting low inductance undulatory galvanometer (SLUG) amplifier. We measure the full scattering matrix of the SLUG. In particular, we measure both forward and reverse gain, as well as reflection. We see 15dB forward gain with added noise from one quanta to several quanta. The -1 dB compression point is around -95 dBm, about two orders of magnitude higher than that of typical Josephson parametric amplifiers. With these properties, SLUG is well suited for the high fidelity, simultaneous multiplexed readout of superconducting qubits.

  10. New Packaging for Amplifier Slabs

    Energy Technology Data Exchange (ETDEWEB)

    Riley, M. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Thorsness, C. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Suratwala, T. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Steele, R. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Rogowski, G. [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

    2015-03-18

    The following memo provides a discussion and detailed procedure for a new finished amplifier slab shipping and storage container. The new package is designed to maintain an environment of <5% RH to minimize weathering.

  11. A Transformer Class E Amplifier

    Directory of Open Access Journals (Sweden)

    Mikolajewski Miroslaw

    2014-12-01

    Full Text Available In a high-efficiency Class E ZVS resonant amplifier a matching and isolation transformer can replace some or even all inductive components of the amplifier thus simplifying the circuit and reducing its cost. In the paper a theoretical analysis, a design example and its experimental verification for a transformer Class E amplifier are presented. In the experimental amplifier with a transformer as the only inductive component in the circuit high efficiency ηMAX = 0.95 was achieved for supply voltage VI = 36 V, maximum output power POMAX = 100 W and the switching frequency f = 300 kHz. Measured parameters and waveforms showed a good agreement with theoretical predictions. Moreover, the relative bandwidth of the switching frequency was only 19% to obtain output power control from 4.8 W to POMAX with efficiency not less than 0.9 in the regulation range.

  12. PID Controller with Operational Amplifier

    Directory of Open Access Journals (Sweden)

    Cristian Paul Chioncel

    2009-01-01

    Full Text Available The paper presents a PID controller made with LM741 operational amplifier that implement the PID controllers laws and allow for a widerange of applications of in the field of automatic control of technicalprocesses and systems.

  13. TARC: Carlo Rubbia's Energy Amplifier

    CERN Multimedia

    Laurent Guiraud

    1997-01-01

    Transmutation by Adiabatic Resonance Crossing (TARC) is Carlo Rubbia's energy amplifier. This CERN experiment demonstrated that long-lived fission fragments, such as 99-TC, can be efficiently destroyed.

  14. A KIND OF NEW AMPLIFIER

    Institute of Scientific and Technical Information of China (English)

    YIN XUN-HE; FENG RU-PENG; REN YONG

    2000-01-01

    Chaotic characteristics in the iteration of logistic map (one-dimensional discrete dynamic system) are simulatedand analyzed. The circuit implementation of a kind of chaotic amplifier model is based on the chaotic characteristicsthat chaos is sensitively dependent on its initial conditions, and the circuit simulation result is given using simulationprogram with integrated circuit emphasis for personal computer (PSPICE), and is compared with linear amplifier.Advantages and disadvantages of such a model are indicated.

  15. Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

    Directory of Open Access Journals (Sweden)

    Pankiewicz Bogdan

    2017-03-01

    Full Text Available In this paper a programmable input mode instrumentation amplifier (IA utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA, which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC. IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

  16. Efficient Slew-Rate Enhanced Operational Transconductance Amplifier

    Institute of Scientific and Technical Information of China (English)

    Xiao-Peng Wan; Fei-Xiang Zhang; Shao-Wei Zhen; Ya-Juan He; Ping Luo

    2015-01-01

    Abstract⎯Today, along with the prevalent use of portable equipment, wireless, and other battery powered systems, the demand for amplifiers with a high gain-bandwidth product (GBW), slew rate (SR), and at the same time very low static power dissipation is growing. In this work, an operational transconductance amplifier (OTA) with an enhanced SR is proposed. By inserting a sensing resistor in the input port of the current mirror in the OTA, the voltage drop across the resistor is converted into an output current containing a term in proportion to the square of the voltage, and then the SR of the proposed OTA is significantly enhanced and the current dissipation can be reduced. The proposed OTA is designed and simulated with a 0.5μm complementary metal oxide semiconductor (CMOS) process. The simulation results show that the SR is 4.54 V/μs, increased by 8.25 times than that of the conventional design, while the current dissipation is only 87.3%.

  17. Towards a generic operational amplifier with dynamic reconfiguration capability

    Directory of Open Access Journals (Sweden)

    S. K. Lakshmanan

    2006-01-01

    Full Text Available Analog and analog-digital mixed signal electronics needed for sensor systems are indispensable components which tend to drifts from the normal phase of operation due to the impact of manufacturing conditions and environmental influences like etching, aging etc. Precise design methodology, trimming / calibration are essential to restore functionality of the system. Recent block level granular approaches using Field Programmable Analog Array and the more recent approaches from evolutionary electronics providing transistor level granularity using Field Programmable Transistor Arrays offers considerable extensions. In our work, we started on a new medium granular level approach called Field Programmable medium-granular Mixed-signal Array (FPMA providing basic building blocks of heterogeneous array of active and passive devices to configure established circuit structures which are adaptive, biologically inspired and dynamically re-configurable. Our design objective is to create components of clear compatibility to that of the industrial standards having predictable behavior along with the incorporation of existing design knowledge. The cells can be used in as a single instance or multiple instances. Further, we will focus on a generic dynamic reconfigurable amplifier cell with flexible topology and dimension called Generic Operational Amplifier (GOPA. The incentive of our work comes from recent development in the field of measurement and instrumentation. The digital programming of analog devices is carried out using range of algorithms from simple to evolutionary. Physical realization of the basic cells is carried out in 0.35 μm CMOS technology.

  18. High-Gm Differential Regulated Cascode Transimpedance Amplifier

    Institute of Scientific and Technical Information of China (English)

    谢生; 陶希子; 毛陆虹; 高谦; 吴思聪

    2016-01-01

    A differential cross-coupled regulated cascode(RGC)transimpedance amplifier(TIA)is proposed. The theory of multi-stage common-source(CS) configuration as an auxiliary amplifier to enhance the bandwidth and output impedance of RGC topology is analyzed. Additionally, negative Miller capacitance and shunt active inductor compensation are exploited to further expand the bandwidth. The proposed RGC TIA is simulated based on UMC 0.18μm standard CMOS process. The simulation results demonstrate that the proposed TIA has a high transim-pedance of 60.5 dBΩ, and a-3 dB bandwidth of 5.4 GHz is achieved for 0.5 pF input capacitance. The average equivalent input noise current spectral density is about 20 pA/Hz1/2 in the interested frequency, and the TIA con-sumes 20 mW DC power under 1.8 V supply voltage. The voltage swing is 460 mVpp, and the saturation input cur-rent is 500μA.

  19. Theoretical performance analysis for CMOS based high resolution detectors.

    Science.gov (United States)

    Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2013-03-06

    High resolution imaging capabilities are essential for accurately guiding successful endovascular interventional procedures. Present x-ray imaging detectors are not always adequate due to their inherent limitations. The newly-developed high-resolution micro-angiographic fluoroscope (MAF-CCD) detector has demonstrated excellent clinical image quality; however, further improvement in performance and physical design may be possible using CMOS sensors. We have thus calculated the theoretical performance of two proposed CMOS detectors which may be used as a successor to the MAF. The proposed detectors have a 300 μm thick HL-type CsI phosphor, a 50 μm-pixel CMOS sensor with and without a variable gain light image intensifier (LII), and are designated MAF-CMOS-LII and MAF-CMOS, respectively. For the performance evaluation, linear cascade modeling was used. The detector imaging chains were divided into individual stages characterized by one of the basic processes (quantum gain, binomial selection, stochastic and deterministic blurring, additive noise). Ranges of readout noise and exposure were used to calculate the detectors' MTF and DQE. The MAF-CMOS showed slightly better MTF than the MAF-CMOS-LII, but the MAF-CMOS-LII showed far better DQE, especially for lower exposures. The proposed detectors can have improved MTF and DQE compared with the present high resolution MAF detector. The performance of the MAF-CMOS is excellent for the angiography exposure range; however it is limited at fluoroscopic levels due to additive instrumentation noise. The MAF-CMOS-LII, having the advantage of the variable LII gain, can overcome the noise limitation and hence may perform exceptionally for the full range of required exposures; however, it is more complex and hence more expensive.

  20. TOFFEE: a full custom amplifier-comparator chip for timing applications with silicon detectors

    Science.gov (United States)

    Cenna, F.; Cartiglia, N.; Di Francesco, A.; Olave, J.; Da Rocha Rolo, M.; Rivetti, A.; Silva, J. C.; Silva, R.; Varela, J.

    2017-03-01

    We report on the design of a full custom amplifier-comparator readout chip for silicon detectors with internal gain designed for precise timing applications. The ASIC has been developed in UMC 110 nm CMOS technology and is aimed to fulfill the CMS-TOTEM Precision Proton Spectrometer (CT-PPS) time resolution requirements (~ 30 ps per detector plane). It features LVDS outputs and the signal dynamic range matches the requirements of the High Precision TDC (HPTDC) system. The preliminary measurements results with a test board are included.

  1. A noble track-and-hold amplifier with 10-b 120-MS/s

    Science.gov (United States)

    Seon, J. K.

    2010-07-01

    A novel track-and-hold (T&H) employing an operational transconductance amplifier (OTA) with two cross-coupled differential pairs (CCDPs) is proposed for high-accuracy and high-frequency applications. The T&H has a simple architecture requiring smaller capacitors and fewer switches and offers higher speed, lower distortion and lower power dissipation than its op-amp-based counterparts. The chip implemented in 0.18 μm CMOS process operates from a single 1.8 V supply and achieves more than 10-bits precision for sampling rate in excess of 120 MS/s.

  2. An audio FIR-DAC in a BCD process for high power Class-D amplifiers

    OpenAIRE

    Doorn, T.S.; Tuijl, van, B.A.J.; Schinkel, D.; Annema, A.J.; Berkhout, M.; Nauta, B.

    2005-01-01

    A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant nature of this PWM-signal. An impulse response with only positive coefficients was chosen, because of its resistance to deadzone and mismatch. With a DAC current of 0.5 mA, the dynamic range is 111 dB (...

  3. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    Science.gov (United States)

    Carniti, P.; De Matteis, M.; Giachero, A.; Gotti, C.; Maino, M.; Pessina, G.

    2012-11-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 μm CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke- (1.2 fC) with an input capacitance of 3.3 pF. With this value of input capacitance a timing resolution down to 10 ps RMS was measured for pulser signals of a few million electrons, corresponding to the single photon response for these detectors.

  4. CLARO-CMOS, a very low power ASIC for fast photon counting with pixellated photodetectors

    CERN Document Server

    Carniti, Paolo

    2012-01-01

    The CLARO-CMOS is an application specific integrated circuit (ASIC) designed for fast photon counting with pixellated photodetectors such as multi-anode photomultiplier tubes (Ma-PMT), micro-channel plates (MCP), and silicon photomultipliers (SiPM). The first prototype has four channels, each with a charge sensitive amplifier with settable gain and a discriminator with settable threshold, providing fast hit information for each channel independently. The design was realized in a long-established, stable and inexpensive 0.35 um CMOS technology, and provides outstanding performance in terms of speed and power dissipation. The prototype consumes less than 1 mW per channel at low rate, and less than 2 mW at an event rate of 10 MHz per channel. The recovery time after each pulse is less than 25 ns for input signals within a factor of 10 above threshold. Input referred RMS noise is about 7.7 ke^- (1.2 fC) with an input capacitance of 3.3 pF. Thanks to the low noise and high speed, a timing resolution down to 10 ps ...

  5. A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-10-01

    Full Text Available In this paper, we propose a simulation-before-test (SBT fault diagnosis methodology based on the use of afault dictionary approach. This technique allows the detection and localization of the most likely defects ofopen-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS analog integratedcircuits (ICs interconnects. The fault dictionary is built by simulating the most likely defects causing thefaults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses andthe power consumption obtained by simulation are stored in a table which constitutes the fault dictionary.In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate aconsidered defect. When testing, the circuit under test is excited with the same stimulus, and the responsesobtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full customCMOS operational amplifier is implemented in 0.25 μm technology and the most likely faults of opencircuittype are deliberately injected and simulated at the layout level.

  6. A Differential CMOS Common-Gate LNA Linearized by Cross-Coupled Post Distortion Technique

    Science.gov (United States)

    Guo, Benqing; Yang, Guomin; Bin, Xiexian

    2014-05-01

    A linearized differential common-gate CMOS low noise amplifier is proposed. The linearity is improved by a cross-coupled post distortion technique, employing auxiliary PMOS transistors in weak inversion region to cancel the third-order nonlinear currents of common-gate LNA and impair the second-order nonlinear currents of that. The negative conductance characteristic of cross-coupled auxiliary PMOS transistors improves the gain while the resulted NF is little affected. Furthermore, noise contribution and linearity deterioration from the cascode stage is eliminated by an inductor resonating with the parasitic capacitance observed at the source net of the cascode transistor. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 dB and 1.4 dB improvements in the designed frequency band, respectively. The noise figure of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

  7. SEMICONDUCTOR INTEGRATED CIRCUITS: Low power CMOS preamplifier for neural recording applications

    Science.gov (United States)

    Xu, Zhang; Weihua, Pei; Beiju, Huang; Hongda, Chen

    2010-04-01

    A fully-differential bandpass CMOS (complementary metal oxide semiconductor) preamplifier for extracellular neural recording is presented. The capacitive-coupled and capacitive-feedback topology is adopted. The preamplifier has a midband gain of 20.4 dB and a DC gain of 0. The -3 dB upper cut-off frequency of the preamplifier is 6.7 kHz. The lower cut-off frequency can be adjusted for amplifying the field or action potentials located in different bands. It has an input-referred noise of 8.2 μVrms integrated from 0.15 Hz to 6.7 kHz for recording the local field potentials and the mixed neural spikes with a power dissipation of 23.1 μW from a 3.3 V supply. A bandgap reference circuitry is also designed for providing the biasing voltage and current. The 0.22 mm2 prototype chip, including the preamplifier and its biasing circuitry, is fabricated in the 0.35-μm N-well CMOS 2P4M process.

  8. CMOS Ultrasound Transceiver Chip for High-Resolution Ultrasonic Imaging Systems.

    Science.gov (United States)

    Insoo Kim; Hyunsoo Kim; Griggio, F; Tutwiler, R L; Jackson, T N; Trolier-McKinstry, S; Kyusun Choi

    2009-10-01

    The proposed CMOS ultrasound transceiver chip will enable the development of portable high resolution, high-frequency ultrasonic imaging systems. The transceiver chip is designed for close-coupled MEMS transducer arrays which operate with a 3.3-V power supply. In addition, a transmit digital beamforming system architecture is supported in this work. A prototype chip containing 16 receive and transmit channels with preamplifiers, time-gain compensation amplifiers, a multiplexed analog-to-digital converter with 3 kB of on-chip SRAM, and 50-MHz resolution time delayed excitation pulse generators has been fabricated. By utilizing a shared A/D converter architecture, the number of A/D converter and SRAM is cut down to one, unlike typical digital beamforming systems which need 16 A/D converters for 16 receive channels. The chip was fabricated in a 0.35-mum standard CMOS process. The chip size is 10 mm(2), and its average power consumption in receive mode is approximately 270 mW with a 3.3-V power supply. The transceiver chip specifications and designs are described, as well as measured results of each transceiver component and initial pulse-echo experimental results are presented.

  9. A low-power column-parallel ADC for high-speed CMOS image sensor

    Science.gov (United States)

    Han, Ye; Li, Quanliang; Shi, Cong; Liu, Liyuan; Wu, Nanjian

    2013-08-01

    This paper presents a 10-bit low-power column-parallel cyclic analog-to-digital converter (ADC) used for high-speed CMOS image sensor (CIS). An opamp sharing technique is used to save power and area. Correlated double sampling (CDS) circuit and programmable gain amplifier (PGA) are integrated in the ADC, which avoids stand-alone circuit blocks. An offset cancellation technique is also introduced, which reduces the column fixed-pattern noise (FPN) effectively. One single channel ADC with an area less than 0.03mm2 was implemented in a 0.18μm 1P4M CMOS image sensor process. The resolution of the proposed ADC is 10-bit, and the conversion rate is 2MS/s. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.62 LSB and 2.1 LSB together with CDS, respectively. The power consumption from 1.8V supply is only 0.36mW.

  10. A LOW NOISE, HIGH-SPEED COMPENSATED CMOS OP-AMP DESIGN TECHNIQUE

    Directory of Open Access Journals (Sweden)

    SOUMYA SHATAKSHI PANDA

    2013-01-01

    Full Text Available In this paper, we have proposed a new methodology for the design of low frequency, low noise and high speed compensated CMOS op-amp which specifies open loop circuit parameters to obtain enhanced gain, settling time and closed loop stability. The op-amp which we have designed consists of an Operational Transconductance Amplifier (OTA followed by an output buffer. The OTA design involves the use of a continuous-time Common mode feedback circuit which maintains the output common voltage at the required level while maximizing the output swing and the desired compensation is done with a capacitor connected between the input and output of the buffer. The low noise high speed Op-Amp is designed using 180nm CMOS technology and exhibits 88 dB DC gain. For a parallel combination of 2 pF and 1 kΩ load, the unity gain frequency and phase margin are found to be 251 MHz and 37o respectively. Under the same load condition, the proposed compensation method results in a roughly 1.8 times increase in unity gain frequency i.e 392 MHz and a 33o improvement in the phase marginas compared to the conventional approach.

  11. High-Precision CMOS Analog Computational Circuits Based on a New Linearly Tunable OTA

    Directory of Open Access Journals (Sweden)

    A. Naderi Saatlo

    2016-06-01

    Full Text Available Implementation of CMOS current-mode analog computational circuits are presented in this paper. A new Linearly Tunable OTA is employed in a modified structure as a basic building block for implementation of the circuits either linear or nonlinear functions. The proposed trans-conductance amplifier provides a constant Gm over a wide range of input voltage which allows the implementation of high precision computational circuits including square rooting, squaring, multiplication and division functions. Layout pattern of the proposed circuit confirms that the circuit can be implemented in 102μm*69μm active area. In order to verify the performance of the circuits, the post layout simulation results are presented through the use of HSPICE and Cadence with TSMC level 49 (BSIM3v3 parameters for 0.18 μm CMOS technology, where under supply voltage of 1.8 V, the maximum relative error of the circuits within 500 µA of input range is about 11 μA (2.2 % error and the THD remains as low as 1.2 % for the worst case. Moreover, the power dissipation of the complete structure is found to be 0.66 mW.

  12. A Fault Dictionary-Based Fault Diagnosis Approach for CMOS Analog Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Mouna Karmani

    2011-09-01

    Full Text Available In this paper, we propose a simulation-before-test (SBT fault diagnosis methodology based on the use of a fault dictionary approach. This technique allows the detection and localization of the most likely defects of open-circuit type occurring in Complementary Metal–Oxide–Semiconductor (CMOS analog integrated circuits (ICs interconnects. The fault dictionary is built by simulating the most likely defects causing the faults to be detected at the layout level. Then, for each injected fault, the spectre’s frequency responses and the power consumption obtained by simulation are stored in a table which constitutes the fault dictionary.In fact, each line in the fault dictionary constitutes a fault signature used to identify and locate a considered defect. When testing, the circuit under test is excited with the same stimulus, and the responses obtained are compared to the stored ones. To prove the efficiency of the proposed technique, a full custom CMOS operational amplifier is implemented in 0.25 μm technology and the most likely faults of open circuit type are deliberately injected and simulated at the layout level.

  13. Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

    Science.gov (United States)

    Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

    2017-02-01

    The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

  14. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-01-15

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  15. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-01-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  16. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors.

    Science.gov (United States)

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-11-06

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within -T(clk)~+T(clk). A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  17. Binary CMOS image sensor with a gate/body-tied MOSFET-type photodetector for high-speed operation

    Science.gov (United States)

    Choi, Byoung-Soo; Jo, Sung-Hyun; Bae, Myunghan; Kim, Sang-Hwan; Shin, Jang-Kyoo

    2016-05-01

    In this paper, a binary complementary metal oxide semiconductor (CMOS) image sensor with a gate/body-tied (GBT) metal oxide semiconductor field effect transistor (MOSFET)-type photodetector is presented. The sensitivity of the GBT MOSFET-type photodetector, which was fabricated using the standard CMOS 0.35-μm process, is higher than the sensitivity of the p-n junction photodiode, because the output signal of the photodetector is amplified by the MOSFET. A binary image sensor becomes more efficient when using this photodetector. Lower power consumptions and higher speeds of operation are possible, compared to the conventional image sensors using multi-bit analog to digital converters (ADCs). The frame rate of the proposed image sensor is over 2000 frames per second, which is higher than those of the conventional CMOS image sensors. The output signal of an active pixel sensor is applied to a comparator and compared with a reference level. The 1-bit output data of the binary process is determined by this level. To obtain a video signal, the 1-bit output data is stored in the memory and is read out by horizontal scanning. The proposed chip is composed of a GBT pixel array (144 × 100), binary-process circuit, vertical scanner, horizontal scanner, and readout circuit. The operation mode can be selected from between binary mode and multi-bit mode.

  18. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Zhiyuan Gao

    2015-11-01

    Full Text Available This paper presents a dynamic range (DR enhanced readout technique with a two-step time-to-digital converter (TDC for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  19. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Science.gov (United States)

    Gao, Zhiyuan; Yang, Congjie; Xu, Jiangtao; Nie, Kaiming

    2015-01-01

    This paper presents a dynamic range (DR) enhanced readout technique with a two-step time-to-digital converter (TDC) for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA) structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration. PMID:26561819

  20. Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

    Science.gov (United States)

    Kleczek, Rafal

    2016-12-01

    The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.