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Sample records for implantable cmos amplifier

  1. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2001-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved. A continuous-time offset-compensation technique is utilized in order to minimize impact...... on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0.5 μm CMOS single poly, n-well process. The prototype amplifier features a gain of 80 dB over a 3.6 kHz bandwidth, a CMRR of more than 87 dB and a PSRR...

  2. An Implantable CMOS Amplifier for Nerve Signals

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Lehmann, Torsten

    2003-01-01

    In this paper, a low noise high gain CMOS amplifier for minute nerve signals is presented. The amplifier is constructed in a fully differential topology to maximize noise rejection. By using a mixture of weak- and strong inversion transistors, optimal noise suppression in the amplifier is achieved....... A continuous-time current-steering offset-compensation technique is utilized in order to minimize the noise contribution and to minimize dynamic impact on the amplifier input nodes. The method for signal recovery from noisy nerve signals is presented. A prototype amplifier is realized in a standard digital 0...

  3. Distributed CMOS Bidirectional Amplifiers Broadbanding and Linearization Techniques

    CERN Document Server

    El-Khatib, Ziad; Mahmoud, Samy A

    2012-01-01

    This book describes methods to design distributed amplifiers useful for performing circuit functions such as duplexing, paraphrase amplification, phase shifting power splitting and power combiner applications.  A CMOS bidirectional distributed amplifier is presented that combines for the first time device-level with circuit-level linearization, suppressing the third-order intermodulation distortion. It is implemented in 0.13μm RF CMOS technology for use in highly linear, low-cost UWB Radio-over-Fiber communication systems. Describes CMOS distributed amplifiers for optoelectronic applications such as Radio-over-Fiber systems, base station transceivers and picocells; Presents most recent techniques for linearization of CMOS distributed amplifiers; Includes coverage of CMOS I-V transconductors, as well as CMOS on-chip inductor integration and modeling; Includes circuit applications for UWB Radio-over-Fiber networks.

  4. Power Amplifiers in CMOS Technology: A contribution to power amplifier theory and techniques

    NARCIS (Netherlands)

    Acar, M.

    2011-01-01

    In order to meet the demands from the market on cheaper, miniaturized mobile communications devices realization of RF power amplifiers in the mainstream CMOS technology is essential. In general, CMOS Power Amplifiers (PAs) require high voltage to decrease the matching network losses and for high

  5. CMOS Current-mode Operational Amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1992-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-range ±700¿A) and a (theoretically) unlimited slew-rate. The amplifier is realized in a standard CMOS 2......A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...

  6. A CMOS current-mode operational amplifier

    DEFF Research Database (Denmark)

    Kaulberg, Thomas

    1993-01-01

    current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain-bandwidth product of 3 MHz, an offset current of 0.8 μA (signal range ±700 μA), and a (theoretically) unlimited slew rate. The amplifier is realized in a standard CMOS 2......A fully differential-input, differential-output, current-mode operational amplifier (COA) is described. The amplifier utilizes three second-generation current conveyors (CCIIs) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced...

  7. Radiation effects of protons and 60Co γ rays on CMOS operational amplifier

    International Nuclear Information System (INIS)

    Lu Wu; Ren Diyuan; Guo Qi; Yu Xuefeng; Yan Rongliang

    1997-01-01

    Radiation effects of 60 Co γ ray and 4,7 and 30 MeV protons on LF 7650 CMOS operational amplifier were investigated. The damage mechanism of LF7650 was discussed. It is indicated that the mobility reduction of major carrier caused by ionizing and displacement damage is the chief mechanism causing the failure of CMOS operational amplifier irradiated by protons, and that is why the degradation of LF 7650 caused by protons is much more serious than that caused by 60 Co γ ray. In addition, a comparison of proton radiation effects on CMOS operational amplifier and MOSFET showed a significant difference in mechanism

  8. Low-voltage CMOS operational amplifiers theory, design and implementation

    CERN Document Server

    Sakurai, Satoshi

    1995-01-01

    Low-Voltage CMOS Operational Amplifiers: Theory, Design and Implementation discusses both single and two-stage architectures. Opamps with constant-gm input stage are designed and their excellent performance over the rail-to-rail input common mode range is demonstrated. The first set of CMOS constant-gm input stages was introduced by a group from Technische Universiteit, Delft and Universiteit Twente, the Netherlands. These earlier versions of circuits are discussed, along with new circuits developed at the Ohio State University. The design, fabrication (MOSIS Tiny Chips), and characterization of the new circuits are now complete. Basic analog integrated circuit design concepts should be understood in order to fully appreciate the work presented. However, the topics are presented in a logical order and the circuits are explained in great detail, so that Low-Voltage CMOS Operational Amplifiers can be read and enjoyed by those without much experience in analog circuit design. It is an invaluable reference boo...

  9. A high efficiency PWM CMOS class-D audio power amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Zhu Zhangming; Liu Lianxi; Yang Yintang [Institute of Microelectronics, Xidian University, Xi' an 710071 (China); Lei Han, E-mail: zmyh@263.ne [Xi' an Power-Rail Micro Co., Ltd, Xi' an 710075 (China)

    2009-02-15

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 mum CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 muA. The active area of the class-D audio power amplifier is about 1.47 x 1.52 mm{sup 2}. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  10. A high efficiency PWM CMOS class-D audio power amplifier

    International Nuclear Information System (INIS)

    Zhu Zhangming; Liu Lianxi; Yang Yintang; Lei Han

    2009-01-01

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 x 1.52 mm 2 . With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  11. A high efficiency PWM CMOS class-D audio power amplifier

    Science.gov (United States)

    Zhangming, Zhu; Lianxi, Liu; Yintang, Yang; Han, Lei

    2009-02-01

    Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.

  12. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R.; Moscone, C.G.

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 microm Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results

  13. A CMOS Integrating Amplifier for the PHENIX Ring Imaging Cherenkov detector

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Jones, J.P. Jr.; Young, G.R. [Oak Ridge National Lab., TN (United States); Moscone, C.G. [Tennessee Univ., Knoxville, TN (United States)

    1997-11-01

    A CMOS integrating amplifier has been developed for use in the PHENIX Ring Imaging Cherenkov (RICH) detector. The amplifier, consisting of a charge-integrating amplifier followed by a variable gain amplifier (VGA), is an element of a photon measurement system comprising a photomultiplier tube, a wideband, gain of 10 amplifier, the integrating amplifier, and an analog memory followed by an ADC and double correlated sampling implemented in software. The integrating amplifier is designed for a nominal full scale input of 160 pC with a gain of 20 mV/pC and a dynamic range of 1000:1. The VGA is used for equalizing gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5 bits digital control, and the risetime is held to approximately 20 ns using switched compensation in the VGA. Details of the design and results from several prototype devices fabricated in 1.2 {micro}m Orbit CMOS are presented. A complete noise analysis of the integrating amplifier and the correlated sampling process is included as well as a comparison of calculated, simulated and measured results.

  14. Linear CMOS RF power amplifiers a complete design workflow

    CERN Document Server

    Ruiz, Hector Solar

    2013-01-01

    The work establishes the design flow for the optimization of linear CMOS power amplifiers from the first steps of the design to the final IC implementation and tests. The authors also focuses on design guidelines of the inductor's geometrical characteristics for power applications and covers their measurement and characterization. Additionally, a model is proposed which would facilitate designs in terms of transistor sizing, required inductor quality factors or minimum supply voltage. The model considers limitations that CMOS processes can impose on implementation. The book also provides diffe

  15. Design of CMOS CFOA Based on Pseudo Operational Transconductance Amplifier

    OpenAIRE

    Hassan Jassim Motlak

    2015-01-01

    A novel design technique employing CMOS Current Feedback Operational Amplifier (CFOA) is presented. The feature of consumption very low power in designing pseudo-OTA is used to decreasing the total power consumption of the proposed CFOA. This design approach applies pseudo-OTA as input stage cascaded with buffer stage. Moreover, the DC input offset voltage and harmonic distortion (HD) of the proposed CFOA are very low values compared with the conventional CMOS CFOA due to...

  16. Ultra-low Voltage CMOS Cascode Amplifier

    OpenAIRE

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique.

  17. Ultra-low Voltage CMOS Cascode Amplifier

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Cassia, Marco

    2000-01-01

    In this paper, we design a folded cascode operational transconductance amplifier in a standard CMOS process, which has a measured 69 dB DC gain, a 2 MHz bandwidth and compatible input- and output voltage levels at a 1 V power supply. This is done by a novel Current Driven Bulk (CDB) technique......, which reduces the MOST threshold voltage by forcing a constant current though the transistor bulk terminal. We also look at limitations and improvements of this CDB technique....

  18. Development of a CMOS process using high energy ion implantation

    International Nuclear Information System (INIS)

    Stolmeijer, A.

    1986-01-01

    The main interest of this thesis is the use of complementary metal oxide semiconductors (CMOS) in electronic technology. Problems in developing a CMOS process are mostly related to the isolation well of p-n junctions. It is shown that by using high energy ion implantation, it is possible to reduce lateral dimensions to obtain a rather high packing density. High energy ion implantation is also presented as a means of simplifying CMOS processing, since extended processing steps at elevated temperatures are superfluous. Process development is also simplified. (Auth.)

  19. Automatic Frequency Controller for Power Amplifiers Used in Bio-Implanted Applications: Issues and Challenges

    Directory of Open Access Journals (Sweden)

    Mahammad A. Hannan

    2014-12-01

    Full Text Available With the development of communication technologies, the use of wireless systems in biomedical implanted devices has become very useful. Bio-implantable devices are electronic devices which are used for treatment and monitoring brain implants, pacemakers, cochlear implants, retinal implants and so on. The inductive coupling link is used to transmit power and data between the primary and secondary sides of the biomedical implanted system, in which efficient power amplifier is very much needed to ensure the best data transmission rates and low power losses. However, the efficiency of the implanted devices depends on the circuit design, controller, load variation, changes of radio frequency coil’s mutual displacement and coupling coefficients. This paper provides a comprehensive survey on various power amplifier classes and their characteristics, efficiency and controller techniques that have been used in bio-implants. The automatic frequency controller used in biomedical implants such as gate drive switching control, closed loop power control, voltage controlled oscillator, capacitor control and microcontroller frequency control have been explained. Most of these techniques keep the resonance frequency stable in transcutaneous power transfer between the external coil and the coil implanted inside the body. Detailed information including carrier frequency, power efficiency, coils displacement, power consumption, supplied voltage and CMOS chip for the controllers techniques are investigated and summarized in the provided tables. From the rigorous review, it is observed that the existing automatic frequency controller technologies are more or less can capable of performing well in the implant devices; however, the systems are still not up to the mark. Accordingly, current challenges and problems of the typical automatic frequency controller techniques for power amplifiers are illustrated, with a brief suggestions and discussion section concerning

  20. Automatic Frequency Controller for Power Amplifiers Used in Bio-Implanted Applications: Issues and Challenges

    Science.gov (United States)

    Hannan, Mahammad A.; Hussein, Hussein A.; Mutashar, Saad; Samad, Salina A.; Hussain, Aini

    2014-01-01

    With the development of communication technologies, the use of wireless systems in biomedical implanted devices has become very useful. Bio-implantable devices are electronic devices which are used for treatment and monitoring brain implants, pacemakers, cochlear implants, retinal implants and so on. The inductive coupling link is used to transmit power and data between the primary and secondary sides of the biomedical implanted system, in which efficient power amplifier is very much needed to ensure the best data transmission rates and low power losses. However, the efficiency of the implanted devices depends on the circuit design, controller, load variation, changes of radio frequency coil's mutual displacement and coupling coefficients. This paper provides a comprehensive survey on various power amplifier classes and their characteristics, efficiency and controller techniques that have been used in bio-implants. The automatic frequency controller used in biomedical implants such as gate drive switching control, closed loop power control, voltage controlled oscillator, capacitor control and microcontroller frequency control have been explained. Most of these techniques keep the resonance frequency stable in transcutaneous power transfer between the external coil and the coil implanted inside the body. Detailed information including carrier frequency, power efficiency, coils displacement, power consumption, supplied voltage and CMOS chip for the controllers techniques are investigated and summarized in the provided tables. From the rigorous review, it is observed that the existing automatic frequency controller technologies are more or less can capable of performing well in the implant devices; however, the systems are still not up to the mark. Accordingly, current challenges and problems of the typical automatic frequency controller techniques for power amplifiers are illustrated, with a brief suggestions and discussion section concerning the progress of

  1. Study of built-in amplifier performance on HV-CMOS sensor for the ATLAS phase-II strip tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Liang, Z., E-mail: zhijun.liang@cern.ch [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Institute of High Energy Physics, Beijing (China); Affolder, A. [University of Liverpool (United Kingdom); Arndt, K. [University of Oxford (United Kingdom); Bates, R. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Benoit, M.; Di Bello, F. [University of Geneva (Switzerland); Blue, A. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Bortoletto, D. [University of Oxford (United Kingdom); Buckland, M. [University of Liverpool (United Kingdom); CERN, European Center for Nuclear Research (Switzerland); Buttar, C. [SUPA – School of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Caragiulo, P. [SLAC National Accelerator Laboratory (United States); Das, D.; Dopke, J. [Rutherford Appleton Laboratory, Didcot (United Kingdom); Dragone, A. [SLAC National Accelerator Laboratory (United States); Ehrler, F. [Karlsruhe Institute of Technology (Germany); Fadeyev, V.; Galloway, Z.; Grabas, H. [University of California Santa Cruz, Santa Cruz Institute for Particle Physics (SCIPP) (United States); Gregor, I.M. [Deutsches Elektronen-Synchrotron (Germany); Grenier, P. [SLAC National Accelerator Laboratory (United States); and others

    2016-09-21

    This paper focuses on the performance of analog readout electronics (built-in amplifier) integrated on the high-voltage (HV) CMOS silicon sensor chip, as well as its radiation hardness. Since the total collected charge from minimum ionizing particle (MIP) for the CMOS sensor is 10 times lower than for a conventional planar sensor, it is crucial to integrate a low noise built-in amplifier on the sensor chip to improve the signal to noise ratio of the system. As part of the investigation for the ATLAS strip detector upgrade, a test chip that comprises several pixel arrays with different geometries, as well as standalone built-in amplifiers and built-in amplifiers in pixel arrays has been fabricated in a 0.35 μm high-voltage CMOS process. Measurements of the gain and the noise of both the standalone amplifiers and built-in amplifiers in pixel arrays were performed before and after gamma radiation of up to 60 Mrad. Of special interest is the variation of the noise as a function of the sensor capacitance. We optimized the configuration of the amplifier for a fast rise time to adapt to the LHC bunch crossing period of 25 ns, and measured the timing characteristics including jitter. Our results indicate an adequate amplifier performance for monolithic structures used in HV-CMOS technology. The results have been incorporated in the next submission of a large-structure chip.

  2. Design of a Programmable Gain, Temperature Compensated Current-Input Current-Output CMOS Logarithmic Amplifier.

    Science.gov (United States)

    Ming Gu; Chakrabartty, Shantanu

    2014-06-01

    This paper presents the design of a programmable gain, temperature compensated, current-mode CMOS logarithmic amplifier that can be used for biomedical signal processing. Unlike conventional logarithmic amplifiers that use a transimpedance technique to generate a voltage signal as a logarithmic function of the input current, the proposed approach directly produces a current output as a logarithmic function of the input current. Also, unlike a conventional transimpedance amplifier the gain of the proposed logarithmic amplifier can be programmed using floating-gate trimming circuits. The synthesis of the proposed circuit is based on the Hart's extended translinear principle which involves embedding a floating-voltage source and a linear resistive element within a translinear loop. Temperature compensation is then achieved using a translinear-based resistive cancelation technique. Measured results from prototypes fabricated in a 0.5 μm CMOS process show that the amplifier has an input dynamic range of 120 dB and a temperature sensitivity of 230 ppm/°C (27 °C- 57°C), while consuming less than 100 nW of power.

  3. Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

    Directory of Open Access Journals (Sweden)

    Abdelhamid Benazzouz

    2013-09-01

    Full Text Available Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-gain, low-noise integrated neuronal amplifier (NA with the capability of recording local field potentials (LFP and spike activity is presented. In vitro and in vivo characterizations of the tissue/electrode interface, with equivalent impedance as an electrical model for recording in the LFP band using macro-electrodes for rodents, contribute to the NA design constraints. The NA occupies 0.15 mm2 and dissipates 6.73 µW, and was fabricated using a 0.35 µm CMOS process. Test-bench validation indicates that the NA provides a mid-band gain of 20 dB and achieves a low input-referred noise of 4 µVRMS. Ability of the NA to perform spike recording in test-bench experiments is presented. Additionally, an awake and freely moving rodent setup was used to illustrate the integrated NA ability to record LFPs, paving the pathway for future implantable systems for neuromodulation.

  4. CMOS image sensor-based implantable glucose sensor using glucose-responsive fluorescent hydrogel.

    Science.gov (United States)

    Tokuda, Takashi; Takahashi, Masayuki; Uejima, Kazuhiro; Masuda, Keita; Kawamura, Toshikazu; Ohta, Yasumi; Motoyama, Mayumi; Noda, Toshihiko; Sasagawa, Kiyotaka; Okitsu, Teru; Takeuchi, Shoji; Ohta, Jun

    2014-11-01

    A CMOS image sensor-based implantable glucose sensor based on an optical-sensing scheme is proposed and experimentally verified. A glucose-responsive fluorescent hydrogel is used as the mediator in the measurement scheme. The wired implantable glucose sensor was realized by integrating a CMOS image sensor, hydrogel, UV light emitting diodes, and an optical filter on a flexible polyimide substrate. Feasibility of the glucose sensor was verified by both in vitro and in vivo experiments.

  5. An NFC-Enabled CMOS IC for a Wireless Fully Implantable Glucose Sensor.

    Science.gov (United States)

    DeHennis, Andrew; Getzlaff, Stefan; Grice, David; Mailand, Marko

    2016-01-01

    This paper presents an integrated circuit (IC) that merges integrated optical and temperature transducers, optical interface circuitry, and a near-field communication (NFC)-enabled digital, wireless readout for a fully passive implantable sensor platform to measure glucose in people with diabetes. A flip-chip mounted LED and monolithically integrated photodiodes serve as the transduction front-end to enable fluorescence readout. A wide-range programmable transimpedance amplifier adapts the sensor signals to the input of an 11-bit analog-to-digital converter digitizing the measurements. Measurement readout is enabled by means of wireless backscatter modulation to a remote NFC reader. The system is able to resolve current levels of less than 10 pA with a single fluorescent measurement energy consumption of less than 1 μJ. The wireless IC is fabricated in a 0.6-μm-CMOS process and utilizes a 13.56-MHz-based ISO15693 for passive wireless readout through a NFC interface. The IC is utilized as the core interface to a fluorescent, glucose transducer to enable a fully implantable sensor-based continuous glucose monitoring system.

  6. Implantable optogenetic device with CMOS IC technology for simultaneous optical measurement and stimulation

    Science.gov (United States)

    Haruta, Makito; Kamiyama, Naoya; Nakajima, Shun; Motoyama, Mayumi; Kawahara, Mamiko; Ohta, Yasumi; Yamasaki, Atsushi; Takehara, Hiroaki; Noda, Toshihiko; Sasagawa, Kiyotaka; Ishikawa, Yasuyuki; Tokuda, Takashi; Hashimoto, Hitoshi; Ohta, Jun

    2017-05-01

    In this study, we have developed an implantable optogenetic device that can measure and stimulate neurons by an optical method based on CMOS IC technology. The device consist of a blue LED array for optically patterned stimulation, a CMOS image sensor for acquiring brain surface image, and eight green LEDs surrounding the CMOS image sensor for illumination. The blue LED array is placed on the CMOS image sensor. We implanted the device in the brain of a genetically modified mouse and successfully demonstrated the stimulation of neurons optically and simultaneously acquire intrinsic optical images of the brain surface using the image sensor. The integrated device can be used for simultaneously measuring and controlling neuronal activities in a living animal, which is important for the artificial control of brain functions.

  7. Design of CMOS Tunable Image-Rejection Low-Noise Amplifier with Active Inductor

    Directory of Open Access Journals (Sweden)

    Ler Chun Lee

    2008-01-01

    Full Text Available A fully integrated CMOS tunable image-rejection low-noise amplifier (IRLNA has been designed using Silterra's industry standard 0.18 μm RF CMOS process. The notch filter is designed using an active inductor. Measurement results show that the notch filter designed using active inductor contributes additional 1.19 dB to the noise figure of the low-noise amplifier (LNA. A better result is possible if the active inductor is optimized. Since active inductors require less die area, the die area occupied by the IRLNA is not significantly different from a conventional LNA, which was designed for comparison. The proposed IRLNA exhibits S21 of 11.8 dB, S11 of −17.8 dB, S22 of −10.7 dB, and input 1 dB compression point of −12 dBm at 3 GHz

  8. Tunable Balun Low-Noise Amplifier in 65nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    J. Sturm

    2014-04-01

    Full Text Available The presented paper includes the design and implementation of a 65 nm CMOS low-noise amplifier (LNA based on inductive source degeneration. The amplifier is realized with an active balun enabling a single-ended input which is an important requirement for low-cost system on chip implementations. The LNA has a tunable bandpass characteristics from 4.7 GHz up to 5.6 GHz and a continuously tunable gain from 22 dB down to 0 dB, which enables the required flexibility for multi-standard, multi-band receiver architectures. The gain and band tuning is realized with an optimized tunable active resistor in parallel to a tunable L-C tank amplifier load. The amplifier achieves an IIP3 linearity of -8dBm and a noise figure of 2.7 dB at the highest gain and frequency setting with a low power consumption of 10 mW. The high flexibility of the proposed LNA structure together with the overall good performance makes it well suited for future multi-standard low-cost receiver front-ends.

  9. An RF Power Amplifier in a Digital CMOS Process

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck; Fallesen, Carsten

    2002-01-01

    A two stage class B power amplifier for 1.9 GHz is presented. The amplifier is fabricated in a standard digital EPI-CMOS process with low resistivity substrate. The measured output power is 29 dBm in a 50 Omega load. A design method to find the large signal parameters of the output transistor...... is presented. It separates the determination of the optimal load resistance and the determination of the large signal drain-source capacitance. Based on this method, proper values for on-chip interstage matching and off-chip output matching can be derived. A envelope linearisation circuit for the PA...... is proposed. Simulations and measurements of a fabricated linearisation circuit are presented and used to calculate the achievable linearity in terms of the spectral leakage and the error vector magnitude of a EDGE (3 pi /8-8PSK) modulated signal....

  10. Design Considerations for CMOS Current Mode Operational Amplifiers and Current Conveyors

    DEFF Research Database (Denmark)

    Bruun, Erik

    implementations of current mode opamps in CMOS technology are described. Also, current conveyor configurations with multiple outputs and flexible feedback connections from outputs to inputs are introduced. The dissertation includes several examples of circuit configurations ranging from simple class A and class......This dissertation is about CMOS current conveyors and current mode operational amplifiers (opamps). They are generic devices for continuous time signal processing in circuits and systems where signals are represented by currents.Substantial advancements are reported in the dissertation, both...... related to circuit implementations and system configurations and to an analysis of the fundamental limitations of the current mode technique.In the field of system configurations and circuit implementations different configurations of high gain current opamps are introduced and some of the first...

  11. A photovoltaic-driven and energy-autonomous CMOS implantable sensor.

    Science.gov (United States)

    Ayazian, Sahar; Akhavan, Vahid A; Soenen, Eric; Hassibi, Arjang

    2012-08-01

    An energy-autonomous, photovoltaic (PV)-driven and MRI-compatible CMOS implantable sensor is presented. On-chip P+/N-well diode arrays are used as CMOS-compatible PV cells to harvest μW's of power from the light that penetrates into the tissue. In this 2.5 mm × 2.5 mm sub-μW integrated system, the in-vivo physiological signals are first measured by using a subthreshold ring oscillator-based sensor, the acquired data is then modulated into a frequency-shift keying (FSK) signal, and finally transmitted neuromorphically to the skin surface by using a pair of polarized electrodes.

  12. Low Voltage CMOS Fully Differential Current Feedback Amplifier with Controllable 3-dB Bandwidth

    International Nuclear Information System (INIS)

    Madian, A.H.; Mahmoud, S.A.; Ashour, M.A.; Soliman, A.M.

    2008-01-01

    This paper presents a new CMOS fully differential current feedback operational amplifier with controllable 3-dB bandwidth suitable for analog data processing and acquisition applications. The FDCFOA has the advantage of a wide range controllable 3-dB bandwidth (∼57 MHz to 500 MHz) without changing the feedback resistance this guarantee the stability of the circuit. The FDCFOA has a standby current of 320μA. PSpice simulations of the FDCFOA block were given using 0.25μm CMOS technology from AMI MOSIS and dual supply voltages ±0.75 V

  13. High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers

    Directory of Open Access Journals (Sweden)

    F. Touati

    2007-12-01

    Full Text Available High gain, wide bandwidth, low noise, and low-power transimpedance amplifiers based on new BiCMOS common- base topologies have been designed for fiber-optic receivers. In particular a design approach, hereafter called "A more- FET approach", added a new dimension to effectively optimize performance tradeoffs inherent in such circuits. Using conventional silicon 0.8 μm process parameters, simulated performance features of a total-FET transimpedance amplifier operating at 7.2 GHz, which is close to the technology fT of 12 GHz, are presented. The results are superior to those of similar recent designs and comparable to IC designs using GaAs technology. A detailed analysis of the design architecture, including a discussion on the effects of moving toward more FET-based designs is presented.

  14. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Gao Tongqiang [Department of Electronics, Tsinghua University, Beijing 100084 (China); Zhang Chun; Chi Baoyong; Wang Zhihua, E-mail: gtq03@mails.tsinghua.edu.c [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-06-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-mum CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  15. Design and analysis of a highly-integrated CMOS power amplifier for RFID readers

    International Nuclear Information System (INIS)

    Gao Tongqiang; Zhang Chun; Chi Baoyong; Wang Zhihua

    2009-01-01

    To implement a fully-integrated on-chip CMOS power amplifier (PA) for RFID readers, the resonant frequency of each matching network is derived in detail. The highlight of the design is the adoption of a bonding wire as the output-stage inductor. Compared with the on-chip inductors in a CMOS process, the merit of the bondwire inductor is its high quality factor, leading to a higher output power and efficiency. The disadvantage of the bondwire inductor is that it is hard to control. A highly integrated class-E PA is implemented with 0.18-μm CMOS process. It can provide a maximum output power of 20 dBm and a 1 dB output power of 14.5 dBm. The maximum power-added efficiency (PAE) is 32.1%. Also, the spectral performance of the PA is analyzed for the specified RFID protocol.

  16. A high-speed low-noise transimpedance amplifier in a 025 mum CMOS technology

    CERN Document Server

    Anelli, G; Casagrande, L; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4fC, an input capacitance of 4pF and a transresistance of 135kOmega, we have measured an output pulse fall time of 3ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the constructio...

  17. An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin' an, E-mail: wangxa@szpku.edu.c [Key Laboratory of Integrated Microsystems, Shenzhen Graduate School of Peking University, Shenzhen 518055 (China)

    2009-06-01

    One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 mum{sup 2} without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

  18. An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

    International Nuclear Information System (INIS)

    Feng Xiaoxing; Zhang Xing; Ge Binjie; Wang Xin'an

    2009-01-01

    One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 x 200 μm 2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

  19. Design and simulation of Gaussian shaping amplifier made only with CMOS FET for FEE of particle detector

    International Nuclear Information System (INIS)

    Wembe Tafo Evariste; Su Hong; Qian Yi; Kong Jie; Wang Tongxi

    2010-01-01

    The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip, Si (Li), CdZnTe and CsI detectors, etc., which can be further integrated the whole system and adopted to develop CMOS-based application, specific integrated circuit for Front End Electronics (FEE) of read-out system of nuclear physics, particle physics and astrophysics research, etc. It's why we used only CMOS transistor to develop the entire system. A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC 4 filter, we perform shaping time in the range, 465 ns to 2.76μs with a low output resistance and the linearity almost good. (authors)

  20. EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

    Science.gov (United States)

    Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

    2003-10-01

    We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM.

  1. EROIC: a BiCMOS pseudo-gaussian shaping amplifier for high-resolution X-ray spectroscopy

    International Nuclear Information System (INIS)

    Buzzetti, Siro; Guazzoni, Chiara; Longoni, Antonio

    2003-01-01

    We present the design and complete characterization of a fifth-order pseudo-gaussian shaping amplifier with 1 μs shaping time. The circuit is optimized for the read-out of signals coming from Silicon Drift Detectors for high-resolution X-ray spectroscopy. The novelty of the designed chip stands in the use of a current feedback loop to place the poles in the desired position on the s-plane. The amplifier has been designed in 0.8 μm BiCMOS technology and fully tested. The EROIC chip comprises also the peak stretcher, the peak detector, the output buffer to drive the external ADC and the pile-up rejection system. The circuit needs a single +5 V power supply and the dissipated power is 5 mW per channel. The digital outputs can be directly coupled to standard digital CMOS ICs. The measured integral-non-linearity of the whole chip is below 0.05% and the achieved energy resolution at the Mn Kα line detected by a 5 mm 2 Peltier-cooled Silicon Drift Detector is 167 eV FWHM

  2. A high-frequency transimpedance amplifier for CMOS integrated 2D CMUT array towards 3D ultrasound imaging.

    Science.gov (United States)

    Huang, Xiwei; Cheong, Jia Hao; Cha, Hyouk-Kyu; Yu, Hongbin; Je, Minkyu; Yu, Hao

    2013-01-01

    One transimpedance amplifier based CMOS analog front-end (AFE) receiver is integrated with capacitive micromachined ultrasound transducers (CMUTs) towards high frequency 3D ultrasound imaging. Considering device specifications from CMUTs, the TIA is designed to amplify received signals from 17.5MHz to 52.5MHz with center frequency at 35MHz; and is fabricated in Global Foundry 0.18-µm 30-V high-voltage (HV) Bipolar/CMOS/DMOS (BCD) process. The measurement results show that the TIA with power-supply 6V can reach transimpedance gain of 61dBΩ and operating frequency from 17.5MHz to 100MHz. The measured input referred noise is 27.5pA/√Hz. Acoustic pulse-echo testing is conducted to demonstrate the receiving functionality of the designed 3D ultrasound imaging system.

  3. A CMOS variable gain amplifier for PHENIX electromagnetic calorimeter and RICH energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Wintenberg, A.L.; Simpson, M.L.; Young, G.R. [Oak Ridge National Lab., TN (United States); Palmer, R.L.; Moscone, C.G.; Jackson, R.G. [Tennessee Univ., Knoxville, TN (United States)

    1996-12-31

    A variable gain amplifier (VGA) has been developed equalizing the gains of integrating amplifier channels used with multiple photomultiplier tubes operating from common high-voltage supplies. The PHENIX lead-scintillator electromagnetic calorimeter will operate in that manner, and gain equalization is needed to preserve the dynamic range of the analog memory and ADC following the integrating amplifier. The VGA is also needed for matching energy channel gains prior to forming analog sums for trigger purposes. The gain of the VGA is variable over a 3:1 range using a 5-bit digital control, and the risetime is held between 15 and 23 ns using switched compensation in the VGA. An additional feature is gated baseline restoration. Details of the design and results from several prototype devices fabricated in 1.2-{mu}m Orbit CMOS are presented.

  4. A Low-Power CMOS Trans-Impedance Amplifier for 2.5 Gb/S Optical Communication Systems

    Directory of Open Access Journals (Sweden)

    Mojgan Mohseni

    2013-01-01

    Full Text Available This Paper presents a new Trans-impedance amplifier for optical receiver circuits. The amplifier is based on parallel (R-C feedback topology which is optimized for power consumption and uses shunt-peaking technique to enhance the frequency bandwidth of the amplifier. However, the circuit is designed and simulated using 0.18µm CMOS technology parameters. As simulation results show, the amplifier has a gain of 67.5dBΩ, bandwidth of 3GHz while consumes only 12.16 mW power which shows a very good performance for using in a 2.5Gb/S (SONET OC-48 optical communication system. Finally, as the simulated Eye-Diagram shows, the circuit has a very good performance for a 2.5Gb/S system for a 10µA input current.

  5. A CMOS-MEMS clamped–clamped beam displacement amplifier for resonant switch applications

    Science.gov (United States)

    Liu, Jia-Ren; Lu, Shih-Chuan; Tsai, Chun-Pu; Li, Wei-Chang

    2018-06-01

    This paper presents a micromechanical clamped–clamped beam (CC-beam) displacement amplifier based on a CMOS-MEMS fabrication process platform. In particular, a 2.0 MHz resonant displacement amplifier composed of two identical CC-beams coupled by a mechanical beam at locations where the two beams have mismatched velocities exhibits a larger displacement, up to 9.96×, on one beam than that of the other. The displacement amplification prevents unwanted input impacting—the structure switches only to the output but not the input—required by resonant switch-based mechanical circuits (Kim et al 2009 22nd IEEE Int. Conf. on Micro Electro Mechanical Systems; Lin et al 2009 15th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’09) Li et al 2013 17th Int. Conf. on Solid-State Sensors, Actuators, & Microsystems (TRANSDUCERS’13)). Compared to a single CC-beam displacement amplifier, theory predicts that the displacement amplifying CC-beam array yields a larger overall output displacement for displacement gain beyond 1.13 thanks to the preserved input driving force. A complete analytical model predicts the resultant stiffness and displacement gain of the coupled CC-beam displacement amplifier that match well with finite element analysis (FEA) prediction and measured results.

  6. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    International Nuclear Information System (INIS)

    Liu Jialin; Zhang Xu; Hu Xiaohui; Li Peng; Liu Ming; Chen Hongda; Guo Yatao; Li Bin

    2015-01-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a −3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μV rms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm 2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. (paper)

  7. A 20 Mfps high frame-depth CMOS burst-mode imager with low power in-pixel NMOS-only passive amplifier

    Science.gov (United States)

    Wu, L.; San Segundo Bello, D.; Coppejans, P.; Craninckx, J.; Wambacq, P.; Borremans, J.

    2017-02-01

    This paper presents a 20 Mfps 32 × 84 pixels CMOS burst-mode imager featuring high frame depth with a passive in-pixel amplifier. Compared to the CCD alternatives, CMOS burst-mode imagers are attractive for their low power consumption and integration of circuitry such as ADCs. Due to storage capacitor size and its noise limitations, CMOS burst-mode imagers usually suffer from a lower frame depth than CCD implementations. In order to capture fast transitions over a longer time span, an in-pixel CDS technique has been adopted to reduce the required memory cells for each frame by half. Moreover, integrated with in-pixel CDS, an in-pixel NMOS-only passive amplifier alleviates the kTC noise requirements of the memory bank allowing the usage of smaller capacitors. Specifically, a dense 108-cell MOS memory bank (10fF/cell) has been implemented inside a 30μm pitch pixel, with an area of 25 × 30μm2 occupied by the memory bank. There is an improvement of about 4x in terms of frame depth per pixel area by applying in-pixel CDS and amplification. With the amplifier's gain of 3.3, an FD input-referred RMS noise of 1mV is achieved at 20 Mfps operation. While the amplification is done without burning DC current, including the pixel source follower biasing, the full pixel consumes 10μA at 3.3V supply voltage at full speed. The chip has been fabricated in imec's 130nm CMOS CIS technology.

  8. The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

    2002-01-01

    The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

  9. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    International Nuclear Information System (INIS)

    Herve, C.; Dzahini, D.; Le Caer, T.; Richer, J.-P.; Torki, K.

    2005-01-01

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 KΩ), bandwidth (25 MHz) and noise (1570 e - +95 e - /pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements

  10. BiCMOS amplifier-discriminator integrated circuit for gas-filled detector readout

    Energy Technology Data Exchange (ETDEWEB)

    Herve, C. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France)]. E-mail: herve@esrf.fr; Dzahini, D. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Le Caer, T. [European Synchrotron Radiation Facility, BP 220, 38043 Grenoble Cedex (France); Richer, J.-P. [Laboratoire de Physique Subatomique et de Cosmologie, Grenoble (France); Torki, K. [Laboratoire TIMA, Grenoble (France)

    2005-03-21

    The paper presents a 16-channel amplifier-discriminator designed in BiCMOS technology. It will be used for the binary parallel readout of gas-filled detectors being designed at the European Synchrotron Radiation Facility. The circuit (named AMS211) has been manufactured. The measured transimpedance gain (400 K{omega}), bandwidth (25 MHz) and noise (1570 e{sup -}+95 e{sup -}/pF ENC) well match the simulated results. The discriminator thresholds are individually controlled by built-in Digital to Analogue Converter. The experience gained with a first prototype of readout electronics indicates that the AMS211 should meet our requirements.

  11. A CMOS frontend chip for implantable neural recording with wide voltage supply range

    Science.gov (United States)

    Jialin, Liu; Xu, Zhang; Xiaohui, Hu; Yatao, Guo; Peng, Li; Ming, Liu; Bin, Li; Hongda, Chen

    2015-10-01

    A design for a CMOS frontend integrated circuit (chip) for neural signal acquisition working at wide voltage supply range is presented in this paper. The chip consists of a preamplifier, a serial instrumental amplifier (IA) and a cyclic analog-to-digital converter (CADC). The capacitive-coupled and capacitive-feedback topology combined with MOS-bipolar pseudo-resistor element is adopted in the preamplifier to create a -3 dB upper cut-off frequency less than 1 Hz without using a ponderous discrete device. A dual-amplifier instrumental amplifier is used to provide a low output impedance interface for ADC as well as to boost the gain. The preamplifier and the serial instrumental amplifier together provide a midband gain of 45.8 dB and have an input-referred noise of 6.7 μVrms integrated from 1 Hz to 5 kHz. The ADC digitizes the amplified signal at 12-bits precision with a highest sampling rate of 130 kS/s. The measured effective number of bits (ENOB) of the ADC is 8.7 bits. The entire circuit draws 165 to 216 μA current from the supply voltage varied from 1.34 to 3.3 V. The prototype chip is fabricated in the 0.18-μm CMOS process and occupies an area of 1.23 mm2 (including pads). In-vitro recording was successfully carried out by the proposed frontend chip. Project supported by the National Natural Science Foundation of China (Nos. 61474107, 61372060, 61335010, 61275200, 61178051) and the Key Program of the Chinese Academy of Sciences (No. KJZD-EW-L11-01).

  12. Poly-Si gate engineering for advanced CMOS transistors by germanium implantation

    International Nuclear Information System (INIS)

    Bourdon, H.; Juhel, M.; Oudet, B.; Breil, N.; Lenoble, D.

    2005-01-01

    Standard gate materials are compared to Ge implanted poly-Si and deposited poly-SiGe. It is demonstrated in this paper that the electrical resistance of the gate is significantly reduced via the use of poly-SiGe (from 30% to 40% decrease in resistance). Similarly, we show via specific optimization that localized Ge implantation is also suitable to reduce gate resistance. Physical characterizations are performed to determine the 'root' causes at the origin of these improvements. In line with future publications showing strong benefits on CMOS device performance, grain size effects seem to be the main mechanisms explaining the measured improvement

  13. Class 1 bluetooth power amplifier with 24dBm output power and 48% PAE at 2.4GHz in 0.25um CMOS

    NARCIS (Netherlands)

    Vathulay, V.; Sowlati, T.; Leenaerts, D.M.W.

    2001-01-01

    In this paper, we report an RF power amplifier design in digital CMOS technology for the Class 1 power level specification (20 dBm) in the Bluetooth Communications standard. We have also investigated hot carrier effects under large signal RF operation of the power amplifier. The two stage circuit,

  14. CMOS Current-mode Operational Amplifier

    OpenAIRE

    Kaulberg, Thomas

    1992-01-01

    A fully differential-input differential-output current-mode operational amplifier (COA) is described. The amplifier utilizes three second generation current-conveyors (CCII) as the basic building blocks. It can be configured to provide either a constant gain-bandwidth product in a fully balanced current-mode feedback amplifier or a constant bandwidth in a transimpedance feedback amplifier. The amplifier is found to have a gain bandwidth product of 8 MHz, an offset current of 0.8 ¿A (signal-r...

  15. Advanced design and characterization methodologies for memory-aware CMOS power-amplifier implementation

    Directory of Open Access Journals (Sweden)

    M. Schleyer

    2017-09-01

    Full Text Available This paper reports on an effective root-cause analysis method of memory effects in power amplifiers, as well as introduces compensation techniques on a circuit design level. Despite conventional memory-effect approaches, the discussed method uses a two-tone scan over a wide operation and modulation range. This enables an in-depth study of physical causes and helps to implement compensation techniques at design stage. On the one hand, this circuit investigation is optimized using an automated SystemC model parametrized with real device and measurement values. Hence, computation time is widely reduced which shortens design cycles. On the other hand, the implementation of the derived circuit compensation means will reduce the complexity of digital pre-distortion due to a reduced memory-effect induced AM/AM and AM/PM hysteresis. The approach is demonstrated on a 65 nm CMOS power amplifier with an OIP1 of 27 dBm and a PAE of over 30 % using WCDMA and LTE signals. In fact, mismatch could be reduced by more than 8 %.

  16. A high-speed low-noise transimpedance amplifier in a 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Anelli, Giovanni; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-01-01

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 kΩ, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO 2 ) without any degradation in the performance

  17. A high-speed low-noise transimpedance amplifier in a 0.25 {mu}m CMOS technology

    Energy Technology Data Exchange (ETDEWEB)

    Anelli, Giovanni E-mail: giovanni.anelli@cern.ch; Borer, Kurt; Casagrande, Luca; Despeisse, Matthieu; Jarron, Pierre; Pelloux, Nicolas; Saramad, Shahyar

    2003-10-11

    We present the simulated and measured performance of a transimpedance amplifier designed in a quarter micron CMOS process. Containing only NMOS and PMOS devices, this amplifier can be integrated in any submicron CMOS process. The main feature of this design is the use of a transistor in the feedback path instead of a resistor. The circuit has been optimized for reading signals coming from silicon strip detectors with few pF input capacitance. For an input charge of 4 fC, an input capacitance of 4 pF and a transresistance of 135 k{omega}, we have measured an output pulse fall time of 3 ns and an Equivalent Noise Charge (ENC) of around 350 electrons rms. In view of the operation of the chip at cryogenic temperatures, measurements at 130 K have also been carried out, showing an overall improvement in the performance of the chip. Fall times down to 1.5 ns have been measured. An integrated circuit containing 32 channels has been designed and wire bonded to a silicon strip detector and successfully used for the construction of a high-intensity proton beam hodoscope for the NA60 experiment. The chip has been laid out using special techniques to improve its radiation tolerance, and it has been irradiated up to 10 Mrd (SiO{sub 2}) without any degradation in the performance.

  18. Swarm intelligence-based approach for optimal design of CMOS differential amplifier and comparator circuit using a hybrid salp swarm algorithm

    Science.gov (United States)

    Asaithambi, Sasikumar; Rajappa, Muthaiah

    2018-05-01

    In this paper, an automatic design method based on a swarm intelligence approach for CMOS analog integrated circuit (IC) design is presented. The hybrid meta-heuristics optimization technique, namely, the salp swarm algorithm (SSA), is applied to the optimal sizing of a CMOS differential amplifier and the comparator circuit. SSA is a nature-inspired optimization algorithm which mimics the navigating and hunting behavior of salp. The hybrid SSA is applied to optimize the circuit design parameters and to minimize the MOS transistor sizes. The proposed swarm intelligence approach was successfully implemented for an automatic design and optimization of CMOS analog ICs using Generic Process Design Kit (GPDK) 180 nm technology. The circuit design parameters and design specifications are validated through a simulation program for integrated circuit emphasis simulator. To investigate the efficiency of the proposed approach, comparisons have been carried out with other simulation-based circuit design methods. The performances of hybrid SSA based CMOS analog IC designs are better than the previously reported studies.

  19. Optoelectronic circuits in nanometer CMOS technology

    CERN Document Server

    Atef, Mohamed

    2016-01-01

    This book describes the newest implementations of integrated photodiodes fabricated in nanometer standard CMOS technologies. It also includes the required fundamentals, the state-of-the-art, and the design of high-performance laser drivers, transimpedance amplifiers, equalizers, and limiting amplifiers fabricated in nanometer CMOS technologies. This book shows the newest results for the performance of integrated optical receivers, laser drivers, modulator drivers and optical sensors in nanometer standard CMOS technologies. Nanometer CMOS technologies rapidly advanced, enabling the implementation of integrated optical receivers for high data rates of several Giga-bits per second and of high-pixel count optical imagers and sensors. In particular, low cost silicon CMOS optoelectronic integrated circuits became very attractive because they can be extensively applied to short-distance optical communications, such as local area network, chip-to-chip and board-to-board interconnects as well as to imaging and medical...

  20. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    Energy Technology Data Exchange (ETDEWEB)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao, E-mail: tanxi@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-12-15

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 {mu}m CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm{sup 2}. System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  1. A 900 MHz, 21 dBm CMOS linear power amplifier with 35% PAE for RFID readers

    International Nuclear Information System (INIS)

    Han Kefeng; Cao Shengguo; Tan Xi; Yan Na; Wang Junyu; Tang Zhangwen; Min Hao

    2010-01-01

    A two-stage differential linear power amplifier (PA) fabricated by 0.18 μm CMOS technology is presented. An output matching and harmonic termination network is exploited to enhance the output power, efficiency and harmonic performance. Measurements show that the designed PA reaches a saturated power of 21.1 dBm and the peak power added efficiency (PAE) is 35.4%, the power gain is 23.3 dB from a power supply of 1.8 V and the harmonics are well controlled. The total area with ESD protected PAD is 1.2 x 0.55 mm 2 . System measurements also show that this power amplifier meets the design specifications and can be applied for RFID reader. (semiconductor integrated circuits)

  2. Wireless power transmission for biomedical implants: The role of near-zero threshold CMOS rectifiers.

    Science.gov (United States)

    Mohammadi, Ali; Redoute, Jean-Michel; Yuce, Mehmet R

    2015-01-01

    Biomedical implants require an electronic power conditioning circuitry to provide a stable electrical power supply. The efficiency of wireless power transmission is strongly dependent on the power conditioning circuitry specifically the rectifier. A cross-connected CMOS bridge rectifier is implemented to demonstrate the impact of thresholds of rectifiers on wireless power transfer. The performance of the proposed rectifier is experimentally compared with a conventional Schottky diode full wave rectifier over 9 cm distance of air and tissue medium between the transmitter and receiver. The output voltage generated by the CMOS rectifier across a 1 KΩ resistive load is around twice as much as the Schottky rectifier.

  3. Flexible CMOS low-noise amplifiers for beyond-3G wireless hand-held devices

    Science.gov (United States)

    Becerra-Alvarez, Edwin C.; Sandoval-Ibarra, Federico; de la Rosa, José M.

    2009-05-01

    This paper explores the use of reconfigurable Low-Noise Amplifiers (LNAs) for the implementation of CMOS Radio Frequency (RF) front-ends in the next generation of multi-standard wireless transceivers. Main circuit strategies reported so far for multi-standard LNAs are reviewed and a novel flexible LNA intended for Beyond-3G RF hand-held terminals is presented. The proposed LNA circuit consists of a two-stage topology that combines inductive-source degeneration with PMOS-varactor based tuning network and a programmable load to adapt its performance to different standard specifications without penalizing the circuit noise and with a reduced number of inductors as compared to previous reported reconfigurable LNAs. The circuit has been designed in a 90-nm CMOS technology to cope with the requirements of the GSM, WCDMA, Bluetooth and WLAN (IEEE 802.11b-g) standards. Simulation results, including technology and packaging parasitics, demonstrate correct operation of the circuit for all the standards under study, featuring NF13.3dB and IIP3>10.9dBm, over a 1.85GHz-2.4GHz band, with an adaptive power consumption between 17mW and 22mW from a 1-V supply voltage. Preliminary experimental measurements are included, showing a correct reconfiguration operation within the operation band.

  4. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    Science.gov (United States)

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  5. CMOS Integrated Carbon Nanotube Sensor

    International Nuclear Information System (INIS)

    Perez, M. S.; Lerner, B.; Boselli, A.; Lamagna, A.; Obregon, P. D. Pareja; Julian, P. M.; Mandolesi, P. S.; Buffa, F. A.

    2009-01-01

    Recently carbon nanotubes (CNTs) have been gaining their importance as sensors for gases, temperature and chemicals. Advances in fabrication processes simplify the formation of CNT sensor on silicon substrate. We have integrated single wall carbon nanotubes (SWCNTs) with complementary metal oxide semiconductor process (CMOS) to produce a chip sensor system. The sensor prototype was designed and fabricated using a 0.30 um CMOS process. The main advantage is that the device has a voltage amplifier so the electrical measure can be taken and amplified inside the sensor. When the conductance of the SWCNTs varies in response to media changes, this is observed as a variation in the output tension accordingly.

  6. An implantable integrated low-power amplifier-microelectrode array for Brain-Machine Interfaces.

    Science.gov (United States)

    Patrick, Erin; Sankar, Viswanath; Rowe, William; Sanchez, Justin C; Nishida, Toshikazu

    2010-01-01

    One of the important challenges in designing Brain-Machine Interfaces (BMI) is to build implantable systems that have the ability to reliably process the activity of large ensembles of cortical neurons. In this paper, we report the design, fabrication, and testing of a polyimide-based microelectrode array integrated with a low-power amplifier as part of the Florida Wireless Integrated Recording Electrode (FWIRE) project at the University of Florida developing a fully implantable neural recording system for BMI applications. The electrode array was fabricated using planar micromachining MEMS processes and hybrid packaged with the amplifier die using a flip-chip bonding technique. The system was tested both on bench and in-vivo. Acute and chronic neural recordings were obtained from a rodent for a period of 42 days. The electrode-amplifier performance was analyzed over the chronic recording period with the observation of a noise floor of 4.5 microVrms, and an average signal-to-noise ratio of 3.8.

  7. Wideband CMOS receivers

    CERN Document Server

    Oliveira, Luis

    2015-01-01

    This book demonstrates how to design a wideband receiver operating in current mode, in which the noise and non-linearity are reduced, implemented in a low cost single chip, using standard CMOS technology.  The authors present a solution to remove the transimpedance amplifier (TIA) block and connect directly the mixer’s output to a passive second-order continuous-time Σ∆ analog to digital converter (ADC), which operates in current-mode. These techniques enable the reduction of area, power consumption, and cost in modern CMOS receivers.

  8. A Baseband Ultra-Low Noise SiGe:C BiCMOS 0.25 µm Amplifier And Its Application For An On-Chip Phase-Noise Measurement Circuit

    OpenAIRE

    Godet , Sylvain; Tournier , Éric; Llopis , Olivier; Cathelin , Andreia; Juyon , Julien

    2009-01-01

    4 pages; International audience; The design and realization of an ultra-low noise operational amplifier is presented. Its applications are integrated low-frequency noise measurements in electronic devices and on-chip phase-noise measurement circuit. This paper discusses the SiGe:C BiCMOS 0.25 µm design improvements used for low noise applications. The proposed three-stage operational amplifier uses parallel bipolar transistor connection as input differential pair for low noise behavior. This ...

  9. Transmission of wireless neural signals through a 0.18 µm CMOS low-power amplifier.

    Science.gov (United States)

    Gazziro, M; Braga, C F R; Moreira, D A; Carvalho, A C P L F; Rodrigues, J F; Navarro, J S; Ardila, J C M; Mioni, D P; Pessatti, M; Fabbro, P; Freewin, C; Saddow, S E

    2015-01-01

    In the field of Brain Machine Interfaces (BMI) researchers still are not able to produce clinically viable solutions that meet the requirements of long-term operation without the use of wires or batteries. Another problem is neural compatibility with the electrode probes. One of the possible ways of approaching these problems is the use of semiconductor biocompatible materials (silicon carbide) combined with an integrated circuit designed to operate with low power consumption. This paper describes a low-power neural signal amplifier chip, named Cortex, fabricated using 0.18 μm CMOS process technology with all electronics integrated in an area of 0.40 mm(2). The chip has 4 channels, total power consumption of only 144 μW, and is impedance matched to silicon carbide biocompatible electrodes.

  10. A high-efficiency low-voltage CMOS rectifier for harvesting energy in implantable devices.

    Science.gov (United States)

    Hashemi, S Saeid; Sawan, Mohamad; Savaria, Yvon

    2012-08-01

    We present, in this paper, a new full-wave CMOS rectifier dedicated for wirelessly-powered low-voltage biomedical implants. It uses bootstrapped capacitors to reduce the effective threshold voltage of selected MOS switches. It achieves a significant increase in its overall power efficiency and low voltage-drop. Therefore, the rectifier is good for applications with low-voltage power supplies and large load current. The rectifier topology does not require complex circuit design. The highest voltages available in the circuit are used to drive the gates of selected transistors in order to reduce leakage current and to lower their channel on-resistance, while having high transconductance. The proposed rectifier was fabricated using the standard TSMC 0.18 μm CMOS process. When connected to a sinusoidal source of 3.3 V peak amplitude, it allows improving the overall power efficiency by 11% compared to the best recently published results given by a gate cross-coupled-based structure.

  11. Self-amplified CMOS image sensor using a current-mode readout circuit

    Science.gov (United States)

    Santos, Patrick M.; de Lima Monteiro, Davies W.; Pittet, Patrick

    2014-05-01

    The feature size of the CMOS processes decreased during the past few years and problems such as reduced dynamic range have become more significant in voltage-mode pixels, even though the integration of more functionality inside the pixel has become easier. This work makes a contribution on both sides: the possibility of a high signal excursion range using current-mode circuits together with functionality addition by making signal amplification inside the pixel. The classic 3T pixel architecture was rebuild with small modifications to integrate a transconductance amplifier providing a current as an output. The matrix with these new pixels will operate as a whole large transistor outsourcing an amplified current that will be used for signal processing. This current is controlled by the intensity of the light received by the matrix, modulated pixel by pixel. The output current can be controlled by the biasing circuits to achieve a very large range of output signal levels. It can also be controlled with the matrix size and this permits a very high degree of freedom on the signal level, observing the current densities inside the integrated circuit. In addition, the matrix can operate at very small integration times. Its applications would be those in which fast imaging processing, high signal amplification are required and low resolution is not a major problem, such as UV image sensors. Simulation results will be presented to support: operation, control, design, signal excursion levels and linearity for a matrix of pixels that was conceived using this new concept of sensor.

  12. A 205GHz Amplifier in 90nm CMOS Technology

    Science.gov (United States)

    2017-03-01

    10.5dB power gain, Psat of -1.6dBm, and P1dB ≈ -5.8dBm in a standard 90nm CMOS process. Moreover, the design employs internal (layout-based) /external...other advantages, such as low- cost , reliability, and mixed-mode analog/digital chips, intensifying its usage in the mm-wave band [5]. CMOS has several... disadvantages at the higher frequency range with the worst case scenario happening when the device operates near its fmax. This is chiefly due to

  13. A 0.8V, 7μA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18μm CMOS

    OpenAIRE

    Citakovic, J; Nielsen, I. Riis; Nielsen, Jannik Hammel; Asbeck, P; Andreani, Pietro

    2005-01-01

    A two-stage amplifier, operational at 0.8V and drawing 7μA, has been integrated in a standard digital 0.18μm CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with gm control. The efficient rail-to-rail output stage is biased in class AB. The measured DC gain of the amplifier is 75dB, and the unity-gain frequency is 870kHz with a 12pF, 100kΩload. Both input and output stage transistors are biased in weak inversion.

  14. Proximity gettering technology for advanced CMOS image sensors using carbon cluster ion-implantation technique. A review

    Energy Technology Data Exchange (ETDEWEB)

    Kurita, Kazunari; Kadono, Takeshi; Okuyama, Ryousuke; Shigemastu, Satoshi; Hirose, Ryo; Onaka-Masada, Ayumi; Koga, Yoshihiro; Okuda, Hidehiko [SUMCO Corporation, Saga (Japan)

    2017-07-15

    A new technique is described for manufacturing advanced silicon wafers with the highest capability yet reported for gettering transition metallic, oxygen, and hydrogen impurities in CMOS image sensor fabrication processes. Carbon and hydrogen elements are localized in the projection range of the silicon wafer by implantation of ion clusters from a hydrocarbon molecular gas source. Furthermore, these wafers can getter oxygen impurities out-diffused to device active regions from a Czochralski grown silicon wafer substrate to the carbon cluster ion projection range during heat treatment. Therefore, they can reduce the formation of transition metals and oxygen-related defects in the device active regions and improve electrical performance characteristics, such as the dark current, white spot defects, pn-junction leakage current, and image lag characteristics. The new technique enables the formation of high-gettering-capability sinks for transition metals, oxygen, and hydrogen impurities under device active regions of CMOS image sensors. The wafers formed by this technique have the potential to significantly improve electrical devices performance characteristics in advanced CMOS image sensors. (copyright 2017 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  15. A CMOS/SOI Single-input PWM Discriminator for Low-voltage Body-implanted Applications

    Directory of Open Access Journals (Sweden)

    Jader A. De Lima

    2002-01-01

    Full Text Available A CMOS/SOI circuit to decode Pulse-Width Modulation (PWM signals is presented as part of a body-implanted neurostimulator for visual prosthesis. Since encoded data is the sole input to the circuit, the decoding technique is based on a novel double-integration concept and does not require low-pass filtering. Non-overlapping control phases are internally derived from the incoming pulses and a fast-settling comparator ensures good discrimination accuracy in the megahertz range. The circuit was integrated on a 2 μm single-metal thin-film CMOS/SOI fabrication process and has an effective area of 2 mm2. Measured resolution of encoding parameter α is better than 10% at 6 MHz and VDD = 3.3 V. Idle-mode consumption is 340 μW. Pulses of frequencies up to15 MHz and α =10% can be discriminated for 2.3 V ≤ VDD ≤ 3.3 V. Such an excellent immunity to VDD deviations meets a design specification with respect to inherent coupling losses on transmitting data and power by means of a transcutaneous link.

  16. Realization of OFCC based Transimpedance Mode Instrumentation Amplifier

    Directory of Open Access Journals (Sweden)

    Neeta Pandey

    2016-01-01

    Full Text Available The paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three Operational Floating Current Conveyors (OFCCs and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematicThe paper presents an instrumentation amplifier suitable for amplifying the current source transducer signals. It provides a voltage output. It has a high gain, common mode rejection ratio and gain independent bandwidth. It uses three operational floating current conveyors (OFCCs and four resistors. The effect of nonidealities of OFCC on performance of proposed transimpedance instrumentation amplifier (TIA is also analyzed. The proposal has been verified through SPICE simulations using CMOS based schematic.

  17. A 0.8V, 7μA, rail-to-rail input/output, constant Gm operational amplifier in standard digital 0.18μm CMOS

    DEFF Research Database (Denmark)

    Citakovic, J; Nielsen, I. Riis; Nielsen, Jannik Hammel

    2005-01-01

    A two-stage amplifier, operational at 0.8V and drawing 7μA, has been integrated in a standard digital 0.18μm CMOS process. Rail-to-rail operations at the input are enabled by complementary transistor pairs with gm control. The efficient rail-to-rail output stage is biased in class AB. The measured...

  18. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 {mu}m CMOS technology for the integrated camera of the Cherenkov Telescope Array

    Energy Technology Data Exchange (ETDEWEB)

    Gascon, D; Sanuy, A; Ribo, M [Dept. AM i Dept.ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E; Glicenstein, J-F [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Sieiro, X [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, E08028, Barcelona (Spain); Feinstein, F; Vorobiov, S [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P, E-mail: gascon@ecm.ub.es [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

    2010-12-15

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35{mu}m CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  19. Wideband pulse amplifier with 8 GHz GBW product in a 0.35 μm CMOS technology for the integrated camera of the Cherenkov Telescope Array

    International Nuclear Information System (INIS)

    Gascon, D; Sanuy, A; Ribo, M; Delagnes, E; Glicenstein, J-F; Sieiro, X; Feinstein, F; Vorobiov, S; Nayman, P; Toussenel, F; Tavernet, J-P; Vincent, P

    2010-01-01

    A fully differential wideband amplifier for the camera of the Cherenkov Telescope Array (CTA) is presented. This amplifier would be part of a new ASIC, developed by the NECTAr collaboration, performing the digitization at 1 GS/s with a dynamic range of 16 bits. Input amplifiers must have a voltage gain up to 20 V/V and a bandwidth of 400 MHz. Being impossible to design a fully differential operational amplifier with an 8 GHz GBW product in a 0.35μm CMOS technology, an alternative implementation based on HF linearised transconductors is explored. Test results show that the required GBW product is achieved, with a linearity error smaller than 1% for a differential output voltage range up to 1 Vpp, and smaller than 3% for 2 Vpp.

  20. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  1. 1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

    International Nuclear Information System (INIS)

    Huang Beiju; Zhang Xu; Chen Hongda

    2009-01-01

    A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 μm RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB·Ω for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz·Ω. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 Ω, and the average input noise current spectral density is 9.7 pA/√Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

  2. 1-Gb/s zero-pole cancellation CMOS transimpedance amplifier for Gigabit Ethernet applications

    Energy Technology Data Exchange (ETDEWEB)

    Huang Beiju; Zhang Xu; Chen Hongda, E-mail: bjhuang@semi.ac.c [State Key Laboratory of Integrated Optoelectronics, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-10-15

    A zero-pole cancellation transimpedance amplifier (TIA) has been realized in 0.35 {mu}m RF CMOS technology for Gigabit Ethernet applications. The TIA exploits a zero-pole cancellation configuration to isolate the input parasitic capacitance including photodiode capacitance from bandwidth deterioration. Simulation results show that the proposed TIA has a bandwidth of 1.9 GHz and a transimpedance gain of 65 dB{center_dot}{Omega} for 1.5 pF photodiode capacitance, with a gain-bandwidth product of 3.4 THz{center_dot}{Omega}. Even with 2 pF photodiode capacitance, the bandwidth exhibits a decline of only 300 MHz, confirming the mechanism of the zero-pole cancellation configuration. The input resistance is 50 {Omega}, and the average input noise current spectral density is 9.7 pA/{radical}Hz. Testing results shows that the eye diagram at 1 Gb/s is wide open. The chip dissipates 17 mW under a single 3.3 V supply.

  3. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  4. Low-Gain, Low-Noise Integrated Neuronal Amplifier for Implantable Artifact-Reduction Recording System

    OpenAIRE

    Zbrzeski, Adeline; Lewis, Noëlle; Rummens, Francois; Jung, Ranu; N'Kaoua, Gilles; Benazzouz, Abdelhamid; Renaud, Sylvie

    2013-01-01

    Brain neuroprostheses for neuromodulation are being designed to monitor the neural activity of the brain in the vicinity of the region being stimulated using a single macro-electrode. Using a single macro-electrode, recent neuromodulation studies show that recording systems with a low gain neuronal amplifier and successive amplifier stages can reduce or reject stimulation artifacts. These systems were made with off-the-shelf components that are not amendable for future implant design. A low-g...

  5. Studies of the LBL CMOS integrated amplifier/discriminator for randomly timed inputs from fixed target experiments

    International Nuclear Information System (INIS)

    Russ, J.S.; Yarema, R.J.; Zimmerman, T.

    1988-12-01

    A group at Lawrence Berkeley Laboratory has reported an elegant CMOS VLSI circuit for amplifying, discriminating, and encoding the signals from highly-segmented charge output devices, e.g., silicon strip detectors or pad readout structures in gaseous detectors. The design exploits switched capacitor circuits and the well-known time structure of data acquisition in colliding beam accelerators to cancel leakage effects and switching noise. For random inputs, these methods are not directly applicable. However, the high speed of the reset switches makes possible a mode of operation for fixed target experiments that uses fast resets to erase unwanted data from random triggers. Data acquisition in this mode has been performed. Details of operation and measurements of noise and rate capability will be presented. 8 refs., 6 figs

  6. Prospects for charge sensitive amplifiers in scaled CMOS

    Science.gov (United States)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-03-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006.

  7. Prospects for charge sensitive amplifiers in scaled CMOS

    International Nuclear Information System (INIS)

    O'Connor, Paul; De Geronimo, Gianluigi

    2002-01-01

    Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006

  8. A wideband CMOS inductorless low noise amplifier employing noise cancellation for digital TV tuner applications

    International Nuclear Information System (INIS)

    Zhang Jihong; Bai Xuefei; Huang Lu

    2013-01-01

    A wideband inductorless low noise amplifier for digital TV tuner applications is presented. The proposed LNA scheme uses a composite NMOS/PMOS cross-coupled transistor pair to provide partial cancellation of noise generated by the input transistors. The chip is implemented in SMIC 0.18 μm CMOS technology. Measurement shows that the proposed LNA achieves 12.2–15.2 dB voltage gain from 300 to 900 MHz, the noise figure is below 3.1 dB and has a minimum value of 2.3 dB, and the best input-referred 1-dB compression point (IP1dB) is − 17 dBm at 900 MHz. The core consumes 7 mA current with a supply voltage of 1.8 V and occupies an area of 0.5 × 0.35 mm 2 . (semiconductor integrated circuits)

  9. Advanced 65 nm CMOS devices fabricated using ultra-low energy plasma doping

    International Nuclear Information System (INIS)

    Walther, S.; Lenoble, D.; Lallement, F.; Grouillet, A.; Erokhin, Y.; Singh, V.; Testoni, A.

    2005-01-01

    For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5x higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p + /n ultra-shallow junctions formed with BF 3 plasma doping have superior X j /R s characteristics to beamline implants and yield up to 30% lower R s for 20 nm X j while using standard spike anneal with ramp-up rate of 75 deg. C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior V t roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving V t roll-off and I on -I off performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity

  10. A fully-integrated 12.5-Gb/s 850-nm CMOS optical receiver based on a spatially-modulated avalanche photodetector.

    Science.gov (United States)

    Lee, Myung-Jae; Youn, Jin-Sung; Park, Kang-Yeob; Choi, Woo-Young

    2014-02-10

    We present a fully integrated 12.5-Gb/s optical receiver fabricated with standard 0.13-µm complementary metal-oxide-semiconductor (CMOS) technology for 850-nm optical interconnect applications. Our integrated optical receiver includes a newly proposed CMOS-compatible spatially-modulated avalanche photodetector, which provides larger photodetection bandwidth than previously reported CMOS-compatible photodetectors. The receiver also has high-speed CMOS circuits including transimpedance amplifier, DC-balanced buffer, equalizer, and limiting amplifier. With the fabricated optical receiver, detection of 12.5-Gb/s optical data is successfully achieved at 5.8 pJ/bit. Our receiver achieves the highest data rate ever reported for 850-nm integrated CMOS optical receivers.

  11. A Demonstration of TIA Using FD-SOI CMOS OPAMP for Far-Infrared Astronomy

    Science.gov (United States)

    Nagase, Koichi; Wada, Takehiko; Ikeda, Hirokazu; Arai, Yasuo; Ohno, Morifumi; Hanaoka, Misaki; Kanada, Hidehiro; Oyabu, Shinki; Hattori, Yasuki; Ukai, Sota; Suzuki, Toyoaki; Watanabe, Kentaroh; Baba, Shunsuke; Kochi, Chihiro; Yamamoto, Keita

    2016-07-01

    We are developing a fully depleted silicon-on-insulator (FD-SOI) CMOS readout integrated circuit (ROIC) operated at temperatures below ˜ 4 K. Its application is planned for the readout circuit of high-impedance far-infrared detectors for astronomical observations. We designed a trans-impedance amplifier (TIA) using a CMOS operational amplifier (OPAMP) with FD-SOI technique. The TIA is optimized to readout signals from a germanium blocked impurity band (Ge BIB) detector which is highly sensitive to wavelengths of up to ˜ 200 \\upmu m. For the first time, we demonstrated the FD-SOI CMOS OPAMP combined with the Ge BIB detector at 4.5 K. The result promises to solve issues faced by conventional cryogenic ROICs.

  12. 45-GHz and 60-GHz 90 nm CMOS power amplifiers with a fully symmetrical 8-way transformer power combiner

    Institute of Scientific and Technical Information of China (English)

    Zhengdong JIANG; Kaizhe GUO; Peng HUANG; Yiming FAN; Chenxi ZHAO; Yongling BAN; Jun LIU; Kai KANG

    2017-01-01

    In this paper,45 GHz and 60 GHz power amplifiers (PAs) with high output power have been successfully designed by using 90 nm CMOS process.The 45 GHz (60 GHz) PA consists of two (four) differential stages.The sizes of transistors have been designed in an appropriate way so as to trade-off gain,efficiency and stability.Due to limited supply voltage and low breakdown voltage of CMOS MOSFET compared with the traditional Ⅲ-Ⅴ technologies,the technique of power combining has been applied to achieve a high output power.In particular,a novel 8-way distributed active transformer power combiner has been proposed for realizing such mm-wave PA.The proposed transformer combiner with a fully symmetrical layout can improve its input impedance balance at mm-wave frequency regime significantly.Taking its advantages of this novel transformer based power combiner,our realized 45 GHz (60 GHz) mm-wave PA has achieved the gain of 20.3 dB (16.8 dB),the maximum PAE of 14.5% (13.4%) and the saturated output power of 21 dBm (21 dBm) with the 1.2 V supply voltage.

  13. Arrays of suspended silicon nanowires defined by ion beam implantation: mechanical coupling and combination with CMOS technology

    Science.gov (United States)

    Llobet, J.; Rius, G.; Chuquitarqui, A.; Borrisé, X.; Koops, R.; van Veghel, M.; Perez-Murano, F.

    2018-04-01

    We present the fabrication, operation, and CMOS integration of arrays of suspended silicon nanowires (SiNWs). The functional structures are obtained by a top-down fabrication approach consisting in a resistless process based on focused ion beam irradiation, causing local gallium implantation and silicon amorphization, plus selective silicon etching by tetramethylammonium hydroxide, and a thermal annealing process in a boron rich atmosphere. The last step enables the electrical functionality of the irradiated material. Doubly clamped silicon beams are fabricated by this method. The electrical readout of their mechanical response can be addressed by a frequency down-mixing detection technique thanks to an enhanced piezoresistive transduction mechanism. Three specific aspects are discussed: (i) the engineering of mechanically coupled SiNWs, by making use of the nanometer scale overhang that it is inherently-generated with this fabrication process, (ii) the statistical distribution of patterned lateral dimensions when fabricating large arrays of identical devices, and (iii) the compatibility of the patterning methodology with CMOS circuits. Our results suggest that the application of this method to the integration of large arrays of suspended SiNWs with CMOS circuitry is interesting in view of applications such as advanced radio frequency band pass filters and ultra-high-sensitivity mass sensors.

  14. Dual-Polarized Antenna Arrays with CMOS Power Amplifiers for SiP Integration at W-Band

    Science.gov (United States)

    Giese, Malte; Vehring, Sönke; Böck, Georg; Jacob, Arne F.

    2017-09-01

    This paper presents requirements and front-end solutions for low-cost communication systems with data rates of 100 Gbit/s. Link budget analyses in different mass-market applications are conducted for that purpose. It proposes an implementation of the front-end as an active antenna array with support for beam steering and polarization multiplexing over the full W-band. The critical system components are investigated and presented. This applies to a transformer coupled power amplifier (PA) in 40 nm bulk CMOS. It shows saturated output power of more than 10 dBm and power-added-efficiency of more than 10 % over the full W-band. Furthermore, the performance of microstrip-to-waveguide transitions is shown exemplarily as an important part of the active antenna as it interfaces active circuitry and antenna in a polymer-and-metal process. The transition test design shows less than 0.9 dB insertion loss and more than 12 dB return loss for the differential transition over the full W-band.

  15. 1 mm3-sized optical neural stimulator based on CMOS integrated photovoltaic power receiver

    Science.gov (United States)

    Tokuda, Takashi; Ishizu, Takaaki; Nattakarn, Wuthibenjaphonchai; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a simple complementary metal-oxide semiconductor (CMOS)-controlled photovoltaic power-transfer platform that is suitable for very small (less than or equal to 1-2 mm) electronic devices such as implantable health-care devices or distributed nodes for the Internet of Things. We designed a 1.25 mm × 1.25 mm CMOS power receiver chip that contains integrated photovoltaic cells. We characterized the CMOS-integrated power receiver and successfully demonstrated blue light-emitting diode (LED) operation powered by infrared light. Then, we integrated the CMOS chip and a few off-chip components into a 1-mm3 implantable optogenetic stimulator, and demonstrated the operation of the device.

  16. Monolithic integration of SOI waveguide photodetectors and transimpedance amplifiers

    Science.gov (United States)

    Li, Shuxia; Tarr, N. Garry; Ye, Winnie N.

    2018-02-01

    In the absence of commercial foundry technologies offering silicon-on-insulator (SOI) photonics combined with Complementary Metal Oxide Semiconductor (CMOS) transistors, monolithic integration of conventional electronics with SOI photonics is difficult. Here we explore the implementation of lateral bipolar junction transistors (LBJTs) and Junction Field Effect Transistors (JFETs) in a commercial SOI photonics technology lacking MOS devices but offering a variety of n- and p-type ion implants intended to provide waveguide modulators and photodetectors. The fabrication makes use of the commercial Institute of Microelectronics (IME) SOI photonics technology. Based on knowledge of device doping and geometry, simple compact LBJT and JFET device models are developed. These models are then used to design basic transimpedance amplifiers integrated with optical waveguides. The devices' experimental current-voltage characteristics results are reported.

  17. Small Pixel Hybrid CMOS X-ray Detectors

    Science.gov (United States)

    Hull, Samuel; Bray, Evan; Burrows, David N.; Chattopadhyay, Tanmoy; Falcone, Abraham; Kern, Matthew; McQuaide, Maria; Wages, Mitchell

    2018-01-01

    Concepts for future space-based X-ray observatories call for a large effective area and high angular resolution instrument to enable precision X-ray astronomy at high redshift and low luminosity. Hybrid CMOS detectors are well suited for such high throughput instruments, and the Penn State X-ray detector lab, in collaboration with Teledyne Imaging Sensors, has recently developed new small pixel hybrid CMOS X-ray detectors. These prototype 128x128 pixel devices have 12.5 micron pixel pitch, 200 micron fully depleted depth, and include crosstalk eliminating CTIA amplifiers and in-pixel correlated double sampling (CDS) capability. We report on characteristics of these new detectors, including the best read noise ever measured for an X-ray hybrid CMOS detector, 5.67 e- (RMS).

  18. CMOS technology and current-feedback op-amps

    DEFF Research Database (Denmark)

    Bruun, Erik

    1993-01-01

    Some of the problems related to the application of CMOS technology to current-feedback operational amplifiers (CFB op-amps) are identified. Problems caused by the low device transconductance and by the absence of matching between p-channel and n-channel transistors are examined, and circuit...

  19. Modeling and Optimization of Class-E Amplifier at Subnominal Condition in a Wireless Power Transfer System for Biomedical Implants.

    Science.gov (United States)

    Liu, Hao; Shao, Qi; Fang, Xuelin

    2017-02-01

    For the class-E amplifier in a wireless power transfer (WPT) system, the design parameters are always determined by the nominal model. However, this model neglects the conduction loss and voltage stress of MOSFET and cannot guarantee the highest efficiency in the WPT system for biomedical implants. To solve this problem, this paper proposes a novel circuit model of the subnominal class-E amplifier. On a WPT platform for capsule endoscope, the proposed model was validated to be effective and the relationship between the amplifier's design parameters and its characteristics was analyzed. At a given duty ratio, the design parameters with the highest efficiency and safe voltage stress are derived and the condition is called 'optimal subnominal condition.' The amplifier's efficiency can reach the highest of 99.3% at the 0.097 duty ratio. Furthermore, at the 0.5 duty ratio, the measured efficiency of the optimal subnominal condition can reach 90.8%, which is 15.2% higher than that of the nominal condition. Then, a WPT experiment with a receiving unit was carried out to validate the feasibility of the optimized amplifier. In general, the design parameters of class-E amplifier in a WPT system for biomedical implants can be determined with the proposed optimization method in this paper.

  20. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  1. CMOS direct time interval measurement of long-lived luminescence lifetimes.

    Science.gov (United States)

    Yao, Lei; Yung, Ka Yi; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-01-01

    We describe a Complementary Metal-Oxide Semiconductor (CMOS) Direct Time Interval Measurement (DTIM) Integrated Circuit (IC) to detect the decay (fall) time of the luminescence emission when analyte-sensitive luminophores are excited with an optical pulse. The CMOS DTIM IC includes 14 × 14 phototransistor array, transimpedance amplifier, regulated gain amplifier, fall time detector, and time-to-digital convertor. We examined the DTIM system to measure the emission lifetime of oxygen-sensitive luminophores tris(4,7-diphenyl-1, 10-phenanthroline) ruthenium(II) ([Ru(dpp)(3)](2+)) encapsulated in sol-gel derived xerogel thin-films. The DTIM system fabricated using TSMC 0.35 μm process functions to detect lifetimes from 4 μs to 14.4 μs but can be tuned to detect longer lifetimes. The system provides 8-bit digital output proportional to lifetimes and consumes 4.5 mW of power with 3.3 V DC supply. The CMOS system provides a useful platform for the development of reliable, robust, and miniaturized optical chemical sensors.

  2. A 3.125-Gb/s inductorless transimpedance amplifier for optical communication in 0.35 μm CMOS

    International Nuclear Information System (INIS)

    Xu Hui; Feng Jun; Liu Quan; Li Wei

    2011-01-01

    A 3.125-Gb/s transimpedance amplifier (TIA) for an optical communication system is realized in 0.35 μm CMOS technology. The proposed TIA employs a regulated cascode configuration as the input stage, and adopts DC-cancellation techniques to stabilize the DC operating point. In addition, noise optimization is processed. The on-wafer measurement results show the transimpedance gain of 54.2 dBΩ and −3 dB bandwidth of 2.31 GHz. The measured average input referred noise current spectral density is about 18.8 pA/√Hz. The measured eye diagram is clear and symmetrical for 2.5-Gb/s and 3.125-Gb/s PRBS. Under a single 3.3-V supply voltage, the TIA consumes only 58.08 mW, including 20 mW from the output buffer. The whole die area is 465 × 435 μm 2 . (semiconductor integrated circuits)

  3. A Low-power CMOS BFSK Transceiver for Health Monitoring Systems.

    Science.gov (United States)

    Kim, Sungho; Lepkowski, William; Wilk, Seth J; Thornton, Trevor J; Bakkaloglu, Bertan

    2011-01-01

    A CMOS low-power transceiver for implantable and external health monitoring devices operating in the MICS band is presented. The LNA core has an integrated mixer in a folded configuration to reuse the bias current, allowing high linearity with a low power supply levels. The baseband strip consists of a pseudo differential MOS-C band-pass filter achieving demodulation of 150kHz-offset BFSK signals. An all digital frequency-locked loop is used for LO generation in the RX mode and for driving a class AB power amplifier in the TX mode. The MICS transceiver is designed and fabricated in a 0.18μm 1-poly, 6-metal CMOS process. The sensitivities of -70dBm and -98dBm were achieved with NF of 40dB and 11dB at the data rate of 100kb/s while consuming only 600μW and 1.5mW at 1.2V and 1.8V, respectively. The BERs are less than 10 -3 at the input powers of -70dBm at 1.2V and -98dBm at 1.8V at the data rate of 100kb/s. Finally, the output power of the transmitter is 0dBm for a power consumption of 1.8mW.

  4. Reducing Switching Artifacts in Chopper Amplifiers

    NARCIS (Netherlands)

    Kusuda, Y.

    2018-01-01

    This thesis describes the theory, design, and implementation of chopper operational amplifiers (op-amps) in CMOS integrated circuits (ICs). The chopping technique periodically corrects DC errors of such op-amps, so that low 1/f noise and stable, microvolt-level offset can be achieved. However,

  5. A 0.1-1.4 GHz inductorless low-noise amplifier with 13 dBm IIP3 and 24 dBm IIP2 in 180 nm CMOS

    Science.gov (United States)

    Guo, Benqing; Chen, Jun; Chen, Hongpeng; Wang, Xuebing

    2018-01-01

    An inductorless noise-canceling CMOS low-noise amplifier (LNA) with wideband linearization technique is proposed. The complementary configuration by stacked NMOS/PMOS is employed to compensate second-order nonlinearity of the circuit. The third-order distortion of the auxiliary stage is also mitigated by that of the weak inversion transistors in the main path. The bias and scaling size combined by digital control words are further tuned to obtain enhanced linearity over the desired band. Implemented in a 0.18 μm CMOS process, simulated results show that the proposed LNA provides a voltage gain of 16.1 dB and a NF of 2.8-3.4 dB from 0.1 GHz to 1.4 GHz. The IIP3 and IIP2 of 13-18.9 and 24-40 dBm are obtained, respectively. The circuit core consumes 19 mW from a 1.8 V supply.

  6. Characterization of active CMOS sensors for capacitively coupled pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Gonella, Laura; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn (Germany); Peric, Ivan [Institut fuer Prozessdatenverarbeitung und Elektronik, Karlsruher Institut fuer Technologie, Karlsruhe (Germany)

    2015-07-01

    Active CMOS pixel sensor is one of the most attractive candidates for detectors of upcoming particle physics experiments. In contrast to conventional sensors of hybrid detectors, signal processing circuit can be integrated in the active CMOS sensor. The characterization and optimization of the pixel circuit are indispensable to obtain a good performance from the sensors. The prototype chips of the active CMOS sensor were fabricated in the AMS 180nm and L-Foundry 150 nm CMOS processes, respectively a high voltage and high resistivity technology. Both chips have a charge sensitive amplifier and a comparator in each pixel. The chips are designed to be glued to the FEI4 pixel readout chip. The signals from 3 pixels of the prototype chips are capacitively coupled to the FEI4 input pads. We have performed lab tests and test beams to characterize the prototypes. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  7. CMOS optimization for radiation hardness

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Fossum, J.G.

    1975-01-01

    Several approaches to the attainment of radiation-hardened MOS circuits have been investigated in the last few years. These have included implanting the SiO 2 gate insulator with aluminum, using chrome-aluminum layered gate metallization, using Al 2 O 3 as the gate insulator, and optimizing the MOS fabrication process. Earlier process optimization studies were restricted primarily to p-channel devices operating with negative gate biases. Since knowledge of the hardness dependence upon processing and design parameters is essential in producing hardened integrated circuits, a comprehensive investigation of the effects of both process and design optimization on radiation-hardened CMOS integrated circuits was undertaken. The goals are to define and establish a radiation-hardened processing sequence for CMOS integrated circuits and to formulate quantitative relationships between process and design parameters and the radiation hardness. Using these equations, the basic CMOS design can then be optimized for radiation hardness and some understanding of the basic physics responsible for the radiation damage can be gained. Results are presented

  8. An Electronically Tunable Transconductance Amplifier for Use in Auditory Prostheses

    Directory of Open Access Journals (Sweden)

    FARAGO, P.

    2015-11-01

    Full Text Available Low-voltage and low-power trends in analog electronics enable novel features in modern bio-medical devices, such as extensive portability, autonomy and even battery-less operation. One specific example is the cochlear implant (CI, which emulates the physiology of hearing to produce auditory sensations via neural stimulation. Besides low-voltage and low-power operation, a key feature in modern CIs is wide-range programmability of the speech processing parameters. This paper proposes an operational transconductance amplifier (OTA for use in CIs, with wide-range electronic tuning of the transconductance value. The proposed OTA is developed around a cascade of two transconductor stages, making the transconductance dependent on the bias current ratio. A combination of linearization techniques: bulk input, parallel differential pairs and feedback, is used to achieve sufficient linear range for CI speech processing. Wide-range parameter tuning of the speech processing sections is illustrated on a variable gain amplifier, a bandpass Tow-Thomas biquad and an envelope detector. Finally, the complete CI speech processing chain is illustrated. The proposed OTA and its employment in CI analog speech processing are validated on a 350 nm CMOS process.

  9. A Wireless Fiber Photometry System Based on a High-Precision CMOS Biosensor With Embedded Continuous-Time Modulation.

    Science.gov (United States)

    Khiarak, Mehdi Noormohammadi; Martianova, Ekaterina; Bories, Cyril; Martel, Sylvain; Proulx, Christophe D; De Koninck, Yves; Gosselin, Benoit

    2018-06-01

    Fluorescence biophotometry measurements require wide dynamic range (DR) and high-sensitivity laboratory apparatus. Indeed, it is often very challenging to accurately resolve the small fluorescence variations in presence of noise and high-background tissue autofluorescence. There is a great need for smaller detectors combining high linearity, high sensitivity, and high-energy efficiency. This paper presents a new biophotometry sensor merging two individual building blocks, namely a low-noise sensing front-end and a order continuous-time modulator (CTSDM), into a single module for enabling high-sensitivity and high energy-efficiency photo-sensing. In particular, a differential CMOS photodetector associated with a differential capacitive transimpedance amplifier-based sensing front-end is merged with an incremental order 1-bit CTSDM to achieve a large DR, low hardware complexity, and high-energy efficiency. The sensor leverages a hardware sharing strategy to simplify the implementation and reduce power consumption. The proposed CMOS biosensor is integrated within a miniature wireless head mountable prototype for enabling biophotometry with a single implantable fiber in the brain of live mice. The proposed biophotometry sensor is implemented in a 0.18- CMOS technology, consuming from a 1.8- supply voltage, while achieving a peak dynamic range of over a 50- input bandwidth, a sensitivity of 24 mV/nW, and a minimum detectable current of 2.46- at a 20- sampling rate.

  10. Merits of CMOS/SIMOX technology for low-voltage SRAM macros

    CERN Document Server

    Kumagai, K; Yamada, T; Nakamura, H; Onishi, H; Matsubara, Y; Imai, K; Kurosawa, S

    1999-01-01

    A 128-kbit SRAM (static random access memory) macro with the 0.35 mu m FD (fully-depleted) CMOS/SIMOX (separation by implantation of oxygen) technology has been developed to demonstrate the merits of that technology for low-voltage $9 applications. Its access time at Vdd =1.5 V was comparable with that obtained with the 0.35 mu m standard bulk CMOS technology at Vdd=3.3 V, due to the combination of the small S/D capacitance and the small back-bias effect. As the $9 yield of the 128-kbit SRAM macros was almost the same as the standard bulk CMOS technology, the manufacturability of the 0.35 mu m FD-CMOS/SIMOX technology has also been demonstrated. (7 refs).

  11. Hybrid Josephson-CMOS memory: a solution for the Josephson memory problem

    International Nuclear Information System (INIS)

    Duzer, Theodore van; Feng Yijun; Meng Xiaofan; Whiteley, Stephen R; Yoshikawa, Nobuyuki

    2002-01-01

    The history of the development of superconductive memory for Josephson digital systems is presented along with the several current proposals. The main focus is on a proposed combination of the highly developed CMOS memory technology with Josephson peripheral circuits to achieve memories of significant size with subnanosecond access time. Background material is presented on the cryogenic operation of CMOS. Simulations and experiments on components of memory with emphasis on the important input interface amplifier are presented

  12. Using MEMS Capacitive Switches in Tunable RF Amplifiers

    OpenAIRE

    Danson John; Plett Calvin; Tait Niall

    2006-01-01

    A MEMS capacitive switch suitable for use in tunable RF amplifiers is described. A MEMS switch is designed, fabricated, and characterized with physical and RF measurements for inclusion in simulations. Using the MEMS switch models, a dual-band low-noise amplifier (LNA) operating at GHz and GHz, and a tunable power amplifier (PA) at GHz are simulated in m CMOS. MEMS switches allow the LNA to operate with 11 dB of isolation between the two bands while maintaining dB of gain and sub- dB no...

  13. Frontend Receiver Electronics for High Frequency Monolithic CMUT-on-CMOS Imaging Arrays

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F. Levent

    2012-01-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for high-frequency intravascular ultrasound imaging. A custom 8-inch wafer is fabricated in a 0.35 μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulse-echo measurement. Transducer noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 MHz to 20 MHz. PMID:21859585

  14. Transimpedance Amplifier for MEMS SAW Oscillator in 1.4GHz

    Science.gov (United States)

    Kamarudin, N.; Karim, J.; Hussin, H.

    2018-03-01

    This work is to design a transimpedance amplifier for MEMS SAW resonator to achieve low power consumption at desired frequency. A transimpedance amplifier is designed and characterized for MEMS SAW resonator in 0.18μm CMOS process. The transimpedance amplifier achieves gain is 31 dBΩ at 176°. The power consume by oscillator is 0.6mW at VDD 1.8V while phase noise at -133.97dBc/Hz at 10kHz.

  15. High speed photodiodes in standard nanometer scale CMOS technology: a comparative study.

    Science.gov (United States)

    Nakhkoob, Behrooz; Ray, Sagar; Hella, Mona M

    2012-05-07

    This paper compares various techniques for improving the frequency response of silicon photodiodes fabricated in mainstream CMOS technology for fully integrated optical receivers. The three presented photodiodes, Spatially Modulated Light detectors, Double, and Interrupted P-Finger photodiodes, aim at reducing the low speed diffusive component of the photo generated current. For the first photodiode, Spatially Modulated Light (SML) detectors, the low speed current component is canceled out by converting it to a common mode current driving a differential transimpedance amplifier. The Double Photodiode (DP) uses two depletion regions to increase the fast drift component, while the Interrupted-P Finger Photodiode (IPFPD) redirects the low speed component towards a different contact from the main fast terminal of the photodiode. Extensive device simulations using 130 nm CMOS technology-parameters are presented to compare their performance using the same technological platform. Finally a new type of photodiode that uses triple well CMOS technology is introduced that can achieve a bandwidth of roughly 10 GHz without any process modification or high reverse bias voltages that would jeopardize the photodetector and subsequent transimpedance amplifier reliability.

  16. A transimpedance amplifier using a novel current mode feedback loop

    CERN Document Server

    Anghinolfi, Francis; Delagnes, E; Jarron, Pierre; Scharfetter, L H H

    1995-01-01

    We present a transimpedance amplifier stage based on a novel current mode feedback topology. This circuit employs NMOS and PMOS transistors exclusively and requires neither capacitor for stabilizing the transimpedance loop nor resistor for the transresistance feedback and transistor loading. This amplifier circuit is fully compatible with submicron digital CMOS processes. The active feedback network consists of two grounded-gate MOS devices which split the output current in both the feedback and output branches. The transresistance and the phase margin are adjustable through external DC signals. The measured rise time of the impulse response of the amplifier implemented in an industrial 0,7µm CMOS process is 18 ns for a transresistance of 180 k‡ and 30 ns for a transresistance of 560 k‡. The measured Equivalent Noise Charge (ENC) is 800 rms e¯ for an input capacitance of 20 pF with the transresistance adjusted to 560 k‡.

  17. Simple BiCMOS CCCTA design and resistorless analog function realization.

    Science.gov (United States)

    Tangsrirat, Worapong

    2014-01-01

    The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA) in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (R x) and current transfer (i o/i z), are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  18. Simple BiCMOS CCCTA Design and Resistorless Analog Function Realization

    Directory of Open Access Journals (Sweden)

    Worapong Tangsrirat

    2014-01-01

    Full Text Available The simple realization of the current-controlled conveyor transconductance amplifier (CCCTA in BiCMOS technology is introduced. The proposed BiCMOS CCCTA realization is based on the use of differential pair and basic current mirror, which results in simple structure. Its characteristics, that is, parasitic resistance (Rx and current transfer (io/iz, are also tunable electronically by external bias currents. The realized circuit is suitable for fabrication using standard 0.35 μm BiCMOS technology. Some simple and compact resistorless applications employing the proposed CCCTA as active elements are also suggested, which show that their circuit characteristics with electronic controllability are obtained. PSPICE simulation results demonstrating the circuit behaviors and confirming the theoretical analysis are performed.

  19. Evaluation of electron beam stabilization for ion implant processing

    Science.gov (United States)

    Buffat, Stephen J.; Kickel, Bee; Philipps, B.; Adams, J.; Ross, Matthew F.; Minter, Jason P.; Marlowe, Trey; Wong, Selmer S.

    1999-06-01

    With the integration of high energy ion implant processes into volume CMOS manufacturing, the need for thick resist stabilization to achieve a stable ion implant process is critical. With new photoresist characteristics, new implant end station characteristics arise. The resist outgassing needs to be addressed as well as the implant profile to ensure that the dosage is correct and the implant angle does not interfere with other underlying features. This study compares conventional deep-UV/thermal with electron beam stabilization. The electron beam system used in this study utilizes a flood electron source and is a non-thermal process. These stabilization techniques are applied to a MeV ion implant process in a CMOS production process flow.

  20. A transimpedance CMOS multichannel amplifier with a 50 Ω-wide output range buffer for high counting rate applications

    International Nuclear Information System (INIS)

    Haralabidis, N.; Loukas, D.; Misiakos, K.; Katsafouros, S.

    1997-01-01

    A fast transimpedance multichannel amplifier has been designed, fabricated in CMOS 1.2-microm technology and tested. Each channel consists of a current sensitive preamplifier followed by a voltage amplification stage and an on-chip buffer able to drive 50 Ω loads with an output range of ±800 mV. Measured peaking time at the output is 40 ns and the circuit recovers to baseline in 90 ns. This results in a counting capability of more than 10 7 hits/s. Signals of both polarities can be handled. The first two stages consume a total of 2 mW per channel and the 50 Ω buffer consumes another 17 mW. The equivalent noise charge (ENC) is 1,100 e - rms with a slope of 40e - /pF. The IC is intended for use in gas and solid-state detectors with high particle rate and extensive charge release as in high energy calorimetry

  1. Low noise monolithic CMOS front end electronics

    International Nuclear Information System (INIS)

    Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

    1987-01-01

    Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

  2. Wide modulation bandwidth terahertz detection in 130 nm CMOS technology

    Science.gov (United States)

    Nahar, Shamsun; Shafee, Marwah; Blin, Stéphane; Pénarier, Annick; Nouvel, Philippe; Coquillat, Dominique; Safwa, Amr M. E.; Knap, Wojciech; Hella, Mona M.

    2016-11-01

    Design, manufacturing and measurements results for silicon plasma wave transistors based wireless communication wideband receivers operating at 300 GHz carrier frequency are presented. We show the possibility of Si-CMOS based integrated circuits, in which by: (i) specific physics based plasma wave transistor design allowing impedance matching to the antenna and the amplifier, (ii) engineering the shape of the patch antenna through a stacked resonator approach and (iii) applying bandwidth enhancement strategies to the design of integrated broadband amplifier, we achieve an integrated circuit of the 300 GHz carrier frequency receiver for wireless wideband operation up to/over 10 GHz. This is, to the best of our knowledge, the first demonstration of low cost 130 nm Si-CMOS technology, plasma wave transistors based fast/wideband integrated receiver operating at 300 GHz atmospheric window. These results pave the way towards future large scale (cost effective) silicon technology based terahertz wireless communication receivers.

  3. Wideband pulse amplifiers for the NECTAr chip

    International Nuclear Information System (INIS)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J-F.; Naumann, C.L.; Nayman, P.; Ribó, M.

    2012-01-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1–3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  4. Wideband pulse amplifiers for the NECTAr chip

    Science.gov (United States)

    Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

    2012-12-01

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  5. An Implantable Cardiovascular Pressure Monitoring System with On-Chip Antenna and RF Energy Harvesting

    Directory of Open Access Journals (Sweden)

    Yu-Chun Liu

    2015-08-01

    Full Text Available An implantable wireless system with on-chip antenna for cardiovascular pressure monitor is studied. The implantable device is operated in a batteryless manner, powered by an external radio frequency (RF power source. The received RF power level can be sensed and wirelessly transmitted along with blood pressure signal for feedback control of the external RF power. The integrated electronic system, consisting of a capacitance-to-voltage converter, an adaptive RF powering system, an RF transmitter and digital control circuitry, is simulated using a TSMC 0.18 μm CMOS technology. The implanted RF transmitter circuit is combined with a low power voltage-controlled oscillator resonating at 5.8 GHz and a power amplifier. For the design, the simulation model is setup using ADS and HFSS software. The dimension of the antenna is 1 × 0.6 × 4.8 mm3 with a 1 × 0.6 mm2 on-chip circuit which is small enough to place in human carotid artery.

  6. Front-end receiver electronics for high-frequency monolithic CMUT-on-CMOS imaging arrays.

    Science.gov (United States)

    Gurun, Gokce; Hasler, Paul; Degertekin, F

    2011-08-01

    This paper describes the design of CMOS receiver electronics for monolithic integration with capacitive micromachined ultrasonic transducer (CMUT) arrays for highfrequency intravascular ultrasound imaging. A custom 8-inch (20-cm) wafer is fabricated in a 0.35-μm two-poly, four-metal CMOS process and then CMUT arrays are built on top of the application specific integrated circuits (ASICs) on the wafer. We discuss advantages of the single-chip CMUT-on-CMOS approach in terms of receive sensitivity and SNR. Low-noise and high-gain design of a transimpedance amplifier (TIA) optimized for a forward-looking volumetric-imaging CMUT array element is discussed as a challenging design example. Amplifier gain, bandwidth, dynamic range, and power consumption trade-offs are discussed in detail. With minimized parasitics provided by the CMUT-on-CMOS approach, the optimized TIA design achieves a 90 fA/√Hz input-referred current noise, which is less than the thermal-mechanical noise of the CMUT element. We show successful system operation with a pulseecho measurement. Transducer-noise-dominated detection in immersion is also demonstrated through output noise spectrum measurement of the integrated system at different CMUT bias voltages. A noise figure of 1.8 dB is obtained in the designed CMUT bandwidth of 10 to 20 MHz.

  7. A CMOS Low-Power Optical Front-End for 5 Gbps Applications

    Science.gov (United States)

    Zohoori, Soorena; Dolatshahi, Mehdi

    2018-01-01

    In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

  8. 5.2-GHz RF Power Harvester in 0.18-/spl mu/m CMOS for Implantable Intraocular Pressure Monitoring

    KAUST Repository

    Ouda, Mahmoud H.

    2013-04-17

    A first fully integrated 5.2-GHz CMOS-based RF power harvester with an on-chip antenna is presented in this paper. The design is optimized for sensors implanted inside the eye to wirelessly monitor the intraocular pressure of glaucoma patients. It includes a five-stage RF rectifier with an on-chip antenna, a dc voltage limiter, two voltage sensors, a low dropout voltage regulator, and MOSCAP based on-chip storage. The chip has been designed and fabricated in a standard 0.18-μm CMOS technology. To emulate the eye environment in measurements, a custom test setup is developed that comprises Plexiglass cavities filled with saline solution. Measurements in this setup show that the proposed chip can be charged to 1 V wirelessly from a 5-W transmitter 3 cm away from the harvester chip. The energy that is stored on the 5-nF on-chip MOSCAP when charged to 1 V is 2.5 nJ, which is sufficient to drive an arbitrary 100-μW load for 9 μs at regulated 0.8 V. Simulated efficiency of the rectifier is 42% at -7 dBm of input power.

  9. Wideband pulse amplifiers for the NECTAr chip

    Energy Technology Data Exchange (ETDEWEB)

    Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

    2012-12-11

    The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

  10. Properties of CMOS devices and circuits fabricated on high-resistivity, detector-grade silicon

    International Nuclear Information System (INIS)

    Holland, S.

    1991-11-01

    A CMOS process that is compatible with silicon p-i-n radiation detectors has been developed and characterized. A total of twelve mask layers are used in the process. The NMOS device is formed in a retrograde well while the PMOS device is fabricated directly in the high-resistivity silicon. Isolation characteristics are similar to a standard foundary CMOS process. Circuit performance using 3 μm design rules has been evaluated. The measured propagation delay and power-delay product for a 51-stage ring oscillator was 1.5 ns and 43 fJ, respectively. Measurements on a simple cascode amplifier results in a gain-bandwidth product of 200 MHz at a bias current of 15 μA. The input-referred noise of the cascode amplifier is 20 nV/√Hz at 1 MHz

  11. Bandwidth tunable amplifier for recording biopotential signals.

    Science.gov (United States)

    Hwang, Sungkil; Aninakwa, Kofi; Sonkusale, Sameer

    2010-01-01

    This paper presents a low noise, low power, bandwidth tunable amplifier for bio-potential signal recording applications. By employing depletion-mode pMOS transistor in diode configuration as a tunable sub pA current source to adjust the resistivity of MOS-Bipolar pseudo-resistor, the bandwidth is adjusted without any need for a separate band-pass filter stage. For high CMRR, PSRR and dynamic range, a fully differential structure is used in the design of the amplifier. The amplifier achieves a midband gain of 39.8dB with a tunable high-pass cutoff frequency ranging from 0.1Hz to 300Hz. The amplifier is fabricated in 0.18εm CMOS process and occupies 0.14mm(2) of chip area. A three electrode ECG measurement is performed using the proposed amplifier to show its feasibility for low power, compact wearable ECG monitoring application.

  12. Characterization of various Si-photodiode junction combinations and layout specialities in 0.18µm CMOS and HV-CMOS technologies

    Science.gov (United States)

    Jonak-Auer, I.; Synooka, O.; Kraxner, A.; Roger, F.

    2017-12-01

    With the ongoing miniaturization of CMOS technologies the need for integrated optical sensors on smaller scale CMOS nodes arises. In this paper we report on the development and implementation of different optical sensor concepts in high performance 0.18µm CMOS and high voltage (HV) CMOS technologies on three different substrate materials. The integration process is such that complete modularity of the CMOS processes remains untouched and no additional masks or ion implantation steps are necessary for the sensor integration. The investigated processes support 1.8V and 3V standard CMOS functionality as well as HV transistors capable of operating voltages of 20V and 50V. These processes intrinsically offer a wide variety of junction combinations, which can be exploited for optical sensing purposes. The availability of junction depths from submicron to several microns enables the selection of spectral range from blue to infrared wavelengths. By appropriate layout the contributions of photo-generated carriers outside the target spectral range can be kept to a minimum. Furthermore by making use of other features intrinsically available in 0.18µm CMOS and HV-CMOS processes dark current rates of optoelectronic devices can be minimized. We present TCAD simulations as well as spectral responsivity, dark current and capacitance data measured for various photodiode layouts and the influence of different EPI and Bulk substrate materials thereon. We show examples of spectral responsivity of junction combinations optimized for peak sensitivity in the ranges of 400-500nm, 550-650nm and 700-900nm. Appropriate junction combination enables good spectral resolution for colour sensing applications even without any additional filter implementation. We also show that by appropriate use of shallow trenches dark current values of photodiodes can further be reduced.

  13. Analog filters in nanometer CMOS

    CERN Document Server

    Uhrmann, Heimo; Zimmermann, Horst

    2014-01-01

    Starting from the basics of analog filters and the poor transistor characteristics in nanometer CMOS 10 high-performance analog filters developed by the authors in 120 nm and 65 nm CMOS are described extensively. Among them are gm-C filters, current-mode filters, and active filters for system-on-chip realization for Bluetooth, WCDMA, UWB, DVB-H, and LTE applications. For the active filters several operational amplifier designs are described. The book, furthermore, contains a review of the newest state of research on low-voltage low-power analog filters. To cover the topic of the book comprehensively, linearization issues and measurement methods for the characterization of advanced analog filters are introduced in addition. Numerous elaborate illustrations promote an easy comprehension. This book will be of value to engineers and researchers in industry as well as scientists and Ph.D students at universities. The book is also recommendable to graduate students specializing on nanoelectronics, microelectronics ...

  14. A High Speed CMOS Image Sensor with a Novel Digital Correlated Double Sampling and a Differential Difference Amplifier

    Directory of Open Access Journals (Sweden)

    Daehyeok Kim

    2015-03-01

    Full Text Available In order to increase the operating speed of a CMOS image sensor (CIS, a new technique of digital correlated double sampling (CDS is described. In general, the fixed pattern noise (FPN of a CIS has been reduced with the subtraction algorithm between the reset signal and pixel signal. This is because a single-slope analog-to-digital converter (ADC has been normally adopted in the conventional digital CDS with the reset ramp and signal ramp. Thus, the operating speed of a digital CDS is much slower than that of an analog CDS. In order to improve the operating speed, we propose a novel digital CDS based on a differential difference amplifier (DDA that compares the reset signal and the pixel signal using only one ramp. The prototype CIS has been fabricated with 0.13 µm CIS technology and it has the VGA resolution of 640 × 480. The measured conversion time is 16 µs, and a high frame rate of 131 fps is achieved at the VGA resolution.

  15. A Glucose Biosensor Using CMOS Potentiostat and Vertically Aligned Carbon Nanofibers.

    Science.gov (United States)

    Al Mamun, Khandaker A; Islam, Syed K; Hensley, Dale K; McFarlane, Nicole

    2016-08-01

    This paper reports a linear, low power, and compact CMOS based potentiostat for vertically aligned carbon nanofibers (VACNF) based amperometric glucose sensors. The CMOS based potentiostat consists of a single-ended potential control unit, a low noise common gate difference-differential pair transimpedance amplifier and a low power VCO. The potentiostat current measuring unit can detect electrochemical current ranging from 500 nA to 7 [Formula: see text] from the VACNF working electrodes with high degree of linearity. This current corresponds to a range of glucose, which depends on the fiber forest density. The potentiostat consumes 71.7 [Formula: see text] of power from a 1.8 V supply and occupies 0.017 [Formula: see text] of chip area realized in a 0.18 [Formula: see text] standard CMOS process.

  16. CMOS 60-GHz and E-band power amplifiers and transmitters

    CERN Document Server

    Zhao, Dixian

    2015-01-01

    This book focuses on the development of design techniques and methodologies for 60-GHz and E-band power amplifiers and transmitters at device, circuit and layout levels. The authors show the recent development of millimeter-wave design techniques, especially of power amplifiers and transmitters, and presents novel design concepts, such as “power transistor layout” and “4-way parallel-series power combiner”, that can enhance the output power and efficiency of power amplifiers in a compact silicon area. Five state-of-the-art 60-GHz and E-band designs with measured results are demonstrated to prove the effectiveness of the design concepts and hands-on methodologies presented. This book serves as a valuable reference for circuit designers to develop millimeter-wave building blocks for future 5G applications.

  17. CMOS technology: a critical enabler for free-form electronics-based killer applications

    Science.gov (United States)

    Hussain, Muhammad M.; Hussain, Aftab M.; Hanna, Amir

    2016-05-01

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today's CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics - and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path.

  18. On-chip power-combining techniques for watt-level linear power amplifiers in 0.18 μm CMOS

    International Nuclear Information System (INIS)

    Ren Zhixiong; Zhang Kefeng; Liu Lanqi; Li Cong; Chen Xiaofei; Liu Dongsheng; Liu Zhenglin; Zou Xuecheng

    2015-01-01

    Three linear CMOS power amplifiers (PAs) with high output power (more than watt-level output power) for high data-rate mobile applications are introduced. To realize watt-level output power, there are two 2.4 GHz PAs using an on-chip parallel combining transformer (PCT) and one 1.95 GHz PA using an on-chip series combining transformer (SCT) to combine output signals of multiple power stages. Furthermore, some linearization techniques including adaptive bias, diode linearizer, multi-gated transistors (MGTR) and the second harmonic control are applied in these PAs. Using the proposed power combiner, these three PAs are designed and fabricated in TSMC 0.18 μm RFCMOS process. According to the measurement results, the proposed two linear 2.4 GHz PAs achieve a gain of 33.2 dB and 34.3 dB, a maximum output power of 30.7 dBm and 29.4 dBm, with 29% and 31.3% of peak PAE, respectively. According to the simulation results, the presented linear 1.95 GHz PA achieves a gain of 37.5 dB, a maximum output power of 34.3 dBm with 36.3% of peak PAE. (paper)

  19. A novel input-parasitic compensation technique for a nanopore-based CMOS DNA detection sensor

    Science.gov (United States)

    Kim, Jungsuk

    2016-12-01

    This paper presents a novel input-parasitic compensation (IPC) technique for a nanopore-based complementary metal-oxide-semiconductor (CMOS) DNA detection sensor. A resistive-feedback transimpedance amplifier is typically adopted as the headstage of a DNA detection sensor to amplify the minute ionic currents generated from a nanopore and convert them to a readable voltage range for digitization. But, parasitic capacitances arising from the headstage input and the nanopore often cause headstage saturation during nanopore sensing, thereby resulting in significant DNA data loss. To compensate for the unwanted saturation, in this work, we propose an area-efficient and automated IPC technique, customized for a low-noise DNA detection sensor, fabricated using a 0.35- μm CMOS process; we demonstrated this prototype in a benchtop test using an α-hemolysin ( α-HL) protein nanopore.

  20. Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

    Directory of Open Access Journals (Sweden)

    Eugen Egel

    2017-05-01

    Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

  1. Using MEMS Capacitive Switches in Tunable RF Amplifiers

    Directory of Open Access Journals (Sweden)

    Danson John

    2006-01-01

    Full Text Available A MEMS capacitive switch suitable for use in tunable RF amplifiers is described. A MEMS switch is designed, fabricated, and characterized with physical and RF measurements for inclusion in simulations. Using the MEMS switch models, a dual-band low-noise amplifier (LNA operating at GHz and GHz, and a tunable power amplifier (PA at GHz are simulated in m CMOS. MEMS switches allow the LNA to operate with 11 dB of isolation between the two bands while maintaining dB of gain and sub- dB noise figure. MEMS switches are used to implement a variable matching network that allows the PA to realize up to 37% PAE improvement at low input powers.

  2. CMOS Optoelectronic Lock-In Amplifier With Integrated Phototransistor Array.

    Science.gov (United States)

    An Hu; Chodavarapu, Vamsy P

    2010-10-01

    We describe the design and development of an optoelectronic lock-in amplifier (LIA) for optical sensing and spectroscopy applications. The prototype amplifier is fabricated using Taiwan Semiconductor Manufacturing Co. complementary metal-oxide semiconductor 0.35-μm technology and uses a phototransistor array (total active area is 400 μm × 640μm) to convert the incident optical signals into electrical currents. The photocurrents are then converted into voltage signals using a transimpedance amplifier for subsequent convenient signal processing by the LIA circuitry. The LIA is optimized to be operational at 20-kHz modulation frequency but is operational in the frequency range from 13 kHz to 25 kHz. The system is tested with a light-emitting diode (LED) as the light source. The noise and signal distortions are suppressed with filters and a phase-locked loop (PLL) implemented in the LIA. The output dc voltage of the LIA is proportional to the incident optical power. The minimum measured dynamic reserve and sensitivity are 1.31 dB and 34 mV/μW, respectively. The output versus input relationship has shown good linearity. The LIA consumes an average power of 12.79 mW with a 3.3-V dc power supply.

  3. CMOS technology: a critical enabler for free-form electronics-based killer applications

    KAUST Repository

    Hussain, Muhammad Mustafa

    2016-05-17

    Complementary metal oxide semiconductor (CMOS) technology offers batch manufacturability by ultra-large-scaleintegration (ULSI) of high performance electronics with a performance/cost advantage and profound reliability. However, as of today their focus has been on rigid and bulky thin film based materials. Their applications have been limited to computation, communication, display and vehicular electronics. With the upcoming surge of Internet of Everything, we have critical opportunity to expand the world of electronics by bridging between CMOS technology and free form electronics which can be used as wearable, implantable and embedded form. The asymmetry of shape and softness of surface (skins) in natural living objects including human, other species, plants make them incompatible with the presently available uniformly shaped and rigidly structured today’s CMOS electronics. But if we can break this barrier then we can use the physically free form electronics for applications like plant monitoring for expansion of agricultural productivity and quality, we can find monitoring and treatment focused consumer healthcare electronics – and many more creative applications. In our view, the fundamental challenge is to engage the mass users to materialize their creative ideas. Present form of electronics are too complex to understand, to work with and to use. By deploying game changing additive manufacturing, low-cost raw materials, transfer printing along with CMOS technology, we can potentially stick high quality CMOS electronics on any existing objects and embed such electronics into any future objects that will be made. The end goal is to make them smart to augment the quality of our life. We use a particular example on implantable electronics (brain machine interface) and its integration strategy enabled by CMOS device design and technology run path. © (2016) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is

  4. High energy ion implantation

    International Nuclear Information System (INIS)

    Ziegler, J.F.

    1985-01-01

    High energy ion implantation offers the oppertunity for unique structures in semiconductor processing. The unusual physical properties of such implantations are discussed as well as the special problems in masking and damage annealing. A review is made of proposed circuit structures which involve deep implantation. Examples are: deep buried bipolar collectors fabricated without epitaxy, barrier layers to reduce FET memory sensitivity to soft-fails, CMOS isolation well structures, MeV implantation for customization and correction of completed circuits, and graded reach-throughs to deep active device components. (orig.)

  5. A fully integrated 16 channel digitally trimmed pulse shaping amplifier

    International Nuclear Information System (INIS)

    Hearn, W.E.; Wright, M.E.

    1993-11-01

    A fully integrated CMOS pulse shaping amplifier has been developed at LBL. All frequency dependent networks are included on the chip. Provision is made for tuning to compensate for process variations. The overall architecture and details of the circuitry are discussed. Test results are presented

  6. A fast large dynamic range shaping amplifier for particle detector front-end

    International Nuclear Information System (INIS)

    Rivetti, Angelo; Delaurenti, Paolo

    2007-01-01

    The paper describes a fast shaping amplifier with rail-to-rail output swing. The circuit is based on a CMOS operational amplifier with a class AB output stage. A baseline holder, incorporating a closed-loop unity gain buffer with slew rate limitation, performs the AC coupling with the preamplifier and guarantees a baseline shift smaller than 3 mV for unipolar output pulses of 3 V and 10 MHz rate

  7. DISEÑO DE UN AMPLIFICADOR RIEL A RIEL CON TECNOLOGÍA CMOS 0,18 µm DESENHO DE UM AMPLIFICADOR DO TRILHO-A-TRILHO COM TECNOLOGIA CMOS 0,18 µm DESIGN OF A RAIL-TO-RAIL AMPLIFIER WITH 0.18 µm TECHNOLOGY

    Directory of Open Access Journals (Sweden)

    Diego F. Hernández

    2012-06-01

    Full Text Available En este artículo se realiza el análisis, diseño y simulación de un amplificador rail to rail R-R (riel a riel a la entrada y a la salida utilizando una fuente sencilla de 3,3 V. La tecnología usada fue CMOS TSMC de 0,18 µm, de bajo costo relativo para uso académico. El proceso de implementación se hizo con herramientas industrial Synopsys. En el artículo se detalla la etapa de entrada R-R complementaria, se describen el circuito sumador y la etapa de salida R-R clase AB. Finalmente, se muestran el layout definitivo y los resultados de la evaluación del diseño.Em este artigo realiza-se a análise, desenho e simulação de um amplificador rail to rail R-R (trilho a trilho à entrada e à saída utilizando uma fonte singela de 3,3 V. A tecnologia usada foi CMOS TSMC de 0,18 µm, de relativo baixo custo para uso acadêmico. O processo de implementação realizou-se com ferramentas industrial Synopsys. No artigo detalha-se a etapa de entrada R-R complementar, descreve-se o circuito somador e a etapa de saída R-R classe AB. Finalmente, mostra-se o layout definitivo e os resultados da avaliação do desenho.This paper shows the full analysis, design and simulation of a 3.3 V CMOS input/output rail to rail or R-R operational amplifier using the design kit for the Synopsys tools. The technology used was CMOS TSMC 0.18µm whose cost is low for academic purposes. This paper details the complementary input stage R-R, the summing circuit and the R-R output stage class AB. At last the final layout and the results of simulation are shown.

  8. Reduced impact of induced gate noise on inductively degenerated LNAs in deep submicron CMOS technologies

    DEFF Research Database (Denmark)

    Rossi, P.; Svelto, F.; Mazzanti, A.

    2005-01-01

    Designers of radio-frequency inductively-degenerated CMOS low-noise-amplifiers have usually not followed the guidelines for achieving minimum noise figure. Nonetheless, state-of-the- art implementations display noise figure values very close to the theoretical minimum. In this paper, we point out...... that this is due to the effect of the parasitic overlap capacitances in the MOS device. In particular, we show that overlap capacitances lead to a significant induced-gate-noise reduction, especially when deep sub-micron CMOS processes are used....

  9. A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

    Science.gov (United States)

    Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

    2013-04-01

    In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

  10. Mechanisms of Low-Energy Operation of XCT-SOI CMOS Devices—Prospect of Sub-20-nm Regime

    Directory of Open Access Journals (Sweden)

    Yasuhisa Omura

    2014-01-01

    Full Text Available This paper describes the performance prospect of scaled cross-current tetrode (XCT CMOS devices and demonstrates the outstanding low-energy aspects of sub-30-nm-long gate XCT-SOI CMOS by analyzing device operations. The energy efficiency improvement of such scaled XCT CMOS circuits (two orders higher stems from the “source potential floating effect”, which offers the dynamic reduction of effective gate capacitance. It is expected that this feature will be very important in many medical implant applications that demand a long device lifetime without recharging the battery.

  11. A Low-Power CMOS Front-End for Photoplethysmographic Signal Acquisition With Robust DC Photocurrent Rejection.

    Science.gov (United States)

    Wong, A K Y; Kong-Pang Pun; Yuan-Ting Zhang; Ka Nang Leung

    2008-12-01

    A micro-power CMOS front-end, consisting of a transimpedance amplifier (TIA) and an ultralow cutoff frequency lowpass filter for the acquisition of photoplethysmographic signal (PPG) is presented. Robust DC photocurrent rejection for the pulsed signal source is achieved through a sample-and-hold stage in the feed-forward signal path and an error amplifier in the feedback path. Ultra-low cutoff frequency of the filter is achieved with a proposed technique that incorporates a pair of current-steering transistors that increases the effective filter capacitance. The design was realized in a 0.35-mum CMOS technology. It consumes 600 muW at 2.5 V, rejects DC photocurrent ranged from 100 nA to 53.6 muA, and achieves lower-band and upper-band - 3-dB cutoff frequencies of 0.46 and 2.8 Hz, respectively.

  12. CMOS-based optical energy harvesting circuit for biomedical and Internet of Things devices

    Science.gov (United States)

    Nattakarn, Wuthibenjaphonchai; Ishizu, Takaaki; Haruta, Makito; Noda, Toshihiko; Sasagawa, Kiyotaka; Tokuda, Takashi; Sawan, Mohamad; Ohta, Jun

    2018-04-01

    In this work, we present a novel CMOS-based optical energy harvesting technology for implantable and Internet of Things (IoT) devices. In the proposed system, a CMOS energy-harvesting circuit accumulates a small amount of photoelectrically converted energy in an external capacitor, and intermittently supplies this power to a target device. Two optical energy-harvesting circuit types were implemented and evaluated. Furthermore, we developed a photoelectrically powered optical identification (ID) circuit that is suitable for IoT technology applications.

  13. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording

    Directory of Open Access Journals (Sweden)

    Marco Crescentini

    2016-05-01

    Full Text Available High-throughput screening (HTS using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i design of scalable microfluidic devices; (ii design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

  14. A Low-Noise Transimpedance Amplifier for BLM-Based Ion Channel Recording.

    Science.gov (United States)

    Crescentini, Marco; Bennati, Marco; Saha, Shimul Chandra; Ivica, Josip; de Planque, Maurits; Morgan, Hywel; Tartagni, Marco

    2016-05-19

    High-throughput screening (HTS) using ion channel recording is a powerful drug discovery technique in pharmacology. Ion channel recording with planar bilayer lipid membranes (BLM) is scalable and has very high sensitivity. A HTS system based on BLM ion channel recording faces three main challenges: (i) design of scalable microfluidic devices; (ii) design of compact ultra-low-noise transimpedance amplifiers able to detect currents in the pA range with bandwidth >10 kHz; (iii) design of compact, robust and scalable systems that integrate these two elements. This paper presents a low-noise transimpedance amplifier with integrated A/D conversion realized in CMOS 0.35 μm technology. The CMOS amplifier acquires currents in the range ±200 pA and ±20 nA, with 100 kHz bandwidth while dissipating 41 mW. An integrated digital offset compensation loop balances any voltage offsets from Ag/AgCl electrodes. The measured open-input input-referred noise current is as low as 4 fA/√Hz at ±200 pA range. The current amplifier is embedded in an integrated platform, together with a microfluidic device, for current recording from ion channels. Gramicidin-A, α-haemolysin and KcsA potassium channels have been used to prove both the platform and the current-to-digital converter.

  15. A CURRENT MIRROR BASED TWO STAGE CMOS CASCODE OP-AMP FOR HIGH FREQUENCY APPLICATION

    Directory of Open Access Journals (Sweden)

    RAMKRISHNA KUNDU

    2017-03-01

    Full Text Available This paper presents a low power, high slew rate, high gain, ultra wide band two stage CMOS cascode operational amplifier for radio frequency application. Current mirror based cascoding technique and pole zero cancelation technique is used to ameliorate the gain and enhance the unity gain bandwidth respectively, which is the novelty of the circuit. In cascading technique a common source transistor drive a common gate transistor. The cascoding is used to enhance the output resistance and hence improve the overall gain of the operational amplifier with less complexity and less power dissipation. To bias the common gate transistor, a current mirror is used in this paper. The proposed circuit is designed and simulated using Cadence analog and digital system design tools of 45 nanometer CMOS technology. The simulated results of the circuit show DC gain of 63.62 dB, unity gain bandwidth of 2.70 GHz, slew rate of 1816 V/µs, phase margin of 59.53º, power supply of the proposed operational amplifier is 1.4 V (rail-to-rail ±700 mV, and power consumption is 0.71 mW. This circuit specification has encountered the requirements of radio frequency application.

  16. A digitally assisted, signal folding neural recording amplifier.

    Science.gov (United States)

    Chen, Yi; Basu, Arindam; Liu, Lei; Zou, Xiaodan; Rajkumar, Ramamoorthy; Dawe, Gavin Stewart; Je, Minkyu

    2014-08-01

    A novel signal folding and reconstruction scheme for neural recording applications that exploits the 1/f(n) characteristics of neural signals is described in this paper. The amplified output is 'folded' into a predefined range of voltages by using comparison and reset circuits along with the core amplifier. After this output signal is digitized and transmitted, a reconstruction algorithm can be applied in the digital domain to recover the amplified signal from the folded waveform. This scheme enables the use of an analog-to-digital convertor with less number of bits for the same effective dynamic range. It also reduces the transmission data rate of the recording chip. Both of these features allow power and area savings at the system level. Other advantages of the proposed topology are increased reliability due to the removal of pseudo-resistors, lower harmonic distortion and low-voltage operation. An analysis of the reconstruction error introduced by this scheme is presented along with a behavioral model to provide a quick estimate of the post reconstruction dynamic range. Measurement results from two different core amplifier designs in 65 nm and 180 nm CMOS processes are presented to prove the generality of the proposed scheme in the neural recording applications. Operating from a 1 V power supply, the amplifier in 180 nm CMOS has a gain of 54.2 dB, bandwidth of 5.7 kHz, input referred noise of 3.8 μVrms and power dissipation of 2.52 μW leading to a NEF of 3.1 in spike band. It exhibits a dynamic range of 66 dB and maximum SNDR of 43 dB in LFP band. It also reduces system level power (by reducing the number of bits in the ADC by 2) as well as data rate to 80% of a conventional design. In vivo measurements validate the ability of this amplifier to simultaneously record spike and LFP signals.

  17. Design and analysis of high gain and low noise figure CMOS low noise amplifier for Q-band nano-sensor application

    Science.gov (United States)

    Suganthi, K.; Malarvizhi, S.

    2018-03-01

    A high gain, low power, low Noise figure (NF) and wide band of milli-meter Wave (mmW) circuits design at 50 GHz are used for Radio Frequency (RF) front end. The fundamental necessity of a receiver front-end includes perfect output and input impedance matching and port-to-port isolation with high gain and low noise over the entire band of interest. In this paper, a design of Cascade-Cascode CMOS LNA circuit at 50 GHz for Q-band application is proposed. The design of Low noise amplifier at 50 GHz using Agilent ADS tool with microstrip lines which provides simplicity in fabrication and less chip area. The low off-leakage current Ioff can be maintained with high K-dielectrics CMOS structure. Nano-scale electronics can be achieved with increased robustness. The design has overall gain of 11.091 dB and noise figure of 2.673 dB for the Q-band of 48.3 GHz to 51.3 GHz. Impedance matching is done by T matching network and the obtained input and output reflection coefficients are S11 = <-10 dB and S22 = <-10 dB. Compared to Silicon (Si) material, Wide Band Gap semiconductor materials used attains higher junction temperatures which is well matched to ceramics used in packaging technology, the protection and reliability also can be achieved with the electronic packaging. The reverse transmission coefficient S21 is less than -21 dB has shown that LNA has better isolation between input and output, Stability factor greater than 1 and Power is also optimized in this design. Layout is designed, power gain of 4.6 dB is achieved and area is optimized which is nearly equal to 502 740 μm2. The observed results show that the proposed Cascade-Cascode LNA design can find its suitability in future milli-meter Wave Radar application.

  18. A 65nm CMOS low-power MedRadio-band integer-N cascaded phase-locked loop for implantable medical systems.

    Science.gov (United States)

    Wang, Yi-Xiao; Chen, Wei-Ming; Wu, Chung-Yu

    2014-01-01

    This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 μW in the first PLL and 195 μW in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.

  19. A CMOS integrated pulse mode alpha-particle counter for application in radon monitoring

    International Nuclear Information System (INIS)

    Ahmed, A.; Walkey, D.J.; Tarr, N.G.

    1997-01-01

    A custom integrated circuit for detecting alpha particles for application in the monitoring of radon has been designed and tested. The design uses the reverse-biased well to a substrate capacitance of a p-n junction in a conventional CMOS process as a sense capacitor for incident alpha particles. A simple CMOS inverter is used as an analog amplifier to detect the small potential change induced by an alpha-particle strike on the sense capacitor. The design was implemented in a 1.2-microm conventional CMOS process with a sense capacitor area of 110 microm 2 . Tests carried out under vacuum conditions using a calibrated 241 Am alpha-particle source showed an output voltage swing of ≥2.0 V for an alpha event. The detector is also shown to have good immunity to noise and high-quantum efficiency for alpha particles

  20. CMOS image sensor with contour enhancement

    Science.gov (United States)

    Meng, Liya; Lai, Xiaofeng; Chen, Kun; Yuan, Xianghui

    2010-10-01

    Imitating the signal acquisition and processing of vertebrate retina, a CMOS image sensor with bionic pre-processing circuit is designed. Integration of signal-process circuit on-chip can reduce the requirement of bandwidth and precision of the subsequent interface circuit, and simplify the design of the computer-vision system. This signal pre-processing circuit consists of adaptive photoreceptor, spatial filtering resistive network and Op-Amp calculation circuit. The adaptive photoreceptor unit with a dynamic range of approximately 100 dB has a good self-adaptability for the transient changes in light intensity instead of intensity level itself. Spatial low-pass filtering resistive network used to mimic the function of horizontal cell, is composed of the horizontal resistor (HRES) circuit and OTA (Operational Transconductance Amplifier) circuit. HRES circuit, imitating dendrite of the neuron cell, comprises of two series MOS transistors operated in weak inversion region. Appending two diode-connected n-channel transistors to a simple transconductance amplifier forms the OTA Op-Amp circuit, which provides stable bias voltage for the gate of MOS transistors in HRES circuit, while serves as an OTA voltage follower to provide input voltage for the network nodes. The Op-Amp calculation circuit with a simple two-stage Op-Amp achieves the image contour enhancing. By adjusting the bias voltage of the resistive network, the smoothing effect can be tuned to change the effect of image's contour enhancement. Simulations of cell circuit and 16×16 2D circuit array are implemented using CSMC 0.5μm DPTM CMOS process.

  1. CMOS circuits manual

    CERN Document Server

    Marston, R M

    1995-01-01

    CMOS Circuits Manual is a user's guide for CMOS. The book emphasizes the practical aspects of CMOS and provides circuits, tables, and graphs to further relate the fundamentals with the applications. The text first discusses the basic principles and characteristics of the CMOS devices. The succeeding chapters detail the types of CMOS IC, including simple inverter, gate and logic ICs and circuits, and complex counters and decoders. The last chapter presents a miscellaneous collection of two dozen useful CMOS circuits. The book will be useful to researchers and professionals who employ CMOS circu

  2. A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

    International Nuclear Information System (INIS)

    Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

    2012-01-01

    A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

  3. A phase-shift self-oscillating stereo class-D amplifier for battery-powered applications

    OpenAIRE

    Huffenus , Alexandre; Pillonnet , Gaël; Abouchi , Nacer; Goutti , Frédéric; Rabary , Vincent; Specq , Cécile

    2010-01-01

    International audience; This paper presents a highly efficient stereo audio amplifier, based on a self-oscillating modulator. This modulation scheme has been analyzed and shows to have a higher bandwidth and error correction than standard Pulse Width Modulation (PWM). A practical implementation in CMOS 0.25um technology has been done to validate our theoretical and simulation results. Our amplifier demonstrated a Total Harmonic Distortion plus Noise (THD+N) as low as 0.07%, current consumptio...

  4. Nanosecond-laser induced crosstalk of CMOS image sensor

    Science.gov (United States)

    Zhu, Rongzhen; Wang, Yanbin; Chen, Qianrong; Zhou, Xuanfeng; Ren, Guangsen; Cui, Longfei; Li, Hua; Hao, Daoliang

    2018-02-01

    The CMOS Image Sensor (CIS) is photoelectricity image device which focused the photosensitive array, amplifier, A/D transfer, storage, DSP, computer interface circuit on the same silicon substrate[1]. It has low power consumption, high integration,low cost etc. With large scale integrated circuit technology progress, the noise suppression level of CIS is enhanced unceasingly, and its image quality is getting better and better. It has been in the security monitoring, biometrice, detection and imaging and even military reconnaissance and other field is widely used. CIS is easily disturbed and damaged while it is irradiated by laser. It is of great significance to study the effect of laser irradiation on optoelectronic countermeasure and device for the laser strengthening resistance is of great significance. There are some researchers have studied the laser induced disturbed and damaged of CIS. They focused on the saturation, supersaturated effects, and they observed different effects as for unsaturation, saturation, supersaturated, allsaturated and pixel flip etc. This paper research 1064nm laser interference effect in a typical before type CMOS, and observring the saturated crosstalk and half the crosstalk line. This paper extracted from cmos devices working principle and signal detection methods such as the Angle of the formation mechanism of the crosstalk line phenomenon are analyzed.

  5. Time Difference Amplifier with Robust Gain Using Closed-Loop Control

    Science.gov (United States)

    Nakura, Toru; Mandai, Shingo; Ikeda, Makoto; Asada, Kunihiro

    This paper presents a Time Difference Amplifier (TDA) that amplifies the input time difference into the output time difference. Cross coupled chains of variable delay cells with the same number of stages are applicable for TDA, and the gain is adjusted via the closed-loop control. The TDA was fabricated using 65nm CMOS and the measurement results show that the time difference gain is 4.78 at a nominal power supply while the designed gain is 4.0. The gain is stable enough to be less than 1.4% gain shift under ±10% power supply voltage fluctuation.

  6. A novel power amplifier structure for RFID tag applications

    International Nuclear Information System (INIS)

    Deng Jianbao; Zhang Shilin; Li De; Zhang Yanzheng; Mao Luhong; Xie Sheng

    2011-01-01

    A novel matching method between the power amplifier (PA) and antenna of an active or semi-active RFID tag is presented. A PCB dipole antenna is used as the resonance inductor of a differential power amplifier. The total PA chip area is reduced greatly to only 240 × 70 μm 2 in a 0.18 μm CMOS process due to saving two on-chip integrated inductors. Operating in class AB with a 1.8 V supply voltage and 2.45 GHz input signal, the PA shows a measured output power of 8 dBm at the 1 dB compression point. (semiconductor integrated circuits)

  7. The Biolink Implantable Telemetry System

    Science.gov (United States)

    Betancourt-Zamora, Rafael J.

    1999-01-01

    Most biotelemetry applications deal with the moderated data rates of biological signals. Few people have studied the problem of transcutaneous data transmission at the rates required by NASA's Life Sciences-Advanced BioTelemetry System (LS-ABTS). Implanted telemetry eliminate the problems associated with wire breaking the skin, and permits experiments with awake and unrestrained subjects. Our goal is to build a low-power 174-216MHz Radio Frequency (RF) transmitter suitable for short range biosensor and implantable use. The BioLink Implantable Telemetry System (BITS) is composed of three major units: an Analog Data Module (ADM), a Telemetry Transmitter Module (TTM), and a Command Receiver Module (CRM). BioLink incorporates novel low-power techniques to implement a monolithic digital RF transmitter operating at 100kbps, using quadrature phase shift keying (QPSK) modulation in the 174-216MHz ISM band. As the ADM will be specific for each application, we focused on solving the problems associated with a monolithic implementation of the TTM and CRM, and this is the emphasis of this report. A system architecture based on a Frequency-Locked Loop (FLL) Frequency Synthesizer is presented, and a novel differential frequency that eliminates the need for a frequency divider is also shown. A self sizing phase modulation scheme suitable for low power implementation was also developed. A full system-level simulation of the FLL was performed and loop filter parameters were determined. The implantable antenna has been designed, simulated and constructed. An implant package compatible with the ABTS requirements is also being proposed. Extensive work performed at 200MHz in 0.5um complementary metal oxide semiconductors (CMOS) showed the feasibility of integrating the RF transmitter circuits in a single chip. The Hajimiri phase noise model was used to optimize the Voltage Controlled Oscillator (VCO) for minimum power consumption. Two test chips were fabricated in a 0.5pm, 3V CMOS

  8. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng, E-mail: xxd@tju.edu.c [School of Electronic Information Engineering, Tianjin University, Tianjin 300072 (China)

    2009-12-15

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 {mu}m EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10{sup -9}. The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  9. A 1.5 Gb/s monolithically integrated optical receiver in the standard CMOS process

    International Nuclear Information System (INIS)

    Xiao Xindong; Mao Luhong; Yu Changliang; Zhang Shilin; Xie Sheng

    2009-01-01

    A monolithically integrated optical receiver, including the photodetector, has been realized in Chartered 0.35 μm EEPROM CMOS technology for 850 nm optical communication. The optical receiver consists of a differential photodetector, a differential transimpedance amplifier, three limiting amplifiers and an output circuit. The experiment results show that the receiver achieves an 875 MHz 3 dB bandwidth, and a data rate of 1.5 Gb/s is achieved at a bit-error-rate of 10 -9 . The chip dissipates 60 mW under a single 3.3 V supply. (semiconductor integrated circuits)

  10. Determination of the excess noise of avalanche photodiodes integrated in 0.35-μm CMOS technologies

    Science.gov (United States)

    Jukić, Tomislav; Brandl, Paul; Zimmermann, Horst

    2018-04-01

    The excess noise of avalanche photodiodes (APDs) integrated in a high-voltage (HV) CMOS process and in a pin-photodiode CMOS process, both with 0.35-μm structure sizes, is described. A precise excess noise measurement technique is applied using a laser source, a spectrum analyzer, a voltage source, a current meter, a cheap transimpedance amplifier, and a personal computer with a MATLAB program. In addition, usage for on-wafer measurements is demonstrated. The measurement technique is verified with a low excess noise APD as a reference device with known ratio k = 0.01 of the impact ionization coefficients. The k-factor of an APD developed in HV CMOS is determined more accurately than known before. In addition, it is shown that the excess noise of the pin-photodiode CMOS APD depends on the optical power for avalanche gains above 35 and that modulation doping can suppress this power dependence. Modulation doping, however, increases the excess noise.

  11. Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Yu Junting; Li Binqiao; Yu Pingping; Xu Jiangtao [School of Electronics Information Engineering, Tianjin University, Tianjin 300072 (China); Mou Cun, E-mail: xujiangtao@tju.edu.c [Logistics Management Office, Hebei University of Technology, Tianjin 300130 (China)

    2010-09-15

    Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 x 10{sup 12} cm{sup -2}, an implant tilt of -2{sup 0}, a transfer gate channel doping dose of 3.0 x 10{sup 12} cm{sup -2} and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors. (semiconductor devices)

  12. Effect of dose and size on defect engineering in carbon cluster implanted silicon wafers

    Science.gov (United States)

    Okuyama, Ryosuke; Masada, Ayumi; Shigematsu, Satoshi; Kadono, Takeshi; Hirose, Ryo; Koga, Yoshihiro; Okuda, Hidehiko; Kurita, Kazunari

    2018-01-01

    Carbon-cluster-ion-implanted defects were investigated by high-resolution cross-sectional transmission electron microscopy toward achieving high-performance CMOS image sensors. We revealed that implantation damage formation in the silicon wafer bulk significantly differs between carbon-cluster and monomer ions after implantation. After epitaxial growth, small and large defects were observed in the implanted region of carbon clusters. The electron diffraction pattern of both small and large defects exhibits that from bulk crystalline silicon in the implanted region. On the one hand, we assumed that the silicon carbide structure was not formed in the implanted region, and small defects formed because of the complex of carbon and interstitial silicon. On the other hand, large defects were hypothesized to originate from the recrystallization of the amorphous layer formed by high-dose carbon-cluster implantation. These defects are considered to contribute to the powerful gettering capability required for high-performance CMOS image sensors.

  13. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    NARCIS (Netherlands)

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In

  14. Recent advances in ion implantation. A state of the art review

    International Nuclear Information System (INIS)

    Stone, J.L.; Plunkett, J.C.

    1976-01-01

    The latest advances in ion implantation related to MOS, CMOS, CCDS, I 2 L, and other semiconductor devices are discussed. In addition, the application of ion implantation to superconductivity, integrated optics, compound semiconductors, and magnetic bubbles is considered. The requirements of ion implantation machine technology to fulfill the needs of the production environment are also reviewed. 75 refs

  15. RAPD analysis of alfalfa DNA mutation via N+ implantation

    International Nuclear Information System (INIS)

    Li Yufeng; Huang Qunce; Yu Zengliang; Liang Yunzhang

    2003-01-01

    Germination capacity of alfalfa seeds under low energy N + implantation manifests oscillations going down with dose strength. From analyzing alfalfa genome DNA under low energy N + implantation by RAPD (Random Amplified Polymorphous DNA), it is recommended that 30 polymorphic DNA fragments be amplified with 8 primers in total 100 primers, and fluorescence intensity of the identical DNA fragment amplified by RAPD is different between CK and treatments. Number of different polymorphic DNA fragments between treatment and CK via N + implantation manifests going up with dose strength

  16. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-11-15

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode show better performance compared to n{sup -}well/p{sup -}sub and n{sup -}well/p{sup -}epi/p{sup -}sub due to the wider depletion width. Comparing n{sup +}/p{sup -}sub and n{sup +}/p{sup -}epi/p{sup -}sub photodiode, n{sup +}/p{sup -}sub has higher photo-responsivity in longer wavelength because of

  17. Photoresponse analysis of the CMOS photodiodes for CMOS x-ray image sensor

    International Nuclear Information System (INIS)

    Kim, Young Soo; Ha, Jang Ho; Kim, Han Soo; Yeo, Sun Mok

    2012-01-01

    Although in the short term CMOS active pixel sensors (APSs) cannot compete with the conventionally used charge coupled devices (CCDs) for high quality scientific imaging, recent development in CMOS APSs indicate that CMOS performance level of CCDs in several domains. CMOS APSs possess thereby a number of advantages such as simpler driving requirements and low power operation. CMOS image sensors can be processed in standard CMOS technologies and the potential of on-chip integration of analog and digital circuitry makes them more suitable for several vision systems where system cost is of importance. Moreover, CMOS imagers can directly benefit from on-going technological progress in the field of CMOS technologies. Due to these advantages, the CMOS APSs are currently being investigated actively for various applications such as star tracker, navigation camera and X-ray imaging etc. In most detection systems, it is thought that the sensor is most important, since this decides the signal and noise level. So, in CMOS APSs, the pixel is very important compared to other functional blocks. In order to predict the performance of such image sensor, a detailed understanding of the photocurrent generation in the photodiodes that comprise the CMOS APS is required. In this work, we developed the analytical model that can calculate the photocurrent generated in CMOS photodiode comprising CMOS APSs. The photocurrent calculations and photo response simulations with respect to the wavelength of the incident photon were performed using this model for four types of photodiodes that can be fabricated in standard CMOS process. n + /p - sub and n + /p - epi/p - sub photodiode show better performance compared to n - well/p - sub and n - well/p - epi/p - sub due to the wider depletion width. Comparing n + /p - sub and n + /p - epi/p - sub photodiode, n + /p - sub has higher photo-responsivity in longer wavelength because of the higher electron diffusion current

  18. Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

    Science.gov (United States)

    Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

    2018-05-01

    Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

  19. High Performance Microaccelerometer with Wafer-level Hermetic Packaged Sensing Element and Continuous-time BiCMOS Interface Circuit

    International Nuclear Information System (INIS)

    Ko, Hyoungho; Park, Sangjun; Paik, Seung-Joon; Choi, Byoung-doo; Park, Yonghwa; Lee, Sangmin; Kim, Sungwook; Lee, Sang Chul; Lee, Ahra; Yoo, Kwangho; Lim, Jaesang; Cho, Dong-il

    2006-01-01

    A microaccelerometer with highly reliable, wafer-level packaged MEMS sensing element and fully differential, continuous time, low noise, BiCMOS interface circuit is fabricated. The MEMS sensing element is fabricated on a (111)-oriented SOI wafer by using the SBM (Sacrificial/Bulk Micromachining) process. To protect the silicon structure of the sensing element and enhance the reliability, a wafer level hermetic packaging process is performed by using a silicon-glass anodic bonding process. The interface circuit is fabricated using 0.8 μm BiCMOS process. The capacitance change of the MEMS sensing element is amplified by the continuous-time, fully-differential transconductance input amplifier. A chopper-stabilization architecture is adopted to reduce low-frequency noise including 1/f noise. The fabricated microaccelerometer has the total noise equivalent acceleration of 0.89 μg/√Hz, the bias instability of 490 μg, the input range of ±10 g, and the output nonlinearity of ±0.5 %FSO

  20. Design of fundamental building blocks for fast binary readout CMOS sensors used in high-energy physics experiments

    Energy Technology Data Exchange (ETDEWEB)

    Degerli, Yavuz [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France)], E-mail: degerli@cea.fr

    2009-04-21

    In this paper, design details of key building blocks for fast binary readout CMOS monolithic active pixel sensors developed for charged particle detection are presented. Firstly, an all-NMOS pixel architecture with in-pixel amplification and reset noise suppression which allows fast readout is presented. This pixel achieves high charge-to-voltage conversion factors (CVF) using a few number of transistors inside the pixel. It uses a pre-amplifying stage close to the detector and a simple double sampling (DS) circuitry to store the reset level of the detector. The DS removes the offset mismatches of amplifiers and the reset noise of the detector. Offset mismatches of the source follower are also corrected by a second column-level DS stage. The second important building block of these sensors, a low-power auto-zeroed column-level discriminator, is also presented. These two blocks transform the charge of the impinging particle into binary data. Finally, some experimental results obtained on CMOS chips designed using these blocks are presented.

  1. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  2. A low-offset low-voltage CMOS Op Amp with rail-to-rail input and output ranges

    NARCIS (Netherlands)

    Holzmann, Peter J.; Wiegerink, Remco J.; Gierkink, Sander L.J.; Wassenaar, R.F.; Stroet, Peter; Stroet, P.M.

    1996-01-01

    A low voltage CMOS op amp is presented. The circuit uses complementary input pairs to achieve a rail-to-rail common mode input voltage range. Special attention has been given to the reduction of the op amp's systematic offset voltage. Gain boost amplifiers are connected in a special way to provide

  3. A CMOS integrated timing discriminator circuit for fast scintillation counters

    International Nuclear Information System (INIS)

    Jochmann, M.W.

    1998-01-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

  4. CMOS VLSI Active-Pixel Sensor for Tracking

    Science.gov (United States)

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  5. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  6. Integrating amplifiers for PHENIX lead-glass and lead-scintillator calorimeters

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Simpson, M.L.; Britton, C.L. Jr.; Palmer, R.L.; Jackson, R.G.

    1995-01-01

    Two types of integrating amplifier systems have been developed for use with lead-glass and lead-scintillator calorimeters with photomultiplier tube readout. Requirements for the amplifier system include termination of the line from the photomultiplier, compact size and low power dissipation to allow multiple channels per chip, dual range outputs producing 10-bit accuracy over a 14-bit dynamic range, rms noise levels of one LSB or less, and compatibility with timing filter amplifiers, tower sum circuits for triggering and calibration circuits to be built on the same integrated circuit (IC). Advantages and disadvantages of an active integrator system are compared and contrasted to those of a passive integrator-based system. In addition, details of the designs and results from prototype devices including an 8-channel active integrator IC fabricated in 1.2 microm Orbit CMOS are presented

  7. A digital input class-D audio amplifier with sixth-order PWM

    International Nuclear Information System (INIS)

    Luo Shumeng; Li Dongmei

    2013-01-01

    A digital input class-D audio amplifier with a sixth-order pulse-width modulation (PWM) modulator is presented. This modulator moves the PWM generator into the closed sigma—delta modulator loop. The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma—delta modulator. Therefore, at the output of the modulator, a very clean PWM signal is acquired for driving the power stage of the class-D amplifier. A sixth-order modulator is designed to balance the performance and the system clock speed. Fabricated in standard 0.18 μm CMOS technology, this class-D amplifier achieves 110 dB dynamic range, 100 dB signal-to-noise rate, and 0.0056% total harmonic distortion plus noise. (semiconductor integrated circuits)

  8. A 240W Monolithic Class-D Audio Amplifier Output Stage

    OpenAIRE

    Nyboe, Flemming; Kaya, Cetin; Risbo, Lars; Andreani, Pietro

    2006-01-01

    A single-channel class-D audio amplifier output stage outputs 240W undipped into 4Omega 0.1% open-loop THD+N allows using the device in a fully-digital audio signal path with no feedback. The output current capability is plusmn18A and the part is fabricated in a 0.4mum/1.8mum high-voltage BiCMOS process. Over-current sensing protects the output from short circuits.

  9. An audio FIR-DAC in a BCD process for high power Class-D amplifiers

    NARCIS (Netherlands)

    Doorn, T.S.; van Tuijl, Adrianus Johannes Maria; Schinkel, Daniel; Annema, Anne J.; Berkhout, M.; Berkhout, M.; Nauta, Bram

    A 322 coefficient semi-digital FIR-DAC using a 1-bit PWM input signal was designed and implemented in a high voltage, audio power bipolar CMOS DMOS (BCD) process. This facilitates digital input signals for an analog class-D amplifier in BCD. The FIR-DAC performance depends on the ISI-resistant

  10. Modulation Techniques for Biomedical Implanted Devices and Their Challenges

    Directory of Open Access Journals (Sweden)

    Salina A. Samad

    2011-12-01

    Full Text Available Implanted medical devices are very important electronic devices because of their usefulness in monitoring and diagnosis, safety and comfort for patients. Since 1950s, remarkable efforts have been undertaken for the development of bio-medical implanted and wireless telemetry bio-devices. Issues such as design of suitable modulation methods, use of power and monitoring devices, transfer energy from external to internal parts with high efficiency and high data rates and low power consumption all play an important role in the development of implantable devices. This paper provides a comprehensive survey on various modulation and demodulation techniques such as amplitude shift keying (ASK, frequency shift keying (FSK and phase shift keying (PSK of the existing wireless implanted devices. The details of specifications, including carrier frequency, CMOS size, data rate, power consumption and supply, chip area and application of the various modulation schemes of the implanted devices are investigated and summarized in the tables along with the corresponding key references. Current challenges and problems of the typical modulation applications of these technologies are illustrated with a brief suggestions and discussion for the progress of implanted device research in the future. It is observed that the prime requisites for the good quality of the implanted devices and their reliability are the energy transformation, data rate, CMOS size, power consumption and operation frequency. This review will hopefully lead to increasing efforts towards the development of low powered, high efficient, high data rate and reliable implanted devices.

  11. Free form CMOS electronics: Physically flexible and stretchable

    KAUST Repository

    Hussain, Muhammad Mustafa

    2015-12-07

    Free form (physically flexible and stretchable) electronics can be used for applications which are unexplored today due to the rigid and brittle nature of the state-of-the-art electronics. Therefore, we show integration strategy to rationally design materials, processes and devices to transform advanced complementary metal oxide semiconductor (CMOS) electronics into flexible and stretchable one while retaining their high performance, energy efficiency, ultra-large-scale-integration (ULSI) density, reliability and performance over cost benefit to expand its applications for wearable, implantable and Internet-of-Everything electronics.

  12. A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    Science.gov (United States)

    Nan, Liu; Guoping, Chen; Zhiliang, Hong

    2009-01-01

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm2 and consumes 37 mW.

  13. A 0.18 μm CMOS fluorescent detector system for bio-sensing application

    International Nuclear Information System (INIS)

    Liu Nan; Chen Guoping; Hong Zhiliang

    2009-01-01

    A CMOS fluorescent detector system for biological experiment is presented. This system integrates a CMOS compatible photodiode, a capacitive trans-impedance amplifier (CTIA), and a 12 bit pipelined analog-to-digital converter (ADC), and is implemented in a 0.18 μm standard CMOS process. Some special techniques, such as a 'contact imaging' detecting method, pseudo-differential architecture, dummy photodiodes, and a T-type reset switch, are adopted to achieve low-level sensing application. Experiment results show that the Nwell/Psub photodiode with CTIA pixel achieves a sensitivity of 0.1 A/W at 515 nm and a dark current of 300 fA with 300 mV reverse biased voltage. The maximum differential and integral nonlinearity of the designed ADC are 0.8 LSB and 3 LSB, respectively. With an integrating time of 50 ms, this system is sensitive to the fluorescence emitted by the fluorescein solution with concentration as low as 20 ng/mL and can generate 7 fA photocurrent. This chip occupies 3 mm 2 and consumes 37 mW.

  14. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    OpenAIRE

    Diwei He; Stephen P. Morgan; Dimitrios Trachanis; Jan van Hese; Dimitris Drogoudis; Franco Fummi; Francesco Stefanni; Valerio Guarnieri; Barrie R. Hayes-Gill

    2015-01-01

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 ?m CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the...

  15. A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor

    Science.gov (United States)

    2015-07-21

    Hybrid Biosensor Jieun Lee1,2, Jaeman Jang1, Bongsik Choi1, Jinsu Yoon1, Jee-Yeon Kim3, Yang-Kyu Choi3, Dong Myong Kim1, Dae Hwan Kim1 & Sung-Jin Choi1...This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response...of field-effect-transistor (FET)-based biosensors . The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential

  16. Linearization and efficiency enhancement techniques for silicon power amplifiers from RF to mmW

    CERN Document Server

    Kerhervé, Eric

    2015-01-01

    This book provides an overview of current efficiency enhancement and linearization techniques for silicon power amplifier designs. It examines the latest state of the art technologies and design techniques to address challenges for RF cellular mobile, base stations, and RF and mmW WLAN applications. Coverage includes material on current silicon (CMOS, SiGe) RF and mmW power amplifier designs, focusing on advantages and disadvantages compared with traditional GaAs implementations. With this book you will learn: The principles of linearization and efficiency improvement techniquesThe arch

  17. Continuously Operating Biosensor and Its Integration into a Hermetically Sealed Medical Implant

    Directory of Open Access Journals (Sweden)

    Mario Birkholz

    2016-10-01

    Full Text Available An integration concept for an implantable biosensor for the continuous monitoring of blood sugar levels is presented. The system architecture is based on technical modules used in cardiovascular implants in order to minimize legal certification efforts for its perspective usage in medical applications. The sensor chip operates via the principle of affinity viscometry, which is realized by a fully embedded biomedical microelectromechanical systems (BioMEMS prepared in 0.25-µm complementary metal–oxide–semiconductor (CMOS/BiCMOS technology. Communication with a base station is established in the 402–405 MHz band used for medical implant communication services (MICS. The implant shall operate within the interstitial tissue, and the hermetical sealing of the electronic system against interaction with the body fluid is established using titanium housing. Only the sensor chip and the antenna are encapsulated in an epoxy header closely connected to the metallic housing. The study demonstrates that biosensor implants for the sensing of low-molecular-weight metabolites in the interstitial may successfully rely on components already established in cardiovascular implantology.

  18. Prolonged Corrosion Stability of a Microchip Sensor Implant during In Vivo Exposure

    Directory of Open Access Journals (Sweden)

    Paul Glogener

    2018-02-01

    Full Text Available A microelectronic biosensor was subjected to in vivo exposure by implanting it in the vicinity of m. trapezii (Trapezius muscle from cattle. The implant is intended for the continuous monitoring of glucose levels, and the study aimed at evaluating the biostability of exposed semiconductor surfaces. The sensor chip was a microelectromechanical system (MEMS prepared using 0.25 µm complementary metal–oxide–semiconductor CMOS/BiCMOS technology. Sensing is based on the principle of affinity viscometry with a sensoric assay, which is separated by a semipermeable membrane from the tissue. Outer dimensions of the otherwise hermetically sealed biosensor system were 39 × 49 × 16 mm. The test system was implanted into cattle in a subcutaneous position without running it. After 17 months, the device was explanted and analyzed by comparing it with unexposed chips and systems. Investigations focused on the MEMS chip using SEM, TEM, and elemental analysis by EDX mapping. The sensor chip turned out to be uncorroded and no diminishing of the topmost passivation layer could be determined, which contrasts remarkably with previous results on CMOS biosensors. The negligible corrosive attack is understood to be a side effect of the semipermeable membrane separating the assay from the tissue. It is concluded that the separation has enabled a prolonged biostability of the chip, which will be of relevance for biosensor implants in general.

  19. Evaluation of stabilization techniques for ion implant processing

    Science.gov (United States)

    Ross, Matthew F.; Wong, Selmer S.; Minter, Jason P.; Marlowe, Trey; Narcy, Mark E.; Livesay, William R.

    1999-06-01

    With the integration of high current ion implant processing into volume CMOS manufacturing, the need for photoresist stabilization to achieve a stable ion implant process is critical. This study compares electron beam stabilization, a non-thermal process, with more traditional thermal stabilization techniques such as hot plate baking and vacuum oven processing. The electron beam processing is carried out in a flood exposure system with no active heating of the wafer. These stabilization techniques are applied to typical ion implant processes that might be found in a CMOS production process flow. The stabilization processes are applied to a 1.1 micrometers thick PFI-38A i-line photoresist film prior to ion implant processing. Post stabilization CD variation is detailed with respect to wall slope and feature integrity. SEM photographs detail the effects of the stabilization technique on photoresist features. The thermal stability of the photoresist is shown for different levels of stabilization and post stabilization thermal cycling. Thermal flow stability of the photoresist is detailed via SEM photographs. A significant improvement in thermal stability is achieved with the electron beam process, such that photoresist features are stable to temperatures in excess of 200 degrees C. Ion implant processing parameters are evaluated and compared for the different stabilization methods. Ion implant system end-station chamber pressure is detailed as a function of ion implant process and stabilization condition. The ion implant process conditions are detailed for varying factors such as ion current, energy, and total dose. A reduction in the ion implant systems end-station chamber pressure is achieved with the electron beam stabilization process over the other techniques considered. This reduction in end-station chamber pressure is shown to provide a reduction in total process time for a given ion implant dose. Improvements in the ion implant process are detailed across

  20. Sensitivity Enhancement of a Vertical-Type CMOS Hall Device for a Magnetic Sensor

    Directory of Open Access Journals (Sweden)

    Sein Oh

    2018-01-01

    Full Text Available This study presents a vertical-type CMOS Hall device with improved sensitivity to detect a 3D magnetic field in various types of sensors or communication devices. To improve sensitivity, trenches are implanted next to the current input terminal, so that the Hall current becomes maximum. The effect of the dimension and location of trenches on sensitivity is simulated in the COMSOL simulator. A vertical-type Hall device with a width of 16 μm and a height of 2 μm is optimized for maximum sensitivity. The simulation result shows that it has a 23% better result than a conventional vertical-type CMOS Hall device without a trench.

  1. First generation of deep n-well CMOS MAPS with in-pixel sparsification for the ILC vertex detector

    International Nuclear Information System (INIS)

    Traversi, Gianluca; Bulgheroni, Antonio; Caccia, Massimo; Jastrzab, Marcin; Manghisoni, Massimo; Pozzati, Enrico; Ratti, Lodovico; Re, Valerio

    2009-01-01

    In this paper we present the characterization results relevant to a deep n-well (DNW) CMOS active pixel sensor chip designed for vertexing applications at the International Linear Collider. In this chip, named sparsified digital readout (SDR0), for the first time we implemented a sparsification logic at the pixel level. The DNW available in deep submicron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. In this work, the experimental characterization of the SDR0 chip, including data from radioactive source ( 55 Fe) tests, will be presented.

  2. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling

    OpenAIRE

    Bruccoleri, F.; Klumperink, Eric A.M.; Nauta, Bram

    2004-01-01

    Known elementary wide-band amplifiers suffer from a fundamental tradeoff between noise figure (NF) and source impedance matching, which limits the NF to values typically above 3 dB. Global negative feedback can be used to break this tradeoff, however, at the price of potential instability. In contrast, this paper presents a feedforward noise-canceling technique, which allows for simultaneous noise and impedance matching, while canceling the noise and distortion contributions of the matching d...

  3. Study of drain-extended NMOS under electrostatic discharge stress in 28 nm and 40 nm CMOS process

    Science.gov (United States)

    Wang, Weihuai; Jin, Hao; Dong, Shurong; Zhong, Lei; Han, Yan

    2016-02-01

    Researches on the electrostatic discharge (ESD) performance of drain-extended NMOS (DeNMOS) under the state-of-the-art 28 nm and 40 nm bulk CMOS process are performed in this paper. Three distinguishing phases of avalanche breakdown stage, depletion region push-out stage and parasitic NPN turn on stage of the gate-grounded DeNMOS (GG-DeNMOS) fabricated under 28 nm CMOS process measured with transmission line pulsing (TLP) test are analyzed through TCAD simulations and tape-out silicon verification detailedly. Damage mechanisms and failure spots of GG-DeNMOS under both CMOS processes are thermal breakdown of drain junction. Improvements based on the basic structure adjustments can increase the GG-DeNMOS robustness from original 2.87 mA/μm to the highest 5.41 mA/μm. Under 40 nm process, parameter adjustments based on the basic structure have no significant benefits on the robustness improvements. By inserting P+ segments in the N+ implantation of drain or an entire P+ strip between the N+ implantation of drain and polysilicon gate to form the typical DeMOS-SCR (silicon-controlled rectifier) structure, the ESD robustness can be enhanced from 1.83 mA/μm to 8.79 mA/μm and 29.78 mA/μm, respectively.

  4. Integrated VCOs for Medical Implant Transceivers

    Directory of Open Access Journals (Sweden)

    Ahmet Tekin

    2008-01-01

    Full Text Available The 402–405 MHz medical implant communication service (MICS band has recently been allocated by the US Federal Communication Commission (FCC with the potential to replace the low-frequency inductive coupling techniques in implantable devices. This band was particularly chosen to provide full-integration, low-power, faster data transfer, and longer communication range. This paper investigates the design of a voltage-controlled oscillator (VCO that will be an essential building block of such wireless implantable devices operating in the MICS service band. Three different integrated quadrature VCOs that meet the requirements of the MICS standard are designed in 0.18 μm TSMC CMOS process to propose an optimum choice. Their performances in terms of power consumption, die area, linearity, and phase noise are compared. The fabricated VCOs are a four-stage differential ring VCO, an LC tank VCO directly loaded with a poly-phase filter, and an 800 MHz LC tank VCO with a high-frequency master-slave divider. All three architectures target a VCO gain of Kvco = 15 MHz/V with 3 calibration control and 2 frequency-shift keying (FSK control signals and are designed for 1.5 V supply voltage in a 0.18-μm standard CMOS process.

  5. CMOS single-stage input-powered bridge rectifier with boost switch and duty cycle control

    Science.gov (United States)

    Radzuan, Roskhatijah; Mohd Salleh, Mohd Khairul; Hamzah, Mustafar Kamal; Ab Wahab, Norfishah

    2017-06-01

    This paper presents a single-stage input-powered bridge rectifier with boost switch for wireless-powered devices such as biomedical implants and wireless sensor nodes. Realised using CMOS process technology, it employs a duty cycle switch control to achieve high output voltage using boost technique, leading to a high output power conversion. It has only six external connections with the boost inductance. The input frequency of the bridge rectifier is set at 50 Hz, while the switching frequency is 100 kHz. The proposed circuit is fabricated on a single 0.18-micron CMOS die with a space area of 0.024 mm2. The simulated and measured results show good agreement.

  6. Design and simulation of resistive SOI CMOS micro-heaters for high temperature gas sensors

    International Nuclear Information System (INIS)

    Iwaki, T; Covington, J A; Udrea, F; Ali, S Z; Guha, P K; Gardner, J W

    2005-01-01

    This paper describes the design of doped single crystal silicon (SCS) microhotplates for gas sensors. Resistive heaters are formed by an n+/p+ implantation into a Silicon-On-Insulator (SOI) wafer with a post-CMOS deep reactive ion etch to remove the silicon substrate. Hence they are fully compatible with CMOS technologies and allows for the integration of associated drive/detection circuitry. 2D electro-thermal models have been constructed and the results of numerical simulations using FEMLAB[reg] are given. Simulations show these micro-hotplates can operate at temperatures of 500 deg. C with a drive voltage of only 5 V and a power consumption of less than 100 mW

  7. A High-Linearity Low-Noise Amplifier with Variable Bandwidth for Neural Recoding Systems

    Science.gov (United States)

    Yoshida, Takeshi; Sueishi, Katsuya; Iwata, Atsushi; Matsushita, Kojiro; Hirata, Masayuki; Suzuki, Takafumi

    2011-04-01

    This paper describes a low-noise amplifier with multiple adjustable parameters for neural recording applications. An adjustable pseudo-resistor implemented by cascade metal-oxide-silicon field-effect transistors (MOSFETs) is proposed to achieve low-signal distortion and wide variable bandwidth range. The amplifier has been implemented in 0.18 µm standard complementary metal-oxide-semiconductor (CMOS) process and occupies 0.09 mm2 on chip. The amplifier achieved a selectable voltage gain of 28 and 40 dB, variable bandwidth from 0.04 to 2.6 Hz, total harmonic distortion (THD) of 0.2% with 200 mV output swing, input referred noise of 2.5 µVrms over 0.1-100 Hz and 18.7 µW power consumption at a supply voltage of 1.8 V.

  8. Robust integration schemes for junction-based modulators in a 200mm CMOS compatible silicon photonic platform (Conference Presentation)

    Science.gov (United States)

    Szelag, Bertrand; Abraham, Alexis; Brision, Stéphane; Gindre, Paul; Blampey, Benjamin; Myko, André; Olivier, Segolene; Kopp, Christophe

    2017-05-01

    Silicon photonic is becoming a reality for next generation communication system addressing the increasing needs of HPC (High Performance Computing) systems and datacenters. CMOS compatible photonic platforms are developed in many foundries integrating passive and active devices. The use of existing and qualified microelectronics process guarantees cost efficient and mature photonic technologies. Meanwhile, photonic devices have their own fabrication constraints, not similar to those of cmos devices, which can affect their performances. In this paper, we are addressing the integration of PN junction Mach Zehnder modulator in a 200mm CMOS compatible photonic platform. Implantation based device characteristics are impacted by many process variations among which screening layer thickness, dopant diffusion, implantation mask overlay. CMOS devices are generally quite robust with respect to these processes thanks to dedicated design rules. For photonic devices, the situation is different since, most of the time, doped areas must be carefully located within waveguides and CMOS solutions like self-alignment to the gate cannot be applied. In this work, we present different robust integration solutions for junction-based modulators. A simulation setup has been built in order to optimize of the process conditions. It consist in a Mathlab interface coupling process and device electro-optic simulators in order to run many iterations. Illustrations of modulator characteristic variations with process parameters are done using this simulation setup. Parameters under study are, for instance, X and Y direction lithography shifts, screening oxide and slab thicknesses. A robust process and design approach leading to a pn junction Mach Zehnder modulator insensitive to lithography misalignment is then proposed. Simulation results are compared with experimental datas. Indeed, various modulators have been fabricated with different process conditions and integration schemes. Extensive

  9. Analog CMOS peak detect and hold circuits. Part 2. The two-phase offset-free and derandomizing configuration

    CERN Document Server

    De Geronimo, G; Kandasamy, A

    2002-01-01

    An analog CMOS peak detect and hold (PDH) circuit, which combines high speed and accuracy, rail-to-rail sensing and driving, low power, and buffering is presented. It is based on a configuration that cancels the major error sources of the classical CMOS PDH, including offset and common mode gain, by re-using the same amplifier for tracking, peak sensing, and output buffering. By virtue of its high absolute accuracy, two or more PDHs can be used in parallel to serve as a data-driven analog memory for derandomization. The first experimental results on the new peak detector and derandomizer (PDD) circuit, fabricated in 0.35 mu m CMOS technology, include a 0.2% absolute accuracy for pulses with 500 ns peaking time, 2.7 V linear input range, 3.3 mW power dissipation, 250 mV/s droop rate, and negligible dead time. The use of such a high performance analog PDD can greatly relax the requirements on the digitization in multi-channel systems.

  10. A capacitive CMOS-MEMS sensor designed by multi-physics simulation for integrated CMOS-MEMS technology

    Science.gov (United States)

    Konishi, Toshifumi; Yamane, Daisuke; Matsushima, Takaaki; Masu, Kazuya; Machida, Katsuyuki; Toshiyoshi, Hiroshi

    2014-01-01

    This paper reports the design and evaluation results of a capacitive CMOS-MEMS sensor that consists of the proposed sensor circuit and a capacitive MEMS device implemented on the circuit. To design a capacitive CMOS-MEMS sensor, a multi-physics simulation of the electromechanical behavior of both the MEMS structure and the sensing LSI was carried out simultaneously. In order to verify the validity of the design, we applied the capacitive CMOS-MEMS sensor to a MEMS accelerometer implemented by the post-CMOS process onto a 0.35-µm CMOS circuit. The experimental results of the CMOS-MEMS accelerometer exhibited good agreement with the simulation results within the input acceleration range between 0.5 and 6 G (1 G = 9.8 m/s2), corresponding to the output voltages between 908.6 and 915.4 mV, respectively. Therefore, we have confirmed that our capacitive CMOS-MEMS sensor and the multi-physics simulation will be beneficial method to realize integrated CMOS-MEMS technology.

  11. 5.2 GHz variable-gain amplifier and power amplifier driver for WLAN IEEE 802.11a transmitter front-end

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Xuelian; Yan Jun; Shi Yin [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China); Foster, Dai Fa, E-mail: xlzhang@semi.ac.c [Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849-5201 (United States)

    2009-01-15

    A 5.2 GHz variable-gain amplifier (VGA) and a power amplifier (PA) driver are designed for WLAN IEEE 802.11a monolithic RFIC. The VGA and the PA driver are implemented in a 50 GHz 0.35 mum SiGe BiCMOS technology and occupy 1.12 x 1.25 mm{sup 2} die area. The VGA with effective temperature compensation is controlled by 5 bits and has a gain range of 34 dB. The PA driver with tuned loads utilizes a differential input, single-ended output topology, and the tuned loads resonate at 5.2 GHz. The maximum overall gain of the VGA and the PA driver is 29 dB with the output third-order intercept point (OIP3) of 11 dBm. The gain drift over the temperature varying from -30 to 85 deg. C converges within +-3 dB. The total current consumption is 45 mA under a 2.85 V power supply.

  12. Ultra compact 45 GHz CMOS compatible Germanium waveguide photodiode with low dark current.

    Science.gov (United States)

    DeRose, Christopher T; Trotter, Douglas C; Zortman, William A; Starbuck, Andrew L; Fisher, Moz; Watts, Michael R; Davids, Paul S

    2011-12-05

    We present a compact 1.3 × 4 μm2 Germanium waveguide photodiode, integrated in a CMOS compatible silicon photonics process flow. This photodiode has a best-in-class 3 dB cutoff frequency of 45 GHz, responsivity of 0.8 A/W and dark current of 3 nA. The low intrinsic capacitance of this device may enable the elimination of transimpedance amplifiers in future optical data communication receivers, creating ultra low power consumption optical communications.

  13. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

    Directory of Open Access Journals (Sweden)

    Preethi Padmanabhan

    2018-02-01

    Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  14. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

    Science.gov (United States)

    Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

    2018-02-03

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

  15. System on chip thermal vacuum sensor based on standard CMOS process

    International Nuclear Information System (INIS)

    Li Jinfeng; Tang Zhenan; Wang Jiaqi

    2009-01-01

    An on-chip microelectromechanical system was fabricated in a 0.5 μm standard CMOS process for gas pressure detection. The sensor was based on a micro-hotplate (MHP) and had been integrated with a rail to rail operational amplifier and an 8-bit successive approximation register (SAR) A/D converter. A tungsten resistor was manufactured on the MHP as the sensing element, and the sacrificial layer of the sensor was made from polysilicon and etched by surface-micromachining technology. The operational amplifier was configured to make the sensor operate in constant current mode. A digital bit stream was provided as the system output. The measurement results demonstrate that the gas pressure sensitive range of the vacuum sensor extends from 1 to 10 5 Pa. In the gas pressure range from 1 to 100 Pa, the sensitivity of the sensor is 0.23 mV/ Pa, the linearity is 4.95%, and the hysteresis is 8.69%. The operational amplifier can drive 200 ω resistors distortionlessly, and the SAR A/D converter achieves a resolution of 7.4 bit with 100 kHz sample rate. The performance of the operational amplifier and the SAR A/D converter meets the requirements of the sensor system.

  16. An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator

    Science.gov (United States)

    Paik, Daehwa; Miyahara, Masaya; Matsuzawa, Akira

    This paper analyzes a pseudo-differential dynamic comparator with a dynamic pre-amplifier. The transient gain of a dynamic pre-amplifier is derived and applied to equations of the thermal noise and the regeneration time of a comparator. This analysis enhances understanding of the roles of transistor's parameters in pre-amplifier's gain. Based on the calculated gain, two calibration methods are also analyzed. One is calibration of a load capacitance and the other is calibration of a bypass current. The analysis helps designers' estimation for the accuracy of calibration, dead-zone of a comparator with a calibration circuit, and the influence of PVT variation. The analyzed comparator uses 90-nm CMOS technology as an example and each estimation is compared with simulation results.

  17. A low-power CMOS readout IC design for bolometer applications

    Science.gov (United States)

    Galioglu, Arman; Abbasi, Shahbaz; Shafique, Atia; Ceylan, Ömer; Yazici, Melik; Kaynak, Mehmet; Durmaz, Emre C.; Arsoy, Elif Gul; Gurbuz, Yasar

    2017-02-01

    A prototype of a readout IC (ROIC) designed for use in high temperature coefficient of resistance (TCR) SiGe microbolometers is presented. The prototype ROIC architecture implemented is based on a bridge with active and blind bolometer pixels with a capacitive transimpedance amplifier (CTIA) input stage and column parallel integration with serial readout. The ROIC is designed for use in high (>= 4 %/K) TCR and high detector resistance Si/SiGe microbolometers with 17x17 μm2 pixel sizes in development. The prototype has been designed and fabricated in 0.25- μm SiGe:C BiCMOS process.

  18. Improved Space Object Orbit Determination Using CMOS Detectors

    Science.gov (United States)

    Schildknecht, T.; Peltonen, J.; Sännti, T.; Silha, J.; Flohrer, T.

    2014-09-01

    CMOS-sensors, or in general Active Pixel Sensors (APS), are rapidly replacing CCDs in the consumer camera market. Due to significant technological advances during the past years these devices start to compete with CCDs also for demanding scientific imaging applications, in particular in the astronomy community. CMOS detectors offer a series of inherent advantages compared to CCDs, due to the structure of their basic pixel cells, which each contains their own amplifier and readout electronics. The most prominent advantages for space object observations are the extremely fast and flexible readout capabilities, feasibility for electronic shuttering and precise epoch registration, and the potential to perform image processing operations on-chip and in real-time. The major challenges and design drivers for ground-based and space-based optical observation strategies have been analyzed. CMOS detector characteristics were critically evaluated and compared with the established CCD technology, especially with respect to the above mentioned observations. Similarly, the desirable on-chip processing functionalities which would further enhance the object detection and image segmentation were identified. Finally, we simulated several observation scenarios for ground- and space-based sensor by assuming different observation and sensor properties. We will introduce the analyzed end-to-end simulations of the ground- and space-based strategies in order to investigate the orbit determination accuracy and its sensitivity which may result from different values for the frame-rate, pixel scale, astrometric and epoch registration accuracies. Two cases were simulated, a survey using a ground-based sensor to observe objects in LEO for surveillance applications, and a statistical survey with a space-based sensor orbiting in LEO observing small-size debris in LEO. The ground-based LEO survey uses a dynamical fence close to the Earth shadow a few hours after sunset. For the space-based scenario

  19. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    International Nuclear Information System (INIS)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan

    2009-01-01

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 μm RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm 2 and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  20. A 3.1-4.8 GHz CMOS receiver for MB-OFDM UWB

    Energy Technology Data Exchange (ETDEWEB)

    Yang Guang; Yao Wang; Yin Jiangwei; Zheng Renliang; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2009-01-15

    An integrated fully differential ultra-wideband CMOS receiver for 3.1-4.8 GHz MB-OFDM systems is presented. A gain controllable low noise amplifier and a merged quadrature mixer are integrated as the RF front-end. Five order Gm-C type low pass filters and VGAs are also integrated for both I and Q IF paths in the receiver. The ESD protected chip is fabricated in a Jazz 0.18 mum RF CMOS process and achieves a maximum total voltage gain of 65 dB, an AGC range of 45 dB with about 6 dB/step, an averaged total noise figure of 6.4 to 8.8 dB over 3 bands and an in-band IIP3 of -5.1 dBm. The receiver occupies 2.3 mm{sup 2} and consumes 110 mA from a 1.8 V supply including test buffers and a digital module.

  1. A 5 Gb/s CMOS adaptive equalizer for serial link

    Science.gov (United States)

    Wu, Hongbing; Wang, Jingyu; Liu, Hongxia

    2018-04-01

    A 5 Gb/s adaptive equalizer with a new adaptation scheme is presented here by using 0.13 μm CMOS process. The circuit consists of the combination of equalizer amplifier, limiter amplifier and adaptation loop. The adaptive algorithm exploits both the low frequency gain loop and the equalizer loop to minimize the inter-symbol interference (ISI) for a variety of cable characteristics. In addition, an offset cancellation loop is used to alleviate the offset influence of the signal path. The adaptive equalizer core occupies an area of 0.3567 mm2 and consumes a power consumption of 81.7 mW with 1.8 V power supply. Experiment results demonstrate that the equalizer could compensate for a designed cable loss with 0.23 UI peak-to-peak jitter. Project supported by the National Natural Science Foundation of China (No. 61376099), the Foundation for Fundamental Research of China (No. JSZL2016110B003), and the Major Fundamental Research Program of Shaanxi (No. 2017ZDJC-26).

  2. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection

    Directory of Open Access Journals (Sweden)

    Diwei He

    2015-07-01

    Full Text Available Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1% with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  3. A Single-Chip CMOS Pulse Oximeter with On-Chip Lock-In Detection.

    Science.gov (United States)

    He, Diwei; Morgan, Stephen P; Trachanis, Dimitrios; van Hese, Jan; Drogoudis, Dimitris; Fummi, Franco; Stefanni, Francesco; Guarnieri, Valerio; Hayes-Gill, Barrie R

    2015-07-14

    Pulse oximetry is a noninvasive and continuous method for monitoring the blood oxygen saturation level. This paper presents the design and testing of a single-chip pulse oximeter fabricated in a 0.35 µm CMOS process. The chip includes photodiode, transimpedance amplifier, analogue band-pass filters, analogue-to-digital converters, digital signal processor and LED timing control. The experimentally measured AC and DC characteristics of individual circuits including the DC output voltage of the transimpedance amplifier, transimpedance gain of the transimpedance amplifier, and the central frequency and bandwidth of the analogue band-pass filters, show a good match (within 1%) with the circuit simulations. With modulated light source and integrated lock-in detection the sensor effectively suppresses the interference from ambient light and 1/f noise. In a breath hold and release experiment the single chip sensor demonstrates consistent and comparable performance to commercial pulse oximetry devices with a mean of 1.2% difference. The single-chip sensor enables a compact and robust design solution that offers a route towards wearable devices for health monitoring.

  4. Post-CMOS selective electroplating technique for the improvement of CMOS-MEMS accelerometers

    International Nuclear Information System (INIS)

    Liu, Yu-Chia; Tsai, Ming-Han; Fang, Weileun; Tang, Tsung-Lin

    2011-01-01

    This study presents a simple approach to improve the performance of the CMOS-MEMS capacitive accelerometer by means of the post-CMOS metal electroplating process. The metal layer can be selectively electroplated on the MEMS structures at low temperature and the thickness of the metal layer can be easily adjusted by this process. Thus the performance of the capacitive accelerometer (i.e. sensitivity, noise floor and the minimum detectable signal) can be improved. In application, the proposed accelerometers have been implemented using (1) the standard CMOS 0.35 µm 2P4M process by CMOS foundry, (2) Ti/Au seed layers deposition/patterning by MEMS foundry and (3) in-house post-CMOS electroplating and releasing processes. Measurements indicate that the sensitivity is improved 2.85-fold, noise is decreased near 1.7-fold and the minimum detectable signal is improved from 1 to 0.2 G after nickel electroplating. Moreover, unwanted structure deformation due to the temperature variation is significantly suppressed by electroplated nickel.

  5. Evolution of Ion Implantation Technology and its Contribution to Semiconductor Industry

    International Nuclear Information System (INIS)

    Tsukamoto, Katsuhiro; Kuroi, Takashi; Kawasaki, Yoji

    2011-01-01

    Industrial aspects of the evolution of ion implantation technology will be reviewed, and their impact on the semiconductor industry will be discussed. The main topics will be the technology's application to the most advanced, ultra scaled CMOS, and to power devices, as well as productivity improvements in implantation technology. Technological insights into future developments in ion-related technologies for emerging industries will also be presented.

  6. Design of 2.4Ghz CMOS Floating Active Inductor LNA using 130nm Technology

    Science.gov (United States)

    Muhamad, M.; Soin, N.; Ramiah, H.

    2018-03-01

    This paper presents about design and optimization of CMOS active inductor integrated circuit. This active inductor implements using Silterra 0.13μm technology and simulated using Cadence Virtuoso and Spectre RF. The center frequency for this active inductor is at 2.4 GHz which follow IEEE 802.11 b/g/n standard. To reduce the chip size of silicon, active inductor is used instead of passive inductor at low noise amplifier LNA circuit. This inductor test and analyse by low noise amplifier circuit. Comparison between active with passive inductor based on LNA circuit has been performed. Result shown that the active inductor has significantly reduce the chip size with 73 % area without sacrificing the noise figure and gain of LNA which is the most important criteria in LNA. The best low noise amplifier provides a power gain (S21) of 20.7 dB with noise figure (NF) of 2.1dB.

  7. Implantable intraocular pressure monitoring systems: Design considerations

    KAUST Repository

    Arsalan, Muhammad

    2013-12-01

    Design considerations and limitations of implantable Intraocular Pressure Monitoring (IOPM) systems are presented in this paper. Detailed comparison with the state of the art is performed to highlight the benefits and challenges of the proposed design. The system-on-chip, presented here, is battery free and harvests energy from incoming RF signals. This low-cost design, in standard CMOS process, does not require any external components or bond wires to function. This paper provides useful insights to the designers of implantable wireless sensors in terms of design choices and associated tradeoffs. © 2013 IEEE.

  8. Implantable intraocular pressure monitoring systems: Design considerations

    KAUST Repository

    Arsalan, Muhammad; Ouda, Mahmoud H.; Marnat, Loic; Shamim, Atif; Salama, Khaled N.

    2013-01-01

    Design considerations and limitations of implantable Intraocular Pressure Monitoring (IOPM) systems are presented in this paper. Detailed comparison with the state of the art is performed to highlight the benefits and challenges of the proposed design. The system-on-chip, presented here, is battery free and harvests energy from incoming RF signals. This low-cost design, in standard CMOS process, does not require any external components or bond wires to function. This paper provides useful insights to the designers of implantable wireless sensors in terms of design choices and associated tradeoffs. © 2013 IEEE.

  9. A current to voltage converter for cryogenics using a CMOS operational amplifier

    International Nuclear Information System (INIS)

    Hayashi, K; Saitoh, K; Shibayama, Y; Shirahama, K

    2009-01-01

    We have constructed a versatile current to voltage (I-V) converter operating at liquid helium temperature, using a commercially available all-CMOS OPamp. It is valuable for cryogenic measurements of electrical current of nano-pico amperes, for example, in scanning probe microscopy. The I-V converter is thermally linked to liquid helium bath and self-heated up to 10.7 K. We have confirmed its capability of a transimpedance gain of 10 6 V/A and a bandwidth from DC to 200 kHz. In order to test the practical use for a frequency-modulation atomic force microscope, we have measured the resonance frequency shift of a quartz tuning fork at 32 kHz. In the operation of the I-V converter close to the sensor at liquid helium temperature, the signal-to-noise ratio has been improved to a factor of 13.6 compared to the operation at room temperature.

  10. A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

    Science.gov (United States)

    Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

    2018-01-01

    Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

  11. BioCMOS Interfaces and Co-Design

    CERN Document Server

    Carrara, Sandro

    2013-01-01

    The application of CMOS circuits and ASIC VLSI systems to problems in medicine and system biology has led to the emergence of Bio/CMOS Interfaces and Co-Design as an exciting and rapidly growing area of research. The mutual inter-relationships between VLSI-CMOS design and the biophysics of molecules interfacing with silicon and/or onto metals has led to the emergence of the interdisciplinary engineering approach to Bio/CMOS interfaces. This new approach, facilitated by 3D circuit design and nanotechnology, has resulted in new concepts and applications for VLSI systems in the bio-world. This book offers an invaluable reference to the state-of-the-art in Bio/CMOS interfaces. It describes leading-edge research in the field of CMOS design and VLSI development for applications requiring integration of biological molecules onto the chip. It provides multidisciplinary content ranging from biochemistry to CMOS design in order to address Bio/CMOS interface co-design in bio-sensing applications.

  12. A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

  13. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf,; Kurt, O [Albuquerque, NM

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  14. A current to voltage converter for cryogenics using a CMOS operational amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Hayashi, K; Saitoh, K; Shibayama, Y; Shirahama, K [Department of Physics, Keio University, Yokohama 223-8522 (Japan)], E-mail: khayashi@a2.keio.jp

    2009-02-01

    We have constructed a versatile current to voltage (I-V) converter operating at liquid helium temperature, using a commercially available all-CMOS OPamp. It is valuable for cryogenic measurements of electrical current of nano-pico amperes, for example, in scanning probe microscopy. The I-V converter is thermally linked to liquid helium bath and self-heated up to 10.7 K. We have confirmed its capability of a transimpedance gain of 10{sup 6} V/A and a bandwidth from DC to 200 kHz. In order to test the practical use for a frequency-modulation atomic force microscope, we have measured the resonance frequency shift of a quartz tuning fork at 32 kHz. In the operation of the I-V converter close to the sensor at liquid helium temperature, the signal-to-noise ratio has been improved to a factor of 13.6 compared to the operation at room temperature.

  15. Hybrid CMOS/Molecular Integrated Circuits

    Science.gov (United States)

    Stan, M. R.; Rose, G. S.; Ziegler, M. M.

    CMOS silicon technologies are likely to run out of steam in the next 10-15 years despite revolutionary advances in the past few decades. Molecular and other nanoscale technologies show significant promise but it is unlikely that they will completely replace CMOS, at least in the near term. This chapter explores opportunities for using CMOS and nanotechnology to enhance and complement each other in hybrid circuits. As an example of such a hybrid CMOS/nano system, a nanoscale programmable logic array (PLA) based on majority logic is described along with its supplemental CMOS circuitry. It is believed that such systems will be able to sustain the historical advances in the semiconductor industry while addressing manufacturability, yield, power, cost, and performance challenges.

  16. Monolithic pixel detectors in a 0.13μm CMOS technology with sensor level continuous time charge amplification and shaping

    International Nuclear Information System (INIS)

    Ratti, L.; Manghisoni, M.; Re, V.; Speziali, V.; Traversi, G.; Bettarini, S.; Calderini, G.; Cenci, R.; Giorgi, M.; Forti, F.; Morsani, F.; Rizzo, G.

    2006-01-01

    This work studies the feasibility of a new implementation of CMOS monolithic active pixel sensors (MAPS) for applications to charged particle tracking. As compared to standard three MOSFET MAPS, where the charge signal is readout by a source follower, the proposed front-end scheme relies upon a charge sensitive amplifier (CSA), embedded in the elementary pixel cell, to perform charge-to-voltage conversion. The area required for the integration of the front-end electronics is mostly provided by the collecting electrode, which consists of a deep n-type diffusion, available as a shielding frame for n-channel devices in deep submicron, triple well CMOS technologies. Based on the above concept, a chip, which includes several test structures differing in the sensitive element area, has been fabricated in a 0.13μm CMOS process. In this paper, the criteria underlying the design of the pixel level analog processor will be presented, together with some preliminary experimental results demonstrating the feasibility of the proposed approach

  17. CMOS MEMS Fabrication Technologies and Devices

    Directory of Open Access Journals (Sweden)

    Hongwei Qu

    2016-01-01

    Full Text Available This paper reviews CMOS (complementary metal-oxide-semiconductor MEMS (micro-electro-mechanical systems fabrication technologies and enabled micro devices of various sensors and actuators. The technologies are classified based on the sequence of the fabrication of CMOS circuitry and MEMS elements, while SOI (silicon-on-insulator CMOS MEMS are introduced separately. Introduction of associated devices follows the description of the respective CMOS MEMS technologies. Due to the vast array of CMOS MEMS devices, this review focuses only on the most typical MEMS sensors and actuators including pressure sensors, inertial sensors, frequency reference devices and actuators utilizing different physics effects and the fabrication processes introduced. Moreover, the incorporation of MEMS and CMOS is limited to monolithic integration, meaning wafer-bonding-based stacking and other integration approaches, despite their advantages, are excluded from the discussion. Both competitive industrial products and state-of-the-art research results on CMOS MEMS are covered.

  18. A CMOS In-Pixel CTIA High Sensitivity Fluorescence Imager.

    Science.gov (United States)

    Murari, Kartikeya; Etienne-Cummings, Ralph; Thakor, Nitish; Cauwenberghs, Gert

    2011-10-01

    Traditionally, charge coupled device (CCD) based image sensors have held sway over the field of biomedical imaging. Complementary metal oxide semiconductor (CMOS) based imagers so far lack sensitivity leading to poor low-light imaging. Certain applications including our work on animal-mountable systems for imaging in awake and unrestrained rodents require the high sensitivity and image quality of CCDs and the low power consumption, flexibility and compactness of CMOS imagers. We present a 132×124 high sensitivity imager array with a 20.1 μm pixel pitch fabricated in a standard 0.5 μ CMOS process. The chip incorporates n-well/p-sub photodiodes, capacitive transimpedance amplifier (CTIA) based in-pixel amplification, pixel scanners and delta differencing circuits. The 5-transistor all-nMOS pixel interfaces with peripheral pMOS transistors for column-parallel CTIA. At 70 fps, the array has a minimum detectable signal of 4 nW/cm(2) at a wavelength of 450 nm while consuming 718 μA from a 3.3 V supply. Peak signal to noise ratio (SNR) was 44 dB at an incident intensity of 1 μW/cm(2). Implementing 4×4 binning allowed the frame rate to be increased to 675 fps. Alternately, sensitivity could be increased to detect about 0.8 nW/cm(2) while maintaining 70 fps. The chip was used to image single cell fluorescence at 28 fps with an average SNR of 32 dB. For comparison, a cooled CCD camera imaged the same cell at 20 fps with an average SNR of 33.2 dB under the same illumination while consuming over a watt.

  19. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal; Elshurafa, Amro M.; Mohammad, Mohammad Ali; Nelson-Fitzpatrick, Nathan E.; Evoy, S.

    2012-01-01

    . The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly

  20. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  1. Single event mirroring and sense amplifier designs for enhanced SE tolerance of DRAMs

    International Nuclear Information System (INIS)

    Gulati, K.; Massengill, L.W.

    1994-01-01

    This paper investigates the applicability of existing SRAM SEU hardening techniques to conventional CMOS cross-coupled sense amplifiers used in DRAM structures. We propose a novel SEU mirroring concept and implementation for hardening DRAMs to bitline hits. Simulations indicate a 24-fold improvement in critical charge during the sensing state using a 10K T-Resistor scheme and a 28-fold improvement during the highly susceptible high impedance state using 2pF dynamic capacitance coupling

  2. A monolithic 180 nm CMOS dosimeter for In Vivo Dosimetry medical application

    International Nuclear Information System (INIS)

    Villani, E.G.; Crepaldi, M.; DeMarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Rosenfeld, A.; Zhang, Z.

    2014-01-01

    The design and development of a monolithic system-on-chip dosimeter fabricated in a standard 180 nm CMOS technology is described. The device is intended for real time In Vivo measurement of dose of radiation during radiotherapy sessions. Owing to its proposed small size, of approximately 1 mm 3 , such solution could be made in-body implantable and, as such, provide a much-enhanced high-resolution, real-time dose measurement for quality assurance in radiation therapy. The device transmits the related information on dose of radiation wirelessly to an external receiver operating in the MICS band. The various phases of this two years project, started in 2011, including the design and development of radiation sensors and integrated RF to perform the readout, will be described. - Highlights: • A novel monolithic CMOS dosimeter of size of 1 mm 3 has been proposed. • Three different fabrications using a CMOS 180 nm technology have been carried out. • Radiation tests results showed a sensitivity of 1 cGy with accuracy better than 3%. • Preliminary RF tests showed that an RF signal is detectable in free air

  3. Ways to suppress click and pop for class D amplifiers

    International Nuclear Information System (INIS)

    Wang Haishi; Zhang Bo; Sun Jiang

    2012-01-01

    Undesirable audio click and pop may be generated in a speaker or headphone. Compared to linear (class A/B/AB) amplifiers, class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop. This article analyzes sources that generate click and pop in class D amplifiers, and corresponding ways to suppress them. For a class D amplifier with a single-ended input, click and pop is likely to be due to two factors. One is from a voltage difference (V DIF ) between the voltage of an input capacitance (V CIN ) and a reference voltage (V REF ) of the input stage, and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage. In this article, a fast charging loop is introduced into the input stage to charge V CIN to roughly near V REF . Then a correction loop further charges or discharges V CIN , substantially equalizing it with V REF . Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC, and the power switches are disabled until the BFVC are set up successfully. A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process. Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop. (semiconductor integrated circuits)

  4. Ways to suppress click and pop for class D amplifiers

    Science.gov (United States)

    Haishi, Wang; Bo, Zhang; Jiang, Sun

    2012-08-01

    Undesirable audio click and pop may be generated in a speaker or headphone. Compared to linear (class A/B/AB) amplifiers, class D amplifiers that comprise of an input stage and a modulation stage are more prone to producing click and pop. This article analyzes sources that generate click and pop in class D amplifiers, and corresponding ways to suppress them. For a class D amplifier with a single-ended input, click and pop is likely to be due to two factors. One is from a voltage difference (VDIF) between the voltage of an input capacitance (VCIN) and a reference voltage (VREF) of the input stage, and the other one is from the non-linear switching during the setting up of the bias and feedback voltages/currents (BFVC) of the modulation stage. In this article, a fast charging loop is introduced into the input stage to charge VCIN to roughly near VREF. Then a correction loop further charges or discharges VCIN, substantially equalizing it with VREF. Dummy switches are introduced into the modulation stage to provide switching signals for setting up BFVC, and the power switches are disabled until the BFVC are set up successfully. A two channel single-ended class D amplifier with the above features is fabricated with 0.5 μm Bi-CMOS process. Road test and fast Fourier transform analysis indicate that there is no noticeable click and pop.

  5. A CMOS Luminescence Intensity and Lifetime Dual Sensor Based on Multicycle Charge Modulation.

    Science.gov (United States)

    Fu, Guoqing; Sonkusale, Sameer R

    2018-06-01

    Luminescence plays an important role in many scientific and industrial applications. This paper proposes a novel complementary metal-oxide-semiconductor (CMOS) sensor chip that can realize both luminescence intensity and lifetime sensing. To enable high sensitivity, we propose parasitic insensitive multicycle charge modulation scheme for low-light lifetime extraction benefiting from simplicity, accuracy, and compatibility with deeply scaled CMOS process. The designed in-pixel capacitive transimpedance amplifier (CTIA) based structure is able to capture the weak luminescence-induced voltage signal by accumulating photon-generated charges in 25 discrete gated 10-ms time windows and 10-μs pulsewidth. A pinned photodiode on chip with 1.04 pA dark current is utilized for luminescence detection. The proposed CTIA-based circuitry can achieve 2.1-mV/(nW/cm 2 ) responsivity and 4.38-nW/cm 2 resolution at 630 nm wavelength for intensity measurement and 45-ns resolution for lifetime measurement. The sensor chip is employed for measuring time constants and luminescence lifetimes of an InGaN-based white light-emitting diode at different wavelengths. In addition, we demonstrate accurate measurement of the lifetime of an oxygen sensitive chromophore with sensitivity to oxygen concentration of 7.5%/ppm and 6%/ppm in both intensity and lifetime domain. This CMOS-enabled oxygen sensor was then employed to test water quality from different sources (tap water, lakes, and rivers).

  6. A 65 nm CMOS analog processor with zero dead time for future pixel detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L., E-mail: luigi.gaioni@unibg.it [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Braga, D.; Christian, D.C.; Deptuch, G.; Fahim, F. [Fermi National Accelerator Laboratory, Batavia IL (United States); Nodari, B. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Centre National de Recherche Scientifique, APC/IN2P3, Paris (France); Ratti, L. [Università di Pavia, I-27100 Pavia (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Re, V. [Università di Bergamo, I-24044 Dalmine (Italy); INFN, Sezione di Pavia, I-27100 Pavia (Italy); Zimmerman, T. [Fermi National Accelerator Laboratory, Batavia IL (United States)

    2017-02-11

    Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10{sup 34} cm{sup −2} s{sup −1} in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. A thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

  7. Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

    Science.gov (United States)

    Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

    2018-04-01

    In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

  8. An implantable CMOS signal conditioning system for recording nerve signals with cuff electrodes

    DEFF Research Database (Denmark)

    Papathanasiou, Konstantinos; Lehmann, Torsten

    2000-01-01

    We propose a system architecture for recording nerve signals with cuff electrodes and develop the key component in this system, the small-input, low-noise, low-power, high-gain amplifier. The amplifier is implemented using a mixture of weak- and strong-inversion transistors and a special off-set ......-set compensation technique; its performance is validated using Spice simulations....

  9. Current feedback operational amplifiers and their applications

    CERN Document Server

    Senani, Raj; Singh, A K; Singh, V K

    2013-01-01

    This book describes a variety of current feedback operational amplifier (CFOA) architectures and their applications in analog signal processing/generation. Coverage includes a comprehensive survey of commercially available, off-the-shelf integrated circuit CFOAs, as well as recent advances made on the design of CFOAs, including design innovations for bipolar and CMOS CFOAs.  This book serves as a single-source reference to the topic, as well as a catalog of over 200 application circuits which would be useful not only for students, educators and researchers in apprising them about the recent developments in the area but would also serve as a comprehensive repertoire of useful circuits for practicing engineers who might be interested in choosing an appropriate CFOA-based topology for use in a given application.

  10. OFCC based voltage and transadmittance mode instrumentation amplifier

    Science.gov (United States)

    Nand, Deva; Pandey, Neeta; Pandey, Rajeshwari; Tripathi, Prateek; Gola, Prashant

    2017-07-01

    The operational floating current conveyor (OFCC) is a versatile active block due to the availability of both low and high input and output impedance terminals. This paper addresses the realization of OFCC based voltage and transadmittance mode instrumentation amplifiers (VMIA and TAM IA). It employs three OFCCs and seven resistors. The transadmittance mode operation can easily be obtained by simply connecting an OFCC based voltage to current converter at the output. The effect of non-idealities of OFCC, in particular finite transimpedance and tracking error, on system performance is also dealt with and corresponding mathematical expressions are derived. The functional verification is performed through SPICE simulation using CMOS based implementation of OFCC.

  11. Microelectronic test structures for CMOS technology

    CERN Document Server

    Ketchen, Mark B

    2011-01-01

    Microelectronic Test Structures for CMOS Technology and Products addresses the basic concepts of the design of test structures for incorporation within test-vehicles, scribe-lines, and CMOS products. The role of test structures in the development and monitoring of CMOS technologies and products has become ever more important with the increased cost and complexity of development and manufacturing. In this timely volume, IBM scientists Manjul Bhushan and Mark Ketchen emphasize high speed characterization techniques for digital CMOS circuit applications and bridging between circuit performance an

  12. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  13. Development of a Depleted Monolithic CMOS Sensor in a 150 nm CMOS Technology for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Wang, T.

    2017-01-01

    The recent R&D focus on CMOS sensors with charge collection in a depleted zone has opened new perspectives for CMOS sensors as fast and radiation hard pixel devices. These sensors, labelled as depleted CMOS sensors (DMAPS), have already shown promising performance as feasible candidates for the ATLAS Inner Tracker (ITk) upgrade, possibly replacing the current passive sensors. A further step to exploit the potential of DMAPS is to investigate the suitability of equipping the outer layers of the ATLAS ITk upgrade with fully monolithic CMOS sensors. This paper presents the development of a depleted monolithic CMOS pixel sensor designed in the LFoundry 150 nm CMOS technology, with the focus on design details and simulation results.

  14. A low power and low distortion rail-to-rail input/output amplifier using constant current technique

    International Nuclear Information System (INIS)

    Liu Yan; Zhao Yiqiang; Zhang Shilin; Zhao Hongliang

    2011-01-01

    A rail-to-rail amplifier with constant transconductance, intended for audio processing, is presented. The constant transconductance is obtained by a constant current technique based on the input differential pairs operating in the weak inversion region. MOSFETs working in the weak inversion region have the advantages of low power and low distortion. The proposed rail-to-rail amplifier, fabricated in a standard 0.35 μm CMOS process, occupies a core die area of 75 x 183 μm 2 . Measured results show that the maximum power consumption is 85.37 μW with a supply voltage of 3.3 V and the total harmonic distortion level is 1.2% at 2 kHz. (semiconductor integrated circuits)

  15. Design of an integrated analog controller for a Class-D Audio Amplifier

    OpenAIRE

    Verbrugghe, Jochen; De Bock, Maarten; Rombouts, Pieter

    2009-01-01

    An integrated analog controller for a self-oscillating class-D audio power amplifier is designed in a 0.35 μm CMOS technology for a 3.3 Volt power supply. It is intended to be used with an external output stage and passive filter, for medium power applications of upto a few 100 Watts. The controller was optimized with regard to its loop gain to suppress the distortion of the output stage. In typical commercially available output stages, the distortion is dominated by dead time effects and th...

  16. Large area CMOS image sensors

    International Nuclear Information System (INIS)

    Turchetta, R; Guerrini, N; Sedgwick, I

    2011-01-01

    CMOS image sensors, also known as CMOS Active Pixel Sensors (APS) or Monolithic Active Pixel Sensors (MAPS), are today the dominant imaging devices. They are omnipresent in our daily life, as image sensors in cellular phones, web cams, digital cameras, ... In these applications, the pixels can be very small, in the micron range, and the sensors themselves tend to be limited in size. However, many scientific applications, like particle or X-ray detection, require large format, often with large pixels, as well as other specific performance, like low noise, radiation hardness or very fast readout. The sensors are also required to be sensitive to a broad spectrum of radiation: photons from the silicon cut-off in the IR down to UV and X- and gamma-rays through the visible spectrum as well as charged particles. This requirement calls for modifications to the substrate to be introduced to provide optimized sensitivity. This paper will review existing CMOS image sensors, whose size can be as large as a single CMOS wafer, and analyse the technical requirements and specific challenges of large format CMOS image sensors.

  17. Highly-Integrated CMOS Interface Circuits for SiPM-Based PET Imaging Systems.

    Science.gov (United States)

    Dey, Samrat; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2012-01-01

    Recent developments in the area of Positron Emission Tomography (PET) detectors using Silicon Photomultipliers (SiPMs) have demonstrated the feasibility of higher resolution PET scanners due to a significant reduction in the detector form factor. The increased detector density requires a proportionally larger number of channels to interface the SiPM array with the backend digital signal processing necessary for eventual image reconstruction. This work presents a CMOS ASIC design for signal reducing readout electronics in support of an 8×8 silicon photomultiplier array. The row/column/diagonal summation circuit significantly reduces the number of required channels, reducing the cost of subsequent digitizing electronics. Current amplifiers are used with a single input from each SiPM cathode. This approach helps to reduce the detector loading, while generating all the necessary row, column and diagonal addressing information. In addition, the single current amplifier used in our Pulse-Positioning architecture facilitates the extraction of pulse timing information. Other components under design at present include a current-mode comparator which enables threshold detection for dark noise current reduction, a transimpedance amplifier and a variable output impedance I/O driver which adapts to a wide range of loading conditions between the ASIC and lines with the off-chip Analog-to-Digital Converters (ADCs).

  18. A Programmable Biopotential Aquisition Front-end with a Resistance-free Current-balancing Instrumentation Amplifier

    Directory of Open Access Journals (Sweden)

    FARAGO, P.

    2018-05-01

    Full Text Available The development of wearable biomedical equipment benefits from low-power and low-voltage circuit techniques for reduced battery size and battery, or even battery-less, operation. This paper proposes a fully-differential low-power resistance-free programmable instrumentation amplifier for the analog front-end of biopotential monitoring systems. The proposed instrumentation amplifier implements the current balancing technique. Low power consumption is achieved with subthreshold biasing. To reduce chip area and enable integration, passive resistances have been replaced with active equivalents. Accordingly, the instrumentation amplifier gain is expressed as the ratio of two transconductance values. The proposed instrumentation amplifier exhibits two degrees of freedom: one to set the desired range and the other for fine-tuning of the voltage gain. The proposed IA is employed in a programmable biopotential acquisition front-end. The programmable frequency-selective behavior is achieved by having the lower cutoff frequency of a Gm-C Tow-Thomas biquad varied in a constant-C tuning approach. The proposed solutions and the programmability of the operation parameters to the specifications of particular bio-medical signals are validated on a 350nm CMOS process.

  19. Design, simulation and comparative analysis of CNT based cascode operational transconductance amplifiers

    Science.gov (United States)

    Nizamuddin, M.; Loan, Sajad A.; Alamoud, Abdul R.; Abbassi, Shuja A.

    2015-10-01

    In this work, design and calibrated simulation of carbon nanotube field effect transistor (CNTFET)-based cascode operational transconductance amplifiers (COTA) have been performed. Three structures of CNTFET-based COTAs have been designed using HSPICE and have been compared with the conventional CMOS-based COTAs. The proposed COTAs include one using pure CNTFETs and two others that employ CNTFETs, as well as the conventional MOSFETs. The simulation study has revealed that the CNTFET-based COTAs have significantly outperformed the conventional MOSFET-based COTAs. A significant increase in dc gain, output resistance and slew rate of 81.4%, 25% and 13.2%, respectively, have been achieved in the proposed pure CNT-based COTA in comparison to the conventional CMOS-based COTA. The power consumption in the pure CNT-COTA is 324 times less in comparison to the conventional CMOS-COTA. Further, the phase margin (PM), gain margin (GM), common mode and power supply rejection ratios have been significantly increased in the proposed CNT-based COTAs in comparison to the conventional CMOS-based COTAs. Furthermore, to see the advantage of cascoding, the proposed CNT-based cascode OTAs have been compared with the CNT-based OTAs. It has been observed that by incorporating the concept of cascode in the CNTFET-based OTAs, significant increases in gain (12.5%) and output resistance (13.07%) have been achieved. The performance of the proposed COTAs has been further observed by changing the number of CNTs (N), CNT pitch (S) and CNT diameter (DCNT) in the CNTFETs used. It has been observed that the performance of the proposed COTAs can be significantly improved by using optimum values of N, S and DCNT.

  20. Low Voltage Current-Reused Pseudo-Differential Programmable Gain Amplifier

    Science.gov (United States)

    Nguyen, Huy-Hieu; Lee, Jeong-Seon; Lee, Sang-Gug

    This paper reports a current-reused pseudo-differential (CRPD) programmable gain amplifier (PGA) that demonstrates small size, low power, wide band, low noise, and high linearity operation with 4 control bits. Implemented in 0.18um CMOS technology, the PGA shows the gain range from -9.9 to 8.3dB with gain error of less than ±0.38dB. The IIP3, P1dB, and smallest 3-dB bandwidth are 10.5 to 27dBm, -9 to 9.5dBm, and 250MHz, respectively. The PGA occupies the chip area of 0.04mm2 and consumes only 460 µA from a 1.2V supply.

  1. CMOS test and evaluation a physical perspective

    CERN Document Server

    Bhushan, Manjul

    2015-01-01

    This book extends test structure applications described in Microelectronic Test Struc­tures for CMOS Technology (Springer 2011) to digital CMOS product chips. Intended for engineering students and professionals, this book provides a single comprehensive source for evaluating CMOS technology and product test data from a basic knowledge of the physical behavior of the constituent components. Elementary circuits that exhibit key properties of complex CMOS chips are simulated and analyzed, and an integrated view of design, test and characterization is developed. Appropriately designed circuit monitors embedded in the CMOS chip serve to correlate CMOS technology models and circuit design tools to the hardware and also aid in test debug. Impact of silicon process variability, reliability, and power and performance sensitivities to a range of product application conditions are described. Circuit simulations exemplify the methodologies presented, and problems are included at the end of the chapters.

  2. An integral whole circuit of amplifying and discriminating suited to high counting rate

    International Nuclear Information System (INIS)

    Dong Chengfu; Su Hong; Wu Ming; Li Xiaogang; Peng Yu; Qian Yi; Liu Yicai; Xu Sijiu; Ma Xiaoli

    2007-01-01

    A hybrid circuit consists of charge sensitive preamplifier, main amplifier, discriminator and shaping circuit was described. This instrument has characteristics of low power consumption, small volume, high sensitivity, potable and so on, and is convenient for use in field. The output pulse of this instrument may directly consist with CMOS or TTL logic level. This instrument was mainly used for count measurement, for example, for high sensitive 3 He neutron detector, meanwhile also may used for other heavy ion detectors, the highest counting rate can reach 10 6 /s. (authors)

  3. Absorbed dose by a CMOS in radiotherapy

    International Nuclear Information System (INIS)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L. C.

    2011-10-01

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  4. Neutron absorbed dose in a pacemaker CMOS

    International Nuclear Information System (INIS)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R.; Paredes G, L.

    2012-01-01

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10 -17 Gy per neutron emitted by the source. (Author)

  5. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: fermineutron@yahoo.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2012-06-15

    The neutron spectrum and the absorbed dose in a Complementary Metal Oxide Semiconductor (CMOS), has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes an oncology patient that must be treated in a linear accelerator. Pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. Above 7 MV therapeutic beam is contaminated with photoneutrons that could damage the CMOS. Here, the neutron spectrum and the absorbed dose in a CMOS cell was calculated, also the spectra were calculated in two point-like detectors in the room. Neutron spectrum in the CMOS cell shows a small peak between 0.1 to 1 MeV and a larger peak in the thermal region, joined by epithermal neutrons, same features were observed in the point-like detectors. The absorbed dose in the CMOS was 1.522 x 10{sup -17} Gy per neutron emitted by the source. (Author)

  6. An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

    Science.gov (United States)

    Edward, Alexander; Chan, Pak Kwong

    This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

  7. Design and Fabrication of Millimeter Wave Hexagonal Nano-Ferrite Circulator on Silicon CMOS Substrate

    Science.gov (United States)

    Oukacha, Hassan

    The rapid advancement of Complementary Metal Oxide Semiconductor (CMOS) technology has formed the backbone of the modern computing revolution enabling the development of computationally intensive electronic devices that are smaller, faster, less expensive, and consume less power. This well-established technology has transformed the mobile computing and communications industries by providing high levels of system integration on a single substrate, high reliability and low manufacturing cost. The driving force behind this computing revolution is the scaling of semiconductor devices to smaller geometries which has resulted in faster switching speeds and the promise of replacing traditional, bulky radio frequency (RF) components with miniaturized devices. Such devices play an important role in our society enabling ubiquitous computing and on-demand data access. This thesis presents the design and development of a magnetic circulator component in a standard 180 nm CMOS process. The design approach involves integration of nanoscale ferrite materials on a CMOS chip to avoid using bulky magnetic materials employed in conventional circulators. This device constitutes the next generation broadband millimeter-wave circulator integrated in CMOS using ferrite materials operating in the 60GHz frequency band. The unlicensed ultra-high frequency spectrum around 60GHz offers many benefits: very high immunity to interference, high security, and frequency re-use. Results of both simulations and measurements are presented in this thesis. The presented results show the benefits of this technique and the potential that it has in incorporating a complete system-on-chip (SoC) that includes low noise amplifier, power amplier, and antenna. This system-on-chip can be used in the same applications where the conventional circulator has been employed, including communication systems, radar systems, navigation and air traffic control, and military equipment. This set of applications of

  8. Absorbed dose by a CMOS in radiotherapy

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Valero L, C. Y.; Guzman G, K. A.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L. C., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-10-15

    Absorbed dose by a complementary metal oxide semiconductor (CMOS) circuit as part of a pacemaker, has been estimated using Monte Carlo calculations. For a cancer patient who is a pacemaker carrier, scattered radiation could damage pacemaker CMOS circuits affecting patient's health. Absorbed dose in CMOS circuit due to scattered photons is too small and therefore is not the cause of failures in pacemakers, but neutron calculations shown an absorbed dose that could cause damage in CMOS due to neutron-hydrogen interactions. (Author)

  9. An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

    Science.gov (United States)

    Chen, Hsin-Han; Hsieh, Chih-Cheng

    2013-09-01

    This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

  10. A 256×256 low-light-level CMOS imaging sensor with digital CDS

    Science.gov (United States)

    Zou, Mei; Chen, Nan; Zhong, Shengyou; Li, Zhengfen; Zhang, Jicun; Yao, Li-bin

    2016-10-01

    In order to achieve high sensitivity for low-light-level CMOS image sensors (CIS), a capacitive transimpedance amplifier (CTIA) pixel circuit with a small integration capacitor is used. As the pixel and the column area are highly constrained, it is difficult to achieve analog correlated double sampling (CDS) to remove the noise for low-light-level CIS. So a digital CDS is adopted, which realizes the subtraction algorithm between the reset signal and pixel signal off-chip. The pixel reset noise and part of the column fixed-pattern noise (FPN) can be greatly reduced. A 256×256 CIS with CTIA array and digital CDS is implemented in the 0.35μm CMOS technology. The chip size is 7.7mm×6.75mm, and the pixel size is 15μm×15μm with a fill factor of 20.6%. The measured pixel noise is 24LSB with digital CDS in RMS value at dark condition, which shows 7.8× reduction compared to the image sensor without digital CDS. Running at 7fps, this low-light-level CIS can capture recognizable images with the illumination down to 0.1lux.

  11. Programmable Input Mode Instrumentation Amplifier Using Multiple Output Current Conveyors

    Directory of Open Access Journals (Sweden)

    Pankiewicz Bogdan

    2017-03-01

    Full Text Available In this paper a programmable input mode instrumentation amplifier (IA utilising second generation, multiple output current conveyors and transmission gates is presented. Its main advantage is the ability to choose a voltage or current mode of inputs by setting the voltage of two configuration nodes. The presented IA is prepared as an integrated circuit block to be used alone or as a sub-block in a microcontroller or in a field programmable gate array (FPGA, which shall condition analogue signals to be next converted by an analogue-to-digital converter (ADC. IA is designed in AMS 0.35 µm CMOS technology and the power supply is 3.3 V; the power consumption is approximately 9.1 mW. A linear input range in the voltage mode reaches ± 1.68 V or ± 250 µA in current mode. A passband of the IA is above 11 MHz. The amplifier works in class A, so its current supply is almost constant and does not cause noise disturbing nearby working precision analogue circuits.

  12. Digital Offset Calibration of an OPAMP Towards Improving Static Parameters of 90 nm CMOS DAC

    Directory of Open Access Journals (Sweden)

    D. Arbet

    2014-09-01

    Full Text Available In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC based on digitally compensated input offset of the operational amplifier (OPAMP is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90 nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error is achieved.

  13. A monolithic active pixel sensor for particle detection in 0.25 μm CMOS technology

    International Nuclear Information System (INIS)

    Velthuis, J.J.; Allport, P.P.; Casse, G.; Evans, A.; Turchetta, R.; Villani, G.

    2006-01-01

    We are developing CMOS monolithic active pixel sensors (MAPS) for High Energy Physics applications. We have successfully produced 3 test structures. They feature several different pixel types including: standard 3MOS, 4MOS allowing Correlated Double Sampling (CDS), charge amplifier pixels and a flexible APS (FAPS). The FAPS has a 10 deep pipeline on each pixel. This is specifically designed with the beam structure of the TESLA proposal for the Linear Collider in mind. Results of a laser test on our first device and source test results on two more recent test structures will be presented

  14. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Zhiyuan Gao

    2015-11-01

    Full Text Available This paper presents a dynamic range (DR enhanced readout technique with a two-step time-to-digital converter (TDC for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  15. Design, simulation and comparative analysis of CNT based cascode operational transconductance amplifiers

    International Nuclear Information System (INIS)

    Nizamuddin, M; Loan, Sajad A; Alamoud, Abdul R; Abbassi, Shuja A

    2015-01-01

    In this work, design and calibrated simulation of carbon nanotube field effect transistor (CNTFET)-based cascode operational transconductance amplifiers (COTA) have been performed. Three structures of CNTFET-based COTAs have been designed using HSPICE and have been compared with the conventional CMOS-based COTAs. The proposed COTAs include one using pure CNTFETs and two others that employ CNTFETs, as well as the conventional MOSFETs. The simulation study has revealed that the CNTFET-based COTAs have significantly outperformed the conventional MOSFET-based COTAs. A significant increase in dc gain, output resistance and slew rate of 81.4%, 25% and 13.2%, respectively, have been achieved in the proposed pure CNT-based COTA in comparison to the conventional CMOS-based COTA. The power consumption in the pure CNT-COTA is 324 times less in comparison to the conventional CMOS-COTA. Further, the phase margin (PM), gain margin (GM), common mode and power supply rejection ratios have been significantly increased in the proposed CNT-based COTAs in comparison to the conventional CMOS-based COTAs. Furthermore, to see the advantage of cascoding, the proposed CNT-based cascode OTAs have been compared with the CNT-based OTAs. It has been observed that by incorporating the concept of cascode in the CNTFET-based OTAs, significant increases in gain (12.5%) and output resistance (13.07%) have been achieved. The performance of the proposed COTAs has been further observed by changing the number of CNTs (N), CNT pitch (S) and CNT diameter (D_C_N_T) in the CNTFETs used. It has been observed that the performance of the proposed COTAs can be significantly improved by using optimum values of N, S and D_C_N_T. (paper)

  16. A high gain wide dynamic range transimpedance amplifier for optical receivers

    International Nuclear Information System (INIS)

    Liu Lianxi; Zou Jiao; Liu Shubin; Niu Yue; Zhu Zhangming; Yang Yintang; En Yunfei

    2014-01-01

    As the front-end preamplifiers in optical receivers, transimpedance amplifiers (TIAs) are commonly required to have a high gain and low input noise to amplify the weak and susceptible input signal. At the same time, the TIAs should possess a wide dynamic range (DR) to prevent the circuit from becoming saturated by high input currents. Based on the above, this paper presents a CMOS transimpedance amplifier with high gain and a wide DR for 2.5 Gbit/s communications. The TIA proposed consists of a three-stage cascade pull push inverter, an automatic gain control circuit, and a shunt transistor controlled by the resistive divider. The inductive-series peaking technique is used to further extend the bandwidth. The TIA proposed displays a maximum transimpedance gain of 88.3 dBΩ with the −3 dB bandwidth of 1.8 GHz, exhibits an input current dynamic range from 100 nA to 10 mA. The output voltage noise is less than 48.23 nV/√Hz within the −3 dB bandwidth. The circuit is fabricated using an SMIC 0.18 μm 1P6M RFCMOS process and dissipates a dc power of 9.4 mW with 1.8 V supply voltage. (semiconductor integrated circuits)

  17. A CMOS Morlet Wavelet Generator

    Directory of Open Access Journals (Sweden)

    A. I. Bautista-Castillo

    2017-04-01

    Full Text Available The design and characterization of a CMOS circuit for Morlet wavelet generation is introduced. With the proposed Morlet wavelet circuit, it is possible to reach a~low power consumption, improve standard deviation (σ control and also have a small form factor. A prototype in a double poly, three metal layers, 0.5 µm CMOS process from MOSIS foundry was carried out in order to verify the functionality of the proposal. However, the design methodology can be extended to different CMOS processes. According to the performance exhibited by the circuit, may be useful in many different signal processing tasks such as nonlinear time-variant systems.

  18. CMOS image sensors: State-of-the-art

    Science.gov (United States)

    Theuwissen, Albert J. P.

    2008-09-01

    This paper gives an overview of the state-of-the-art of CMOS image sensors. The main focus is put on the shrinkage of the pixels : what is the effect on the performance characteristics of the imagers and on the various physical parameters of the camera ? How is the CMOS pixel architecture optimized to cope with the negative performance effects of the ever-shrinking pixel size ? On the other hand, the smaller dimensions in CMOS technology allow further integration on column level and even on pixel level. This will make CMOS imagers even smarter that they are already.

  19. All-CMOS night vision viewer with integrated microdisplay

    Science.gov (United States)

    Goosen, Marius E.; Venter, Petrus J.; du Plessis, Monuko; Faure, Nicolaas M.; Janse van Rensburg, Christo; Rademeyer, Pieter

    2014-02-01

    The unrivalled integration potential of CMOS has made it the dominant technology for digital integrated circuits. With the advent of visible light emission from silicon through hot carrier electroluminescence, several applications arose, all of which rely upon the advantages of mature CMOS technologies for a competitive edge in a very active and attractive market. In this paper we present a low-cost night vision viewer which employs only standard CMOS technologies. A commercial CMOS imager is utilized for near infrared image capturing with a 128x96 pixel all-CMOS microdisplay implemented to convey the image to the user. The display is implemented in a standard 0.35 μm CMOS process, with no process alterations or post processing. The display features a 25 μm pixel pitch and a 3.2 mm x 2.4 mm active area, which through magnification presents the virtual image to the user equivalent of a 19-inch display viewed from a distance of 3 meters. This work represents the first application of a CMOS microdisplay in a low-cost consumer product.

  20. A low power cyclic ADC design for a wireless monitoring system for orthopedic implants

    Energy Technology Data Exchange (ETDEWEB)

    Chen Yi; Li Fule; Chen Hong; Zhang Chun; Wang Zhihua, E-mail: chenyi02@mails.tsinghua.edu.c [Tsinghua National Laboratory for Information Science and Technology, Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2009-08-15

    This paper presents a low power cyclic analog-to-digital convertor (ADC) design for a wireless monitoring system for orthopedic implants. A two-stage cyclic structure including a single to differential converter, two multiplying DAC functional blocks (MDACs) and some comparators is adopted, which brings moderate speed and moderate resolution with low power consumption. The MDAC is implemented with the common switched capacitor method. The 1.5-bit stage greatly simplifies the design of the comparator. The operational amplifier is carefully optimized both in schematic and layout for low power and offset. The prototype chip has been fabricated in a United Microelectronics Corporation (UMC) 0.18-{mu}m 1P6M CMOS process. The core of the ADC occupies only 0.12 mm{sup 2}. With a 304.7-Hz input and 4-kHz sampling rate, the measured peak SNDR and SFDR are 47.1 dB and 57.8 dBc respectively and its DNL and INL are 0.27 LSB and 0.3 LSB, respectively. The power consumption of the ADC is only 12.5 {mu}W in normal working mode and less than 150 nW in sleep mode. (semiconductor integrated circuits)

  1. Beyond CMOS nanodevices 1

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students.  It particularly focuses on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications

  2. Beyond CMOS nanodevices 2

    CERN Document Server

    Balestra, Francis

    2014-01-01

    This book offers a comprehensive review of the state-of-the-art in innovative Beyond-CMOS nanodevices for developing novel functionalities, logic and memories dedicated to researchers, engineers and students. The book will particularly focus on the interest of nanostructures and nanodevices (nanowires, small slope switches, 2D layers, nanostructured materials, etc.) for advanced More than Moore (RF-nanosensors-energy harvesters, on-chip electronic cooling, etc.) and Beyond-CMOS logic and memories applications.

  3. On-Chip Implantable Antennas for Wireless Power and Data Transfer in a Glaucoma-Monitoring SoC

    KAUST Repository

    Marnat, Loic; Arsalan, Muhammad; Ouda, Mahmoud H.; Salama, Khaled N.; Shamim, Atif

    2013-01-01

    For the first time separate transmit and receive onchip antennas have been designed in a eye environment for implantable intraocular pressure monitoring application. The miniaturized antennas fit on a 1.4 mm3 CMOS (0.18 μm) chip with the rest

  4. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  5. Variation-aware advanced CMOS devices and SRAM

    CERN Document Server

    Shin, Changhwan

    2016-01-01

    This book provides a comprehensive overview of contemporary issues in complementary metal-oxide semiconductor (CMOS) device design, describing how to overcome process-induced random variations such as line-edge-roughness, random-dopant-fluctuation, and work-function variation, and the applications of novel CMOS devices to cache memory (or Static Random Access Memory, SRAM). The author places emphasis on the physical understanding of process-induced random variation as well as the introduction of novel CMOS device structures and their application to SRAM. The book outlines the technical predicament facing state-of-the-art CMOS technology development, due to the effect of ever-increasing process-induced random/intrinsic variation in transistor performance at the sub-30-nm technology nodes. Therefore, the physical understanding of process-induced random/intrinsic variations and the technical solutions to address these issues plays a key role in new CMOS technology development. This book aims to provide the reade...

  6. A 94GHz Temperature Compensated Low Noise Amplifier in 45nm Silicon-on-Insulator Complementary Metal-Oxide Semiconductor (SOI CMOS)

    Science.gov (United States)

    2014-01-01

    ring oscillator based temperature sensor will be designed to compensate for gain variations over temperature. For comparison to a competing solution...Simulated (Green) Capacitance of the GSG Pads ........................ 9 Figure 6: Die Picture and Schematic of the L-2L Coplanar Waveguides...complementary metal-oxide-semiconductor (CMOS) technology. A ring oscillator based temperature sensor was designed to compensate for gain variations

  7. A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

    Science.gov (United States)

    Zheng, Hao; Zhu, Zhangming; Ma, Rui

    2017-07-01

    This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35 μm digital technology achieves a THD+N of 0.02% when delivering 400 mW to an 8 {{Ω }} load from {V}{DD}=3.6 {{V}}. The PSRR of the prototype class D amplifier is 80 dB at 217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with V DD range from 2.5 to 4.2 V in mobile application. The total area of the amplifier is 1.7 mm2. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044).

  8. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  9. Poly-SiGe for MEMS-above-CMOS sensors

    CERN Document Server

    Gonzalez Ruiz, Pilar; Witvrouw, Ann

    2014-01-01

    Polycrystalline SiGe has emerged as a promising MEMS (Microelectromechanical Systems) structural material since it provides the desired mechanical properties at lower temperatures compared to poly-Si, allowing the direct post-processing on top of CMOS. This CMOS-MEMS monolithic integration can lead to more compact MEMS with improved performance. The potential of poly-SiGe for MEMS above-aluminum-backend CMOS integration has already been demonstrated. However, aggressive interconnect scaling has led to the replacement of the traditional aluminum metallization by copper (Cu) metallization, due to its lower resistivity and improved reliability. Poly-SiGe for MEMS-above-CMOS sensors demonstrates the compatibility of poly-SiGe with post-processing above the advanced CMOS technology nodes through the successful fabrication of an integrated poly-SiGe piezoresistive pressure sensor, directly fabricated above 0.13 m Cu-backend CMOS. Furthermore, this book presents the first detailed investigation on the influence o...

  10. CMOS dot matrix microdisplay

    Science.gov (United States)

    Venter, Petrus J.; Bogalecki, Alfons W.; du Plessis, Monuko; Goosen, Marius E.; Nell, Ilse J.; Rademeyer, P.

    2011-03-01

    Display technologies always seem to find a wide range of interesting applications. As devices develop towards miniaturization, niche applications for small displays may emerge. While OLEDs and LCDs dominate the market for small displays, they have some shortcomings as relatively expensive technologies. Although CMOS is certainly not the dominating semiconductor for photonics, its widespread use, favourable cost and robustness present an attractive potential if it could find application in the microdisplay environment. Advances in improving the quantum efficiency of avalanche electroluminescence and the favourable spectral characteristics of light generated through the said mechanism may afford CMOS the possibility to be used as a display technology. This work shows that it is possible to integrate a fully functional display in a completely standard CMOS technology mainly geared towards digital design while using light sources completely compatible with the process and without any post processing required.

  11. Lower-power, high-linearity class-AB current-mode programmable gain amplifier

    International Nuclear Information System (INIS)

    Wu Yiqiang; Wang Zhigong; Wang Junliang; Ma Li; Xu Jian; Tang Lu

    2014-01-01

    A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099 μm 2 . The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP 1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range. (semiconductor integrated circuits)

  12. A Fully Reconfigurable Low-Noise Biopotential Sensing Amplifier With 1.96 Noise Efficiency Factor.

    Science.gov (United States)

    Tzu-Yun Wang; Min-Rui Lai; Twigg, Christopher M; Sheng-Yu Peng

    2014-06-01

    A fully reconfigurable biopotential sensing amplifier utilizing floating-gate transistors is presented in this paper. By using the complementary differential pairs along with the current reuse technique, the theoretical limit for the noise efficiency factor of the proposed amplifier is below 1.5. Without consuming any extra power, floating-gate transistors are employed to program the low-frequency cutoff corner of the amplifier and to implement the common-mode feedback. A concept proving prototype chip was designed and fabricated in a 0.35 μm CMOS process occupying 0.17 mm (2) silicon area. With a supply voltage of 2.5 V, the measured midband gain is 40.7 dB and the measured input-referred noise is 2.8 μVrms. The chip was tested under several configurations with the amplifier bandwidth being programmed to 100 Hz, 1 kHz , and 10 kHz. The measured noise efficiency factors in these bandwidth settings are 1.96, 2.01, and 2.25, respectively, which are among the best numbers reported to date. The measured common-mode rejection and the supply rejection are above 70 dB . When the bandwidth is configured to be 10 kHz, the dynamic range measured at 1 kHz is 60 dB with total harmonic distortion less than 0.1%. The proposed amplifier is also demonstrated by recording electromyography (EMG), electrocardiography (ECG), electrooculography (EOG), and electroencephalography (EEG) signals from human bodies.

  13. A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

    Science.gov (United States)

    Quilligan, Gerard T.; Aslam, Shahid; Lakew, Brook; DuMonthier, Jeffery J.; Katz, Richard B.; Kleyner, Igor

    2014-01-01

    Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

  14. On the integration of ultrananocrystalline diamond (UNCD with CMOS chip

    Directory of Open Access Journals (Sweden)

    Hongyi Mi

    2017-03-01

    Full Text Available A low temperature deposition of high quality ultrananocrystalline diamond (UNCD film onto a finished Si-based CMOS chip was performed to investigate the compatibility of the UNCD deposition process with CMOS devices for monolithic integration of MEMS on Si CMOS platform. DC and radio-frequency performances of the individual PMOS and NMOS devices on the CMOS chip before and after the UNCD deposition were characterized. Electrical characteristics of CMOS after deposition of the UNCD film remained within the acceptable ranges, namely showing small variations in threshold voltage Vth, transconductance gm, cut-off frequency fT and maximum oscillation frequency fmax. The results suggest that low temperature UNCD deposition is compatible with CMOS to realize monolithically integrated CMOS-driven MEMS/NEMS based on UNCD.

  15. A CMOS smart temperature and humidity sensor with combined readout.

    Science.gov (United States)

    Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

    2014-09-16

    A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

  16. Fabrication of CMOS-compatible nanopillars for smart bio-mimetic CMOS image sensors

    KAUST Repository

    Saffih, Faycal

    2012-06-01

    In this paper, nanopillars with heights of 1μm to 5μm and widths of 250nm to 500nm have been fabricated with a near room temperature etching process. The nanopillars were achieved with a continuous deep reactive ion etching technique and utilizing PMMA (polymethylmethacrylate) and Chromium as masking layers. As opposed to the conventional Bosch process, the usage of the unswitched deep reactive ion etching technique resulted in nanopillars with smooth sidewalls with a measured surface roughness of less than 40nm. Moreover, undercut was nonexistent in the nanopillars. The proposed fabrication method achieves etch rates four times faster when compared to the state-of-the-art, leading to higher throughput and more vertical side walls. The fabrication of the nanopillars was carried out keeping the CMOS process in mind to ultimately obtain a CMOS-compatible process. This work serves as an initial step in the ultimate objective of integrating photo-sensors based on these nanopillars seamlessly along with the controlling transistors to build a complete bio-inspired smart CMOS image sensor on the same wafer. © 2012 IEEE.

  17. A Standard CMOS Humidity Sensor without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 2 ?W power dissipation, voltage-output, humidity sensor accurate to 5% relative humidity was developed using the LFoundry 0.15 ?m CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a Intervia Photodielectric 8023?10 humidity-sensitive layer, and a CMOS capacitance to voltage converter.

  18. Fully CMOS-compatible titanium nitride nanoantennas

    Energy Technology Data Exchange (ETDEWEB)

    Briggs, Justin A., E-mail: jabriggs@stanford.edu [Department of Applied Physics, Stanford University, 348 Via Pueblo Mall, Stanford, California 94305 (United States); Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Naik, Gururaj V.; Baum, Brian K.; Dionne, Jennifer A. [Department of Materials Science and Engineering, Stanford University, 496 Lomita Mall, Stanford, California 94305 (United States); Petach, Trevor A.; Goldhaber-Gordon, David [Department of Physics, Stanford University, 382 Via Pueblo Mall, Stanford, California 94305 (United States)

    2016-02-01

    CMOS-compatible fabrication of plasmonic materials and devices will accelerate the development of integrated nanophotonics for information processing applications. Using low-temperature plasma-enhanced atomic layer deposition (PEALD), we develop a recipe for fully CMOS-compatible titanium nitride (TiN) that is plasmonic in the visible and near infrared. Films are grown on silicon, silicon dioxide, and epitaxially on magnesium oxide substrates. By optimizing the plasma exposure per growth cycle during PEALD, carbon and oxygen contamination are reduced, lowering undesirable loss. We use electron beam lithography to pattern TiN nanopillars with varying diameters on silicon in large-area arrays. In the first reported single-particle measurements on plasmonic TiN, we demonstrate size-tunable darkfield scattering spectroscopy in the visible and near infrared regimes. The optical properties of this CMOS-compatible material, combined with its high melting temperature and mechanical durability, comprise a step towards fully CMOS-integrated nanophotonic information processing.

  19. A novel pseudo resistor structure for biomedical front-end amplifiers.

    Science.gov (United States)

    Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

    2015-08-01

    This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

  20. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Science.gov (United States)

    Roy, Sukanta; Ramiah, Harikrishnan; Reza, Ahmed Wasif; Lim, Chee Cheow; Ferrer, Eloi Marigo

    2016-01-01

    Micro-electro mechanical system (MEMS) based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C) beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM). A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  1. Design of a MEMS-Based Oscillator Using 180nm CMOS Technology.

    Directory of Open Access Journals (Sweden)

    Sukanta Roy

    Full Text Available Micro-electro mechanical system (MEMS based oscillators are revolutionizing the timing industry as a cost effective solution, enhanced with more features, superior performance and better reliability. The design of a sustaining amplifier was triggered primarily to replenish MEMS resonator's high motion losses due to the possibility of their 'system-on-chip' integrated circuit solution. The design of a sustaining amplifier observing high gain and adequate phase shift for an electrostatic clamp-clamp (C-C beam MEMS resonator, involves the use of an 180nm CMOS process with an unloaded Q of 1000 in realizing a fixed frequency oscillator. A net 122dBΩ transimpedance gain with adequate phase shift has ensured 17.22MHz resonant frequency oscillation with a layout area consumption of 0.121 mm2 in the integrated chip solution, the sustaining amplifier draws 6.3mW with a respective phase noise of -84dBc/Hz at 1kHz offset is achieved within a noise floor of -103dBC/Hz. In this work, a comparison is drawn among similar design studies on the basis of a defined figure of merit (FOM. A low phase noise of 1kHz, high figure of merit and the smaller size of the chip has accredited to the design's applicability towards in the implementation of a clock generative integrated circuit. In addition to that, this complete silicon based MEMS oscillator in a monolithic solution has offered a cost effective solution for industrial or biomedical electronic applications.

  2. An RF Energy Harvester System Using UHF Micropower CMOS Rectifier Based on a Diode Connected CMOS Transistor

    Directory of Open Access Journals (Sweden)

    Mohammad Reza Shokrani

    2014-01-01

    Full Text Available This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18 μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier’s output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  3. An RF energy harvester system using UHF micropower CMOS rectifier based on a diode connected CMOS transistor.

    Science.gov (United States)

    Shokrani, Mohammad Reza; Khoddam, Mojtaba; Hamidon, Mohd Nizar B; Kamsani, Noor Ain; Rokhani, Fakhrul Zaman; Shafie, Suhaidi Bin

    2014-01-01

    This paper presents a new type diode connected MOS transistor to improve CMOS conventional rectifier's performance in RF energy harvester systems for wireless sensor networks in which the circuits are designed in 0.18  μm TSMC CMOS technology. The proposed diode connected MOS transistor uses a new bulk connection which leads to reduction in the threshold voltage and leakage current; therefore, it contributes to increment of the rectifier's output voltage, output current, and efficiency when it is well important in the conventional CMOS rectifiers. The design technique for the rectifiers is explained and a matching network has been proposed to increase the sensitivity of the proposed rectifier. Five-stage rectifier with a matching network is proposed based on the optimization. The simulation results shows 18.2% improvement in the efficiency of the rectifier circuit and increase in sensitivity of RF energy harvester circuit. All circuits are designed in 0.18 μm TSMC CMOS technology.

  4. Neutron absorbed dose in a pacemaker CMOS

    Energy Technology Data Exchange (ETDEWEB)

    Borja H, C. G.; Guzman G, K. A.; Valero L, C. Y.; Banuelos F, A.; Hernandez D, V. M.; Vega C, H. R. [Universidad Autonoma de Zacatecas, Unidad Academica de Estudios Nucleares, Calle Cipres No. 10, Fracc. La Penuela, 98068 Zacatecas (Mexico); Paredes G, L., E-mail: candy_borja@hotmail.com [ININ, Carretera Mexico-Toluca s/n, 52750 Ocoyoacac, Estado de Mexico (Mexico)

    2011-11-15

    The absorbed dose due to neutrons by a Complementary Metal Oxide Semiconductor (CMOS) has been estimated using Monte Carlo methods. Eventually a person with a pacemaker becomes a patient that must be treated by radiotherapy with a linear accelerator; the pacemaker has integrated circuits as CMOS that are sensitive to intense and pulsed radiation fields. When the Linac is working in Bremsstrahlung mode an undesirable neutron field is produced due to photoneutron reactions; these neutrons could damage the CMOS putting the patient at risk during the radiotherapy treatment. In order to estimate the neutron dose in the CMOS a Monte Carlo calculation was carried out where a full radiotherapy vault room was modeled with a W-made spherical shell in whose center was located the source term of photoneutrons produced by a Linac head operating in Bremsstrahlung mode at 18 MV. In the calculations a phantom made of tissue equivalent was modeled while a beam of photoneutrons was applied on the phantom prostatic region using a field of 10 x 10 cm{sup 2}. During simulation neutrons were isotropically transported from the Linac head to the phantom chest, here a 1 {theta} x 1 cm{sup 2} cylinder made of polystyrene was modeled as the CMOS, where the neutron spectrum and the absorbed dose were estimated. Main damages to CMOS are by protons produced during neutron collisions protective cover made of H-rich materials, here the neutron spectrum that reach the CMOS was calculated showing a small peak around 0.1 MeV and a larger peak in the thermal region, both connected through epithermal neutrons. (Author)

  5. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  6. Investigation on thermodynamics of ion-slicing of GaN and heterogeneously integrating high-quality GaN films on CMOS compatible Si(100) substrates.

    Science.gov (United States)

    Huang, Kai; Jia, Qi; You, Tiangui; Zhang, Runchun; Lin, Jiajie; Zhang, Shibin; Zhou, Min; Zhang, Bo; Yu, Wenjie; Ou, Xin; Wang, Xi

    2017-11-08

    Die-to-wafer heterogeneous integration of single-crystalline GaN film with CMOS compatible Si(100) substrate using the ion-cutting technique has been demonstrated. The thermodynamics of GaN surface blistering is in-situ investigated via a thermal-stage optical microscopy, which indicates that the large activation energy (2.5 eV) and low H ions utilization ratio (~6%) might result in the extremely high H fluence required for the ion-slicing of GaN. The crystalline quality, surface topography and the microstructure of the GaN films are characterized in detail. The full width at half maximum (FWHM) for GaN (002) X-ray rocking curves is as low as 163 arcsec, corresponding to a density of threading dislocation of 5 × 10 7  cm -2 . Different evolution of the implantation-induced damage was observed and a relationship between the damage evolution and implantation-induced damage is demonstrated. This work would be beneficial to understand the mechanism of ion-slicing of GaN and to provide a platform for the hybrid integration of GaN devices with standard Si CMOS process.

  7. Integrated Circuit Design of 3 Electrode Sensing System Using Two-Stage Operational Amplifier

    Science.gov (United States)

    Rani, S.; Abdullah, W. F. H.; Zain, Z. M.; N, Aqmar N. Z.

    2018-03-01

    This paper presents the design of a two-stage operational amplifier(op amp) for 3-electrode sensing system readout circuits. The designs have been simulated using 0.13μm CMOS technology from Silterra (Malaysia) with Mentor graphics tools. The purpose of this projects is mainly to design a miniature interfacing circuit to detect the redox reaction in the form of current using standard analog modules. The potentiostat consists of several op amps combined together in order to analyse the signal coming from the 3-electrode sensing system. This op amp design will be used in potentiostat circuit device and to analyse the functionality for each module of the system.

  8. Biostability of an implantable glucose sensor chip

    Science.gov (United States)

    Fröhlich, M.; Birkholz, M.; Ehwald, K. E.; Kulse, P.; Fursenko, O.; Katzer, J.

    2012-12-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and Ra roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  9. Biostability of an implantable glucose sensor chip

    International Nuclear Information System (INIS)

    Fröhlich, M; Ehwald, K E; Kulse, P; Fursenko, O; Katzer, J; Birkholz, M

    2012-01-01

    Surface materials of an implantable microelectronic chip intended for medical applications were evaluated with respect to their long-term stability in bio-environments. The sensor chip shall apply in a glucose monitor by operating as a microviscosimeter according to the principle of affinity viscosimetry. A monolithic integration of a microelectromechanical system (MEMS) into the sensor chip was successfully performed in a combined 0.25 μm CMOS/BiCMOS technology. In order to study material durability and biostability of the surfaces, sensor chips were exposed to various in vitro and in vivo tests. Corrosional damage of SiON, SiO 2 and TiN surfaces was investigated by optical microscopy, ellipsometry and AFM. The results served for optimizing the Back-end-of-Line (BEoL) stack, from which the MEMS was prepared. Corrosion of metal lines could significantly be reduced by improving the topmost passivation layer. The experiments revealed no visible damage of the actuator or other functionally important MEMS elements. Sensor chips were also exposed to human body fluid for three month by implantation into the abdomen of a volunteer. Only small effects were observed for layer thickness and R a roughness after explantation. In particular, TiN as used for the actuator beam showed no degradation by biocorrosion. The highest degradation rate of about 50 nm per month was revealed for the SiON passivation layer. These results suggest that the sensor chip may safely operate in subcutaneous tissue for a period of several months.

  10. CMOS-sensors for energy-resolved X-ray imaging

    International Nuclear Information System (INIS)

    Doering, D.; Amar-Youcef, S.; Deveaux, M.; Linnik, B.; Müntz, C.; Stroth, Joachim; Baudot, J.; Dulinski, W.; Kachel, M.

    2016-01-01

    Due to their low noise, CMOS Monolithic Active Pixel Sensors are suited to sense X-rays with a few keV quantum energy, which is of interest for high resolution X-ray imaging. Moreover, the good energy resolution of the silicon sensors might be used to measure this quantum energy. Combining both features with the good spatial resolution of CMOS sensors opens the potential to build ''color sensitive' X-ray cameras. Taking such colored images is hampered by the need to operate the CMOS sensors in a single photon counting mode, which restricts the photon flux capability of the sensors. More importantly, the charge sharing between the pixels smears the potentially good energy resolution of the sensors. Based on our experience with CMOS sensors for charged particle tracking, we studied techniques to overcome the latter by means of an offline processing of the data obtained from a CMOS sensor prototype. We found that the energy resolution of the pixels can be recovered at the expense of reduced quantum efficiency. We will introduce the results of our study and discuss the feasibility of taking colored X-ray pictures with CMOS sensors

  11. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    International Nuclear Information System (INIS)

    Luo Yanbin; Ma Chengyan; Gan Yebing; Qian Min; Ye Tianchun

    2015-01-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm 2 . (paper)

  12. A 200 mA CMOS low-dropout regulator with double frequency compensation techniques for SoC applications

    International Nuclear Information System (INIS)

    Lei Qianqian; Chen Zhiming; Gong Zheng; Shi Yin

    2011-01-01

    This paper presents a 200 mA low-dropout (LDO) linear regulator using two modified techniques for frequency compensation. One technique is that the error amplifier uses a common source stage with variable load, which is controlled by the output current, is served as the second stage for a stable frequency response. The other technique is that the LDO uses a pole-zero tracking compensation technique at the error amplifier to achieve a good frequency response. The proposed circuit was fabricated and tested in HJTC 0.18 μm CMOS technology. The designed LDO linear regulator works under the input voltage of 2.8–5 V and provides up to 200 mA load current for an output voltage of 1.8 V. The total error of the output voltage due to line and load variation is less than 0.015%. The LDO die area is 630 × 550 μm 2 and the quiescent current is 130 μA. (semiconductor integrated circuits)

  13. An integrated 12.5-Gb/s optoelectronic receiver with a silicon avalanche photodetector in standard SiGe BiCMOS technology.

    Science.gov (United States)

    Youn, Jin-Sung; Lee, Myung-Jae; Park, Kang-Yeob; Rücker, Holger; Choi, Woo-Young

    2012-12-17

    An optoelectronic integrated circuit (OEIC) receiver is realized with standard 0.25-μm SiGe BiCMOS technology for 850-nm optical interconnect applications. The OEIC receiver consists of a Si avalanche photodetector, a transimpedance amplifier with a DC-balanced buffer, a tunable equalizer, and a limiting amplifier. The fabricated OEIC receiver successfully detects 12.5-Gb/s 2(31)-1 pseudorandom bit sequence optical data with the bit-error rate less than 10(-12) at incident optical power of -7 dBm. The OEIC core has 1000 μm x 280 μm chip area, and consumes 59 mW from 2.5-V supply. To the best of our knowledge, this OEIC receiver achieves the highest data rate with the smallest sensitivity as well as the best power efficiency among integrated OEIC receivers fabricated with standard Si technology.

  14. High-speed nonvolatile CMOS/MNOS RAM

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Dodson, W.D.; Sokel, R.J.

    1979-01-01

    A bulk silicon technology for a high-speed static CMOS/MNOS RAM has been developed. Radiation-hardened, high voltage CMOS circuits have been fabricated for the memory array driving circuits and the enhancement-mode p-channel MNOS memory transistors have been fabricated using a native tunneling oxide with a 45 nm CVD Si 3 N 4 insulator deposited at 750 0 C. Read cycle times less than 350 ns and write cycle times of 1 μs are projected for the final 1Kx1 design. The CMOS circuits provide adequate speed for the write and read cycles and minimize the standby power dissipation. Retention times well in excess of 30 min are projected

  15. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  16. JPL CMOS Active Pixel Sensor Technology

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    This paper will present the JPL-developed complementary metal- oxide-semiconductor (CMOS) active pixel sensor (APS) technology. The CMOS APS has achieved performance comparable to charge coupled devices, yet features ultra low power operation, random access readout, on-chip timing and control, and on-chip analog to digital conversion. Previously published open literature will be reviewed.

  17. NINO An ultra-fast and low-power front-end amplifier/discriminator ASIC designed for the multigap resistive plate chamber

    CERN Document Server

    Anghinolfi, F; Martemyanov, A N; Usenko, E; Wenninger, Horst; Williams, M C S; Zichichi, A

    2004-01-01

    For the full exploitation of the excellent timing properties of the Multigap Resistive Plate Chamber (MRPC), front-end electronics with special characteristics are needed. These are (a) differential input, to profit from the differential signal from the MRPC (b) a fast amplifier with less than 1 ns peaking time and (c) input charge measurement by Time-Over-Threshold for slewing correction. An 8- channel amplifier and discriminator chip has been developed to match these requirements. This is the NINO ASIC, fabricated with 0.25 omegam CMOS technology. The power requirement at 40mW/channel is low. Results on the performance of the MRPCs using the NINO ASIC are presented. Typical time resolution a of the MRPC system is in the 50 ps range, with an efficiency of 99.9%.

  18. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.; Sevilla, Galo T.; Ghoneim, Mohamed T.; Hussain, Muhammad Mustafa

    2014-01-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due

  19. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa

    2017-11-23

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications. While there exist bulk material reduction methods to flex them, such thinned CMOS electronics are fragile and vulnerable to handling for high throughput manufacturing. Here, we show a fusion of a CMOS technology compatible fabrication process for flexible CMOS electronics, with inkjet and conductive cellulose based interconnects, followed by additive manufacturing (i.e. 3D printing based packaging) and finally roll-to-roll printing of packaged decal electronics (thin film transistors based circuit components and sensors) focusing on printed high performance flexible electronic systems. This work provides the most pragmatic route for packaged flexible electronic systems for wide ranging applications.

  20. Batch Processing of CMOS Compatible Feedthroughs

    DEFF Research Database (Denmark)

    Rasmussen, F.E.; Heschel, M.; Hansen, Ole

    2003-01-01

    . The feedthrough technology employs a simple solution to the well-known CMOS compatibility issue of KOH by protecting the CMOS side of the wafer using sputter deposited TiW/Au. The fabricated feedthroughs exhibit excellent electrical performance having a serial resistance of 40 mOmega and a parasitic capacitance...... of 2.5 pF. (C) 2003 Elsevier Science B.V. All rights reserved....

  1. Technology CAD for germanium CMOS circuit

    Energy Technology Data Exchange (ETDEWEB)

    Saha, A.R. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)]. E-mail: ars.iitkgp@gmail.com; Maiti, C.K. [Department of Electronics and ECE, IIT Kharagpur, Kharagpur-721302 (India)

    2006-12-15

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f {sub T} of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted.

  2. Technology CAD for germanium CMOS circuit

    International Nuclear Information System (INIS)

    Saha, A.R.; Maiti, C.K.

    2006-01-01

    Process simulation for germanium MOSFETs (Ge-MOSFETs) has been performed in 2D SILVACO virtual wafer fabrication (VWF) suite towards the technology CAD for Ge-CMOS process development. Material parameters and mobility models for Germanium were incorporated in simulation via C-interpreter function. We also report on the device design issues along with the DC and RF characterization of the bulk Ge-MOSFETs, AC parameter extraction and circuit simulation of Ge-CMOS. Simulation results are compared with bulk-Si devices. Simulations predict a cut-off frequency, f T of about 175 GHz for Ge-MOSFETs compared to 70 GHz for a similar gate-length Si MOSFET. For a single stage Ge-CMOS inverter circuit, a GATE delay of 0.6 ns is predicted

  3. Resistor Extends Life Of Battery In Clocked CMOS Circuit

    Science.gov (United States)

    Wells, George H., Jr.

    1991-01-01

    Addition of fixed resistor between battery and clocked complementary metal oxide/semiconductor (CMOS) circuit reduces current drawn from battery. Basic idea to minimize current drawn from battery by operating CMOS circuit at lowest possible current consistent with use of simple, fixed off-the-shelf components. Prolongs lives of batteries in such low-power CMOS circuits as watches and calculators.

  4. Carbon Nanotube Integration with a CMOS Process

    Science.gov (United States)

    Perez, Maximiliano S.; Lerner, Betiana; Resasco, Daniel E.; Pareja Obregon, Pablo D.; Julian, Pedro M.; Mandolesi, Pablo S.; Buffa, Fabian A.; Boselli, Alfredo; Lamagna, Alberto

    2010-01-01

    This work shows the integration of a sensor based on carbon nanotubes using CMOS technology. A chip sensor (CS) was designed and manufactured using a 0.30 μm CMOS process, leaving a free window on the passivation layer that allowed the deposition of SWCNTs over the electrodes. We successfully investigated with the CS the effect of humidity and temperature on the electrical transport properties of SWCNTs. The possibility of a large scale integration of SWCNTs with CMOS process opens a new route in the design of more efficient, low cost sensors with high reproducibility in their manufacture. PMID:22319330

  5. CARIOCA : A Fast Binary Front-End Implemented in 0.25Pm CMOS using a Novel Current-Mode Technique for the LHCb Muon Detector

    CERN Multimedia

    2000-01-01

    The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF.

  6. Depleted CMOS pixels for LHC proton–proton experiments

    International Nuclear Information System (INIS)

    Wermes, N.

    2016-01-01

    While so far monolithic pixel detectors have remained in the realm of comparatively low rate and radiation applications outside LHC, new developments exploiting high resistivity substrates with three or four well CMOS process options allow reasonably large depletion depths and full CMOS circuitry in a monolithic structure. This opens up the possibility to target CMOS pixel detectors also for high radiation pp-experiments at the LHC upgrade, either in a hybrid-type fashion or even fully monolithic. Several pixel matrices have been prototyped with high ohmic substrates, high voltage options, and full CMOS electronics. They were characterized in the lab and in test beams. An overview of the necessary development steps and different approaches as well as prototype results are presented in this paper.

  7. Single photon detection and localization accuracy with an ebCMOS camera

    Energy Technology Data Exchange (ETDEWEB)

    Cajgfinger, T. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Dominjon, A., E-mail: agnes.dominjon@nao.ac.jp [Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France); Barbier, R. [CNRS/IN2P3, Institut de Physique Nucléaire de Lyon, Villeurbanne F-69622 (France); Université de Lyon, Université de Lyon 1, Lyon 69003 France. (France)

    2015-07-01

    The CMOS sensor technologies evolve very fast and offer today very promising solutions to existing issues facing by imaging camera systems. CMOS sensors are very attractive for fast and sensitive imaging thanks to their low pixel noise (1e-) and their possibility of backside illumination. The ebCMOS group of IPNL has produced a camera system dedicated to Low Light Level detection and based on a 640 kPixels ebCMOS with its acquisition system. After reminding the principle of detection of an ebCMOS and the characteristics of our prototype, we confront our camera to other imaging systems. We compare the identification efficiency and the localization accuracy of a point source by four different photo-detection devices: the scientific CMOS (sCMOS), the Charge Coupled Device (CDD), the Electron Multiplying CCD (emCCD) and the Electron Bombarded CMOS (ebCMOS). Our ebCMOS camera is able to identify a single photon source in less than 10 ms with a localization accuracy better than 1 µm. We report as well efficiency measurement and the false positive identification of the ebCMOS camera by identifying more than hundreds of single photon sources in parallel. About 700 spots are identified with a detection efficiency higher than 90% and a false positive percentage lower than 5. With these measurements, we show that our target tracking algorithm can be implemented in real time at 500 frames per second under a photon flux of the order of 8000 photons per frame. These results demonstrate that the ebCMOS camera concept with its single photon detection and target tracking algorithm is one of the best devices for low light and fast applications such as bioluminescence imaging, quantum dots tracking or adaptive optics.

  8. Broadband image sensor array based on graphene-CMOS integration

    Science.gov (United States)

    Goossens, Stijn; Navickaite, Gabriele; Monasterio, Carles; Gupta, Shuchi; Piqueras, Juan José; Pérez, Raúl; Burwell, Gregory; Nikitskiy, Ivan; Lasanta, Tania; Galán, Teresa; Puma, Eric; Centeno, Alba; Pesquera, Amaia; Zurutuza, Amaia; Konstantatos, Gerasimos; Koppens, Frank

    2017-06-01

    Integrated circuits based on complementary metal-oxide-semiconductors (CMOS) are at the heart of the technological revolution of the past 40 years, enabling compact and low-cost microelectronic circuits and imaging systems. However, the diversification of this platform into applications other than microcircuits and visible-light cameras has been impeded by the difficulty to combine semiconductors other than silicon with CMOS. Here, we report the monolithic integration of a CMOS integrated circuit with graphene, operating as a high-mobility phototransistor. We demonstrate a high-resolution, broadband image sensor and operate it as a digital camera that is sensitive to ultraviolet, visible and infrared light (300-2,000 nm). The demonstrated graphene-CMOS integration is pivotal for incorporating 2D materials into the next-generation microelectronics, sensor arrays, low-power integrated photonics and CMOS imaging systems covering visible, infrared and terahertz frequencies.

  9. CMOS Cell Sensors for Point-of-Care Diagnostics

    Science.gov (United States)

    Adiguzel, Yekbun; Kulah, Haluk

    2012-01-01

    The burden of health-care related services in a global era with continuously increasing population and inefficient dissipation of the resources requires effective solutions. From this perspective, point-of-care diagnostics is a demanded field in clinics. It is also necessary both for prompt diagnosis and for providing health services evenly throughout the population, including the rural districts. The requirements can only be fulfilled by technologies whose productivity has already been proven, such as complementary metal-oxide-semiconductors (CMOS). CMOS-based products can enable clinical tests in a fast, simple, safe, and reliable manner, with improved sensitivities. Portability due to diminished sensor dimensions and compactness of the test set-ups, along with low sample and power consumption, is another vital feature. CMOS-based sensors for cell studies have the potential to become essential counterparts of point-of-care diagnostics technologies. Hence, this review attempts to inform on the sensors fabricated with CMOS technology for point-of-care diagnostic studies, with a focus on CMOS image sensors and capacitance sensors for cell studies. PMID:23112587

  10. CMOS capacitive sensors for lab-on-chip applications a multidisciplinary approach

    CERN Document Server

    Ghafar-Zadeh, Ebrahim

    2010-01-01

    The main components of CMOS capacitive biosensors including sensing electrodes, bio-functionalized sensing layer, interface circuitries and microfluidic packaging are verbosely explained in chapters 2-6 after a brief introduction on CMOS based LoCs in Chapter 1. CMOS Capacitive Sensors for Lab-on-Chip Applications is written in a simple pedagogical way. It emphasises practical aspects of fully integrated CMOS biosensors rather than mathematical calculations and theoretical details. By using CMOS Capacitive Sensors for Lab-on-Chip Applications, the reader will have circuit design methodologies,

  11. Middle ear implants

    Directory of Open Access Journals (Sweden)

    K S Gangadhara Somayaji

    2013-01-01

    Full Text Available Hearing loss is becoming more common in the society living in cities with lot of background noise around, and frequent use of gadgets like mobile phones, MP3s, and IPods are adding to the problem. The loss may involve the conductive or perceptive pathway. Majority of the patients with conductive hearing loss will revert back to normal hearing levels with medical and/or surgical treatment. However, in sensorineural hearing loss, many factors are involved in the management. Though traditionally hearing aids in various forms are the most commonly used modality in managing these patients, there are some drawbacks associated with them. Implantable middle ear amplifiers represent the most recent breakthrough in the management of hearing loss. Middle ear implants are surgically implanted electronic devices that aim to correct hearing loss by stimulating the ossicular chain or middle ear. Of late, they are also being used in the management of congenital conductive hearing loss and certain cases of chronic otitis media with residual hearing loss. The article aims to provide general information about the technology, indications and contraindications, selection of candidates, available systems, and advantages of middle ear implants. (MEI

  12. CMOS Image Sensor and System for Imaging Hemodynamic Changes in Response to Deep Brain Stimulation.

    Science.gov (United States)

    Zhang, Xiao; Noor, Muhammad S; McCracken, Clinton B; Kiss, Zelma H T; Yadid-Pecht, Orly; Murari, Kartikeya

    2016-06-01

    Deep brain stimulation (DBS) is a therapeutic intervention used for a variety of neurological and psychiatric disorders, but its mechanism of action is not well understood. It is known that DBS modulates neural activity which changes metabolic demands and thus the cerebral circulation state. However, it is unclear whether there are correlations between electrophysiological, hemodynamic and behavioral changes and whether they have any implications for clinical benefits. In order to investigate these questions, we present a miniaturized system for spectroscopic imaging of brain hemodynamics. The system consists of a 144 ×144, [Formula: see text] pixel pitch, high-sensitivity, analog-output CMOS imager fabricated in a standard 0.35 μm CMOS process, along with a miniaturized imaging system comprising illumination, focusing, analog-to-digital conversion and μSD card based data storage. This enables stand alone operation without a computer, nor electrical or fiberoptic tethers. To achieve high sensitivity, the pixel uses a capacitive transimpedance amplifier (CTIA). The nMOS transistors are in the pixel while pMOS transistors are column-parallel, resulting in a fill factor (FF) of 26%. Running at 60 fps and exposed to 470 nm light, the CMOS imager has a minimum detectable intensity of 2.3 nW/cm(2) , a maximum signal-to-noise ratio (SNR) of 49 dB at 2.45 μW/cm(2) leading to a dynamic range (DR) of 61 dB while consuming 167 μA from a 3.3 V supply. In anesthetized rats, the system was able to detect temporal, spatial and spectral hemodynamic changes in response to DBS.

  13. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  14. CMOS MEMS capacitive absolute pressure sensor

    International Nuclear Information System (INIS)

    Narducci, M; Tsai, J; Yu-Chia, L; Fang, W

    2013-01-01

    This paper presents the design, fabrication and characterization of a capacitive pressure sensor using a commercial 0.18 µm CMOS (complementary metal–oxide–semiconductor) process and postprocess. The pressure sensor is capacitive and the structure is formed by an Al top electrode enclosed in a suspended SiO 2 membrane, which acts as a movable electrode against a bottom or stationary Al electrode fixed on the SiO 2 substrate. Both the movable and fixed electrodes form a variable parallel plate capacitor, whose capacitance varies with the applied pressure on the surface. In order to release the membranes the CMOS layers need to be applied postprocess and this mainly consists of four steps: (1) deposition and patterning of PECVD (plasma-enhanced chemical vapor deposition) oxide to protect CMOS pads and to open the pressure sensor top surface, (2) etching of the sacrificial layer to release the suspended membrane, (3) deposition of PECVD oxide to seal the etching holes and creating vacuum inside the gap, and finally (4) etching of the passivation oxide to open the pads and allow electrical connections. This sensor design and fabrication is suitable to obey the design rules of a CMOS foundry and since it only uses low-temperature processes, it allows monolithic integration with other types of CMOS compatible sensors and IC (integrated circuit) interface on a single chip. Experimental results showed that the pressure sensor has a highly linear sensitivity of 0.14 fF kPa −1 in the pressure range of 0–300 kPa. (paper)

  15. A 10 MHz micropower CMOS front end for direct readout of pixel detectors

    International Nuclear Information System (INIS)

    Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

    1990-01-01

    In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

  16. CMOS integrated avalanche photodiodes and frequency-mixing optical sensor front end for portable NIR spectroscopy instruments.

    Science.gov (United States)

    Yun, Ruida; Sthalekar, Chirag; Joyner, Valencia M

    2011-01-01

    This paper presents the design and measurement results of two avalanche photodiode structures (APDs) and a novel frequency-mixing transimpedance amplifier (TIA), which are key building blocks towards a monolithically integrated optical sensor front end for near-infrared (NIR) spectroscopy applications. Two different APD structures are fabricated in an unmodified 0.18 \\im CMOS process, one with a shallow trench isolation (STI) guard ring and the other with a P-well guard ring. The APDs are characterized in linear mode. The STI bounded APD demonstrates better performance and exhibits 3.78 A/W responsivity at a wavelength of 690 nm and bias voltage of 10.55 V. The frequency-mixing TIA (FM-TIA) employs a T-feedback network incorporating gate-controlled transistors for resistance modulation, enabling the simultaneous down-conversion and amplification of the high frequency modulated photodiode (PD) current. The TIA achieves 92 dS Ω conversion gain with 0.5 V modulating voltage. The measured IIP(3) is 10.6/M. The amplifier together with the 50 Ω output buffer draws 23 mA from a1.8 V power supply.

  17. A sub-nJ CMOS ECG classifier for wireless smart sensor.

    Science.gov (United States)

    Chollet, Paul; Pallas, Remi; Lahuec, Cyril; Arzel, Matthieu; Seguin, Fabrice

    2017-07-01

    Body area sensor networks hold the promise of more efficient and cheaper medical care services through the constant monitoring of physiological markers such as heart beats. Continuously transmitting the electrocardiogram (ECG) signal requires most of the wireless ECG sensor energy budget. This paper presents the analog implantation of a classifier for ECG signals that can be embedded onto a sensor. The classifier is a sparse neural associative memory. It is implemented using the ST 65 nm CMOS technology and requires only 234 pJ per classification while achieving a 93.6% classification accuracy. The energy requirement is 6 orders of magnitude lower than a digital accelerator that performs a similar task. The lifespan of the resulting sensor is 191 times as large as that of a sensor sending all the data.

  18. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  19. A low power 3-5 GHz CMOS UWB receiver front-end

    International Nuclear Information System (INIS)

    Li Weinan; Huang Yumei; Hong Zhiliang

    2009-01-01

    A novel low power RF receiver front-end for 3-5 GHz UWB is presented. Designed in the 0.13 μm CMOS process, the direct conversion receiver features a wideband balun-coupled noise cancelling transconductance input stage, followed by quadrature passive mixers and transimpedance loading amplifiers. Measurement results show that the receiver achieves an input return loss below -8.5 dB across the 3.1-4.7 GHz frequency range, maximum voltage conversion gain of 27 dB, minimum noise figure of 4 dB, IIP3 of -11.5 dBm, and IIP2 of 33 dBm. Working under 1.2 V supply voltage, the receiver consumes total current of 18 mA including 10 mA by on-chip quadrature LO signal generation and buffer circuits. The chip area with pads is 1.1 x 1.5 mm 2 .

  20. Design of a multi-axis implantable MEMS sensor for intraosseous bone stress monitoring

    International Nuclear Information System (INIS)

    Alfaro, Fernando; Weiss, Lee; Campbell, Phil; Fedder, Gary K; Miller, Mark

    2009-01-01

    The capability to assess the biomechanical properties of living bone is important for basic research as well as the clinical management of skeletal trauma and disease. Even though radiodensitometric imaging is commonly used to infer bone quality, bone strength does not necessarily correlate well with these non-invasive measurements. This paper reports on the design, fabrication and initial testing of an implantable ultra-miniature multi-axis sensor for directly measuring bone stresses at a micro-scale. The device, which is fabricated with CMOS-MEMS processes, is intended to be permanently implanted within open fractures, or embedded in bone grafts, or placed on implants at the interfaces between bone and prosthetics. The stress sensor comprises an array of piezoresistive pixels to detect a stress tensor at the interfacial area between the MEMS chip and bone, with a resolution to 100 Pa, in 1 s averaging. The sensor system design and manufacture is also compatible with the integration of wireless RF telemetry, for power and data retrieval, all within a 3 mm × 3 mm × 0.3 mm footprint. The piezoresistive elements are integrated within a textured surface to enhance sensor integration with bone. Finite element analysis led to a sensor design for normal and shear stress detection. A wired sensor was fabricated in the Jazz 0.35 µm BiCMOS process and then embedded in mock bone material to characterize its response to tensile and bending loads up to 250 kPa

  1. A Single-Transistor Active Pixel CMOS Image Sensor Architecture

    International Nuclear Information System (INIS)

    Zhang Guo-An; He Jin; Zhang Dong-Wei; Su Yan-Mei; Wang Cheng; Chen Qin; Liang Hai-Lang; Ye Yun

    2012-01-01

    A single-transistor CMOS active pixel image sensor (1 T CMOS APS) architecture is proposed. By switching the photosensing pinned diode, resetting and selecting can be achieved by diode pull-up and capacitive coupling pull-down of the source follower. Thus, the reset and selected transistors can be removed. In addition, the reset and selected signal lines can be shared to reduce the metal signal line, leading to a very high fill factor. The pixel design and operation principles are discussed in detail. The functionality of the proposed 1T CMOS APS architecture has been experimentally verified using a fabricated chip in a standard 0.35 μm CMOS AMIS technology

  2. Testing methodologies and systems for semiconductor optical amplifiers

    Science.gov (United States)

    Wieckowski, Michael

    Semiconductor optical amplifiers (SOA's) are gaining increased prominence in both optical communication systems and high-speed optical processing systems, due primarily to their unique nonlinear characteristics. This in turn, has raised questions regarding their lifetime performance reliability and has generated a demand for effective testing techniques. This is especially critical for industries utilizing SOA's as components for system-in-package products. It is important to note that very little research to date has been conducted in this area, even though production volume and market demand has continued to increase. In this thesis, the reliability of dilute-mode InP semiconductor optical amplifiers is studied experimentally and theoretically. The aging characteristics of the production level devices are demonstrated and the necessary techniques to accurately characterize them are presented. In addition, this work proposes a new methodology for characterizing the optical performance of these devices using measurements in the electrical domain. It is shown that optical performance degradation, specifically with respect to gain, can be directly qualified through measurements of electrical subthreshold differential resistance. This metric exhibits a linear proportionality to the defect concentration in the active region, and as such, can be used for prescreening devices before employing traditional optical testing methods. A complete theoretical analysis is developed in this work to explain this relationship based upon the device's current-voltage curve and its associated leakage and recombination currents. These results are then extended to realize new techniques for testing semiconductor optical amplifiers and other similarly structured devices. These techniques can be employed after fabrication and during packaged operation through the use of a proposed stand-alone testing system, or using a proposed integrated CMOS self-testing circuit. Both methods are capable

  3. Self-calibrated humidity sensor in CMOS without post-processing.

    Science.gov (United States)

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2012-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  4. Self-Calibrated Humidity Sensor in CMOS without Post-Processing

    OpenAIRE

    Nizhnik, Oleg; Higuchi, Kohei; Maenaka, Kazusuke

    2011-01-01

    A 1.1 μW power dissipation, voltage-output humidity sensor with 10% relative humidity accuracy was developed in the LFoundry 0.15 μm CMOS technology without post-processing. The sensor consists of a woven lateral array of electrodes implemented in CMOS top metal, a humidity-sensitive layer of Intervia Photodielectric 8023D-10, a CMOS capacitance to voltage converter, and the self-calibration circuitry.

  5. Fiber Amplifiers

    DEFF Research Database (Denmark)

    Rottwitt, Karsten

    2017-01-01

    The chapter provides a discussion of optical fiber amplifiers and through three sections provides a detailed treatment of three types of optical fiber amplifiers, erbium doped fiber amplifiers (EDFA), Raman amplifiers, and parametric amplifiers. Each section comprises the fundamentals including...... the basic physics and relevant in-depth theoretical modeling, amplifiers characteristics and performance data as a function of specific operation parameters. Typical applications in fiber optic communication systems and the improvement achievable through the use of fiber amplifiers are illustrated....

  6. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 {mu}m CMOS process

    Energy Technology Data Exchange (ETDEWEB)

    Wang Jingchao; Zhang Chun; Wang Zhihua, E-mail: wangjc@gmail.co [Institute of Microelectronics, Tsinghua University, Beijing 100084 (China)

    2010-08-15

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 {mu}m CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm{sup 2} including pads. (semiconductor integrated circuits)

  7. A fully integrated UHF RFID reader SoC for handheld applications in the 0.18 μm CMOS process

    International Nuclear Information System (INIS)

    Wang Jingchao; Zhang Chun; Wang Zhihua

    2010-01-01

    A low cost fully integrated single-chip UHF radio frequency identification (RFID) reader SoC for short distance handheld applications is presented. The SoC integrates all building blocks-including an RF transceiver, a PLL frequency synthesizer, a digital baseband and an MCU-in a 0.18 μm CMOS process. A high-linearity RX front-end is designed to handle the large self-interferer. A class-E power amplifier with high power efficiency is also integrated to fulfill the function of a UHF passive RFID reader. The measured maximum output power of the transmitter is 20.28 dBm and the measured receiver sensitivity is -60 dBm. The digital baseband including MCU core consumes 3.91 mW with a clock of 10 MHz and the analog part including power amplifier consumes 368.4 mW. The chip has a die area of 5.1 x 3.8 mm 2 including pads. (semiconductor integrated circuits)

  8. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  9. Radiation-hardened bulk CMOS technology

    International Nuclear Information System (INIS)

    Dawes, W.R. Jr.; Habing, D.H.

    1979-01-01

    The evolutionary development of a radiation-hardened bulk CMOS technology is reviewed. The metal gate hardened CMOS status is summarized, including both radiation and reliability data. The development of a radiation-hardened bulk silicon gate process which was successfully implemented to a commercial microprocessor family and applied to a new, radiation-hardened, LSI standard cell family is also discussed. The cell family is reviewed and preliminary characterization data is presented. Finally, a brief comparison of the various radiation-hardened technologies with regard to performance, reliability, and availability is made

  10. CMOS/SOS processing

    Science.gov (United States)

    Ramondetta, P.

    1980-01-01

    Report describes processes used in making complementary - metal - oxide - semiconductor/silicon-on-sapphire (CMOS/SOS) integrated circuits. Report lists processing steps ranging from initial preparation of sapphire wafers to final mapping of "good" and "bad" circuits on a wafer.

  11. CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology

    Directory of Open Access Journals (Sweden)

    Jose Luis Muñoz-Gamarra

    2016-02-01

    Full Text Available This work demonstrates the feasibility to obtain copper nanoelectromechanical (NEMS relays using a commercial complementary metal oxide semiconductor (CMOS technology (ST 65 nm following an intra CMOS-MEMS approach. We report experimental demonstration of contact-mode nano-electromechanical switches obtaining low operating voltage (5.5 V, good ION/IOFF (103 ratio, abrupt subthreshold swing (4.3 mV/decade and minimum dimensions (3.50 μm × 100 nm × 180 nm, and gap of 100 nm. With these dimensions, the operable Cell area of the switch will be 3.5 μm (length × 0.2 μm (100 nm width + 100 nm gap = 0.7 μm2 which is the smallest reported one using a top-down fabrication approach.

  12. Development of three channel linear bipolar high voltage amplifier (±2 KV) for electrostatic steerer

    International Nuclear Information System (INIS)

    Rajesh Kumar; Mukesh Kumar; Suman, S.K.; Safvan, C.P.; Mandal, A.

    2011-01-01

    Electrostatic steerers and scanners are planned for low energy ion beam facilities at IUAC to steer and scan the ion beam on target. The power supplies for electrostatic steerers are high voltage bipolar DC amplifiers and for scanners are bipolar AC amplifiers. To fulfil the requirements a common unit has been designed and assembled for AC and DC applications. It can be used with electrostatic devices in scanning, steering and sweeping of low energy ion beams at high frequencies to attain uniform implantation. The unit consist of three independent limited bandwidth high voltage, linear bipolar amplifiers (for X-axis, Y-axis and Y1-dog leg plates). The unit has been provided with both local and remote control. (author)

  13. Simulations of depleted CMOS sensors for high-radiation environments

    CERN Document Server

    Liu, J.; Bhat, S.; Breugnon, P.; Caicedo, I.; Chen, Z.; Degerli, Y.; Godiot-Basolo, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Hügging, F.; Krüger, H.; Moustakas, K.; Pangaud, P.; Rozanov, A.; Rymaszewski, P.; Schwemling, P.; Wang, M.; Wang, T.; Wermes, N.; Zhang, L.

    2017-01-01

    After the Phase II upgrade for the Large Hadron Collider (LHC), the increased luminosity requests a new upgraded Inner Tracker (ITk) for the ATLAS experiment. As a possible option for the ATLAS ITk, a new pixel detector based on High Voltage/High Resistivity CMOS (HV/HR CMOS) technology is under study. Meanwhile, a new CMOS pixel sensor is also under development for the tracker of Circular Electron Position Collider (CEPC). In order to explore the sensor electric properties, such as the breakdown voltage and charge collection efficiency, 2D/3D Technology Computer Aided Design (TCAD) simulations have been performed carefully for the above mentioned both of prototypes. In this paper, the guard-ring simulation for a HV/HR CMOS sensor developed for the ATLAS ITk and the charge collection efficiency simulation for a CMOS sensor explored for the CEPC tracker will be discussed in details. Some comparisons between the simulations and the latest measurements will also be addressed.

  14. Single-Event Effects in High-Frequency Linear Amplifiers: Experiment and Analysis

    Science.gov (United States)

    Zeinolabedinzadeh, Saeed; Ying, Hanbin; Fleetwood, Zachary E.; Roche, Nicolas J.-H.; Khachatrian, Ani; McMorrow, Dale; Buchner, Stephen P.; Warner, Jeffrey H.; Paki-Amouzou, Pauline; Cressler, John D.

    2017-01-01

    The single-event transient (SET) response of two different silicon-germanium (SiGe) X-band (8-12 GHz) low noise amplifier (LNA) topologies is fully investigated in this paper. The two LNAs were designed and implemented in 130nm SiGe HBT BiCMOS process technology. Two-photon absorption (TPA) laser pulses were utilized to induce transients within various devices in these LNAs. Impulse response theory is identified as a useful tool for predicting the settling behavior of the LNAs subjected to heavy ion strikes. Comprehensive device and circuit level modeling and simulations were performed to accurately simulate the behavior of the circuits under ion strikes. The simulations agree well with TPA measurements. The simulation, modeling and analysis presented in this paper can be applied for any other circuit topologies for SET modeling and prediction.

  15. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.; Gumus, Abdurrahman; Nassar, Joanna M.; Hussain, Muhammad Mustafa

    2018-01-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  16. CMOS Enabled Microfluidic Systems for Healthcare Based Applications

    KAUST Repository

    Khan, Sherjeel M.

    2018-02-27

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen.

  17. A Sub-µW Tuneable Switched-Capacitor Amplifier-Filter for Neural Recording Using a Class-C Inverter

    Directory of Open Access Journals (Sweden)

    A Ghorbani-Nejad

    2013-12-01

    Full Text Available A two stage sub-µW Inverter-based switched-capacitor amplifier-filter is presented which is capable of amplifying both spikes and local field potentials (LFP signals. Here we employ a switched capacitor technique for frequency tuning and reducing of 1/f noise of two stages. The reduction of power consumption is very necessary for neural recording devices however, in switched capacitor (SC circuits OTA is a major building block that consumes most of the power. Therefore an OTA-less technique utilizing a class-C inverter is employed that significantly reduces the power consumption. A detailed analysis of noise performance for the inverter-based SC circuits is presented. A mathematical model useful for analysis of such SC integrators is derived and a good comparison is obtained between simulation and analytical technique. With a supply voltage of 0.7V and using 0.18 µm CMOS technology, this design can achieves a power consumption of about 538 nW. The designed amplifier-filter has the gains 18.6 dB and 28.2 dB for low pass only and cascaded filter, respectively. By applying different sampling frequencies, the filter attains a reconfigurable bandwidth.

  18. Prevention of CMOS latch-up by gold doping

    International Nuclear Information System (INIS)

    Dawes, W.R.; Derbenwick, G.F.

    1976-01-01

    CMOS integrated circuits fabricated with the bulk silicon technology typically exhibit latch-up effects in either an ionizing radiation environment or an overvoltage stress condition. The latch-up effect has been shown to arise from regenerative switching, analogous to an SCR, in the adjacent parasitic bipolar transistors formed during the fabrication of a bulk CMOS device. Once latch-up has been initiated, it is usually self-sustaining and eventually destructive. Naturally, the circuit is inoperative during latch-up. This paper discusses a generic process technique that prevents the latch-up mechanism in CMOS devices

  19. Subthreshold currents in CMOS transistors made on oxygen-implanted silicon

    International Nuclear Information System (INIS)

    Foster, D.J.

    1983-01-01

    Kinks have been observed in subthreshold current plots of mesa-shaped n-channel transistors made on oxygen-implanted silicon substrates. The kinks represent additional current flow and are due to overlapping fields from the gate electrode causing early corner inversion and to a Qsub(ss) side-wall effect. Subthreshold currents in n-channel transistors are dominated by the two effects which, as a consequence, reduce threshold voltages especially in narrow n-channel transistors. The subthreshold characteristics of p-channel transistors were not affected in the same way. (author)

  20. High performance flexible CMOS SOI FinFETs

    KAUST Repository

    Fahad, Hossain M.

    2014-06-01

    We demonstrate the first ever CMOS compatible soft etch back based high performance flexible CMOS SOI FinFETs. The move from planar to non-planar FinFETs has enabled continued scaling down to the 14 nm technology node. This has been possible due to the reduction in off-state leakage and reduced short channel effects on account of the superior electrostatic charge control of multiple gates. At the same time, flexible electronics is an exciting expansion opportunity for next generation electronics. However, a fully integrated low-cost system will need to maintain ultra-large-scale-integration density, high performance and reliability - same as today\\'s traditional electronics. Up until recently, this field has been mainly dominated by very weak performance organic electronics enabled by low temperature processes, conducive to low melting point plastics. Now however, we show the world\\'s highest performing flexible version of 3D FinFET CMOS using a state-of-the-art CMOS compatible fabrication technique for high performance ultra-mobile consumer applications with stylish design. © 2014 IEEE.

  1. Toward CMOS image sensor based glucose monitoring.

    Science.gov (United States)

    Devadhasan, Jasmine Pramila; Kim, Sanghyo

    2012-09-07

    Complementary metal oxide semiconductor (CMOS) image sensor is a powerful tool for biosensing applications. In this present study, CMOS image sensor has been exploited for detecting glucose levels by simple photon count variation with high sensitivity. Various concentrations of glucose (100 mg dL(-1) to 1000 mg dL(-1)) were added onto a simple poly-dimethylsiloxane (PDMS) chip and the oxidation of glucose was catalyzed with the aid of an enzymatic reaction. Oxidized glucose produces a brown color with the help of chromogen during enzymatic reaction and the color density varies with the glucose concentration. Photons pass through the PDMS chip with varying color density and hit the sensor surface. Photon count was recognized by CMOS image sensor depending on the color density with respect to the glucose concentration and it was converted into digital form. By correlating the obtained digital results with glucose concentration it is possible to measure a wide range of blood glucose levels with great linearity based on CMOS image sensor and therefore this technique will promote a convenient point-of-care diagnosis.

  2. High-voltage CMOS detectors

    International Nuclear Information System (INIS)

    Ehrler, F.; Blanco, R.; Leys, R.; Perić, I.

    2016-01-01

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  3. High-voltage CMOS detectors

    Energy Technology Data Exchange (ETDEWEB)

    Ehrler, F., E-mail: felix.ehrler@student.kit.edu; Blanco, R.; Leys, R.; Perić, I.

    2016-07-11

    High-voltage CMOS (HVCMOS) pixel sensors are depleted active pixel sensors implemented in standard commercial CMOS processes. The sensor element is the n-well/p-substrate diode. The sensor electronics are entirely placed inside the n-well which is at the same time used as the charge collection electrode. High voltage is used to deplete the part of the substrate around the n-well. HVCMOS sensors allow implementation of complex in-pixel electronics. This, together with fast signal collection, allows a good time resolution, which is required for particle tracking in high energy physics. HVCMOS sensors will be used in Mu3e experiment at PSI and are considered as an option for both ATLAS and CLIC (CERN). Radiation tolerance and time walk compensation have been tested and results are presented. - Highlights: • High-voltage CMOS sensors will be used in Mu3e experiment at PSI (Switzerland). • HVCMOS sensors are considered as an option for ATLAS (LHC/CERN) and CLIC (CERN). • Efficiency of more than 95% (99%) has been measured with (un-)irradiated chips. • The time resolution measured in the beam tests is nearly 100 ns. • We plan to improve time resolution and efficiency by using high-resistive substrate.

  4. Large Format CMOS-based Detectors for Diffraction Studies

    Science.gov (United States)

    Thompson, A. C.; Nix, J. C.; Achterkirchen, T. G.; Westbrook, E. M.

    2013-03-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  5. Large Format CMOS-based Detectors for Diffraction Studies

    International Nuclear Information System (INIS)

    Thompson, A C; Westbrook, E M; Nix, J C; Achterkirchen, T G

    2013-01-01

    Complementary Metal Oxide Semiconductor (CMOS) devices are rapidly replacing CCD devices in many commercial and medical applications. Recent developments in CMOS fabrication have improved their radiation hardness, device linearity, readout noise and thermal noise, making them suitable for x-ray crystallography detectors. Large-format (e.g. 10 cm × 15 cm) CMOS devices with a pixel size of 100 μm × 100 μm are now becoming available that can be butted together on three sides so that very large area detector can be made with no dead regions. Like CCD systems our CMOS systems use a GdOS:Tb scintillator plate to convert stopping x-rays into visible light which is then transferred with a fiber-optic plate to the sensitive surface of the CMOS sensor. The amount of light per x-ray on the sensor is much higher in the CMOS system than a CCD system because the fiber optic plate is only 3 mm thick while on a CCD system it is highly tapered and much longer. A CMOS sensor is an active pixel matrix such that every pixel is controlled and readout independently of all other pixels. This allows these devices to be readout while the sensor is collecting charge in all the other pixels. For x-ray diffraction detectors this is a major advantage since image frames can be collected continuously at up 20 Hz while the crystal is rotated. A complete diffraction dataset can be collected over five times faster than with CCD systems with lower radiation exposure to the crystal. In addition, since the data is taken fine-phi slice mode the 3D angular position of diffraction peaks is improved. We have developed a cooled 6 sensor CMOS detector with an active area of 28.2 × 29.5 cm with 100 μm × 100 μm pixels and a readout rate of 20 Hz. The detective quantum efficiency exceeds 60% over the range 8-12 keV. One, two and twelve sensor systems are also being developed for a variety of scientific applications. Since the sensors are butt able on three sides, even larger systems could be built at

  6. Avalanche-mode silicon LEDs for monolithic optical coupling in CMOS technology

    NARCIS (Netherlands)

    Dutta, Satadal

    2017-01-01

    Complementary Metal-Oxide-Semiconductor (CMOS) integrated circuit (IC) technology is the most commercially successful platform in modern electronic and control systems. So called "smart power" technologies such as Bipolar CMOS DMOS (BCD), combine the computational power of CMOS with high voltage

  7. SRAP analysis of M3 lotus mutants induced by Fe+ ion implantation

    International Nuclear Information System (INIS)

    Jia Yanyan; Deng Chuanliang; Gao Jun; Ren Yingxue; Wang Ningna; Gao Wujun; Lu Longdou; Zhang Tao; Li Pengfei

    2011-01-01

    To examine and determine the lotus mutants induced by the same Fe + ion implantation at the molecular level, the SRAP technique was used, and the non denatured polyacrylamide gel electrophoresis was undertaken to analyze the PCR products. At the optimized SRAP reaction condition, of the 121 primer pairs tested, 10 primer pairs could amplify stable and remarkable specific bands, with primer polymorphism of 8.26%. This 10 primer pairs amplified a total of 215 bands, 83 of which were polymorphic, and the percent of polymorphic bands was 38.6%. A total of 141 bands were amplified for the mutant 1, 22 of which were different from the control with the variation ratio of 15.6%. However, the variation ratios of mutant 2 to 6 were 16.4%, 17.1%, 16.9%, 18.2% and 20.5% respectively. The results indicated that Fe + ion implantation into the seeds of Baiyangdian red lotus could induce random genetic DNA variations. (authors)

  8. Design of CMOS imaging system based on FPGA

    Science.gov (United States)

    Hu, Bo; Chen, Xiaolai

    2017-10-01

    In order to meet the needs of engineering applications for high dynamic range CMOS camera under the rolling shutter mode, a complete imaging system is designed based on the CMOS imaging sensor NSC1105. The paper decides CMOS+ADC+FPGA+Camera Link as processing architecture and introduces the design and implementation of the hardware system. As for camera software system, which consists of CMOS timing drive module, image acquisition module and transmission control module, the paper designs in Verilog language and drives it to work properly based on Xilinx FPGA. The ISE 14.6 emulator ISim is used in the simulation of signals. The imaging experimental results show that the system exhibits a 1280*1024 pixel resolution, has a frame frequency of 25 fps and a dynamic range more than 120dB. The imaging quality of the system satisfies the requirement of the index.

  9. CMOS Electrochemical Instrumentation for Biosensor Microsystems: A Review

    Directory of Open Access Journals (Sweden)

    Haitao Li

    2016-12-01

    Full Text Available Modern biosensors play a critical role in healthcare and have a quickly growing commercial market. Compared to traditional optical-based sensing, electrochemical biosensors are attractive due to superior performance in response time, cost, complexity and potential for miniaturization. To address the shortcomings of traditional benchtop electrochemical instruments, in recent years, many complementary metal oxide semiconductor (CMOS instrumentation circuits have been reported for electrochemical biosensors. This paper provides a review and analysis of CMOS electrochemical instrumentation circuits. First, important concepts in electrochemical sensing are presented from an instrumentation point of view. Then, electrochemical instrumentation circuits are organized into functional classes, and reported CMOS circuits are reviewed and analyzed to illuminate design options and performance tradeoffs. Finally, recent trends and challenges toward on-CMOS sensor integration that could enable highly miniaturized electrochemical biosensor microsystems are discussed. The information in the paper can guide next generation electrochemical sensor design.

  10. A 2 GS/s 8-bit folding and interpolating ADC in 90 nm CMOS

    International Nuclear Information System (INIS)

    He Wenwei; Meng Qiao; Zhang Yi; Tang Kai

    2014-01-01

    A single-channel 2 GS/s 8-bit analog-to-digital converter in 90 nm CMOS process technology is presented. It utilizes cascade folding architecture, which incorporates an additional inter-stage sample-and-hold amplifier between the folding circuits to enhance the quantization time. It also uses the foreground on-chip digital-assisted calibration circuit to improve the linearity of the circuit. The post simulation results demonstrate that it has a differential nonlinearity < ±0.3 LSB and an integral nonlinearity < ±0.25 LSB at the Nyquist frequency. Moreover, 7.338 effective numbers of bits can be achieved at 2 GSPS. The whole chip area is 0.88 × 0.88 mm 2 with the pad. It consumes 210 mW from a 1.2 V single supply. (semiconductor integrated circuits)

  11. Implantation of oxygen ions for the realization of SOS (silicon on insulator) structures: SIMOX

    International Nuclear Information System (INIS)

    Margail, J.

    1987-03-01

    Highdose oxygen implantation is becoming a serious candidate for SOI (silicon on insulator) structure realization. The fabrication condition study of these substrates allowed to show up the implantation and annealing parameter importance for microstructure, and particularly for crystal quality of silicon films. It has been shown that the use of high temperature annealings leads to high quality substrates: monocrystal silicon film without any precipitate, at the card scale; Si/Si O 2 interface formation. After annealing at 1340 O C, Hall mobilities have been measured in silicon film, and its residual doping is very low. First characteristics and performance of submicron CMOS circuits prooves the electric quality of these substrates [fr

  12. E-Beam Effects on CMOS Active Pixel Sensors

    International Nuclear Information System (INIS)

    Kang, Dong Ook; Jo, Gyu Seong; Kim, Hyeon Daek; Kim, Hyunk Taek; Kim, Jong Yeol; Kim, Chan Kyu

    2011-01-01

    Three different CMOS active pixel structures manufactured in a deep submicron process have been evaluated with electron beam. The devices were exposed to 1 MeV electron beam up to 5kGy. Dark current increased after E-beam irradiation differently at each pixel structure. Dark current change is dependent on CMOS pixel structures. CMOS image sensors are now good candidates in demanding applications such as medical image sensor, particle detection and space remote sensing. In these situations, CISs are exposed to high doses of radiation. In fact radiation is known to generate trapped charge in CMOS oxides. It can lead to threshold voltage shifts and current leakages in MOSFETs and dark current increase in photodiodes. We studied ionizing effects in three types of CMOS APSs fabricated by 0.25 CMOS process. The devices were irradiated by a Co 60 source up to 50kGy. All irradiation took place at room temperature. The dark current in the three different pixels exhibits increase with electron beam exposure. From the above figure, the change of dark current is dependent on the pixel structure. Double junction structure has shown relatively small increase of dark current after electron beam irradiation. The dark current in the three different pixels exhibits increase with electron beam exposure. The contribution of the total ionizing dose to the dark current increase is small here, since the devices were left unbiased during the electron beam irradiation. Radiation hardness in dependent on the pixel structures. Pixel2 is relatively vulnerable to radiation exposure. Pixel3 has radiation hardened structure

  13. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  14. CMOS-compatible spintronic devices: a review

    Science.gov (United States)

    Makarov, Alexander; Windbacher, Thomas; Sverdlov, Viktor; Selberherr, Siegfried

    2016-11-01

    For many decades CMOS devices have been successfully scaled down to achieve higher speed and increased performance of integrated circuits at lower cost. Today’s charge-based CMOS electronics encounters two major challenges: power dissipation and variability. Spintronics is a rapidly evolving research and development field, which offers a potential solution to these issues by introducing novel ‘more than Moore’ devices. Spin-based magnetoresistive random-access memory (MRAM) is already recognized as one of the most promising candidates for future universal memory. Magnetic tunnel junctions, the main elements of MRAM cells, can also be used to build logic-in-memory circuits with non-volatile storage elements on top of CMOS logic circuits, as well as versatile compact on-chip oscillators with low power consumption. We give an overview of CMOS-compatible spintronics applications. First, we present a brief introduction to the physical background considering such effects as magnetoresistance, spin-transfer torque (STT), spin Hall effect, and magnetoelectric effects. We continue with a comprehensive review of the state-of-the-art spintronic devices for memory applications (STT-MRAM, domain wall-motion MRAM, and spin-orbit torque MRAM), oscillators (spin torque oscillators and spin Hall nano-oscillators), logic (logic-in-memory, all-spin logic, and buffered magnetic logic gate grid), sensors, and random number generators. Devices with different types of resistivity switching are analyzed and compared, with their advantages highlighted and challenges revealed. CMOS-compatible spintronic devices are demonstrated beginning with predictive simulations, proceeding to their experimental confirmation and realization, and finalized by the current status of application in modern integrated systems and circuits. We conclude the review with an outlook, where we share our vision on the future applications of the prospective devices in the area.

  15. A Fully Implantable, NFC Enabled, Continuous Interstitial Glucose Monitor.

    Science.gov (United States)

    Anabtawi, Nijad; Freeman, Sabrina; Ferzli, Rony

    2016-02-01

    This work presents an integrated system-on-chip (SoC) that forms the core of a long-term, fully implantable, battery assisted, passive continuous glucose monitor. It integrates an amperometric glucose sensor interface, a near field communication (NFC) wireless front-end and a fully digital switched mode power management unit for supply regulation and on board battery charging. It uses 13.56 MHz (ISM) band to harvest energy and backscatter data to an NFC reader. System was implemented in 14nm CMOS technology and validated with post layout simulations.

  16. Extra source implantation for suppression floating-body effect in partially depleted SOI MOSFETs

    International Nuclear Information System (INIS)

    Chen Jing; Luo Jiexin; Wu Qingqing; Chai Zhan; Huang Xiaolu; Wei Xing; Wang Xi

    2012-01-01

    Silicon-on-insulate (SOI) MOSFETs offer benefits over bulk competitors for fully isolation and smaller junction capacitance. The performance of partially depleted (PD) SOI MOSFETs, though, is not good enough. Since the body is floating, the extra holes (for nMOSFETs) in this region accumulate, causing body potential arise, which of course degrades the performance of the device. How to suppress the floating-body effect becomes critical. There are mainly two ways for the goal. One is to employ body-contact structures, and the other SiGe source/drain structures. However, the former consumes extra area, not welcomed in the state-of-the-art chips design. The latter is not compatible with the traditional CMOS technology. Finding a structure both saving area and compatible technology is the most urgent for PD SOI MOSFETs. Recently, we have developed a new structure with extra heavy boron implantation in the source region for PD SOI nMOSFETs. It consumes no extra area and is also compatible with CMOS technology. The device is found to be free of kink effect in simulation, which implies the floating-body effect is greatly suppressed. In addition, the mechanisms of the kink-free, as well as the impact of different implanting conditions are interpreted.

  17. A linearization time-domain CMOS smart temperature sensor using a curvature compensation oscillator.

    Science.gov (United States)

    Chen, Chun-Chi; Chen, Hao-Wen

    2013-08-28

    This paper presents an area-efficient time-domain CMOS smart temperature sensor using a curvature compensation oscillator for linearity enhancement with a -40 to 120 °C temperature range operability. The inverter-based smart temperature sensors can substantially reduce the cost and circuit complexity of integrated temperature sensors. However, a large curvature exists on the temperature-to-time transfer curve of the inverter-based delay line and results in poor linearity of the sensor output. For cost reduction and error improvement, a temperature-to-pulse generator composed of a ring oscillator and a time amplifier was used to generate a thermal sensing pulse with a sufficient width proportional to the absolute temperature (PTAT). Then, a simple but effective on-chip curvature compensation oscillator is proposed to simultaneously count and compensate the PTAT pulse with curvature for linearization. With such a simple structure, the proposed sensor possesses an extremely small area of 0.07 mm2 in a TSMC 0.35-mm CMOS 2P4M digital process. By using an oscillator-based scheme design, the proposed sensor achieves a fine resolution of 0.045 °C without significantly increasing the circuit area. With the curvature compensation, the inaccuracy of -1.2 to 0.2 °C is achieved in an operation range of -40 to 120 °C after two-point calibration for 14 packaged chips. The power consumption is measured as 23 mW at a sample rate of 10 samples/s.

  18. A Wireless Implantable Switched-Capacitor Based Optogenetic Stimulating System

    Science.gov (United States)

    Lee, Hyung-Min; Kwon, Ki-Yong; Li, Wen

    2015-01-01

    This paper presents a power-efficient implantable optogenetic interface using a wireless switched-capacitor based stimulating (SCS) system. The SCS efficiently charges storage capacitors directly from an inductive link and periodically discharges them into an array of micro-LEDs, providing high instantaneous power without affecting wireless link and system supply voltage. A custom-designed computer interface in LabVIEW environment wirelessly controls stimulation parameters through the inductive link, and an optrode array enables simultaneous neural recording along with optical stimulation. The 4-channel SCS system prototype has been implemented in a 0.35-μm CMOS process and combined with the optrode array. In vivo experiments involving light-induced local field potentials verified the efficacy of the SCS system. An implantable version of the SCS system with flexible hermetic sealing is under development for chronic experiments. PMID:25570099

  19. CMOS Enabled Microfluidic Systems for Healthcare Based Applications.

    Science.gov (United States)

    Khan, Sherjeel M; Gumus, Abdurrahman; Nassar, Joanna M; Hussain, Muhammad M

    2018-04-01

    With the increased global population, it is more important than ever to expand accessibility to affordable personalized healthcare. In this context, a seamless integration of microfluidic technology for bioanalysis and drug delivery and complementary metal oxide semiconductor (CMOS) technology enabled data-management circuitry is critical. Therefore, here, the fundamentals, integration aspects, and applications of CMOS-enabled microfluidic systems for affordable personalized healthcare systems are presented. Critical components, like sensors, actuators, and their fabrication and packaging, are discussed and reviewed in detail. With the emergence of the Internet-of-Things and the upcoming Internet-of-Everything for a people-process-data-device connected world, now is the time to take CMOS-enabled microfluidics technology to as many people as possible. There is enormous potential for microfluidic technologies in affordable healthcare for everyone, and CMOS technology will play a major role in making that happen. © 2018 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  20. CMOS serial link for fully duplexed data communication

    Science.gov (United States)

    Lee, Kyeongho; Kim, Sungjoon; Ahn, Gijung; Jeong, Deog-Kyoon

    1995-04-01

    This paper describes a CMOS serial link allowing fully duplexed 500 Mbaud serial data communication. The CMOS serial link is a robust and low-cost solution to high data rate requirements. A central charge pump PLL for generating multiphase clocks for oversampling is shared by several serial link channels. Fully duplexed serial data communication is realized in the bidirectional bridge by separating incoming data from the mixed signal on the cable end. The digital PLL accomplishes process-independent data recovery by using a low-ratio oversampling, a majority voting, and a parallel data recovery scheme. Mostly, digital approach could extend its bandwidth further with scaled CMOS technology. A single channel serial link and a charge pump PLL are integrated in a test chip using 1.2 micron CMOS process technology. The test chip confirms upto 500 Mbaud unidirectional mode operation and 320 Mbaud fully duplexed mode operation with pseudo random data patterns.

  1. Decal electronics for printed high performance cmos electronic systems

    KAUST Repository

    Hussain, Muhammad Mustafa; Sevilla, Galo Torres; Cordero, Marlon Diaz; Kutbee, Arwa T.

    2017-01-01

    High performance complementary metal oxide semiconductor (CMOS) electronics are critical for any full-fledged electronic system. However, state-of-the-art CMOS electronics are rigid and bulky making them unusable for flexible electronic applications

  2. CMOS Thermal Ox and Diffusion Furnace: Tystar Tytan 2000

    Data.gov (United States)

    Federal Laboratory Consortium — Description:CORAL Names: CMOS Wet Ox, CMOS Dry Ox, Boron Doping (P-type), Phos. Doping (N-Type)This four-stack furnace bank is used for the thermal growth of silicon...

  3. CMOS Compressed Imaging by Random Convolution

    OpenAIRE

    Jacques, Laurent; Vandergheynst, Pierre; Bibet, Alexandre; Majidzadeh, Vahid; Schmid, Alexandre; Leblebici, Yusuf

    2009-01-01

    We present a CMOS imager with built-in capability to perform Compressed Sensing. The adopted sensing strategy is the random Convolution due to J. Romberg. It is achieved by a shift register set in a pseudo-random configuration. It acts as a convolutive filter on the imager focal plane, the current issued from each CMOS pixel undergoing a pseudo-random redirection controlled by each component of the filter sequence. A pseudo-random triggering of the ADC reading is finally applied to comp...

  4. The challenge of sCMOS image sensor technology to EMCCD

    Science.gov (United States)

    Chang, Weijing; Dai, Fang; Na, Qiyue

    2018-02-01

    In the field of low illumination image sensor, the noise of the latest scientific-grade CMOS image sensor is close to EMCCD, and the industry thinks it has the potential to compete and even replace EMCCD. Therefore we selected several typical sCMOS and EMCCD image sensors and cameras to compare their performance parameters. The results show that the signal-to-noise ratio of sCMOS is close to EMCCD, and the other parameters are superior. But signal-to-noise ratio is very important for low illumination imaging, and the actual imaging results of sCMOS is not ideal. EMCCD is still the first choice in the high-performance application field.

  5. Characterisation of a novel reverse-biased PPD CMOS image sensor

    Science.gov (United States)

    Stefanov, K. D.; Clarke, A. S.; Ivory, J.; Holland, A. D.

    2017-11-01

    A new pinned photodiode (PPD) CMOS image sensor (CIS) has been developed and characterised. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the pixel p-wells, called Deep Depletion Extension (DDE), have been added in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The first prototype has been manufactured on a 18 μm thick, 1000 Ω .cm epitaxial silicon wafers using 180 nm PPD image sensor process at TowerJazz Semiconductor. The chip contains arrays of 10 μm and 5.4 μm pixels, with variations of the shape, size and the depth of the DDE implant. Back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v, and characterised together with the front-side illuminated (FSI) variants. The presented results show that the devices could be reverse-biased without parasitic leakage currents, in good agreement with simulations. The new 10 μm pixels in both BSI and FSI variants exhibit nearly identical photo response to the reference non-modified pixels, as characterised with the photon transfer curve. Different techniques were used to measure the depletion depth in FSI and BSI chips, and the results are consistent with the expected full depletion.

  6. Mixed-signal 0.18μm CMOS and SiGe BiCMOS foundry technologies for ROIC applications

    Science.gov (United States)

    Kar-Roy, Arjun; Howard, David; Racanelli, Marco; Scott, Mike; Hurwitz, Paul; Zwingman, Robert; Chaudhry, Samir; Jordan, Scott

    2010-10-01

    Today's readout integrated-circuits (ROICs) require a high level of integration of high performance analog and low power digital logic. TowerJazz offers a commercial 0.18μm CMOS technology platform for mixed-signal, RF, and high performance analog applications which can be used for ROIC applications. The commercial CA18HD dual gate oxide 1.8V/3.3V and CA18HA dual gate oxide 1.8V/5V RF/mixed signal processes, consisting of six layers of metallization, have high density stacked linear MIM capacitors, high-value resistors, triple-well isolation and thick top aluminum metal. The CA18HA process also has scalable drain extended LDMOS devices, up to 40V Vds, for high-voltage sensor applications, and high-performance bipolars for low noise requirements in ROICs. Also discussed are the available features of the commercial SBC18 SiGe BiCMOS platform with SiGe NPNs operating up to 200/200GHz (fT/fMAX frequencies in manufacturing and demonstrated to 270 GHz fT, for reduced noise and integrated RF capabilities which could be used in ROICs. Implementation of these technologies in a thick film SOI process for integrated RF switch and power management and the availability of high fT vertical PNPs to enable complementary BiCMOS (CBiCMOS), for RF enabled ROICs, are also described in this paper.

  7. Variationen und ihre Kompensation in CMOS Digitalschaltungen

    OpenAIRE

    Baumann, Thomas

    2010-01-01

    Variationen bei der Herstellung und während des Betriebs von CMOS Schaltungen beeinflussen deren Geschwindigkeit und erschweren die Verifikation der in der Spezifikation zugesicherten Eigenschaften. In dieser Arbeit wird eine abstraktionsebenenübergreifende Vorgehensweise zur Abschätzung des Einflusses von Prozess- und betriebsbedingten Umgebungsvariationen auf die Geschwindigkeit einer Schaltung vorgestellt. Neben Untersuchungen der Laufzeitsensitivität in low-power CMOS Technologien von...

  8. Development of a low-noise, two-dimensional amplifier array

    International Nuclear Information System (INIS)

    Kishishita, Tetsuichi; Ikeda, Hirokazu; Sakumura, Takuto; Tamura, Ken-ichi; Takahashi, Tadayuki

    2009-01-01

    This paper describes the recent development of a low-noise, two-dimensional analog front-end ASIC for hybrid pixel imaging detectors. Based on the Open-IP LSI project, the ASIC is designed to meet a low-noise requirement of better than 100e - (rms) with self-triggering capability. The ASIC is intended for the readout of pixel sensors utilizing silicon (Si) and cadmium telluride (CdTe) as detector materials for spectroscopic imaging observations in the X-ray and gamma-ray regions. The readout chip consists of a 4x4 matrix of identical 270μmx270μm pixel cells and was implemented with TSMC 0.35-μm CMOS technology. Each pixel cell contains a charge-sensitive amplifier, pole-zero cancellation circuit, shaper, comparator, and peak hold circuit. Preliminary testing of the ASIC achieved an 88e - (rms) equivalent noise charge and a 25e - /pF noise slope with power consumption of 150μW per pixel.

  9. A Low Noise Amplifier for Neural Spike Recording Interfaces

    Directory of Open Access Journals (Sweden)

    Jesus Ruiz-Amaya

    2015-09-01

    Full Text Available This paper presents a Low Noise Amplifier (LNA for neural spike recording applications. The proposed topology, based on a capacitive feedback network using a two-stage OTA, efficiently solves the triple trade-off between power, area and noise. Additionally, this work introduces a novel transistor-level synthesis methodology for LNAs tailored for the minimization of their noise efficiency factor under area and noise constraints. The proposed LNA has been implemented in a 130 nm CMOS technology and occupies 0.053 mm-sq. Experimental results show that the LNA offers a noise efficiency factor of 2.16 and an input referred noise of 3.8 μVrms for 1.2 V power supply. It provides a gain of 46 dB over a nominal bandwidth of 192 Hz–7.4 kHz and consumes 1.92 μW. The performance of the proposed LNA has been validated through in vivo experiments with animal models.

  10. Multi-Channel Amplifier-Discriminator for Highly Time-Resolved Detection

    CERN Document Server

    Despeisse, M; Lapington, J; Jarron, P

    2011-01-01

    A low-power multi-channel amplifier-discriminator was developed for application in highly time-resolved detection systems. The proposed circuit architecture, so-called Nino, is based on a time-over-threshold approach and shows a high potential for time-resolved readout of solid-state photo-detectors and of detectors based on vacuum technologies. The Irpics circuit was designed in a 250 nm CMOS technology, implementing 32 channels of a Nino version optimized to achieve high-time resolution on the output low-voltage differential signals (LVDS) while keeping a low power consumption of 10 mW per channel. Electrical characterizations of the circuit demonstrate a very low intrinsic time jitter on the output pulse leading edge, measured below 10 ps rms for each channel for high input signal charges (100 fC) and below 25 ps rms for low input signal charges (20-100 fC). The read-out architecture moreover permits to retrieve the input signal charge from the timing measurements, while a calibration procedure was develop...

  11. A Highly Responsive Silicon Nanowire/Amplifier MOSFET Hybrid Biosensor.

    Science.gov (United States)

    Lee, Jieun; Jang, Jaeman; Choi, Bongsik; Yoon, Jinsu; Kim, Jee-Yeon; Choi, Yang-Kyu; Kim, Dong Myong; Kim, Dae Hwan; Choi, Sung-Jin

    2015-07-21

    This study demonstrates a hybrid biosensor comprised of a silicon nanowire (SiNW) integrated with an amplifier MOSFET to improve the current response of field-effect-transistor (FET)-based biosensors. The hybrid biosensor is fabricated using conventional CMOS technology, which has the potential advantage of high density and low noise performance. The biosensor shows a current response of 5.74 decades per pH for pH detection, which is 2.5 × 10(5) times larger than that of a single SiNW sensor. In addition, we demonstrate charged polymer detection using the biosensor, with a high current change of 4.5 × 10(5) with a 500 nM concentration of poly(allylamine hydrochloride). In addition, we demonstrate a wide dynamic range can be obtained by adjusting the liquid gate voltage. We expect that this biosensor will be advantageous and practical for biosensor applications which requires lower noise, high speed, and high density.

  12. Process techniques of charge transfer time reduction for high speed CMOS image sensors

    International Nuclear Information System (INIS)

    Cao Zhongxiang; Li Quanliang; Han Ye; Qin Qi; Feng Peng; Liu Liyuan; Wu Nanjian

    2014-01-01

    This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 × 64 pixels was designed and implemented in the 0.18 μm CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques. (semiconductor devices)

  13. Novel pre-equalization transimpedance amplifier for 10 Gb/s optical interconnects

    International Nuclear Information System (INIS)

    Song Qiwei; Mao Luhong; Xie Sheng; Kang Yuzhuo

    2015-01-01

    This paper presents a modified regulated cascode (RGC) transimpedance amplifier (TIA) with a novel pre-equalized technique. The pre-equalized circuit employed the broadband series inductive π-network and G m -boosting technique. The introduction of this technique compensates the transferred signal at the input port of the TIA without an increase in power dissipation. Furthermore, a novel miller capacitance degeneration method is designed in the gain stage for further bandwidth improvement. The TIA is realized in UMC 0.18 πm CMOS technology and tested with an on-chip 0.3 pF capacitor to emulate a photodetector (PD). The measured transimpedance gain amounts to 57 dBΩ with a −3 dB bandwidth of about 8.2 GHz and consumes only 22 mW power from a single 1.8 V supply. (paper)

  14. CMOS analog circuit design

    CERN Document Server

    Allen, Phillip E

    1987-01-01

    This text presents the principles and techniques for designing analog circuits to be implemented in a CMOS technology. The level is appropriate for seniors and graduate students familiar with basic electronics, including biasing, modeling, circuit analysis, and some familiarity with frequency response. Students learn the methodology of analog integrated circuit design through a hierarchically-oriented approach to the subject that provides thorough background and practical guidance for designing CMOS analog circuits, including modeling, simulation, and testing. The authors' vast industrial experience and knowledge is reflected in the circuits, techniques, and principles presented. They even identify the many common pitfalls that lie in the path of the beginning designer--expert advice from veteran designers. The text mixes the academic and practical viewpoints in a treatment that is neither superficial nor overly detailed, providing the perfect balance.

  15. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  16. Long term ionization response of several BiCMOS VLSIC technologies

    International Nuclear Information System (INIS)

    Pease, R.L.; Combs, W.; Clark, S.

    1992-01-01

    BiCMOS is emerging as a strong competitor to CMOS for gate arrays and memories because of its performance advantages for the same feature size. In this paper, the authors examine the long term ionization response of five BiCMOS technologies by characterizing test structures which emphasize the various failure modes of CMOS and bipolar. The primary failure modes are found to be associated with the recessed field oxide isolation; edge leakage in the n channel MOSFETs and buried layer to buried layer leakage in the bipolar. The ionization failure thresholds for worst case bias were in the range of 5-20 Krad(Si) for both failure modes in all five technologies

  17. Maximization of DRAM yield by control of surface charge and particle addition during high dose implantation

    Science.gov (United States)

    Horvath, J.; Moffatt, S.

    1991-04-01

    Ion implantation processing exposes semiconductor devices to an energetic ion beam in order to deposit dopant ions in shallow layers. In addition to this primary process, foreign materials are deposited as particles and surface films. The deposition of particles is a major cause of IC yield loss and becomes even more significant as device dimensions are decreased. Control of particle addition in a high-volume production environment requires procedures to limit beamline and endstation sources, control of particle transport, cleaning procedures and a well grounded preventative maintenance philosophy. Control of surface charge by optimization of the ion beam and electron shower conditions and measurement with a real-time charge sensor has been effective in improving the yield of NMOS and CMOS DRAMs. Control of surface voltages to a range between 0 and -20 V was correlated with good implant yield with PI9200 implanters for p + and n + source-drain implants.

  18. First principle leakage current reduction technique for CMOS devices

    CSIR Research Space (South Africa)

    Tsague, HD

    2015-12-01

    Full Text Available This paper presents a comprehensive study of leakage reduction techniques applicable to CMOS based devices. In the process, mathematical equations that model the power-performance trade-offs in CMOS logic circuits are presented. From those equations...

  19. Characterization of 13 and 30 mum thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

    CERN Document Server

    Despeisse, M; Commichau, S C; Dissertori, G; Garrigos, A; Jarron, P; Miazza, C; Moraes, D; Shah, A; Wyrsch, N; Viertel, Gert M; 10.1016/j.nima.2003.11.022

    2004-01-01

    We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30mum thick a-Si:H films deposited on top of an ASIC containing a linear array of high- speed low-noise transimpedance amplifiers designed in a 0.25mum CMOS technology. Experimental results presented have been obtained with a 600nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed.

  20. Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

    CERN Document Server

    INSPIRE-00218480

    2016-01-01

    The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

  1. A monolithic 180 nm CMOS dosimeter for wireless In Vivo Dosimetry

    International Nuclear Information System (INIS)

    Villani, E.G.; Crepaldi, M.; DeMarchi, D.; Gabrielli, A.; Khan, A.; Pikhay, E.; Roizin, Y.; Rosenfeld, A.; Zhang, Z.

    2016-01-01

    The design, fabrication and testing of a novel monolithic system-on-chip dosimeter fabricated in a standard 180 nm CMOS technology is described. The device, implementing a radiation sensor and an RF transmitter, is proposed to address the need for real-time In Vivo Dosimetry (IVD) of radiation during Linac radiotherapy sessions. Owing to its small size, of approximately 1 mm"3, such solution could be made in-body implantable and, as such, provide a much-enhanced high-resolution, real-time dose measurement to improve Quality Assurance (QA) in radiation therapy. The device transmits the related information on dose of radiation wirelessly to a remote receiver operating in the Medical Implant Communication Service (MICS) band. Comprehensive description of the various phases of this project, including the development of the radiation sensors and integrated RF transmitter to perform the readout, along with the final test results using a radiation beam, will be given. - Highlights: • A Monolithic Dosimeter for real time dosimetry during radiotherapy is proposed. • The proposed device is 1 mm3 in size and could potentially be body implantable. • The device includes a radiation sensor and RF readout, operating in the MICS band. • Detailed tests have been performed under radiation beam in a clinical environment. • Reported sensitivity is 1 cGy over 50 Gy, with an accuracy of better than 3%.

  2. Ion traps fabricated in a CMOS foundry

    Energy Technology Data Exchange (ETDEWEB)

    Mehta, K. K.; Ram, R. J. [Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Eltony, A. M.; Chuang, I. L. [Center for Ultracold Atoms, Research Laboratory of Electronics and Department of Physics, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139 (United States); Bruzewicz, C. D.; Sage, J. M., E-mail: jsage@ll.mit.edu; Chiaverini, J., E-mail: john.chiaverini@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2014-07-28

    We demonstrate trapping in a surface-electrode ion trap fabricated in a 90-nm CMOS (complementary metal-oxide-semiconductor) foundry process utilizing the top metal layer of the process for the trap electrodes. The process includes doped active regions and metal interconnect layers, allowing for co-fabrication of standard CMOS circuitry as well as devices for optical control and measurement. With one of the interconnect layers defining a ground plane between the trap electrode layer and the p-type doped silicon substrate, ion loading is robust and trapping is stable. We measure a motional heating rate comparable to those seen in surface-electrode traps of similar size. This demonstration of scalable quantum computing hardware utilizing a commercial CMOS process opens the door to integration and co-fabrication of electronics and photonics for large-scale quantum processing in trapped-ion arrays.

  3. Towards on-chip integration of brain imaging photodetectors using standard CMOS process.

    Science.gov (United States)

    Kamrani, Ehsan; Lesage, Frederic; Sawan, Mohamad

    2013-01-01

    The main effects of on-chip integration on the performance and efficiency of silicon avalanche photodiode (SiAPD) and photodetector front-end is addressed in this paper based on the simulation and fabrication experiments. Two different silicon APDs are fabricated separately and also integrated with a transimpedance amplifier (TIA) front-end using standard CMOS technology. SiAPDs are designed in p+/n-well structure with guard rings realized in different shapes. The TIA front-end has been designed using distributed-gain concept combined with resistive-feedback and common-gate topology to reach low-noise and high gain-bandwidth product (GBW) characteristics. The integrated SiAPDs show higher signal-to-noise ratio (SNR), sensitivity and detection efficiency comparing to the separate SiAPDs. The integration does not show a significant effect on the gain and preserves the low power consumption. Using APDs with p-well guard-ring is preferred due to the higher observed efficiency after integration.

  4. CMOS front ends for millimeter wave wireless communication systems

    CERN Document Server

    Deferm, Noël

    2015-01-01

    This book focuses on the development of circuit and system design techniques for millimeter wave wireless communication systems above 90GHz and fabricated in nanometer scale CMOS technologies. The authors demonstrate a hands-on methodology that was applied to design six different chips, in order to overcome a variety of design challenges. Behavior of both actives and passives, and how to design them to achieve high performance is discussed in detail. This book serves as a valuable reference for millimeter wave designers, working at both the transistor level and system level.   Discusses advantages and disadvantages of designing wireless mm-wave communication circuits and systems in CMOS; Analyzes the limitations and pitfalls of building mm-wave circuits in CMOS; Includes mm-wave building block and system design techniques and applies these to 6 different CMOS chips; Provides guidelines for building measurement setups to evaluate high-frequency chips.  

  5. Gas spectroscopy system with 245 GHz transmitter and receiver in SiGe BiCMOS

    Science.gov (United States)

    Schmalz, Klaus; Rothbart, Nick; Borngräber, Johannes; Yilmaz, Selahattin Berk; Kissinger, Dietmar; Hübers, Heinz-Wilhelm

    2017-02-01

    The implementation of an integrated mm-wave transmitter (TX) and receiver (RX) in SiGe BiCMOS or CMOS technology offers a path towards a compact and low-cost system for gas spectroscopy. Previously, we have demonstrated TXs and RXs for spectroscopy at 238 -252 GHz and 495 - 497 GHz using external phase-locked loops (PLLs) with signal generators for the reference frequency ramps. Here, we present a more compact system by using two external fractional-N PLLs allowing frequency ramps for the TX and RX, and for TX with superimposed frequency shift keying (FSK) or reference frequency modulation realized by a direct digital synthesizer (DDS) or an arbitrary waveform generator. The 1.9 m folded gas absorption cell, the vacuum pumps, as well as the TX and RX are placed on a portable breadboard with dimensions of 75 cm x 45 cm. The system performance is evaluated by high-resolution absorption spectra of gaseous methanol at 13 Pa for 241 - 242 GHz. The 2f (second harmonic) content of the absorption spectrum of the methanol was obtained by detecting the IF power of RX using a diode power sensor connected to a lock-in amplifier. The reference frequency modulation reveals a higher SNR (signal-noise-ratio) of 98 within 32 s acquisition compared to 66 for FSK. The setup allows for jumping to preselected frequency regions according to the spectral signature thus reducing the acquisition time by up to one order of magnitude.

  6. Hybrid Josephson-CMOS Memory in Advanced Technologies and Larger Sizes

    International Nuclear Information System (INIS)

    Liu, Q; Van Duzer, T; Fujiwara, K; Yoshikawa, N

    2006-01-01

    Recent progress on demonstrating components of the 64 kb Josephson-CMOS hybrid memory has encouraged exploration of the advancement possible with use of advanced technologies for both the Josephson and CMOS parts of the memory, as well as considerations of the effect of memory size on access time and power dissipation. The simulations to be reported depend on the use of an approximate model for 90 nm CMOS at 4 K. This model is an extension of the one we developed for 0.25 μm CMOS and have already verified. For the Josephson parts, we have chosen 20 kA/cm 2 technology, which was recently demonstrated. The calculations show that power dissipation and access time increase rather slowly with increasing size of the memory

  7. CMOS Imaging Sensor Technology for Aerial Mapping Cameras

    Science.gov (United States)

    Neumann, Klaus; Welzenbach, Martin; Timm, Martin

    2016-06-01

    In June 2015 Leica Geosystems launched the first large format aerial mapping camera using CMOS sensor technology, the Leica DMC III. This paper describes the motivation to change from CCD sensor technology to CMOS for the development of this new aerial mapping camera. In 2002 the DMC first generation was developed by Z/I Imaging. It was the first large format digital frame sensor designed for mapping applications. In 2009 Z/I Imaging designed the DMC II which was the first digital aerial mapping camera using a single ultra large CCD sensor to avoid stitching of smaller CCDs. The DMC III is now the third generation of large format frame sensor developed by Z/I Imaging and Leica Geosystems for the DMC camera family. It is an evolution of the DMC II using the same system design with one large monolithic PAN sensor and four multi spectral camera heads for R,G, B and NIR. For the first time a 391 Megapixel large CMOS sensor had been used as PAN chromatic sensor, which is an industry record. Along with CMOS technology goes a range of technical benefits. The dynamic range of the CMOS sensor is approx. twice the range of a comparable CCD sensor and the signal to noise ratio is significantly better than with CCDs. Finally results from the first DMC III customer installations and test flights will be presented and compared with other CCD based aerial sensors.

  8. Cryo-CMOS Circuits and Systems for Quantum Computing Applications

    NARCIS (Netherlands)

    Patra, B; Incandela, R.M.; van Dijk, J.P.G.; Homulle, H.A.R.; Song, Lin; Shahmohammadi, M.; Staszewski, R.B.; Vladimirescu, A.; Babaie, M.; Sebastiano, F.; Charbon, E.E.E.

    2018-01-01

    A fault-tolerant quantum computer with millions of quantum bits (qubits) requires massive yet very precise control electronics for the manipulation and readout of individual qubits. CMOS operating at cryogenic temperatures down to 4 K (cryo-CMOS) allows for closer system integration, thus promising

  9. From VHF to UHF CMOS-MEMS Monolithically Integrated Resonators

    DEFF Research Database (Denmark)

    Teva, Jordi; Berini, Abadal Gabriel; Uranga, A.

    2008-01-01

    This paper presents the design, fabrication and characterization of microresonators exhibiting resonance frequencies in the VHF and UHF bands, fabricated using the available layers of the standard and commercial CMOS technology, AMS-0.35mum. The resonators are released in a post-CMOS process cons...

  10. CMOS-compatible high-voltage integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Parpia, Z

    1988-01-01

    Considerable savings in cost and development time can be achieved if high-voltage ICs (HVICs) are fabricated in an existing low-voltage process. In this thesis, the feasibility of fabricating HVICs in a standard CMOS process is investigated. The high-voltage capabilities of an existing 5-{mu}m CMOS process are first studied. High-voltage n- and p-channel transistors with breakdown voltages of 50 and 190 V, respectively, were fabricated without any modifications to the process under consideration. SPICE models for these transistors are developed, and their accuracy verified by comparison with experimental results. In addition, the effect of the interconnect metallization on the high-voltage performance of these devices is also examined. Polysilicon field plates are found to be effective in preventing premature interconnect induced breakdown in these devices. A novel high-voltage transistor structure, the insulated base transistor (IBT), based on a merged MOS-bipolar concept, is proposed and implemented. In order to enhance the high-voltage device capabilities, an improved CMOS-compatible HVIC process using junction isolation is developed.

  11. An Integrated Low-Power Lock-In Amplifier and Its Application to Gas Detection

    Directory of Open Access Journals (Sweden)

    Paulina M. Maya-Hernández

    2014-08-01

    Full Text Available This paper presents a new micropower analog lock-in amplifier (LIA suitable for battery-operated applications thanks to its reduced size and power consumption as well as its operation with single-supply voltage. The proposed LIA was designed in a 0.18 µm CMOS process with a single supply voltage of 1.8 V. Experimental results show a variable DC gain ranging from 24.7 to 42 dB, power consumption of 417 µW and integration area of 0.013 mm2. The LIA performance was demonstrated by measuring carbon monoxide concentrations as low as 1 ppm in dry N2. The experimental results show that the response to CO of the sensing system can be considerably improved by means of the proposed LIA.

  12. A Low-Noise CMOS THz Imager Based on Source Modulation and an In-Pixel High-Q Passive Switched-Capacitor N-Path Filter.

    Science.gov (United States)

    Boukhayma, Assim; Dupret, Antoine; Rostaing, Jean-Pierre; Enz, Christian

    2016-03-03

    This paper presents the first low noise complementary metal oxide semiconductor (CMOS) deletedCMOS terahertz (THz) imager based on source modulation and in-pixel high-Q filtering. The 31 × 31 focal plane array has been fully integrated in a 0 . 13 μ m standard CMOS process. The sensitivity has been improved significantly by modulating the active THz source that lights the scene and performing on-chip high-Q filtering. Each pixel encompass a broadband bow tie antenna coupled to an N-type metal-oxide-semiconductor (NMOS) detector that shifts the THz radiation, a low noise adjustable gain amplifier and a high-Q filter centered at the modulation frequency. The filter is based on a passive switched-capacitor (SC) N-path filter combined with a continuous-time broad-band Gm-C filter. A simplified analysis that helps in designing and tuning the passive SC N-path filter is provided. The characterization of the readout chain shows that a Q factor of 100 has been achieved for the filter with a good matching between the analytical calculation and the measurement results. An input-referred noise of 0 . 2 μ V RMS has been measured. Characterization of the chip with different THz wavelengths confirms the broadband feature of the antenna and shows that this THz imager reaches a total noise equivalent power of 0 . 6 nW at 270 GHz and 0 . 8 nW at 600 GHz.

  13. Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

    Science.gov (United States)

    Stefanov, Konstantin D; Clarke, Andrew S; Ivory, James; Holland, Andrew D

    2018-01-03

    A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

  14. Signal-Conditioning Block of a 1 × 200 CMOS Detector Array for a Terahertz Real-Time Imaging System

    Directory of Open Access Journals (Sweden)

    Jong-Ryul Yang

    2016-03-01

    Full Text Available A signal conditioning block of a 1 × 200 Complementary Metal-Oxide-Semiconductor (CMOS detector array is proposed to be employed with a real-time 0.2 THz imaging system for inspecting large areas. The plasmonic CMOS detector array whose pixel size including an integrated antenna is comparable to the wavelength of the THz wave for the imaging system, inevitably carries wide pixel-to-pixel variation. To make the variant outputs from the array uniform, the proposed signal conditioning block calibrates the responsivity of each pixel by controlling the gate bias of each detector and the voltage gain of the lock-in amplifiers in the block. The gate bias of each detector is modulated to 1 MHz to improve the signal-to-noise ratio of the imaging system via the electrical modulation by the conditioning block. In addition, direct current (DC offsets of the detectors in the array are cancelled by initializing the output voltage level from the block. Real-time imaging using the proposed signal conditioning block is demonstrated by obtaining images at the rate of 19.2 frame-per-sec of an object moving on the conveyor belt with a scan width of 20 cm and a scan speed of 25 cm/s.

  15. CMOS Image Sensors: Electronic Camera On A Chip

    Science.gov (United States)

    Fossum, E. R.

    1995-01-01

    Recent advancements in CMOS image sensor technology are reviewed, including both passive pixel sensors and active pixel sensors. On- chip analog to digital converters and on-chip timing and control circuits permit realization of an electronic camera-on-a-chip. Highly miniaturized imaging systems based on CMOS image sensor technology are emerging as a competitor to charge-coupled devices for low cost uses.

  16. CMOS image sensor-based immunodetection by refractive-index change.

    Science.gov (United States)

    Devadhasan, Jasmine P; Kim, Sanghyo

    2012-01-01

    A complementary metal oxide semiconductor (CMOS) image sensor is an intriguing technology for the development of a novel biosensor. Indeed, the CMOS image sensor mechanism concerning the detection of the antigen-antibody (Ag-Ab) interaction at the nanoscale has been ambiguous so far. To understand the mechanism, more extensive research has been necessary to achieve point-of-care diagnostic devices. This research has demonstrated a CMOS image sensor-based analysis of cardiovascular disease markers, such as C-reactive protein (CRP) and troponin I, Ag-Ab interactions on indium nanoparticle (InNP) substrates by simple photon count variation. The developed sensor is feasible to detect proteins even at a fg/mL concentration under ordinary room light. Possible mechanisms, such as dielectric constant and refractive-index changes, have been studied and proposed. A dramatic change in the refractive index after protein adsorption on an InNP substrate was observed to be a predominant factor involved in CMOS image sensor-based immunoassay.

  17. Characterization of 13 and 30 μm thick hydrogenated amorphous silicon diodes deposited over CMOS integrated circuits for particle detection application

    International Nuclear Information System (INIS)

    Despeisse, M.; Anelli, G.; Commichau, S.; Dissertori, G.; Garrigos, A.; Jarron, P.; Miazza, C.; Moraes, D.; Shah, A.; Wyrsch, N.; Viertel, G.

    2004-01-01

    We present the experimental results obtained with a novel monolithic silicon pixel detector which consists in depositing a n-i-p hydrogenated amorphous silicon (a-Si:H) diode straight above the readout ASIC (this technology is called Thin Film on ASIC, TFA). The characterization has been performed on 13 and 30 μm thick a-Si:H films deposited on top of an ASIC containing a linear array of high-speed low-noise transimpedance amplifiers designed in a 0.25 μm CMOS technology. Experimental results presented have been obtained with a 600 nm pulsed laser. The results of charge collection efficiency and charge collection speed of these structures are discussed

  18. CMOS circuit design, layout and simulation

    CERN Document Server

    Baker, R Jacob

    2010-01-01

    The Third Edition of CMOS Circuit Design, Layout, and Simulation continues to cover the practical design of both analog and digital integrated circuits, offering a vital, contemporary view of a wide range of analog/digital circuit blocks including: phase-locked-loops, delta-sigma sensing circuits, voltage/current references, op-amps, the design of data converters, and much more. Regardless of one's integrated circuit (IC) design skill level, this book allows readers to experience both the theory behind, and the hands-on implementation of, complementary metal oxide semiconductor (CMOS) IC design via detailed derivations, discussions, and hundreds of design, layout, and simulation examples.

  19. Operation amplifier

    NARCIS (Netherlands)

    Tetsuya, Saito; Nauta, Bram

    2008-01-01

    To provide an operation amplifier which improves power source voltage removal ratios while assuring phase compensation characteristics, and therefore can be realized with a small-scale circuit and low power consumption. SOLUTION: The operation amplifier comprises: a differential amplifier circuit 1;

  20. Implantable medical electronics prosthetics, drug delivery, and health monitoring

    CERN Document Server

    Khanna, Vinod Kumar

    2016-01-01

    This book is a comprehensive, interdisciplinary resource for the latest information on implantable medical devices, and is intended for graduate students studying electrical engineering, electronic instrumentation, and biomedical engineering. It is also appropriate for academic researchers, professional engineers, practicing doctors, and paramedical staff. Divided into two sections on Basic Concepts and Principles, and Applications, the first section provides an all-embracing perspective of the electronics background necessary for this work. The second section deals with pacing techniques used for the heart, brain, spinal cord, and the network of nerves that interlink the brain and spinal cord with the major organs, including ear and eye prostheses. The four main offshoots of implantable electronics, which this book discusses, are: The insertion of an implantable neural amplifier for accurate recording of neural signals for neuroengineering studies The use of implantable pulse generators for pacing the activi...

  1. Photon detection with CMOS sensors for fast imaging

    International Nuclear Information System (INIS)

    Baudot, J.; Dulinski, W.; Winter, M.; Barbier, R.; Chabanat, E.; Depasse, P.; Estre, N.

    2009-01-01

    Pixel detectors employed in high energy physics aim to detect single minimum ionizing particle with micrometric positioning resolution. Monolithic CMOS sensors succeed in this task thanks to a low equivalent noise charge per pixel of around 10 to 15 e - , and a pixel pitch varying from 10 to a few 10 s of microns. Additionally, due to the possibility for integration of some data treatment in the sensor itself, readout times of 100μs have been reached for 100 kilo-pixels sensors. These aspects of CMOS sensors are attractive for applications in photon imaging. For X-rays of a few keV, the efficiency is limited to a few % due to the thin sensitive volume. For visible photons, the back-thinned version of CMOS sensor is sensitive to low intensity sources, of a few hundred photons. When a back-thinned CMOS sensor is combined with a photo-cathode, a new hybrid detector results (EBCMOS) and operates as a fast single photon imager. The first EBCMOS was produced in 2007 and demonstrated single photon counting with low dark current capability in laboratory conditions. It has been compared, in two different biological laboratories, with existing CCD-based 2D cameras for fluorescence microscopy. The current EBCMOS sensitivity and frame rate is comparable to existing EMCCDs. On-going developments aim at increasing this frame rate by, at least, an order of magnitude. We report in conclusion, the first test of a new CMOS sensor, LUCY, which reaches 1000 frames per second.

  2. Contact CMOS imaging of gaseous oxygen sensor array.

    Science.gov (United States)

    Daivasagaya, Daisy S; Yao, Lei; Yi Yung, Ka; Hajj-Hassan, Mohamad; Cheung, Maurice C; Chodavarapu, Vamsy P; Bright, Frank V

    2011-10-01

    We describe a compact luminescent gaseous oxygen (O 2 ) sensor microsystem based on the direct integration of sensor elements with a polymeric optical filter and placed on a low power complementary metal-oxide semiconductor (CMOS) imager integrated circuit (IC). The sensor operates on the measurement of excited-state emission intensity of O 2 -sensitive luminophore molecules tris(4,7-diphenyl-1,10-phenanthroline) ruthenium(II) ([Ru(dpp) 3 ] 2+ ) encapsulated within sol-gel derived xerogel thin films. The polymeric optical filter is made with polydimethylsiloxane (PDMS) that is mixed with a dye (Sudan-II). The PDMS membrane surface is molded to incorporate arrays of trapezoidal microstructures that serve to focus the optical sensor signals on to the imager pixels. The molded PDMS membrane is then attached with the PDMS color filter. The xerogel sensor arrays are contact printed on top of the PDMS trapezoidal lens-like microstructures. The CMOS imager uses a 32 × 32 (1024 elements) array of active pixel sensors and each pixel includes a high-gain phototransistor to convert the detected optical signals into electrical currents. Correlated double sampling circuit, pixel address, digital control and signal integration circuits are also implemented on-chip. The CMOS imager data is read out as a serial coded signal. The CMOS imager consumes a static power of 320 µW and an average dynamic power of 625 µW when operating at 100 Hz sampling frequency and 1.8 V DC. This CMOS sensor system provides a useful platform for the development of miniaturized optical chemical gas sensors.

  3. Single-chip RF communications systems in CMOS

    DEFF Research Database (Denmark)

    Olesen, Ole

    1997-01-01

    The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone.......The paper describes the state of the art of the Nordic mobile communication project ConFront. This is a cooperation project with 3 Nordic universities and local industry. The ultimate goal is to make a CMOS one-chip mobile phone....

  4. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  5. Cochlear Implant

    Directory of Open Access Journals (Sweden)

    Mehrnaz Karimi

    1992-04-01

    Full Text Available People with profound hearing loss are not able to use some kinds of conventional amplifiers due to the nature of their loss . In these people, hearing sense is stimulated only when the auditory nerve is activated via electrical stimulation. This stimulation is possible through cochlear implant. In fact, for the deaf people who have good mental health and can not use surgical and medical treatment and also can not benefit from air and bone conduction hearing aids, this device is used if they have normal central auditory system. The basic parts of the device included: Microphone, speech processor, transmitter, stimulator and receiver, and electrode array.

  6. High-Voltage-Input Level Translator Using Standard CMOS

    Science.gov (United States)

    Yager, Jeremy A.; Mojarradi, Mohammad M.; Vo, Tuan A.; Blalock, Benjamin J.

    2011-01-01

    proposed integrated circuit would translate (1) a pair of input signals having a low differential potential and a possibly high common-mode potential into (2) a pair of output signals having the same low differential potential and a low common-mode potential. As used here, "low" and "high" refer to potentials that are, respectively, below or above the nominal supply potential (3.3 V) at which standard complementary metal oxide/semiconductor (CMOS) integrated circuits are designed to operate. The input common-mode potential could lie between 0 and 10 V; the output common-mode potential would be 2 V. This translation would make it possible to process the pair of signals by use of standard 3.3-V CMOS analog and/or mixed-signal (analog and digital) circuitry on the same integrated-circuit chip. A schematic of the circuit is shown in the figure. Standard 3.3-V CMOS circuitry cannot withstand input potentials greater than about 4 V. However, there are many applications that involve low-differential-potential, high-common-mode-potential input signal pairs and in which standard 3.3-V CMOS circuitry, which is relatively inexpensive, would be the most appropriate circuitry for performing other functions on the integrated-circuit chip that handles the high-potential input signals. Thus, there is a need to combine high-voltage input circuitry with standard low-voltage CMOS circuitry on the same integrated-circuit chip. The proposed circuit would satisfy this need. In the proposed circuit, the input signals would be coupled into both a level-shifting pair and a common-mode-sensing pair of CMOS transistors. The output of the level-shifting pair would be fed as input to a differential pair of transistors. The resulting differential current output would pass through six standoff transistors to be mirrored into an output branch by four heterojunction bipolar transistors. The mirrored differential current would be converted back to potential by a pair of diode-connected transistors

  7. Linearisation of RF Power Amplifiers

    DEFF Research Database (Denmark)

    Nielsen, Per Asbeck

    2001-01-01

    and an amplitude detection circuit is given. The purpose is to explore the limitation on commercial available parts and to recognize the challenges in polar loop linearisation. The design of a fabricated CMOS PA is presented. The design is carried out in a standard digital Epi-CMOS which allows integration...... different detectors were designed. Two non-linear detectors and one linear. The two former AM-detectors have been measured. Based on these measurements the achievable spectral leakage and error vector magnitude were predicted....

  8. Advancement of CMOS Doping Technology in an External Development Framework

    Science.gov (United States)

    Jain, Amitabh; Chambers, James J.; Shaw, Judy B.

    2011-01-01

    The consumer appetite for a rich multimedia experience drives technology development for mobile hand-held devices and the infrastructure to support them. Enhancements in functionality, speed, and user experience are derived from advancements in CMOS technology. The technical challenges in developing each successive CMOS technology node to support these enhancements have become increasingly difficult. These trends have motivated the CMOS business towards a collaborative approach based on strategic partnerships. This paper describes our model and experience of CMOS development, based on multi-dimensional industrial and academic partnerships. We provide to our process equipment, materials, and simulation partners, as well as to our silicon foundry partners, the detailed requirements for future integrated circuit products. This is done very early in the development cycle to ensure that these requirements can be met. In order to determine these fundamental requirements, we rely on a strategy that requires strong interaction between process and device simulation, physical and chemical analytical methods, and research at academic institutions. This learning is shared with each project partner to address integration and manufacturing issues encountered during CMOS technology development from its inception through product ramp. We utilize TI's core strengths in physical analysis, unit processes and integration, yield ramp, reliability, and product engineering to support this technological development. Finally, this paper presents examples of the advancement of CMOS doping technology for the 28 nm node and beyond through this development model.

  9. Design and Fabrication of Vertically-Integrated CMOS Image Sensors

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2011-01-01

    Technologies to fabricate integrated circuits (IC) with 3D structures are an emerging trend in IC design. They are based on vertical stacking of active components to form heterogeneous microsystems. Electronic image sensors will benefit from these technologies because they allow increased pixel-level data processing and device optimization. This paper covers general principles in the design of vertically-integrated (VI) CMOS image sensors that are fabricated by flip-chip bonding. These sensors are composed of a CMOS die and a photodetector die. As a specific example, the paper presents a VI-CMOS image sensor that was designed at the University of Alberta, and fabricated with the help of CMC Microsystems and Micralyne Inc. To realize prototypes, CMOS dies with logarithmic active pixels were prepared in a commercial process, and photodetector dies with metal-semiconductor-metal devices were prepared in a custom process using hydrogenated amorphous silicon. The paper also describes a digital camera that was developed to test the prototype. In this camera, scenes captured by the image sensor are read using an FPGA board, and sent in real time to a PC over USB for data processing and display. Experimental results show that the VI-CMOS prototype has a higher dynamic range and a lower dark limit than conventional electronic image sensors. PMID:22163860

  10. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  11. Microfabrication and Characterization of an Integrated 3-Axis CMOS-MEMS Accelerometer

    Directory of Open Access Journals (Sweden)

    Hongwei QU

    2007-10-01

    Full Text Available This paper reports the fabrication and characterization of a monolithically integrated 3-axis CMOS-MEMS accelerometer with a single proof mass. An improved microfabrication process has been developed to solve the structure overheating and particle contamination problems in the plasma etching processes of device fabrication. The whole device is made of bulk silicon except for some short thin films for electrical isolation, allowing large sensing capacitance and flat device structure. A low-noise, low-power amplifier is designed for each axis, which provides 40 dB on-chip amplification and consumes only 1 mW power. Quasi-static and dynamic characterization of the fabricated device has been performed. The measured sensitivities of the lateral- and z-axis accelerometers are 560 mV/g and 320 mV/g, respectively, which can be tuned by simply varying the amplitude of the modulation signal. The over-all noise floors of the lateral- and z-axis are 12 μg/ÖHz and 110 μg/ÖHz, respectively when tested at 200 Hz.

  12. Spiral-Shaped Piezoelectric MEMS Cantilever Array for Fully Implantable Hearing Systems

    Directory of Open Access Journals (Sweden)

    Péter Udvardi

    2017-10-01

    Full Text Available Fully implantable, self-powered hearing aids with no external unit could significantly increase the life quality of patients suffering severe hearing loss. This highly demanding concept, however, requires a strongly miniaturized device which is fully implantable in the middle/inner ear and includes the following components: frequency selective microphone or accelerometer, energy harvesting device, speech processor, and cochlear multielectrode. Here we demonstrate a low volume, piezoelectric micro-electromechanical system (MEMS cantilever array which is sensitive, even in the lower part of the voice frequency range (300–700 Hz. The test array consisting of 16 cantilevers has been fabricated by standard bulk micromachining using a Si-on-Insulator (SOI wafer and aluminum nitride (AlN as a complementary metal-oxide-semiconductor (CMOS and biocompatible piezoelectric material. The low frequency and low device footprint are ensured by Archimedean spiral geometry and Si seismic mass. Experimentally detected resonance frequencies were validated by an analytical model. The generated open circuit voltage (3–10 mV is sufficient for the direct analog conversion of the signals for cochlear multielectrode implants.

  13. A 128 x 128 CMOS Active Pixel Image Sensor for Highly Integrated Imaging Systems

    Science.gov (United States)

    Mendis, Sunetra K.; Kemeny, Sabrina E.; Fossum, Eric R.

    1993-01-01

    A new CMOS-based image sensor that is intrinsically compatible with on-chip CMOS circuitry is reported. The new CMOS active pixel image sensor achieves low noise, high sensitivity, X-Y addressability, and has simple timing requirements. The image sensor was fabricated using a 2 micrometer p-well CMOS process, and consists of a 128 x 128 array of 40 micrometer x 40 micrometer pixels. The CMOS image sensor technology enables highly integrated smart image sensors, and makes the design, incorporation and fabrication of such sensors widely accessible to the integrated circuit community.

  14. CMOS Compatibility of a Micromachining Process Developed for Semiconductor Neural Probe

    National Research Council Canada - National Science Library

    An, S

    2001-01-01

    .... Test transistor patterns generated using standard CMOS fabrication line were exposed to a post-CMOS probe making process including dielectric deposition, gold metalization and the dry etching step...

  15. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  16. A CMOS transconductance-C filter technique for very high frequencies

    NARCIS (Netherlands)

    Nauta, Bram

    1992-01-01

    CMOS circuits for integrated analog filters at very high frequencies, based on transconductance-C integrators, are presented. First a differential transconductance element based on CMOS inverters is described. With this circuit a linear, tunable integrator for very-high-frequency integrated filters

  17. Amplifier Distortion

    Science.gov (United States)

    Keeports, David

    2006-12-01

    By definition, a high fidelity amplifier's instantaneous output voltage is directly proportional to its instantaneous input voltage. While high fidelity is generally valued in the amplification of recorded music, nonlinearity, also known as distortion, is desirable in the amplification of some musical instruments. In particular, guitar amplifiers exploit nonlinearity to increase both the harmonic content and sustain of a guitar's sound. I will discuss how both modifications in sound result from saturation of triode tubes and transistors. Additionally, I will describe the difference in the symmetry of saturation curves for transistors and tubes and the reason why tube guitar amplifiers are generally considered to be superior to solid-state amplifiers. Finally, I will discuss attempts to use solid-state electronics to replicate the sound of tube amplifiers.

  18. An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

    International Nuclear Information System (INIS)

    Fiorini, C.; Porro, M.

    2006-01-01

    We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

  19. Nano-electromechanical switch-CMOS hybrid technology and its applications.

    Science.gov (United States)

    Lee, B H; Hwang, H J; Cho, C H; Lim, S K; Lee, S Y; Hwang, H

    2011-01-01

    Si-based CMOS technology is facing a serious challenge in terms of power consumption and variability. The increasing costs associated with physical scaling have motivated a search for alternative approaches. Hybridization of nano-electromechanical (NEM)-switch and Si-based CMOS devices has shown a theoretical feasibility for power management, but a huge technical gap must be bridged before a nanoscale NEM switch can be realized due to insufficient material development and the limited understanding of its reliability characteristics. These authors propose the use of a multilayer graphene as a nanoscale cantilever material for a nanoscale NEM switchwith dimensions comparable to those of the state-of-the-art Si-based CMOS devices. The optimal thickness for the multilayer graphene (about five layers) is suggested based on an analytical model. Multilayer graphene can provide the highest Young's modulus among the known electrode materials and a yielding strength that allows more than 15% bending. Further research on material screening and device integration is needed, however, to realize the promises of the hybridization of NEM-switch and Si-based CMOS devices.

  20. Development of radiation hard CMOS active pixel sensors for HL-LHC

    International Nuclear Information System (INIS)

    Pernegger, Heinz

    2016-01-01

    New pixel detectors, based on commercial high voltage and/or high resistivity full CMOS processes, hold promise as next-generation active pixel sensors for inner and intermediate layers of the upgraded ATLAS tracker. The use of commercial CMOS processes allow cost-effective detector construction and simpler hybridisation techniques. The paper gives an overview of the results obtained on AMS-produced CMOS sensors coupled to the ATLAS Pixel FE-I4 readout chips. The SOI (silicon-on-insulator) produced sensors by XFAB hold great promise as radiation hard SOI-CMOS sensors due to their combination of partially depleted SOI transistors reducing back-gate effects. The test results include pre-/post-irradiation comparison, measurements of charge collection regions as well as test beam results.

  1. NINO an ultrafast low-power front-end amplifier discriminator for the time-of-flight detector in the ALICE experiment

    CERN Document Server

    Anghinolfi, F; Krummenacher, F; Usenko, E; Williams, M C S

    2004-01-01

    An ultrafast front-end preamplifier-discriminator chip called NINO has been developed for use in the ALICE time-of-flight detector. The chip has eight channels. Each channel is designed with an amplifier with less than 1-ns peaking time, a discriminator with a minimum detection threshold of 10 fC and an output stage. The output pulse has minimum time jitter (less than 25 ps) on the front edge, and the pulsewidth is dependent of the input signal charge. Each channel consumes 27 mW, and the eight channels fit in a 2*4 mm/sup 2/ ASIC processed in IBM 0.25- mu m CMOS technology. (3 refs).

  2. NINO, an ultra-fast, low-power, front-end amplifier discriminator for the Time-Of-Flight detector in ALICE experiment

    CERN Document Server

    Anghinolfi, F; Krummenacher, F; Usenko, E; Williams, M C S

    2004-01-01

    An ultra fast front-end preamplifier-discriminator chip NINO has been developed for use in the ALICE Time-Of-Flight detector. The chip has 8 channels. Each channel is designed with an amplifier with less than 1 ns peaking time, a discriminator with a minimum detection threshold of 10fC and an output stage. The output pulse has minimum time jitter (less than 25ps) on the front edge, and the pulse width is dependent of the input signal charge. Each channel consumes 27mW, and the 8 channels fit in a 2*4mm/sup 2/ ASIC processed in IBM 0.2 mu m CMOS technology. (3 refs).

  3. In vivo characterization of the electrophysiological and astrocytic responses to a silicon neuroprobe implanted in the mouse neocortex.

    Science.gov (United States)

    Mols, Katrien; Musa, Silke; Nuttin, Bart; Lagae, Liesbet; Bonin, Vincent

    2017-11-15

    Silicon neuroprobes hold great potential for studies of large-scale neural activity and brain computer interfaces, but data on brain response in chronic implants is limited. Here we explored with in vivo cellular imaging the response to multisite silicon probes for neural recordings. We tested a chronic implant for mice consisting of a CMOS-compatible silicon probe rigidly implanted in the cortex under a cranial imaging window. Multiunit recordings of cortical neurons with the implant showed no degradation of electrophysiological signals weeks after implantation (mean spike and noise amplitudes of 186 ± 42 µV pp and 16 ± 3.2 µV rms , respectively, n = 5 mice). Two-photon imaging through the cranial window allowed longitudinal monitoring of fluorescently-labeled astrocytes from the second week post implantation for 8 weeks (n = 3 mice). The imaging showed a local increase in astrocyte-related fluorescence that remained stable from the second to the tenth week post implantation. These results demonstrate that, in a standard electrophysiology protocol in mice, rigidly implanted silicon probes can provide good short to medium term chronic recording performance with a limited astrocyte inflammatory response. The precise factors influencing the response to silicon probe implants remain to be elucidated.

  4. Pre-Clinical Tests of an Integrated CMOS Biomolecular Sensor for Cardiac Diseases Diagnosis.

    Science.gov (United States)

    Lee, Jen-Kuang; Wang, I-Shun; Huang, Chi-Hsien; Chen, Yih-Fan; Huang, Nien-Tsu; Lin, Chih-Ting

    2017-11-26

    Coronary artery disease and its related complications pose great threats to human health. In this work, we aim to clinically evaluate a CMOS field-effect biomolecular sensor for cardiac biomarkers, cardiac-specific troponin-I (cTnI), N -terminal prohormone brain natriuretic peptide (NT-proBNP), and interleukin-6 (IL-6). The CMOS biosensor is implemented via a standard commercialized 0.35 μm CMOS process. To validate the sensing characteristics, in buffer conditions, the developed CMOS biosensor has identified the detection limits of IL-6, cTnI, and NT-proBNP as being 45 pM, 32 pM, and 32 pM, respectively. In clinical serum conditions, furthermore, the developed CMOS biosensor performs a good correlation with an enzyme-linked immuno-sorbent assay (ELISA) obtained from a hospital central laboratory. Based on this work, the CMOS field-effect biosensor poses good potential for accomplishing the needs of a point-of-care testing (POCT) system for heart disease diagnosis.

  5. A novel multi-actuation CMOS RF MEMS switch

    Science.gov (United States)

    Lee, Chiung-I.; Ko, Chih-Hsiang; Huang, Tsun-Che

    2008-12-01

    This paper demonstrates a capacitive shunt type RF MEMS switch, which is actuated by electro-thermal actuator and electrostatic actuator at the same time, and than latching the switching status by electrostatic force only. Since thermal actuators need relative low voltage compare to electrostatic actuators, and electrostatic force needs almost no power to maintain the switching status, the benefits of the mechanism are very low actuation voltage and low power consumption. Moreover, the RF MEMS switch has considered issues for integrated circuit compatible in design phase. So the switch is fabricated by a standard 0.35um 2P4M CMOS process and uses wet etching and dry etching technologies for postprocess. This compatible ability is important because the RF characteristics are not only related to the device itself. If a packaged RF switch and a packaged IC wired together, the parasitic capacitance will cause the problem for optimization. The structure of the switch consists of a set of CPW transmission lines and a suspended membrane. The CPW lines and the membrane are in metal layers of CMOS process. Besides, the electro-thermal actuators are designed by polysilicon layer of the CMOS process. So the RF switch is only CMOS process layers needed for both electro-thermal and electrostatic actuations in switch. The thermal actuator is composed of a three-dimensional membrane and two heaters. The membrane is a stacked step structure including two metal layers in CMOS process, and heat is generated by poly silicon resistors near the anchors of membrane. Measured results show that the actuation voltage of the switch is under 7V for electro-thermal added electrostatic actuation.

  6. Low-Power Amplifier-Discriminators for High Time Resolution Detection

    CERN Document Server

    Despeisse, M; Anghinolfi, F; Tiuraniemi, S; Osmic, F; Riedler, P; Kluge, A; Ceccucci, A

    2009-01-01

    Low-power amplifier-discriminators based on a so-called NINO architecture have been developed with high time resolution for the readout of radiation detectors. Two different circuits were integrated in the NINO13 chip, processed in IBM 130 nm CMOS technology. The LCO version (Low Capacitance and consumption Optimization) was designed for potential use as front-end electronics in the Gigatracker of the NA62 experiment at CERN. It was developed as pixel readout for solid-state pixel detectors to permit minimum ionizing particle detection with less than 180 ps rms resolution per pixel on the output pulse, for power consumption below 300 mu W per pixel. The HCO version (High Capacitance Optimization) was designed with 4 mW power consumption per channel to provide timing resolution below 20 ps rms on the output pulse, for charges above 10 fC. Results presented show the potential of the LCO and HCO circuits for the precise timing readout of solid-state detectors, vacuum tubes or gas detectors, for applications in h...

  7. Wireless neural recording with single low-power integrated circuit.

    Science.gov (United States)

    Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

    2009-08-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

  8. Integrated 60GHz RF beamforming in CMOS

    CERN Document Server

    Yu, Yikun; van Roermund, Arthur H M

    2011-01-01

    ""Integrated 60GHz RF Beamforming in CMOS"" describes new concepts and design techniques that can be used for 60GHz phased array systems. First, general trends and challenges in low-cost high data-rate 60GHz wireless system are studied, and the phased array technique is introduced to improve the system performance. Second, the system requirements of phase shifters are analyzed, and different phased array architectures are compared. Third, the design and implementation of 60GHz passive and active phase shifters in a CMOS technology are presented. Fourth, the integration of 60GHz phase shifters

  9. Challenges & Roadmap for Beyond CMOS Computing Simulation.

    Energy Technology Data Exchange (ETDEWEB)

    Rodrigues, Arun F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Frank, Michael P. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-12-01

    Simulating HPC systems is a difficult task and the emergence of “Beyond CMOS” architectures and execution models will increase that difficulty. This document presents a “tutorial” on some of the simulation challenges faced by conventional and non-conventional architectures (Section 1) and goals and requirements for simulating Beyond CMOS systems (Section 2). These provide background for proposed short- and long-term roadmaps for simulation efforts at Sandia (Sections 3 and 4). Additionally, a brief explanation of a proof-of-concept integration of a Beyond CMOS architectural simulator is presented (Section 2.3).

  10. CMOS compatible fabrication process of MEMS resonator for timing reference and sensing application

    Science.gov (United States)

    Huynh, Duc H.; Nguyen, Phuong D.; Nguyen, Thanh C.; Skafidas, Stan; Evans, Robin

    2015-12-01

    CMOS IC. This device is expected to operate in hundreds of Mhz frequency range; quality factor surpasses 10000 and series motional impedance low enough that could be matching into conventional system without enormous effort. This MEMS resonator can be used in the design of many blocks in wireless and RF (Radio Frequency) systems such as low phase noise oscillator, band pass filter, power amplifier and in many sensing application.

  11. VLSI scaling methods and low power CMOS buffer circuit

    International Nuclear Information System (INIS)

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  12. Characterization of active CMOS pixel sensors on high resistive substrate

    Energy Technology Data Exchange (ETDEWEB)

    Hirono, Toko; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Bonn (Germany)

    2016-07-01

    Active CMOS pixel sensors are very attractive as radiation imaging pixel detector because they do not need cost-intensive fine pitch bump bonding. High radiation tolerance and time resolution are required to apply those sensors to upcoming particle physics experiments. To achieve these requirements, the active CMOS pixel sensors were developed on high resistive substrates. Signal charges are collected faster by drift in high resistive substrates than in standard low resistive substrates yielding also a higher radiation tolerance. A prototype of the active CMOS pixel sensor has been fabricated in the LFoundry 150 nm CMOS process on 2 kΩcm substrate. This prototype chip was thinned down to 300 μm and the backside has been processed and can contacted by an aluminum contact. The breakdown voltage is around -115 V, and the depletion width has been measured to be as large as 180 μm at a bias voltage of -110 V. Gain and noise of the readout circuitry agree with the designed values. Performance tests in the lab and test beam have been done before and after irradiation with X-rays and neutrons. In this presentation, the measurement results of the active CMOS prototype sensors are shown.

  13. New Criteria of Indication and Selection of Patients to Cochlear Implant

    Directory of Open Access Journals (Sweden)

    André L. L. Sampaio

    2011-01-01

    Full Text Available Numerous changes continue to occur in cochlear implant candidacy. In general, these have been accompanied by concomitant and satisfactory changes in surgical techniques. Together, this has advanced the utility and safety of cochlear implantation. Most devices are now approved for use in patients with severe to profound unilateral hearing loss rather then the prior requirement of a bilateral profound loss. Furthermore, studies have begun utilizing short electrode arrays for shallow insertion in patients with considerable low-frequency residual hearing. This technique will allow the recipient to continue to use acoustically amplified hearing for the low frequencies simultaneously with a cochlear implant for the high frequencies. The advances in design of, and indications for, cochlear implants have been matched by improvements in surgical techniques and decrease in complications. The resulting improvements in safety and efficacy have further encouraged the use of these devices. This paper will review the new concepts in the candidacy of cochlear implant. Medline data base was used to search articles dealing with the following topics: cochlear implant in younger children, cochlear implant and hearing preservation, cochlear implant for unilateral deafness and tinnitus, genetic hearing loss and cochlear implant, bilateral cochlear implant, neuropathy and cochlear implant and neural plasticity, and the selection of patients for cochlear implant.

  14. Suppression of boron diffusion using carbon co-implantation in DRAM

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Suk Hun [School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon-si 440-746 (Korea, Republic of); Park, Se Geun; Kim, Shin Deuk; Jung, Hyuck-Chai; Kim, Il Gweon [Memory Division, Samsung Electronics Co. Ltd., Hwasung-si 445-330 (Korea, Republic of); Kang, Dong-Ho [School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon-si 440-746 (Korea, Republic of); Kim, Dae Jung; Lee, Kyu Pil; Choi, Joo Sun [Memory Division, Samsung Electronics Co. Ltd., Hwasung-si 445-330 (Korea, Republic of); Baek, Jung-Woo [Industrial Engineering Department, Chosun University, Gwangju-si 501-759 (Korea, Republic of); Choi, Moonsuk [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791, South Korea (Korea, Republic of); Park, Yongkook [School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon-si 440-746 (Korea, Republic of); Choi, Changhwan, E-mail: cchoi@hanyang.ac.kr [Division of Materials Science and Engineering, Hanyang University, Seoul 133-791, South Korea (Korea, Republic of); Park, Jin-Hong, E-mail: jhpark9@skku.edu [School of Electronic and Electrical Engineering, Sungkyunkwan University, Suwon-si 440-746 (Korea, Republic of)

    2016-10-15

    Highlights: • The impact of Ge + C co-implantation on dopant diffusion was investigated. • DIBL and V{sub TH} variation was improved by Ge + C co-implantation. • The V{sub TH} mismatch and the write characteristics were improved in the DRAM device. - Abstract: In this paper, germanium pre-amorphization implantation (PAI) and carbon co-implantation (Ge + C co-IIP) were applied to suppress boron diffusion. The corresponding characteristics were investigated in terms of the dopant diffusion, device performance, and its application to dynamic random access memory (DRAM). A shallow dopant profile was indicated and the threshold voltage (V{sub TH}) was reduced by approximately 45 mV by Ge + C co-IIP. In the DRAM device, the V{sub TH} mismatch of the sense amplifier NMOS pairs was reduced by approximately 15% and the write characteristics were improved two-fold.

  15. Performance of capacitively coupled active pixel sensors in 180 nm HV-CMOS technology after irradiation to HL-LHC fluences

    International Nuclear Information System (INIS)

    Feigl, S

    2014-01-01

    In this ATLAS upgrade R and D project, we explore the concept of using a deep-submicron HV-CMOS process to produce a drop-in replacement for traditional radiation-hard silicon sensors. Such active sensors contain simple circuits, e.g. amplifiers and discriminators, but still require a traditional (pixel or strip) readout chip. This approach yields most advantages of MAPS (improved resolution, reduced cost and material budget, etc.), without the complication of full integration on a single chip. After outlining the basic design of the HV2FEI4 test ASIC, results after irradiation with X-rays to 862 Mrad and neutrons up to 10 16 (1 MeV n eq )/cm 2 will be presented. Finally, a brief outlook on further development plans is given

  16. Design of CMOS RFIC ultra-wideband impulse transmitters and receivers

    CERN Document Server

    Nguyen, Cam

    2017-01-01

    This book presents the design of ultra-wideband (UWB) impulse-based transmitter and receiver frontends, operating within the 3.1-10.6 GHz frequency band, using CMOS radio-frequency integrated-circuits (RFICs). CMOS RFICs are small, cheap, low power devices, better suited for direct integration with digital ICs as compared to those using III-V compound semiconductor devices. CMOS RFICs are thus very attractive for RF systems and, in fact, the principal choice for commercial wireless markets.  The book comprises seven chapters. The first chapter gives an introduction to UWB technology and outlines its suitability for high resolution sensing and high-rate, short-range ad-hoc networking and communications. The second chapter provides the basics of CMOS RFICs needed for the design of the UWB RFIC transmitter and receiver presented in this book. It includes the design fundamentals, lumped and distributed elements for RFIC, layout, post-layout simulation, and measurement. The third chapter discusses the basics of U...

  17. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  18. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    CERN Document Server

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  19. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  20. VHF NEMS-CMOS piezoresistive resonators for advanced sensing applications

    Science.gov (United States)

    Arcamone, Julien; Dupré, Cécilia; Arndt, Grégory; Colinet, Eric; Hentz, Sébastien; Ollier, Eric; Duraffourg, Laurent

    2014-10-01

    This work reports on top-down nanoelectromechanical resonators, which are among the smallest resonators listed in the literature. To overcome the fact that their electromechanical transduction is intrinsically very challenging due to their very high frequency (100 MHz) and ultimate size (each resonator is a 1.2 μm long, 100 nm wide, 20 nm thick silicon beam with 100 nm long and 30 nm wide piezoresistive lateral nanowire gauges), they have been monolithically integrated with an advanced fully depleted SOI CMOS technology. By advantageously combining the unique benefits of nanomechanics and nanoelectronics, this hybrid NEMS-CMOS device paves the way for novel breakthrough applications, such as NEMS-based mass spectrometry or hybrid NEMS/CMOS logic, which cannot be fully implemented without this association.

  1. Recent developments with CMOS SSPM photodetectors

    Energy Technology Data Exchange (ETDEWEB)

    Stapels, Christopher J. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)], E-mail: CStapels@RMDInc.com; Barton, Paul [University of Michigan, Ann Arbor, MI (United States); Johnson, Erik B. [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Wehe, David K. [University of Michigan, Ann Arbor, MI (United States); Dokhale, Purushottam; Shah, Kanai [Radiation Monitoring Devices, Inc., Watertown, MA (United States); Augustine, Frank L. [Augustine Engineering, Encinitas, CA (United States); Christian, James F. [Radiation Monitoring Devices, Inc., Watertown, MA (United States)

    2009-10-21

    Experiments and simulations using various solid-state photomultiplier (SSPM) designs have been performed to evaluate pixel layouts and explore design choices. SPICE simulations of a design for position-sensing SSPMs showed charge division in the resistor network, and anticipated timing performance of the device. The simulation results predict good position information for resistances in the range of 1-5 k{omega} and 150-{omega} preamplifier input impedance. Back-thinning of CMOS devices can possibly increase the fill factor to 100%, improve spectral sensitivity, and allow for the deposition of anti-reflective coatings after fabrication. We report initial results from back illuminating a CMOS SSPM, and single Geiger-mode avalanche photodiode (GPD) pixels, thinned to 50 {mu}m.

  2. Electromagnetic Investigation of a CMOS MEMS Inductive Microphone

    Directory of Open Access Journals (Sweden)

    Farès TOUNSI

    2009-09-01

    Full Text Available This paper presents a detailed electromagnetic modeling for a new structure of a monolithic CMOS micromachined inductive microphone. We have shown, that the use of an alternative current (AC in the primary fixed inductor results in a substantially higher induced voltage in the secondary inductor comparing to the case when a direct current (DC is used. The expected increase of the induced voltage can be expressed by a voltage ratio of AC and DC solutions that is in the range of 3 to 6. A prototype fabrication of this microphone has been realized using a combination of standard CMOS 0.6 µm process with a CMOS-compatible post-process consisting in a bulk micromachining technology. The output voltage of the electrodynamic microphone that achieves the µV range can be increased by the use of the symmetric dual-layer spiral inductor structure.

  3. Fast CMOS binary front-end for silicon strip detectors at LHC experiments

    CERN Document Server

    Kaplon, Jan

    2004-01-01

    We present the design and the test results of a front-end circuit developed in a 0.25 mu m CMOS technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front-end for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time and two-stage differential discriminator. Particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e/sup -/ ENC has been achieved for 300 mu A bias current in the input transistor, which is comparable with levels achieved in the past for a front-end using bipolar input transistor. The total supply current of the front-end is 600 mu A and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms.

  4. High-content analysis of single cells directly assembled on CMOS sensor based on color imaging.

    Science.gov (United States)

    Tanaka, Tsuyoshi; Saeki, Tatsuya; Sunaga, Yoshihiko; Matsunaga, Tadashi

    2010-12-15

    A complementary metal oxide semiconductor (CMOS) image sensor was applied to high-content analysis of single cells which were assembled closely or directly onto the CMOS sensor surface. The direct assembling of cell groups on CMOS sensor surface allows large-field (6.66 mm×5.32 mm in entire active area of CMOS sensor) imaging within a second. Trypan blue-stained and non-stained cells in the same field area on the CMOS sensor were successfully distinguished as white- and blue-colored images under white LED light irradiation. Furthermore, the chemiluminescent signals of each cell were successfully visualized as blue-colored images on CMOS sensor only when HeLa cells were placed directly on the micro-lens array of the CMOS sensor. Our proposed approach will be a promising technique for real-time and high-content analysis of single cells in a large-field area based on color imaging. Copyright © 2010 Elsevier B.V. All rights reserved.

  5. CMOS-based avalanche photodiodes for direct particle detection

    International Nuclear Information System (INIS)

    Stapels, Christopher J.; Squillante, Michael R.; Lawrence, William G.; Augustine, Frank L.; Christian, James F.

    2007-01-01

    Active Pixel Sensors (APSs) in complementary metal-oxide-semiconductor (CMOS) technology are augmenting Charge-Coupled Devices (CCDs) as imaging devices and cameras in some demanding optical imaging applications. Radiation Monitoring Devices are investigating the APS concept for nuclear detection applications and has successfully migrated avalanche photodiode (APD) pixel fabrication to a CMOS environment, creating pixel detectors that can be operated with internal gain as proportional detectors. Amplification of the signal within the diode allows identification of events previously hidden within the readout noise of the electronics. Such devices can be used to read out a scintillation crystal, as in SPECT or PET, and as direct-conversion particle detectors. The charge produced by an ionizing particle in the epitaxial layer is collected by an electric field within the diode in each pixel. The monolithic integration of the readout circuitry with the pixel sensors represents an improved design compared to the current hybrid-detector technology that requires wire or bump bonding. In this work, we investigate designs for CMOS APD detector elements and compare these to typical values for large area devices. We characterize the achievable detector gain and the gain uniformity over the active area. The excess noise in two different pixel structures is compared. The CMOS APD performance is demonstrated by measuring the energy spectra of X-rays from 55 Fe

  6. The total dose effects on the 1/f noise of deep submicron CMOS transistors

    International Nuclear Information System (INIS)

    Hu Rongbin; Wang Yuxin; Lu Wu

    2014-01-01

    Using 0.18 μm CMOS transistors, the total dose effects on the 1/f noise of deep-submicron CMOS transistors are studied for the first time in mainland China. From the experimental results and the theoretic analysis, we realize that total dose radiation causes a lot of trapped positive charges in STI (shallow trench isolation) SiO 2 layers, which induces a current leakage passage, increasing the 1/f noise power of CMOS transistors. In addition, we design some radiation-hardness structures on the CMOS transistors and the experimental results show that, until the total dose achieves 750 krad, the 1/f noise power of the radiation-hardness CMOS transistors remains unchanged, which proves our conclusion. (semiconductor devices)

  7. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  8. PERFORMANCE OF DIFFERENT CMOS LOGIC STYLES FOR LOW POWER AND HIGH SPEED

    OpenAIRE

    Sreenivasa Rao.Ijjada; Ayyanna.G; G.Sekhar Reddy; Dr.V.Malleswara Rao

    2011-01-01

    Designing high-speed low-power circuits with CMOS technology has been a major research problem for many years. Several logic families have been proposed and used to improve circuit performance beyond that of conventional static CMOS family. Fast circuit families are becoming attractive in deep sub micron technologies since the performance benefits obtained from process scaling are decreasing as feature size decreases. This paper presents CMOS differential circuit families such as Dual rail do...

  9. Out-of-Plane Strain Effects on Physically Flexible FinFET CMOS

    KAUST Repository

    Ghoneim, Mohamed T.; Alfaraj, Nasir; Torres-Sevilla, Galo A.; Fahad, Hossain M.; Hussain, Muhammad Mustafa

    2016-01-01

    . The devices were fabricated using the state-of-the-art CMOS technology and then transformed into flexible form by using a CMOS-compatible maskless deep reactive-ion etching technique. Mechanical out-of-plane stresses (compressive and tensile) were applied

  10. Application of CMOS Technology to Silicon Photomultiplier Sensors

    Science.gov (United States)

    D’Ascenzo, Nicola; Zhang, Xi; Xie, Qingguo

    2017-01-01

    We use the 180 nm GLOBALFOUNDRIES (GF) BCDLite CMOS process for the production of a silicon photomultiplier prototype. We study the main characteristics of the developed sensor in comparison with commercial SiPMs obtained in custom technologies and other SiPMs developed with CMOS-compatible processes. We support our discussion with a transient modeling of the detection process of the silicon photomultiplier as well as with a series of static and dynamic experimental measurements in dark and illuminated environments. PMID:28946675

  11. Epoxy Chip-in-Carrier Integration and Screen-Printed Metalization for Multichannel Microfluidic Lab-on-CMOS Microsystems.

    Science.gov (United States)

    Li, Lin; Yin, Heyu; Mason, Andrew J

    2018-04-01

    The integration of biosensors, microfluidics, and CMOS instrumentation provides a compact lab-on-CMOS microsystem well suited for high throughput measurement. This paper describes a new epoxy chip-in-carrier integration process and two planar metalization techniques for lab-on-CMOS that enable on-CMOS electrochemical measurement with multichannel microfluidics. Several design approaches with different fabrication steps and materials were experimentally analyzed to identify an ideal process that can achieve desired capability with high yield and low material and tool cost. On-chip electrochemical measurements of the integrated assembly were performed to verify the functionality of the chip-in-carrier packaging and its capability for microfluidic integration. The newly developed CMOS-compatible epoxy chip-in-carrier process paves the way for full implementation of many lab-on-CMOS applications with CMOS ICs as core electronic instruments.

  12. Effect of telecobalt irradiation on the function of implantable pacemaker

    International Nuclear Information System (INIS)

    Toyoda, Michiaki

    1986-01-01

    In patients implanted with a pacemaker, radiotherapy may be chosen as the treatment when malignant tumor is complicated. Therefore, on the assumption that the pacemaker apparatus is exposed to X-ray, 21 lithium cells used for CMOS or TTL circuit were collected before expiration date and irradiated with 60 Co. The pacemaker used were 10 apparatuses of unprogrammed model VVI, 9 apparatuses of programmed model VVI and 2 apparatuses programmed model DVI. Irradiation was done up to 1,000 rads in dividing doses or at 1,000 rads as a single dose. Observations were made for effects on intervals, amplitude and wave shape of stimula to pacemaker, power, sensitivity, refractory phase, and program functions. In conclusion, it was found that pacemaker is sure to be affected considerably for various functions, although no functional arrest occurs, under irradiation up to 1,000 rads of 60 Co in dividing dose. When irradiation at 1,000 rads was given as a single dose, dysfunctions of pacemaker developed in some cases indicating that direct irradiation at high doses is contraindicated for pacemakers using much of LSI-CMOS. (author)

  13. CMOS SPDT switch for WLAN applications

    International Nuclear Information System (INIS)

    Bhuiyan, M A S; Reaz, M B I; Rahman, L F; Minhad, K N

    2015-01-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal. (paper)

  14. Cmos spdt switch for wlan applications

    Science.gov (United States)

    Bhuiyan, M. A. S.; Reaz, M. B. I.; Rahman, L. F.; Minhad, K. N.

    2015-04-01

    WLAN has become an essential part of our today's life. The advancement of CMOS technology let the researchers contribute low power, size and cost effective WLAN devices. This paper proposes a single pole double through transmit/receive (T/R) switch for WLAN applications in 0.13 μm CMOS technology. The proposed switch exhibit 1.36 dB insertion loss, 25.3 dB isolation and 24.3 dBm power handling capacity. Moreover, it only dissipates 786.7 nW power per cycle. The switch utilizes only transistor aspect ratio optimization and resistive body floating technique to achieve such desired performance. In this design the use of bulky inductor and capacitor is avoided to evade imposition of unwanted nonlinearities to the communication signal.

  15. A piezoresistive cantilever for lateral force detection fabricated by a monolithic post-CMOS process

    International Nuclear Information System (INIS)

    Ji Xu; Li Zhihong; Li Juan; Wang Yangyuan; Xi Jianzhong

    2008-01-01

    This paper presents a post-CMOS process to monolithically integrate a piezoresistive cantilever for lateral force detection and signal processing circuitry. The fabrication process includes a standard CMOS process and one more lithography step to micromachine the cantilever structure in the post-CMOS process. The piezoresistors are doped in the CMOS process but defined in the post-CMOS micromachining process without any extra process required. A partially split cantilever configuration is developed for the lateral force detection. The piezoresistors are self-aligned to the split cantilever, and therefore the width of the beam is only limited by lithography. Consequently, this kind of cantilever potentially has a high resolution. The preliminary experimental results show expected performances of the fabricated piezoresistors and electronic circuits

  16. Auto-Zero Differential Amplifier

    Science.gov (United States)

    Quilligan, Gerard T. (Inventor); Aslam, Shahid (Inventor)

    2017-01-01

    An autozero amplifier may include a window comparator network to monitor an output offset of a differential amplifier. The autozero amplifier may also include an integrator to receive a signal from a latched window comparator network, and send an adjustment signal back to the differential amplifier to reduce an offset of the differential amplifier.

  17. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Ristic, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

  18. Radiation Induced Fault Analysis for Wide Temperature BiCMOS Circuits, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — State of the art Radiation Hardened by Design (RHBD) techniques do not account for wide temperature variations in BiCMOS process. Silicon-Germanium BiCMOS process...

  19. CMOS voltage references an analytical and practical perspective

    CERN Document Server

    Kok, Chi-Wah

    2013-01-01

    A practical overview of CMOS circuit design, this book covers the technology, analysis, and design techniques of voltage reference circuits.  The design requirements covered follow modern CMOS processes, with an emphasis on low power, low voltage, and low temperature coefficient voltage reference design. Dedicating a chapter to each stage of the design process, the authors have organized the content to give readers the tools they need to implement the technologies themselves. Readers will gain an understanding of device characteristics, the practical considerations behind circuit topology,

  20. Latch-up and radiation integrated circuit--LURIC: a test chip for CMOS latch-up investigation

    International Nuclear Information System (INIS)

    Estreich, D.B.

    1978-11-01

    A CMOS integrated circuit test chip (Latch-Up and Radiation Integrated Circuit--LURIC) designed for CMOS latch-up and radiation effects research is described. The purpose of LURIC is (a) to provide information on the physics of CMOS latch-up, (b) to study the layout dependence of CMOS latch-up, and (c) to provide special latch-up test structures for the development and verification of a latch-up model. Many devices and test patterns on LURIC are also well suited for radiation effects studies. LURIC contains 86 devices and related test structures. A 12-layer mask set allows both metal gate CMOS and silicon gate ELA (Extended Linear Array) CMOS to be fabricated. Six categories of test devices and related test structures are included. These are (a) the CD4007 metal gate CMOS IC with auxiliary test structures, (b) ELA CMOS cells, (c) field-aided lateral pnp transistors, (d) p-well and substrate spreading resistance test structures, (e) latch-up test structures (simplified symmetrical latch-up paths), and (f) support test patterns (e.g., MOS capacitors, p + n diodes, MOS test transistors, van der Pauw and Kelvin contact resistance test patterns, etc.). A standard probe pattern array has been used on all twenty-four subchips for testing convenience

  1. George E. Pake Prize Lecture: CMOS Technology Roadmap: Is Scaling Ending?

    Science.gov (United States)

    Chen, Tze-Chiang (T. C.)

    The development of silicon technology has been based on the principle of physics and driven by the system needs. Traditionally, the system needs have been satisfied by the increase in transistor density and performance, as suggested by Moore's Law and guided by ''Dennard CMOS scaling theory''. As the silicon industry moves towards the 14nm node and beyond, three of the most important challenges facing Moore's Law and continued CMOS scaling are the growing standby power dissipation, the increasing variability in device characteristics and the ever increasing manufacturing cost. Actually, the first two factors are the embodiments of CMOS approaching atomistic and quantum-mechanical physics boundaries. Industry directions for addressing these challenges are also developing along three primary approaches: Extending silicon scaling through innovations in materials and device structure, expanding the level of integration through three-dimensional structures comprised of through-silicon-vias holes and chip stacking in order to enhance functionality and parallelism and exploring post-silicon CMOS innovation with new nano-devices based on distinctly different principles of physics, new materials and new processes such as spintronics, carbon nanotubes and nanowires. Hence, the infusion of new materials, innovative integration and novel device structures will continue to extend CMOS technology scaling for at least another decade.

  2. The review of radiation effects of γ total dose in CMOS circuits

    International Nuclear Information System (INIS)

    Chen Panxun; Gao Wenming; Xie Zeyuan; Mi Bang

    1992-01-01

    Radiation performances of commercial and rad-hard CMOS circuits are reviewed. Threshold voltage, static power current, V in -V out characteristic and propagation delay time related with total dose are presented for CMOS circuits from several manufacturing processes. The performance of radiation-annealing of experimental circuits had been observed for two years. The comparison has been made between the CMOS circuits made in China and the commercial RCA products. 60 Co γ source can serve as γ simulator of the nuclear explosion

  3. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A. Jr.; Estreich, D.B.; Dawes, W.R. Jr.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS structures. Under normal bias, the parasitic SCR is in its blocking state, but if subjected to a high-voltage spike or if exposed to an ionizing environment, triggering may occur. Prevention of latch-up has been achieved by lifetime control methods such as gold doping or neutron irradiation and by modifying the structure with buried layers. Smaller, next-generation CMOS designs will enhance parasitic action making the problem a concern for other than military or space applications alone. Latch-up control methods presently employed are surveyed. Their adaptability to VSLI designs is analyzed

  4. A novel CMOS SRAM feedback element for SEU environments

    International Nuclear Information System (INIS)

    Verghese, S.; Wortman, J.J.; Kerns, S.E.

    1987-01-01

    A hardened CMOS SRAM has been proposed which utilizes a leaky polysilicon Schottky diode placed in the feedback path to attain the SEU immunity of resistor-coupled SRAMs while improving the access speed of the cell. Novel polysilicon hybrid Schottky-resistor structures which emulate the leaky diodes have been designed and fabricated. The elements' design criteria and methods of fulfilling them are presented along with a practical implementation scheme for CMOS SRAM cells

  5. Materials Characterization of CIGS solar cells on Top of CMOS chips

    NARCIS (Netherlands)

    Lu, J.; Liu, W.; Kovalgin, A.Y.; Sun, Y.; Schmitz, J.; Venkatasubramanian, R.; Radousky, H.; Liang, H.

    2011-01-01

    In the current work, we present a detailed study on the material properties of the CIGS layers, fabricated on top of the CMOS chips, and compare the results with the fabrication on standard glass substrates. Almost identical elemental composition on both glass and CMOS chips (within measurement

  6. Radiation imaging detectors made by wafer post-processing of CMOS chips

    NARCIS (Netherlands)

    Blanco Carballo, V.M.

    2009-01-01

    In this thesis several wafer post-processing steps have been applied to CMOS chips. Amplification gas strucutures are built on top of the microchips. A complete radiation imaging detector is obtained this way. Integrated Micromegas-like and GEM-like structures were fabricated on top of Timepix CMOS

  7. Two CMOS BGR using CM and DTMOST techniques

    International Nuclear Information System (INIS)

    Mohd-Yasin, F.; Teh, Y.K.; Choong, F.; Reaz, M.B.I.

    2009-06-01

    Two CMOS BGR using current mode (0.044mm 2 ) and Dynamic Threshold MOST (0.017mm 2 ) techniques are designed on CMOS 0.18μm process. On-wafer measurement shows both circuits have minimum operating V DD 1.28V at 25 o C; taking 2.1μA and 0.5μA (maximum current 3.1μA and 1.1μA) and output voltage of 514mV and 457mV. Both circuits could support V DD range up to 4V required by passive UHF RFID. (author)

  8. A 13.56 MHz CMOS Active Rectifier With Switched-Offset and Compensated Biasing for Biomedical Wireless Power Transfer Systems.

    Science.gov (United States)

    Yan Lu; Wing-Hung Ki

    2014-06-01

    A full-wave active rectifier switching at 13.56 MHz with compensated bias current for a wide input range for wirelessly powered high-current biomedical implants is presented. The four diodes of a conventional passive rectifier are replaced by two cross-coupled PMOS transistors and two comparator- controlled NMOS switches to eliminate diode voltage drops such that high voltage conversion ratio and power conversion efficiency could be achieved even at low AC input amplitude |VAC|. The comparators are implemented with switched-offset biasing to compensate for the delays of active diodes and to eliminate multiple pulsing and reverse current. The proposed rectifier uses a modified CMOS peaking current source with bias current that is quasi-inversely proportional to the supply voltage to better control the reverse current over a wide AC input range (1.5 to 4 V). The rectifier was fabricated in a standard 0.35 μm CMOS N-well process with active area of 0.0651 mm(2). For the proposed rectifier measured at |VAC| = 3.0 V, the voltage conversion ratios are 0.89 and 0.93 for RL=500 Ω and 5 kΩ, respectively, and the measured power conversion efficiencies are 82.2% to 90.1% with |VAC| ranges from 1.5 to 4 V for RL=500 Ω.

  9. Wireless Neural Recording With Single Low-Power Integrated Circuit

    Science.gov (United States)

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  10. Hermetic electronic packaging of an implantable brain-machine-interface with transcutaneous optical data communication.

    Science.gov (United States)

    Schuettler, Martin; Kohler, Fabian; Ordonez, Juan S; Stieglitz, Thomas

    2012-01-01

    Future brain-computer-interfaces (BCIs) for severely impaired patients are implanted to electrically contact the brain tissue. Avoiding percutaneous cables requires amplifier and telemetry electronics to be implanted too. We developed a hermetic package that protects the electronic circuitry of a BCI from body moisture while permitting infrared communication through the package wall made from alumina ceramic. The ceramic package is casted in medical grade silicone adhesive, for which we identified MED2-4013 as a promising candidate.

  11. Design of Pixellated CMOS Photon Detector for Secondary Electron Detection in the Scanning Electron Microscope

    Directory of Open Access Journals (Sweden)

    Joon Huang Chuah

    2011-01-01

    Full Text Available This paper presents a novel method of detecting secondary electrons generated in the scanning electron microscope (SEM. The method suggests that the photomultiplier tube (PMT, traditionally used in the Everhart-Thornley (ET detector, is to be replaced with a configurable multipixel solid-state photon detector offering the advantages of smaller dimension, lower supply voltage and power requirements, and potentially cheaper product cost. The design of the proposed detector has been implemented using a standard 0.35 μm CMOS technology with optical enhancement. This microchip comprises main circuit constituents of an array of photodiodes connecting to respective noise-optimised transimpedance amplifiers (TIAs, a selector-combiner (SC circuit, and a postamplifier (PA. The design possesses the capability of detecting photons with low input optical power in the range of 1 nW with 100 μm × 100 μm sized photodiodes and achieves a total amplification of 180 dBΩ at the output.

  12. A CMOS silicon spin qubit

    Science.gov (United States)

    Maurand, R.; Jehl, X.; Kotekar-Patil, D.; Corna, A.; Bohuslavskyi, H.; Laviéville, R.; Hutin, L.; Barraud, S.; Vinet, M.; Sanquer, M.; de Franceschi, S.

    2016-11-01

    Silicon, the main constituent of microprocessor chips, is emerging as a promising material for the realization of future quantum processors. Leveraging its well-established complementary metal-oxide-semiconductor (CMOS) technology would be a clear asset to the development of scalable quantum computing architectures and to their co-integration with classical control hardware. Here we report a silicon quantum bit (qubit) device made with an industry-standard fabrication process. The device consists of a two-gate, p-type transistor with an undoped channel. At low temperature, the first gate defines a quantum dot encoding a hole spin qubit, the second one a quantum dot used for the qubit read-out. All electrical, two-axis control of the spin qubit is achieved by applying a phase-tunable microwave modulation to the first gate. The demonstrated qubit functionality in a basic transistor-like device constitutes a promising step towards the elaboration of scalable spin qubit geometries in a readily exploitable CMOS platform.

  13. Portable musical instrument amplifier

    Science.gov (United States)

    Christian, David E.

    1990-07-24

    The present invention relates to a musical instrument amplifier which is particularly useful for electric guitars. The amplifier has a rigid body for housing both the electronic system for amplifying and processing signals from the guitar and the system's power supply. An input plug connected to and projecting from the body is electrically coupled to the signal amplifying and processing system. When the plug is inserted into an output jack for an electric guitar, the body is rigidly carried by the guitar, and the guitar is operatively connected to the electrical amplifying and signal processing system without use of a loose interconnection cable. The amplifier is provided with an output jack, into which headphones are plugged to receive amplified signals from the guitar. By eliminating the conventional interconnection cable, the amplifier of the present invention can be used by musicians with increased flexibility and greater freedom of movement.

  14. A digital output accelerometer using MEMS-based piezoelectric accelerometers and arrayed CMOS inverters with satellite capacitors

    International Nuclear Information System (INIS)

    Kobayashi, T; Okada, H; Maeda, R; Itoh, T; Masuda, T

    2011-01-01

    The present paper describes the development of a digital output accelerometer composed of microelectromechanical systems (MEMS)-based piezoelectric accelerometers and arrayed complementary metal–oxide–semiconductor (CMOS) inverters accompanied by capacitors. The piezoelectric accelerometers were fabricated from multilayers of Pt/Ti/PZT/Pt/Ti/SiO 2 deposited on silicon-on-insulator (SOI) wafers. The fabricated piezoelectric accelerometers were connected to arrayed CMOS inverters. Each of the CMOS inverters was accompanied by a capacitor with a different capacitance called a 'satellite capacitor'. We have confirmed that the output voltage generated from the piezoelectric accelerometers can vary the output of the CMOS inverters from a high to a low level; the state of the CMOS inverters has turned from the 'off-state' into the 'on-state' when the output voltage of the piezoelectric accelerometers is larger than the threshold voltage of the CMOS inverters. We have also confirmed that the CMOS inverters accompanied by the larger satellite capacitor have become 'on-state' at a lower acceleration. On increasing the acceleration, the number of on-state CMOS inverters has increased. Assuming that the on-state and off-state of CMOS inverters correspond to logic '0' and '1', the present digital output accelerometers have expressed the accelerations of 2.0, 3.0, 5.0, and 5.5 m s −2 as digital outputs of 111, 110, 100, and 000, respectively

  15. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  16. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  17. An Integrated Chip High-Voltage Power Receiver for Wireless Biomedical Implants

    Directory of Open Access Journals (Sweden)

    Vijith Vijayakumaran Nair

    2015-06-01

    Full Text Available In near-field wireless-powered biomedical implants, the receiver voltage largely overrides the compliance of low-voltage power receiver systems. To limit the induced voltage, generally, low-voltage topologies utilize limiter circuits, voltage clippers or shunt regulators, which are power-inefficient methods. In order to overcome the voltage limitation and improve power efficiency, we propose an integrated chip high-voltage power receiver based on the step down approach. The topology accommodates voltages as high as 30 V and comprises a high-voltage semi-active rectifier, a voltage reference generator and a series regulator. Further, a battery management circuit that enables safe and reliable implant battery charging based on analog control is proposed and realized. The power receiver is fabricated in 0.35-μm high-voltage Bipolar-CMOS-DMOStechnology based on the LOCOS0.35-μm CMOS process. Measurement results indicate 83.5% power conversion efficiency for a rectifier at 2.1 mA load current. The low drop-out regulator based on the current buffer compensation and buffer impedance attenuation scheme operates with low quiescent current, reduces the power consumption and provides good stability. The topology also provides good power supply rejection, which is adequate for the design application. Measurement results indicate regulator output of 4 ± 0.03 V for input from 5 to 30 V and 10 ± 0.05 V output for input from 11 to 30 V with load current 0.01–100 mA. The charger circuit manages the charging of the Li-ion battery through all if the typical stages of the Li-ion battery charging profile.

  18. Differential InP HEMT MMIC Amplifiers Embedded in Waveguides

    Science.gov (United States)

    Kangaslahti, Pekka; Schlecht, Erich; Samoska, Lorene

    2009-01-01

    Monolithic microwave integrated-circuit (MMIC) amplifiers of a type now being developed for operation at frequencies of hundreds of gigahertz contain InP high-electron-mobility transistors (HEMTs) in a differential configuration. The differential configuration makes it possible to obtain gains greater than those of amplifiers having the single-ended configuration. To reduce losses associated with packaging, the MMIC chips are designed integrally with, and embedded in, waveguide packages, with the additional benefit that the packages are compact enough to fit into phased transmitting and/or receiving antenna arrays. Differential configurations (which are inherently balanced) have been used to extend the upper limits of operating frequencies of complementary metal oxide/semiconductor (CMOS) amplifiers to the microwave range but, until now, have not been applied in millimeter- wave amplifier circuits. Baluns have traditionally been used to transform from single-ended to balanced configurations, but baluns tend to be lossy. Instead of baluns, finlines are used to effect this transformation in the present line of development. Finlines have been used extensively to drive millimeter- wave mixers in balanced configurations. In the present extension of the finline balancing concept, finline transitions are integrated onto the affected MMICs (see figure). The differential configuration creates a virtual ground within each pair of InP HEMT gate fingers, eliminating the need for inductive vias to ground. Elimination of these vias greatly reduces parasitic components of current and the associated losses within an amplifier, thereby enabling more nearly complete utilization of the full performance of each transistor. The differential configuration offers the additional benefit of multiplying (relative to the single-ended configuration) the input and output impedances of each transistor by a factor of four, so that it is possible to use large transistors that would otherwise have

  19. A Nordic project on high speed low power design in sub-micron CMOS technology for mobile phones

    DEFF Research Database (Denmark)

    Olesen, Ole

    circuit design is based on state-of-the-art CMOS technology (0.5µm and below) including circuits operating at 2GHz. CMOS technology is chosen, since a CMOS implementation is likely to be significantly cheaper than a bipolar or a BiCMOS solution, and it offers the possibility to integrate the predominantly...

  20. Study in mutation of alfalfa genome DNA due to low energy N+ implantation using RAPD

    International Nuclear Information System (INIS)

    Chen Roulei; Song Daojun; Yu Zengliang; Li Yufeng; Liang Yunzhang

    2001-01-01

    After implanted by various dosage N + beams, germination rate of alfalfa seeds appears to be saddle line with dosage increasing. The authors have studied in mutation of genome DNA due to low energy N + implantation, and concluded that 30 differential DNA fragments have been amplified by 8 primers (S 41 , S 42 , S 45 , S 46 , S 50 , S 52 , S 56 , S 58 ) in 100 primers, moreover, number of differential DNA fragments between CK and treatments increases with dosage. Consequently, low energy ion implantation can cause mutation of alfalfa genome DNA. The more dosage it is, the more mutation alfalfa will be