WorldWideScience

Sample records for ieee vlsi test

  1. The test of VLSI circuits

    Baviere, Ph.

    Tests which have proven effective for evaluating VLSI circuits for space applications are described. It is recommended that circuits be examined after each manfacturing step to gain fast feedback on inadequacies in the production system. Data from failure modes which occur during operational lifetimes of circuits also permit redefinition of the manufacturing and quality control process to eliminate the defects identified. Other tests include determination of the operational envelope of the circuits, examination of the circuit response to controlled inputs, and the performance and functional speeds of ROM and RAM memories. Finally, it is desirable that all new circuits be designed with testing in mind.

  2. Heavy ion tests on programmable VLSI

    Provost-Grellier, A.

    1989-11-01

    The radiation from space environment induces operation damages in onboard computers systems. The definition of a strategy, for the Very Large Scale Integrated Circuitry (VLSI) qualification and choice, is needed. The 'upset' phenomena is known to be the most critical integrated circuit radiation effect. The strategies for testing integrated circuits are reviewed. A method and a test device were developed and applied to space applications candidate circuits. Cyclotron, synchrotron and Californium source experiments were carried out [fr

  3. VLSI design

    Einspruch, Norman G

    1986-01-01

    VLSI Electronics Microstructure Science, Volume 14: VLSI Design presents a comprehensive exposition and assessment of the developments and trends in VLSI (Very Large Scale Integration) electronics. This volume covers topics that range from microscopic aspects of materials behavior and device performance to the comprehension of VLSI in systems applications. Each article is prepared by a recognized authority. The subjects discussed in this book include VLSI processor design methodology; the RISC (Reduced Instruction Set Computer); the VLSI testing program; silicon compilers for VLSI; and special

  4. VLSI design

    Basu, D K

    2014-01-01

    Very Large Scale Integrated Circuits (VLSI) design has moved from costly curiosity to an everyday necessity, especially with the proliferated applications of embedded computing devices in communications, entertainment and household gadgets. As a result, more and more knowledge on various aspects of VLSI design technologies is becoming a necessity for the engineering/technology students of various disciplines. With this goal in mind the course material of this book has been designed to cover the various fundamental aspects of VLSI design, like Categorization and comparison between various technologies used for VLSI design Basic fabrication processes involved in VLSI design Design of MOS, CMOS and Bi CMOS circuits used in VLSI Structured design of VLSI Introduction to VHDL for VLSI design Automated design for placement and routing of VLSI systems VLSI testing and testability The various topics of the book have been discussed lucidly with analysis, when required, examples, figures and adequate analytical and the...

  5. Microfluidic very large scale integration (VLSI) modeling, simulation, testing, compilation and physical synthesis

    Pop, Paul; Madsen, Jan

    2016-01-01

    This book presents the state-of-the-art techniques for the modeling, simulation, testing, compilation and physical synthesis of mVLSI biochips. The authors describe a top-down modeling and synthesis methodology for the mVLSI biochips, inspired by microelectronics VLSI methodologies. They introduce a modeling framework for the components and the biochip architecture, and a high-level microfluidic protocol language. Coverage includes a topology graph-based model for the biochip architecture, and a sequencing graph to model for biochemical application, showing how the application model can be obtained from the protocol language. The techniques described facilitate programmability and automation, enabling developers in the emerging, large biochip market. · Presents the current models used for the research on compilation and synthesis techniques of mVLSI biochips in a tutorial fashion; · Includes a set of "benchmarks", that are presented in great detail and includes the source code of several of the techniques p...

  6. IEEE Std 101-1987: IEEE guide for the statistical analysis of thermal life test data

    Anon.

    1992-01-01

    This revision of IEEE Std 101-1972 describes statistical analyses for data from thermally accelerated aging tests. It explains the basis and use of statistical calculations for an engineer or scientist. Accelerated test procedures usually call for a number of specimens to be aged at each of several temperatures appreciably above normal operating temperatures. High temperatures are chosen to produce specimen failures (according to specified failure criteria) in typically one week to one year. The test objective is to determine the dependence of median life on temperature from the data, and to estimate, by extrapolation, the median life to be expected at service temperature. This guide presents methods for analyzing such data and for comparing test data on different materials

  7. IEEE C37.98-1987: IEEE standard seismic testing of relays

    Anon.

    1992-01-01

    This standard specifies the procedures to be used in the seismic testing of relays used in power system facilities. The standard is concerned with the determination of the seismic fragility level of relays and also gives recommendations for proof testing. The purpose of this standard is to establish procedures for determining the seismic capabilities of protective and auxiliary relays. These procedures employ what has been called fragility testing in IEEE Std 344-1987. To define the conditions for fragility testing of relays, parameters in three separate areas must be specified. In general, they are (1) the electrical settings and inputs to the relay, and other information to define its conditions during the test; (2) the change in state, deviation in operating characteristics or tolerances, or other change of performance of the relay that constitutes failure; (3) the seismic vibration environment to be imposed during the test. Since it is not possible to define the conditions for every conceivable application for all relays, those parameters, which in practice encompass the majority of applications, have been specified in this standard. When the application of the relay is other than as specified under any of (1), (2), and (3), or if it is not practical to apply existing results of fragility tests to that new application, then proof testing must be performed for that new case

  8. IEEE C37.98-1978: IEEE standard seismic testing of relays

    Anon.

    1992-01-01

    This standard specifies the procedures to be used in the seismic testing of relays used in power system facilities. The standard is concerned with the determination of the seismic fragility level of relays and also gives recommendations for proof testing. The purpose of this standard is to establish procedures for determining the seismic capabilities of protective and auxiliary relays. These procedures employ what has been called fragility testing in ANSI/IEEE Std 344-1975, Recommended Practices for Seismic Qualification of Class 1E Equipment for Nuclear Power Generating Stations. In order to define the conditions for fragility testing of relays, parameters in three separate areas must be specified. In general they are: (1) the electrical settings and inputs to the relay, and other information to define its conditions during the test; (2) the change in state, deviation in operating characteristics or tolerances, or other change of performance of the relay which constitutes failure; (3) the seismic vibration environment to be imposed during the test. Since it is not possible to define the conditions for every conceivable application for all relays, those parameters, which in practice encompass the majority of applications, have been specified in this standard. When the application of the relay is other than as specified under any of (1), (2), and (3), or if it is not practical to apply existing results of fragility tests to that new case

  9. High-energy heavy ion testing of VLSI devices for single event ...

    Unknown

    per describes the high-energy heavy ion radiation testing of VLSI devices for single event upset (SEU) ... The experimental set up employed to produce low flux of heavy ions viz. silicon ... through which they pass, leaving behind a wake of elec- ... for use in Bus Management Unit (BMU) and bulk CMOS ... was scheduled.

  10. Qualification test of Class 1E equipment based on IEEE323 Std 2003

    Kim, J. S.; Jung, S. C.; Kim, T. R.

    2004-01-01

    IEEE Standard for Qualifying Class 1E Equipment has been updated to 2003 edition since the issue of IEEE Std 323-1971, 1974, 1983. NRC approved the IEEE Std 323-1974 as Qualification standard of Class 1E Equipment in domestic nuclear power plant. IEEE Std 323-2003 was issued in September of 2003 and utility is waiting the approval of NRC. IEEE Std 323-2003 suggest a new qualification technique which adopts the condition monitoring. Performance of two transient during DBA test is no longer recommended in IEEE Std 323-2003. IEEE323 Std 2003 included a chapter of ''extension of Qualified life'' to make available the life extension of components during plant life extension. For the efficient control of preserving EQ in domestic nuclear power plant, IEEE323 Std 2003 is strongly recommended

  11. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    Altmeyer, Ronald

    2002-01-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

  12. An engineering methodology for implementing and testing VLSI (Very Large Scale Integrated) circuits

    Corliss, Walter F., II

    1989-03-01

    The engineering methodology for producing a fully tested VLSI chip from a design layout is presented. A 16-bit correlator, NPS CORN88, that was previously designed, was used as a vehicle to demonstrate this methodology. The study of the design and simulation tools, MAGIC and MOSSIM II, was the focus of the design and validation process. The design was then implemented and the chip was fabricated by MOSIS. This fabricated chip was then used to develop a testing methodology for using the digital test facilities at NPS. NPS CORN88 was the first full custom VLSI chip, designed at NPS, to be tested with the NPS digital analysis system, Tektronix DAS 9100 series tester. The capabilities and limitations of these test facilities are examined. NPS CORN88 test results are included to demonstrate the capabilities of the digital test system. A translator, MOS2DAS, was developed to convert the MOSSIM II simulation program to the input files required by the DAS 9100 device verification software, 91DVS. Finally, a tutorial for using the digital test facilities, including the DAS 9100 and associated support equipments, is included as an appendix.

  13. Initial beam test results from a silicon-strip detector with VLSI readout

    Adolphsen, C.; Litke, A.; Schwarz, A.

    1986-01-01

    Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

  14. New domain for image analysis: VLSI circuits testing, with Romuald, specialized in parallel image processing

    Rubat Du Merac, C; Jutier, P; Laurent, J; Courtois, B

    1983-07-01

    This paper describes some aspects of specifying, designing and evaluating a specialized machine, Romuald, for the capture, coding, and processing of video and scanning electron microscope (SEM) pictures. First the authors present the functional organization of the process unit of romuald and its hardware, giving details of its behaviour. Then they study the capture and display unit which, thanks to its flexibility, enables SEM images coding. Finally, they describe an application which is now being developed in their laboratory: testing VLSI circuits with new methods: sem+voltage contrast and image processing. 15 references.

  15. VLSI design

    Chandrasetty, Vikram Arkalgud

    2011-01-01

    This book provides insight into the practical design of VLSI circuits. It is aimed at novice VLSI designers and other enthusiasts who would like to understand VLSI design flows. Coverage includes key concepts in CMOS digital design, design of DSP and communication blocks on FPGAs, ASIC front end and physical design, and analog and mixed signal design. The approach is designed to focus on practical implementation of key elements of the VLSI design process, in order to make the topic accessible to novices. The design concepts are demonstrated using software from Mathworks, Xilinx, Mentor Graphic

  16. Validation of IEEE P1547.1 Interconnection Test Procedures: ASCO 7000 Soft Load Transfer System

    Kroposki, B.; Englebretson, S.; Pink, C.; Daley, J.; Siciliano, R.; Hinton, D.

    2003-09-01

    This report presents the preliminary results of testing the ASCO 7000 Soft Load Transfer System according to IEEE P1547.1 procedures. The ASCO system interconnects synchronous generators with the electric power system and provides monitoring and control for the generator and grid connection through extensive protective functions. The purpose of this testing is to evaluate and give feedback on the contents of IEEE Draft Standard P1547.1 Conformance Tests Procedures for Equipment Interconnecting Distributed Resources With Electric Power Systems.

  17. IEEE Std 101-1972: IEEE guide for the statistical analysis of thermal life test data

    Anon.

    1992-01-01

    Procedures for estimating the thermal life of electrical insulation systems and materials call for life tests at several temperatures, usually well above the expected normal operating temperature. By the selection of high temperatures for the tests, life of the insulation samples will be terminated, according to some selected failure criterion or criteria, within relatively short times -- typically one week to one year. The result of these thermally accelerated life tests will be a set of data of life values for a corresponding set of temperatures. Usually the data consist of a set of life values for each of two to four (occasionally more) test temperatures, 10 C to 25 C apart. The objective then is to establish from these data the mean life vales at each temperature and the functional dependence of life on temperature, as well as the statistical consistency and the confidence to be attributed to the mean life values and the functional life temperature dependence. The purpose of this guide is to assist in this objective and to give guidance for comparing the results of tests on different materials and of different tests on the same materials

  18. Radiation hardness tests with a demonstrator preamplifier circuit manufactured in silicon on sapphire (SOS) VLSI technology

    Bingefors, N.; Ekeloef, T.; Eriksson, C.; Paulsson, M.; Moerk, G.; Sjoelund, A.

    1992-01-01

    Samples of the preamplifier circuit, as well as of separate n and p channel transistors of the type contained in the circuit, were irradiated with gammas from a 60 Co source up to an integrated dose of 3 Mrad (30 kGy). The VLSI manufacturing technology used is the SOS4 process of ABB Hafo. A first analysis of the tests shows that the performance of the amplifier remains practically unaffected by the radiation for total doses up to 1 Mrad. At higher doses up to 3 Mrad the circuit amplification factor decreases by a factor between 4 and 5 whereas the output noise level remains unchanged. It is argued that it may be possible to reduce the decrease in amplification factor in future by optimizing the amplifier circuit design further. (orig.)

  19. An Extended IEEE 118-Bus Test System With High Renewable Penetration

    Pena, Ivonne; Martinez-Anido, Carlo Brancucci; Hodge, Bri-Mathias

    2018-01-01

    This article describes a new publicly available version of the IEEE 118-bus test system, named NREL-118. The database is based on the transmission representation (buses and lines) of the IEEE 118-bus test system, with a reconfigured generation representation using three regions of the US Western Interconnection from the latest Western Electricity Coordination Council (WECC) 2024 Common Case [1]. Time-synchronous hourly load, wind, and solar time series are provided for over one year (8784 hours). The public database presented and described in this manuscript will allow researchers to model a test power system using detailed transmission, generation, load, wind, and solar data. This database includes key additional features that add to the current IEEE 118-bus test model, such as: the inclusion of 10 generation technologies with different heat rate functions, minimum stable levels and ramping rates, GHG emissions rates, regulation and contingency reserves, and hourly time series data for one full year for load, wind and solar generation.

  20. Implementation of neuromorphic systems: from discrete components to analog VLSI chips (testing and communication issues).

    Dante, V; Del Giudice, P; Mattia, M

    2001-01-01

    We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a special purpose, asynchronous bus for communication among neuromorphic chips; a short and preliminary account of an application-oriented device, taking advantage of the above communication infrastructure.

  1. State-of-the-art assessment of testing and testability of custom LSI/VLSI circuits. Volume 8: Fault simulation

    Breuer, M. A.; Carlan, A. J.

    1982-10-01

    Fault simulation is widely used by industry in such applications as scoring the fault coverage of test sequences and construction of fault dictionaries. For use in testing VLSI circuits a simulator is evaluated by its accuracy, i.e., modelling capability. To be accurate simulators must employ multi-valued logic in order to represent unknown signal values, impedance, signal transitions, etc., circuit delays such as transport rise/fall, inertial, and the fault modes it is capable of handling. Of the three basic fault simulators now in use (parallel, deductive and concurrent) concurrent fault simulation appears most promising.

  2. IEEE Std 381-1977: IEEE standard criteria for type tests of Class 1E modules used in nuclear power generating stations

    Anon.

    1992-01-01

    This document describes the basic requirements of a type test program with the objective of verifying that a module used as Class 1E equipment in a nuclear power generating station meets or exceeds its design specifications. This document is limited to class 1E modules from and including the sensor through the logic circuitry of the final actuation devices. Except for those that are part of a module, switchgear, cables, connections, motors, valve actuators, station batteries, and penetrations are not included and are covered by other IEEE documents. The purpose of this document is to supplement the procedures and requirements given in IEEE Std 323-1974 [24] for type testing Class 1E modules, thereby providing directions for establishment of a type test program which will obtain the required test data and yield the required documentation of test methods and results. This standard is structured to present to the user the principal performance characteristics and environmental parameters which must be considered in designing a type test program for any give Class 1E module. These modules range from tiny sensors to complete racks or cabinets full of equipment that may be located inside or outside containment. The Class 1E modules are required to perform their function before, during, or after, or all, any design basis event specified for the module. The vast variety of modules covered by this document precludes the listing here of specific requirements for each type test

  3. IEEE Std 383-1974: IEEE standard for type test of Class IE electric cables, field splices, and connections for nuclear power generating stations

    Anon.

    1992-01-01

    This standard provides direction for establishing type tests which may be used in qualifying Class 1E electric cables, field splices, and other connections for service in nuclear power generating stations. General guidelines for qualifications are given in IEEE Std 323-1974, Standard for Qualifying Class IE Electric Equipment for Nuclear Power Generating Stations. Categories of cables covered are those used for power control and instrumentation services. Though intended primarily to pertain to cable for field installation, this guide may also be used for the qualification of internal wiring of manufactured devices. This guide does not cover cables for service within the reactor vessel

  4. VLSI electronics microstructure science

    1982-01-01

    VLSI Electronics: Microstructure Science, Volume 4 reviews trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the silicon-on-insulator for VLSI and VHSIC, X-ray lithography, and transient response of electron transport in GaAs using the Monte Carlo method. The technology and manufacturing of high-density magnetic-bubble memories, metallic superlattices, challenge of education for VLSI, and impact of VLSI on medical signal processing are also elaborated. This text likewise covers the impact of VLSI t

  5. UW VLSI chip tester

    McKenzie, Neil

    1989-12-01

    We present a design for a low-cost, functional VLSI chip tester. It is based on the Apple MacIntosh II personal computer. It tests chips that have up to 128 pins. All pin drivers of the tester are bidirectional; each pin is programmed independently as an input or an output. The tester can test both static and dynamic chips. Rudimentary speed testing is provided. Chips are tested by executing C programs written by the user. A software library is provided for program development. Tests run under both the Mac Operating System and A/UX. The design is implemented using Xilinx Logic Cell Arrays. Price/performance tradeoffs are discussed.

  6. VLSI in medicine

    Einspruch, Norman G

    1989-01-01

    VLSI Electronics Microstructure Science, Volume 17: VLSI in Medicine deals with the more important applications of VLSI in medical devices and instruments.This volume is comprised of 11 chapters. It begins with an article about medical electronics. The following three chapters cover diagnostic imaging, focusing on such medical devices as magnetic resonance imaging, neurometric analyzer, and ultrasound. Chapters 5, 6, and 7 present the impact of VLSI in cardiology. The electrocardiograph, implantable cardiac pacemaker, and the use of VLSI in Holter monitoring are detailed in these chapters. The

  7. VLSI electronics microstructure science

    1981-01-01

    VLSI Electronics: Microstructure Science, Volume 3 evaluates trends for the future of very large scale integration (VLSI) electronics and the scientific base that supports its development.This book discusses the impact of VLSI on computer architectures; VLSI design and design aid requirements; and design, fabrication, and performance of CCD imagers. The approaches, potential, and progress of ultra-high-speed GaAs VLSI; computer modeling of MOSFETs; and numerical physics of micron-length and submicron-length semiconductor devices are also elaborated. This text likewise covers the optical linewi

  8. The VLSI handbook

    Chen, Wai-Kai

    2007-01-01

    Written by a stellar international panel of expert contributors, this handbook remains the most up-to-date, reliable, and comprehensive source for real answers to practical problems. In addition to updated information in most chapters, this edition features several heavily revised and completely rewritten chapters, new chapters on such topics as CMOS fabrication and high-speed circuit design, heavily revised sections on testing of digital systems and design languages, and two entirely new sections on low-power electronics and VLSI signal processing. An updated compendium of references and othe

  9. Plasma processing for VLSI

    Einspruch, Norman G

    1984-01-01

    VLSI Electronics: Microstructure Science, Volume 8: Plasma Processing for VLSI (Very Large Scale Integration) discusses the utilization of plasmas for general semiconductor processing. It also includes expositions on advanced deposition of materials for metallization, lithographic methods that use plasmas as exposure sources and for multiple resist patterning, and device structures made possible by anisotropic etching.This volume is divided into four sections. It begins with the history of plasma processing, a discussion of some of the early developments and trends for VLSI. The second section

  10. Electron beam effects on VLSI MOS conditions for testing and reconfiguration

    Girard, P.; Roche, F.M.; Pistoulet, B.

    1986-01-01

    Wafer scale integrated-MOS circuits problems related to test and reconfiguration by electron beams are analyzed. First of all the alterations in characteristics of MOS circuits submitted to an electron beam testing are considered. Then the capabilities of reconfiguration by an electron beam bombardment are discussed. The various phenomena involved are reviewed. Experimental data are reported and discussed on the light of data of the literature. (Auth.)

  11. Reliability data collection on IC and VLSI devices tested under accelerated life conditions

    Barry, D.M.; Meniconi, M.

    1986-01-01

    As part of a more general investigation into the reliability and failure causes of semiconductor devices, statistical samples of integrated circuit devices (LM741C) and dynamic random access memory devices (TMS4116) were tested destructively to failure using elevated temperature as the accelerating stress. The devices were operated during the life test and the failure data generated were collected automatically using a multiple question-and-answer program and a process control computer. The failure data were modelled from the lognormal, inverse Gaussian and Weibull distribution using an Arrhenius reaction rate model. The failed devices were later decapsulated for failure cause determination. (orig./DG)

  12. Compliance and Functional Testing of IEEE 1451.1 for NCAP-to-NCAP Communications in a Sensor Network

    Figueroa, Jorge; Gurkan, Deniz; Yuan, X.; Benhaddou, D.; Liu, H.; Singla, A.; Franzl, R.; Ma, H.; Bhatt, S.; Morris, J.; hide

    2008-01-01

    Distributed control in a networked environment is an irreplaceable feature in systems with remote sensors and actuators. Although distributed control was not originally designed to be networked, usage of off-the-shelf networking technologies has become so prevalent that control systems are desired to have access mechanisms similar to computer networks. However, proprietary transducer interfaces for network communications and distributed control overwhelmingly dominate this industry. Unless the lack of compatibility and interoperability among transducers is resolved, the mature level of access (that computer networking can deliver) will not be achieved in such networked distributed control systems. Standardization of networked transducer interfaces will enable devices from different manufacturers to talk to each other and ensure their plug-and-play capability. One such standard is the suite of IEEE 1451 for sensor network communication and transducer interfaces. The suite not only provides a standard interface for smart transducers, but also outlines the connection of an NCAP (network capable application processor) and transducers (through a transducer interface module TIM). This paper presents the design of the compliance testing of IEEE 1451.1 (referred to as Dot1) compatible NCAP-to-NCAP communications on a link-layer independent medium. The paper also represents the first demonstration of NCAP-to-NCAP communications with Dot1 compatibility: a tester NCAP and an NCAP under test (NUT).

  13. IEEE standard for type test of class 1E electric cables, field splices, and connections for nuclear power generating stations

    Anon.

    1974-01-01

    The Institute of Electrical and Electronics Engineers has generated this document to provide guidance for developing a program to type test cables, field splices, and connections and obtain specific type test data. It supplements IEEE Std 323-1974 Standard for Qualifying Class IE Equipment for Nuclear Power Generating Stations, which describes basic requirements for equipment qualification. It is the integrated performance of the structures, fluid systems, the electrical systems, the instrumentation systems of the station, and in particular, the plant protection system, that limits the consequences of accidents. Seismic effects on installed cable systems are not within the scope of this document. Section 2 of this guide is an example of type tests. It is the purpose of this guide to deal with cable and connections; however, at the time of issue, detailed examples of tests for connections were not available

  14. An integrated framework to support remote IEEE 1149.1 / 1149.4 design for test experiments

    Antonio M. Cardoso

    2006-08-01

    Full Text Available Remote experiments for academic purposes can only achieve their educational goals if an appropriate framework is able to provide a basic set of features, namely remote laboratory management, collaborative learning tools and content management and delivery. This paper presents a framework developed to support remote experiments in a design for test class offered to final year students at the Electrical and Computer Engineering degree at the University of Porto. The proposed solution combines a test language command interpreter and various virtual instruments (VIs, with a demonstration board that comprises a boundary-scan IEEE 1149.1 / 1149.4 test infrastructure. The experiments are presented as embedded learning objects, with no distinction from other e-learning contents (e.g. lessons, lecture notes, etc..

  15. Lithography for VLSI

    Einspruch, Norman G

    1987-01-01

    VLSI Electronics Microstructure Science, Volume 16: Lithography for VLSI treats special topics from each branch of lithography, and also contains general discussion of some lithographic methods.This volume contains 8 chapters that discuss the various aspects of lithography. Chapters 1 and 2 are devoted to optical lithography. Chapter 3 covers electron lithography in general, and Chapter 4 discusses electron resist exposure modeling. Chapter 5 presents the fundamentals of ion-beam lithography. Mask/wafer alignment for x-ray proximity printing and for optical lithography is tackled in Chapter 6.

  16. IEEE standard criteria for type tests of class 1E modules used in nuclear power generating stations

    Anon.

    1977-01-01

    The Institute of Electrical and Electronics Engineers has generated this document to provide direction for type testing Class 1E modules and obtaining specific type test data. It supplements IEEE Std 323-1974, Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations, which describes the basic requirements for Class 1E equipment qualification. Adherence to this document alone may not suffice for assuring public health and safety because it is the integrated performance of the structures, the fluid systems, the electrical systems, the instrumentation systems of the station, and in particular, the plant protection system of which these modules are a part that prevents accidents or limits the consequences of accidents. Each applicant to the Nuclear Regulatory Commission for a license to operate a nuclear power generating station has the responsibility to assure himself and others that this document, if used, is pertinent to his application and that the integrated performance of his station is adequate

  17. IEEE guide for planning of pre-operational testing programs for class 1E power systems for nuclear-power generating stations

    Anon.

    1976-01-01

    The Institute of Electrical and Electronics Engineers (IEEE) guide for pre-operational testing of Class 1E power systems for nuclear-power generating stations is presented. The guidelines apply to power systems both ac and dc supplies but not to the equipment which utilizes the ac and dc power. The pre-operational tests are performed after appropriate construction tests

  18. Development and results of a test program to demonstrate compliance with IEEE STD 384 and R.G. 1.75 electrical separation requirements

    Eckert, G.P.; Heneberry, E.F.; Walker, F.P.; Konkus, J.F.

    1987-01-01

    The IEEE Std 384-1974, entitled ''Criteria for Separation of Class 1E Equipment and Circuits,'' contains criteria to ensure the independence of redundant Class 1E equipment when designing electrical systems in nuclear plants. The NRC, in R.G. 1.75 Rev. 2, 1978, endorses, with comments, IEEE-384, as the means of achieving independence. One method given in IEEE-384, is that of maintaining a specified separation between components; another method utilizes a combination of separation and barriers. The standard also allows alternative methods to be used when justified by test-based analyses. This paper is a report of a test program undertaken to provide a basis for analysis in the development of alternative methods of achieving separation. The test parameters developed and used, and the results obtained, should prove useful in determining alternative methods of complying with R.G. 1.75 requirements

  19. Simulasi Dinamika untuk Menentukan Stabilitas Sistem Tenaga Listrik Menggunakan Thyristor Controlled Braking Resistor pada Sistem IEEE 34 Node Test Feeder

    Andi Taufiq

    2012-09-01

    Full Text Available Terdapat berbagai macam metode untuk meningkatkan stabilitas sistem  tenaga listrik. Salah satunya adalah dengan menggunakan metode pengereman dinamis (dynamic braking. Generator sinkron sebagai distributed generator yang digerakkan oleh mesin diesel. Pada saat terjadi gangguan pada sistem, digunakan sebuah Thyristor Controlled Braking Resistor (TCBR untuk meredam osilasi yang terjadi. Sistem yang hendak dianalisis dinamika dan stabilitasnnya adalah IEEE 34 node test feeder. Dengan sistem ini diilustrasikan karakteristik dan keefektifan TCBR untuk meredam osilasi frekuensi rendah dan mencegah terjadinya ketidakstabilan transien sistem. Dari hasil analisis diperoleh bahwa dengan adanya penambahan TCBR (Thyristor Controlled Braking Resistor maka respon transien sistem akan menjadi lebih baik. Hal ini ditunjukkan dengan adanya penurunan overshoot dan settling timenya. Dengan demikian sistem akan menuju kondisi stabil dengan lebih cepat setelah terjadi gangguan.

  20. Parallel VLSI Architecture

    Truong, T. K.; Reed, I.; Yeh, C.; Shao, H.

    1985-01-01

    Fermat number transformation convolutes two digital data sequences. Very-large-scale integration (VLSI) applications, such as image and radar signal processing, X-ray reconstruction, and spectrum shaping, linear convolution of two digital data sequences of arbitrary lenghts accomplished using Fermat number transform (ENT).

  1. IEEE Std 600: IEEE trial-use standard requirements for organizations that conduct qualification testing of safety systems equipment for use in nuclear power generating stations

    Anon.

    1992-01-01

    The purpose of this standard is to provide requirements for establishing a program for conducting qualification tests of safety systems equipment used in nuclear power generating stations. Compliance with the requirements of this standard does not assure the adequacy of the qualification tests performed. This standard applies to organizations that conduct qualification tests on equipment that has a definable safety function and is an identifiable part of a safety system for use in nuclear power generating stations. It requires a technical program, a quality assurance program, and a demonstrated ability to meet specified technical requirements. It does not apply to materials tests, production tests, normal performance testing, qualification by analysis, qualification by operating experience, or reliability tests such as diesel-generator multiple start tests. The intent of this standard is to achieve greater consistency, reliability, and reproducibility of test results and to provide adequate control of qualification testing of safety systems equipment

  2. Extended device profiles and testing procedures for the approval process of integrated medical devices using the IEEE 11073 communication standard.

    Janß, Armin; Thorn, Johannes; Schmitz, Malte; Mildner, Alexander; Dell'Anna-Pudlik, Jasmin; Leucker, Martin; Radermacher, Klaus

    2018-02-23

    Nowadays, only closed and proprietary integrated operating room systems (IORS) from big manufacturers are available on the market. Hence, the interconnection of components from third-party vendors is only possible with increased time and costs. In the context of the German Federal Ministry of Education and Research (BMBF)-funded project OR.NET (2012-2016), the open integration of medical devices from different manufacturers was addressed. An integrated operating theater based on the open communication standard IEEE 11073 shall give clinical operators the opportunity to choose medical devices independently of the manufacturer. This approach would be advantageous especially for hospital operators and small- and medium-sized enterprises (SME) of medical devices. Actual standards and concepts regarding technical feasibility and the approval process do not cope with the requirements for a modular integration of medical devices in the operating room (OR), based on an open communication standard. Therefore, innovative approval strategies and corresponding certification and test procedures, which cover actual legal and normative standards, have to be developed in order to support the future risk management and the usability engineering process of open integrated medical devices in the OR. The use of standardized device and service profiles and a three-step testing procedure, including conformity, interoperability and integration tests are described in this paper and shall support the manufacturers to integrate their medical devices without disclosing the medical devices' risk analysis and related confidential expertise or proprietary information.

  3. Pursuit, Avoidance, and Cohesion in Flight: Multi-Purpose Control Laws and Neuromorphic VLSI

    2010-10-01

    spatial navigation in mammals. We have designed, fabricated, and are now testing a neuromorphic VLSI chip that implements a spike-based, attractor...Control Laws and Neuromorphic VLSI 5a. CONTRACT NUMBER 070402-7705 5b. GRANT NUMBER FA9550-07-1-0446 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S...implementations (custom Neuromorphic VLSI and robotics) we will apply important practical constraints that can lead to deeper insight into how and why efficient

  4. Parallel computation of nondeterministic algorithms in VLSI

    Hortensius, P D

    1987-01-01

    This work examines parallel VLSI implementations of nondeterministic algorithms. It is demonstrated that conventional pseudorandom number generators are unsuitable for highly parallel applications. Efficient parallel pseudorandom sequence generation can be accomplished using certain classes of elementary one-dimensional cellular automata. The pseudorandom numbers appear in parallel on each clock cycle. Extensive study of the properties of these new pseudorandom number generators is made using standard empirical random number tests, cycle length tests, and implementation considerations. Furthermore, it is shown these particular cellular automata can form the basis of efficient VLSI architectures for computations involved in the Monte Carlo simulation of both the percolation and Ising models from statistical mechanics. Finally, a variation on a Built-In Self-Test technique based upon cellular automata is presented. These Cellular Automata-Logic-Block-Observation (CALBO) circuits improve upon conventional design for testability circuitry.

  5. VLSI 'smart' I/O module development

    Kirk, Dan

    The developmental history, design, and operation of the MIL-STD-1553A/B discrete and serial module (DSM) for the U.S. Navy AN/AYK-14(V) avionics computer are described and illustrated with diagrams. The ongoing preplanned product improvement for the AN/AYK-14(V) includes five dual-redundant MIL-STD-1553 channels based on DSMs. The DSM is a front-end processor for transferring data to and from a common memory, sharing memory with a host processor to provide improved 'smart' input/output performance. Each DSM comprises three hardware sections: three VLSI-6000 semicustomized CMOS arrays, memory units to support the arrays, and buffers and resynchronization circuits. The DSM hardware module design, VLSI-6000 design tools, controlware and test software, and checkout procedures (using a hardware simulator) are characterized in detail.

  6. VLSI signal processing technology

    Swartzlander, Earl

    1994-01-01

    This book is the first in a set of forthcoming books focussed on state-of-the-art development in the VLSI Signal Processing area. It is a response to the tremendous research activities taking place in that field. These activities have been driven by two factors: the dramatic increase in demand for high speed signal processing, especially in consumer elec­ tronics, and the evolving microelectronic technologies. The available technology has always been one of the main factors in determining al­ gorithms, architectures, and design strategies to be followed. With every new technology, signal processing systems go through many changes in concepts, design methods, and implementation. The goal of this book is to introduce the reader to the main features of VLSI Signal Processing and the ongoing developments in this area. The focus of this book is on: • Current developments in Digital Signal Processing (DSP) pro­ cessors and architectures - several examples and case studies of existing DSP chips are discussed in...

  7. Nano lasers in photonic VLSI

    Hill, M.T.; Oei, Y.S.; Smit, M.K.

    2007-01-01

    We examine the use of micro and nano lasers to form digital photonic VLSI building blocks. Problems such as isolation and cascading of building blocks are addressed, and the potential of future nano lasers explored.

  8. VLSI Architectures for Computing DFT's

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Reed, I. S.; Pei, D. Y.

    1986-01-01

    Simplifications result from use of residue Fermat number systems. System of finite arithmetic over residue Fermat number systems enables calculation of discrete Fourier transform (DFT) of series of complex numbers with reduced number of multiplications. Computer architectures based on approach suitable for design of very-large-scale integrated (VLSI) circuits for computing DFT's. General approach not limited to DFT's; Applicable to decoding of error-correcting codes and other transform calculations. System readily implemented in VLSI.

  9. Fast-prototyping of VLSI

    Saucier, G.; Read, E.

    1987-01-01

    Fast-prototyping will be a reality in the very near future if both straightforward design methods and fast manufacturing facilities are available. This book focuses, first, on the motivation for fast-prototyping. Economic aspects and market considerations are analysed by European and Japanese companies. In the second chapter, new design methods are identified, mainly for full custom circuits. Of course, silicon compilers play a key role and the introduction of artificial intelligence techniques sheds a new light on the subject. At present, fast-prototyping on gate arrays or on standard cells is the most conventional technique and the third chapter updates the state-of-the art in this area. The fourth chapter concentrates specifically on the e-beam direct-writing for submicron IC technologies. In the fifth chapter, a strategic point in fast-prototyping, namely the test problem is addressed. The design for testability and the interface to the test equipment are mandatory to fulfill the test requirement for fast-prototyping. Finally, the last chapter deals with the subject of education when many people complain about the lack of use of fast-prototyping in higher education for VLSI

  10. Multi-valued LSI/VLSI logic design

    Santrakul, K.

    A procedure for synthesizing any large complex logic system, such as LSI and VLSI integrated circuits is described. This scheme uses Multi-Valued Multi-plexers (MVMUX) as the basic building blocks and the tree as the structure of the circuit realization. Simple built-in test circuits included in the network (the main current), provide a thorough functional checking of the network at any time. In brief, four major contributions are made: (1) multi-valued Algorithmic State Machine (ASM) chart for describing an LSI/VLSI behavior; (2) a tree-structured multi-valued multiplexer network which can be obtained directly from an ASM chart; (3) a heuristic tree-structured synthesis method for realizing any combinational logic with minimal or nearly-minimal MVMUX; and (4) a hierarchical design of LSI/VLSI with built-in parallel testing capability.

  11. VLSI implementations for image communications

    Pirsch, P

    1993-01-01

    The past few years have seen a rapid growth in image processing and image communication technologies. New video services and multimedia applications are continuously being designed. Essential for all these applications are image and video compression techniques. The purpose of this book is to report on recent advances in VLSI architectures and their implementation for video signal processing applications with emphasis on video coding for bit rate reduction. Efficient VLSI implementation for video signal processing spans a broad range of disciplines involving algorithms, architectures, circuits

  12. Impact of Distribution Feeders that do not have Voltage Regulators on the number of Charged Electric Vehicles using IEEE 34 Bus Test Feeder

    Allehyani, Ahmed [University of Southern California, Department of Electrical Engineering; Beshir, Mohammed [University of Southern California, Department of Electrical Engineering

    2015-02-01

    Voltage regulators help maintain an acceptable voltage profile for the system. This paper discusses the effect of installing voltage regulators to the system to fix the voltage drop resulting from the electrical vehicles loading increase when they are being charged. The effect will be studied in the afternoon, when the peak load occurs, using the IEEE 34 bus test feeder. First, only one spot node is used to charge the electric vehicles while a voltage regulator is present. Second, five spot nodes are loaded at the same time to charge the electric vehicles while voltage regulators are installed at each node. After that, the impact of electric vehicles on distribution feeders that do not have voltage regulators will appear.

  13. Application of evolutionary algorithms for multi-objective optimization in VLSI and embedded systems

    2015-01-01

    This book describes how evolutionary algorithms (EA), including genetic algorithms (GA) and particle swarm optimization (PSO) can be utilized for solving multi-objective optimization problems in the area of embedded and VLSI system design. Many complex engineering optimization problems can be modelled as multi-objective formulations. This book provides an introduction to multi-objective optimization using meta-heuristic algorithms, GA and PSO, and how they can be applied to problems like hardware/software partitioning in embedded systems, circuit partitioning in VLSI, design of operational amplifiers in analog VLSI, design space exploration in high-level synthesis, delay fault testing in VLSI testing, and scheduling in heterogeneous distributed systems. It is shown how, in each case, the various aspects of the EA, namely its representation, and operators like crossover, mutation, etc. can be separately formulated to solve these problems. This book is intended for design engineers and researchers in the field ...

  14. Computer-aided design of microfluidic very large scale integration (mVLSI) biochips design automation, testing, and design-for-testability

    Hu, Kai; Ho, Tsung-Yi

    2017-01-01

    This book provides a comprehensive overview of flow-based, microfluidic VLSI. The authors describe and solve in a comprehensive and holistic manner practical challenges such as control synthesis, wash optimization, design for testability, and diagnosis of modern flow-based microfluidic biochips. They introduce practical solutions, based on rigorous optimization and formal models. The technical contributions presented in this book will not only shorten the product development cycle, but also accelerate the adoption and further development of modern flow-based microfluidic biochips, by facilitating the full exploitation of design complexities that are possible with current fabrication techniques. Offers the first practical problem formulation for automated control-layer design in flow-based microfluidic biochips and provides a systematic approach for solving this problem; Introduces a wash-optimization method for cross-contamination removal; Presents a design-for-testability (DfT) technique that can achieve 100...

  15. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    2007-03-31

    IFinal 03/01/04 - 02/28/07 4. TITLE AND SUBTITLE 5a. CONTRACT NUMBER Neuromorphic VLSI-based Bat Echolocation for Micro-aerial 5b.GRANTNUMBER Vehicle...uncovered interesting new issues in our choice for representing the intensity of signals. We have just finished testing the first chip version of an echo...timing-based algorithm (’openspace’) for sonar-guided navigation amidst multiple obstacles. 15. SUBJECT TERMS Neuromorphic VLSI, bat echolocation

  16. Drift chamber tracking with a VLSI neural network

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-10-01

    We have tested a commercial analog VLSI neural network chip for finding in real time the intercept and slope of charged particles traversing a drift chamber. Voltages proportional to the drift times were input to the Intel ETANN chip and the outputs were recorded and later compared off line to conventional track fits. We will discuss the chamber and test setup, the chip specifications, and results of recent tests. We'll briefly discuss possible applications in high energy physics detector triggers

  17. System design considerations for implementing performance and service tests on Class 1E batteries in accordance with IEEE 450-1980

    Pagan, E.J.; Weronick, R.

    1982-01-01

    Extensive electrical system design considerations are required to implement performance and service tests on Class 1E in accordance iwth IEEE 450-1980 ''Recommended Practice For Maintenance Testing and Replacement of Large Lead Storage Batteries For Generating Stations and Substations''. Class 1E is the safety classification of the electric equipment and systems that are essential to emergency reactor shutdown, cotainment isolation, reactor core cooling, and containment and reactor heat removal, or are otherwise essential to emergency reactor shutdown, containment isolation, reactor core cooling, and containment and reactor heat removal, or are otherwise essential in preventing significant release of radioactive material to the environment. The paper discusses alternatives which merit investigating to determine a feasible method for performing these tests at operating nuclear power plants, or plants nearing completion, which may lack provisions for incorporating such tests. The scope of each alternative presented includes a description and critique of the test circuit configuration and the auxiliary equipment required to isolate the battery and connect it to a Battery Capacity Tester (BCT). 6 refs

  18. IEEE Smart Grid Series of Standards IEEE 2030 (Interoperability) and IEEE 1547 (Interconnection) Status: Preprint

    Basso, T.; DeBlasio, R.

    2012-04-01

    The IEEE American National Standards smart grid publications and standards development projects IEEE 2030, which addresses smart grid interoperability, and IEEE 1547TM, which addresses distributed resources interconnection with the grid, have made substantial progress since 2009. The IEEE 2030TM and 1547 standards series focus on systems-level aspects and cover many of the technical integration issues involved in a mature smart grid. The status and highlights of these two IEEE series of standards, which are sponsored by IEEE Standards Coordinating Committee 21 (SCC21), are provided in this paper.

  19. Power gating of VLSI circuits using MEMS switches in low power applications

    Shobak, Hosam

    2011-12-01

    Power dissipation poses a great challenge for VLSI designers. With the intense down-scaling of technology, the total power consumption of the chip is made up primarily of leakage power dissipation. This paper proposes combining a custom-designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result of implementing this novel power gating technique, a standby leakage power reduction of 99% and energy savings of 33.3% are achieved. Finally the possible effects of surge currents and ground bounce noise are studied. These findings allow longer operation times for battery-operated systems characterized by long standby periods. © 2011 IEEE.

  20. VLSI structures for track finding

    Dell'Orso, M.

    1989-01-01

    We discuss the architecture of a device based on the concept of associative memory designed to solve the track finding problem, typical of high energy physics experiments, in a time span of a few microseconds even for very high multiplicity events. This ''machine'' is implemented as a large array of custom VLSI chips. All the chips are equal and each of them stores a number of ''patterns''. All the patterns in all the chips are compared in parallel to the data coming from the detector while the detector is being read out. (orig.)

  1. The AMchip: A VLSI associative memory for track finding

    Morsani, F.; Galeotti, S.; Passuello, D.; Amendolia, S.R.; Ristori, L.; Turini, N.

    1992-01-01

    An associative memory to be used for super-fast track finding in future high energy physics experiments, has been implemented on silicon as a full-custom CMOS VLSI chip (the AMchip). The first prototype has been designed and successfully tested at INFN in Pisa. It is implemented in 1.6 μm, double metal, silicon gate CMOS technology and contains about 140 000 MOS transistors on a 1x1 cm 2 silicon chip. (orig.)

  2. VLSI Design with Alliance Free CAD Tools: an Implementation Example

    Chávez-Bracamontes Ramón

    2015-07-01

    Full Text Available This paper presents the methodology used for a digital integrated circuit design that implements the communication protocol known as Serial Peripheral Interface, using the Alliance CAD System. The aim of this paper is to show how the work of VLSI design can be done by graduate and undergraduate students with minimal resources and experience. The physical design was sent to be fabricated using the CMOS AMI C5 process that features 0.5 micrometer in transistor size, sponsored by the MOSIS Educational Program. Tests were made on a platform that transfers data from inertial sensor measurements to the designed SPI chip, which in turn sends the data back on a parallel bus to a common microcontroller. The results show the efficiency of the employed methodology in VLSI design, as well as the feasibility of ICs manufacturing from school projects that have insufficient or no source of funding

  3. Surface and interface effects in VLSI

    Einspruch, Norman G

    1985-01-01

    VLSI Electronics Microstructure Science, Volume 10: Surface and Interface Effects in VLSI provides the advances made in the science of semiconductor surface and interface as they relate to electronics. This volume aims to provide a better understanding and control of surface and interface related properties. The book begins with an introductory chapter on the intimate link between interfaces and devices. The book is then divided into two parts. The first part covers the chemical and geometric structures of prototypical VLSI interfaces. Subjects detailed include, the technologically most import

  4. A PROPOSED NOVEL ARCHITECTURE OF EC CONTROL SYSTEM USING IEEE 802.11n NETWORK AT ITER-INDIA GYROTRON TEST FACILITY

    Deepak Mandge

    2017-06-01

    Full Text Available IEEE 802.11 Wi-Fi networks are increasingly becoming popular for its use in industrial applications. With the availability of recent amendments to IEEE 802.11 series of standards, particularly IEEE 802.11n, the adoption of Wi-Fi networks for process automation is gaining more focus and importance. The installation of Wireless networks naturally provides reduction in cable and its maintenance related costs, provides increased flexibility and mobility to enhance performance of industrial control system. The IEEE 802.11n supports parameterization that can be set for particular industrial applications and hence it has addressed to the aspects of timeliness and criticality to some extent. This paper proposes the use of IEEE 802.11n network to interconnect field instruments with Siemens PLC controller in harsh EMI/EMC environment. An application example is shown where the alternate control system architecture is developed in which non-critical and non-safety signals are communicated over Wi-Fi. While, for critical and safety signals, traditional hardwired signals methods can be implemented.

  5. IEEE Prize for Lucio Rossi

    IEEE Council on Superconductivity

    2007-01-01

    Lucio Rossi receives his prize from John Spargo, Chairman of the IEEE Council on Superconductivity (left), and Martin Nisenoff, Chairman of the Council on Superconductivity's Awards Committee (right).

  6. VLSI scaling methods and low power CMOS buffer circuit

    Sharma Vijay Kumar; Pattanaik Manisha

    2013-01-01

    Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. (semiconductor integrated circuits)

  7. VLSI Technology for Cognitive Radio

    VIJAYALAKSHMI, B.; SIDDAIAH, P.

    2017-08-01

    One of the most challenging tasks of cognitive radio is the efficiency in the spectrum sensing scheme to overcome the spectrum scarcity problem. The popular and widely used spectrum sensing technique is the energy detection scheme as it is very simple and doesn’t require any previous information related to the signal. We propose one such approach which is an optimised spectrum sensing scheme with reduced filter structure. The optimisation is done in terms of area and power performance of the spectrum. The simulations of the VLSI structure of the optimised flexible spectrum is done using verilog coding by using the XILINX ISE software. Our method produces performance with 13% reduction in area and 66% reduction in power consumption in comparison to the flexible spectrum sensing scheme. All the results are tabulated and comparisons are made. A new scheme for optimised and effective spectrum sensing opens up with our model.

  8. Convolving optically addressed VLSI liquid crystal SLM

    Jared, David A.; Stirk, Charles W.

    1994-03-01

    We designed, fabricated, and tested an optically addressed spatial light modulator (SLM) that performs a 3 X 3 kernel image convolution using ferroelectric liquid crystal on VLSI technology. The chip contains a 16 X 16 array of current-mirror-based convolvers with a fixed kernel for finding edges. The pixels are located on 75 micron centers, and the modulators are 20 microns on a side. The array successfully enhanced edges in illumination patterns. We developed a high-level simulation tool (CON) for analyzing the performance of convolving SLM designs. CON has a graphical interface and simulates SLM functions using SPICE-like device models. The user specifies the pixel function along with the device parameters and nonuniformities. We discovered through analysis, simulation and experiment that the operation of current-mirror-based convolver pixels is degraded at low light levels by the variation of transistor threshold voltages inherent to CMOS chips. To function acceptable, the test SLM required the input image to have an minimum irradiance of 10 (mu) W/cm2. The minimum required irradiance can be further reduced by adding a photodarlington near the photodetector or by increasing the size of the transistors used to calculate the convolution.

  9. Access to IEEE Electronic Library

    2007-01-01

    From 2007, the CERN Library now offers readers online access to the complete IEEE Electronic Library (Institute of Electrical and Electronics Engineers). This new licence gives unlimited online access to all IEEE and IET (previously IEE) journals and proceedings as well as all current IEEE standards and selected archived ones. Some of the titles offer volumes back to 1913. This service currently represents more than 1,400,000 full-text articles! This leading engineering information resource replaces the previous service, a sub-product of the IEEE database called 'IEEE Enterprise', which offered online access to the complete collection of IEEE journals and proceedings, but with limited features. The service had become so popular that the CERN Working Group for Acquisitions recommended that the Library subscribe to the complete IEEE Electronic Library for 2007. Usage statistics for recent months showed there was a demand for the service from a large community of CERN users and we were aware that many users h...

  10. Design of a Low-Power VLSI Macrocell for Nonlinear Adaptive Video Noise Reduction

    Sergio Saponara

    2004-09-01

    Full Text Available A VLSI macrocell for edge-preserving video noise reduction is proposed in the paper. It is based on a nonlinear rational filter enhanced by a noise estimator for blind and dynamic adaptation of the filtering parameters to the input signal statistics. The VLSI filter features a modular architecture allowing the extension of both mask size and filtering directions. Both spatial and spatiotemporal algorithms are supported. Simulation results with monochrome test videos prove its efficiency for many noise distributions with PSNR improvements up to 3.8 dB with respect to a nonadaptive solution. The VLSI macrocell has been realized in a 0.18 μm CMOS technology using a standard-cells library; it allows for real-time processing of main video formats, up to 30 fps (frames per second 4CIF, with a power consumption in the order of few mW.

  11. The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

    Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

    1993-01-01

    An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

  12. Digital VLSI design with Verilog a textbook from Silicon Valley Technical Institute

    Williams, John

    2008-01-01

    This unique textbook is structured as a step-by-step course of study along the lines of a VLSI IC design project. In a nominal schedule of 12 weeks, two days and about 10 hours per week, the entire verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer - deserializer, including synthesizable PLLs. Digital VLSI Design With Verilog is all an engineer needs for in-depth understanding of the verilog language: Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided on the

  13. Compact MOSFET models for VLSI design

    Bhattacharyya, A B

    2009-01-01

    Practicing designers, students, and educators in the semiconductor field face an ever expanding portfolio of MOSFET models. In Compact MOSFET Models for VLSI Design , A.B. Bhattacharyya presents a unified perspective on the topic, allowing the practitioner to view and interpret device phenomena concurrently using different modeling strategies. Readers will learn to link device physics with model parameters, helping to close the gap between device understanding and its use for optimal circuit performance. Bhattacharyya also lays bare the core physical concepts that will drive the future of VLSI.

  14. Lithography requirements in complex VLSI device fabrication

    Wilson, A.D.

    1985-01-01

    Fabrication of complex very large scale integration (VLSI) circuits requires continual advances in lithography to satisfy: decreasing minimum linewidths, larger chip sizes, tighter linewidth and overlay control, increasing topography to linewidth ratios, higher yield demands, increased throughput, harsher device processing, lower lithography cost, and a larger part number set with quick turn-around time. Where optical, electron beam, x-ray, and ion beam lithography can be applied to judiciously satisfy the complex VLSI circuit fabrication requirements is discussed and those areas that are in need of major further advances are addressed. Emphasis will be placed on advanced electron beam and storage ring x-ray lithography

  15. Design of two easily-testable VLSI array multipliers

    Ferguson, J.; Shen, J.P.

    1983-01-01

    Array multipliers are well-suited to VLSI implementation because of the regularity in their iterative structure. However, most VLSI circuits are very difficult to test. This paper shows that, with appropriate cell design, array multipliers can be designed to be very easily testable. An array multiplier is called c-testable if all its adder cells can be exhaustively tested while requiring only a constant number of test patterns. The testability of two well-known array multiplier structures are studied. The conventional design of the carry-save array multipler is shown to be not c-testable. However, a modified design, using a modified adder cell, is generated and shown to be c-testable and requires only 16 test patterns. Similar results are obtained for the baugh-wooley two's complement array multiplier. A modified design of the baugh-wooley array multiplier is shown to be c-testable and requires 55 test patterns. The implementation of a practical c-testable 16*16 array multiplier is also presented. 10 references.

  16. A Knowledge Based Approach to VLSI CAD

    1983-09-01

    Avail-and/or Dist ISpecial L| OI. SEICURITY CLASIIrCATION OP THIS IPA.lErllm S Daene." A KNOwLEDE BASED APPROACH TO VLSI CAD’ Louis L Steinberg and...major issues lies in building up and managing the knowledge base of oesign expertise. We expect that, as with many recent expert systems, in order to

  17. Electro-optic techniques for VLSI interconnect

    Neff, J. A.

    1985-03-01

    A major limitation to achieving significant speed increases in very large scale integration (VLSI) lies in the metallic interconnects. They are costly not only from the charge transport standpoint but also from capacitive loading effects. The Defense Advanced Research Projects Agency, in pursuit of the fifth generation supercomputer, is investigating alternatives to the VLSI metallic interconnects, especially the use of optical techniques to transport the information either inter or intrachip. As the on chip performance of VLSI continues to improve via the scale down of the logic elements, the problems associated with transferring data off and onto the chip become more severe. The use of optical carriers to transfer the information within the computer is very appealing from several viewpoints. Besides the potential for gigabit propagation rates, the conversion from electronics to optics conveniently provides a decoupling of the various circuits from one another. Significant gains will also be realized in reducing cross talk between the metallic routings, and the interconnects need no longer be constrained to the plane of a thin film on the VLSI chip. In addition, optics can offer an increased programming flexibility for restructuring the interconnect network.

  18. VLSI architecture and design for the Fermat Number Transform implementation

    Pajayakrit, A.

    1987-01-01

    A new technique of sectioning a pipelined transformer, using the Fermat Number Transform (FNT), is introduced. Also, a novel VLSI design which overcomes the problems of implementing FNTs, for use in fast convolution/correlation, is described. The design comprises one complete section of a pipelined transformer and may be programmed to function at any point in a forward or inverse pipeline, so allowing the construction of a pipelined convolver or correlator using identical chips, thus the favorable properties of the transform can be exploited. This overcomes the difficulty of fitting a complete pipeline onto one chip without resorting to the use of several different designs. The implementation of high-speed convolver/correlator using the VLSI chips has been successfully developed and tested. For impulse response lengths of up to 16 points the sampling rates of 0.5 MHz can be achieved. Finally, the filter speed performance using the FNT chips is compared to other designs and conclusions drawn on the merits of the FNT for this application. Also, the advantages and limitations of the FNT are analyzed, with respect to the more conventional FFT, and the results are provided.

  19. IEEE Conference Publications in Libraries.

    Johnson, Karl E.

    1984-01-01

    Conclusions of surveys (63 libraries, OCLC database, University of Rhode Island users) assessing handling of Institute of Electrical and Electronics Engineers (IEEE) conference publications indicate that most libraries fully catalog these publications using LC cataloging, and library patrons frequently require series access to publications. Eight…

  20. Harnessing VLSI System Design with EDA Tools

    Kamat, Rajanish K; Gaikwad, Pawan K; Guhilot, Hansraj

    2012-01-01

    This book explores various dimensions of EDA technologies for achieving different goals in VLSI system design. Although the scope of EDA is very broad and comprises diversified hardware and software tools to accomplish different phases of VLSI system design, such as design, layout, simulation, testability, prototyping and implementation, this book focuses only on demystifying the code, a.k.a. firmware development and its implementation with FPGAs. Since there are a variety of languages for system design, this book covers various issues related to VHDL, Verilog and System C synergized with EDA tools, using a variety of case studies such as testability, verification and power consumption. * Covers aspects of VHDL, Verilog and Handel C in one text; * Enables designers to judge the appropriateness of each EDA tool for relevant applications; * Omits discussion of design platforms and focuses on design case studies; * Uses design case studies from diversified application domains such as network on chip, hospital on...

  1. Researching the roots of IEEE Region 8

    Bastiaans, M.J.

    2013-01-01

    This paper describes the preliminary steps towards the foundation and the early history of IRE Region 9 / IEEE Region 8. The information has been gathered mainly from the archives of the IEEE Benelux Section.

  2. Applications of VLSI circuits to medical imaging

    O'Donnell, M.

    1988-01-01

    In this paper the application of advanced VLSI circuits to medical imaging is explored. The relationship of both general purpose signal processing chips and custom devices to medical imaging is discussed using examples of fabricated chips. In addition, advanced CAD tools for silicon compilation are presented. Devices built with these tools represent a possible alternative to custom devices and general purpose signal processors for the next generation of medical imaging systems

  3. PERFORMANCE OF LEAKAGE POWER MINIMIZATION TECHNIQUE FOR CMOS VLSI TECHNOLOGY

    T. Tharaneeswaran

    2012-06-01

    Full Text Available Leakage power of CMOS VLSI Technology is a great concern. To reduce leakage power in CMOS circuits, a Leakage Power Minimiza-tion Technique (LPMT is implemented in this paper. Leakage cur-rents are monitored and compared. The Comparator kicks the charge pump to give body voltage (Vbody. Simulations of these circuits are done using TSMC 0.35µm technology with various operating temper-atures. Current steering Digital-to-Analog Converter (CSDAC is used as test core to validate the idea. The Test core (eg.8-bit CSDAC had power consumption of 347.63 mW. LPMT circuit alone consumes power of 6.3405 mW. This technique results in reduction of leakage power of 8-bit CSDAC by 5.51mW and increases the reliability of test core. Mentor Graphics ELDO and EZ-wave are used for simulations.

  4. 2012 IEEE Vehicular Networking Conference (VNC)

    Altintas, Onur; Chen, Wai; Heijenk, Geert; Oh, Hyun Seo; Chung, Jong-Moon; Dressler, Falko; Kargl, Frank; Pau, Giovanni; Schoch, Elmar

    2012-01-01

    On behalf of the Organizing Committee, we would like to welcome you to the fourth edition of the IEEE Vehicular Networking Conference in Seoul, Korea. IEEE VNC is a unique conference sponsored by both IEEE Communications Society and Intelligent Transportation Systems Society. It brings together

  5. IEEE Prize for Lucio Rossi

    2007-01-01

    Lucio Rossi receives his prize from John Spargo, Chairman of the IEEE Council on Superconductivity (left), and Martin Nisenoff, Chairman of the Council on Superconductivity’s Awards Committee (right). (Photo: IEEE Council on Superconductivity)With the magnets installed in the tunnel and work on the interconnections almost completed, Lucio Rossi has reaped the rewards of fifteen years of work. And yet, when the physicist from Milan arrived to take charge of the group responsible for the superconducting magnets in 2001, success seemed far from assured. Endowed with surprising levels of energy, Lucio Rossi, together with his team, ensured that production of these highly complex magnets got underway. Today, that achievement earns them the recognition not only of CERN but also of the international superconducting community. It is for this achievement that Lucio Rossi was awarded the prize by the IEEE’s (Institute of Electrical an...

  6. IEEE Standard for qualification of Class 1E lead storage batteries for nuclear power generating stations

    Anon.

    1980-01-01

    This document describes qualification methods for Class 1E lead storage batteries and racks to be used in nuclear power generating stations outside of primary containment. Qualification required in ANSI/IEEE Std 279-1979 and IEEE Std 308-1978, can be demonstrated by using the procedures provided in this Standard in accordance with IEEE Std 323-1974. Battery sizing, maintenance, capacity testing, installation, charging equipment and consideration of other types batteries are beyond the scope of this Standard

  7. IEEE standard for qualification of class 1E lead storage batteries for nuclear power generating stations

    Anon.

    1979-01-01

    IEEE Std 323-1974, Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations, was developed to provide guidance for demonstrating and documenting the adequacy of electrical equipment used in all Class 1E and interface systems. This standard, IEEE Std 535-1979, was developed to provide specific methods and type test procedures for lead storage batteries in reference to IEEE Std 323-1974

  8. First results from a silicon-strip detector with VLSI readout

    Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

    1986-01-01

    A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

  9. VLSI Design of SVM-Based Seizure Detection System With On-Chip Learning Capability.

    Feng, Lichen; Li, Zunchao; Wang, Yuanfa

    2018-02-01

    Portable automatic seizure detection system is very convenient for epilepsy patients to carry. In order to make the system on-chip trainable with high efficiency and attain high detection accuracy, this paper presents a very large scale integration (VLSI) design based on the nonlinear support vector machine (SVM). The proposed design mainly consists of a feature extraction (FE) module and an SVM module. The FE module performs the three-level Daubechies discrete wavelet transform to fit the physiological bands of the electroencephalogram (EEG) signal and extracts the time-frequency domain features reflecting the nonstationary signal properties. The SVM module integrates the modified sequential minimal optimization algorithm with the table-driven-based Gaussian kernel to enable efficient on-chip learning. The presented design is verified on an Altera Cyclone II field-programmable gate array and tested using the two publicly available EEG datasets. Experiment results show that the designed VLSI system improves the detection accuracy and training efficiency.

  10. Technology computer aided design simulation for VLSI MOSFET

    Sarkar, Chandan Kumar

    2013-01-01

    Responding to recent developments and a growing VLSI circuit manufacturing market, Technology Computer Aided Design: Simulation for VLSI MOSFET examines advanced MOSFET processes and devices through TCAD numerical simulations. The book provides a balanced summary of TCAD and MOSFET basic concepts, equations, physics, and new technologies related to TCAD and MOSFET. A firm grasp of these concepts allows for the design of better models, thus streamlining the design process, saving time and money. This book places emphasis on the importance of modeling and simulations of VLSI MOS transistors and

  11. Wavelength-encoded OCDMA system using opto-VLSI processors.

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  12. Wavelength-encoded OCDMA system using opto-VLSI processors

    Aljada, Muhsen; Alameh, Kamal

    2007-07-01

    We propose and experimentally demonstrate a 2.5 Gbits/sper user wavelength-encoded optical code-division multiple-access encoder-decoder structure based on opto-VLSI processing. Each encoder and decoder is constructed using a single 1D opto-very-large-scale-integrated (VLSI) processor in conjunction with a fiber Bragg grating (FBG) array of different Bragg wavelengths. The FBG array spectrally and temporally slices the broadband input pulse into several components and the opto-VLSI processor generates codewords using digital phase holograms. System performance is measured in terms of the autocorrelation and cross-correlation functions as well as the eye diagram.

  13. Memory Based Machine Intelligence Techniques in VLSI hardware

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  14. ORGANIZATION OF GRAPHIC INFORMATION FOR VIEWING THE MULTILAYER VLSI TOPOLOGY

    V. I. Romanov

    2016-01-01

    Full Text Available One of the possible ways to reorganize of graphical information describing the set of topology layers of modern VLSI. The method is directed on the use in the conditions of the bounded size of video card memory. An additional effect, providing high performance of forming multi- image layout a multi-layer topology of modern VLSI, is achieved by preloading the required texture by means of auxiliary background process.

  15. Synthesis algorithm of VLSI multipliers for ASIC

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  16. Multi-net optimization of VLSI interconnect

    Moiseev, Konstantin; Wimer, Shmuel

    2015-01-01

    This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and several design optimization problems are addressed, such as minimization of interconnect power under delay constraints, or design for minimal delay in wire bundles within a given routing area. A handy reference or a guide for design methodologies and layout automation techniques, this book provides a foundation for physical design challenges of interconnect in advanced integrated circuits.  • Describes the evolution of interconnect scaling and provides new techniques for layout migration and optimization, focusing on multi-net optimization; • Presents research results that provide a level of design optimization which does not exist in commercially-available design automation software tools; • Includes mathematical properties and conditions for optimal...

  17. DPL/Daedalus design environment (for VLSI)

    Batali, J; Mayle, N; Shrobe, H; Sussman, G; Weise, D

    1981-01-01

    The DPL/Daedalus design environment is an interactive VLSI design system implemented at the MIT Artificial Intelligence Laboratory. The system consists of several components: a layout language called DPL (for design procedure language); an interactive graphics facility (Daedalus); and several special purpose design procedures for constructing complex artifacts such as PLAs and microprocessor data paths. Coordinating all of these is a generalized property list data base which contains both the data representing circuits and the procedures for constructing them. The authors first review the nature of the data base and then turn to DPL and Daedalus, the two most common ways of entering information into the data base. The next two sections review the specialized procedures for constructing PLAs and data paths; the final section describes a tool for hierarchical node extraction. 5 references.

  18. PLA realizations for VLSI state machines

    Gopalakrishnan, S.; Whitaker, S.; Maki, G.; Liu, K.

    1990-01-01

    A major problem associated with state assignment procedures for VLSI controllers is obtaining an assignment that produces minimal or near minimal logic. The key item in Programmable Logic Array (PLA) area minimization is the number of unique product terms required by the design equations. This paper presents a state assignment algorithm for minimizing the number of product terms required to implement a finite state machine using a PLA. Partition algebra with predecessor state information is used to derive a near optimal state assignment. A maximum bound on the number of product terms required can be obtained by inspecting the predecessor state information. The state assignment algorithm presented is much simpler than existing procedures and leads to the same number of product terms or less. An area-efficient PLA structure implemented in a 1.0 micron CMOS process is presented along with a summary of the performance for a controller implemented using this design procedure.

  19. Development methods for VLSI-processors

    Horninger, K.; Sandweg, G.

    1982-01-01

    The aim of this project, which was originally planed for 3 years, was the development of modern system and circuit concepts, for VLSI-processors having a 32 bit wide data path. The result of this first years work is the concept of a general purpose processor. This processor is not only logically but also physically (on the chip) divided into four functional units: a microprogrammable instruction unit, an execution unit in slice technique, a fully associative cache memory and an I/O unit. For the ALU of the execution unit circuits in PLA and slice techniques have been realized. On the basis of regularity, area consumption and achievable performance the slice technique has been prefered. The designs utilize selftesting circuitry. (orig.) [de

  20. VLSI Design of Trusted Virtual Sensors

    Macarena C. Martínez-Rodríguez

    2018-01-01

    Full Text Available This work presents a Very Large Scale Integration (VLSI design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF based on a Static Random Access Memory (SRAM to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time.

  1. VLSI Design of Trusted Virtual Sensors.

    Martínez-Rodríguez, Macarena C; Prada-Delgado, Miguel A; Brox, Piedad; Baturone, Iluminada

    2018-01-25

    This work presents a Very Large Scale Integration (VLSI) design of trusted virtual sensors providing a minimum unitary cost and very good figures of size, speed and power consumption. The sensed variable is estimated by a virtual sensor based on a configurable and programmable PieceWise-Affine hyper-Rectangular (PWAR) model. An algorithm is presented to find the best values of the programmable parameters given a set of (empirical or simulated) input-output data. The VLSI design of the trusted virtual sensor uses the fast authenticated encryption algorithm, AEGIS, to ensure the integrity of the provided virtual measurement and to encrypt it, and a Physical Unclonable Function (PUF) based on a Static Random Access Memory (SRAM) to ensure the integrity of the sensor itself. Implementation results of a prototype designed in a 90-nm Complementary Metal Oxide Semiconductor (CMOS) technology show that the active silicon area of the trusted virtual sensor is 0.86 mm 2 and its power consumption when trusted sensing at 50 MHz is 7.12 mW. The maximum operation frequency is 85 MHz, which allows response times lower than 0.25 μ s. As application example, the designed prototype was programmed to estimate the yaw rate in a vehicle, obtaining root mean square errors lower than 1.1%. Experimental results of the employed PUF show the robustness of the trusted sensing against aging and variations of the operation conditions, namely, temperature and power supply voltage (final value as well as ramp-up time).

  2. Spike Neuromorphic VLSI-Based Bat Echolocation for Micro-Aerial Vehicle Guidance

    Horiuchi, Timothy K; Krishnaprasad, P. S

    2007-01-01

    .... This includes multiple efforts related to a VLSI-based echolocation system being developed in one of our laboratories from algorithm development, bat flight data analysis, to VLSI circuit design...

  3. The IEEE Milestone event at CERN

    2005-01-01

    On the initiative of its French and Swiss Sections, the IEEE has honoured CERN with an 'IEEE Milestone in the history of electricity and electronics' for the invention of the multi-wire proportional chamber in 1968. The IEEE established the Electrical Engineering Milestones programe in 1983 to honour significant achievements in the history of electrical and electronics engineering. To be designated, an achievement must be at least 25 years old, must have involved a unique solution to an engineering problem, and must have had at least regional impact. Currently there are more than  50 IEEE Milestones around the world. http://www.ieee.org/organizations/history_center/cern.html The installation and unveiling of this IEEE Milestone will provide the opportunity to emphasize the close relationship between science, technology, industry and well-being in society.  A ceremony, organised with the support of a group of IEEE members working at CERN, will be held at the CERN Globe of Science and Inn...

  4. IEEE Std 535-1979: IEEE standard for qualification of Class 1E lead storage batteries for nuclear power generating stations

    Anon.

    1992-01-01

    This document describes qualification methods for Class 1E lead storage batteries and racks to be used in nuclear power generating stations outside of primary containment. Qualification required in ANSI/IEEE Std 279-1971 and IEE Std 308-1978, can be demonstrated by using the procedures provided in this standard in accordance with IEEE Std 323-1974. Battery sizing, maintenance, capacity testing, installation, charging equipment and consideration of other type batteries are beyond the scope of this standard

  5. IEEE Std 535-1986: IEEE standard for qualification of Class 1E lead storage batteries for nuclear power generating stations

    Anon.

    1992-01-01

    This document describes qualification methods for Class 1E lead storage batteries and racks to be used in nuclear power generating stations outside of primary containment. Qualification required in ANSI/IEEE Std 308-1980 can be demonstrated by using the procedures provided in this standard in accordance with ANSI/IEEE Std 323-1983. Battery sizing, maintenance, capacity testing, installation, charging equipment, and consideration of other type batteries are beyond the scope of this standard

  6. IEEE Std 650-1990: IEEE standard for qualification of Class 1E static battery chargers and inverters for nuclear power generating stations

    Anon.

    1992-01-01

    Methods for qualifying static battery chargers and inverters for Class 1E installations in a mild environment outside containment in nuclear power generating stations are described. The qualification methods set forth employ a combination of type testing and analysis, the latter including a justification of methods, theories, and assumptions used. These procedures meet the requirements of IEEE Std 323-1983, IEEE Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations

  7. CERN receives prestigious Milestone recognition from IEEE

    2005-01-01

    At a ceremony at CERN, Mr W. Cleon Anderson, President of the Institute of Electrical and Electronics Engineers (IEEE) formally a Milestone plaque in recognition of the invention of electronic particle detectors at CERN

  8. An electron undulating ring for VLSI lithography

    Tomimasu, T.; Mikado, T.; Noguchi, T.; Sugiyama, S.; Yamazaki, T.

    1985-01-01

    The development of the ETL storage ring ''TERAS'' as an undulating ring has been continued to achieve a wide area exposure of synchrotron radiation (SR) in VLSI lithography. Stable vertical and horizontal undulating motions of stored beams are demonstrated around a horizontal design orbit of TERAS, using two small steering magnets of which one is used for vertical undulating and another for horizontal one. Each steering magnet is inserted into one of the periodic configulation of guide field elements. As one of useful applications of undulaing electron beams, a vertically wide exposure of SR has been demonstrated in the SR lithography. The maximum vertical deviation from the design orbit nCcurs near the steering magnet. The maximum vertical tilt angle of the undulating beam near the nodes is about + or - 2mrad for a steering magnetic field of 50 gauss. Another proposal is for hith-intensity, uniform and wide exposure of SR from a wiggler installed in TERAS, using vertical and horizontal undulating motions of stored beams. A 1.4 m long permanent magnet wiggler has been installed for this purpose in this April

  9. NASA Space Engineering Research Center for VLSI systems design

    1991-01-01

    This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

  10. Handbook of VLSI chip design and expert systems

    Schwarz, A F

    1993-01-01

    Handbook of VLSI Chip Design and Expert Systems provides information pertinent to the fundamental aspects of expert systems, which provides a knowledge-based approach to problem solving. This book discusses the use of expert systems in every possible subtask of VLSI chip design as well as in the interrelations between the subtasks.Organized into nine chapters, this book begins with an overview of design automation, which can be identified as Computer-Aided Design of Circuits and Systems (CADCAS). This text then presents the progress in artificial intelligence, with emphasis on expert systems.

  11. VLSI micro- and nanophotonics science, technology, and applications

    Lee, El-Hang; Razeghi, Manijeh; Jagadish, Chennupati

    2011-01-01

    Addressing the growing demand for larger capacity in information technology, VLSI Micro- and Nanophotonics: Science, Technology, and Applications explores issues of science and technology of micro/nano-scale photonics and integration for broad-scale and chip-scale Very Large Scale Integration photonics. This book is a game-changer in the sense that it is quite possibly the first to focus on ""VLSI Photonics"". Very little effort has been made to develop integration technologies for micro/nanoscale photonic devices and applications, so this reference is an important and necessary early-stage pe

  12. FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

    Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

    1998-01-01

    We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

  13. IEEE International Symposium on Biomedical Imaging.

    2017-01-01

    The IEEE International Symposium on Biomedical Imaging (ISBI) is a scientific conference dedicated to mathematical, algorithmic, and computational aspects of biological and biomedical imaging, across all scales of observation. It fosters knowledge transfer among different imaging communities and contributes to an integrative approach to biomedical imaging. ISBI is a joint initiative from the IEEE Signal Processing Society (SPS) and the IEEE Engineering in Medicine and Biology Society (EMBS). The 2018 meeting will include tutorials, and a scientific program composed of plenary talks, invited special sessions, challenges, as well as oral and poster presentations of peer-reviewed papers. High-quality papers are requested containing original contributions to the topics of interest including image formation and reconstruction, computational and statistical image processing and analysis, dynamic imaging, visualization, image quality assessment, and physical, biological, and statistical modeling. Accepted 4-page regular papers will be published in the symposium proceedings published by IEEE and included in IEEE Xplore. To encourage attendance by a broader audience of imaging scientists and offer additional presentation opportunities, ISBI 2018 will continue to have a second track featuring posters selected from 1-page abstract submissions without subsequent archival publication.

  14. High performance VLSI telemetry data systems

    Chesney, J.; Speciale, N.; Horner, W.; Sabia, S.

    1990-01-01

    NASA's deployment of major space complexes such as Space Station Freedom (SSF) and the Earth Observing System (EOS) will demand increased functionality and performance from ground based telemetry acquisition systems well above current system capabilities. Adaptation of space telemetry data transport and processing standards such as those specified by the Consultative Committee for Space Data Systems (CCSDS) standards and those required for commercial ground distribution of telemetry data, will drive these functional and performance requirements. In addition, budget limitations will force the requirement for higher modularity, flexibility, and interchangeability at lower cost in new ground telemetry data system elements. At NASA's Goddard Space Flight Center (GSFC), the design and development of generic ground telemetry data system elements, over the last five years, has resulted in significant solutions to these problems. This solution, referred to as the functional components approach includes both hardware and software components ready for end user application. The hardware functional components consist of modern data flow architectures utilizing Application Specific Integrated Circuits (ASIC's) developed specifically to support NASA's telemetry data systems needs and designed to meet a range of data rate requirements up to 300 Mbps. Real-time operating system software components support both embedded local software intelligence, and overall system control, status, processing, and interface requirements. These components, hardware and software, form the superstructure upon which project specific elements are added to complete a telemetry ground data system installation. This paper describes the functional components approach, some specific component examples, and a project example of the evolution from VLSI component, to basic board level functional component, to integrated telemetry data system.

  15. Radio Frequency Fingerprinting Techniques Through Preamble Modification in IEEE 802.11B

    2014-06-30

    4.2.1 Wald–Wolfowitz Runs Test . . . . . . . . . . . . . . . . . . . . . . 41 4.2.2 Wald–Wolfowitz Application to SXS System . . . . . . . . . . . . 42...Station SXS Signals eXploitation System USB Universal Serial Bus xiv Acronym Definition USRP Universal Software Radio Peripheral WLAN Wireless Local...Electronics Engineers (IEEE) defines standards applicable to the IEEE 802.11 protocol, however the standard does not reach the level of specificity to dictate

  16. CERN receives prestigious Milestone recognition from IEEE

    2005-01-01

    The Nobel prize winner Georges Charpak and W. Cleon Anderson, IEEE President, unveil the Milestone bronze plaques. At a ceremony on 26 September at the Globe of Science and Innovation, Mr W. Cleon Anderson, President of the Institute of Electrical and Electronics Engineers (IEEE) formally dedicated Milestone plaques recognising the invention of electronic particle detectors at CERN. The plaque were unveiled by Mr Anderson and Georges Charpak, the Nobel-prize winning inventor of wire chamber technology at CERN in 1968. The IEEE is the world's largest professional association dedicated to the advancement of technology with 365,000 individual members in over 150 countries. Established in 1983, there are currently over 60 Milestones around the world. They honour momentous achievements in the history of electrical and electronics engineering, such as the landing of the first transatlantic cable, code breaking at Bletchley Park during World War II, and the development of the Japanese Bullet train, the Tokaido Shin...

  17. The scalable coherent interface, IEEE P1596

    Gustavson, D.B.

    1990-01-01

    IEEE P1596, the scalable coherent interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960--1986, IEC 935), Futurebus (IEEE P896.x) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics

  18. Artificial immune system algorithm in VLSI circuit configuration

    Mansor, Mohd. Asyraf; Sathasivam, Saratha; Kasihmuddin, Mohd Shareduwan Mohd

    2017-08-01

    In artificial intelligence, the artificial immune system is a robust bio-inspired heuristic method, extensively used in solving many constraint optimization problems, anomaly detection, and pattern recognition. This paper discusses the implementation and performance of artificial immune system (AIS) algorithm integrated with Hopfield neural networks for VLSI circuit configuration based on 3-Satisfiability problems. Specifically, we emphasized on the clonal selection technique in our binary artificial immune system algorithm. We restrict our logic construction to 3-Satisfiability (3-SAT) clauses in order to outfit with the transistor configuration in VLSI circuit. The core impetus of this research is to find an ideal hybrid model to assist in the VLSI circuit configuration. In this paper, we compared the artificial immune system (AIS) algorithm (HNN-3SATAIS) with the brute force algorithm incorporated with Hopfield neural network (HNN-3SATBF). Microsoft Visual C++ 2013 was used as a platform for training, simulating and validating the performances of the proposed network. The results depict that the HNN-3SATAIS outperformed HNN-3SATBF in terms of circuit accuracy and CPU time. Thus, HNN-3SATAIS can be used to detect an early error in the VLSI circuit design.

  19. An efficient interpolation filter VLSI architecture for HEVC standard

    Zhou, Wei; Zhou, Xin; Lian, Xiaocong; Liu, Zhenyu; Liu, Xiaoxiang

    2015-12-01

    The next-generation video coding standard of High-Efficiency Video Coding (HEVC) is especially efficient for coding high-resolution video such as 8K-ultra-high-definition (UHD) video. Fractional motion estimation in HEVC presents a significant challenge in clock latency and area cost as it consumes more than 40 % of the total encoding time and thus results in high computational complexity. With aims at supporting 8K-UHD video applications, an efficient interpolation filter VLSI architecture for HEVC is proposed in this paper. Firstly, a new interpolation filter algorithm based on the 8-pixel interpolation unit is proposed in this paper. It can save 19.7 % processing time on average with acceptable coding quality degradation. Based on the proposed algorithm, an efficient interpolation filter VLSI architecture, composed of a reused data path of interpolation, an efficient memory organization, and a reconfigurable pipeline interpolation filter engine, is presented to reduce the implement hardware area and achieve high throughput. The final VLSI implementation only requires 37.2k gates in a standard 90-nm CMOS technology at an operating frequency of 240 MHz. The proposed architecture can be reused for either half-pixel interpolation or quarter-pixel interpolation, which can reduce the area cost for about 131,040 bits RAM. The processing latency of our proposed VLSI architecture can support the real-time processing of 4:2:0 format 7680 × 4320@78fps video sequences.

  20. Numerical analysis of electromigration in thin film VLSI interconnections

    Petrescu, V.; Mouthaan, A.J.; Schoenmaker, W.; Angelescu, S.; Vissarion, R.; Dima, G.; Wallinga, Hans; Profirescu, M.D.

    1995-01-01

    Due to the continuing downscaling of the dimensions in VLSI circuits, electromigration is becoming a serious reliability hazard. A software tool based on finite element analysis has been developed to solve the two partial differential equations of the two particle vacancy/imperfection model.

  1. Hybrid VLSI/QCA Architecture for Computing FFTs

    Fijany, Amir; Toomarian, Nikzad; Modarres, Katayoon; Spotnitz, Matthew

    2003-01-01

    A data-processor architecture that would incorporate elements of both conventional very-large-scale integrated (VLSI) circuitry and quantum-dot cellular automata (QCA) has been proposed to enable the highly parallel and systolic computation of fast Fourier transforms (FFTs). The proposed circuit would complement the QCA-based circuits described in several prior NASA Tech Briefs articles, namely Implementing Permutation Matrices by Use of Quantum Dots (NPO-20801), Vol. 25, No. 10 (October 2001), page 42; Compact Interconnection Networks Based on Quantum Dots (NPO-20855) Vol. 27, No. 1 (January 2003), page 32; and Bit-Serial Adder Based on Quantum Dots (NPO-20869), Vol. 27, No. 1 (January 2003), page 35. The cited prior articles described the limitations of very-large-scale integrated (VLSI) circuitry and the major potential advantage afforded by QCA. To recapitulate: In a VLSI circuit, signal paths that are required not to interact with each other must not cross in the same plane. In contrast, for reasons too complex to describe in the limited space available for this article, suitably designed and operated QCAbased signal paths that are required not to interact with each other can nevertheless be allowed to cross each other in the same plane without adverse effect. In principle, this characteristic could be exploited to design compact, coplanar, simple (relative to VLSI) QCA-based networks to implement complex, advanced interconnection schemes.

  2. Harmonization of IEEE323 and IEC60780 standards For Environmental Qualificaiton of Electric Equipment

    Kim, Jong Seog

    2009-01-01

    IEEE323 standard has been widely used for the qualification of electric equipment in Asian pacific area while IEC6070 has been mostly used in European area. Since each plant use different standard for environmental qualification, manufacturer has to perform the qualification test twice in accordance with each standard. Problem also can be happened in the plant site when they are going to purchase equipment qualified by different qualification standard which are not used in his plant. The need of harmonization of each standard has been raised several years and it is known that some studies are in progress by IEEE committee. KEPRI has a plan of comparing EQ relative standards of IEEE, IEC and RCC in 2009. In this paper, brief comparing result between IEEE323 and IEC60780 and the proper harmonization method is introduced

  3. Editorial for IEEE Transactions on Power Electronics

    Blaabjerg, Frede

    2007-01-01

    Our IEEE transactions on power electronics has had some very positive progress these past years under the leadership of Dr. Daan van Wyk. Papers have been processed efficiently both in review time and publication time. This success has spread throughout the whole power electronics community which...

  4. The IEEE 802.11a standards

    First page Back Continue Last page Overview Graphics. The IEEE 802.11a standards. Provides higher data rate and system capacities and uses OFDM in Physical Layer to mitigate the multi path effects;. Supports multiple 20Mhz channel. Each channel being an OFDM Modulated;; 52 Carriers. 48 data carrier; 4 Carry pilot ...

  5. Aplicación de flujos de cargas sucesivos con jacobiana constante para la determinación del punto de colapso de tensión. Validación con patrón IEEE-14;Aplication of sucessive power flows with constant jacobian to obtain the point of voltage collapse. Test with IEEE-14 bus

    Zaid García - Sánchez, et al.

    2011-06-01

    Full Text Available Este trabajo presenta un método de solución para el análisis estático de las inestabilidades de tensión. El principal aporte del trabajo es la obtención de la región inestable de la curva P-V utilizando flujos sucesivos basados en un método Newton con jacobiana constante que mantiene los lazos de acoplamiento P-V y Q-δ. El algoritmo se implementó en el paquete de programas PSX, se modela la carga dependiente del voltaje, los límites de potencia activa y reactiva de las máquinas y la variación de la generación de potencia activa de los nodos P-V teniendo en cuenta la reserva de cada máquina que participa en la variación de generación. Se comparan los resultados con un flujo continuado implementado en el software PSAT para el patrón de 14 nodos de la IEEE. Para ambos casos se obtienen resultados muy similares, comprobándose así la exactitud obtenida con la técnica implementadaThis paper presents a solution method for tension instability static analyses. The main contribution of this research is the determinations of the unstable part of P-V curve using a multiple power flow based on the Newton method with constant Jacobian that keeps the links between P-V y Q-δ. This algorithm was implemented within PSX program, the load is modeled as voltage dependent and the limits of active and reactive power of the machines, plus the variation of P-V node generation, taking into account the reserve in each node. The result are compared with a continuation power flow implemented in PSAT software for a grid of 14 nodes patron. In both cases the result are very similar verifying the exactitude of the program developed.

  6. Built-in self-repair of VLSI memories employing neural nets

    Mazumder, Pinaki

    1998-10-01

    The decades of the Eighties and the Nineties have witnessed the spectacular growth of VLSI technology, when the chip size has increased from a few hundred devices to a staggering multi-millon transistors. This trend is expected to continue as the CMOS feature size progresses towards the nanometric dimension of 100 nm and less. SIA roadmap projects that, where as the DRAM chips will integrate over 20 billion devices in the next millennium, the future microprocessors may incorporate over 100 million transistors on a single chip. As the VLSI chip size increase, the limited accessibility of circuit components poses great difficulty for external diagnosis and replacement in the presence of faulty components. For this reason, extensive work has been done in built-in self-test techniques, but little research is known concerning built-in self-repair. Moreover, the extra hardware introduced by conventional fault-tolerance techniques is also likely to become faulty, therefore causing the circuit to be useless. This research demonstrates the feasibility of implementing electronic neural networks as intelligent hardware for memory array repair. Most importantly, we show that the neural network control possesses a robust and degradable computing capability under various fault conditions. Overall, a yield analysis performed on 64K DRAM's shows that the yield can be improved from as low as 20 percent to near 99 percent due to the self-repair design, with overhead no more than 7 percent.

  7. Advanced symbolic analysis for VLSI systems methods and applications

    Shi, Guoyong; Tlelo Cuautle, Esteban

    2014-01-01

    This book provides comprehensive coverage of the recent advances in symbolic analysis techniques for design automation of nanometer VLSI systems. The presentation is organized in parts of fundamentals, basic implementation methods and applications for VLSI design. Topics emphasized include  statistical timing and crosstalk analysis, statistical and parallel analysis, performance bound analysis and behavioral modeling for analog integrated circuits . Among the recent advances, the Binary Decision Diagram (BDD) based approaches are studied in depth. The BDD-based hierarchical symbolic analysis approaches, have essentially broken the analog circuit size barrier. In particular, this book   • Provides an overview of classical symbolic analysis methods and a comprehensive presentation on the modern  BDD-based symbolic analysis techniques; • Describes detailed implementation strategies for BDD-based algorithms, including the principles of zero-suppression, variable ordering and canonical reduction; • Int...

  8. Trace-based post-silicon validation for VLSI circuits

    Liu, Xiao

    2014-01-01

    This book first provides a comprehensive coverage of state-of-the-art validation solutions based on real-time signal tracing to guarantee the correctness of VLSI circuits.  The authors discuss several key challenges in post-silicon validation and provide automated solutions that are systematic and cost-effective.  A series of automatic tracing solutions and innovative design for debug (DfD) techniques are described, including techniques for trace signal selection for enhancing visibility of functional errors, a multiplexed signal tracing strategy for improving functional error detection, a tracing solution for debugging electrical errors, an interconnection fabric for increasing data bandwidth and supporting multi-core debug, an interconnection fabric design and optimization technique to increase transfer flexibility and a DfD design and associated tracing solution for improving debug efficiency and expanding tracing window. The solutions presented in this book improve the validation quality of VLSI circuit...

  9. Emerging Applications for High K Materials in VLSI Technology

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  10. Emerging Applications for High K Materials in VLSI Technology

    Robert D. Clark

    2014-04-01

    Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

  11. A VLSI image processor via pseudo-mersenne transforms

    Sei, W.J.; Jagadeesh, J.M.

    1986-01-01

    The computational burden on image processing in medical fields where a large amount of information must be processed quickly and accurately has led to consideration of special-purpose image processor chip design for some time. The very large scale integration (VLSI) resolution has made it cost-effective and feasible to consider the design of special purpose chips for medical imaging fields. This paper describes a VLSI CMOS chip suitable for parallel implementation of image processing algorithms and cyclic convolutions by using Pseudo-Mersenne Number Transform (PMNT). The main advantages of the PMNT over the Fast Fourier Transform (FFT) are: (1) no multiplications are required; (2) integer arithmetic is used. The design and development of this processor, which operates on 32-point convolution or 5 x 5 window image, are described

  12. Embedded Processor Based Automatic Temperature Control of VLSI Chips

    Narasimha Murthy Yayavaram

    2009-01-01

    Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

  13. Design of a VLSI Decoder for Partially Structured LDPC Codes

    Fabrizio Vacca

    2008-01-01

    of their parity matrix can be partitioned into two disjoint sets, namely, the structured and the random ones. For the proposed class of codes a constructive design method is provided. To assess the value of this method the constructed codes performance are presented. From these results, a novel decoding method called split decoding is introduced. Finally, to prove the effectiveness of the proposed approach a whole VLSI decoder is designed and characterized.

  14. Using Software Technology to Specify Abstract Interfaces in VLSI Design.

    1985-01-01

    with the complexity lev- els inherent in VLSI design, in that they can capitalize on their foundations in discrete mathemat- ics and the theory of...basis, rather than globally. Such a partitioning of module semantics makes the specification easier to construct and verify intelectual !y; it also...access function definitions. A standard language improves executability characteristics by capitalizing on portable, optimized system software developed

  15. vPELS: An E-Learning Social Environment for VLSI Design with Content Security Using DRM

    Dewan, Jahangir; Chowdhury, Morshed; Batten, Lynn

    2014-01-01

    This article provides a proposal for personal e-learning system (vPELS [where "v" stands for VLSI: very large scale integrated circuit])) architecture in the context of social network environment for VLSI Design. The main objective of vPELS is to develop individual skills on a specific subject--say, VLSI--and share resources with peers.…

  16. Real time track finding in a drift chamber with a VLSI neural network

    Lindsey, C.S.; Denby, B.; Haggerty, H.; Johns, K.

    1992-01-01

    In a test setup, a hardware neural network determined track parameters of charged particles traversing a drift chamber. Voltages proportional to the drift times in 6 cells of the 3-layer chamber were inputs to the Intel ETANN neural network chip which had been trained to give the slope and intercept of tracks. We compare network track parameters to those obtained from off-line track fits. To our knowledge this is the first on-line application of a VLSI neural network to a high energy physics detector. This test explored the potential of the chip and the practical problems of using it in a real world setting. We compare the chip performance to a neural network simulation on a conventional computer. We discuss possible applications of the chip in high energy physics detector triggers. (orig.)

  17. Las Vegas is better than determinism in VLSI and distributed computing

    Mehlhorn, Kurt; Schmidt, Erik Meineche

    1982-01-01

    In this paper we describe a new method for proving lower bounds on the complexity of VLSI - computations and more generally distributed computations. Lipton and Sedgewick observed that the crossing sequence arguments used to prove lower bounds in VLSI (or TM or distributed computing) apply to (ac...

  18. Operation of a Fast-RICH Prototype with VLSI readout electronics

    Guyonnet, J.L. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Arnold, R. (CRN, IN2P3-CNRS / Louis Pasteur Univ., Strasbourg (France)); Jobez, J.P. (Coll. de France, 75 - Paris (France)); Seguinot, J. (Coll. de France, 75 - Paris (France)); Ypsilantis, T. (Coll. de France, 75 - Paris (France)); Chesi, E. (CERN / ECP Div., Geneve (Switzerland)); Racz, A. (CERN / ECP Div., Geneve (Switzerland)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland)); Joram, C. (Karlsruhe Univ. (Germany)); Adachi, I. (KEK, Tsukuba (Japan)); Enomoto, R. (KEK, Tsukuba (Japan)); Sumiyoshi, T. (KEK, Tsukuba (Japan))

    1994-04-01

    We discuss the first test results, obtained with cosmic rays, of a full-scale Fast-RICH Prototype with proximity-focused 10 mm thick LiF (CaF[sub 2]) solid radiators, TEA as photosensor in CH[sub 4], and readout of 12 x 10[sup 3] cathode pads (5.334 x 6.604 mm[sup 2]) using dedicated VLSI electronics we have developed. The number of detected photoelectrons is 7.7 (6.9) for the CaF[sub 2] (LiF) radiator, very near to the expected values 6.4 (7.5) from Monte Carlo simulations. The single-photon Cherenkov angle resolution [sigma][sub [theta

  19. Application of IEEE 1588 to the real-time control system of accelerator

    Ma Mingchao; Chen Jianfeng; Shen Liren; Jiang Geyang

    2014-01-01

    Background: Time synchronization is one of the core technology of realizing the real-time control of accelerator under the distributed control system architecture. The ordinary crystal frequency deviation of IEEE 1588 causes low synchronous accuracy, which doesn't meet the needs of high precision synchronization. Purpose: This paper proposes an algorithm to improve the synchronization precision caused by the crystal frequency deviation. Methods: According to the basic principle of IEEE 1588 time synchronization, a dynamic frequency compensation (DFC) algorithm module was designed and a test platform was built to verify the feasibility and practicability of the algorithm. The influence of the synchronous cycle and delay jitter of the switch on the synchronization accuracy were analyzed. Results: Experimental results showed the great precision improvement of synchronization after using DFC algorithm. Conclusion: Low synchronous accuracy caused by the crystal frequency deviation can be improved by using DFC algorithm implemented for precision time protocol (PTP) of IEEE 1588. (authors)

  20. Point DCT VLSI Architecture for Emerging HEVC Standard

    Ahmed, Ashfaq; Shahid, Muhammad Usman; Rehman, Ata ur

    2012-01-01

    This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4 × 4 up to 3 2 × 3 2 , the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into ...

  1. VLSI architectures for modern error-correcting codes

    Zhang, Xinmiao

    2015-01-01

    Error-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI

  2. Power efficient and high performance VLSI architecture for AES algorithm

    K. Kalaiselvi

    2015-09-01

    Full Text Available Advanced encryption standard (AES algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The VHDL language is utilized for simulating the design and an FPGA chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput and critical path delay.

  3. Formal verification an essential toolkit for modern VLSI design

    Seligman, Erik; Kumar, M V Achutha Kiran

    2015-01-01

    Formal Verification: An Essential Toolkit for Modern VLSI Design presents practical approaches for design and validation, with hands-on advice for working engineers integrating these techniques into their work. Building on a basic knowledge of System Verilog, this book demystifies FV and presents the practical applications that are bringing it into mainstream design and validation processes at Intel and other companies. The text prepares readers to effectively introduce FV in their organization and deploy FV techniques to increase design and validation productivity. Presents formal verific

  4. 7th IEEE International Conference Intelligent Systems

    Atanassov, KT; Doukovska, L; Hadjiski, M; Jotsov, V; Kacprzyk, J; Kasabov, N; Sotirov, S; Szmidt, E; Zadrożny, S; Filev, D; Jabłkowski, J; Kacprzyk, J; Krawczak, M; Popchev, I; Rutkowski, L; Sgurev, V; Sotirova, E; Szynkarczyk, P

    2015-01-01

    This two volume set of books constitutes the proceedings of the 2014  7th IEEE International Conference Intelligent Systems (IS), or IEEE IS’2014 for short, held on September 24‐26, 2014 in Warsaw, Poland. Moreover, it contains some selected papers from the collocated IWIFSGN'2014-Thirteenth International Workshop on Intuitionistic Fuzzy Sets and Generalized Nets.The conference was organized by the Systems Research Institute, Polish Academy of Sciences, Department IV of Engineering Sciences, Polish Academy of Sciences, and Industrial Institute of Automation and Measurements - PIAP.The papers included in the two proceedings volumes have been subject to a thorough review process by three highly qualified peer reviewers.Comments and suggestions from them have considerable helped improve the quality of the papers but also the division of the volumes into parts, and assignment of the papers to the best suited parts.  

  5. IEEE 802.11 ECG monitoring system.

    Tejero-Calado, Juan; Lopez-Casado, Carmen; Bernal-Martin, Antonio; Lopez-Gomez, Miguel; Romero-Romero, Marco; Quesada, Guillermo; Lorca, Julio; Rivas, Ramon

    2005-01-01

    New wireless technologies make possible the implementation of high level integration wireless devices which allow the replacement of traditional large wired monitoring devices. This kind of devices favours at-home hospitalization, reducing the affluence to sanitary assistance centers to make routine controls. This fact causes a really favourable social impact, especially for elder people, rural-zone inhabitant, chronic patients and handicapped people. Furthermore, it offers new functionalities to physicians and will reduce the sanitary cost. Among these functionalities, biomedical signals can be sent to other devices (screen, PDA, PC...) or processing centers, without restricting the patients' mobility. The aim of this project is the development and implementation of a reduced size multi-channel electrocardiograph based on IEEE 802.11, which allows wireless monitoring of patients, and the insertion of the information into the TCP/IP Hospital network.

  6. Qualification of cables to IEEE standards 323-1974 and 383-1974

    Hosticka, C.; Kingsbury, E.R.; Bruhin, A.C.

    1980-01-01

    Wire and Cable manufacturers generally qualify products for class IE application by envelope type testing to user specifications and environmental conditions recommended by IEEE Standards 323-1974 and 383-1974. The General Electric Wire and Cable Business Department recently completed two such qualification programs. Cable constructions tested were 600V control cables and 600 V, 2kV, and 15kV power cables insulated with flame resistant mineral filled crosslinked polyethylene. The 15kV samples included taped field splices. In the second test program, the steam pressure-temperature profile included a simulated main steam line break. Test specimens were wrapped on grounded mandrels and were electrically loaded throughout the simulated LOCA tests. After completion of environmental testing, samples were subjected to the IEEE 383 simulated post-LOCA test. 6 refs

  7. Qualification of cables to IEEE standards 323-1974 and 383-1974

    Hosticka, C.; Kingsbury, E.R.; Bruhin, A.C.

    1980-01-01

    Wire and Cable manufacturers generally qualify products for class IE application by envelope type testing to user specifications and environmental conditions recommended by IEEE Standards 323-1974 and 383-1974. The General Electric Wire and Cable Business Department recently completed two such qualification programs. Cable constructions tested were 600V control cables and 600 V, 2KV, and 15KV power cables insulated with flame resistant mineral filled crosslinked polyethylene. The 15KV samples included taped field splices. In the second test program, the steam pressure-temperature profile included a simulated main steam line break. Test specimens were wrapped on grounded mandrels and were electrically loaded throughout the simulated LOCA tests. After completion of environmental testing, samples were subjected to the IEEE 383 simulated post-LOCA test. 6 refs

  8. Opto-VLSI-based reconfigurable free-space optical interconnects architecture

    Aljada, Muhsen; Alameh, Kamal; Chung, Il-Sug

    2007-01-01

    is the Opto-VLSI processor which can be driven by digital phase steering and multicasting holograms that reconfigure the optical interconnects between the input and output ports. The optical interconnects architecture is experimentally demonstrated at 2.5 Gbps using high-speed 1×3 VCSEL array and 1......×3 photoreceiver array in conjunction with two 1×4096 pixel Opto-VLSI processors. The minimisation of the crosstalk between the output ports is achieved by appropriately aligning the VCSEL and PD elements with respect to the Opto-VLSI processors and driving the latter with optimal steering phase holograms....

  9. Assimilation of Biophysical Neuronal Dynamics in Neuromorphic VLSI.

    Wang, Jun; Breen, Daniel; Akinin, Abraham; Broccard, Frederic; Abarbanel, Henry D I; Cauwenberghs, Gert

    2017-12-01

    Representing the biophysics of neuronal dynamics and behavior offers a principled analysis-by-synthesis approach toward understanding mechanisms of nervous system functions. We report on a set of procedures assimilating and emulating neurobiological data on a neuromorphic very large scale integrated (VLSI) circuit. The analog VLSI chip, NeuroDyn, features 384 digitally programmable parameters specifying for 4 generalized Hodgkin-Huxley neurons coupled through 12 conductance-based chemical synapses. The parameters also describe reversal potentials, maximal conductances, and spline regressed kinetic functions for ion channel gating variables. In one set of experiments, we assimilated membrane potential recorded from one of the neurons on the chip to the model structure upon which NeuroDyn was designed using the known current input sequence. We arrived at the programmed parameters except for model errors due to analog imperfections in the chip fabrication. In a related set of experiments, we replicated songbird individual neuron dynamics on NeuroDyn by estimating and configuring parameters extracted using data assimilation from intracellular neural recordings. Faithful emulation of detailed biophysical neural dynamics will enable the use of NeuroDyn as a tool to probe electrical and molecular properties of functional neural circuits. Neuroscience applications include studying the relationship between molecular properties of neurons and the emergence of different spike patterns or different brain behaviors. Clinical applications include studying and predicting effects of neuromodulators or neurodegenerative diseases on ion channel kinetics.

  10. Development of Radhard VLSI electronics for SSC calorimeters

    Dawson, J.W.; Nodulman, L.J.

    1989-01-01

    A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

  11. IEEE International Workshop on Machine Learning for Signal Processing: Preface

    Tao, Jianhua

    The 21st IEEE International Workshop on Machine Learning for Signal Processing will be held in Beijing, China, on September 18–21, 2011. The workshop series is the major annual technical event of the IEEE Signal Processing Society's Technical Committee on Machine Learning for Signal Processing...

  12. Proceedings of IEEE Machine Learning for Signal Processing Workshop XV

    Larsen, Jan

    These proceedings contains refereed papers presented at the Fifteenth IEEE Workshop on Machine Learning for Signal Processing (MLSP’2005), held in Mystic, Connecticut, USA, September 28-30, 2005. This is a continuation of the IEEE Workshops on Neural Networks for Signal Processing (NNSP) organized...... by the NNSP Technical Committee of the IEEE Signal Processing Society. The name of the Technical Committee, hence of the Workshop, was changed to Machine Learning for Signal Processing in September 2003 to better reflect the areas represented by the Technical Committee. The conference is organized...... by the Machine Learning for Signal Processing Technical Committee with sponsorship of the IEEE Signal Processing Society. Following the practice started two years ago, the bound volume of the proceedings is going to be published by IEEE following the Workshop, and we are pleased to offer to conference attendees...

  13. IEEE Std 323-1983: IEEE standard for qualifying Class 1E equipment for nuclear power generating stations

    Anon.

    1992-01-01

    This standard describes the basic requirements for qualifying Class 1E equipment with interfaces that are to be used in nuclear power generating stations. The requirements presented include the principles, procedures, and methods of qualification. These qualification requirements, when met, will confirm the adequacy of the equipment design under normal, abnormal, design basis event, post design basis event, and in-service test conditions for the performance of safety function(s). The purpose of this standard is to identify requirements for the qualification of Class 1E equipment, including those interfaces whose failure could adversely affect the performance of Class 1E equipment and systems. The methods described shall be used for qualifying equipment, extending qualification, and updating qualification if the equipment is modified. Other issued IEEE standards which present qualification methods for specific equipment or components, or both, and those that deal with parts of the qualification program, may be used to supplement this standard, as applicable

  14. Performance comparison of IEEE 802.11g and IEEE 802.11n in the presence of interference from 802.15.4 networks

    Masood, Syed Haani

    2013-01-01

    In this paper we compare the packet error rate (PER) and maximum throughput of IEEE 802.11n and IEEE 802.11g under interference from IEEE 802.15.4 by using MATLAB to simulate the IEEE PHY for 802.11n and 802.11g networks.

  15. A coexistence model of IEEE 802.15.4 and IEEE 802.1 lbIg

    Yuan, Wei; Wang, Xiangyu; Linnartz, J.P.M.G.

    2007-01-01

    IEEE 802.15.4 was developed to meet the needs for low-rate wireless communication. However, due to its low power, IEEE 802.15.4 is potentially vulnerable to interference by other wireless technologies having much higher power and working in the same industrial, scientific, and medical (ISM) band

  16. Active Channel Reservation for Coexistence Mechanism (ACROS) for IEEE 802.15.4 and IEEE 802.11

    Shin, Soo Young; Woo, Dong Hyuk; Lee, Jong Wook; Park, Hong Seong; Kwon, Wook Hyun

    In this paper, a coexistence mechanism between IEEE 802.15.4 and IEEE 802.11b, Active Channel Reservation for cOexiStence (ACROS), is proposed. The key idea underlining ACROS is to reserve the channel for IEEE 802.15.4 transmission, where IEEE 802.11 transmissions are forbidden. The request-to-send (RTS)/clear-to send (CTS) mechanism within IEEE 802.11 is used to reserve a channel. The proposed ACROS mechanism is implemented into a PC based prototype. The embedded version of ACROS is also developed to mitigate the timing drift problem in the PC-based ACROS. The efficiency of ACROS is shown using the throughput and packet error rate achieved in actual experiments.

  17. Custom VLSI circuits for high energy physics

    Parker, S.

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner's guide through the maze, and that is the main purpose of this text

  18. Custom VLSI circuits for high energy physics

    Parker, S. [Univ. of Hawaii, Honolulu, HI (United States)

    1998-06-01

    This article provides a brief guide to integrated circuits, including their design, fabrication, testing, radiation hardness, and packaging. It was requested by the Panel on Instrumentation, Innovation, and Development of the International Committee for Future Accelerators, as one of a series of articles on instrumentation for future experiments. Their original request emphasized a description of available custom circuits and a set of recommendations for future developments. That has been done, but while traps that stop charge in solid-state devices are well known, those that stop physicists trying to develop the devices are not. Several years spent dodging the former and developing the latter made clear the need for a beginner`s guide through the maze, and that is the main purpose of this text.

  19. VLSI Architectures for the Multiplication of Integers Modulo a Fermat Number

    Chang, J. J.; Truong, T. K.; Reed, I. S.; Hsu, I. S.

    1984-01-01

    Multiplication is central in the implementation of Fermat number transforms and other residue number algorithms. There is need for a good multiplication algorithm that can be realized easily on a very large scale integration (VLSI) chip. The Leibowitz multiplier is modified to realize multiplication in the ring of integers modulo a Fermat number. This new algorithm requires only a sequence of cyclic shifts and additions. The designs developed for this new multiplier are regular, simple, expandable, and, therefore, suitable for VLSI implementation.

  20. IEEE C37.105-1987: IEEE standard for qualifying Class 1E protective relays and auxiliaries for nuclear power generating stations

    Anon.

    1992-01-01

    This standard describes the basic principles, requirements, and methods for qualifying Class 1E protective relays and auxiliaries such as test and control switches, terminal blocks, and indicating lamps for applications in nuclear power generating stations. When properly employed it can be used to demonstrate the design adequacy of such equipment under normal, abnormal, design basis event and post design basis event conditions in accordance with ANSI/IEEE Std 323-1983. When protective relays and auxiliaries are located in areas not subject to harsh environments, environmental qualification is not required. Protective relays and auxiliaries located inside primary containment in a nuclear power generating station present special conditions beyond the scope of this document. The qualification procedure presented is generic in nature. Other methods may be used at the discretion of the qualifier, provided the basic precepts of ANSI/IEEE Std 32301983 are satisfied

  1. VLSI and system architecture-the new development of system 5G

    Sakamura, K.; Sekino, A.; Kodaka, T.; Uehara, T.; Aiso, H.

    1982-01-01

    A research and development proposal is presented for VLSI CAD systems and for a hardware environment called system 5G on which the VLSI CAD systems run. The proposed CAD systems use a hierarchically organized design language to enable design of anything from basic architectures of VLSI to VLSI mask patterns in a uniform manner. The cad systems will eventually become intelligent cad systems that acquire design knowledge and perform automatic design of VLSI chips when the characteristic requirements of VLSI chip is given. System 5G will consist of superinference machines and the 5G communication network. The superinference machine will be built based on a functionally distributed architecture connecting inferommunication network. The superinference machine will be built based on a functionally distributed architecture connecting inference machines and relational data base machines via a high-speed local network. The transfer rate of the local network will be 100 mbps at the first stage of the project and will be improved to 1 gbps. Remote access to the superinference machine will be possible through the 5G communication network. Access to system 5G will use the 5G network architecture protocol. The users will access the system 5G using standardized 5G personal computers. 5G personal logic programming stations, very high intelligent terminals providing an instruction set that supports predicate logic and input/output facilities for audio and graphical information.

  2. Modeling selective attention using a neuromorphic analog VLSI device.

    Indiveri, G

    2000-12-01

    Attentional mechanisms are required to overcome the problem of flooding a limited processing capacity system with information. They are present in biological sensory systems and can be a useful engineering tool for artificial visual systems. In this article we present a hardware model of a selective attention mechanism implemented on a very large-scale integration (VLSI) chip, using analog neuromorphic circuits. The chip exploits a spike-based representation to receive, process, and transmit signals. It can be used as a transceiver module for building multichip neuromorphic vision systems. We describe the circuits that carry out the main processing stages of the selective attention mechanism and provide experimental data for each circuit. We demonstrate the expected behavior of the model at the system level by stimulating the chip with both artificially generated control signals and signals obtained from a saliency map, computed from an image containing several salient features.

  3. Point DCT VLSI Architecture for Emerging HEVC Standard

    Ashfaq Ahmed

    2012-01-01

    Full Text Available This work presents a flexible VLSI architecture to compute the -point DCT. Since HEVC supports different block sizes for the computation of the DCT, that is, 4×4 up to 32×32, the design of a flexible architecture to support them helps reducing the area overhead of hardware implementations. The hardware proposed in this work is partially folded to save area and to get speed for large video sequences sizes. The proposed architecture relies on the decomposition of the DCT matrices into sparse submatrices in order to reduce the multiplications. Finally, multiplications are completely eliminated using the lifting scheme. The proposed architecture sustains real-time processing of 1080P HD video codec running at 150 MHz.

  4. VLSI-based video event triggering for image data compression

    Williams, Glenn L.

    1994-02-01

    Long-duration, on-orbit microgravity experiments require a combination of high resolution and high frame rate video data acquisition. The digitized high-rate video stream presents a difficult data storage problem. Data produced at rates of several hundred million bytes per second may require a total mission video data storage requirement exceeding one terabyte. A NASA-designed, VLSI-based, highly parallel digital state machine generates a digital trigger signal at the onset of a video event. High capacity random access memory storage coupled with newly available fuzzy logic devices permits the monitoring of a video image stream for long term (DC-like) or short term (AC-like) changes caused by spatial translation, dilation, appearance, disappearance, or color change in a video object. Pre-trigger and post-trigger storage techniques are then adaptable to archiving only the significant video images.

  5. Carbon nanotube based VLSI interconnects analysis and design

    Kaushik, Brajesh Kumar

    2015-01-01

    The brief primarily focuses on the performance analysis of CNT based interconnects in current research scenario. Different CNT structures are modeled on the basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The brief is organized into five chapters which mainly discuss: (1) an overview of current research scenario and basics of interconnects; (2) unique crystal structures and the basics of physical properties of CNTs, and the production, purification and applications of CNTs; (3) a brief technical review, the geometry and equivalent RLC parameters for different single and bundled CNT structures; (4) a comparative analysis of crosstalk and delay for different single and bundled CNT structures; and (5) various unique mixed CNT bundle structures and their equivalent electrical models.

  6. Attacks on IEEE 802.11 wireless networks

    Dejan Milan Tepšić

    2013-06-01

    networking it has never been easier to penetrate the network. One of the biggest problems of today's wireless networks is the lack of effective systems for intrusion detection. Forgetting to cover gaps in wireless network security may result in intrusion into the network by an attacker. Security in IEEE 802.11 wireless networks Although the IEEE 802.11 protocol defines security standards, wireless networks are one of the weakest links in the chain of computer networks. The basic security requirements of each computer network are reliable user authentication, privacy protection and user authentication. Security attacks on IEEE 802.11 wireless networks Non-technical attacks include a variety of human weaknesses, such as lack of conscience, negligence or over-confidence towards the strangers. Network attacks include a number of techniques that enable attackers to penetrate into  the wireless network, or at least to disable it. Apart from the security problems with the IEEE 802.11 protocol, there are vulnerabilities in operating systems and applications on wireless clients. The methodology of attack Before testing wireless network security vulnerabilities, it is important to define a formal testing methodology. The first step before the actual attack is footprinting. The second step is the creation of a network map that shows how the wireless system looks. For this purpose, hackers are using specific tools, such as Network Stumbler, Nmap and Fping. When basic information about the wireless network is gathered, more information can be found out through the process of system scanning (enumeration. Attacks on IEEE 802.11 wireless networks Social engineering is a technique by which attackers exploit the natural trust of most people. Radio waves do not respect defined boundaries. If radio waves are broadcasted outside of the boundaries of the defined area, then it is necessary to reduce signal strength on wireless access points. In that way, radio waves travel over shorter distances

  7. Guest editors' introduction : Highlights from IEEE Pacific Visualization

    Wijk, van J.J.; North, S.; Shen, H.-W.

    2010-01-01

    This article looks briefly at four articles based on papers from the 2010 IEEE Pacific Visualization Symposium. These articles, which strongly focus on visual design and applications, cover a range of applications in scientific visualization, information visualization, and graph visualization,

  8. IEEE Conference Record - Abstracts. 1997 IEEE International Conference on Plasma Science, 19 - 22 May 1997 San Diego, California

    Hyman, Julius

    1997-01-01

    This 360 page softbound publication includes the following major sections. An invitation to ICOPS'97, Catamaran Resort Hotel Floor Pinas, Officers of the IEEE Nuclear and Plasma Sciences Society, Conference Information...

  9. Digital VLSI design with Verilog a textbook from Silicon Valley Polytechnic Institute

    Williams, John Michael

    2014-01-01

    This book is structured as a step-by-step course of study along the lines of a VLSI integrated circuit design project.  The entire Verilog language is presented, from the basics to everything necessary for synthesis of an entire 70,000 transistor, full-duplex serializer-deserializer, including synthesizable PLLs.  The author includes everything an engineer needs for in-depth understanding of the Verilog language:  Syntax, synthesis semantics, simulation, and test. Complete solutions for the 27 labs are provided in the downloadable files that accompany the book.  For readers with access to appropriate electronic design tools, all solutions can be developed, simulated, and synthesized as described in the book.   A partial list of design topics includes design partitioning, hierarchy decomposition, safe coding styles, back annotation, wrapper modules, concurrency, race conditions, assertion-based verification, clock synchronization, and design for test.   A concluding presentation of special topics inclu...

  10. Delay Analysis of GTS Bridging between IEEE 802.15.4 and IEEE 802.11 Networks for Healthcare Applications

    Mišić, Jelena; (Sherman) Shen, Xuemin

    2009-01-01

    We consider interconnection of IEEE 802.15.4 beacon-enabled network cluster with IEEE 802.11b network. This scenario is important in healthcare applications where IEEE 802.15.4 nodes comprise patient's body area network (BAN) and are involved in sensing some health-related data. BAN nodes have very short communication range in order to avoid harming patient's health and save energy. Sensed data needs to be transmitted to an access point in the ward room using wireless technology with higher transmission range and rate such as IEEE 802.11b. We model the interconnected network where IEEE 802.15.4-based BAN operates in guaranteed time slot (GTS) mode, and IEEE 802.11b part of the bridge conveys GTS superframe to the 802.11b access point. We then analyze the network delays. Performance analysis is performed using EKG traffic from continuous telemetry, and we discuss the delays of communication due the increasing number of patients. PMID:19107184

  11. Delay Analysis of GTS Bridging between IEEE 802.15.4 and IEEE 802.11 Networks for Healthcare Applications.

    Misić, Jelena; Sherman Shen, Xuemin

    2009-01-01

    We consider interconnection of IEEE 802.15.4 beacon-enabled network cluster with IEEE 802.11b network. This scenario is important in healthcare applications where IEEE 802.15.4 nodes comprise patient's body area network (BAN) and are involved in sensing some health-related data. BAN nodes have very short communication range in order to avoid harming patient's health and save energy. Sensed data needs to be transmitted to an access point in the ward room using wireless technology with higher transmission range and rate such as IEEE 802.11b. We model the interconnected network where IEEE 802.15.4-based BAN operates in guaranteed time slot (GTS) mode, and IEEE 802.11b part of the bridge conveys GTS superframe to the 802.11b access point. We then analyze the network delays. Performance analysis is performed using EKG traffic from continuous telemetry, and we discuss the delays of communication due the increasing number of patients.

  12. Simulasi Kinerja Jaringan Nirkabel IEEE-802.11a dan IEEE-802.11g Menggunakan NS-2

    Helm Fitriawan

    2014-03-01

    Full Text Available Wireless network uses transmission media based on radio waves. This type of networks is mainly useddue to its efficiency and mobility in data exchanging. This paper reports the modeling and simulation of wirelessnetworks based on Cisco Aironet 1130ag access point devices with IEEE 802.11a and IEEE 802.11g standards. Themodeling and simulation are performed using network simulator version 2 (NS-2 that is installed on operationsystem Linux Ubuntu v.10.10. The NS-2 is commonly used and works well in numerous types of network simulation. From simulation, we obtain quality of service parameters by employing several simulation scenarios in terms ofnumber of nodes, distances, and packet data sizes. It can be concluded from simulation results that the IEEE 802.11gnetworks transfer data with better quality than those of IEEE 802.11a networks.  Furthermore, the IEEE 802.11gnetworks provide a higher throughput, with smaller amount of delay and packet loss percentage compared to thoseof IEEE 802.11a networks.

  13. A versatile electrical penetration design qualified to IEEE Std. 317-1983

    Lankenau, W.; Wetherill, T.M.

    1994-01-01

    Although worldwide demand for new construction of nuclear power stations has been on a decline, the available opportunities for the design and construction of qualified electrical penetrations continues to offer challenges, requiring a highly versatile design. Versatility is necessary in order to meet unique customer requirements within the constraints of a design basis qualified to IEEE Std. 317-1983. This paper summarizes such a versatile electrical penetration designed, built and tested to IEEE Std. 317-1983. The principal features are described including major materials of construction. Some of the design constraints such as sealing requirements, and conductor density (including numerical example) are discussed. The requirements for qualification testing of the penetration assembly to IEEE Std. 317-1983 are delineated in a general sense, and some typical test ranges for preconditioning, radiation exposure, and LOCA are provided. The paper concludes by describing ways in which this versatile design has been adapted to meet unique customer requirements in a variety of nuclear power plants

  14. IEEE 693 seismic qualification of composites for substation high-voltage equipment

    Schiff, A.J. [Precision Measurement Instruments, Los Altos Hills, CA (United States); Kempner, L.Jr. [Bonneville Power Administration, Vancouver, BC (Canada)

    2004-07-01

    Standard 693-1997 of the Institute of Electrical and Electronic Engineers (IEEE) is the recommended practice for seismic design of substations. It represents a significant improvement in the way the power industry seismically qualifies substation high-voltage equipment. This paper described the use of IEEE Standard 693 for hollow-core composite insulators that are used on high-voltage transformers and demonstrated that changes are warranted. The following four failure modes associated with the composite insulator were discussed: bond degradation, bond failure, tube degradation and tube layer delamination. The authors evaluated the IEEE 693 qualification procedure of time history shake-table and static-pull tests and were concerned about acceptance criteria. It was shown that acceptance criteria are not valid for qualifying hollow-core composites and that static-pull tests are needed after the vibration qualification tests are completed. It was suggested that more research is warranted to determine if bonding at the top part of the flange can be eliminated, thereby eliminating bond degradation. The resulting increase in system damping would improve the dynamic response of the unit. 1 ref., 10 figs.

  15. An Asynchronous IEEE Floating-Point Arithmetic Unit

    Joel R. Noche

    2007-12-01

    Full Text Available An asynchronous floating-point arithmetic unit is designed and tested at the transistor level usingCadence software. It uses CMOS (complementary metal oxide semiconductor and DCVS (differentialcascode voltage switch logic in a 0.35 µm process using a 3.3 V supply voltage, with dual-rail data andsingle-rail control signals using four-phase handshaking.Using 17,085 transistors, the unit handles single-precision (32-bit addition/subtraction, multiplication,division, and remainder using the IEEE 754-1985 Standard for Binary Floating-Point Arithmetic, withrounding and other operations to be handled by separate hardware or software. Division and remainderare done using a restoring subtractive algorithm; multiplication uses an additive algorithm. Exceptionsare noted by flags (and not trap handlers and the output is in single-precision.Previous work on asynchronous floating-point arithmetic units have mostly focused on single operationssuch as division. This is the first work to the authors' knowledge that can perform floating-point addition,multiplication, division, and remainder using a common datapath.

  16. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    McEwan, Alistair; van Schaik, André

    2003-12-01

    The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a) rate level functions for onset and steady-state response, (b) recovery after masking, (c) additivity, (d) two-component adaptation, (e) phase locking, (f) recovery of spontaneous activity, and (g) computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  17. An Analogue VLSI Implementation of the Meddis Inner Hair Cell Model

    Alistair McEwan

    2003-06-01

    Full Text Available The Meddis inner hair cell model is a widely accepted, but computationally intensive computer model of mammalian inner hair cell function. We have produced an analogue VLSI implementation of this model that operates in real time in the current domain by using translinear and log-domain circuits. The circuit has been fabricated on a chip and tested against the Meddis model for (a rate level functions for onset and steady-state response, (b recovery after masking, (c additivity, (d two-component adaptation, (e phase locking, (f recovery of spontaneous activity, and (g computational efficiency. The advantage of this circuit, over other electronic inner hair cell models, is its nearly exact implementation of the Meddis model which can be tuned to behave similarly to the biological inner hair cell. This has important implications on our ability to simulate the auditory system in real time. Furthermore, the technique of mapping a mathematical model of first-order differential equations to a circuit of log-domain filters allows us to implement real-time neuromorphic signal processors for a host of models using the same approach.

  18. CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

    Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

    1996-01-01

    In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

  19. A High Performance VLSI Computer Architecture For Computer Graphics

    Chin, Chi-Yuan; Lin, Wen-Tai

    1988-10-01

    A VLSI computer architecture, consisting of multiple processors, is presented in this paper to satisfy the modern computer graphics demands, e.g. high resolution, realistic animation, real-time display etc.. All processors share a global memory which are partitioned into multiple banks. Through a crossbar network, data from one memory bank can be broadcasted to many processors. Processors are physically interconnected through a hyper-crossbar network (a crossbar-like network). By programming the network, the topology of communication links among processors can be reconfigurated to satisfy specific dataflows of different applications. Each processor consists of a controller, arithmetic operators, local memory, a local crossbar network, and I/O ports to communicate with other processors, memory banks, and a system controller. Operations in each processor are characterized into two modes, i.e. object domain and space domain, to fully utilize the data-independency characteristics of graphics processing. Special graphics features such as 3D-to-2D conversion, shadow generation, texturing, and reflection, can be easily handled. With the current high density interconnection (MI) technology, it is feasible to implement a 64-processor system to achieve 2.5 billion operations per second, a performance needed in most advanced graphics applications.

  20. Adaptive WTA with an analog VLSI neuromorphic learning chip.

    Häfliger, Philipp

    2007-03-01

    In this paper, we demonstrate how a particular spike-based learning rule (where exact temporal relations between input and output spikes of a spiking model neuron determine the changes of the synaptic weights) can be tuned to express rate-based classical Hebbian learning behavior (where the average input and output spike rates are sufficient to describe the synaptic changes). This shift in behavior is controlled by the input statistic and by a single time constant. The learning rule has been implemented in a neuromorphic very large scale integration (VLSI) chip as part of a neurally inspired spike signal image processing system. The latter is the result of the European Union research project Convolution AER Vision Architecture for Real-Time (CAVIAR). Since it is implemented as a spike-based learning rule (which is most convenient in the overall spike-based system), even if it is tuned to show rate behavior, no explicit long-term average signals are computed on the chip. We show the rule's rate-based Hebbian learning ability in a classification task in both simulation and chip experiment, first with artificial stimuli and then with sensor input from the CAVIAR system.

  1. Monolithic active pixel sensors (MAPS) in a VLSI CMOS technology

    Turchetta, R; Manolopoulos, S; Tyndel, M; Allport, P P; Bates, R; O'Shea, V; Hall, G; Raymond, M

    2003-01-01

    Monolithic Active Pixel Sensors (MAPS) designed in a standard VLSI CMOS technology have recently been proposed as a compact pixel detector for the detection of high-energy charged particle in vertex/tracking applications. MAPS, also named CMOS sensors, are already extensively used in visible light applications. With respect to other competing imaging technologies, CMOS sensors have several potential advantages in terms of low cost, low power, lower noise at higher speed, random access of pixels which allows windowing of region of interest, ability to integrate several functions on the same chip. This brings altogether to the concept of 'camera-on-a-chip'. In this paper, we review the use of CMOS sensors for particle physics and we analyse their performances in term of the efficiency (fill factor), signal generation, noise, readout speed and sensor area. In most of high-energy physics applications, data reduction is needed in the sensor at an early stage of the data processing before transfer of the data to ta...

  2. CAPCAL, 3-D Capacitance Calculator for VLSI Purposes

    Seidl, Albert; Klose, Helmut; Svoboda, Mildos

    2004-01-01

    1 - Description of program or function: CAPCAL is devoted to the calculation of capacitances of three-dimensional wiring configurations are typically used in VLSI circuits. Due to analogies in the mathematical description also conductance and heat transport problems can be treated by CAPCAL. To handle the problem using CAPCAL same approximations have to be applied to the structure under investigation: - the overall geometry has to be confined to a finite domain by using symmetry-properties of the problem - Non-rectangular structures have to be simplified into an artwork of multiple boxes. 2 - Method of solution: The electrical field is described by the Laplace-equation. The differential equation is discretized by using the finite difference method. NEA-1327/01: The linear equation system is solved by using a combined ADI-multigrid method. NEA-1327/04: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. NEA-1327/05: The linear equation system is solved by using a conjugate gradient method for CAPCAL V1.3. 3 - Restrictions on the complexity of the problem: NEA-1327/01: Certain restrictions of use may arise from the dimensioning of arrays. Field lengths are defined via PARAMETER-statements which can easily by modified. If the geometry of the problem is defined such that Neumann boundaries are dominating the convergence of the iterative equation system solver is affected

  3. Fiber optics backbone for IEEE 802.3 networks

    Shani, Ron

    1990-01-01

    In the last few years the IEEE 802.3 committee has developed fiber optics inter-repeater link standard called FOIRL. This standard defines the "Fiber Optics Media Access Unit" (FOMAU) which is used to connect two IEEE 802.3 repeaters that are up to 1Km apart. The IEEE 802.3 lOBaseF task force is currently standardizing a full F/O system in two directions: passive and active. The active approach is a compromise between the FOIRL (Asynchronous) approach and the Synchronous approach. As a result of this activity the IEEE 802.3 standard will define three different F/O interfaces and several devices that will not inter-operate. Such a standard will lower the credibility among the IEEE 802.3 user community, as customers will be confused amidst the many chapters and devices with no clear choice. This paper describes a method that can reduce the number of standards to two (passive and active), while proposing a solution for all the requirements of 802.3 F/O LAN. (The question of passive vs active approach will be discussed in this paper).

  4. A second generation 50 Mbps VLSI level zero processing system prototype

    Harris, Jonathan C.; Shi, Jeff; Speciale, Nick; Bennett, Toby

    1994-01-01

    Level Zero Processing (LZP) generally refers to telemetry data processing functions performed at ground facilities to remove all communication artifacts from instrument data. These functions typically include frame synchronization, error detection and correction, packet reassembly and sorting, playback reversal, merging, time-ordering, overlap deletion, and production of annotated data sets. The Data Systems Technologies Division (DSTD) at Goddard Space Flight Center (GSFC) has been developing high-performance Very Large Scale Integration Level Zero Processing Systems (VLSI LZPS) since 1989. The first VLSI LZPS prototype demonstrated 20 Megabits per second (Mbp's) capability in 1992. With a new generation of high-density Application-specific Integrated Circuits (ASIC) and a Mass Storage System (MSS) based on the High-performance Parallel Peripheral Interface (HiPPI), a second prototype has been built that achieves full 50 Mbp's performance. This paper describes the second generation LZPS prototype based upon VLSI technologies.

  5. Implicit Block ACK Scheme for IEEE 802.11 WLANs

    Sthapit, Pranesh; Pyun, Jae-Young

    2016-01-01

    The throughput of IEEE 802.11 standard is significantly bounded by the associated Medium Access Control (MAC) overhead. Because of the overhead, an upper limit exists for throughput, which is bounded, including situations where data rates are extremely high. Therefore, an overhead reduction is necessary to achieve higher throughput. The IEEE 802.11e amendment introduced the block ACK mechanism, to reduce the number of control messages in MAC. Although the block ACK scheme greatly reduces overhead, further improvements are possible. In this letter, we propose an implicit block ACK method that further reduces the overhead associated with IEEE 802.11e’s block ACK scheme. The mathematical analysis results are presented for both the original protocol and the proposed scheme. A performance improvement of greater than 10% was achieved with the proposed implementation.

  6. IEEE guide for the analysis of human reliability

    Dougherty, E.M. Jr.

    1987-01-01

    The Institute of Electrical and Electronics Engineers (IEEE) working group 7.4 of the Human Factors and Control Facilities Subcommittee of the Nuclear Power Engineering Committee (NPEC) has released its fifth draft of a Guide for General Principles of Human Action Reliability Analysis for Nuclear Power Generating Stations, for approval of NPEC. A guide is the least mandating in the IEEE hierarchy of standards. The purpose is to enhance the performance of an human reliability analysis (HRA) as a part of a probabilistic risk assessment (PRA), to assure reproducible results, and to standardize documentation. The guide does not recommend or even discuss specific techniques, which are too rapidly evolving today. Considerable maturation in the analysis of human reliability in a PRA context has taken place in recent years. The IEEE guide on this subject is an initial step toward bringing HRA out of the research and development arena into the toolbox of standard engineering practices

  7. Synthesis of on-chip control circuits for mVLSI biochips

    Potluri, Seetal; Schneider, Alexander Rüdiger; Hørslev-Petersen, Martin

    2017-01-01

    them to laboratory environments. To address this issue, researchers have proposed methods to reduce the number of offchip pressure sources, through integration of on-chip pneumatic control logic circuits fabricated using three-layer monolithic membrane valve technology. Traditionally, mVLSI biochip......-chip control circuit design and (iii) the integration of on-chip control in the placement and routing design tasks. In this paper we present a design methodology for logic synthesis and physical synthesis of mVLSI biochips that use on-chip control. We show how the proposed methodology can be successfully...... applied to generate biochip layouts with integrated on-chip pneumatic control....

  8. IEEE prize awarded to CERN PhD student

    2006-01-01

    Rafael Ballabriga Suñe is the recipient of the 2006 Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nuclear and Plasma Sciences Society (NPSS)'s Student Paper Award. Ballabriga's winning paper reported on a prototype chip, which belongs to a new generation of single photon counting hybrid pixel detector readout chips - Medipix3. The award was presented by the deputy programme chair Vince Cianciolo (left) at the IEEE Nuclear Science Symposium held in San Diego on 29 October to 4 November.

  9. Development of an integrated circuit VLSI used for time measurement and selective read out in the front end electronics of the DIRC for the Babar experience at SLAC; Developpement d'un circuit integre VLSI assurant mesure de temps et lecture selective dans l'electronique frontale du compteur DIRC de l'experience babar a slac

    Zhang, B

    1999-07-01

    This thesis deals with the design the development and the tests of an integrated circuit VLSI, supplying selective read and time measure for 16 channels. This circuit has been developed for a experiment of particles physics, BABAR, that will take place at SLAC (Stanford Linear Accelerator Center). A first part describes the physical stakes of the experiment, the electronic architecture and the place of the developed circuit in the research program. The second part presents the technical drawings of the circuit, the prototypes leading to the final design and the validity tests. (A.L.B.)

  10. IEEE 1588 Time Synchronization Board in MTCA.4 Form Factor

    Jabłoński, G.; Makowski, D.; Mielczarek, A.; Orlikowski, M.; Perek, P.; Napieralski, A.; Makijarvi, P.; Simrock, S.

    2015-06-01

    Distributed data acquisition and control systems in large-scale scientific experiments, like e.g. ITER, require time synchronization with nanosecond precision. A protocol commonly used for that purpose is the Precise Timing Protocol (PTP), also known as IEEE 1588 standard. It uses the standard Ethernet signalling and protocols and allows obtaining timing accuracy of the order of tens of nanoseconds. The MTCA.4 is gradually becoming the platform of choice for building such systems. Currently there is no commercially available implementation of the PTP receiver on that platform. In this paper, we present a module in the MTCA.4 form factor supporting this standard. The module may be used as a timing receiver providing reference clocks in an MTCA.4 chassis, generating a Pulse Per Second (PPS) signal and allowing generation of triggers and timestamping of events on 8 configurable backplane lines and two front panel connectors. The module is based on the Xilinx Spartan 6 FPGA and thermally stabilized Voltage Controlled Oscillator controlled by the digital-to-analog converter. The board supports standalone operation, without the support from the host operating system, as the entire control algorithm is run on a Microblaze CPU implemented in the FPGA. The software support for the card includes the low-level API in the form of Linux driver, user-mode library, high-level API: ITER Nominal Device Support and EPICS IOC. The device has been tested in the ITER timing distribution network (TCN) with three cascaded PTP-enabled Hirschmann switches and a GPS reference clock source. An RMS synchronization accuracy, measured by direct comparison of the PPS signals, better than 20 ns has been obtained.

  11. Editorial for the IEEE Transactions on Power Electronics, January 2009

    Blaabjerg, Frede

    2009-01-01

    I am entering the fourth year as the Editor in Chief of the IEEE TRANSACTIONS ON POWER ELECTRONICS. A position like this becomes more and more important for the technical field as publishing in a peer-reviewed highly ranked journal has influence on the industrial and academic career. It is a way...

  12. ARC Researchers at IEEE 2015 Vehicle Power and Propulsion Conference

    Contacts Researchers News & Events Event Calendar Annual Program Review Research Seminars Press Room Event Archives ARC Researchers at the IEEE 2015 Vehicle Power and Propulsion Conference (October 19-22 Ballroom B P-SS4-2 Comparison of SOFC and PEM Fuel Cell Hybrid Power Management Strategies for Mobile

  13. Eleanor McElwee and the Formation of IEEE PCS

    Malone, Edward A.

    2015-01-01

    This article examines the historical professional project that created the Institute of Radio Engineers' Professional Group on Engineering Writing an Speech (IRE PGEWS)--now called the Institute of Electrical and Electronics Engineers' Professional Communication Society (IEEE PCS)--and recounts the group's early history in detail. It also traces…

  14. 2011 IEEE Vehicular Networking Conference (VNC): Demo Summaries

    Altintas, O.; Chen, W.; Heijenk, Geert; Dressler, F.; Ekici, E.; Kargl, Frank; Shigeno, H.; Dietzel, Stefan

    2011-01-01

    Foreword For the first time in its history, IEEE VNC has included this year’s demonstrations in its program. Demonstrations play an important role to expose the research community to practical aspects of research and to foster cross-fertilization among researchers both in academia and in industry.

  15. 0011-0030.Data Representation amp Computer Arithmetic6 IEEE ...

    Home; public; Volumes; reso; 021; 01; 0011-0030.Data Representation amp Computer Arithmetic6 IEEE Standard Double Precision FormatIn.pdf. 404! error. The page your are looking for can not be found! Please check the link or use the navigation bar at the top. YouTube; Twitter; Facebook; Blog. Academy News.

  16. Power gating of VLSI circuits using MEMS switches in low power applications

    Shobak, Hosam; Ghoneim, Mohamed T.; El Boghdady, Nawal; Halawa, Sarah; Iskander, Sophinese M.; Anis, Mohab H.

    2011-01-01

    -designed MEMS switch to power gate VLSI circuits, such that leakage power is efficiently reduced while accounting for performance and reliability. The designed MEMS switch is characterized by an 0.1876 ? ON resistance and requires 4.5 V to switch. As a result

  17. Implementation of a VLSI Level Zero Processing system utilizing the functional component approach

    Shi, Jianfei; Horner, Ward P.; Grebowsky, Gerald J.; Chesney, James R.

    1991-01-01

    A high rate Level Zero Processing system is currently being prototyped at NASA/Goddard Space Flight Center (GSFC). Based on state-of-the-art VLSI technology and the functional component approach, the new system promises capabilities of handling multiple Virtual Channels and Applications with a combined data rate of up to 20 Megabits per second (Mbps) at low cost.

  18. An area-efficient path memory structure for VLSI Implementation of high speed Viterbi decoders

    Paaske, Erik; Pedersen, Steen; Sparsø, Jens

    1991-01-01

    Path storage and selection methods for Viterbi decoders are investigated with special emphasis on VLSI implementations. Two well-known algorithms, the register exchange, algorithm, REA, and the trace back algorithm, TBA, are considered. The REA requires the smallest number of storage elements...

  19. VLSI top-down design based on the separation of hierarchies

    Spaanenburg, L.; Broekema, A.; Leenstra, J.; Huys, C.

    1986-01-01

    Despite the presence of structure, interactions between the three views on VLSI design still lead to lengthy iterations. By separating the hierarchies for the respective views, the interactions are reduced. This separated hierarchy allows top-down design with functional abstractions as exemplified

  20. CMOS VLSI Active-Pixel Sensor for Tracking

    Pain, Bedabrata; Sun, Chao; Yang, Guang; Heynssens, Julie

    2004-01-01

    An architecture for a proposed active-pixel sensor (APS) and a design to implement the architecture in a complementary metal oxide semiconductor (CMOS) very-large-scale integrated (VLSI) circuit provide for some advanced features that are expected to be especially desirable for tracking pointlike features of stars. The architecture would also make this APS suitable for robotic- vision and general pointing and tracking applications. CMOS imagers in general are well suited for pointing and tracking because they can be configured for random access to selected pixels and to provide readout from windows of interest within their fields of view. However, until now, the architectures of CMOS imagers have not supported multiwindow operation or low-noise data collection. Moreover, smearing and motion artifacts in collected images have made prior CMOS imagers unsuitable for tracking applications. The proposed CMOS imager (see figure) would include an array of 1,024 by 1,024 pixels containing high-performance photodiode-based APS circuitry. The pixel pitch would be 9 m. The operations of the pixel circuits would be sequenced and otherwise controlled by an on-chip timing and control block, which would enable the collection of image data, during a single frame period, from either the full frame (that is, all 1,024 1,024 pixels) or from within as many as 8 different arbitrarily placed windows as large as 8 by 8 pixels each. A typical prior CMOS APS operates in a row-at-a-time ( grolling-shutter h) readout mode, which gives rise to exposure skew. In contrast, the proposed APS would operate in a sample-first/readlater mode, suppressing rolling-shutter effects. In this mode, the analog readout signals from the pixels corresponding to the windows of the interest (which windows, in the star-tracking application, would presumably contain guide stars) would be sampled rapidly by routing them through a programmable diagonal switch array to an on-chip parallel analog memory array. The

  1. Driving a car with custom-designed fuzzy inferencing VLSI chips and boards

    Pin, Francois G.; Watanabe, Yutaka

    1993-01-01

    Vehicle control in a-priori unknown, unpredictable, and dynamic environments requires many calculational and reasoning schemes to operate on the basis of very imprecise, incomplete, or unreliable data. For such systems, in which all the uncertainties can not be engineered away, approximate reasoning may provide an alternative to the complexity and computational requirements of conventional uncertainty analysis and propagation techniques. Two types of computer boards including custom-designed VLSI chips were developed to add a fuzzy inferencing capability to real-time control systems. All inferencing rules on a chip are processed in parallel, allowing execution of the entire rule base in about 30 microseconds, and therefore, making control of 'reflex-type' of motions envisionable. The use of these boards and the approach using superposition of elemental sensor-based behaviors for the development of qualitative reasoning schemes emulating human-like navigation in a-priori unknown environments are first discussed. Then how the human-like navigation scheme implemented on one of the qualitative inferencing boards was installed on a test-bed platform to investigate two control modes for driving a car in a-priori unknown environments on the basis of sparse and imprecise sensor data is described. In the first mode, the car navigates fully autonomously, while in the second mode, the system acts as a driver's aid providing the driver with linguistic (fuzzy) commands to turn left or right and speed up or slow down depending on the obstacles perceived by the sensors. Experiments with both modes of control are described in which the system uses only three acoustic range (sonar) sensor channels to perceive the environment. Simulation results as well as indoors and outdoors experiments are presented and discussed to illustrate the feasibility and robustness of autonomous navigation and/or safety enhancing driver's aid using the new fuzzy inferencing hardware system and some human

  2. Introduction to IEEE Std. 7-4.3.2 Annex D -- ''Qualification of existing commercial computers''

    Holmstrom, K.J.

    1995-01-01

    On September 15th of 1993 the IEEE standards board approved IEEE Std. 7-4.3.2-1993, IEEE Standard for Digital Computers in Safety Systems of Nuclear Power Generating Stations. This paper is an introduction to Annex D of this document which concerns the commercial grade dedication of existing computers or new non-1E computers

  3. IEEE C37.82-1987: IEEE standard for the qualification of switchgear assemblies for Class 1E applications in nuclear power generating stations

    Anon.

    1992-01-01

    This document describes the methods and requirements for qualifying switchgear assemblies for indoor areas outside of the containment in nuclear power generating stations. These assemblies include (1) metal-enclosed low-voltage power circuit breaker switchgear assemblies, as defined in ANSI/IEEE C37.20.1-1987, (2) metal-clad switchgear assemblies, as defined in ANSI/IEEE C37.20.2-1987, (3) metal-enclosed bus, as defined in ANSI/IEEE C37.23-1987, and (4) metal-enclosed interrupter switchgear assemblies, as defined in ANSI/IEEE C37.20.3-1987. The purpose of this document is to provide amplification of the general requirements of ANSI/IEEE Std 323-1983 as they apply to the specific features of Class 1E switchgear assemblies. Where differences exist between this document and ANSI/IEEE Std 323-1983, this document takes precedence insofar as switchgear assemblies are concerned

  4. Proceedings of IEEE Machine Learning for Signal Processing Workshop XVI

    Larsen, Jan

    These proceedings contains refereed papers presented at the sixteenth IEEE Workshop on Machine Learning for Signal Processing (MLSP'2006), held in Maynooth, Co. Kildare, Ireland, September 6-8, 2006. This is a continuation of the IEEE Workshops on Neural Networks for Signal Processing (NNSP......). The name of the Technical Committee, hence of the Workshop, was changed to Machine Learning for Signal Processing in September 2003 to better reflect the areas represented by the Technical Committee. The conference is organized by the Machine Learning for Signal Processing Technical Committee...... the same standard as the printed version and facilitates the reading and searching of the papers. The field of machine learning has matured considerably in both methodology and real-world application domains and has become particularly important for solution of problems in signal processing. As reflected...

  5. IEEE prize awarded to CERN PhD student

    2006-01-01

    Rafael Ballabriga Suñe (right) receives the Student Paper Award. Rafael Ballabriga Suñe is the recipient of the 2006 Institute of Electrical and Electronics Engineers, Inc. (IEEE) Nuclear and Plasma Sciences Society (NPSS)'s Student Paper Award. Ballabriga's winning paper reported on a prototype chip, which belongs to a new generation of single photon counting hybrid pixel detector readout chips - Medipix3. The NPSS established this award in 2005 to encourage outstanding student contributions and greater student participation as principle or sole authors of papers. The prizes were presented at the IEEE Nuclear Science Symposium held in San Diego on 29 October to 4 November. The prototype chip was designed by Ballabriga based on ideas generated within the CERN Medipix team - part of the PH Microelectronics group. It could be used in various fields in the future, including medical imaging, neutron imaging, electron microscopy, radiation monitoring and other applications in high-energy physics. The novel aspe...

  6. IEEE 802.3 Fiber Optic Inter-Repeater Link

    Tarrant, Peter J.

    1987-01-01

    This paper describes the implementation of a fiber optic inter-repeater link (FOIRL), used for connecting two remote copper segments of an IEEE 802.3 local area network. The rationale for the design, the signalling used and the collision detection mechanism is discussed. The evolution of the draft international standard for the FOIRL and the concurrence amongst various manufacturers is also presented. Finally some examples of typical applications, highlighting the ease of installation, are given.

  7. Basic security measures for IEEE 802.11 wireless networks

    Sarmiento, Oscar P.; Guerrero, Fabio G.; Rey Argote, David

    2008-01-01

    This article presents a tutorial/discussion of three commonly-used IEEE 802.11 wireless network security standards: WEP, WPA and WPA2. A detailed analysis of the RC4 algorithm supporting WEP is presented, including its vulnerabilities. The WPA and WPA2 encryption protocols’ most relevant aspects and technical characteristics are reviewed for a comparative analysis of the three standards in terms of the security they provide. Special attention has been paid to WEP encryption by using an educat...

  8. 17th IEEE NPSS Real Time Conference – RT-2010

    Carlos Varandas

    2010-01-01

    Congress Centre of “Instituto Superior Técnico”, Lisboa, Portugal, 24-28 May, 2010 ABSTRACT SUBMISSION OPEN Abstract Submission Deadline: March 1st, 2010 Dear Sir/Madam, We are pleased to announce that abstract submission for the 17th IEEE NPSS Real Time Conference is now open on our web site. The deadline for submitting an abstract is 1st March 2010. Full conference details General Chairman

  9. Recovery Act - CAREER: Sustainable Silicon -- Energy-Efficient VLSI Interconnect for Extreme-Scale Computing

    Chiang, Patrick [Oregon State Univ., Corvallis, OR (United States)

    2014-01-31

    The research goal of this CAREER proposal is to develop energy-efficient, VLSI interconnect circuits and systems that will facilitate future massively-parallel, high-performance computing. Extreme-scale computing will exhibit massive parallelism on multiple vertical levels, from thou­ sands of computational units on a single processor to thousands of processors in a single data center. Unfortunately, the energy required to communicate between these units at every level (on­ chip, off-chip, off-rack) will be the critical limitation to energy efficiency. Therefore, the PI's career goal is to become a leading researcher in the design of energy-efficient VLSI interconnect for future computing systems.

  10. Towards an Analogue Neuromorphic VLSI Instrument for the Sensing of Complex Odours

    Ab Aziz, Muhammad Fazli; Harun, Fauzan Khairi Che; Covington, James A.; Gardner, Julian W.

    2011-09-01

    Almost all electronic nose instruments reported today employ pattern recognition algorithms written in software and run on digital processors, e.g. micro-processors, microcontrollers or FPGAs. Conversely, in this paper we describe the analogue VLSI implementation of an electronic nose through the design of a neuromorphic olfactory chip. The modelling, design and fabrication of the chip have already been reported. Here a smart interface has been designed and characterised for thisneuromorphic chip. Thus we can demonstrate the functionality of the a VLSI neuromorphic chip, producing differing principal neuron firing patterns to real sensor response data. Further work is directed towards integrating 9 separate neuromorphic chips to create a large neuronal network to solve more complex olfactory problems.

  11. An analog VLSI real time optical character recognition system based on a neural architecture

    Bo, G.; Caviglia, D.; Valle, M.

    1999-01-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system

  12. An analog VLSI real time optical character recognition system based on a neural architecture

    Bo, G.; Caviglia, D.; Valle, M. [Genoa Univ. (Italy). Dip. of Biophysical and Electronic Engineering

    1999-03-01

    In this paper a real time Optical Character Recognition system is presented: it is based on a feature extraction module and a neural network classifier which have been designed and fabricated in analog VLSI technology. Experimental results validate the circuit functionality. The results obtained from a validation based on a mixed approach (i.e., an approach based on both experimental and simulation results) confirm the soundness and reliability of the system.

  13. International Conference on VLSI, Communication, Advanced Devices, Signals & Systems and Networking

    Shirur, Yasha; Prasad, Rekha

    2013-01-01

    This book is a collection of papers presented by renowned researchers, keynote speakers and academicians in the International Conference on VLSI, Communication, Analog Designs, Signals and Systems, and Networking (VCASAN-2013), organized by B.N.M. Institute of Technology, Bangalore, India during July 17-19, 2013. The book provides global trends in cutting-edge technologies in electronics and communication engineering. The content of the book is useful to engineers, researchers and academicians as well as industry professionals.

  14. Proceedings IEEE Visualization Conference and IEEE Information Visualization Conference (VIS'07 and INFOVIS'07, Sacramento CA, USA, October 28-November 1, 2007)

    Chen, M.; Hansen, C.; North, C.; Pang, A.; Wijk, van J.J.

    2007-01-01

    These are the proceedings of the IEEE Visualization Conference 2007 (Vis 2007) and the IEEE Information Visualization Conference 2007 (InfoVis 2007) held during October 28 to November 1, 2007 in Sacramento, California. The power of using computing technology to create useful, effective imagery for

  15. Coexistence of IEEE 802.11b/g WLANs and IEEE 802.15.4 WSNs : Modeling and Protocol Enhancements

    Yuan, W.

    2011-01-01

    As an emerging short-range wireless technology, IEEE 802.15.4/ZigBee Wireless Sensor Networks (WSNs) are increasingly used in the fields of home control, industrial control, consumer electronics, energy management, building automation, telecom services, personal healthcare, etc. IEEE

  16. VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm

    Rachmad Vidya Wicaksana Putra

    2016-06-01

    Full Text Available Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

  17. Test methods of total dose effects in very large scale integrated circuits

    He Chaohui; Geng Bin; He Baoping; Yao Yujuan; Li Yonghong; Peng Honglun; Lin Dongsheng; Zhou Hui; Chen Yusheng

    2004-01-01

    A kind of test method of total dose effects (TDE) is presented for very large scale integrated circuits (VLSI). The consumption current of devices is measured while function parameters of devices (or circuits) are measured. Then the relation between data errors and consumption current can be analyzed and mechanism of TDE in VLSI can be proposed. Experimental results of 60 Co γ TDEs are given for SRAMs, EEPROMs, FLASH ROMs and a kind of CPU

  18. 15th IEEE International Conference on Intelligent Engineering Systems

    Živčák, Jozef; Aspects of Computational Intelligence Theory and Applications

    2013-01-01

    This volume covers the state-of-the art of the research and development in various aspects of computational intelligence and gives some perspective directions of development. Except the traditional engineering areas that contain theoretical knowledge, applications, designs and projects, the book includes the area of use of computational intelligence in biomedical engineering. „Aspects of Computational Intelligence: Theory and Applications” is a compilation of carefully selected extended papers written on the basis of original contributions presented at the 15th IEEE International Conference on Intelligent Engineering Systems 2011, INES 2011 held at June 23.-26. 2011 in AquaCity Poprad, Slovakia.    

  19. Status of the IEEE P896 Future Backplane Bus

    Gustavson, D.B.

    1983-10-01

    The IEEE P896 Future Backplane Bus project has been influenced by and has influenced FASTBUS and several other contemporary bus designs. This paper summarizes the current status of that project, which is directed toward the needs of modern 32-bit microprocessor systems with multiple processors. Some of the technology developed for P896 will be important for future non-ECL implementations of FASTBUS and other buses. In particular, new bus drivers and receivers should greatly improve the performance and reliability of backplane buses and cable buses. The current status of the P896 serial bus is also summarized

  20. A strategy for implementation of experience based seismic equipment qualification in IEEE and ASME industry standards

    Adams, T.M.

    1996-01-01

    In the past 20 years, extensive data on the performance of mechanical and electric equipment during actual strong motion earthquakes and seismic qualification tests has been accumulated. Recognizing that an experience based approach provides a technically sound and cost effective method for the seismic qualification of some or certain equipment, the IEEE Nuclear Power Engineering Committee and the ASME Committee on Qualification of Mechanical Equipment established a Special Working Group to investigate the incorporation of experienced based methods into the industry consensus codes and standards currently used in the seismic qualification of Seismic Category Nuclear Power Plant equipment. This paper presents the strategy (course of action) which was developed by the Special Working Group for meeting this objective of incorporation of experience based seismic qualification standards used in the design and seismic qualification of seismic category nuclear power plant equipment. This strategy was recommended to both chartering organizations, the IEEE Nuclear Power Engineering Committee and the ASME Committee on Qualification of Mechanical Equipment for their consideration and implementation. The status of the review and implementation of the Special Working Group's recommended strategy by the sponsoring organization is also discussed

  1. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing

    2011-01-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm 2 area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  2. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 μm CMOS

    Bin, Wu; Yumei, Zhou; Yongxu, Zhu; Zhengdong, Zhang; Jingjing, Cai

    2011-05-01

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 μm 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 × 2.6 mm2 area and consumes 83 mW under typical work modes.

  3. Design and implementation of an IEEE 802.11 baseband OFDM transceiver in 0.18 {mu}m CMOS

    Wu Bin; Zhou Yumei; Zhu Yongxu; Zhang Zhengdong; Cai Jingjing, E-mail: wubin@ime.ac.cn [Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029 (China)

    2011-05-15

    An SISO IEEE 802.11 baseband OFDM transceiver ASIC is implemented. The chip can support all of the SISO IEEE 802.11 work modes by optimizing the key module and sharing the module between the transmitter and receiver. The area and power are decreased greatly compared with other designs. The baseband prototype has been verified under the WLAN baseband test equipment and through transferring the video. The 0.18 {mu}m 1P/6M CMOS technology layout is finished and the chip is fabricated in SMIC, which occupies a 2.6 x 2.6 mm{sup 2} area and consumes 83 mW under typical work modes. (semiconductor integrated circuits)

  4. Extending Service Area of IEEE 802.11 Ad Hoc Networks

    Choi, Woo-Yong

    2012-06-01

    According to the current IEEE 802.11 wireless LAN standards, IEEE 802.11 ad hoc networks have the limitation that all STAs (Stations) are in the one-hop transmission range of each other. In this paper, to alleviate the limitation of IEEE 802.11 ad hoc networks we propose the efficient method for selecting the most appropriate pseudo AP (Access Point) from among the set of ad hoc STAs and extending the service area of IEEE 802.11 ad hoc networks by the pseudo AP's relaying the internal traffic of IEEE 802.11 ad hoc networks. Numerical examples show that the proposed method significantly extends the service area of IEEE 802.11 ad hoc networks.

  5. IEEE Std 649-1991: IEEE standard for qualifying Class 1E motor control centers for nuclear power generating stations

    Anon.

    1993-01-01

    The basic principles, requirements, and methods for qualifying Class 1E motor control centers for both harsh and mild environment applications in nuclear power generating stations are described. In addition to defining specific qualification requirements for Class 1E motor control centers and their components in accordance with the more general qualification requirements of IEEE Std 323-1983, this standard is intended to provide guidance in establishing a qualification program for demonstrating the adequacy of Class 1E motor control centers in nuclear power generating station applications

  6. Fault-Tolerant Topology and Routing Synthesis for IEEE Time-Sensitive Networking

    Gavrilut, Voica Maria; Zarrin, Bahram; Pop, Paul

    2017-01-01

    of the applications are satisffied. We propose three approaches to solve this optimization problem: (1) a heuristic solution, (2) a Greedy Randomized Adaptive Search Procedure (GRASP) metaheuristic, and (3) a Constraint Programmingbased model. The approaches are evaluated on several test cases, including a test case......Time-Sensitive Networking (TSN) is a set of IEEE standards that extend Ethernet for safety-critical and real-time applications. TSN is envisioned to be widely used in several applications areas, from industrial automation to in-vehicle networking. A TSN network is composed of end systems...... interconnected by physical links and bridges (switches). The data in TSN is exchanged via streams. We address safety-critical real-time systems, and we consider that the streams use the Urgency-Based Scheduler (UBS) traffic-type, suitable for hard real-time traffic. We are interested in determining a fault...

  7. Proceedings of the IEEE Machine Learning for Signal Processing XVII

    The seventeenth of a series of workshops sponsored by the IEEE Signal Processing Society and organized by the Machine Learning for Signal Processing Technical Committee (MLSP-TC). The field of machine learning has matured considerably in both methodology and real-world application domains and has...... become particularly important for solution of problems in signal processing. As reflected in this collection, machine learning for signal processing combines many ideas from adaptive signal/image processing, learning theory and models, and statistics in order to solve complex real-world signal processing......, and two papers from the winners of the Data Analysis Competition. The program included papers in the following areas: genomic signal processing, pattern recognition and classification, image and video processing, blind signal processing, models, learning algorithms, and applications of machine learning...

  8. Editorial for IEEE Transactions on Power Electronics, January 2013

    Blaabjerg, Frede; Lehman, Brad

    2013-01-01

    should increase the impact factor of the IEEE TRANSACTIONS ON POWER ELECTRONICS (TPEL). In 2007, TPEL published 2600 pages, and it has gradually been increased to 4000 pages in 2011, 5000 pages in 2012, and 5500 pages are projected for 2013. We have decided to publish 12 printed issues so every month...... a new issue will be printed. A graph is provided showing the number of regular papers received in the past years as well as the number of published pages in the TPEL. Finally they note that in 2008, TPEL obtained a record high value for the impact factor (as shown in a figure) but in 2009 it was reduced...... the papers to be read over a longer time span; 2) Web of Science (ISI Thomsen Reuter) began to register new power electronics conferences in their database, and citations from conferences counts and contributes to a higher impact factor....

  9. Report of the 2017 IEEE Cyber Science and Technology Congress

    Wenbing Zhao

    2017-12-01

    Full Text Available The modern digitized world has led to the emergence of a new paradigm on global information networks and infrastructures known as Cyberspace and the studies of Cybernetics, which bring seamless integration of physical, social and mental spaces. Cyberspace is becoming an integral part of our daily life from learning and entertainment to business and cultural activities. As expected, this whole concept of Cybernetics brings new challenges that need to be tackled. The 2017 IEEE Cyber Science and Technology Congress (CyberSciTech 2017 provided a forum for researchers to report their research findings and exchange ideas. The congress took place in Orlando, Florida, USA during 6–10 November 2017. Not counting poster papers, the congress accepted over fifty papers that are divided into nine sessions. In this report, we provide an overview of the research contributions of the papers in CyberSciTech 2017.

  10. WIH-based IEEE 802.11 ECG monitoring implementation.

    Moein, A; Pouladian, M

    2007-01-01

    New wireless technologies make possible the implementation of high level integration wireless devices which allow the replacement of traditional large wired monitoring devices. It offers new functionalities to physicians and will reduce the costs. Among these functionalities, biomedical signals can be sent to other devices (PDA, PC . . . ) or processing centers, without restricting the patients' mobility. This article discusses the WIH (Ward-In-Hand) structure and the software required for its implementation before an operational example is presented with its results. The aim of this project is the development and implementation of a reduced size electrocardiograph based on IEEE 802.11 with high speed and more accuracy, which allows wireless monitoring of patients, and the insertion of the information into the Wi-Fi hospital networks.

  11. Basic security measures for IEEE 802.11 wireless networks

    Oscar P. Sarmiento

    2008-05-01

    Full Text Available This article presents a tutorial/discussion of three commonly-used IEEE 802.11 wireless network security standards: WEP, WPA and WPA2. A detailed analysis of the RC4 algorithm supporting WEP is presented, including its vulnera-bilities. The WPA and WPA2 encryption protocols’ most relevant aspects and technical characteristics are reviewed for a comparative analysis of the three standards in terms of the security they provide. Special attention has been paid to WEP encryption by using an educational simulation tool written in C++ Builder for facilitating the unders-tanding of this protocol at academic level. Two practical cases of wireless security configurations using Cisco net-working equipment are also presented: configuring and enabling WPA-Personal and WPA2-Personal (these being security options used by TKIP and AES, respectively.

  12. Fir Filters Compliant with the IEEE Standard for M Class PMU

    Duda Krzysztof

    2016-12-01

    Full Text Available In this paper it is shown that M class PMU (Phasor Measurement Unit reference model for phasor estimation recommended by the IEEE Standard C37.118.1 with the Amendment 1 is not compliant with the Standard. The reference filter preserves only the limits for TVE (total vector error, and exceeds FE (frequency error and RFE (rate of frequency error limits. As a remedy we propose new filters for phasor estimation for M class PMU that are fully compliant with the Standard requirements. The proposed filters are designed: 1 by the window method; 2 as flat-top windows; or as 3 optimal min-max filters. The results for all Standard compliance tests are presented, confirming good performance of the proposed filters. The proposed filters are fixed at the nominal frequency, i.e. frequency tracking and adaptive filter tuning are not required, therefore they are well suited for application in lowcost popular PMUs.

  13. Mobile Device Passive Localization Based on IEEE 802.11 Probe Request Frames

    Lin Sun

    2017-01-01

    Full Text Available This paper presents a novel passive mobile device localization mode based on IEEE 802.11 Probe Request frames. In this approach, the listener can discover mobile devices by receiving the Probe Request frames and localize them on his walking path. The unique location of the mobile device is estimated on a geometric diagram and right-angled walking path. In model equations, site-related parameter, that is, path loss exponent, is eliminated to make the approach site-independent. To implement unique localization, the right-angled walking path is designed and the optimal location is estimated from the optional points. The performance of our method has been evaluated inside the room, outside the room, and in outdoor scenarios. Three kinds of walking paths, for example, horizontal, vertical, and slanted, are also tested.

  14. VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders

    Georgios Passas

    2012-01-01

    Full Text Available The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. In this paper, a complete architectural model of a space-time turbo code receiver that includes elementary decoders is presented. These architectures are based on newly proposed building blocks such as a recursive add-compare-select-offset (ACSO unit, A-, B-, Γ-, and LLR output calculation modules. Measurements of complexity and decoding delay of several sliding-window-technique-based MAP decoder architectures and a proposed parameter set lead to defining equations and comparison between those architectures.

  15. Vlsi implementation of flexible architecture for decision tree classification in data mining

    Sharma, K. Venkatesh; Shewandagn, Behailu; Bhukya, Shankar Nayak

    2017-07-01

    The Data mining algorithms have become vital to researchers in science, engineering, medicine, business, search and security domains. In recent years, there has been a terrific raise in the size of the data being collected and analyzed. Classification is the main difficulty faced in data mining. In a number of the solutions developed for this problem, most accepted one is Decision Tree Classification (DTC) that gives high precision while handling very large amount of data. This paper presents VLSI implementation of flexible architecture for Decision Tree classification in data mining using c4.5 algorithm.

  16. Positron emission tomographic images and expectation maximization: A VLSI architecture for multiple iterations per second

    Jones, W.F.; Byars, L.G.; Casey, M.E.

    1988-01-01

    A digital electronic architecture for parallel processing of the expectation maximization (EM) algorithm for Positron Emission tomography (PET) image reconstruction is proposed. Rapid (0.2 second) EM iterations on high resolution (256 x 256) images are supported. Arrays of two very large scale integration (VLSI) chips perform forward and back projection calculations. A description of the architecture is given, including data flow and partitioning relevant to EM and parallel processing. EM images shown are produced with software simulating the proposed hardware reconstruction algorithm. Projected cost of the system is estimated to be small in comparison to the cost of current PET scanners

  17. Techniques for Computing the DFT Using the Residue Fermat Number Systems and VLSI

    Truong, T. K.; Chang, J. J.; Hsu, I. S.; Pei, D. Y.; Reed, I. S.

    1985-01-01

    The integer complex multiplier and adder over the direct sum of two copies of a finite field is specialized to the direct sum of the rings of integers modulo Fermat numbers. Such multiplications and additions can be used in the implementation of a discrete Fourier transform (DFT) of a sequence of complex numbers. The advantage of the present approach is that the number of multiplications needed for the DFT can be reduced substantially over the previous approach. The architectural designs using this approach are regular, simple, expandable and, therefore, naturally suitable for VLSI implementation.

  18. A formal analysis of ISO/IEEE P11073-20601 standard of medical device communication

    Goga, Nicolae; Costache, Stefania; Moldoveanu, Florica

    2009-01-01

    This article presents the formal work done for the ISO/IEEE P11073-20601 Draft Standard for Health informatics - Personal health device communication - Application profile Optimized exchange protocol. ISO/IEEE 11073 family defines standards for device communication between agents (e.g. blood

  19. Comparison Of Several Methods Of Implementing A Fiber Optic IEEE 802.3 Ethernet

    Thompson, Geoffrey O.

    1987-01-01

    Several different methods of implementing a fiber optic version of IEEE 802.3 10BASE LANs have been proposed as a candidate for standardization by IEEE. There have been extensive discussions as to the relative merits and features of the several systems. This paper will discuss the merits of each for this particular application on a comparative basis.

  20. 0011-0030.How to make an abstract in IEEE Format for ...

    Home; public; Volumes; reso; 021; 01; 0011-0030.How to make an abstract in IEEE Format for AvishkarMulticultural Night in IEEE R10 Student Congress 2009Performances.pdf. 404! error. The page your are looking for can not be found! Please check the link or use the navigation bar at the top. YouTube; Twitter; Facebook ...

  1. 0011-0030.What is IEEE 754 StandardHow to convert real number ...

    Home; public; Volumes; reso; 021; 01; 0011-0030.What is IEEE 754 StandardHow to convert real number in binary format using IEEE 754 StandardAn.pdf. 404! error. The page your are looking for can not be found! Please check the link or use the navigation bar at the top. YouTube; Twitter; Facebook; Blog. Academy News.

  2. IEEE Std 649-1980: IEEE standard for qualifying Class 1E motor control centers for nuclear power generating stations

    Anon.

    1992-01-01

    This standard describes the basic principles, requirements, and methods for qualifying Class 1E motor control centers for outside containment applications in nuclear power generating stations. Qualification of motor control centers located inside containment in a nuclear power generating station is beyond the scope of this standard. The purpose of this standard is (1) to define specific qualification requirements for Class 1E motor control centers in accordance with the more general qualification requirements of IEEE Std 323-1974, IEE Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations; (2) to provide guidance in establishing a qualification program for demonstrating the design adequacy of Class 1E motor control centers in nuclear power generating station applications

  3. Performance Analysis of IEEE 802.11 DCF and IEEE 802.11e EDCA in Non-saturation Condition

    Kim, Tae Ok; Kim, Kyung Jae; Choi, Bong Dae

    We analyze the MAC performance of the IEEE 802.11 DCF and 802.11e EDCA in non-saturation condition where device does not have packets to transmit sometimes. We assume that a flow is not generated while the previous flow is in service and the number of packets in a flow is geometrically distributed. In this paper, we take into account the feature of non-saturation condition in standards: possibility of transmission performed without preceding backoff procedure for the first packet arriving at the idle station. Our approach is to model a stochastic behavior of one station as a discrete time Markov chain. We obtain four performance measures: normalized channel throughput, average packet HoL (head of line) delay, expected time to complete transmission of a flow and packet loss probability. Our results can be used for admission control to find the optimal number of stations with some constraints on these measures.

  4. A novel low-voltage low-power analogue VLSI implementation of neural networks with on-chip back-propagation learning

    Carrasco, Manuel; Garde, Andres; Murillo, Pilar; Serrano, Luis

    2005-06-01

    In this paper a novel design and implementation of a VLSI Analogue Neural Net based on Multi-Layer Perceptron (MLP) with on-chip Back Propagation (BP) learning algorithm suitable for the resolution of classification problems is described. In order to implement a general and programmable analogue architecture, the design has been carried out in a hierarchical way. In this way the net has been divided in synapsis-blocks and neuron-blocks providing an easy method for the analysis. These blocks basically consist on simple cells, which are mainly, the activation functions (NAF), derivatives (DNAF), multipliers and weight update circuits. The analogue design is based on current-mode translinear techniques using MOS transistors working in the weak inversion region in order to reduce both the voltage supply and the power consumption. Moreover, with the purpose of minimizing the noise, offset and distortion of even order, the topologies are fully-differential and balanced. The circuit, named ANNE (Analogue Neural NEt), has been prototyped and characterized as a proof of concept on CMOS AMI-0.5A technology occupying a total area of 2.7mm2. The chip includes two versions of neural nets with on-chip BP learning algorithm, which are respectively a 2-1 and a 2-2-1 implementations. The proposed nets have been experimentally tested using supply voltages from 2.5V to 1.8V, which is suitable for single cell lithium-ion battery supply applications. Experimental results of both implementations included in ANNE exhibit a good performance on solving classification problems. These results have been compared with other proposed Analogue VLSI implementations of Neural Nets published in the literature demonstrating that our proposal is very efficient in terms of occupied area and power consumption.

  5. Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform

    Sanjay Singh

    2017-06-01

    Full Text Available Motion detection is the heart of a potentially complex automated video surveillance system, intended to be used as a standalone system. Therefore, in addition to being accurate and robust, a successful motion detection technique must also be economical in the use of computational resources on selected FPGA development platform. This is because many other complex algorithms of an automated video surveillance system also run on the same platform. Keeping this key requirement as main focus, a memory efficient VLSI architecture for real-time motion detection and its implementation on FPGA platform is presented in this paper. This is accomplished by proposing a new memory efficient motion detection scheme and designing its VLSI architecture. The complete real-time motion detection system using the proposed memory efficient architecture along with proper input/output interfaces is implemented on Xilinx ML510 (Virtex-5 FX130T FPGA development platform and is capable of operating at 154.55 MHz clock frequency. Memory requirement of the proposed architecture is reduced by 41% compared to the standard clustering based motion detection architecture. The new memory efficient system robustly and automatically detects motion in real-world scenarios (both for the static backgrounds and the pseudo-stationary backgrounds in real-time for standard PAL (720 × 576 size color video.

  6. A multichip aVLSI system emulating orientation selectivity of primary visual cortical cells.

    Shimonomura, Kazuhiro; Yagi, Tetsuya

    2005-07-01

    In this paper, we designed and fabricated a multichip neuromorphic analog very large scale integrated (aVLSI) system, which emulates the orientation selective response of the simple cell in the primary visual cortex. The system consists of a silicon retina and an orientation chip. An image, which is filtered by a concentric center-surround (CS) antagonistic receptive field of the silicon retina, is transferred to the orientation chip. The image transfer from the silicon retina to the orientation chip is carried out with analog signals. The orientation chip selectively aggregates multiple pixels of the silicon retina, mimicking the feedforward model proposed by Hubel and Wiesel. The chip provides the orientation-selective (OS) outputs which are tuned to 0 degrees, 60 degrees, and 120 degrees. The feed-forward aggregation reduces the fixed pattern noise that is due to the mismatch of the transistors in the orientation chip. The spatial properties of the orientation selective response were examined in terms of the adjustable parameters of the chip, i.e., the number of aggregated pixels and size of the receptive field of the silicon retina. The multichip aVLSI architecture used in the present study can be applied to implement higher order cells such as the complex cell of the primary visual cortex.

  7. A Compact VLSI System for Bio-Inspired Visual Motion Estimation.

    Shi, Cong; Luo, Gang

    2018-04-01

    This paper proposes a bio-inspired visual motion estimation algorithm based on motion energy, along with its compact very-large-scale integration (VLSI) architecture using low-cost embedded systems. The algorithm mimics motion perception functions of retina, V1, and MT neurons in a primate visual system. It involves operations of ternary edge extraction, spatiotemporal filtering, motion energy extraction, and velocity integration. Moreover, we propose the concept of confidence map to indicate the reliability of estimation results on each probing location. Our algorithm involves only additions and multiplications during runtime, which is suitable for low-cost hardware implementation. The proposed VLSI architecture employs multiple (frame, pixel, and operation) levels of pipeline and massively parallel processing arrays to boost the system performance. The array unit circuits are optimized to minimize hardware resource consumption. We have prototyped the proposed architecture on a low-cost field-programmable gate array platform (Zynq 7020) running at 53-MHz clock frequency. It achieved 30-frame/s real-time performance for velocity estimation on 160 × 120 probing locations. A comprehensive evaluation experiment showed that the estimated velocity by our prototype has relatively small errors (average endpoint error < 0.5 pixel and angular error < 10°) for most motion cases.

  8. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Jian Haifang; Shi Yin

    2009-01-01

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  9. VLSI architecture of a K-best detector for MIMO-OFDM wireless communication systems

    Jian Haifang; Shi Yin, E-mail: jhf@semi.ac.c [Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083 (China)

    2009-07-15

    The K-best detector is considered as a promising technique in the MIMO-OFDM detection because of its good performance and low complexity. In this paper, a new K-best VLSI architecture is presented. In the proposed architecture, the metric computation units (MCUs) expand each surviving path only to its partial branches, based on the novel expansion scheme, which can predetermine the branches' ascending order by their local distances. Then a distributed sorter sorts out the new K surviving paths from the expanded branches in pipelines. Compared to the conventional K-best scheme, the proposed architecture can approximately reduce fundamental operations by 50% and 75% for the 16-QAM and the 64-QAM cases, respectively, and, consequently, lower the demand on the hardware resource significantly. Simulation results prove that the proposed architecture can achieve a performance very similar to conventional K-best detectors. Hence, it is an efficient solution to the K-best detector's VLSI implementation for high-throughput MIMO-OFDM systems.

  10. A multi coding technique to reduce transition activity in VLSI circuits

    Vithyalakshmi, N.; Rajaram, M.

    2014-01-01

    Advances in VLSI technology have enabled the implementation of complex digital circuits in a single chip, reducing system size and power consumption. In deep submicron low power CMOS VLSI design, the main cause of energy dissipation is charging and discharging of internal node capacitances due to transition activity. Transition activity is one of the major factors that also affect the dynamic power dissipation. This paper proposes power reduction analyzed through algorithm and logic circuit levels. In algorithm level the key aspect of reducing power dissipation is by minimizing transition activity and is achieved by introducing a data coding technique. So a novel multi coding technique is introduced to improve the efficiency of transition activity up to 52.3% on the bus lines, which will automatically reduce the dynamic power dissipation. In addition, 1 bit full adders are introduced in the Hamming distance estimator block, which reduces the device count. This coding method is implemented using Verilog HDL. The overall performance is analyzed by using Modelsim and Xilinx Tools. In total 38.2% power saving capability is achieved compared to other existing methods. (semiconductor technology)

  11. Parallel algorithms for placement and routing in VLSI design. Ph.D. Thesis

    Brouwer, Randall Jay

    1991-01-01

    The computational requirements for high quality synthesis, analysis, and verification of very large scale integration (VLSI) designs have rapidly increased with the fast growing complexity of these designs. Research in the past has focused on the development of heuristic algorithms, special purpose hardware accelerators, or parallel algorithms for the numerous design tasks to decrease the time required for solution. Two new parallel algorithms are proposed for two VLSI synthesis tasks, standard cell placement and global routing. The first algorithm, a parallel algorithm for global routing, uses hierarchical techniques to decompose the routing problem into independent routing subproblems that are solved in parallel. Results are then presented which compare the routing quality to the results of other published global routers and which evaluate the speedups attained. The second algorithm, a parallel algorithm for cell placement and global routing, hierarchically integrates a quadrisection placement algorithm, a bisection placement algorithm, and the previous global routing algorithm. Unique partitioning techniques are used to decompose the various stages of the algorithm into independent tasks which can be evaluated in parallel. Finally, results are presented which evaluate the various algorithm alternatives and compare the algorithm performance to other placement programs. Measurements are presented on the parallel speedups available.

  12. IEEE Std 730 Software Quality Assurance: Supporting CMMI-DEV v1.3, Product and Process Quality Assurance

    2011-05-27

    frameworks 4 CMMI-DEV IEEE / ISO / IEC 15288 / 12207 Quality Assurance ©2011 Walz IEEE Life Cycle Processes & Artifacts • Systems Life Cycle Processes...TAG to ISO TC 176 Quality Management • Quality: ASQ, work experience • Software: three books, consulting, work experience • Systems: Telecom & DoD...and IEEE 730 SQA need to align. The P730 IEEE standards working group has expanded the scope of the SQA process standard to align with IS 12207

  13. IEEE 802.11ah: A Technology to Face the IoT Challenge.

    Baños-Gonzalez, Victor; Afaqui, M Shahwaiz; Lopez-Aguilera, Elena; Garcia-Villegas, Eduard

    2016-11-22

    Since the conception of the Internet of things (IoT), a large number of promising applications and technologies have been developed, which will change different aspects in our daily life. This paper explores the key characteristics of the forthcoming IEEE 802.11ah specification. This future IEEE 802.11 standard aims to amend the IEEE 802.11 legacy specification to support IoT requirements. We present a thorough evaluation of the foregoing amendment in comparison to the most notable IEEE 802.11 standards. In addition, we expose the capabilities of future IEEE 802.11ah in supporting different IoT applications. Also, we provide a brief overview of the technology contenders that are competing to cover the IoT communications framework. Numerical results are presented showing how the future IEEE 802.11ah specification offers the features required by IoT communications, thus putting forward IEEE 802.11ah as a technology to cater the needs of the Internet of Things paradigm.

  14. 48 CFR 52.223-16 - IEEE 1680 Standard for the Environmental Assessment of Personal Computer Products.

    2010-10-01

    ... 48 Federal Acquisition Regulations System 2 2010-10-01 2010-10-01 false IEEE 1680 Standard for the... CONTRACT CLAUSES Text of Provisions and Clauses 52.223-16 IEEE 1680 Standard for the Environmental Assessment of Personal Computer Products. As prescribed in 23.706(b)(1), insert the following clause: IEEE...

  15. A VLSI System-on-Chip for Particle Detectors

    AUTHOR|(CDS)2078019

    In this thesis I present a System-on-Chip (SoC) I designed to oer a self- contained, compact data acquisition platform for micromegas detector mon- itoring. I carried on my work within the RD-51 collab oration of CERN. With a companion ADC, my architecture is capable to acquire the signal from a detector electro de, pro cess the data and p erform monitoring tests. The SoC is built around on a custom 8-bit micropro cessor with internal mem- ory resources and emb eds the p eripherals to b e interf...

  16. Augmenting the Energy-Saving Impact of IEEE 802.3az via the Control Plane

    Thaenchaikun , Chakadkit; Jakllari , Gentian; Paillassa , Béatrice

    2015-01-01

    International audience; IEEE 802.3az, the recent standard for Energy Efficient Ethernet, is one of the main contributions of the ICT industry to the global quest for energy efficiency. Energy consumption reduction is accomplished by essentially replacing the continuous IDLE of legacy IEEE 802.3 cards with a Low Power Idle. While this is an important step in the right direction, studies have shown that the energy saving with IEEE 802.3az highly depends on the traffic load and stops for link ut...

  17. Energy Harvesting - Wireless Sensor Networks for Indoors Applications Using IEEE 802.11

    Fafoutis, Xenofon; Sørensen, Thomas; Madsen, Jan

    2014-01-01

    The paper investigates the feasibility of using IEEE 802.11 in energy harvesting low-power sensing applications. The investigation is based on a prototype carbon dioxide sensor node that is powered by artificial indoors light. The wireless communication module of the sensor node is based on the RTX......4100 module. RTX4100 incorporates a wireless protocol that duty-cycles the radio while being compatible with IEEE 802.11 access points. The presented experiments demonstrate sustainable operation but indicate a trade-off between the benefits of using IEEE 802.11 in energy harvesting applications...

  18. Performance Analysis of IEEE 802.11e (EDCF) and IEEE 802.11(DCF) WLAN Incorporating Different Physical Layer Standards

    Sharma, V.; Singh, H.; Malhotra, J.

    2012-12-01

    Medium access coordination function basically implements the distributed coordination function (DCF) which provides support to best effort services but limited to QoS services. Subsequently, a new standard, namely enhanced distributed channel access (EDCA) is reported. The IEEE 802.11e (EDCA) defines MAC procedures to support QoS requirements which specifies distributed contention based access scheme to access the shared wireless media. This paper evaluates the performance of EDCA based IEEE 802.11 WLAN for various access categories (ACs) using OPNET™ Modeller 14.5. Further, the computed results are compared with DCF protocols in terms of QoS parameters. Furthermore, the simulative observation is reported at data rate of 54 Mbps using different physical layer protocols such as IEEE 802.11a/b/g to stumble on the best one to be implemented with EDCF to achieve improved QoS.

  19. Analysis of Adaptive Control Scheme in IEEE 802.11 and IEEE 802.11e Wireless LANs

    Lee, Bih-Hwang; Lai, Hui-Cheng

    In order to achieve the prioritized quality of service (QoS) guarantee, the IEEE 802.11e EDCAF (the enhanced distributed channel access function) provides the distinguished services by configuring the different QoS parameters to different access categories (ACs). An admission control scheme is needed to maximize the utilization of wireless channel. Most of papers study throughput improvement by solving the complicated multidimensional Markov-chain model. In this paper, we introduce a back-off model to study the transmission probability of the different arbitration interframe space number (AIFSN) and the minimum contention window size (CWmin). We propose an adaptive control scheme (ACS) to dynamically update AIFSN and CWmin based on the periodical monitoring of current channel status and QoS requirements to achieve the specific service differentiation at access points (AP). This paper provides an effective tuning mechanism for improving QoS in WLAN. Analytical and simulation results show that the proposed scheme outperforms the basic EDCAF in terms of throughput and service differentiation especially at high collision rate.

  20. Improvement of CMOS VLSI rad tolerance by processing technics

    Guyomard, D.; Desoutter, I.

    1986-01-01

    The following study concerns the development of integrated circuits for fields requiring only relatively low radiation tolerance levels, and especially for the civil spatial district area. Process modifications constitute our basic study. They have been carried into effects. Our work and main results are reported in this paper. Well known 2.5 and 3 μm CMOS technologies are under our concern. A first set of modifications enables us to double the cumulative dose tolerance of a 4 Kbit SRAM, keeping at the same time the same kind of damage. We obtain memories which tolerate radiation doses as high as 16 KRad(Si). Repetitivity of the results, linked to the quality assurance of this specific circuit, is reported here. A second set of modifications concerns the processing of gate array. In particular, the choice of the silicon substrate type, (epitaxy substrate), is under investigation. On the other hand, a complete study of a test vehicule allows us to accurately measure the rad tolerance of various components of the Cell library [fr

  1. 2011 IEEE Visualization Contest Winner: Visualizing Unsteady Vortical Behavior of a Centrifugal Pump

    Otto, Mathias; Kuhn, Alexander; Engelke, Wito; Theisel, Holger

    2012-01-01

    In the 2011 IEEE Visualization Contest, the dataset represented a high-resolution simulation of a centrifugal pump operating below optimal speed. The goal was to find suitable visualization techniques to identify regions of rotating stall

  2. Defending IEEE 802.11-Based Networks Against Denial Of Service Attacks

    Tan, Boon

    2003-01-01

    The convenience of IEEE 8O2.11-based wireless access networks has led to widespread deployment in the consumer, industrial and military sectors However, this use is predicated on an implicit assumption of confidentiality...

  3. Corrections to "Connectivity-Based Reliable Multicast MAC Protocol for IEEE 802.11 Wireless LANs"

    Choi Woo-Yong

    2010-01-01

    Full Text Available We have found the errors in the throughput formulae presented in our paper "Connectivity-based reliable multicast MAC protocol for IEEE 802.11 wireless LANs". We provide the corrected formulae and numerical results.

  4. Return of IEEE Std 627 and its Value to Equipment Qualification Programs

    Horvath, D.A.

    2012-01-01

    IEEE Std 627 ''Design Qualification of Safety Systems Equipment Used in Nuclear Power Generating Stations'' was issued to more generically establish qualification requirements in the form of a high level umbrella document. Efforts on this standard began in late 1975 at the request of the IEEE Nuclear Standards Management Board. In 1977 a joint ASME/IEEE agreement established responsibility for qualification and quality assurance standards preparation. ASME accepted responsibility for Quality Assurance and IEEE for qualification. In accordance with that agreement, IEEE completed the generic qualification standard in 1980. This document provided high level approaches, criteria, guidance, and principles for qualification of both electrical and mechanical equipment that at that time appeared in no other industry standard. IEEE Std 627-1980 was later reaffirmed in 1996. In 1986, ASME's Board on Nuclear Codes and Standards directed its Committee on Qualification of Mechanical Equipment (QME) to develop a standard for qualifying mechanical equipment. This task was completed in several parts during the time frame from 1992 to 1994. Partly in response to this activity, IEEE Std 627 was withdrawn in 2002. Later although withdrawn, it was found that IEEE Std 627 was continuing to be used and referenced by many entities both in the US and other countries including in ASME's QME-1-2002 ''Qualification of Active Mechanical Equipment Used in Nuclear Power Plants'', US NRC's NUREG-0800 Standard Review Plan Section 3.11, at least one reactor vendor's Design Certification Document (DCD), several international licensing documents, and elsewhere. As a result, in 2007, the IEEE Standards Board authorized Working Group 2.10 of Subcommittee 2 (Qualification) of the Power and Energy Society's Nuclear Power Engineering Committee to resurrect and update IEEE Std 627-1980 (Reaff 1996). The result was the culmination IEEE Std 627 in 2010. This paper will report on the eight improvements made

  5. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-01-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  6. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-01-01

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction. PMID:26287193

  7. Analog VLSI Models of Range-Tuned Neurons in the Bat Echolocation System

    Horiuchi Timothy

    2003-01-01

    Full Text Available Bat echolocation is a fascinating topic of research for both neuroscientists and engineers, due to the complex and extremely time-constrained nature of the problem and its potential for application to engineered systems. In the bat's brainstem and midbrain exist neural circuits that are sensitive to the specific difference in time between the outgoing sonar vocalization and the returning echo. While some of the details of the neural mechanisms are known to be species-specific, a basic model of reafference-triggered, postinhibitory rebound timing is reasonably well supported by available data. We have designed low-power, analog VLSI circuits to mimic this mechanism and have demonstrated range-dependent outputs for use in a real-time sonar system. These circuits are being used to implement range-dependent vocalization amplitude, vocalization rate, and closest target isolation.

  8. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

    Chen, Ying-Lun; Hwang, Wen-Jyi; Ke, Chi-En

    2015-08-13

    A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  9. Ant System-Corner Insertion Sequence: An Efficient VLSI Hard Module Placer

    HOO, C.-S.

    2013-02-01

    Full Text Available Placement is important in VLSI physical design as it determines the time-to-market and chip's reliability. In this paper, a new floorplan representation which couples with Ant System, namely Corner Insertion Sequence (CIS is proposed. Though CIS's search complexity is smaller than the state-of-the-art representation Corner Sequence (CS, CIS adopts a preset boundary on the placement and hence, leading to search bound similar to CS. This enables the previous unutilized corner edges to become viable. Also, the redundancy of CS representation is eliminated in CIS leads to a lower search complexity of CIS. Experimental results on Microelectronics Center of North Carolina (MCNC hard block benchmark circuits show that the proposed algorithm performs comparably in terms of area yet at least two times faster than CS.

  10. A parallel VLSI architecture for a digital filter of arbitrary length using Fermat number transforms

    Truong, T. K.; Reed, I. S.; Yeh, C. S.; Shao, H. M.

    1982-01-01

    A parallel architecture for computation of the linear convolution of two sequences of arbitrary lengths using the Fermat number transform (FNT) is described. In particular a pipeline structure is designed to compute a 128-point FNT. In this FNT, only additions and bit rotations are required. A standard barrel shifter circuit is modified so that it performs the required bit rotation operation. The overlap-save method is generalized for the FNT to compute a linear convolution of arbitrary length. A parallel architecture is developed to realize this type of overlap-save method using one FNT and several inverse FNTs of 128 points. The generalized overlap save method alleviates the usual dynamic range limitation in FNTs of long transform lengths. Its architecture is regular, simple, and expandable, and therefore naturally suitable for VLSI implementation.

  11. Defending IEEE 802.11-Based Networks Against Denial Of Service Attacks

    Tan, Boon

    2003-01-01

    ...) attacks targeting its management and media access protocols Computer simulation models have proven to be effective tools in the study of cause and effect in numerous fields This thesis involved the design and implementation of a IEEE 8O2.11-based simulation model using OMNeT++, to investigate the effects of different types of DoS attacks on a IEEE 8O2.11 network, and the effectiveness of corresponding countermeasures.

  12. Homeland Security Affairs Journal, Supplement - 2012: IEEE 2011 Conference on Technology for Homeland Security: Best Papers

    2012-01-01

    Homeland Security Affairs is the peer-reviewed online journal of the Naval Postgraduate School Center for Homeland Defense and Security (CHDS), providing a forum to propose and debate strategies, policies, and organizational arrangements to strengthen U.S. homeland security. The instructors, participants, alumni, and partners of CHDS represent the leading subject matter experts and practitioners in the field of homeland security. IEEE Supplement 2012. Supplement: IEEE 2011 Conference on Te...

  13. Performance of the IEEE 802.3 EPON registration scheme under high load

    Bhatia, Swapnil P.; Bartos, Radim

    2004-09-01

    The proposed standard for the IEEE 802.3 Ethernet Passive Optical Network includes a random delayed transmission scheme for registration of new nodes. Although the scheme performs well on low loads, our simulation demonstrates the degraded and undesirable performance of the scheme at higher loads. We propose a simple modification to the current scheme that increases its range of operation and is compatible with the IEEE draft standard. We demonstrate the improvement in performance gained without any significant increase in registration delay.

  14. Isolan - A Fibre Optic Network Conforming To IEEE 802.3 Standards

    Roworth, D. A. A.; Howe, N.

    1986-10-01

    The progress of the IEEE 802.3 standard for fibre optic LANs is indicated with reference to both mixed media networks and full fibre networks. For a fibre optic network the most suitable layout is a "snowflake" topology composed of multiport repeaters and active fibre hubs. A range of components is described which enables the realisation of such a topology in conformance with the IEEE 802.3 standard.

  15. Real-time-service-based Distributed Scheduling Scheme for IEEE 802.16j Networks

    Kuo-Feng Huang; Shih-Jung Wu

    2013-01-01

    Supporting Quality of Service (QoS) guarantees for diverse multimedia services is the primary concern for IEEE802.16j networks. A scheduling scheme that satisfies the QoS requirements has become more important for wireless communications. We proposed an adaptive nontransparent-based distributed scheduling scheme (ANDS) for IEEE 802.16j networks. ANDS comprises three major components: Priority Assignment, Resource Allocation, Preserved Bandwidth Adjustment. Different service-type connections p...

  16. Enhancing MAC performance of DCF protocol for IEEE 802.11 wireless LANs

    Choi, Woo-Yong

    2017-01-01

    The DCF (Distributed Coordination Function) is the basic MAC (Medium Access Control) protocol of IEEE 802.11 wireless LANs and compatible with various IEEE 802.11 PHY extensions. The performance of the DCF degrades exponentially as the number of nodes participating in the DCF transmission procedure increases. To deal with this problem, we propose a simple, however efficient modification of the DCF by which the performance of the DCF is greatly enhanced.

  17. A novel configurable VLSI architecture design of window-based image processing method

    Zhao, Hui; Sang, Hongshi; Shen, Xubang

    2018-03-01

    Most window-based image processing architecture can only achieve a certain kind of specific algorithms, such as 2D convolution, and therefore lack the flexibility and breadth of application. In addition, improper handling of the image boundary can cause loss of accuracy, or consume more logic resources. For the above problems, this paper proposes a new VLSI architecture of window-based image processing operations, which is configurable and based on consideration of the image boundary. An efficient technique is explored to manage the image borders by overlapping and flushing phases at the end of row and the end of frame, which does not produce new delay and reduce the overhead in real-time applications. Maximize the reuse of the on-chip memory data, in order to reduce the hardware complexity and external bandwidth requirements. To perform different scalar function and reduction function operations in pipeline, this can support a variety of applications of window-based image processing. Compared with the performance of other reported structures, the performance of the new structure has some similarities to some of the structures, but also superior to some other structures. Especially when compared with a systolic array processor CWP, this structure at the same frequency of approximately 12.9% of the speed increases. The proposed parallel VLSI architecture was implemented with SIMC 0.18-μm CMOS technology, and the maximum clock frequency, power consumption, and area are 125Mhz, 57mW, 104.8K Gates, respectively, furthermore the processing time is independent of the different window-based algorithms mapped to the structure

  18. Aplicación de flujos de cargas sucesivos con jacobiana constante para la determinación del punto de colapso de tensión. Validación con patrón IEEE-14; Aplication of sucessive power flows with constant jacobian to obtain the point of voltage collapse. Test

    Zaid García Sánchez

    2011-06-01

    Full Text Available Este trabajo presenta un método de solución para el análisis estático de las inestabilidades de tensión. El principal aporte del trabajo es la obtención de la región inestable de la curva P-V utilizando flujos sucesivos basados en un método Newton con jacobiana constante que mantiene los lazos de acoplamiento P-V y Q-δ. El algoritmo se implementó en el paquete de programas PSX, se modela la carga dependiente del voltaje, los límites de potencia activa y reactiva de las máquinas y la variación de la generación de potencia activa de los nodos P-V teniendo en cuenta la reserva de cada máquina que participa en la variación de generación. Se comparan los resultados con un flujo continuado implementado en el software PSAT para el patrón de 14 nodos de la IEEE. Para ambos casos se obtienen resultados muy similares, comprobándose así la exactitud obtenida con la técnica implementada.   This paper presents a solution method for tension instability static analyses. The main contribution of this research is the determinations of the unstable part of P-V curve using a multiple power flow based on the Newton method with constant Jacobian that keeps the links between P-V y Q-δ. This algorithm was implemented within PSX program, the load is modeled as voltage dependent and the limits of active and reactive power of the machines, plus the variation of P-V node generation, taking into account the reserve in each node. The result are compared with a continuation power flow implemented in PSAT software for a grid of 14 nodes patron. In both cases the result are very similar verifying the exactitude of the program developed.

  19. ANÁLISE DE DESEMPENHO EM REDES IEEE 802.3 APLICADO PARA SISTEMA DE TEMPO REAL

    Ricardo Alexsandro de Medeiros Valentim

    2011-06-01

    Full Text Available A tecnologia Ethernet domina o mercado de rede local de computadores. No entanto, não foi estabelecida como uma tecnologia para automação industrial, onde o determinismo procura os requisitos com um desempenho de tempo real. Muitas soluções têm sido propostas para resolver o problema do determinismo não, que se baseiam principalmente no TDMA (acesso múltiplo por divisão de tempo, passagem de token e mestre-escravo. É neste contexto que este trabalho é realizado, através de medidas de desempenho em redes de comunicação que utilizam o padrão IEEE 802.3, observando o comportamento destas redes, quando submetidos a diferentes cenários de sobrecarga. Para isso, as variações foram aprovadas em ambiente de teste, que será baseado em Shared Ethernet (Hub, Ethernet e Ethernet Switch com prioridade (IEEE 802.1Q. Desta forma, é possível indicar quais os dispositivos analisados pelos testes de desempenho demonstrado um comportamento mais adequado para suportar as aplicações com requisitos de tempo real.

  20. VLSI Research

    1984-04-01

    Interpretation of IMMEDIATE fields of instructions (except ldhi ): W (c) (d) (e) sssssssssssss s imml9 sssssssssssssssssss...s imml3 Destination REGISTER of a LDHI instruction: imml9 0000000000000 Data in REGISTERS when operated upon: 32-bit quantity...Oll x l OOOO OOOl calli sll OOlO getpsw sra xxzOOll getlpc srl OlOO putpsw ldhi OlOl and zzzOllO or ldxw stxw Olll xor

  1. VLSI Implementation of a Fixed-Complexity Soft-Output MIMO Detector for High-Speed Wireless

    Di Wu

    2010-01-01

    Full Text Available This paper presents a low-complexity MIMO symbol detector with close-Maximum a posteriori performance for the emerging multiantenna enhanced high-speed wireless communications. The VLSI implementation is based on a novel MIMO detection algorithm called Modified Fixed-Complexity Soft-Output (MFCSO detection, which achieves a good trade-off between performance and implementation cost compared to the referenced prior art. By including a microcode-controlled channel preprocessing unit and a pipelined detection unit, it is flexible enough to cover several different standards and transmission schemes. The flexibility allows adaptive detection to minimize power consumption without degradation in throughput. The VLSI implementation of the detector is presented to show that real-time MIMO symbol detection of 20 MHz bandwidth 3GPP LTE and 10 MHz WiMAX downlink physical channel is achievable at reasonable silicon cost.

  2. A new VLSI complex integer multiplier which uses a quadratic-polynomial residue system with Fermat numbers

    Shyu, H. C.; Reed, I. S.; Truong, T. K.; Hsu, I. S.; Chang, J. J.

    1987-01-01

    A quadratic-polynomial Fermat residue number system (QFNS) has been used to compute complex integer multiplications. The advantage of such a QFNS is that a complex integer multiplication requires only two integer multiplications. In this article, a new type Fermat number multiplier is developed which eliminates the initialization condition of the previous method. It is shown that the new complex multiplier can be implemented on a single VLSI chip. Such a chip is designed and fabricated in CMOS-Pw technology.

  3. VLSI System Implementation of 200 MHz, 8-bit, 90nm CMOS Arithmetic and Logic Unit (ALU Processor Controller

    Fazal NOORBASHA

    2012-08-01

    Full Text Available In this present study includes the Very Large Scale Integration (VLSI system implementation of 200MHz, 8-bit, 90nm Complementary Metal Oxide Semiconductor (CMOS Arithmetic and Logic Unit (ALU processor control with logic gate design style and 0.12µm six metal 90nm CMOS fabrication technology. The system blocks and the behaviour are defined and the logical design is implemented in gate level in the design phase. Then, the logic circuits are simulated and the subunits are converted in to 90nm CMOS layout. Finally, in order to construct the VLSI system these units are placed in the floor plan and simulated with analog and digital, logic and switch level simulators. The results of the simulations indicates that the VLSI system can control different instructions which can divided into sub groups: transfer instructions, arithmetic and logic instructions, rotate and shift instructions, branch instructions, input/output instructions, control instructions. The data bus of the system is 16-bit. It runs at 200MHz, and operating power is 1.2V. In this paper, the parametric analysis of the system, the design steps and obtained results are explained.

  4. Improving the communication reliability of body sensor networks based on the IEEE 802.15.4 protocol.

    Gomes, Diogo; Afonso, José A

    2014-03-01

    Body sensor networks (BSNs) enable continuous monitoring of patients anywhere, with minimum constraints to daily life activities. Although the IEEE 802.15.4 and ZigBee(®) (ZigBee Alliance, San Ramon, CA) standards were mainly developed for use in wireless sensors network (WSN) applications, they are also widely used in BSN applications because of device characteristics such as low power, low cost, and small form factor. However, compared with WSNs, BSNs present some very distinctive characteristics in terms of traffic and mobility patterns, heterogeneity of the nodes, and quality of service requirements. This article evaluates the suitability of the carrier sense multiple access-collision avoidance protocol, used by the IEEE 802.15.4 and ZigBee standards, for data-intensive BSN applications, through the execution of experimental tests in different evaluation scenarios, in order to take into account the effects of contention, clock drift, and hidden nodes on the communication reliability. Results show that the delivery ratio may decrease substantially during transitory periods, which can last for several minutes, to a minimum of 90% with retransmissions and 13% without retransmissions. This article also proposes and evaluates the performance of the BSN contention avoidance mechanism, which was designed to solve the identified reliability problems. This mechanism was able to restore the delivery ratio to 100% even in the scenario without retransmissions.

  5. On the Feasibility of Wireless Multimedia Sensor Networks over IEEE 802.15.5 Mesh Topologies.

    Garcia-Sanchez, Antonio-Javier; Losilla, Fernando; Rodenas-Herraiz, David; Cruz-Martinez, Felipe; Garcia-Sanchez, Felipe

    2016-05-05

    Wireless Multimedia Sensor Networks (WMSNs) are a special type of Wireless Sensor Network (WSN) where large amounts of multimedia data are transmitted over networks composed of low power devices. Hierarchical routing protocols typically used in WSNs for multi-path communication tend to overload nodes located within radio communication range of the data collection unit or data sink. The battery life of these nodes is therefore reduced considerably, requiring frequent battery replacement work to extend the operational life of the WSN system. In a wireless sensor network with mesh topology, any node may act as a forwarder node, thereby enabling multiple routing paths toward any other node or collection unit. In addition, mesh topologies have proven advantages, such as data transmission reliability, network robustness against node failures, and potential reduction in energy consumption. This work studies the feasibility of implementing WMSNs in mesh topologies and their limitations by means of exhaustive computer simulation experiments. To this end, a module developed for the Synchronous Energy Saving (SES) mode of the IEEE 802.15.5 mesh standard has been integrated with multimedia tools to thoroughly test video sequences encoded using H.264 in mesh networks.

  6. TCP Performance in Multi-Polling Game Theory-Based IEEE 802.11 Networks

    Cuzanauskas Tomas

    2016-12-01

    Full Text Available Easy usage and integration with various applications made IEEE 802.11 one of the most used technologies these days, both at home and business premises. Over the years, there have been many additional improvements to the 802.11 standards. Nevertheless, the algorithms and Media Access Control (MAC layer methods are almost the same as in previous Wi-Fi versions. In this paper, a set of methods to improve the total system capacity is proposed – such as efficient transmit power management based on Game Theory with a custom wireless medium protocol. The transmit power management and wireless medium protocol is verified by both simulation and real application scenarios. The results conclude that the capacity of the proposed wireless medium protocol is overall 20 percent higher than the standard 802.11 wireless medium access protocols. Additional TCP Acknowledgment filtering, which was tested together with the proposed wireless medium access protocol, can provide up to 10-percent-higher TCP throughput in high-density scenarios, especially for asymmetrical traffic cases. The conducted research suggests that efficient power management could result in lighter transmit power allocation rules that are currently set by the local regulators for current Wi-Fi devices. Thus, better propagation characteristics and wireless medium management would lead to an overall higher wireless system capacity.

  7. On the Feasibility of Wireless Multimedia Sensor Networks over IEEE 802.15.5 Mesh Topologies

    Antonio-Javier Garcia-Sanchez

    2016-05-01

    Full Text Available Wireless Multimedia Sensor Networks (WMSNs are a special type of Wireless Sensor Network (WSN where large amounts of multimedia data are transmitted over networks composed of low power devices. Hierarchical routing protocols typically used in WSNs for multi-path communication tend to overload nodes located within radio communication range of the data collection unit or data sink. The battery life of these nodes is therefore reduced considerably, requiring frequent battery replacement work to extend the operational life of the WSN system. In a wireless sensor network with mesh topology, any node may act as a forwarder node, thereby enabling multiple routing paths toward any other node or collection unit. In addition, mesh topologies have proven advantages, such as data transmission reliability, network robustness against node failures, and potential reduction in energy consumption. This work studies the feasibility of implementing WMSNs in mesh topologies and their limitations by means of exhaustive computer simulation experiments. To this end, a module developed for the Synchronous Energy Saving (SES mode of the IEEE 802.15.5 mesh standard has been integrated with multimedia tools to thoroughly test video sequences encoded using H.264 in mesh networks.

  8. Application of statistics to VLSI circuit manufacturing : test, diagnosis, and reliability

    Krishnan, Shaji

    2017-01-01

    Semiconductor product manufacturing companies strive to deliver defect free, and reliable products to their customers. However, with the down-scaling of technology, increasing the throughput at every stage of semiconductor product manufacturing becomes a harder challenge. To avoid process-related

  9. IEEE 1547 and 2030 Standards for Distributed Energy Resources Interconnection and Interoperability with the Electricity Grid

    Basso, T.

    2014-12-01

    Public-private partnerships have been a mainstay of the U.S. Department of Energy and the National Renewable Energy Laboratory (DOE/NREL) approach to research and development. These partnerships also include technology development that enables grid modernization and distributed energy resources (DER) advancement, especially renewable energy systems integration with the grid. Through DOE/NREL and industry support of Institute of Electrical and Electronics Engineers (IEEE) standards development, the IEEE 1547 series of standards has helped shape the way utilities and other businesses have worked together to realize increasing amounts of DER interconnected with the distribution grid. And more recently, the IEEE 2030 series of standards is helping to further realize greater implementation of communications and information technologies that provide interoperability solutions for enhanced integration of DER and loads with the grid. For these standards development partnerships, for approximately $1 of federal funding, industry partnering has contributed $5. In this report, the status update is presented for the American National Standards IEEE 1547 and IEEE 2030 series of standards. A short synopsis of the history of the 1547 standards is first presented, then the current status and future direction of the ongoing standards development activities are discussed.

  10. IEEE No. 323, IEEE trial-use standard: General guide for qualifying Class I electric equipment for nuclear power generating stations

    Anon.

    1992-01-01

    This document describes the basic requirements for the qualification of Class I electric equipment. This is equipment which is essential to the safe shutdown and isolation of the reactor or whose failure or damage could result in significant release of radioactive material. The purpose of this document is to provide guidance for demonstrating the qualifications of electrical equipment as required in the IEEE Std 279 -- Criteria for Nuclear Power Generating Station Protection Systems, and IEEE Std 308 -- Criteria for Class 1E Electric Systems for Nuclear Power Generating Stations. The qualification methods described may be used in conjunction with the Guides for qualifying specific types of equipment, (see Foreword), for updating qualification following modifications or for qualifying equipment for which no applicable Guide exists

  11. Design of handoff procedures for broadband wireless access IEEE 802.16 based networks

    V. Rangel–Licea

    2008-01-01

    Full Text Available IEEE 802.16 is a protocol for fixed broad band wire less access that is currently trying to add mobility among mobile users in the standard. However, mobility adds some technical barriers that should be solved first, this is the case of HO "handoff" (change of connection between two base stations "BS" by a mobile user. In this paper, the problem of HO in IEEE 802.16 is approached try ing to maintain the quality of service (QoS of mobile users. A mechanism for changing connection during HO is pre sented. A simulation model based on OPNET MODELER1 was developed to evaluate the performance of the proposed HO mechanism. Finally, this paper demonstrates that it is possible to implement a seam less HO mech a nism over IEEE 802.16 even for users with de manding applications such as voice over IP.

  12. PERFORMANCE STUDY OF DISTRIBUTED COORDINATION FUNCTION OVER IEEE 802.11A PHYSICAL LAYER

    S. SELVAKENEDDY

    2006-06-01

    Full Text Available IEEE 802.11a is one of the latest standards to be released by the IEEE Project 802 for wireless LANs. It has specified an additional physical layer (PHY to support higher data rates, and is termed as the orthogonal frequency division multiplexing (OFDM. In order to exploit its benefits, one of the medium access control (MAC protocols specified in the IEEE 802.11 specification is called distributed coordination function (DCF. DCF is a carrier sense multiple access with collision avoidance (CSMA/CA scheme with slotted binary exponential backoff. The frames can be transmitted using the basic access scheme or the RTS/CTS scheme in DCF. It was demonstrated previously that the RTS/CTS mechanism works well in most scenarios for the previously specified PHYs. In this work, a simple simulator is developed to verify the scalability of the RTS/CTS mechanism over OFDM PHY, which supports much higher data rates.

  13. IEEE 1451.2 based Smart sensor system using ADuc847

    Sreejithlal, A.; Ajith, Jose

    IEEE 1451 standard defines a standard interface for connecting transducers to microprocessor based data acquisition systems, instrumentation systems, control and field networks. Smart transducer interface module (STIM) acts as a unit which provides signal conditioning, digitization and data packet generation functions to the transducers connected to it. This paper describes the implementation of a microcontroller based smart transducer interface module based on IEEE 1451.2 standard. The module, implemented using ADuc847 microcontroller has 2 transducer channels and is programmed using Embedded C language. The Sensor system consists of a Network Controlled Application Processor (NCAP) module which controls the Smart transducer interface module (STIM) over an IEEE1451.2-RS232 bus. The NCAP module is implemented as a software module in C# language. The hardware details, control principles involved and the software implementation for the STIM are described in detail.

  14. The scalable coherent interface, IEEE P1596, status and possible applications to data acquisition and physics

    Gustavson, D.B.

    1990-01-01

    IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained while developing Fastbus (ANSI/IEEE 960-1986, IEC 935), Futurebus (IEEE P896.x) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor in multiprocessor systems with thousands of processors; efficient support of a coherent distributed-cache image of distributed shared memory; support for repeaters which interface to existing or future buses; and support for inexpensive small rings as well as for general switched interconnections like Banyan, Omega, or crossbar networks. This paper presents a summary of current directions, reports the status of the work in progress, and suggests some applications in data acquisition and physics. 7 refs

  15. An analytical model for the performance analysis of concurrent transmission in IEEE 802.15.4.

    Gezer, Cengiz; Zanella, Alberto; Verdone, Roberto

    2014-03-20

    Interference is a serious cause of performance degradation for IEEE802.15.4 devices. The effect of concurrent transmissions in IEEE 802.15.4 has been generally investigated by means of simulation or experimental activities. In this paper, a mathematical framework for the derivation of chip, symbol and packet error probability of a typical IEEE 802.15.4 receiver in the presence of interference is proposed. Both non-coherent and coherent demodulation schemes are considered by our model under the assumption of the absence of thermal noise. Simulation results are also added to assess the validity of the mathematical framework when the effect of thermal noise cannot be neglected. Numerical results show that the proposed analysis is in agreement with the measurement results on the literature under realistic working conditions.

  16. Throughput and delay analysis of IEEE 802.15.6-based CSMA/CA protocol.

    Ullah, Sana; Chen, Min; Kwak, Kyung Sup

    2012-12-01

    The IEEE 802.15.6 is a new communication standard on Wireless Body Area Network (WBAN) that focuses on a variety of medical, Consumer Electronics (CE) and entertainment applications. In this paper, the throughput and delay performance of the IEEE 802.15.6 is presented. Numerical formulas are derived to determine the maximum throughput and minimum delay limits of the IEEE 802.15.6 for an ideal channel with no transmission errors. These limits are derived for different frequency bands and data rates. Our analysis is validated by extensive simulations using a custom C+ + simulator. Based on analytical and simulation results, useful conclusions are derived for network provisioning and packet size optimization for different applications.

  17. An IEEE 802.11 EDCA Model with Support for Analysing Networks with Misbehaving Nodes

    Szott Szymon

    2010-01-01

    Full Text Available We present a novel model of IEEE 802.11 EDCA with support for analysing networks with misbehaving nodes. In particular, we consider backoff misbehaviour. Firstly, we verify the model by extensive simulation analysis and by comparing it to three other IEEE 802.11 models. The results show that our model behaves satisfactorily and outperforms other widely acknowledged models. Secondly, a comparison with simulation results in several scenarios with misbehaving nodes proves that our model performs correctly for these scenarios. The proposed model can, therefore, be considered as an original contribution to the area of EDCA models and backoff misbehaviour.

  18. Reactive GTS Allocation Protocol for Sporadic Events Using the IEEE 802.15.4

    Mukhtar Azeem

    2014-01-01

    by the IEEE 802.15.4 standard. The proposed control protocol ensures that a given offline sporadic schedule can be adapted online in a timely manner such that the static periodic schedule has not been disturbed and the IEEE 802.15.4 standard compliance remains intact. The proposed protocol is simulated in OPNET. The simulation results are analyzed and presented in this paper to prove the correctness of the proposed protocol regarding the efficient real-time sporadic event delivery along with the periodic event propagation.

  19. Analysis Of Impact Of Various Parameters On BER Performance For IEEE 802.11b

    Nilesh B. Kalani

    2015-08-01

    Full Text Available Abstract This paper discusses about IEEE 802.11b simulation model implemented using LabVIEW software and its analyses for impact on bit error rate BER for different parameters as channel type channel number data transmission rate and packet size. Audio file is being transmitted processed and analyzed using the model for various parameters. This paper gives analysis of BER verses ESN0 for various parameter like data rate packet size and communication channel for the IEEE 802.11b simulation model generated using LabVIEW. It is proved that BER can be optimized by tweaking different parameters of wireless communication system.

  20. Spectrum Hole Identification in IEEE 802.22 WRAN using Unsupervised Learning

    V. Balaji; S. Anand; C.R. Hota; G. Raghurama

    2016-01-01

    In this paper we present a Cooperative Spectrum Sensing (CSS) algorithm for Cognitive Radios (CR) based on IEEE 802.22Wireless Regional Area Network (WRAN) standard. The core objective is to improve cooperative sensing efficiency which specifies how fast a decision can be reached in each round of cooperation (iteration) to sense an appropriate number of channels/bands (i.e. 86 channels of 7MHz bandwidth as per IEEE 802.22) within a time constraint (channel sensing time). To meet this objectiv...

  1. Self-Coexistence among IEEE 802.22 Networks: Distributed Allocation of Power and Channel

    Sayef Azad Sakin; Md. Abdur Razzaque; Mohammad Mehedi Hassan; Atif Alamri; Nguyen H. Tran; Giancarlo Fortino

    2017-01-01

    Ensuring self-coexistence among IEEE 802.22 networks is a challenging problem owing to opportunistic access of incumbent-free radio resources by users in co-located networks. In this study, we propose a fully-distributed non-cooperative approach to ensure self-coexistence in downlink channels of IEEE 802.22 networks. We formulate the self-coexistence problem as a mixed-integer non-linear optimization problem for maximizing the network data rate, which is an NP-hard one. This work explores a s...

  2. International Conference on Grey Systems and intelligent Services (IEEE GSIS 2009)

    Liu, Sifeng; Advances in Grey Systems Research

    2010-01-01

    This book contains contributions by some of the leading researchers in the area of grey systems theory and applications. All the papers included in this volume are selected from the contributions physically presented at the 2009 IEEE International Conference on Grey Systems and Intelligent Services, November 11 – 12, 2009, Nanjing, Jiangsu, People’s Republic of China. This event was jointly sponsored by IEEE Systems, Man, and Cybernetics Society, Natural Science Foundation of China, and Grey Systems Society of China. Additionally, Nanjing University of Aeronautics and Astronautics also invested heavily in this event with its direct and indirect financial and administrative supports.

  3. IEEE 802.11e (EDCA analysis in the presence of hidden stations

    Xijie Liu

    2011-07-01

    Full Text Available The key contribution of this paper is the combined analytical analysis of both saturated and non-saturated throughput of IEEE 802.11e networks in the presence of hidden stations. This approach is an extension to earlier works by other authors which provided Markov chain analysis to the IEEE 802.11 family under various assumptions. Our approach also modifies earlier expressions for the probability that a station transmits a packet in a vulnerable period. The numerical results provide the impact of the access categories on the channel throughput. Various throughput results under different mechanisms are presented.

  4. An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm

    Ying-Lun Chen

    2015-08-01

    Full Text Available A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO, and the feature extraction is carried out by the generalized Hebbian algorithm (GHA. To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

  5. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search

    Yuan-Jyun Chang

    2016-12-01

    Full Text Available The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO. The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  6. Motion-sensor fusion-based gesture recognition and its VLSI architecture design for mobile devices

    Zhu, Wenping; Liu, Leibo; Yin, Shouyi; Hu, Siqi; Tang, Eugene Y.; Wei, Shaojun

    2014-05-01

    With the rapid proliferation of smartphones and tablets, various embedded sensors are incorporated into these platforms to enable multimodal human-computer interfaces. Gesture recognition, as an intuitive interaction approach, has been extensively explored in the mobile computing community. However, most gesture recognition implementations by now are all user-dependent and only rely on accelerometer. In order to achieve competitive accuracy, users are required to hold the devices in predefined manner during the operation. In this paper, a high-accuracy human gesture recognition system is proposed based on multiple motion sensor fusion. Furthermore, to reduce the energy overhead resulted from frequent sensor sampling and data processing, a high energy-efficient VLSI architecture implemented on a Xilinx Virtex-5 FPGA board is also proposed. Compared with the pure software implementation, approximately 45 times speed-up is achieved while operating at 20 MHz. The experiments show that the average accuracy for 10 gestures achieves 93.98% for user-independent case and 96.14% for user-dependent case when subjects hold the device randomly during completing the specified gestures. Although a few percent lower than the conventional best result, it still provides competitive accuracy acceptable for practical usage. Most importantly, the proposed system allows users to hold the device randomly during operating the predefined gestures, which substantially enhances the user experience.

  7. Prototype architecture for a VLSI level zero processing system. [Space Station Freedom

    Shi, Jianfei; Grebowsky, Gerald J.; Horner, Ward P.; Chesney, James R.

    1989-01-01

    The prototype architecture and implementation of a high-speed level zero processing (LZP) system are discussed. Due to the new processing algorithm and VLSI technology, the prototype LZP system features compact size, low cost, high processing throughput, and easy maintainability and increased reliability. Though extensive control functions have been done by hardware, the programmability of processing tasks makes it possible to adapt the system to different data formats and processing requirements. It is noted that the LZP system can handle up to 8 virtual channels and 24 sources with combined data volume of 15 Gbytes per orbit. For greater demands, multiple LZP systems can be configured in parallel, each called a processing channel and assigned a subset of virtual channels. The telemetry data stream will be steered into different processing channels in accordance with their virtual channel IDs. This super system can cope with a virtually unlimited number of virtual channels and sources. In the near future, it is expected that new disk farms with data rate exceeding 150 Mbps will be available from commercial vendors due to the advance in disk drive technology.

  8. VLSI design of an RSA encryption/decryption chip using systolic array based architecture

    Sun, Chi-Chia; Lin, Bor-Shing; Jan, Gene Eu; Lin, Jheng-Yi

    2016-09-01

    This article presents the VLSI design of a configurable RSA public key cryptosystem supporting the 512-bit, 1024-bit and 2048-bit based on Montgomery algorithm achieving comparable clock cycles of current relevant works but with smaller die size. We use binary method for the modular exponentiation and adopt Montgomery algorithm for the modular multiplication to simplify computational complexity, which, together with the systolic array concept for electric circuit designs effectively, lower the die size. The main architecture of the chip consists of four functional blocks, namely input/output modules, registers module, arithmetic module and control module. We applied the concept of systolic array to design the RSA encryption/decryption chip by using VHDL hardware language and verified using the TSMC/CIC 0.35 m 1P4 M technology. The die area of the 2048-bit RSA chip without the DFT is 3.9 × 3.9 mm2 (4.58 × 4.58 mm2 with DFT). Its average baud rate can reach 10.84 kbps under a 100 MHz clock.

  9. A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

    Chang, Yuan-Jyun; Hwang, Wen-Jyi; Chen, Chih-Chang

    2016-12-07

    The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

  10. Emergent auditory feature tuning in a real-time neuromorphic VLSI system

    Sadique eSheik

    2012-02-01

    Full Text Available Many sounds of ecological importance, such as communication calls, are characterised by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamocortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP, which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectrotemporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step towards the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  11. Robust working memory in an asynchronously spiking neural network realized in neuromorphic VLSI

    Massimiliano eGiulioni

    2012-02-01

    Full Text Available We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory of integrate-and-fire (LIF neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of ‘high’ and ‘low’-firing activity. Depending on the overall excitability, transitions to the ‘high’ state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the ‘high’ state retains a working memory of a stimulus until well after its release. In the latter case, ‘high’ states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated corrupted ‘high’ states comprising neurons of both excitatory populations. Within a basin of attraction, the network dynamics corrects such states and re-establishes the prototypical ‘high’ state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  12. Robust Working Memory in an Asynchronously Spiking Neural Network Realized with Neuromorphic VLSI.

    Giulioni, Massimiliano; Camilleri, Patrick; Mattia, Maurizio; Dante, Vittorio; Braun, Jochen; Del Giudice, Paolo

    2011-01-01

    We demonstrate bistable attractor dynamics in a spiking neural network implemented with neuromorphic VLSI hardware. The on-chip network consists of three interacting populations (two excitatory, one inhibitory) of leaky integrate-and-fire (LIF) neurons. One excitatory population is distinguished by strong synaptic self-excitation, which sustains meta-stable states of "high" and "low"-firing activity. Depending on the overall excitability, transitions to the "high" state may be evoked by external stimulation, or may occur spontaneously due to random activity fluctuations. In the former case, the "high" state retains a "working memory" of a stimulus until well after its release. In the latter case, "high" states remain stable for seconds, three orders of magnitude longer than the largest time-scale implemented in the circuitry. Evoked and spontaneous transitions form a continuum and may exhibit a wide range of latencies, depending on the strength of external stimulation and of recurrent synaptic excitation. In addition, we investigated "corrupted" "high" states comprising neurons of both excitatory populations. Within a "basin of attraction," the network dynamics "corrects" such states and re-establishes the prototypical "high" state. We conclude that, with effective theoretical guidance, full-fledged attractor dynamics can be realized with comparatively small populations of neuromorphic hardware neurons.

  13. Biophysical Neural Spiking, Bursting, and Excitability Dynamics in Reconfigurable Analog VLSI.

    Yu, T; Sejnowski, T J; Cauwenberghs, G

    2011-10-01

    We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm × 3 mm in 0.5 μm CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

  14. Biophysical synaptic dynamics in an analog VLSI network of Hodgkin-Huxley neurons.

    Yu, Theodore; Cauwenberghs, Gert

    2009-01-01

    We study synaptic dynamics in a biophysical network of four coupled spiking neurons implemented in an analog VLSI silicon microchip. The four neurons implement a generalized Hodgkin-Huxley model with individually configurable rate-based kinetics of opening and closing of Na+ and K+ ion channels. The twelve synapses implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The implemented models on the chip are fully configurable by 384 parameters accounting for conductances, reversal potentials, and pre/post-synaptic voltage-dependence of the channel kinetics. We describe the models and present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. The 3mm x 3mm microchip consumes 1.29 mW power making it promising for applications including neuromorphic modeling and neural prostheses.

  15. Emergent Auditory Feature Tuning in a Real-Time Neuromorphic VLSI System.

    Sheik, Sadique; Coath, Martin; Indiveri, Giacomo; Denham, Susan L; Wennekers, Thomas; Chicca, Elisabetta

    2012-01-01

    Many sounds of ecological importance, such as communication calls, are characterized by time-varying spectra. However, most neuromorphic auditory models to date have focused on distinguishing mainly static patterns, under the assumption that dynamic patterns can be learned as sequences of static ones. In contrast, the emergence of dynamic feature sensitivity through exposure to formative stimuli has been recently modeled in a network of spiking neurons based on the thalamo-cortical architecture. The proposed network models the effect of lateral and recurrent connections between cortical layers, distance-dependent axonal transmission delays, and learning in the form of Spike Timing Dependent Plasticity (STDP), which effects stimulus-driven changes in the pattern of network connectivity. In this paper we demonstrate how these principles can be efficiently implemented in neuromorphic hardware. In doing so we address two principle problems in the design of neuromorphic systems: real-time event-based asynchronous communication in multi-chip systems, and the realization in hybrid analog/digital VLSI technology of neural computational principles that we propose underlie plasticity in neural processing of dynamic stimuli. The result is a hardware neural network that learns in real-time and shows preferential responses, after exposure, to stimuli exhibiting particular spectro-temporal patterns. The availability of hardware on which the model can be implemented, makes this a significant step toward the development of adaptive, neurobiologically plausible, spike-based, artificial sensory systems.

  16. A neuromorphic VLSI device for implementing 2-D selective attention systems.

    Indiveri, G

    2001-01-01

    Selective attention is a mechanism used to sequentially select and process salient subregions of the input space, while suppressing inputs arriving from nonsalient regions. By processing small amounts of sensory information in a serial fashion, rather than attempting to process all the sensory data in parallel, this mechanism overcomes the problem of flooding limited processing capacity systems with sensory inputs. It is found in many biological systems and can be a useful engineering tool for developing artificial systems that need to process in real-time sensory data. In this paper we present a neuromorphic hardware model of a selective attention mechanism implemented on a very large scale integration (VLSI) chip, using analog circuits. The chip makes use of a spike-based representation for receiving input signals, transmitting output signals and for shifting the selection of the attended input stimulus over time. It can be interfaced to neuromorphic sensors and actuators, for implementing multichip selective attention systems. We describe the characteristics of the circuits used in the architecture and present experimental data measured from the system.

  17. A novel VLSI processor for high-rate, high resolution spectroscopy

    Pullia, Antonio; Gatti, E; Longoni, A; Buttler, W

    2000-01-01

    A novel time-variant VLSI shaper amplifier, suitable for multi-anode Silicon Drift Detectors or other multi-element solid-state X-ray detection systems, is proposed. The new read-out scheme has been conceived for demanding applications with synchrotron light sources, such as X-ray holography or EXAFS, where both high count-rates and high-energy resolutions are required. The circuit is of the linear time-variant class, accepts randomly distributed events and features: a finite-width (1-10 mu s) quasi-optimal weight function, an ultra-low-level energy discrimination (approx 150 eV), and a full compatibility for monolithic integration in CMOS technology. Its impulse response has a staircase-like shape, but the weight function (which is in general different from the impulse response in time-variant systems) is quasi trapezoidal. The operation principles of the new scheme as well as the first experimental results obtained with a prototype of the circuit are presented and discussed in the work.

  18. VLSI ARCHITECTURE FOR IMAGE COMPRESSION THROUGH ADDER MINIMIZATION TECHNIQUE AT DCT STRUCTURE

    N.R. Divya

    2014-08-01

    Full Text Available Data compression plays a vital role in multimedia devices to present the information in a succinct frame. Initially, the DCT structure is used for Image compression, which has lesser complexity and area efficient. Similarly, 2D DCT also has provided reasonable data compression, but implementation concern, it calls more multipliers and adders thus its lead to acquire more area and high power consumption. To contain an account of all, this paper has been dealt with VLSI architecture for image compression using Rom free DA based DCT (Discrete Cosine Transform structure. This technique provides high-throughput and most suitable for real-time implementation. In order to achieve this image matrix is subdivided into odd and even terms then the multiplication functions are removed by shift and add approach. Kogge_Stone_Adder techniques are proposed for obtaining a bit-wise image quality which determines the new trade-off levels as compared to the previous techniques. Overall the proposed architecture produces reduced memory, low power consumption and high throughput. MATLAB is used as a funding tool for receiving an input pixel and obtaining output image. Verilog HDL is used for implementing the design, Model Sim for simulation, Quatres II is used to synthesize and obtain details about power and area.

  19. VLSI IMPLEMENTATION OF NOVEL ROUND KEYS GENERATION SCHEME FOR CRYPTOGRAPHY APPLICATIONS BY ERROR CONTROL ALGORITHM

    B. SENTHILKUMAR

    2015-05-01

    Full Text Available A novel implementation of code based cryptography (Cryptocoding technique for multi-layer key distribution scheme is presented. VLSI chip is designed for storing information on generation of round keys. New algorithm is developed for reduced key size with optimal performance. Error Control Algorithm is employed for both generation of round keys and diffusion of non-linearity among them. Two new functions for bit inversion and its reversal are developed for cryptocoding. Probability of retrieving original key from any other round keys is reduced by diffusing nonlinear selective bit inversions on round keys. Randomized selective bit inversions are done on equal length of key bits by Round Constant Feedback Shift Register within the error correction limits of chosen code. Complexity of retrieving the original key from any other round keys is increased by optimal hardware usage. Proposed design is simulated and synthesized using VHDL coding for Spartan3E FPGA and results are shown. Comparative analysis is done between 128 bit Advanced Encryption Standard round keys and proposed round keys for showing security strength of proposed algorithm. This paper concludes that chip based multi-layer key distribution of proposed algorithm is an enhanced solution to the existing threats on cryptography algorithms.

  20. A Single Chip VLSI Implementation of a QPSK/SQPSK Demodulator for a VSAT Receiver Station

    Kwatra, S. C.; King, Brent

    1995-01-01

    This thesis presents a VLSI implementation of a QPSK/SQPSK demodulator. It is designed to be employed in a VSAT earth station that utilizes the FDMA/TDM link. A single chip architecture is used to enable this chip to be easily employed in the VSAT system. This demodulator contains lowpass filters, integrate and dump units, unique word detectors, a timing recovery unit, a phase recovery unit and a down conversion unit. The design stages start with a functional representation of the system by using the C programming language. Then it progresses into a register based representation using the VHDL language. The layout components are designed based on these VHDL models and simulated. Component generators are developed for the adder, multiplier, read-only memory and serial access memory in order to shorten the design time. These sub-components are then block routed to form the main components of the system. The main components are block routed to form the final demodulator.

  1. Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

    I. Hameem Shanavas

    2014-01-01

    Full Text Available In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design automation of very large scale integration chips. The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components like partitioning, floorplanning, placement, and routing. This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth. Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes one or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length. This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

  2. Design of 10Gbps optical encoder/decoder structure for FE-OCDMA system using SOA and opto-VLSI processors.

    Aljada, Muhsen; Hwang, Seow; Alameh, Kamal

    2008-01-21

    In this paper we propose and experimentally demonstrate a reconfigurable 10Gbps frequency-encoded (1D) encoder/decoder structure for optical code division multiple access (OCDMA). The encoder is constructed using a single semiconductor optical amplifier (SOA) and 1D reflective Opto-VLSI processor. The SOA generates broadband amplified spontaneous emission that is dynamically sliced using digital phase holograms loaded onto the Opto-VLSI processor to generate 1D codewords. The selected wavelengths are injected back into the same SOA for amplifications. The decoder is constructed using single Opto-VLSI processor only. The encoded signal can successfully be retrieved at the decoder side only when the digital phase holograms of the encoder and the decoder are matched. The system performance is measured in terms of the auto-correlation and cross-correlation functions as well as the eye diagram.

  3. Field-programmable gate array implementation of an all-digital IEEE 802.15.4-compliant transceiver

    Cornetta, Gianluca; Touhafi, Abdellah; Santos, David J.; Vázquez, José M.

    2010-12-01

    An architecture for a low-cost, low-complexity digital transceiver is presented in this article. The proposed architecture targets the IEEE 802.15.4 standard for short-range wireless personal area networks and has been implemented as a synthesisable VHDL register transfer level description. The system has been evaluated and tested using a Xilinx 90 nm Virtex-4 field-programmable gate array as the target technology. Bit error rate (BER) and error vector magnitude (EVM) have been used as the figures of merit for modem performance. Simulations show that the recommended minimum BER is achieved at E b/N 0 = 8.7 dB, whereas the EVM is 19.5%. The implemented device occupies 10% of the target FPGA and has a normalised maximum power consumption of 44 mW in transmit mode and 53 mW in receiver mode.

  4. Physico-topological methods of increasing stability of the VLSI circuit components to irradiation. Fiziko-topologhicheskie sposoby uluchsheniya radiatsionnoj stojkosti komponentov BIS

    Pereshenkov, V S [MIFI, Moscow, (Russian Federation); Shishianu, F S; Rusanovskij, V I [S. Lazo KPI, Chisinau, (Moldova, Republic of)

    1992-01-01

    The paper presents the method used and the experimental results obtained for 8-bit microprocessor irradiated with [gamma]-rays and neutrons. The correlation between the electrical and technological parameters with the irradiation ones is revealed. The influence of leakage current between devices incorporated in VLSI circuits was studied. The obtained results create the possibility to determine the technological parameters necessary for designing the circuit able to work at predetermined doses. The necessary substrate doping concentration for isolation which eliminates the leakage current between devices prevents the VLSI circuit break down was determined. (Author).

  5. The tree identify protocol of IEEE 1394 in uCRL

    C. Shankland; M.B. van der Zwaag

    1998-01-01

    textabstractWe specify the tree identify protocol of the IEEE 1394 high performance serial multimedia bus at three different levels of detail using $mu$CRL. We use the cones and foci verification technique of Groote and Springintveld to show that the descriptions are equivalent under branching

  6. A 1-GHz charge pump PLL frequency synthesizer for IEEE 1394b PHY

    Ji, J.; Liu, H.; Li, Q.

    2012-01-01

    This paper presents an implementation of multi-rate SerDes transceiver for IEEE 1394b applications. Simple and effective pre-emphasis and equalizer circuits are used at transmitter and receiver, respectively. A phase interpolator based clock and data recovery circuit with optimized linearity is a...

  7. Energy-aware path selection metric for IEEE 802.11s wireless mesh networking

    Mhlanga, MM

    2009-01-01

    Full Text Available The IEEE 802.11s working group has commenced activities, which would lead to the development of a standard for wireless mesh networks (WMNs). The draft of 802.11s introduces a new path selection metric called airtime link metric. However...

  8. Energy-aware path selection metric for IEEE 802.11s wireless mesh networking

    Mhlanga, MM

    2009-08-01

    Full Text Available The IEEE 802.11s working group has commenced activities, which would lead to the development of a standard for wireless mesh networks (WMNs). The draft of 802.11s introduces a new path selection metric called airtime link metric. However...

  9. IEEE 8023 ethernet, current status and future prospects at the LHC

    Dobinson, Robert W; Haas, S; Martin, B; Le Vine, M J; Saka, F

    2000-01-01

    The status of the IEEE 802.3 standard is reviewed and prospects for the future, including the new 10 Gigabit version of Ethernet, are discussed. The relevance of Ethernet for experiments at the CERN Large Hadron Collider is considered, with emphasis on on-line applications and areas which are technically challenging. 8 Refs.

  10. IEEE 802.3 Ethernet, Current Status and Future Prospects at the LHC

    Dobinson, Robert W; Haas, S W; Martin, B; Le Vine, M J; Saka, F

    2000-01-01

    The status of the IEEE 802.3 standard is reviewed and prospects for the future, including the new 10 Gigabit version of Ethernet, are discussed. The relevance of Ethernet for experiments at the CERN Large Hadron Collider is considered, with emphasis on on-line applications and areas which are technically challenging.

  11. Performance Evaluations for IEEE 802.15.4-based IoT Smart Home Solution

    Nga Dinh

    2016-09-01

    Full Text Available The Internet of Things (IoT is going to be a market-changing force for a variety of real-time applications such as e-healthcare, home automation, environmental monitoring, and industrial automation. Low power wireless communication protocols offering long lifetime and high reliability such as the IEEE 802.15.4 standard have been a key enabling technology for IoT deployments and are deployed for home automation recently. The issues of the IEEE 802.15.4 networks have moved from theory to real world deployments. The work presented herein intends to demonstrate the use of the IEEE 802.15.4 standard in recent IoT commercial products for smart home applications: the Smart Home Starter Kit. The contributions of the paper are twofold. First, the paper presents how the IEEE 802.15.4 standard is employed in Smart Home Starter Kit. In particular, network topology, network operations, and data transfer mode are investigated. Second, network performance metrics such as end-to-end (E2E delay and frame reception ratio (FRR are evaluated by experiments. In addition, the paper discusses several directions for future improvements of home automation commercial products.

  12. The IEEE-SA patent policy update under the lens of EU competition law

    Kanevskaia, Olia; Zingales, Nicolo

    2016-01-01

    In 2015, the Institute of Electrical and Electronics Engineers (IEEE) Standardization Association made some controversial changes to its patent policy. The changes include a recommended method of calculation of FRAND royalty rates, and a request to members holding a standard essential patent (SEP)

  13. 0011-0030.IEEE 754: 64 Bit Double Precision FloatsThis.pdf | 01 ...

    Home; public; Volumes; reso; 021; 01; 0011-0030.IEEE 754: 64 Bit Double Precision FloatsThis.pdf. 404! error. The page your are looking for can not be found! Please check the link or use the navigation bar at the top. YouTube; Twitter; Facebook; Blog. Academy News. IAS Logo. 29th Mid-year meeting. Posted on 19 ...

  14. Evaluation of the Effects of Hidden Node Problems in IEEE 802.15.7 Uplink Performance.

    Ley-Bosch, Carlos; Alonso-González, Itziar; Sánchez-Rodríguez, David; Ramírez-Casañas, Carlos

    2016-02-06

    In the last few years, the increasing use of LEDs in illumination systems has been conducted due to the emergence of Visible Light Communication (VLC) technologies, in which data communication is performed by transmitting through the visible band of the electromagnetic spectrum. In 2011, the Institute of Electrical and Electronics Engineers (IEEE) published the IEEE 802.15.7 standard for Wireless Personal Area Networks based on VLC. Due to limitations in the coverage of the transmitted signal, wireless networks can suffer from the hidden node problems, when there are nodes in the network whose transmissions are not detected by other nodes. This problem can cause an important degradation in communications when they are made by means of the Carrier Sense Multiple Access with Collision Avoidance (CSMA/CA) access control method, which is used in IEEE 802.15.7 This research work evaluates the effects of the hidden node problem in the performance of the IEEE 802.15.7 standard We implement a simulator and analyze VLC performance in terms of parameters like end-to-end goodput and message loss rate. As part of this research work, a solution to the hidden node problem is proposed, based on the use of idle patterns defined in the standard. Idle patterns are sent by the network coordinator node to communicate to the other nodes that there is an ongoing transmission. The validity of the proposed solution is demonstrated with simulation results.

  15. Adaptive Radio Resource Allocation in Hierarchical QoS Scheduling for IEEE 802.16 Systems

    Wang, Hua; Dittmann, Lars

    2007-01-01

    Future mobile communication systems such as IEEE 802.16 are expected to deliver a variety of multimedia services with diverse QoS requirements. To guarantee the QoS provision, appropriate scheduler architecture and scheduling algorithms have to be carefully designed. In this paper, we propose...

  16. Evaluation of H.264/AVC over IEEE 802.11p vehicular networks

    Rozas-Ramallal, Ismael; Fernández-Caramés, Tiago M.; Dapena, Adriana; García-Naya, José Antonio

    2013-12-01

    The capacity of vehicular networks to offer non-safety services, like infotainment applications or the exchange of multimedia information between vehicles, have attracted a great deal of attention to the field of Intelligent Transport Systems (ITS). In particular, in this article we focus our attention on IEEE 802.11p which defines enhancements to IEEE 802.11 required to support ITS applications. We present an FPGA-based testbed developed to evaluate H.264/AVC (Advanced Video Coding) video transmission over vehicular networks. The testbed covers some of the most common situations in vehicle-to-vehicle and roadside-to-vehicle communications and it is highly flexible, allowing the performance evaluation of different vehicular standard configurations. We also show several experimental results to illustrate the quality obtained when H.264/AVC encoded video is transmitted over IEEE 802.11p networks. The quality is measured considering two important parameters: the percentage of recovered group of pictures and the frame quality. In order to improve performance, we propose to substitute the convolutional channel encoder used in IEEE 802.11p for a low-density parity-check code encoder. In addition, we suggest a simple strategy to decide the optimum number of iterations needed to decode each packet received.

  17. IEEE Conference Record of 1980 Fourteenth Pulse Power Modulator Symposium, 3-5 June 1980.

    1980-01-01

    Capacitor Discharges, Proc IEEE 113, p. able operation on Nova we are examing alter- 1549 (1966). nate switch gas (Ar:N 2 :SF 6 ) and electrode material...VOLTTA-KILOVOLTS PLATE VO LTAM --LOVLTS Figure 8. Constant Current Curve for the X2097U Figure 11. Constant Current Curve for the X2097V at 2000 Volt

  18. Oldest Packet Drop (OPD): a Buffering Mechanism for Beaconing in IEEE 802.11p VANETs

    van Eenennaam, Martijn; Hendriks, Luuk; Karagiannis, Georgios; Heijenk, Geert

    2011-01-01

    The IEEE 802.11p MAC technology can be used to provide connectivity for real-time vehicle control known as Cooperative Adaptive Cruise Control. Due to the real-time nature of this system, it is paramount the delay of the received information is as small as possible. This paper researches the Oldest

  19. A Comprehensive Taxonomy and Analysis of IEEE 802.15.4 Attacks

    Yasmin M. Amin

    2016-01-01

    Full Text Available The IEEE 802.15.4 standard has been established as the dominant enabling technology for Wireless Sensor Networks (WSNs. With the proliferation of security-sensitive applications involving WSNs, WSN security has become a topic of great significance. In comparison with traditional wired and wireless networks, WSNs possess additional vulnerabilities which present opportunities for attackers to launch novel and more complicated attacks against such networks. For this reason, a thorough investigation of attacks against WSNs is required. This paper provides a single unified survey that dissects all IEEE 802.15.4 PHY and MAC layer attacks known to date. While the majority of existing references investigate the motive and behavior of each attack separately, this survey classifies the attacks according to clear metrics within the paper and addresses the interrelationships and differences between the attacks following their classification. The authors’ opinions and comments regarding the placement of the attacks within the defined classifications are also provided. A comparative analysis between the classified attacks is then performed with respect to a set of defined evaluation criteria. The first half of this paper addresses attacks on the IEEE 802.15.4 PHY layer, whereas the second half of the paper addresses IEEE 802.15.4 MAC layer attacks.

  20. Interference Measurements in IEEE 802.11 Communication Links Due to Different Types of Interference Sources

    van Bloem, J.W.H.; Schiphorst, Roelof; Kluwer, Taco; Slump, Cornelis H.

    2012-01-01

    The number of wireless devices (smartphones, laptops, sensors) that use the 2.4 GHz ISM band is rapidly increasing. The most common communication system in this band is Wi-Fi (IEEE 802.11b/g/n). For that reason coexistence between Wi-Fi and other systems becomes more and more important. In this

  1. Proceedings of the 1988 IEEE international conference on robotics and automation. Volume 1

    Anon.

    1988-01-01

    These proceedings compile the papers presented at the international conference (1988) sponsored by IEEE Council on ''Robotics and Automation''. The subjects discussed were: automation and robots of nuclear power stations; algorithms of multiprocessors; parallel processing and computer architecture; and U.S. DOE research programs on nuclear power plants

  2. Performance Analysis of Non-saturated IEEE 802.11 DCF Networks

    Zhai, Linbo; Zhang, Xiaomin; Xie, Gang

    This letter presents a model with queueing theory to analyze the performance of non-saturated IEEE 802.11 DCF networks. We use the closed queueing network model and derive an approximate representation of throughput which can reveal the relationship between the throughput and the total offered load under finite traffic load conditions. The accuracy of the model is verified by extensive simulations.

  3. IEEE 802.11 Wireless LANs: Performance Analysis and Protocol Refinement

    Chatzimisios P.

    2005-01-01

    Full Text Available The IEEE 802.11 protocol is emerging as a widely used standard and has become the most mature technology for wireless local area networks (WLANs. In this paper, we focus on the tuning of the IEEE 802.11 protocol parameters taking into consideration, in addition to throughput efficiency, performance metrics such as the average packet delay, the probability of a packet being discarded when it reaches the maximum retransmission limit, the average time to drop a packet, and the packet interarrival time. We present an analysis, which has been validated by simulation that is based on a Markov chain model commonly used in the literature. We further study the improvement on these performance metrics by employing suitable protocol parameters according to the specific communication needs of the IEEE 802.11 protocol for both basic access and RTS/CTS access schemes. We show that the use of a higher initial contention window size does not considerably degrade performance in small networks and performs significantly better in any other scenario. Moreover, we conclude that the combination of a lower maximum contention window size and a higher retry limit considerably improves performance. Results indicate that the appropriate adjustment of the protocol parameters enhances performance and improves the services that the IEEE 802.11 protocol provides to various communication applications.

  4. Performance characterization of the IEEE 802.11 signal transmission over a multimode fiber PON

    Maksymiuk, L.; Siuzdak, J.

    2014-11-01

    In this paper there are presented measurements concerning performance analysis of the IEEE 802.11 signal distribution over multimode fiber based passive optical network. In the paper there are addressed three main sources of impairments: modal noise, frequency response fluctuation of the multimode fiber and non-linear distortion of the signal in the receiver.

  5. Multitemporal Very High Resolution From Space: Outcome of the 2016 IEEE GRSS Data Fusion Contest

    Mou, L.; Zhu, X.; Vakalopoulou, M.; Karantzalos, K.; Paragios, N.; Saux, Le B.; Moser, G.; Tuia, D.

    2017-01-01

    In this paper, the scientific outcomes of the 2016 Data Fusion Contest organized by the Image Analysis and Data Fusion Technical Committee of the IEEE Geoscience and Remote Sensing Society are discussed. The 2016 Contest was an open topic competition based on a multitemporal and multimodal dataset,

  6. Outdoor Long-Range WLANs : A Lesson for IEEE 802.11ah

    Aust, Stefan; Venkatesha Prasad, R.; Niemegeers, Ignas G M M

    2015-01-01

    Several service applications have been reported by many who proposed the use of wireless LANs (WLANs) over a wide variety of outdoor deployments. In particular, the upcoming IEEE 802.11ah WLAN protocol will enable a longer transmission range between WLAN access points (APs) and stations (STAs) up to

  7. Incorporating antenna beamswitching technique into drivers for IEEE802.11 WLAN devices

    Mofolo, M

    2015-11-23

    Full Text Available the beamswitching technique for switched parasitic array (SPA) and electronically steerable parasitic array radiator (ESPAR) antennas in the drivers for IEEE802.11 WLAN devices. The modifications of the open source drivers (ath5k and ath9k) to enable real...

  8. Digital VLSI systems design a design manual for implementation of projects on FPGAs and ASICs using Verilog

    Ramachandran, S

    2007-01-01

    Digital VLSI Systems Design is written for an advanced level course using Verilog and is meant for undergraduates, graduates and research scholars of Electrical, Electronics, Embedded Systems, Computer Engineering and interdisciplinary departments such as Bio Medical, Mechanical, Information Technology, Physics, etc. It serves as a reference design manual for practicing engineers and researchers as well. Diligent freelance readers and consultants may also start using this book with ease. The book presents new material and theory as well as synthesis of recent work with complete Project Designs

  9. A versatile trigger and synchronization module with IEEE1588 capabilities and EPICS support

    Lopez, J.M.; Ruiz, M.; Borrego, J.; Arcas, G. de; Barrera, E.; Vega, J.

    2010-01-01

    Event timing and synchronization are two key aspects to improve in the implementation of distributed data acquisition (dDAQ) systems such as the ones used in fusion experiments. It is also of great importance the integration of dDAQ in control and measurement networks. This paper analyzes the applicability of the IEEE1588 and EPICS standards to solve these problems, and presents a hardware module implementation based in both of them that allow adding these functionalities to any DAQ. The IEEE1588 standard facilitates the integration of event timing and synchronization mechanisms in distributed data acquisition systems based on IEEE 803.3 (Ethernet). An optimal implementation of such system requires the use of network interface devices which include specific hardware resources devoted to the IEE1588 functionalities. Unfortunately, this is not the approach followed in most of the large number of applications available nowadays. Therefore, most solutions are based in software and use standard hardware network interfaces. This paper presents the development of a hardware module (GI2E) with IEEE1588 capabilities which includes USB, RS232, RS485 and CAN interfaces. This permits to integrate any DAQ element that uses these interfaces in dDAQ systems in an efficient and simple way. The module has been developed with Motorola's Coldfire MCF5234 processor and National Semiconductors's PHY DP83640T, providing it with the possibility to implement the PTP protocol of IEEE1588 by hardware, and therefore increasing its performance over other implementations based in software. To facilitate the integration of the dDAQ system in control and measurement networks the module includes a basic Input/Output Controller (IOC) functionality of the Experimental Physics and Industrial Control System (EPICS) architecture. The paper discusses the implementation details of this module and presents its applications in advanced dDAQ applications in the fusion community.

  10. Regulation on control systems tests

    Grau, J.; Navarro, J.M.

    1978-01-01

    Requirements under regulation applicable to the testing of control systems and controlled equipments in the case of USA nuclear projects are examined. They are reviewed, in particular, the following standards and criteria: 10 Code of Federal Regulations 50, Appendix A, General Design Criteria 20 and 21; IEEE Standards 279 and 308; IEEE Standard 338; US Regulatory Guides 1.22 and 1.118.(J.E.de C.)

  11. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates

    T. Kalavathi Devi

    2015-01-01

    Full Text Available Convolutional codes are comprehensively used as Forward Error Correction (FEC codes in digital communication systems. For decoding of convolutional codes at the receiver end, Viterbi decoder is often used to have high priority. This decoder meets the demand of high speed and low power. At present, the design of a competent system in Very Large Scale Integration (VLSI technology requires these VLSI parameters to be finely defined. The proposed asynchronous method focuses on reducing the power consumption of Viterbi decoder for various constraint lengths using asynchronous modules. The asynchronous designs are based on commonly used Quasi Delay Insensitive (QDI templates, namely, Precharge Half Buffer (PCHB and Weak Conditioned Half Buffer (WCHB. The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC. The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.

  12. Performance Analysis of the IEEE 802.11p Multichannel MAC Protocol in Vehicular Ad Hoc Networks.

    Song, Caixia

    2017-12-12

    Vehicular Ad Hoc Networks (VANETs) employ multichannel to provide a variety of safety and non-safety applications, based on the IEEE 802.11p and IEEE 1609.4 protocols. The safety applications require timely and reliable transmissions, while the non-safety applications require efficient and high throughput. In the IEEE 1609.4 protocol, operating interval is divided into alternating Control Channel (CCH) interval and Service Channel (SCH) interval with an identical length. During the CCH interval, nodes transmit safety-related messages and control messages, and Enhanced Distributed Channel Access (EDCA) mechanism is employed to allow four Access Categories (ACs) within a station with different priorities according to their criticality for the vehicle's safety. During the SCH interval, the non-safety massages are transmitted. An analytical model is proposed in this paper to evaluate performance, reliability and efficiency of the IEEE 802.11p and IEEE 1609.4 protocols. The proposed model improves the existing work by taking serval aspects and the character of multichannel switching into design consideration. Extensive performance evaluations based on analysis and simulation help to validate the accuracy of the proposed model and analyze the capabilities and limitations of the IEEE 802.11p and IEEE 1609.4 protocols, and enhancement suggestions are given.

  13. IEEE Std 317-1972: IEEE standard for electric penetration assemblies in containment structures for nuclear power generating stations

    Anon.

    1992-01-01

    This standard prescribes the mechanical, electrical, and test requirements for the design, construction, and installation of electric penetration assemblies in containment structures for stationary nuclear power generating stations. The electric conductor and insulation characteristics of external circuits which connect to penetration assemblies are beyond the scope of these criteria. If there should be any conflict between this standard and those documents referenced herein, this standard shall take precedence over the referenced documents

  14. Hybrid Polling Method for Direct Link Communication for IEEE 802.11 Wireless LANs

    Woo-Yong Choi

    2008-10-01

    Full Text Available The direct link communication between STAtions (STAs is one of the techniques to improve the MAC performance of IEEE 802.11 infrastructure networks. For the efficient direct link communication, in the literature, the simultaneous polling method was proposed to allow the multiple direct data communication to be performed simultaneously. However, the efficiency of the simultaneous polling method is affected by the interference condition. To alleviate the problem of the lower polling efficiency with the larger interference range, the hybrid polling method is proposed for the direct link communication between STAs in IEEE 802.11 infrastructure networks. By the proposed polling method, we can integrate the sequential and simultaneous polling methods properly according to the interference condition. Numerical examples are also presented to show the medium access control (MAC performance improvement by the proposed polling method.

  15. 2011 IEEE Visualization Contest Winner: Visualizing Unsteady Vortical Behavior of a Centrifugal Pump

    Otto, Mathias

    2012-09-01

    In the 2011 IEEE Visualization Contest, the dataset represented a high-resolution simulation of a centrifugal pump operating below optimal speed. The goal was to find suitable visualization techniques to identify regions of rotating stall that impede the pump\\'s effectiveness. The winning entry split analysis of the pump into three parts based on the pump\\'s functional behavior. It then applied local and integration-based methods to communicate the unsteady flow behavior in different regions of the dataset. This research formed the basis for a comparison of common vortex extractors and more recent methods. In particular, integration-based methods (separation measures, accumulated scalar fields, particle path lines, and advection textures) are well suited to capture the complex time-dependent flow behavior. This video (http://youtu.be/ oD7QuabY0oU) shows simulations of unsteady flow in a centrifugal pump. © 2012 IEEE.

  16. The Exploration of Network Coding in IEEE 802.15.4 Networks

    Deze Zeng

    2011-01-01

    communication protocol should be energy efficient. The IEEE 802.15.4 is designed as a standard protocol for low power, low data rate, low complexity, and short range connections in WPANs. The standard supports allocating several numbers of collision-free guarantee time slots (GTSs within a superframe for some time-critical transmissions. Recently, COPE was proposed as a promising network coding architecture to essentially improve the throughput of wireless networks. In this paper, we exploit the network coding technique at coordinators to improve energy efficiency of the WPAN. Some related practical issues, such as GTS allocation and multicast, are also discussed in order to exploit the network coding opportunities efficiently. Since the coding opportunities are mostly exploited, our proposal achieves both higher energy efficiency and throughput performance than the original IEEE 802.15.4.

  17. The IEEE 1355 Standard. Developments, performance and application in high energy physics

    Haas, S.

    1998-12-01

    The data acquisition systems of the next generation High Energy Physics experiments at the Large Hadron Collider (LHC) at CERN will rely on high-speed point-to-point links and switching networks for their higher level trigger and event building systems. This thesis provides a detailed evaluation of the DS-Link and switch technology, which is based on the IEEE 1355 standard for Heterogeneous Interconnect (HIC). The DS-Link is a bidirectional point-to-point serial interconnect, operating at speeds up to 200 MBaud. The objective of this thesis was to study the performance of the IEEE 1355 link and switch technology and to demonstrate that switching networks using this technology would scale to meet the requirements of the High Energy Physics applications

  18. VARNOST BREZŽIČNIH OMREŽIJ PO STANDARDU IEEE 802.11

    Štumberger, Matej

    2013-01-01

    Diplomska naloga se osredotoča na problem varovanja brezžičnih omrežij, zasnovanih po standardu IEEE 802.11. Opisano je združenje IEEE in njihova specifikacija standardov z oznako 802, prav tako pa so opisani tudi standardi, protokoli in tehnike varovanja in zaščite omrežij, ki delujejo po tej specifikaciji. Predstavljeno je tudi trenutno stanje varnosti brezžičnih omrežij na področju mesta Ptuj, opisani in prikazani pa so tudi različni pristopi za zlorabo brezžičnih omrežij, skupaj s program...

  19. Design Optimization of Cyber-Physical Distributed Systems using IEEE Time-sensitive Networks (TSN)

    Pop, Paul; Lander Raagaard, Michael; Craciunas, Silviu S.

    2016-01-01

    to the optimization of distributed cyber-physical systems using real-time Ethernet for communication. Then, we formulate two novel optimization problems related to the scheduling and routing of TT and AVB traffic in TSN. Thus, we consider that we know the topology of the network as well as the set of TT and AVB flows......In this paper we are interested in safety-critical real-time applications implemented on distributed architectures supporting the Time-SensitiveNetworking (TSN) standard. The ongoing standardization of TSN is an IEEE effort to bring deterministic real-time capabilities into the IEEE 802.1 Ethernet...... standard supporting safety-critical systems and guaranteed Quality-of-Service. TSN will support Time-Triggered (TT) communication based on schedule tables, Audio-Video-Bridging (AVB) flows with bounded end-to-end latency as well as Best-Effort messages. We first present a survey of research related...

  20. Transient Stability Improvement of IEEE 9 Bus System Using Power World Simulator

    Kaur Ramandeep

    2016-01-01

    Full Text Available The improvement of transient stability of power system was one of the most challenging research areas in power engineer.The main aim of this paper was transient stability analysis and improvement of IEEE 9 bus system. These studies were computed using POWER WORLD SIMULATOR. The IEEE 9 bus system was modelled in power world simulator and load flow studies were performed to determine pre-fault conditions in the system using Newton-Raphson method. The transient stability analysis was carried out using Runga method during three-phase balanced fault. For the improvement transient stability, the general methods adopted were fast acting exciters, FACT devices and addition of parallel transmission line. These techniques play an important role in improving the transient stability, increasing transmission capacity and damping low frequency oscillations.

  1. Integration of IEEE 1451 and HL7 exchanging information for patients' sensor data.

    Kim, Wooshik; Lim, Suyoung; Ahn, Jinsoo; Nah, Jiyoung; Kim, Namhyun

    2010-12-01

    HL7 (Health Level 7) is a standard developed for exchanging incompatible healthcare information generated from programs or devices among heterogenous medical information systems. At present, HL7 is growing as a global standard. However, the HL7 standard does not support effective methods for treating data from various medical sensors, especially from mobile sensors. As ubiquitous systems are growing, HL7 must communicate with various medical transducers. In the area of sensor fields, IEEE 1451 is a group of standards for controlling transducers and for communicating data from/to various transducers. In this paper, we present the possibility of interoperability between the two standards, i.e., HL7 and IEEE 1451. After we present a method to integrate them and show the preliminary results of this approach.

  2. A note on bound constraints handling for the IEEE CEC'05 benchmark function suite.

    Liao, Tianjun; Molina, Daniel; de Oca, Marco A Montes; Stützle, Thomas

    2014-01-01

    The benchmark functions and some of the algorithms proposed for the special session on real parameter optimization of the 2005 IEEE Congress on Evolutionary Computation (CEC'05) have played and still play an important role in the assessment of the state of the art in continuous optimization. In this article, we show that if bound constraints are not enforced for the final reported solutions, state-of-the-art algorithms produce infeasible best candidate solutions for the majority of functions of the IEEE CEC'05 benchmark function suite. This occurs even though the optima of the CEC'05 functions are within the specified bounds. This phenomenon has important implications on algorithm comparisons, and therefore on algorithm designs. This article's goal is to draw the attention of the community to the fact that some authors might have drawn wrong conclusions from experiments using the CEC'05 problems.

  3. A Novel IEEE 802.15.4e DSME MAC for Wireless Sensor Networks.

    Sahoo, Prasan Kumar; Pattanaik, Sudhir Ranjan; Wu, Shih-Lin

    2017-01-16

    IEEE 802.15.4e standard proposes Deterministic and Synchronous Multichannel Extension (DSME) mode for wireless sensor networks (WSNs) to support industrial, commercial and health care applications. In this paper, a new channel access scheme and beacon scheduling schemes are designed for the IEEE 802.15.4e enabled WSNs in star topology to reduce the network discovery time and energy consumption. In addition, a new dynamic guaranteed retransmission slot allocation scheme is designed for devices with the failure Guaranteed Time Slot (GTS) transmission to reduce the retransmission delay. To evaluate our schemes, analytical models are designed to analyze the performance of WSNs in terms of reliability, delay, throughput and energy consumption. Our schemes are validated with simulation and analytical results and are observed that simulation results well match with the analytical one. The evaluated results of our designed schemes can improve the reliability, throughput, delay, and energy consumptions significantly.

  4. A Fast MAC-Layer Handover for an IEEE 802.16e-Based WMAN

    Ray, Sayan K.; Pawlikowski, Krzysztof; Sirisena, Harsha

    We propose a modification of the IEEE 802.16e hard handover (HHO) procedure, which significantly reduces the handover latency constraint of the original HHO procedure in IEEE 802.16e networks. It allows a better handling of the delay-sensitive traffic by avoiding unnecessary time-consuming scanning and synchronization activity as well as simplifies the network re-entry procedure. With the help of the backhaul network, it reduces the number of control messages in the original handover policy, making the handover latency acceptable also for real-time streaming traffic. Preliminary performance evaluation studies show that the modified handover procedure is able to reduce the total handover latency by about 50%.

  5. A network architecture for precision formation flying using the IEEE 802.11 MAC Protocol

    Clare, Loren P.; Gao, Jay L.; Jennings, Esther H.; Okino, Clayton

    2005-01-01

    Precision Formation Flying missions involve the tracking and maintenance of spacecraft in a desired geometric formation. The strong coupling of spacecraft in formation flying control requires inter-spacecraft communication to exchange information. In this paper, we present a network architecture that supports PFF control, from the initial random deployment phase to the final formation. We show that a suitable MAC layer for the application protocol is IEEE's 802.11 MAC protocol. IEEE 802.11 MAC has two modes of operations: DCF and PCF. We show that DCF is suitable for the initial deployment phase while switching to PCF when the spacecraft are in formation improves jitter and throughput. We also consider the effect of routing on protocol performance and suggest when it is profitable to turn off route discovery to achieve better network performance.

  6. Capacity Evaluation for IEEE 802.16e Mobile WiMAX

    Chakchai So-In

    2010-01-01

    Full Text Available We present a simple analytical method for capacity evaluation of IEEE 802.16e Mobile WiMAX networks. Various overheads that impact the capacity are explained and methods to reduce these overheads are also presented. The advantage of a simple model is that the effect of each decision and sensitivity to various parameters can be seen easily. We illustrate the model by estimating the capacity for three sample applications—Mobile TV, VoIP, and data. The analysis process helps explain various features of IEEE 802.16e Mobile WiMAX. It is shown that proper use of overhead reducing mechanisms and proper scheduling can make an order of magnitude difference in performance. This capacity evaluation method can also be used for validation of simulation models.

  7. Contributions to the 14th IEEE/NPSS Symposium on fusion engineering

    Navarro, A.P.; Almoguera, L.; Alonso Gozalo, J.; Alonso Candenas, J.; Blaumoser, M.

    1992-01-01

    Three communications about the TJ-II device, under construction at CIEMAT with preferential support from EURATOM, were presented to the 14th IEEE/NPSS Symposium on Fusion Engineering and are collected in this report. The first one describes in detail the device and its present status of design and construction. The remaining two deal with the two most critical components of the project: the vacuum vessel and the central hard conductor. (author) 16 fig. 16 ref

  8. Utilizing reliability concepts in the development of IEEE recommended good practices for nuclear plant maintenance

    Gradin, L.P.

    1986-01-01

    This paper presents information describing the concern for nuclear power plant electrical equipment maintenance and the IEEE Nuclear Power Engineering Committee's method to address that concern. That method includes the creation of Working Group 3.3, ''Maintenance Good Practices'' which is developing specific maintenance good practice documents, supporting technical information exchange, and providing a vehicle to promote practices which can reduce cost and enhance plant safety. The foundation for that effort is the utilization of Reliability concepts

  9. Practical support for Lean Six Sigma software process definition using IEEE software engineering standards

    Land, Susan K; Walz, John W

    2012-01-01

    Practical Support for Lean Six Sigma Software Process Definition: Using IEEE Software Engineering Standards addresses the task of meeting the specific documentation requirements in support of Lean Six Sigma. This book provides a set of templates supporting the documentation required for basic software project control and management and covers the integration of these templates for their entire product development life cycle. Find detailed documentation guidance in the form of organizational policy descriptions, integrated set of deployable document templates, artifacts required in suppo

  10. [Mobile Health: IEEE Standard for Wearable Cuffless Blood Pressure Measuring Devices].

    Zhou, Xia; Wu, Wenli; Bao, Shudi

    2015-07-01

    IEEE Std 1708-2014 breaks through the traditional standards of cuff based blood pressure measuring devices and establishes a normative definition of wearable cuffless blood pressure measuring devices and the objective performance evaluation of this kind of devices. This study firstly introduces the background of the new standard. Then, the standard details will be described, and the impact of cuffless blood pressure measuring devices with the new standard on manufacturers and end users will be addressed.

  11. IEEE guide for general principles of reliability analysis of nuclear power generating station protection systems

    Anon.

    1975-01-01

    Presented is the Institute of Electrical and Electronics Engineers, Inc. (IEEE) guide for general principles of reliability analysis of nuclear power generating station protection systems. The document has been prepared to provide the basic principles needed to conduct a reliability analysis of protection systems. Included is information on qualitative and quantitative analysis, guides for failure data acquisition and use, and guide for establishment of intervals

  12. IEEE standard for qualifying class IE equipment for nuclear power generating stations

    Anon.

    1974-01-01

    The Institute of Electrical and Electrical Engineers, Inc. (IEEE) standards for electrical equipment (Class IE) for nuclear power generating stations are given. The standards are to provide guidance for demonstrating and documenting the adequacy of electric equipment used in all Class IE and interface systems. Representative in containment design basis event conditions for the principal reactor types are included in the appendixes for guidance in enviromental simulation

  13. An improved IEEE 802.11 protocol for reliable data transmission in power distribution fault diagnosis

    Campoccia, F.; Di Silvestre, M.L.; Sanseverino, E.R.; Zizzo, G. [Palermo Univ., Palermo (Italy)

    2010-10-15

    In power systems, on-line transmission between local units and the central unit can be done by means of power line communications or wireless technology. During an electrical fault, the reliability of the distribution system depends on the security of the timely protective and restorative actions on the network. This paper focused on the WiFi system because of its economy and ease of installation. However, WiFi systems are typically managed by the IEEE 802.11 protocol, which is not reliable in terms of security in data communication. In WiFi networks, data is divided into packets and sent in succession to reduce errors within the radio channel. The IEEE 802.11 protocol has high probability for loss of packets or delay in their transmission. In order to ensure the reliability of data transmission times between two terminal units connected by WiFi stations, a new protocol was derived by modifying the IEEE 802.11. The improvements of the new protocol were highlighted and its capability for the diagnostic service was verified. The modified protocol eliminates the danger of collisions between packets and optimizes the transmission time for sending information. 6 refs., 7 tabs., 8 figs.

  14. FPGA implementation cost and performance evaluation of IEEE 802.11 protocol encryption security schemes

    Sklavos, N.; Selimis, G.; Koufopavlou, O.

    2005-01-01

    The explosive growth of internet and consumer demand for mobility has fuelled the exponential growth of wireless communications and networks. Mobile users want access to services and information, from both internet and personal devices, from a range of locations without the use of a cable medium. IEEE 802.11 is one of the most widely used wireless standards of our days. The amount of access and mobility into wireless networks requires a security infrastructure that protects communication within that network. The security of this protocol is based on the wired equivalent privacy (WEP) scheme. Currently, all the IEEE 802.11 market products support WEP. But recently, the 802.11i working group introduced the advanced encryption standard (AES), as the security scheme for the future IEEE 802.11 applications. In this paper, the hardware integrations of WEP and AES are studied. A field programmable gate array (FPGA) device has been used as the hardware implementation platform, for a fair comparison between the two security schemes. Measurements for the FPGA implementation cost, operating frequency, power consumption and performance are given.

  15. Performance Evaluation of Beacon-Enabled Mode for IEEE 802.15.4 Wireless Sensor Network

    M. Udin Harun Al Rasyid

    2013-12-01

    Full Text Available IEEE 802.15.5 standard support structure of star and peer-to-peer network formation. Strating from these, the cluster tree network can be built as a special case of peer-to-peer network to increse coverage area. In this paper, we provide an performance evaluation of beacon- enabled mode for IEEE 802.15.4 wireless sensor network on star and cluster topology in order to get the maximum result to apply the appropriate topology model as needed. We conduct analysis on each topology model by using the numbers of nodes from 10 nodes to 100 nodes to analyze throughput, delay, energy consumption, and probability success packet by using NS2 simulator. The simulation results show that the throughput and the probability of success packet of cluster topology are higher than that of star topology, and the energy consumption of cluster topology is lesser than that of star topology. However, cluster topology increases the delay more than star topology. Keywords: IEEE 802.15.4, wireless sensor network, beacon-enabled mode, topology, csma/ca

  16. Interoperability in digital electrocardiography: harmonization of ISO/IEEE x73-PHD and SCP-ECG.

    Trigo, Jesús D; Chiarugi, Franco; Alesanco, Alvaro; Martínez-Espronceda, Miguel; Serrano, Luis; Chronaki, Catherine E; Escayola, Javier; Martínez, Ignacio; García, José

    2010-11-01

    The ISO/IEEE 11073 (x73) family of standards is a reference frame for medical device interoperability. A draft for an ECG device specialization (ISO/IEEE 11073-10406-d02) has already been presented to the Personal Health Device (PHD) Working Group, and the Standard Communications Protocol for Computer-Assisted ElectroCardioGraphy (SCP-ECG) Standard for short-term diagnostic ECGs (EN1064:2005+A1:2007) has recently been approved as part of the x73 family (ISO 11073-91064:2009). These factors suggest the coordinated use of these two standards in foreseeable telecardiology environments, and hence the need to harmonize them. Such harmonization is the subject of this paper. Thus, a mapping of the mandatory attributes defined in the second draft of the ISO/IEEE 11073-10406-d02 and the minimum SCP-ECG fields is presented, and various other capabilities of the SCP-ECG Standard (such as the messaging part) are also analyzed from an x73-PHD point of view. As a result, this paper addresses and analyzes the implications of some inconsistencies in the coordinated use of these two standards. Finally, a proof-of-concept implementation of the draft x73-PHD ECG device specialization is presented, along with the conversion from x73-PHD to SCP-ECG. This paper, therefore, provides recommendations for future implementations of telecardiology systems that are compliant with both x73-PHD and SCP-ECG.

  17. IEEE recommended practices for seismic qualification of Class 1E equipment for nuclear power generating stations

    Anon.

    1975-01-01

    The IEEE has developed this document to provide direction for developing programs to seismically qualify Class 1E equipment for nuclear power generating stations. It supplements IEEE Std 323-1974, IEEE Standard for Qualifying Class 1E Equipment for Nuclear Power Generating Stations, which describes the basic requirements for equipment qualification. The Class 1E equipment to be qualified by produres or standards established by this document are of many forms, characteristics, and materials; therefore, the document presents many acceptable methods with the intent of permitting the user to make a judicious selection from among the various options. In making such a selection, the user should choose those that best meet a particular equipment's requirements. Further, in using this document as a specification for the purchase of equipment, the many options should also be recognized and the document invoked accordingly. It is recommended that the need for specific standards for the seismic qualifiction of particular kinds of equipment be evaluated by those responsible for such documents and that consideration be given to the application of particular methods from these documents which are most suitable

  18. IEEE P1596, a scalable coherent interface for GigaByte/sec multiprocessor applications

    Gustavson, D.B.

    1988-11-01

    IEEE P1596, the Scalable Coherent Interface (formerly known as SuperBus) is based on experience gained during the development of Fastbus (IEEE 960), Futurebus (IEEE 896.1) and other modern 32-bit buses. SCI goals include a minimum bandwidth of 1 GByte/sec per processor; efficient support of a coherent distributed-cache image of shared memory; and support for segmentation, bus repeaters and general switched interconnections like Banyan, Omega, or full crossbar networks. To achieve these ambitious goals, SCI must sacrifice the immediate handshake characteristic of the present generation of buses in favor of a packet-like split-cycle protocol. Wire-ORs, broadcasts, and even ordinary passive bus structures are to be avoided. However, a lower performance (1 GByte/sec per backplane instead of per processor) implementation using a register insertion ring architecture on a passive ''backplane'' appears to be possible using the same interface as for the more costly switch networks. This paper presents a summary of current directions, and reports the status of the work in progress

  19. Study on Additional Carrier Sensing for IEEE 802.15.4 Wireless Sensor Networks

    Bih-Hwang Lee

    2010-06-01

    Full Text Available Wireless sensor networks based on the IEEE 802.15.4 standard are able to achieve low-power transmissions in the guise of low-rate and short-distance wireless personal area networks (WPANs. The slotted carrier sense multiple access with collision avoidance (CSMA/CA is used for contention mechanism. Sensor nodes perform a backoff process as soon as the clear channel assessment (CCA detects a busy channel. In doing so they may neglect the implicit information of the failed CCA detection and further cause the redundant sensing. The blind backoff process in the slotted CSMA/CA will cause lower channel utilization. This paper proposes an additional carrier sensing (ACS algorithm based on IEEE 802.15.4 to enhance the carrier sensing mechanism for the original slotted CSMA/CA. An analytical Markov chain model is developed to evaluate the performance of the ACS algorithm. Both analytical and simulation results show that the proposed algorithm performs better than IEEE 802.15.4, which in turn significantly improves throughput, average medium access control (MAC delay and power consumption of CCA detection.

  20. FPGA implementation cost and performance evaluation of IEEE 802.11 protocol encryption security schemes

    Sklavos, N; Selimis, G; Koufopavlou, O

    2005-01-01

    The explosive growth of internet and consumer demand for mobility has fuelled the exponential growth of wireless communications and networks. Mobile users want access to services and information, from both internet and personal devices, from a range of locations without the use of a cable medium. IEEE 802.11 is one of the most widely used wireless standards of our days. The amount of access and mobility into wireless networks requires a security infrastructure that protects communication within that network. The security of this protocol is based on the wired equivalent privacy (WEP) scheme. Currently, all the IEEE 802.11 market products support WEP. But recently, the 802.11i working group introduced the advanced encryption standard (AES), as the security scheme for the future IEEE 802.11 applications. In this paper, the hardware integrations of WEP and AES are studied. A field programmable gate array (FPGA) device has been used as the hardware implementation platform, for a fair comparison between the two security schemes. Measurements for the FPGA implementation cost, operating frequency, power consumption and performance are given

  1. Strategies for Optimal MAC Parameters Tuning in IEEE 802.15.6 Wearable Wireless Sensor Networks.

    Alam, Muhammad Mahtab; Ben Hamida, Elyes

    2015-09-01

    Wireless body area networks (WBAN) has penetrated immensely in revolutionizing the classical heath-care system. Recently, number of WBAN applications has emerged which introduce potential limits to existing solutions. In particular, IEEE 802.15.6 standard has provided great flexibility, provisions and capabilities to deal emerging applications. In this paper, we investigate the application-specific throughput analysis by fine-tuning the physical (PHY) and medium access control (MAC) parameters of the IEEE 802.15.6 standard. Based on PHY characterizations in narrow band, at the MAC layer, carrier sense multiple access collision avoidance (CSMA/CA) and scheduled access protocols are extensively analyzed. It is concluded that, IEEE 802.15.6 standard can satisfy most of the WBANs applications throughput requirements by maximum achieving 680 Kbps. However, those emerging applications which require high quality audio or video transmissions, standard is not able to meet their constraints. Moreover, delay, energy efficiency and successful packet reception are considered as key performance metrics for comparing the MAC protocols. CSMA/CA protocol provides the best results to meet the delay constraints of medical and non-medical WBAN applications. Whereas, the scheduled access approach, performs very well both in energy efficiency and packet reception ratio.

  2. Study on additional carrier sensing for IEEE 802.15.4 wireless sensor networks.

    Lee, Bih-Hwang; Lai, Ruei-Lung; Wu, Huai-Kuei; Wong, Chi-Ming

    2010-01-01

    Wireless sensor networks based on the IEEE 802.15.4 standard are able to achieve low-power transmissions in the guise of low-rate and short-distance wireless personal area networks (WPANs). The slotted carrier sense multiple access with collision avoidance (CSMA/CA) is used for contention mechanism. Sensor nodes perform a backoff process as soon as the clear channel assessment (CCA) detects a busy channel. In doing so they may neglect the implicit information of the failed CCA detection and further cause the redundant sensing. The blind backoff process in the slotted CSMA/CA will cause lower channel utilization. This paper proposes an additional carrier sensing (ACS) algorithm based on IEEE 802.15.4 to enhance the carrier sensing mechanism for the original slotted CSMA/CA. An analytical Markov chain model is developed to evaluate the performance of the ACS algorithm. Both analytical and simulation results show that the proposed algorithm performs better than IEEE 802.15.4, which in turn significantly improves throughput, average medium access control (MAC) delay and power consumption of CCA detection.

  3. On IEEE 802.15.6 IR-UWB receivers - simulations for DBPSK modulation.

    Niemelä, Ville; Hämäläinen, Matti; Iinatti, Jari

    2013-01-01

    In 2002, Federal Communications Commission (FCC) was the first in defining regulations for ultra wideband (UWB) communications followed by Europe and Japan some years later. Focusing on impulse radio (IR) UWB, in 2007 was the time for the first published standard targeting in personal area networks, released by the IEEE. The second IEEE released standard including UWB definitions is targeted for wireless body area networks (WBAN) and was published in 2012. As the wireless communications has been and will be passing through almost any levels in society, the natural step with WBAN is using it in different medical, healthcare and wellbeing applications. The arguments for these are related to the modern lifestyle, in which people have increasingly more free time and are more interested in taking care of their health and wellbeing. Another challenge is the population composition, i.e., aging in developed countries which call for new solutions and procedures, particularly from cost wise. In this paper, we are evaluating UWB receivers based on the IEEE 802.15.6 physical layer definitions and capable of detecting differentially encoded modulation. The evaluation is performed using two different WBAN channel models.

  4. Segmentized Clear Channel Assessment for IEEE 802.15.4 Networks.

    Son, Kyou Jung; Hong, Sung Hyeuck; Moon, Seong-Pil; Chang, Tae Gyu; Cho, Hanjin

    2016-06-03

    This paper proposed segmentized clear channel assessment (CCA) which increases the performance of IEEE 802.15.4 networks by improving carrier sense multiple access with collision avoidance (CSMA/CA). Improving CSMA/CA is important because the low-power consumption feature and throughput performance of IEEE 802.15.4 are greatly affected by CSMA/CA behavior. To improve the performance of CSMA/CA, this paper focused on increasing the chance to transmit a packet by assessing precise channel status. The previous method used in CCA, which is employed by CSMA/CA, assesses the channel by measuring the energy level of the channel. However, this method shows limited channel assessing behavior, which comes from simple threshold dependent channel busy evaluation. The proposed method solves this limited channel decision problem by dividing CCA into two groups. Two groups of CCA compare their energy levels to get precise channel status. To evaluate the performance of the segmentized CCA method, a Markov chain model has been developed. The validation of analytic results is confirmed by comparing them with simulation results. Additionally, simulation results show the proposed method is improving a maximum 8.76% of throughput and decreasing a maximum 3.9% of the average number of CCAs per packet transmission than the IEEE 802.15.4 CCA method.

  5. Spectrum Hole Identification in IEEE 802.22 WRAN using Unsupervised Learning

    V. Balaji

    2016-01-01

    Full Text Available In this paper we present a Cooperative Spectrum Sensing (CSS algorithm for Cognitive Radios (CR based on IEEE 802.22Wireless Regional Area Network (WRAN standard. The core objective is to improve cooperative sensing efficiency which specifies how fast a decision can be reached in each round of cooperation (iteration to sense an appropriate number of channels/bands (i.e. 86 channels of 7MHz bandwidth as per IEEE 802.22 within a time constraint (channel sensing time. To meet this objective, we have developed CSS algorithm using unsupervised K-means clustering classification approach. The received energy level of each Secondary User (SU is considered as the parameter for determining channel availability. The performance of proposed algorithm is quantified in terms of detection accuracy, training and classification delay time. Further, the detection accuracy of our proposed scheme meets the requirement of IEEE 802.22 WRAN with the target probability of falsealrm as 0.1. All the simulations are carried out using Matlab tool.

  6. Analysis and Enhancement of IEEE 802.15.4e DSME Beacon Scheduling Model

    Kwang-il Hwang

    2014-01-01

    Full Text Available In order to construct a successful Internet of things (IoT, reliable network construction and maintenance in a sensor domain should be supported. However, IEEE 802.15.4, which is the most representative wireless standard for IoT, still has problems in constructing a large-scale sensor network, such as beacon collision. To overcome some problems in IEEE 802.15.4, the 15.4e task group proposed various different modes of operation. Particularly, the IEEE 802.15.4e deterministic and synchronous multichannel extension (DSME mode presents a novel scheduling model to solve beacon collision problems. However, the DSME model specified in the 15.4e draft does not present a concrete design model but a conceptual abstract model. Therefore, in this paper we introduce a DSME beacon scheduling model and present a concrete design model. Furthermore, validity and performance of DSME are evaluated through experiments. Based on experiment results, we analyze the problems and limitations of DSME, present solutions step by step, and finally propose an enhanced DSME beacon scheduling model. Through additional experiments, we prove the performance superiority of enhanced DSME.

  7. A Novel Prioritization Scheme to Improve QoS in IEEE 802.11e Networks

    Navid Tadayon

    2010-01-01

    Full Text Available IEEE 802.11 WLAN utilizes a distributed function at its MAC layer, namely, DCF to access the wireless medium. Due to its distributed nature, DCF is able to guarantee working stability in a wireless medium while maintaining the assembling and maintenance cost in a low level. However, DCF is inefficient in dealing with real-time traffics due to its incapability on providing QoS. IEEE 802.11e was introduced as a supplementary standard to cope with this problem. This standard introduces an Enhanced Distributed Coordination Function (EDCF that works based on diff-Serve model and can serve multiple classes of traffics (by using different prioritizations schemes. With the emergence of new time-sensitive applications, EDCF has proved to be yet inefficient in dealing with these kinds of traffics because it could not provide network with well-differentiated QoS. In this study, we propose a novel prioritization scheme to improve QoS level in IEEE 802.11e network. In this scheme, we replace Uniform PDF with Gamma PDF, which has salient differentiating properties. We investigate the suitability and superiority of this scheme on furnishing network with well-differentiated QoS using probabilistic analysis. We strengthen our claims by extensive simulation runs.

  8. Single event upset test programs

    Russen, L.C.

    1984-11-01

    It has been shown that the heavy ions in cosmic rays can give rise to single event upsets in VLSI random access memory devices (RAMs). Details are given of the programs written to test 1K, 4K, 16K and 64K memories during their irradiation with heavy charged ions, in order to simulate the effects of cosmic rays in space. The test equipment, which is used to load the memory device to be tested with a known bit pattern, and subsequently interrogate it for upsets, or ''flips'', is fully described. (author)

  9. Conference Proceedings for 1997 IEEE 24th International Conference on Plasma Sciences, 19 - 22 May 1997, San Diego, California

    Hyman, Julius

    1997-01-01

    This 360 page softbound publication includes the following major sections, An invitation to ICOPS'97, Catamaran Resort Hotel Floor Pinas, Officers of the IEEE Nuclear and Plasma Sciences Society, Conference Information...

  10. NIH-IEEE 2015 Strategic Conference on Healthcare Innovations and Point-of-Care Technologies for Prec

    NIH and the Institute for Electrical and Electronics Engineering, Engineering in Medicine and Biology Society (IEEE/EMBS) hosted the third iteration of the Healthcare Innovations and Point-of-Care Technologies Conference last week.

  11. Study of Allocation Guaranteed Time Slot Wireless Body Area Networks Based on IEEE 802.15.4

    Yundra, E.; Harsono, G. D.

    2018-04-01

    This paper aims to determine the size of the Guaranteed Time Slot (GTS) on the super frame structure required for each sensor as well as to know the performance of the GTS resized system compared to the GTS standard on IEEE 802.15.4. This article proposes a scheme to improve IEEE 802.15.4 medium access control, called allocation Guaranteed Time Slot (ALGATIS). ALGATIS is expected to effectively allocate guaranteed time slot to the requested sensors, it adjusts the length of the slot in super frame duration based on the length of the packet data. This article presents a simulation experiment of IEEE 802.15.4, especially for star network, to predict the throughput of networks and average energy consumption. The simulation experiments show that the performance of ALGATIS is better than that of IEEE 802.15.4 standard in term of the throughput of networks and average energy consumption

  12. Performance Analysis of IEEE 802.11g TCM Waveforms Transmitted over a Channel with Pulse-Noise Interference

    Drivas, Athanasios

    2007-01-01

    .... The application of TCM combines FEC coding and M-ary modulation in one operation. The objective of this thesis is to investigate the performance of an orthogonal frequency-division multiplexing (OFDM) based IEEE...

  13. Implementation of DoS attack and mitigation strategies in IEEE 802.11b/g WLAN

    Deng, Julia; Meng, Ke; Xiao, Yang; Xu, Roger

    2010-04-01

    IEEE 802.11 wireless Local Area Network (WLAN) becomes very prevalent nowadays. Either as a simple range extender for a home wired Ethernet interface, or as a wireless deployment throughout an enterprise, WLAN provides mobility, convenience, and low cost. However, an IEEE 802.11b/g wireless network uses the frequency of unlicensed 2.4GHz, which makes the network unsafe and more vulnerable than traditional Ethernet networks. As a result, anyone who is familiar with wireless network may initiate a Denial of Service (DoS) attack to influence the common communication of the network or even make it crash. In this paper, we present our studies on the DoS attacks and mitigation strategies for IEEE 802.11b/g WLANs and describe some initial implementations using IEEE 802.11b/g wireless devices.

  14. Implementation of IEEE-1588 timing and synchronization for ATCA control and data acquisition systems

    Correia, Miguel; Sousa, Jorge; Combo, Álvaro; Rodrigues, António P.; Carvalho, Bernardo B.; Batista, António J.N.; Gonçalves, Bruno; Correia, Carlos M.B.A.; Varandas, Carlos A.F.

    2012-01-01

    Highlights: ► IEEE-1588 over Ethernet protocol is implemented for the synchronization of all clock signals of an ATCA AMC carrier module. ► The ATCA hardware consists of an AMC quad-carrier main-board with PCI Express switching. ► IEEE-1588 is to be implemented on a Virtex-6 FPGA. ► Timing signals on the ATX-AMC4-PTP are managed and routed by a crosspoint-switch implemented on a Virtex-6 FPGA. ► Each clock signal source may be independently located (on each of the AMC cards, RTM or ATCA backplane). - Abstract: Control and data acquisition (C and DA) systems for Fusion experiments are required to provide accurate timing and synchronization (T and S) signals to all of its components. IPFN adopted PICMG's Advanced Telecommunications Computing Architecture (ATCA) industry standard to develop C and DA instrumentation. ATCA was chosen not only for its high throughput characteristics but also for its high availability (HA) features which become of greater importance in steady-state operation scenarios. However, the specified ATCA clock and synchronization interface may be too limited for the timing and synchronization needs in advanced Physics experiments. Upcoming specification extensions, developed by the “xTCA for Physics” workgroups, will contemplate, among others, a complementary timing specification, developed by the PICMG xTCA for Physics IO, Timing and Synchronization Technical Committee. The IEEE-1588 Precision Time Protocol (PTP) over Ethernet is one of the protocols, proposed by the Committee, aiming for precise synchronization of clocks in measurement and control systems, based on low jitter and slave-to-slave skew criteria. The paper presents an implementation of IEEE-1588 over Ethernet, in an ATCA hardware platform. The ATCA hardware consists of an Advanced Mezzanine Card (AMC) quad-carrier front board with PCI Express switching. IEEE-1588 is to be implemented on a Virtex-6 FPGA. Ethernet connectivity with the remote master clock is located on

  15. An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures

    Sparsø, Jens; Jørgensen, Henrik Nordtorp; Paaske, Erik

    1991-01-01

    A topology for single-chip implementation of computing structures based on shuffle-exchange (SE)-type interconnection networks is presented. The topology is suited for structures with a small number of processing elements (i.e. 32-128) whose area cannot be neglected compared to the area required....... The topology has been used in a VLSI implementation of the add-compare-select (ACS) module of a fully parallel K=7, R=1/2 Viterbi decoder. Both the floor-planning issues and some of the important algorithm and circuit-level aspects of this design are discussed. The chip has been designed and fabricated in a 2....... The interconnection network occupies 32% of the area.>...

  16. 10 K gate I(2)L and 1 K component analog compatible bipolar VLSI technology - HIT-2

    Washio, K.; Watanabe, T.; Okabe, T.; Horie, N.

    1985-02-01

    An advanced analog/digital bipolar VLSI technology that combines on the same chip 2-ns 10 K I(2)L gates with 1 K analog devices is proposed. The new technology, called high-density integration technology-2, is based on a new structure concept that consists of three major techniques: shallow grooved-isolation, I(2)L active layer etching, and I(2)L current gain increase. I(2)L circuits with 80-MHz maximum toggle frequency have developed compatibly with n-p-n transistors having a BV(CE0) of more than 10 V and an f(T) of 5 GHz, and lateral p-n-p transistors having an f(T) of 150 MHz.

  17. Macrocell Builder: IP-Block-Based Design Environment for High-Throughput VLSI Dedicated Digital Signal Processing Systems

    Urard Pascal

    2006-01-01

    Full Text Available We propose an efficient IP-block-based design environment for high-throughput VLSI systems. The flow generates SystemC register-transfer-level (RTL architecture, starting from a Matlab functional model described as a netlist of functional IP. The refinement model inserts automatically control structures to manage delays induced by the use of RTL IPs. It also inserts a control structure to coordinate the execution of parallel clocked IP. The delays may be managed by registers or by counters included in the control structure. The flow has been used successfully in three real-world DSP systems. The experimentations show that the approach can produce efficient RTL architecture and allows to save huge amount of time.

  18. Recent trends on Software Verification and Validation Testing

    Kim, Hyungtae; Jeong, Choongheui

    2013-01-01

    Verification and Validation (V and V) include the analysis, evaluation, review, inspection, assessment, and testing of products. Especially testing is an important method to verify and validate software. Software V and V testing covers test planning to execution. IEEE Std. 1012 is a standard on the software V and V. Recently, IEEE Std. 1012-2012 was published. This standard is a major revision to IEEE Std. 1012-2004 which defines only software V and V. It expands the scope of the V and V processes to include system and hardware as well as software. This standard describes the scope of V and V testing according to integrity level. In addition, independent V and V requirement related to software V and V testing in IEEE 7-4.3.2-2010 have been revised. This paper provides a recent trend of software V and V testing by reviewing of IEEE Std. 1012-2012 and IEEE 7-4.3.2-2010. There are no major changes of software V and V testing activities and tasks in IEEE 1012-2012 compared with IEEE 1012-2004. But the positions on the responsibility to perform software V and V testing are changed. In addition IEEE 7-4.3.2-2010 newly describes the positions on responsibility to perform Software V and V Testing. However, the positions of these standards on the V and V testing are different. For integrity level 3 and 4, IEEE 1012-2012 basically requires that V and V organization shall conduct all of V and V testing tasks such as test plan, test design, test case, and test procedure except test execution. If V and V testing is conducted by not V and V but another organization, the results of that testing shall be analyzed by the V and V organization. For safety-related software, IEEE 7-4.3.2-2010 requires that test procedures and reports shall be independently verified by the alternate organization regardless of who writes the procedures and/or conducts the tests

  19. DoS detection in IEEE 802.11 with the presence of hidden nodes

    Joseph Soryal

    2014-07-01

    Full Text Available The paper presents a novel technique to detect Denial of Service (DoS attacks applied by misbehaving nodes in wireless networks with the presence of hidden nodes employing the widely used IEEE 802.11 Distributed Coordination Function (DCF protocols described in the IEEE standard [1]. Attacker nodes alter the IEEE 802.11 DCF firmware to illicitly capture the channel via elevating the probability of the average number of packets transmitted successfully using up the bandwidth share of the innocent nodes that follow the protocol standards. We obtained the theoretical network throughput by solving two-dimensional Markov Chain model as described by Bianchi [2], and Liu and Saadawi [3] to determine the channel capacity. We validated the results obtained via the theoretical computations with the results obtained by OPNET simulator [4] to define the baseline for the average attainable throughput in the channel under standard conditions where all nodes follow the standards. The main goal of the DoS attacker is to prevent the innocent nodes from accessing the channel and by capturing the channel’s bandwidth. In addition, the attacker strives to appear as an innocent node that follows the standards. The protocol resides in every node to enable each node to police other nodes in its immediate wireless coverage area. All innocent nodes are able to detect and identify the DoS attacker in its wireless coverage area. We applied the protocol to two Physical Layer technologies: Direct Sequence Spread Spectrum (DSSS and Frequency Hopping Spread Spectrum (FHSS and the results are presented to validate the algorithm.

  20. DoS detection in IEEE 802.11 with the presence of hidden nodes.

    Soryal, Joseph; Liu, Xijie; Saadawi, Tarek

    2014-07-01

    The paper presents a novel technique to detect Denial of Service (DoS) attacks applied by misbehaving nodes in wireless networks with the presence of hidden nodes employing the widely used IEEE 802.11 Distributed Coordination Function (DCF) protocols described in the IEEE standard [1]. Attacker nodes alter the IEEE 802.11 DCF firmware to illicitly capture the channel via elevating the probability of the average number of packets transmitted successfully using up the bandwidth share of the innocent nodes that follow the protocol standards. We obtained the theoretical network throughput by solving two-dimensional Markov Chain model as described by Bianchi [2], and Liu and Saadawi [3] to determine the channel capacity. We validated the results obtained via the theoretical computations with the results obtained by OPNET simulator [4] to define the baseline for the average attainable throughput in the channel under standard conditions where all nodes follow the standards. The main goal of the DoS attacker is to prevent the innocent nodes from accessing the channel and by capturing the channel's bandwidth. In addition, the attacker strives to appear as an innocent node that follows the standards. The protocol resides in every node to enable each node to police other nodes in its immediate wireless coverage area. All innocent nodes are able to detect and identify the DoS attacker in its wireless coverage area. We applied the protocol to two Physical Layer technologies: Direct Sequence Spread Spectrum (DSSS) and Frequency Hopping Spread Spectrum (FHSS) and the results are presented to validate the algorithm.

  1. A Novel Energy Saving Algorithm with Frame Response Delay Constraint in IEEE 802.16e

    Nga, Dinh Thi Thuy; Kim, Mingon; Kang, Minho

    Sleep-mode operation of a Mobile Subscriber Station (MSS) in IEEE 802.16e effectively saves energy consumption; however, it induces frame response delay. In this letter, we propose an algorithm to quickly find the optimal value of the final sleep interval in sleep-mode in order to minimize energy consumption with respect to a given frame response delay constraint. The validations of our proposed algorithm through analytical results and simulation results suggest that our algorithm provide a potential guidance to energy saving.

  2. A Secure Simplification of the PKMv2 Protocol in IEEE 802.16e-2005

    Yuksel, Ender; Nielson, Hanne Riis; Nielsen, Christoffer Rosenkilde

    2007-01-01

    Static analysis is successfully used for automatically validating security properties of classical cryptographic protocols. In this paper, we shall employ the same technique to a modern security protocol for wireless networks, namely the latest version of the Privacy and Key Management protocol...... for IEEE 802.16e, PKMv2. This protocol seems to have an exaggerated mixture of security features. Thus, we iteratively investigate which components are necessary for upholding the security properties and which can be omitted safely. This approach is based on the LySa process calculus and employs...

  3. An IEEE 802.3 Compatible Real Time Medium Access Control with Length-based Priority

    2006-01-01

    A new medium access control method is proposed over the predominant Ethernet broadcast channel. Taking advantages of intrinsic variable length characteristic of standard Ethernet frame, message-oriented dynamic priority mechanism is established. Prioritized medium access control operates under a so-called block mode in event of collisions.High priority messages have a chance to preempt block status incurred by low priority ones. By this means, the new MAC provides a conditional deterministic real time performance beyond a statistical one. Experiments demonstrate effectiveness and attractiveness of the proposed scheme. Moreover, this new MAC is completely compatible with IEEE802.3.

  4. 2012 Special NSREC Issue of the IEEE Transactions on Nuclear Science Comments by the Editors

    Schwank, Jim; Brown, Dennis; Girard, Sylvain; Gouker, Pascale; Gerardin, Simone; Quinn, Heather; Barnaby, Hugh

    2012-12-01

    The December 2012 special issue of the IEEE Transactions on Nuclear Science contains selected papers from the 49th annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC) held July 16-20, 2012, in Miami, Florida USA. 95 papers presented at the 2012 NSREC were submitted for consideration for this year’s special issue. Those papers that appear in this special issue were able to successfully complete the review process before the deadline for the December issue. A few additional papers may appear in subsequent issues of the TRANSACTIONS. This publication is the premier archival journal for research on space and nuclear radiation effects in materials, devices, circuits, and systems. This distinction is the direct result of the conscientious efforts of both the authors, who present and document their work, and the reviewers, who selflessly volunteer their time and talent to help review the manuscripts. Each paper in this journal has been reviewed by experts selected by the editors for their expertise and knowledge of the particular subject areas. The peer review process for a typical technical journal generally takes six months to one year to complete. To publish this special issue of the IEEE Transactions on Nuclear Science (in December), the review process, from initial submission to final form, must be completed in about 10 weeks. Because of the short schedule, both the authors and reviewers are required to respond very quickly. The reviewers listed on the following pages contributed vitally to this quick-turn review process.We would like to express our sincere appreciation to each of them for accepting this difficult, but critical role in the process. To provide consistent reviews of papers throughout the year, the IEEE Transactions on Nuclear Science relies on a year-round editorial board that manages reviews for submissions throughout the year to the TRANSACTIONS in the area of radiation effects. The review process is managed by a Senior

  5. A time-based admission control mechanism for IEEE 802.11 ad Hoc networks

    Costa, Luís Henrique M. K.; Cerveira, Carlos Rodrigo

    2006-01-01

    This paper presents a time-based admission control mechanism (TAC) for IEEE 802.11 ad hoc networks. The proposed mechanism was adapted to the QoS AODV routing protocol, which takes the quality of service requirements of the data flow into account in the route discovery process. TAC-AODV estimates the idle time of the physical medium based on the frames listened. The incoming traffic is admitted according to the offered load as well as the intra-flow interference, calculated based on the numbe...

  6. 4th IEEE/ACIS International Conference on Computer and Information Science

    2016-01-01

    This edited book presents scientific results of the 14th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2015) which was held on June 28 – July 1, 2015 in Las Vegas, USA. The aim of this conference was to bring together researchers and scientists, businessmen and entrepreneurs, teachers, engineers, computer users, and students to discuss the numerous fields of computer science and to share their experiences and exchange new ideas and information in a meaningful way. Research results about all aspects (theory, applications and tools) of computer and information science, and to discuss the practical challenges encountered along the way and the solutions adopted to solve them.

  7. Impacto de mecanismos de seguridad en sensores IEEE 802.15.4

    Tripp Barba, Carolina; Casademont Serra, Jordi

    2009-01-01

    En la actualidad son muchos los mecanismos de seguridad que el estándar IEEE 802.15.4 permite a las redes inalámbricas de sensores [1] Dicho estándar define las especificaciones de la Capa de Acceso al Medio y la Capa Física de los dispositivos inalámbricos de área personal. La última revisión corresponde al 2006. Dichas revisiones y actualizaciones son hechas por el grupo de trabajo 802.15. Sin embargo estos mecanismos consumen recursos como memoria y batería, que son...

  8. Low-frequency electrical dosimetry: research agenda of the IEEE International Committee on Electromagnetic Safety.

    Reilly, J Patrick; Hirata, Akimasa

    2016-06-21

    This article treats unsettled issues in the use of numerical models of electrical dosimetry as applied to international limits on human exposure to low-frequency (typically  IEEE-ICES (International Committee on Electromagnetic Safety) Technical Committee 95. The paper discusses 25 issues needing attention, fitting into three general categories: induction models; electrostimulation models; and human exposure limits. Of these, 9 were voted as 'high priority' by members of Subcommittee 6. The list is presented as a research agenda for refinements in numerical modeling with applications to human exposure limits. It is likely that such issues are also important in medical and electrical product safety design applications.

  9. Connectivity-Based Reliable Multicast MAC Protocol for IEEE 802.11 Wireless LANs

    Woo-Yong Choi

    2009-01-01

    Full Text Available We propose the efficient reliable multicast MAC protocol based on the connectivity information among the recipients. Enhancing the BMMM (Batch Mode Multicast MAC protocol, the reliable multicast MAC protocol significantly reduces the RAK (Request for ACK frame transmissions in a reasonable computational time and enhances the MAC performance. By the analytical performance analysis, the throughputs of the BMMM protocol and our proposed MAC protocol are derived. Numerical examples show that our proposed MAC protocol increases the reliable multicast MAC performance for IEEE 802.11 wireless LANs.

  10. Impact of cell load on 5GHz IEEE 802.11 WLAN

    Abu-Tair, Mamoun; Bhatti, Saleem Noel

    2017-01-01

    We have conducted an empirical study of the latest 5GHz IEEE 802.11 wireless LAN (WLAN) variants of 802.11n (5GHz) and 802.11ac (Wave 1), under different cell load conditions. We have considered typical configurations of both protocols on a Linux testbed. Under light load,there is no clear difference between 802.11n and 802.11ac in terms of performance and energy consumption. However, in some cases of high cell load, we have found that there may be a small advantage with 802.11ac. Overall, we...

  11. Distributed Fair Access Point Selection for Multi-Rate IEEE 802.11 WLANs

    Gong, Huazhi; Nahm, Kitae; Kim, Jongwon

    In IEEE 802.11 networks, the access point (AP) selection based on the strongest signal strength often results in the extremely unfair bandwidth allocation among mobile users (MUs). In this paper, we propose a distributed AP selection algorithm to achieve a fair bandwidth allocation for MUs. The proposed algorithm gradually balances the AP loads based on max-min fairness for the available multiple bit rate choices in a distributed manner. We analyze the stability and overhead of the proposed algorithm, and show the improvement of the fairness via computer simulation.

  12. Rate Adaptation Based on Collision Probability for IEEE 802.11 WLANs

    Kim, Taejoon; Lim, Jong-Tae

    Nowadays IEEE 802.11 wireless local area networks (WLANs) support multiple transmission rates. To achieve the best performance, transmitting stations adopt the various forms of automatic rate fallback (ARF). However, ARF suffers from severe performance degradation as the number of transmitting stations increases. In this paper, we propose a new rate adaptation scheme which adjusts the ARF's up/down threshold according to the channel contention level. Simulation result shows that the proposed scheme achieves fairly good performance compared with the existing schemes.

  13. Adaptive rate selection scheme for video transmission to resolve IEEE 802.11 performance anomaly

    Tang, Guijin; Zhu, Xiuchang

    2011-10-01

    Multi-rate transmission may lead to performance anomaly in an IEEE 802.11 network. It will decrease the throughputs of all the higher rate stations. This paper proposes an adaptive rate selection scheme for video service when performance anomaly occurs. Considering that video has the characteristic of tolerance to packet loss, we actively drop several packets so as to select the rates as high as possible for transmitting packets. Experiment shows our algorithm can decrease the delay and jitter of video, and improve the system throughput as well.

  14. A Fair Cooperative MAC Protocol in IEEE 802.11 WLAN

    Seyed Davoud Mousavi

    2018-05-01

    Full Text Available Cooperative communication techniques have recently enabled wireless technologies to overcome their challenges. The main objective of these techniques is to improve resource allocation. In this paper, we propose a new protocol in medium access control (MAC of the IEEE 802.11 standard. In our new protocol, which is called Fair Cooperative MAC (FC-MAC, every relay node participates in cooperation proportionally to its provided cooperation gain. This technique improves network resource allocation by exploiting the potential capacity of all relay candidates. Simulation results demonstrate that the FC-MAC protocol presents better performance in terms of throughput, fairness, and network lifetime.

  15. Latency and Jitter Analysis for IEEE 802.11e Wireless LANs

    Sungkwan Youm

    2013-01-01

    Full Text Available This paper presents a numerical analysis of latency and jitter for IEEE 802.11e wireless local area networks (WLANs in a saturation condition, by using a Markov model. We use this model to explicate how the enhanced distributed coordination function (EDCF differentiates classes of service and to characterize the probability distribution of the medium access control (MAC layer packet latency and jitter, on which the quality of the voice over Internet protocol (VoIP calls is dependent. From the proposed analytic model, we can estimate the available number of nodes determining the system performance, in order to satisfy user demands on the latency and jitter.

  16. Planning of Efficient Wireless Access with IEEE 802.16 for Connecting Home Network to the Internet

    Pichet Ritthisoonthorn

    2010-01-01

    Full Text Available The emergence of IEEE802.16 wireless standard technology (WiMAX has significantly increased the choice to operators for the provisioning of wireless broadband access network. WiMAX is being deployed to compliment with xDSL in underserved or lack of the broadband network area, in both developed and developing countries. Many incumbent operators in developing countries are considering the deployment of WiMAX as part of their broadband access strategy. This paper presents an efficient and simple method for planning of broadband fixed wireless access (BFWA with IEEE802.16 standard to support home connection to Internet. The study formulates the framework for planning both coverage and capacity designs. The relationship between coverage area and access rate from subscriber in each environment area is presented. The study also presents the throughput and channel capacity of IEEE802.16 in different access rates. An extensive analysis is performed and the results are applied to the real case study to demonstrate the practicality of using IEEE 802.16 for connecting home to Internet. Using empirical data and original subscriber traffic from measurement, it is shown that the BFWA with IEEE802.16 standard is a capacity limited system. The capacity of IEEE802.16 is related to different factors including frequency bandwidth, spectrum allocation, estimation of traffic per subscriber, and choice of adaptive modulation from subscriber terminal. The wireless access methods and procedures evolved in this research work and set out in this paper are shown to be well suited for planning BFWA system based on IEEE802.16 which supports broadband home to Internet connections.

  17. Device interoperability and authentication for telemedical appliance based on the ISO/IEEE 11073 Personal Health Device (PHD) Standards.

    Caranguian, Luther Paul R; Pancho-Festin, Susan; Sison, Luis G

    2012-01-01

    In this study, we focused on the interoperability and authentication of medical devices in the context of telemedical systems. A recent standard called the ISO/IEEE 11073 Personal Health Device (X73-PHD) Standards addresses the device interoperability problem by defining common protocols for agent (medical device) and manager (appliance) interface. The X73-PHD standard however has not addressed security and authentication of medical devices which is important in establishing integrity of a telemedical system. We have designed and implemented a security policy within the X73-PHD standards. The policy will enable device authentication using Asymmetric-Key Cryptography and the RSA algorithm as the digital signature scheme. We used two approaches for performing the digital signatures: direct software implementation and use of embedded security modules (ESM). The two approaches were evaluated and compared in terms of execution time and memory requirement. For the standard 2048-bit RSA, ESM calculates digital signatures only 12% of the total time for the direct implementation. Moreover, analysis shows that ESM offers more security advantage such as secure storage of keys compared to using direct implementation. Interoperability with other systems was verified by testing the system with LNI Healthlink, a manager software that implements the X73-PHD standard. Lastly, security analysis was done and the system's response to common attacks on authentication systems was analyzed and several measures were implemented to protect the system against them.

  18. 2008 Special NSREC Issue of the IEEE Transactions on Nuclear Science Comments by the Editors

    Schwank, Jim; Buchner, Steve; Marshall, Paul; Duzellier, Sophie; Brown, Dennis; Poivey, Christian; Pease, Ron

    2008-12-01

    The December 2008 special issue of the IEEE Transactions on Nuclear Science contains selected papers from the 45th annual IEEE International Nuclear and Space Radiation Effects Conference (NSREC) held in Tucson, Arizona, July 14 - 18, 2008. Over 115 papers presented at the 2008 NSREC were submitted for consideration for this year's special issue. Those papers that appear in this special issue were able to successfully complete the review process before the deadline for the December issue. A few additional papers may appear in subsequent issues of the TRANSACTIONS. This publication is the premier archival journal for research on space and nuclear radiation effects in materials, devices, circuits, and systems. This distinction is the direct result of the conscientious efforts of both the authors, who present and document their work, and the reviewers, who selflessly volunteer their time and talent to help review the manuscripts. Each paper in this journal has been reviewed by experts selected by the editors for their expertise and knowledge of the particular subject areas.

  19. BOB-RED queue management for IEEE 802.15.4 wireless sensor networks

    Wu Jean-Lien

    2011-01-01

    Full Text Available Abstract Multimedia services over resource constrained wireless sensor networks (WSNs face a performance bottleneck issue from the gateway node to the sink node. Therefore, the queue management at the gateway node is crucial for diversified messages conveyed from the front nodes to the sink node. In this article, beacon order-based random early detection (BOB-RED queue management is proposed. BOB-RED is a dynamic adaptation scheme based on adjusting beacon interval and superframe duration in the IEEE 802.15.4 MAC superframe accompanied with RED queue management scheme to increase the transmission efficiency of multimedia over WSNs. We focus on the performance improvement upon different traffic loads over WSNs. Evaluation metrics include end-to-end delay, packet delivery ratio, and energy consumption in IEEE 802.15.4 beacon enabled mode. Simulation results show that BOB-RED can effectively decrease end-to-end delay and energy consumption compared to the DropTail scheme.

  20. Throughput analysis of the IEEE 802.4 token bus standard under heavy load

    Pang, Joseph; Tobagi, Fouad

    1987-01-01

    It has become clear in the last few years that there is a trend towards integrated digital services. Parallel to the development of public Integrated Services Digital Network (ISDN) is service integration in the local area (e.g., a campus, a building, an aircraft). The types of services to be integrated depend very much on the specific local environment. However, applications tend to generate data traffic belonging to one of two classes. According to IEEE 802.4 terminology, the first major class of traffic is termed synchronous, such as packetized voice and data generated from other applications with real-time constraints, and the second class is called asynchronous which includes most computer data traffic such as file transfer or facsimile. The IEEE 802.4 token bus protocol which was designed to support both synchronous and asynchronous traffic is examined. The protocol is basically a timer-controlled token bus access scheme. By a suitable choice of the design parameters, it can be shown that access delay is bounded for synchronous traffic. As well, the bandwidth allocated to asynchronous traffic can be controlled. A throughput analysis of the protocol under heavy load with constant channel occupation of synchronous traffic and constant token-passing times is presented.

  1. Real-Time-Simulation of IEEE-5-Bus Network on OPAL-RT-OP4510 Simulator

    Atul Bhandakkar, Anjali; Mathew, Lini, Dr.

    2018-03-01

    The Real-Time Simulator tools have high computing technologies, improved performance. They are widely used for design and improvement of electrical systems. The advancement of the software tools like MATLAB/SIMULINK with its Real-Time Workshop (RTW) and Real-Time Windows Target (RTWT), real-time simulators are used extensively in many engineering fields, such as industry, education, and research institutions. OPAL-RT-OP4510 is a Real-Time Simulator which is used in both industry and academia. In this paper, the real-time simulation of IEEE-5-Bus network is carried out by means of OPAL-RT-OP4510 with CRO and other hardware. The performance of the network is observed with the introduction of fault at various locations. The waveforms of voltage, current, active and reactive power are observed in the MATLAB simulation environment and on the CRO. Also, Load Flow Analysis (LFA) of IEEE-5-Bus network is computed using MATLAB/Simulink power-gui load flow tool.

  2. Improving Energy Efficiency in Idle Listening of IEEE 802.11 WLANs

    Muhammad Adnan

    2016-01-01

    Full Text Available This paper aims to improve energy efficiency of IEEE 802.11 wireless local area networks (WLANs by effectively dealing with idle listening (IL, which is required for channel sensing and is unavoidable in a contention-based channel access mechanism. Firstly, we show that IL is a dominant source of energy drain in WLANs and it cannot be effectively alleviated by the power saving mechanism proposed in the IEEE 802.11 standard. To solve this problem, we propose an energy-efficient mechanism that combines three schemes in a systematic way: downclocking, frame aggregation, and contention window adjustment. The downclocking scheme lets a station remain in a semisleep state when overhearing frames destined to neighbor stations, whereby the station consumes the minimal energy without impairing channel access capability. As well as decreasing the channel access overhead, the frame aggregation scheme prolongs the period of semisleep time. Moreover, by controlling the size of contention window based on the number of stations, the proposed mechanism decreases unnecessary IL time due to collision and retransmission. By deriving an analysis model and performing extensive simulations, we confirm that the proposed mechanism significantly improves the energy efficiency and throughput, by up to 2.8 and 1.8 times, respectively, compared to the conventional power saving mechanisms.

  3. A Green Media Access Method for IEEE 802.15.6 Wireless Body Area Network.

    Jacob, Anil K; Jacob, Lillykutty

    2017-09-30

    It is of utmost importance to conserve battery energy to the maximum possible extent in WBAN nodes while collecting and transferring medical data. The IEEE 802.15.6 WBAN standard does not specify any method to conserve energy. This paper focuses on a method to conserve energy in IEEE 802.15.6 WBAN nodes when using CSMA/CA, while simultaneously restricting data delivery delay to the required value as specified in medical applications. The technique is to allow the nodes to sleep all the times except for receiving beacons and for transmitting data frames whenever a data frame enters an empty buffer. The energy consumed by the nodes and the average latency of data frame for periodical arrival of data are found out analytically. The analytical results are validated and also the proposed method is compared with other energy conserving schemes, using Castalia simulation studies. The proposed method shows superior performance in both device lifetime and latency of emergency medical data.

  4. Predictable and reliable ECG monitoring over IEEE 802.11 WLANs within a hospital.

    Park, Juyoung; Kang, Kyungtae

    2014-09-01

    Telecardiology provides mobility for patients who require constant electrocardiogram (ECG) monitoring. However, its safety is dependent on the predictability and robustness of data delivery, which must overcome errors in the wireless channel through which the ECG data are transmitted. We report here a framework that can be used to gauge the applicability of IEEE 802.11 wireless local area network (WLAN) technology to ECG monitoring systems in terms of delay constraints and transmission reliability. For this purpose, a medical-grade WLAN architecture achieved predictable delay through the combination of a medium access control mechanism based on the point coordination function provided by IEEE 802.11 and an error control scheme based on Reed-Solomon coding and block interleaving. The size of the jitter buffer needed was determined by this architecture to avoid service dropout caused by buffer underrun, through analysis of variations in transmission delay. Finally, we assessed this architecture in terms of service latency and reliability by modeling the transmission of uncompressed two-lead electrocardiogram data from the MIT-BIH Arrhythmia Database and highlight the applicability of this wireless technology to telecardiology.

  5. Investigating the efficiency of IEEE 802.15.4 for medical monitoring applications.

    Pelegris, P; Banitsas, K

    2011-01-01

    Recent advancements in wireless communications technologies bring us one step closer to provide reliable Telecare services as an alternative to patients staying in a hospital mainly for monitoring purposes. In this research we investigate the efficiency of IEEE 802.15.4 in a simple scenario where a patient is being monitored using an ECG and a blood analysis module. This approach binds well with assisted living solutions, by sharing the network infrastructure for both monitoring and control while taking advantage of the low power features of the protocol. Such applications are becoming more and more realistic to implement as IEEE 802.15.4 compatible hardware becomes increasingly available. Our aim is to examine the impact of Beacon and Superframe Order in the medium access delay, dropped packets, end to end delay, average retransmission attempts and consumed power focusing on this bandwidth demanding situation where the network load does not allow low duty cycles, in order to draw some conclusions on the effect that this will have to telemonitoring applications.

  6. Self-Coexistence among IEEE 802.22 Networks: Distributed Allocation of Power and Channel.

    Sakin, Sayef Azad; Razzaque, Md Abdur; Hassan, Mohammad Mehedi; Alamri, Atif; Tran, Nguyen H; Fortino, Giancarlo

    2017-12-07

    Ensuring self-coexistence among IEEE 802.22 networks is a challenging problem owing to opportunistic access of incumbent-free radio resources by users in co-located networks. In this study, we propose a fully-distributed non-cooperative approach to ensure self-coexistence in downlink channels of IEEE 802.22 networks. We formulate the self-coexistence problem as a mixed-integer non-linear optimization problem for maximizing the network data rate, which is an NP-hard one. This work explores a sub-optimal solution by dividing the optimization problem into downlink channel allocation and power assignment sub-problems. Considering fairness, quality of service and minimum interference for customer-premises-equipment, we also develop a greedy algorithm for channel allocation and a non-cooperative game-theoretic framework for near-optimal power allocation. The base stations of networks are treated as players in a game, where they try to increase spectrum utilization by controlling power and reaching a Nash equilibrium point. We further develop a utility function for the game to increase the data rate by minimizing the transmission power and, subsequently, the interference from neighboring networks. A theoretical proof of the uniqueness and existence of the Nash equilibrium has been presented. Performance improvements in terms of data-rate with a degree of fairness compared to a cooperative branch-and-bound-based algorithm and a non-cooperative greedy approach have been shown through simulation studies.

  7. Performance analysis of the IEEE 802.16e power management for the initiations of awakening

    2007-01-01

    To increase battery life in IEEE 802.16e systems, it is essential to efficiently manage energy in mobile stations. The sleep-mode operation in power management helps to increase the life of a station by saving energy consumption. In power management, there are two important performance metrics: energy consumption and the response delay of awakening medium access control (MAC) service data unit (SDU). While in a base station (BS) initiation of awakening, the two performance metrics should be simultaneously considered, in a mobile subscriber station (MSS) initiation of awakening, the response delay is not considered because it is self-operational. There performance metrics are affected by the minimum sleep interval (Tmin), the maximum sleep interval (Tmax), and the average interarrival time of awakening MAC SDUs (TI) during sleep-mode operation. Therefore, it is imperative to evaluate the two initiations of awakening depending on TI. To reach a fuller understanding of the performance, this paper shows an analytical mode and simulations results for the standard sleep-mode operation in the IEEE 802.16e MAC.

  8. IEEE 1394 CAMERA IMAGING SYSTEM FOR BROOKHAVENS BOOSTER APPLICATION FACILITY BEAM DIAGNOSTICS

    BROWN, K.A.; FRAK, B.; GASSNER, D.; HOFF, L.; OLSEN, R.H.; SATOGATA, T.; TEPIKIAN, S.

    2002-01-01

    Brookhaven's Booster Applications Facility (BAF) will deliver resonant extracted heavy ion beams from the AGS Booster to short-exposure fixed-target experiments located at the end of the BAF beam line. The facility is designed to deliver a wide range of heavy ion species over a range of intensities from 10 3 to over 10 8 ions/pulse, and over a range of energies from 0.1 to 3.0 GeV/nucleon. With these constraints we have designed instrumentation packages which can deliver the maximum amount of dynamic range at a reasonable cost. Through the use of high quality optics systems and neutral density light filters we will achieve 4 to 5 orders of magnitude in light collection. By using digital IEEE1394 camera systems we are able to eliminate the frame-grabber stage in processing and directly transfer data at maximum rates of 400 Mb/set. In this note we give a detailed description of the system design and discuss the parameters used to develop the system specifications. We will also discuss the IEEE1394 camera software interface and the high-level user interface

  9. An Adaptive Medium Access Parameter Prediction Scheme for IEEE 802.11 Real-Time Applications

    Estefanía Coronado

    2017-01-01

    Full Text Available Multimedia communications have experienced an unprecedented growth due mainly to the increase in the content quality and the emergence of smart devices. The demand for these contents is tending towards wireless technologies. However, these transmissions are quite sensitive to network delays. Therefore, ensuring an optimum QoS level becomes of great importance. The IEEE 802.11e amendment was released to address the lack of QoS capabilities in the original IEEE 802.11 standard. Accordingly, the Enhanced Distributed Channel Access (EDCA function was introduced, allowing it to differentiate traffic streams through a group of Medium Access Control (MAC parameters. Although EDCA recommends a default configuration for these parameters, it has been proved that it is not optimum in many scenarios. In this work a dynamic prediction scheme for these parameters is presented. This approach ensures an appropriate traffic differentiation while maintaining compatibility with the stations without QoS support. As the APs are the only devices that use this algorithm, no changes are required to current network cards. The results show improvements in both voice and video transmissions, as well as in the QoS level of the network that the proposal achieves with regard to EDCA.

  10. Dynamic Contention Window Control Scheme in IEEE 802.11e EDCA-Based Wireless LANs

    Abeysekera, B. A. Hirantha Sithira; Matsuda, Takahiro; Takine, Tetsuya

    In the IEEE 802.11 MAC protocol, access points (APs) are given the same priority as wireless terminals in terms of acquiring the wireless link, even though they aggregate several downlink flows. This feature leads to a serious throughput degradation of downlink flows, compared with uplink flows. In this paper, we propose a dynamic contention window control scheme for the IEEE 802.11e EDCA-based wireless LANs, in order to achieve fairness between uplink and downlink TCP flows while guaranteeing QoS requirements for real-time traffic. The proposed scheme first determines the minimum contention window size in the best-effort access category at APs, based on the number of TCP flows. It then determines the minimum and maximum contention window sizes in higher priority access categories, such as voice and video, so as to guarantee QoS requirements for these real-time traffic. Note that the proposed scheme does not require any modification to the MAC protocol at wireless terminals. Through simulation experiments, we show the effectiveness of the proposed scheme.

  11. Adaptive Backoff Algorithm for Contention Window for Dense IEEE 802.11 WLANs

    Ikram Syed

    2016-01-01

    Full Text Available The performance improvement in IEEE 802.11 WLANs in widely fluctuating network loads is a challenging task. To improve the performance in this saturated state, we develop an adaptive backoff algorithm that maximizes the system throughput, reduces the collision probability, and maintains a high fairness for the IEEE 802.11 DCF under dense network conditions. In this paper, we present two main advantages of the proposed ABA-CW algorithm. First, it estimates the number of active stations and then calculates an optimal contention window based on the active station number. Each station calculates the channel state probabilities by observing the channel for the total backoff period. Based on these channel states probabilities, each station can estimate the number of active stations in the network, after which it calculates the optimal CW utilizing the estimated active number of stations. To evaluate the proposed mechanism, we derive an analytical model to determine the network performance. From our results, the proposed ABA-CW mechanism achieved better system performance compared to fixed-CW (BEB, EIED, LILD, and SETL and adaptive-CW (AMOCW, Idle Sense mechanisms. The simulation results confirmed the outstanding performance of the proposed mechanism in that it led to a lower collision probability, higher throughput, and high fairness.

  12. Self-Coexistence among IEEE 802.22 Networks: Distributed Allocation of Power and Channel

    Sayef Azad Sakin

    2017-12-01

    Full Text Available Ensuring self-coexistence among IEEE 802.22 networks is a challenging problem owing to opportunistic access of incumbent-free radio resources by users in co-located networks. In this study, we propose a fully-distributed non-cooperative approach to ensure self-coexistence in downlink channels of IEEE 802.22 networks. We formulate the self-coexistence problem as a mixed-integer non-linear optimization problem for maximizing the network data rate, which is an NP-hard one. This work explores a sub-optimal solution by dividing the optimization problem into downlink channel allocation and power assignment sub-problems. Considering fairness, quality of service and minimum interference for customer-premises-equipment, we also develop a greedy algorithm for channel allocation and a non-cooperative game-theoretic framework for near-optimal power allocation. The base stations of networks are treated as players in a game, where they try to increase spectrum utilization by controlling power and reaching a Nash equilibrium point. We further develop a utility function for the game to increase the data rate by minimizing the transmission power and, subsequently, the interference from neighboring networks. A theoretical proof of the uniqueness and existence of the Nash equilibrium has been presented. Performance improvements in terms of data-rate with a degree of fairness compared to a cooperative branch-and-bound-based algorithm and a non-cooperative greedy approach have been shown through simulation studies.

  13. An Authentication and Key Management Mechanism for Resource Constrained Devices in IEEE 802.11-based IoT Access Networks

    Kim, Ki-Wook; Han, Youn-Hee; Min, Sung-Gi

    2017-01-01

    Many Internet of Things (IoT) services utilize an IoT access network to connect small devices with remote servers. They can share an access network with standard communication technology, such as IEEE 802.11ah. However, an authentication and key management (AKM) mechanism for resource constrained IoT devices using IEEE 802.11ah has not been proposed as yet. We therefore propose a new AKM mechanism for an IoT access network, which is based on IEEE 802.11 key management with the IEEE 802.1X aut...

  14. Problems and solutions in application of IEEE standards at Savannah River Site, Department of Energy (DOE) nuclear facilities

    Lee, Y.S.; Bowers, T.L.; Chopra, B.J.; Thompson, T.T.; Zimmerman, E.W.

    1993-01-01

    The Department of Energy (DOE) Nuclear Material Production Facilities at the Savannah River Site (SRS) were designed, constructed, and placed into operation in the early 1950's, based on existing industry codes/standards, design criteria, analytical procedures. Since that time, DOE has developed Orders and Polices for the planning, design and construction of DOE Nuclear Reactor Facilities which invoke or reference commercial nuclear reactor codes and standards. The application of IEEE reactor design requirements such as Equipment Qualification, Seismic Qualification, Single Failure Criteria, and Separation Requirement, to non-reactor facilities has been a problem since the IEEE reactor criteria do not directly confirm to the needs of non-reactor facilities. SRS Systems Engineering is developing a methodology for the application of IEEE Standards to non-reactor facilities at SRS

  15. A distributed scheme to manage the dynamic coexistence of IEEE 802.15.4-based health-monitoring WBANs.

    Deylami, Mohammad N; Jovanov, Emil

    2014-01-01

    The overlap of transmission ranges between wireless networks as a result of mobility is referred to as dynamic coexistence. The interference caused by coexistence may significantly affect the performance of wireless body area networks (WBANs) where reliability is particularly critical for health monitoring applications. In this paper, we analytically study the effects of dynamic coexistence on the operation of IEEE 802.15.4-based health monitoring WBANs. The current IEEE 802.15.4 standard lacks mechanisms for effectively managing the coexistence of mobile WBANs. Considering the specific characteristics and requirements of health monitoring WBANs, we propose the dynamic coexistence management (DCM) mechanism to make IEEE 802.15.4-based WBANs able to detect and mitigate the harmful effects of coexistence. We assess the effectiveness of this scheme using extensive OPNET simulations. Our results indicate that DCM improves the successful transmission rates of dynamically coexisting WBANs by 20%-25% for typical medical monitoring applications.

  16. Simultaneous transmission of the IEEE 802.11 radio signal and optical Gbit Ethernet over the multimode fiber link

    Maksymiuk, L.; Podziewski, A.

    2015-09-01

    In the paper we present a successful joint transmission of the IEEE 802.11 signal and an optical Gbit Ethernet over a multimode fiber based link. Most importantly, the multiplexation of both signals was performed in the optical domain. Due to the utilization of the multimode fiber the OBI noise was avoided and both channels were able to operate at the same wavelength. We prove that potential RoF link for IEEE 802.11 signal distribution may be used to additionally transmit other signals as Gbit Ethernet and therefore utilize the fiber infrastructure installed more effectively. The qualities of both the IEEE 802.11 and Ethernet transmissions fulfilled the requirements imposed by appropriate standards.

  17. A Cross-Layer Key Management Scheme for MIPv6 Fast Handover over IEEE 802.11 Wireless LAN

    Chang-Seop Park

    2015-01-01

    Full Text Available A new key management and security scheme is proposed to integrate Layer Two (L2 and Layer Three (L3 keys for secure and fast Mobile IPv6 handover over IEEE 802.11 Wireless Local Area Network (WLAN. Unlike the original IEEE 802.11-based Mobile IPv6 Fast Handover (FMIPv6 that requires time-consuming IEEE 802.1x-based Extensible Authentication Protocol (EAP authentication on each L3 handover, the newly proposed key management and security scheme requires only one 802.1x-EAP regardless of how many L3 handovers occur. Therefore, the proposed scheme reduces the handover latency that results from a lengthy 802.1x-based EAP. The proposed key management and security scheme is extensively analyzed in terms of security and performance, and the proposed security scheme is shown to be more secure than those that were previously proposed.

  18. Galileo battery testing and the impact of test automation

    Pertuch, W. T.; Dils, C. T.

    1985-01-01

    Test complexity, changes of test specifications, and the demand for tight control of tests led to the development of automated testing used for Galileo and other projects. The use of standardized interfacing, i.e., IEEE-488, with desktop computers and test instruments, resulted in greater reliability, repeatability, and accuracy of both control and data reporting. Increased flexibility of test programming has reduced costs by permitting a wide spectrum of test requirements at one station rather than many stations.

  19. IEEE Xplore® Digital Library - Evolving to Meet YOUR Changing Needs

    2014-01-01

    Представлена презентация доклада "Использование платформы IEEE Digital Library: уникальные научные публикации в области электроники, радиосвязи, вычислительной техники, информационных технологий, энергетики, машиностроения, физики, химии, геологии, нанотехнологий" Эстер Лукаш, специалиста по обучению IEEE (Германия), на семинаре «Использование платформы IEEE Digital Library», прошедшем 02 октября 2014 года в УрФУ, на английском языке....

  20. Synchronous ethernet and IEEE 1588 in telecoms next generation synchronization networks

    2013-01-01

    This book addresses the multiple technical aspects of the distribution of synchronization in new generation telecommunication networks, focusing in particular on synchronous Ethernet and IEEE1588 technologies. Many packet network engineers struggle with understanding the challenges that precise synchronization distribution can impose on networks. The usual “why”, “when” and particularly “how” can cause problems for many engineers. In parallel to this, some other markets have identical synchronization requirements, but with their own design requirements, generating further questions. This book attempts to respond to the different questions by providing background technical information. Invaluable information on state of-the-art packet network synchronization and timing architectures is provided, as well as an unbiased view on the synchronization technologies that have been internationally standardized over recent years, with the aim of providing the average reader (who is not skilled in the art) wi...

  1. 12th ACIS/IEEE International Conference on Computer Science and Information Science

    2013-01-01

    This edited book presents scientific results of the 12th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2013) which was held on June 16-20, 2013 in Toki Messe, Niigata, Japan. The aim of this conference was to bring together scientists, engineers, computer users, and students to share their experiences and exchange new ideas, research results about all aspects (theory, applications and tools) of computer and information science, and to discuss the practical challenges encountered along the way and the solutions adopted to solve them The conference organizers selected the best 20 papers from those papers accepted for presentation at the conference. The papers were chosen based on review scores submitted by members of the program committee, and underwent further rigorous rounds of review.    

  2. Efficient Beacon Collision Resolution Procedure for IEEE 802.15.4 /Zigbee Wireless Personal Area Networks

    Bassam A. Zafar

    2017-04-01

    Full Text Available While IEEE 802.15.4/Zigbee is a promising technology for Wireless Personal Area Networks, several transmission problems are not yet resolved. In particular, the problem of beacon transmission interferences is causing the device connection loss to the network. In order to resolve this problem, we present a new distributed and reactive procedure for beacon collision resolution. It is an extension of the alignment procedure to reorganize randomly the beacon transmission time when a collision has occurred. The detail of the proposed procedure will be fully described and analyzed. The performance of our approach is performed by simulations. The results show that our approach reduces the collision probability and the device disconnections consequently.

  3. The IEEE guide to writing in the engineering and technical fields

    Kmiec, David

    2017-01-01

    This book introduces students and practicing engineers to all the components of writing in the workplace. It teaches readers how considerations of audience and purpose govern the structure of their documents within particular work settings. The IEEE Guide to Writing in the Engineering and Technical Fields is broken up into two sections: "Writing in Engineering Organizations" and "What Can You Do With Writing?" The first section helps readers approach their writing in a logical and persuasive way as well as analyze their purpose for writing. The second section demonstrates how to distinguish rhetorical situations and the generic forms to inform, train, persuade, and collaborate. The emergence of the global workplace has brought with it an increasingly important role for effective technical communication. Engineers more often need to work in cross-functional teams with people in different disciplines, in different countries, and in different parts of the world. Engineers must know how to communicate in a rapid...

  4. Development of a low mobility IEEE 802.15.4 compliant VANET system for urban environments.

    Nazabal, Juan Antonio; Falcone, Francisco; Fernández-Valdivielso, Carlos; Matías, Ignacio Raúl

    2013-05-29

    The use of Vehicular Ad-Hoc Networks (VANETs) is growing nowadays and it includes both roadside-to-vehicle communication (RVC) and inter-vehicle communication (IVC). The purpose of VANETs is to exchange useful information between vehicles and the roadside infrastructures for making an intelligent use of them. There are several possible applications for this technology like: emergency warning system for vehicles, cooperative adaptive cruise control or collision avoidance, among others. The objective of this work is to develop a VANET prototype system for urban environments using IEEE 802.15.4 compliant devices. Simulation-based values of the estimated signal strength and radio link quality values are obtained and compared with measurements in outdoor conditions to validate an implemented VANET system. The results confirm the possibility of implementing low cost vehicular communication networks operating at moderate vehicular speeds.

  5. 2011 IEEE Visualization Contest winner: Visualizing unsteady vortical behavior of a centrifugal pump.

    Otto, Mathias; Kuhn, Alexander; Engelke, Wito; Theisel, Holger

    2012-01-01

    In the 2011 IEEE Visualization Contest, the dataset represented a high-resolution simulation of a centrifugal pump operating below optimal speed. The goal was to find suitable visualization techniques to identify regions of rotating stall that impede the pump's effectiveness. The winning entry split analysis of the pump into three parts based on the pump's functional behavior. It then applied local and integration-based methods to communicate the unsteady flow behavior in different regions of the dataset. This research formed the basis for a comparison of common vortex extractors and more recent methods. In particular, integration-based methods (separation measures, accumulated scalar fields, particle path lines, and advection textures) are well suited to capture the complex time-dependent flow behavior. This video (http://youtu.be/oD7QuabY0oU) shows simulations of unsteady flow in a centrifugal pump.

  6. Vispubdata.org: A Metadata Collection About IEEE Visualization (VIS) Publications.

    Isenberg, Petra; Heimerl, Florian; Koch, Steffen; Isenberg, Tobias; Xu, Panpan; Stolper, Charles D; Sedlmair, Michael; Chen, Jian; Moller, Torsten; Stasko, John

    2017-09-01

    We have created and made available to all a dataset with information about every paper that has appeared at the IEEE Visualization (VIS) set of conferences: InfoVis, SciVis, VAST, and Vis. The information about each paper includes its title, abstract, authors, and citations to other papers in the conference series, among many other attributes. This article describes the motivation for creating the dataset, as well as our process of coalescing and cleaning the data, and a set of three visualizations we created to facilitate exploration of the data. This data is meant to be useful to the broad data visualization community to help understand the evolution of the field and as an example document collection for text data visualization research.

  7. Beamforming transmission in IEEE 802.11ac under time-varying channels.

    Yu, Heejung; Kim, Taejoon

    2014-01-01

    The IEEE 802.11ac wireless local area network (WLAN) standard has adopted beamforming (BF) schemes to improve spectral efficiency and throughput with multiple antennas. To design the transmit beam, a channel sounding process to feedback channel state information (CSI) is required. Due to sounding overhead, throughput increases with the amount of transmit data under static channels. Under practical channel conditions with mobility, however, the mismatch between the transmit beam and the channel at transmission time causes performance loss when transmission duration after channel sounding is too long. When the fading rate, payload size, and operating signal-to-noise ratio are given, the optimal transmission duration (i.e., packet length) can be determined to maximize throughput. The relationship between packet length and throughput is also investigated for single-user and multiuser BF modes.

  8. IEEE [Institute of Electrical and Electronics Engineers] standards and nuclear software quality engineering

    Daughtrey, T.

    1988-01-01

    Significant new nuclear-specific software standards have recently been adopted under the sponsorship of the American Nuclear Society and the American Society of Mechanical Engineers. The interest of the US Nuclear Regulatory Commission has also been expressed through their issuance of NUREG/CR-4640. These efforts all indicate a growing awareness of the need for thorough, referenceable expressions of the way to build in and evaluate quality in nuclear software. A broader professional perspective can be seen in the growing number of software engineering standards sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society. This family of standards represents a systematic effort to capture professional consensus on quality practices throughout the software development life cycle. The only omission-the implementation phase-is treated by accepted American National Standards Institute or de facto standards for programming languages

  9. 3th IEEE/ACIS International Conference on Computer and Information Science

    2015-01-01

    This edited book presents scientific results of the 13th IEEE/ACIS International Conference on Computer and Information Science (ICIS 2014) which was held on June 4-6, 2014 in Taiyuan, China. The aim of this conference was to bring together researchers and scientists, businessmen and entrepreneurs, teachers, engineers, computer users, and students to discuss the numerous fields of computer science and to share their experiences and exchange new ideas and information in a meaningful way. Research results about all aspects (theory, applications and tools) of computer and information science, and to discuss the practical challenges encountered along the way and the solutions adopted to solve them. The conference organizers selected the best papers from those papers accepted for presentation at the conference.  The papers were chosen based on review scores submitted by members of the program committee, and underwent further rigorous rounds of review. This publication captures 14 of the conference’s most promis...

  10. Delay efficient cooperation in public safety vehicular networks using LTE and IEEE 802.11p

    Atat, Rachad

    2012-01-01

    Cooperative schemes for critical content distribution over vehicular networks are presented and analyzed. The first scheme is based on unicasting from the base station, whereas the second is based on threshold based multicasting. Long Term Evolution (LTE) is used for long range communications with the base station (BS) and 802.11p is considered for inter-vehicle collaboration on the short range. A high mobility environment with correlated shadowing is adopted. Both schemes are shown to outperform non-cooperative unicasting and multicasting, respectively, when the appropriate 802.11p power class is used. The first scheme achieves the best performance among the compared methods, and a practical approximation of that scheme is shown to be close to optimal performance. © 2012 IEEE.

  11. Dynamic Voltage Stability Studies using a Modified IEEE 30-Bus System

    Oluwafemi Emmanuel Oni

    2016-09-01

    Full Text Available Power System stability is an essential study in the planning and operation of an efficient, economic, reliable and secure electric power system because it encompasses all the facet of power systems operations, from planning, to conceptual design stages of the project as well as during the systems operating life span. This paper presents different scenario of power system stability studies on a modified IEEE 30-bus system which is subjected to different faults conditions. A scenario whereby the longest high voltage alternating current (HVAC line is replaced with a high voltage direct current (HVDC line was implemented. The results obtained show that the HVDC line enhances system stability more compared to the contemporary HVAC line. Dynamic analysis using RMS simulation tool was used on DigSILENT PowerFactory.

  12. Reliable Multicast MAC Protocol for IEEE 802.11 Wireless LANs with Extended Service Range

    Choi, Woo-Yong

    2011-11-01

    In this paper, we propose the efficient reliable multicast MAC protocol by which the AP (Access Point) can transmit reliably its multicast data frames to the recipients in the AP's one-hop or two-hop transmission range. The AP uses the STAs (Stations) that are directly associated with itself as the relays for the data delivery to the remote recipients that cannot be reached directly from itself. Based on the connectivity information among the recipients, the reliable multicast MAC protocol optimizes the number of the RAK (Request for ACK) frame transmissions in a reasonable computational time. Numerical examples show that our proposed MAC protocol significantly enhances the MAC performance compared with the BMMM (Batch Mode Multicast MAC) protocol that is extended to support the recipients that are in the AP's one-hop or two-hop transmission range in IEEE 802.11 wireless LANs.

  13. Experimental video signals distribution MMF network based on IEEE 802.11 standard

    Kowalczyk, Marcin; Maksymiuk, Lukasz; Siuzdak, Jerzy

    2014-11-01

    The article was focused on presentation the achievements in a scope of experimental research on transmission of digital video streams in the frame of specially realized for this purpose ROF (Radio over Fiber) network. Its construction was based on the merge of wireless IEEE 802.11 network, popularly referred as Wi-Fi, with a passive optical network PON based on multimode fibers MMF. The proposed approach can constitute interesting proposal in area of solutions in the scope of the systems monitoring extensive, within which is required covering of a large area with ensuring of a relatively high degree of immunity on the interferences transmitted signals from video IP cameras to the monitoring center and a high configuration flexibility (easily change the deployment of cameras) of such network.

  14. IEEE 1394/firewire a low cost, high speed, digital serial bus

    Gaunt, R.

    1997-05-01

    Does the world need yet another 1/0 bus standard? If you need fast and cheap serial video communication, then the answer is yes. As technology advances, so too must data transport mechanisms advance. You can`t expect RS-232 to support real-time digital video, and if you can`t afford expensive professional serial video interfaces, (such as Sony`s Serial Digital Interface), Firewire may be a good solution. IEEE 1394, or commonly known as Firewire, is a general purpose serial bus that meets many of the 1/0 needs of today`s video and multimedia developers. For those of you who only read the first paragraph, here`s Firewire in a nutshell: It provides a guaranteed transfer rate of 10OMbps or 20OMbps of digital data (such as video direct from camera to computer), over an inexpensive, non-proprietary serial bus. Here is a list of its features.

  15. A Study of IEEE 802.15.4 Security Framework for Wireless Body Area Networks

    Kyung Sup Kwak

    2011-01-01

    Full Text Available A Wireless Body Area Network (WBAN is a collection of low-power and lightweight wireless sensor nodes that are used to monitor the human body functions and the surrounding environment. It supports a number of innovative and interesting applications, including ubiquitous healthcare and Consumer Electronics (CE applications. Since WBAN nodes are used to collect sensitive (life-critical information and may operate in hostile environments, they require strict security mechanisms to prevent malicious interaction with the system. In this paper, we first highlight major security requirements and Denial of Service (DoS attacks in WBAN at Physical, Medium Access Control (MAC, Network, and Transport layers. Then we discuss the IEEE 802.15.4 security framework and identify the security vulnerabilities and major attacks in the context of WBAN. Different types of attacks on the Contention Access Period (CAP and Contention Free Period (CFP parts of the superframe are analyzed and discussed. It is observed that a smart attacker can successfully corrupt an increasing number of GTS slots in the CFP period and can considerably affect the Quality of Service (QoS in WBAN (since most of the data is carried in CFP period. As we increase the number of smart attackers the corrupted GTS slots are eventually increased, which prevents the legitimate nodes to utilize the bandwidth efficiently. This means that the direct adaptation of IEEE 802.15.4 security framework for WBAN is not totally secure for certain WBAN applications. New solutions are required to integrate high level security in WBAN.

  16. A study of IEEE 802.15.4 security framework for wireless body area networks.

    Saleem, Shahnaz; Ullah, Sana; Kwak, Kyung Sup

    2011-01-01

    A Wireless Body Area Network (WBAN) is a collection of low-power and lightweight wireless sensor nodes that are used to monitor the human body functions and the surrounding environment. It supports a number of innovative and interesting applications, including ubiquitous healthcare and Consumer Electronics (CE) applications. Since WBAN nodes are used to collect sensitive (life-critical) information and may operate in hostile environments, they require strict security mechanisms to prevent malicious interaction with the system. In this paper, we first highlight major security requirements and Denial of Service (DoS) attacks in WBAN at Physical, Medium Access Control (MAC), Network, and Transport layers. Then we discuss the IEEE 802.15.4 security framework and identify the security vulnerabilities and major attacks in the context of WBAN. Different types of attacks on the Contention Access Period (CAP) and Contention Free Period (CFP) parts of the superframe are analyzed and discussed. It is observed that a smart attacker can successfully corrupt an increasing number of GTS slots in the CFP period and can considerably affect the Quality of Service (QoS) in WBAN (since most of the data is carried in CFP period). As we increase the number of smart attackers the corrupted GTS slots are eventually increased, which prevents the legitimate nodes to utilize the bandwidth efficiently. This means that the direct adaptation of IEEE 802.15.4 security framework for WBAN is not totally secure for certain WBAN applications. New solutions are required to integrate high level security in WBAN.

  17. Mixed-Dimensionality VLSI-Type Configurable Tools for Virtual Prototyping of Biomicrofluidic Devices and Integrated Systems

    Makhijani, Vinod B.; Przekwas, Andrzej J.

    2002-10-01

    This report presents results of a DARPA/MTO Composite CAD Project aimed to develop a comprehensive microsystem CAD environment, CFD-ACE+ Multiphysics, for bio and microfluidic devices and complete microsystems. The project began in July 1998, and was a three-year team effort between CFD Research Corporation, California Institute of Technology (CalTech), University of California, Berkeley (UCB), and Tanner Research, with Mr. Don Verlee from Abbott Labs participating as a consultant on the project. The overall objective of this project was to develop, validate and demonstrate several applications of a user-configurable VLSI-type mixed-dimensionality software tool for design of biomicrofluidics devices and integrated systems. The developed tool would provide high fidelity 3-D multiphysics modeling capability, l-D fluidic circuits modeling, and SPICE interface for system level simulations, and mixed-dimensionality design. It would combine tools for layouts and process fabrication, geometric modeling, and automated grid generation, and interfaces to EDA tools (e.g. Cadence) and MCAD tools (e.g. ProE).

  18. Mathematical modeling of a radio-frequency path for IEEE 802.11ah based wireless sensor networks

    Tyshchenko, Igor; Cherepanov, Alexander; Dmitrii, Vakhnin; Popova, Mariia

    2017-09-01

    This article discusses the process of creating the mathematical model of a radio-frequency path for an IEEE 802.11ah based wireless sensor networks using M atLab Simulink CAD tools. In addition, it describes occurring perturbing effects and determining the presence of a useful signal in the received mixture.

  19. Spectrum-efficient multi-channel design for coexisting IEEE 802.15.4 networks: A stochastic geometry approach

    Elsawy, Hesham

    2014-07-01

    For networks with random topologies (e.g., wireless ad-hoc and sensor networks) and dynamically varying channel gains, choosing the long term operating parameters that optimize the network performance metrics is very challenging. In this paper, we use stochastic geometry analysis to develop a novel framework to design spectrum-efficient multi-channel random wireless networks based on the IEEE 802.15.4 standard. The proposed framework maximizes both spatial and time domain frequency utilization under channel gain uncertainties to minimize the number of frequency channels required to accommodate a certain population of coexisting IEEE 802.15.4 networks. The performance metrics are the outage probability and the self admission failure probability. We relax the single channel assumption that has been used traditionally in the stochastic geometry analysis. We show that the intensity of the admitted networks does not increase linearly with the number of channels and the rate of increase of the intensity of the admitted networks decreases with the number of channels. By using graph theory, we obtain the minimum required number of channels to accommodate a certain intensity of coexisting networks under a self admission failure probability constraint. To this end, we design a superframe structure for the coexisting IEEE 802.15.4 networks and a method for time-domain interference alignment. © 2002-2012 IEEE.

  20. Real-life IT architecture design reports and their relation to IEEE Std 1471 stakeholders and concerns

    van Vliet, H.; Koning, H.

    2006-01-01

    Architectural designs are an important means to manage the development and deployment of information technology (IT). Much debate has been going on about a proper definition of architecture in IT and about how to describe it. In 2000, the IEEE Std 1471 proposed a model of an architecture description

  1. Architectural and Functional Design and Evaluation of E-Learning VUIS Based on the Proposed IEEE LTSA Reference Model.

    O'Droma, Mairtin S.; Ganchev, Ivan; McDonnell, Fergal

    2003-01-01

    Presents a comparative analysis from the Institute of Electrical and Electronics Engineers (IEEE) Learning Technology Standards Committee's (LTSC) of the architectural and functional design of e-learning delivery platforms and applications, e-learning course authoring tools, and learning management systems (LMSs), with a view of assessing how…

  2. Analyzing the Engineering Educational Research in Spain: A Global Vision through the Awards of CESEI-IEEE

    Plaza, I.; Arcega, F.; Castro, M.; Llamas, M.

    2011-01-01

    CESEI is the acronym of the Spanish Chapter of the Education Society of IEEE (the Institute of Electric and Electronics Engineers). Every year, the CESEI awards a prize for the best doctoral thesis and FDP (final (master) degree projects) about education. The thesis or the project must be developed in the areas of electrical engineering,…

  3. Analysis of Radio communication solutions in small and isolated communities under the IEEE 802.22 standard

    Arroyo Arzubi, Alejandro; Castro Lechtaler, Antonio; Foti, Antonio Roberto; Fusario, Rubén J.; García Guibout, Jorge; Sens, Lorena

    2013-01-01

    In recent years the use of wireless communications has increased significantly. Rural communities without cable network communication have found a solution in wireless technologies. Based on previous fieldwork, this paper analyzes software development of integration based technologies for communication equipment. It focuses on the feasibility of the IEEE 802.22 standard as a solution to the wireless problem.

  4. AVSS 2007: IEEE International Conference onAdvanced Video and Signal based Surveillance, London, UK, September 2007

    Fihl, Preben

    This technical report will cover the participation in the IEEE International Conference on Advanced Video and Signal based Surveillance in September 2007. The report will give a concise description of the most relevant topics presented at the conference, focusing on the work related to the HERMES...... project and human motion and action recognition. Our contribution to the conference will also be described....

  5. Low-cost RAU with Optical Power Supply Used in a Hybrid RoF IEEE 802.11 Network

    Kowalczyk, M.; Siuzdak, J.

    2014-09-01

    The paper presents design and implementation of a low-cost RAU (Remote Antenna Unit) device. It was designed to work in a hybrid Wi-Fi/optical network based on the IEEE 802.11b/g standard. An unique feature of the device is the possibility of optical power supply.

  6. Open Data for Global Multimodal Land Use Classification: Outcome of the 2017 IEEE GRSS Data Fusion Contest

    Yokoya, Naoto; Ghamisi, Pedram; Xia, Junshi; Sukhanov, Sergey; Heremans, Roel; Tankoyeu, Ivan; Bechtel, Benjamin; Saux, Le Bertrand; Moser, Gabriele; Tuia, Devis

    2018-01-01

    In this paper, we present the scientific outcomes of the 2017 Data Fusion Contest organized by the Image Analysis and Data Fusion Technical Committee of the IEEE Geoscience and Remote Sensing Society. The 2017 Contest was aimed at addressing the problem of local climate zones classification based on

  7. Real-Time Station Grouping under Dynamic Traffic for IEEE 802.11ah.

    Tian, Le; Khorov, Evgeny; Latré, Steven; Famaey, Jeroen

    2017-07-04

    IEEE 802.11ah, marketed as Wi-Fi HaLow, extends Wi-Fi to the sub-1 GHz spectrum. Through a number of physical layer (PHY) and media access control (MAC) optimizations, it aims to bring greatly increased range, energy-efficiency, and scalability. This makes 802.11ah the perfect candidate for providing connectivity to Internet of Things (IoT) devices. One of these new features, referred to as the Restricted Access Window (RAW), focuses on improving scalability in highly dense deployments. RAW divides stations into groups and reduces contention and collisions by only allowing channel access to one group at a time. However, the standard does not dictate how to determine the optimal RAW grouping parameters. The optimal parameters depend on the current network conditions, and it has been shown that incorrect configuration severely impacts throughput, latency and energy efficiency. In this paper, we propose a traffic-adaptive RAW optimization algorithm (TAROA) to adapt the RAW parameters in real time based on the current traffic conditions, optimized for sensor networks in which each sensor transmits packets with a certain (predictable) frequency and may change the transmission frequency over time. The TAROA algorithm is executed at each target beacon transmission time (TBTT), and it first estimates the packet transmission interval of each station only based on packet transmission information obtained by access point (AP) during the last beacon interval. Then, TAROA determines the RAW parameters and assigns stations to RAW slots based on this estimated transmission frequency. The simulation results show that, compared to enhanced distributed channel access/distributed coordination function (EDCA/DCF), the TAROA algorithm can highly improve the performance of IEEE 802.11ah dense networks in terms of throughput, especially when hidden nodes exist, although it does not always achieve better latency performance. This paper contributes with a practical approach to optimizing

  8. Performance Evaluation of IEEE 802.11ah Networks With High-Throughput Bidirectional Traffic.

    Šljivo, Amina; Kerkhove, Dwight; Tian, Le; Famaey, Jeroen; Munteanu, Adrian; Moerman, Ingrid; Hoebeke, Jeroen; De Poorter, Eli

    2018-01-23

    So far, existing sub-GHz wireless communication technologies focused on low-bandwidth, long-range communication with large numbers of constrained devices. Although these characteristics are fine for many Internet of Things (IoT) applications, more demanding application requirements could not be met and legacy Internet technologies such as Transmission Control Protocol/Internet Protocol (TCP/IP) could not be used. This has changed with the advent of the new IEEE 802.11ah Wi-Fi standard, which is much more suitable for reliable bidirectional communication and high-throughput applications over a wide area (up to 1 km). The standard offers great possibilities for network performance optimization through a number of physical- and link-layer configurable features. However, given that the optimal configuration parameters depend on traffic patterns, the standard does not dictate how to determine them. Such a large number of configuration options can lead to sub-optimal or even incorrect configurations. Therefore, we investigated how two key mechanisms, Restricted Access Window (RAW) grouping and Traffic Indication Map (TIM) segmentation, influence scalability, throughput, latency and energy efficiency in the presence of bidirectional TCP/IP traffic. We considered both high-throughput video streaming traffic and large-scale reliable sensing traffic and investigated TCP behavior in both scenarios when the link layer introduces long delays. This article presents the relations between attainable throughput per station and attainable number of stations, as well as the influence of RAW, TIM and TCP parameters on both. We found that up to 20 continuously streaming IP-cameras can be reliably connected via IEEE 802.11ah with a maximum average data rate of 160 kbps, whereas 10 IP-cameras can achieve average data rates of up to 255 kbps over 200 m. Up to 6960 stations transmitting every 60 s can be connected over 1 km with no lost packets. The presented results enable the fine tuning

  9. A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory.

    Chicca, E; Badoni, D; Dante, V; D'Andreagiovanni, M; Salina, G; Carota, L; Fusi, S; Del Giudice, P

    2003-01-01

    Electronic neuromorphic devices with on-chip, on-line learning should be able to modify quickly the synaptic couplings to acquire information about new patterns to be stored (synaptic plasticity) and, at the same time, preserve this information on very long time scales (synaptic stability). Here, we illustrate the electronic implementation of a simple solution to this stability-plasticity problem, recently proposed and studied in various contexts. It is based on the observation that reducing the analog depth of the synapses to the extreme (bistable synapses) does not necessarily disrupt the performance of the device as an associative memory, provided that 1) the number of neurons is large enough; 2) the transitions between stable synaptic states are stochastic; and 3) learning is slow. The drastic reduction of the analog depth of the synaptic variable also makes this solution appealing from the point of view of electronic implementation and offers a simple methodological alternative to the technological solution based on floating gates. We describe the full custom analog very large-scale integration (VLSI) realization of a small network of integrate-and-fire neurons connected by bistable deterministic plastic synapses which can implement the idea of stochastic learning. In the absence of stimuli, the memory is preserved indefinitely. During the stimulation the synapse undergoes quick temporary changes through the activities of the pre- and postsynaptic neurons; those changes stochastically result in a long-term modification of the synaptic efficacy. The intentionally disordered pattern of connectivity allows the system to generate a randomness suited to drive the stochastic selection mechanism. We check by a suitable stimulation protocol that the stochastic synaptic plasticity produces the expected pattern of potentiation and depression in the electronic network.

  10. Model, analysis, and evaluation of the effects of analog VLSI arithmetic on linear subspace-based image recognition.

    Carvajal, Gonzalo; Figueroa, Miguel

    2014-07-01

    Typical image recognition systems operate in two stages: feature extraction to reduce the dimensionality of the input space, and classification based on the extracted features. Analog Very Large Scale Integration (VLSI) is an attractive technology to achieve compact and low-power implementations of these computationally intensive tasks for portable embedded devices. However, device mismatch limits the resolution of the circuits fabricated with this technology. Traditional layout techniques to reduce the mismatch aim to increase the resolution at the transistor level, without considering the intended application. Relating mismatch parameters to specific effects in the application level would allow designers to apply focalized mismatch compensation techniques according to predefined performance/cost tradeoffs. This paper models, analyzes, and evaluates the effects of mismatched analog arithmetic in both feature extraction and classification circuits. For the feature extraction, we propose analog adaptive linear combiners with on-chip learning for both Least Mean Square (LMS) and Generalized Hebbian Algorithm (GHA). Using mathematical abstractions of analog circuits, we identify mismatch parameters that are naturally compensated during the learning process, and propose cost-effective guidelines to reduce the effect of the rest. For the classification, we derive analog models for the circuits necessary to implement Nearest Neighbor (NN) approach and Radial Basis Function (RBF) networks, and use them to emulate analog classifiers with standard databases of face and hand-writing digits. Formal analysis and experiments show how we can exploit adaptive structures and properties of the input space to compensate the effects of device mismatch at the application level, thus reducing the design overhead of traditional layout techniques. Results are also directly extensible to multiple application domains using linear subspace methods. Copyright © 2014 Elsevier Ltd. All rights

  11. VLSI Design of a Variable-Length FFT/IFFT Processor for OFDM-Based Communication Systems

    Jen-Chih Kuo

    2003-12-01

    Full Text Available The technique of {orthogonal frequency division multiplexing (OFDM} is famous for its robustness against frequency-selective fading channel. This technique has been widely used in many wired and wireless communication systems. In general, the {fast Fourier transform (FFT} and {inverse FFT (IFFT} operations are used as the modulation/demodulation kernel in the OFDM systems, and the sizes of FFT/IFFT operations are varied in different applications of OFDM systems. In this paper, we design and implement a variable-length prototype FFT/IFFT processor to cover different specifications of OFDM applications. The cached-memory FFT architecture is our suggested VLSI system architecture to design the prototype FFT/IFFT processor for the consideration of low-power consumption. We also implement the twiddle factor butterfly {processing element (PE} based on the {{coordinate} rotation digital computer (CORDIC} algorithm, which avoids the use of conventional multiplication-and-accumulation unit, but evaluates the trigonometric functions using only add-and-shift operations. Finally, we implement a variable-length prototype FFT/IFFT processor with TSMC 0.35 μm 1P4M CMOS technology. The simulations results show that the chip can perform (64-2048-point FFT/IFFT operations up to 80 MHz operating frequency which can meet the speed requirement of most OFDM standards such as WLAN, ADSL, VDSL (256∼2K, DAB, and 2K-mode DVB.

  12. An empirical evaluation of bufferbloat in IEEE 802.11n wireless networks

    Showail, Ahmad

    2014-04-06

    In this paper, we analyze the impact of large, persistently-full buffers (`bufferbloat\\') on various network dynamics in IEEE 802.11n wireless networks. Bufferbloat has mostly been studied in the context of wired networks. We study the impact of bufferbloat on a variety of wireless network topologies, including wireless LAN (WLAN) and multi-hop wireless networks. Our results show that a single FTP transfer between two Linux wireless hosts can saturate the buffers in the network stack, leading to RTT delays exceeding 4.5 s in multi-hop configurations. We show that well-designed Aggregate MAC Protocol Data Unit (A-MPDU) MAC-layer frame aggregation can reduce RTT delays while simultaneously increasing network throughput. However, additional measures may still be required to meet the constraints of real-time flows (such as VoIP). Our experiments show that large buffers can deteriorate the fairness in rate allocation in parking lot based multi-hop networks.

  13. Green Frame Aggregation Scheme for IEEE 802.11n Networks

    Alaslani, Maha S.

    2015-04-01

    Frame aggregation is one of the major MAC layer enhancements in the IEEE 802.11 family that boosts the network throughput performance. It aims to achieve higher throughput by transmitting huge amount of data in a single transmit oppor- tunity. With the increasing awareness of energy e ciency, it has become vital to rethink about the design of such frame aggregation protocol. Aggregation techniques help to reduce energy consumption over ideal channel conditions. However, in a noisy channel environment, a new energy-aware frame aggregation scheme is required. In this thesis, a novel Green Frame Aggregation (GFA) scheduling scheme has been proposed and evaluated. GFA optimizes the aggregate size based on channel quality in order to minimize the consumed energy. GFA selects the optimal sub-frame size that satisfies the loss constraint for real-time applications as well as the energy budget of the ideal channel situations. The design, the implementation, and evaluation of GFA using testbed deployment is done. The experimental analysis shows that GFA outperforms the conventional frame aggregation methodology in terms of energy e ciency by about 6⇥ in the presence of severe interference conditions. Moreover, GFA also outperforms the static frame sizing method in terms of network goodput and maintains almost the same end- to-end latency.

  14. Smart City Pilot Projects Using LoRa and IEEE802.15.4 Technologies.

    Pasolini, Gianni; Buratti, Chiara; Feltrin, Luca; Zabini, Flavio; De Castro, Cristina; Verdone, Roberto; Andrisano, Oreste

    2018-04-06

    Information and Communication Technologies (ICTs), through wireless communications and the Internet of Things (IoT) paradigm, are the enabling keys for transforming traditional cities into smart cities, since they provide the core infrastructure behind public utilities and services. However, to be effective, IoT-based services could require different technologies and network topologies, even when addressing the same urban scenario. In this paper, we highlight this aspect and present two smart city testbeds developed in Italy. The first one concerns a smart infrastructure for public lighting and relies on a heterogeneous network using the IEEE 802.15.4 short-range communication technology, whereas the second one addresses smart-building applications and is based on the LoRa low-rate, long-range communication technology. The smart lighting scenario is discussed providing the technical details and the economic benefits of a large-scale (around 3000 light poles) flexible and modular implementation of a public lighting infrastructure, while the smart-building testbed is investigated, through measurement campaigns and simulations, assessing the coverage and the performance of the LoRa technology in a real urban scenario. Results show that a proper parameter setting is needed to cover large urban areas while maintaining the airtime sufficiently low to keep packet losses at satisfactory levels.

  15. IEEE 802.11-Based Wireless Sensor System for Vibration Measurement

    Yutaka Uchimura

    2010-01-01

    Full Text Available Network-based wireless sensing has become an important area of research and various new applications for remote sensing are expected to emerge. One of the promising applications is structural health monitoring of building or civil engineering structure and it often requires vibration measurement. For the vibration measurement via wireless network, time synchronization is indispensable. In this paper, we introduce a newly developed time synchronized wireless sensor network system. The system employs IEEE 802.11 standard-based TSF-counter and sends the measured data with the counter value. TSF based synchronization enables consistency on common clock among different wireless nodes. We consider the scale effect on synchronization accuracy and evaluated the effect by taking beacon collisions into account. The scalability issue by numerical simulations is also studied. This paper also introduces a newly developed wireless sensing system and the hardware and software specifications are introduced. The experiments were conducted in a reinforced concrete building to evaluate synchronization accuracy. The developed system was also applied for a vibration measurement of a 22-story steel structured high rise building. The experimental results showed that the system performed more than sufficiently.

  16. The Impact of Dynamic RTS Threshold Adjustment for IEEE 802.11 MAC Protocol

    Mostafa Mjidi

    2009-01-01

    Full Text Available In recent years, wireless technologies and application received great attention. The Medium Access Control (MAC protocol is the main element that determines the efficiency in sharing the limited communication bandwidth of the wireless channel in wireless local area networks (WLANs. IEEE 802.11 introduced the optional RTS/CTS handshaking mechanism to address the hidden terminal problem as well as to reduces the chance of collision in case of higher node density and traffic. RTS Threshold (RT determines when RTS/CTS mechanism should be used and proved to be an important parameter for performance characteristics in data transmission. We first investigate to find a meaningful threshold value according to the network situation and determine the impact of using or disengaging the RTS/CTS optional mechanism and dynamically adjust the RTS Threshold to maximize data transmission. The results show a significant improvement over existing CSMA/CA and RTS/CTS schemes. Our adaptive scheme performed even better when data rate increases. We verify our proposed scheme both analytically and with extensive network simulation using ns-2.

  17. An empirical evaluation of bufferbloat in IEEE 802.11n wireless networks

    Showail, Ahmad; Jamshaid, Kamran; Shihada, Basem

    2014-01-01

    In this paper, we analyze the impact of large, persistently-full buffers (`bufferbloat') on various network dynamics in IEEE 802.11n wireless networks. Bufferbloat has mostly been studied in the context of wired networks. We study the impact of bufferbloat on a variety of wireless network topologies, including wireless LAN (WLAN) and multi-hop wireless networks. Our results show that a single FTP transfer between two Linux wireless hosts can saturate the buffers in the network stack, leading to RTT delays exceeding 4.5 s in multi-hop configurations. We show that well-designed Aggregate MAC Protocol Data Unit (A-MPDU) MAC-layer frame aggregation can reduce RTT delays while simultaneously increasing network throughput. However, additional measures may still be required to meet the constraints of real-time flows (such as VoIP). Our experiments show that large buffers can deteriorate the fairness in rate allocation in parking lot based multi-hop networks.

  18. On the Optimization of the IEEE 802.11 DCF: A Cross-Layer Perspective

    Massimiliano Laddomada

    2010-01-01

    Full Text Available This paper is focused on the problem of optimizing the aggregate throughput of the distributed coordination function (DCF employing the basic access mechanism at the data link layer of IEEE 802.11 protocols. We consider general operating conditions accounting for both nonsaturated and saturated traffic in the presence of transmission channel errors, as exemplified by the packet error rate . The main clue of this work stems from the relation that links the aggregate throughput of the network to the packet rate of the contending stations. In particular, we show that the aggregate throughput ( presents two clearly distinct operating regions that depend on the actual value of the packet rate with respect to a critical value , theoretically derived in this work. The behavior of ( paves the way to a cross-layer optimization algorithm, which proved to be effective for maximizing the aggregate throughput in a variety of network operating conditions. A nice consequence of the proposed optimization framework relies on the fact that the aggregate throughput can be predicted quite accurately with a simple, yet effective, closed-form expression. Finally, theoretical and simulation results are presented in order to unveil, as well as verify, the key ideas.

  19. An SNMP-based solution to enable remote ISO/IEEE 11073 technical management.

    Lasierra, Nelia; Alesanco, Alvaro; García, José

    2012-07-01

    This paper presents the design and implementation of an architecture based on the integration of simple network management protocol version 3 (SNMPv3) and the standard ISO/IEEE 11073 (X73) to manage technical information in home-based telemonitoring scenarios. This architecture includes the development of an SNMPv3-proxyX73 agent which comprises a management information base (MIB) module adapted to X73. In the proposed scenario, medical devices (MDs) send information to a concentrator device [designated as compute engine (CE)] using the X73 standard. This information together with extra information collected in the CE is stored in the developed MIB. Finally, the information collected is available for remote access via SNMP connection. Moreover, alarms and events can be configured by an external manager in order to provide warnings of irregularities in the MDs' technical performance evaluation. This proposed SNMPv3 agent provides a solution to integrate and unify technical device management in home-based telemonitoring scenarios fully adapted to X73.

  20. New IEEE 11073 Standards for interoperable, networked Point-of-Care Medical Devices.

    Kasparick, Martin; Schlichting, Stefan; Golatowski, Frank; Timmermann, Dirk

    2015-08-01

    Surgical procedures become more and more complex and the number of medical devices in an operating room (OR) increases continuously. Today's vendor-dependent solutions for integrated ORs are not able to handle this complexity. They can only form isolated solutions. Furthermore, high costs are a result of vendor-dependent approaches. Thus we present a service-oriented device communication for distributed medical systems that enables the integration and interconnection between medical devices among each other and to (medical) information systems, including plug-and-play functionality. This system will improve patient's safety by making technical complexity of a comprehensive integration manageable. It will be available as open standards that are part of the IEEE 11073 family of standards. The solution consists of a service-oriented communication technology, the so called Medical Devices Profile for Web Services (MDPWS), a Domain Information & Service Model, and a binding between the first two mechanisms. A proof of this concept has been done with demonstrators of real world OR devices.

  1. IEEE-802.15.4-based low-power body sensor node with RF energy harvester.

    Tran, Thang Viet; Chung, Wan-Young

    2014-01-01

    This paper proposes the design and implementation of a low-voltage and low-power body sensor node based on the IEEE 802.15.4 standard to collect electrocardiography (ECG) and photoplethysmography (PPG) signals. To achieve compact size, low supply voltage, and low power consumption, the proposed platform is integrated into a ZigBee mote, which contains a DC-DC booster, a PPG sensor interface module, and an ECG front-end circuit that has ultra-low current consumption. The input voltage of the proposed node is very low and has a wide range, from 0.65 V to 3.3 V. An RF energy harvester is also designed to charge the battery during the working mode or standby mode of the node. The power consumption of the proposed node reaches 14 mW in working mode to prolong the battery lifetime. The software is supported by the nesC language under the TinyOS environment, which enables the proposed node to be easily configured to function as an individual health monitoring node or a node in a wireless body sensor network (BSN). The proposed node is used to set up a wireless BSN that can simultaneously collect ECG and PPG signals and monitor the results on the personal computer.

  2. An Enhanced Reservation-Based MAC Protocol for IEEE 802.15.4 Networks

    Afonso, José A.; Silva, Helder D.; Macedo, Pedro; Rocha, Luis A.

    2011-01-01

    The IEEE 802.15.4 Medium Access Control (MAC) protocol is an enabling standard for wireless sensor networks. In order to support applications requiring dedicated bandwidth or bounded delay, it provides a reservation-based scheme named Guaranteed Time Slot (GTS). However, the GTS scheme presents some drawbacks, such as inefficient bandwidth utilization and support to a maximum of only seven devices. This paper presents eLPRT (enhanced Low Power Real Time), a new reservation-based MAC protocol that introduces several performance enhancing features in comparison to the GTS scheme. This MAC protocol builds on top of LPRT (Low Power Real Time) and includes various mechanisms designed to increase data transmission reliability against channel errors, improve bandwidth utilization and increase the number of supported devices. A motion capture system based on inertial and magnetic sensors has been used to validate the protocol. The effectiveness of the performance enhancements introduced by each of the new features is demonstrated through the provision of both simulation and experimental results. PMID:22163826

  3. Link Investigation of IEEE 802.15.4 Wireless Sensor Networks in Forests.

    Ding, Xingjian; Sun, Guodong; Yang, Gaoxiang; Shang, Xinna

    2016-06-27

    Wireless sensor networks are expected to automatically monitor the ecological evolution and wildlife habits in forests. Low-power links (transceivers) are often adopted in wireless sensor network applications, in order to save the precious sensor energy and then achieve long-term, unattended monitoring. Recent research has presented some performance characteristics of such low-power wireless links under laboratory or outdoor scenarios with less obstacles, and they have found that low-power wireless links are unreliable and prone to be affected by the target environment. However, there is still less understanding about how well the low-power wireless link performs in real-world forests and to what extent the complex in-forest surrounding environments affect the link performances. In this paper, we empirically evaluate the low-power links of wireless sensors in three typical different forest environments. Our experiment investigates the performance of the link layer compatible with the IEEE 802.15.4 standard and analyzes the variation patterns of the packet reception ratio (PRR), the received signal strength indicator (RSSI) and the link quality indicator (LQI) under diverse experimental settings. Some observations of this study are inconsistent with or even contradict prior results that are achieved in open fields or relatively clean environments and thus, provide new insights both into effectively evaluating the low-power wireless links and into efficiently deploying wireless sensor network systems in forest environments.

  4. Low-power secure body area network for vital sensors toward IEEE802.15.6.

    Kuroda, Masahiro; Qiu, Shuye; Tochikubo, Osamu

    2009-01-01

    Many healthcare/medical services have started using personal area networks, such as Bluetooth and ZigBee; these networks consist of various types of vital sensors. These works focus on generalized functions for sensor networks that expect enough battery capacity and low-power CPU/RF (Radio Frequency) modules, but less attention to easy-to-use privacy protection. In this paper, we propose a commercially-deployable secure body area network (S-BAN) with reduced computational burden on a real sensor that has limited RAM/ROM sizes and CPU/RF power consumption under a light-weight battery. Our proposed S-BAN provides vital data ordering among sensors that are involved in an S-BAN and also provides low-power networking with zero-administration security by automatic private key generation. We design and implement the power-efficient media access control (MAC) with resource-constraint security in sensors. Then, we evaluate the power efficiency of the S-BAN consisting of small sensors, such as an accessory type ECG and ring-type SpO2. The evaluation of power efficiency of the S-BAN using real sensors convinces us in deploying S-BAN and will also help us in providing feedbacks to the IEEE802.15.6 MAC, which will be the standard for BANs.

  5. SIMULADOR INTERACTIVO DE REDES INALÁMBRICAS BASADAS EN IEEE802.11a

    Arturo Infante Riello

    2010-09-01

    Full Text Available Normal 0 21 false false false ES-TRAD X-NONE X-NONE MicrosoftInternetExplorer4 /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} Este artículo presenta los fundamentos y características básicas del diseño de un simulador de redes inalámbricas basadas en el estándar IEEE802.11a, mostrando aspectos de la capa física, canal de radio, programación e interfaz de usuario.

  6. Smart City Pilot Projects Using LoRa and IEEE802.15.4 Technologies

    Gianni Pasolini

    2018-04-01

    Full Text Available Information and Communication Technologies (ICTs, through wireless communications and the Internet of Things (IoT paradigm, are the enabling keys for transforming traditional cities into smart cities, since they provide the core infrastructure behind public utilities and services. However, to be effective, IoT-based services could require different technologies and network topologies, even when addressing the same urban scenario. In this paper, we highlight this aspect and present two smart city testbeds developed in Italy. The first one concerns a smart infrastructure for public lighting and relies on a heterogeneous network using the IEEE 802.15.4 short-range communication technology, whereas the second one addresses smart-building applications and is based on the LoRa low-rate, long-range communication technology. The smart lighting scenario is discussed providing the technical details and the economic benefits of a large-scale (around 3000 light poles flexible and modular implementation of a public lighting infrastructure, while the smart-building testbed is investigated, through measurement campaigns and simulations, assessing the coverage and the performance of the LoRa technology in a real urban scenario. Results show that a proper parameter setting is needed to cover large urban areas while maintaining the airtime sufficiently low to keep packet losses at satisfactory levels.

  7. Signaling-Free Max-Min Airtime Fairness in IEEE 802.11 Ad Hoc Networks

    Youngsoo Lee

    2016-01-01

    Full Text Available We propose a novel media access control (MAC protocol, referred to as signaling-free max-min airtime fair (SMAF MAC, to improve fairness and channel utilization in ad hoc networks based on IEEE 802.11 wireless local area networks (WLANs. We introduce busy time ratio (BTR as a measure for max-min airtime fairness. Each node estimates its BTR and adjusts the transmission duration by means of frame aggregation and fragmentation, so that it can implicitly announce the BTR to neighbor nodes. Based on the announced BTR, each of the neighbor nodes controls its contention window. In this way, the SMAF MAC works in a distributed manner without the need to know the max-min fair share of airtime, and it does not require exchanging explicit control messages among nodes to attain fairness. Moreover, we successfully incorporate the hidden node detection and resolution mechanisms into the SMAF MAC to deal with the hidden node problem in ad hoc networks. The simulation results confirm that the SMAF MAC enhances airtime fairness without degrading channel utilization, and it effectively resolves several serious problems in ad hoc networks such as the starvation, performance anomaly, and hidden node problems.

  8. Achievable Throughput-Based MAC Layer Handoff in IEEE 802.11 Wireless Local Area Networks

    Wu Haitao

    2009-01-01

    Full Text Available We propose a MAC layer handoff mechanism for IEEE 802.11 Wireless Local Area Networks (WLAN to give benefit to bandwidth-greedy applications at STAs. The proposed mechanism determines an optimal AP with the maximum achievable throughput rather than the best signal condition by estimating the AP's bandwidth with a new on-the-fly measurement method, Transient Frame Capture (TFC, and predicting the actual throughput could be achieved at STAs. Since the TFC is employed based on the promiscuous mode of WLAN NIC, STAs can avoid the service degradation through the current associated AP. In addition, the proposed mechanism is a client-only solution which does not require any modification of network protocol on APs. To evaluate the performance of the proposed mechanism, we develop an analytic model to estimate reliable and accurate bandwidth of the AP and demonstrate through testbed measurement with various experimental study methods. We also validate the fairness of the proposed mechanism through simulation studies.

  9. BER IMPROVEMENT OF WIRELESS LAN IEEE 802.11 STANDARD USING WAVELET PACKET TRANSFORMS

    Sanjeev Kumar

    2012-09-01

    Full Text Available High data rates and spectral efficiency is the main requirements for wireless communication systems. Orthogonal Frequency Division Multiplexing (OFDM is a special form of multi carrier transmission used to achieve high data rates of the various WLAN standards. WLAN uses an Inverse Fast Fourier Transform (IFFT at the transmitter to modulate a high bit-rate signal onto a number of carriers and ensure orthogonality between the carriers. The FFT-OFDM has a disadvantage that it is inherently inflexible and requires a complex IFFT core. Recently, Wavelet Packet Transform is proposed as an alternate to FFT. It is a multiplexing method in which data is assigned to wavelet sub bands having different time and frequency resolutions. This paper presents a BER analysis of Fourier-based OFDM (FFT-OFDM and Wavelet Packet based OFDM (WPT-OFDM in WLAN standard (IEEE 802.11a. The performance of FFT and WPT OFDM for various modulation techniques such as PSK, DPSK and QAM for varying values of M was evaluated in AWGN Channel.

  10. Cross-layer TCP Performance Analysis in IEEE 802.11 Vehicular Environments

    T. Janevski

    2014-06-01

    Full Text Available In this paper we provide a performance analysis of TCP in IEEE 802.11 vehicular environments for different well-known TCP versions, such as Tahoe, Reno, New Reno, Vegas, and Sack. The parameters of interest from the TCP side are the number of Duplicate Acknowledgements - DupAck, and the number of Delayed Acknowledgements - DelAck, while on the wireless network side the analyzed parameter is the interface queue - IFQ. We have made the analysis for the worst-case distance scenario for single-hop and worst-case multihop vehicular environments. The results show that the number of wireless hops in vehicular environments significantly reduces the TCP throughput. The best average performances considering all scenarios were obtained for TCP Vegas. However, the results show that the interface queue at wireless nodes should be at least five packets or more. On the other side, due to shorter distances in the vehicular wireless network, results show possible flexibility of using different values for the DupAck without degradation of the TCP throughput. On the other side, the introduction of the DelAck parameter provides enhancement in the average TCP throughput for all TCP versions.

  11. A IEEE 802.11e HCCA Scheduler with a Reclaiming Mechanism for Multimedia Applications

    Anna Lina Ruscelli

    2014-01-01

    Full Text Available The QoS offered by the IEEE 802.11e reference scheduler is satisfactory in the case of Constant Bit Rate traffic streams, but not yet in the case of Variable Bit Rate traffic streams, whose variations stress its scheduling behavior. Despite the numerous proposed alternative schedulers with QoS, multimedia applications are looking for refined methods suitable to ensure service differentiation and dynamic update of protocol parameters. In this paper a scheduling algorithm, Unused Time Shifting Scheduler (UTSS, is deeply analyzed. It is designed to cooperate with a HCCA centralized real-time scheduler through the integration of a bandwidth reclaiming scheme, suitable to recover nonexhausted transmission time and assign that to the next polled stations. UTSS dynamically computes with an O(1 complexity transmission time providing an instantaneous resource overprovisioning. The theoretical analysis and the simulation results highlight that this injection of resources does not affect the admission control nor the centralized scheduler but is suitable to improve the performance of the centralized scheduler in terms of mean access delay, transmission queues length, bursts of traffic management, and packets drop rate. These positive effects are more relevant for highly variable bit rate traffic.

  12. A micro-strip gas counter test with the RD20 front-end

    Clergeau, J.F.; Contardo, D.; Haroutunian, R.; Smadja, G.

    1994-05-01

    A Micro-Strip Gas Counter equipped with the VLSI preamplifier of the RD20 chip has been tested with minimum ionizing particles. The measured pulse shape and the signal to noise ratio are presented. The time resolution of the detector is compared for the Ar/DME and DME/CO 2 gas mixtures. Three methods for the bunch crossing identification at LHC are discussed. (authors). 5 refs., 7 figs., 3 tabs

  13. Real-Time Support on IEEE 802.11 Wireless Ad-Hoc Networks: Reality vs. Theory

    Kang, Mikyung; Kang, Dong-In; Suh, Jinwoo

    The usable throughput of an IEEE 802.11 system for an application is much less than the raw bandwidth. Although 802.11b has a theoretical maximum of 11Mbps, more than half of the bandwidth is consumed by overhead leaving at most 5Mbps of usable bandwidth. Considering this characteristic, this paper proposes and analyzes a real-time distributed scheduling scheme based on the existing IEEE 802.11 wireless ad-hoc networks, using USC/ISI's Power Aware Sensing Tracking and Analysis (PASTA) hardware platform. We compared the distributed real-time scheduling scheme with the real-time polling scheme to meet deadline, and compared a measured real bandwidth with a theoretical result. The theoretical and experimental results show that the distributed scheduling scheme can guarantee real-time traffic and enhances the performance up to 74% compared with polling scheme.

  14. Diseño y verificación de un amplificador para IEEE802.16

    Lloret Arjona, Patricia

    2005-01-01

    Hace más de 6 años se empezó a gestar el IEEE802.16, un estándar para una nueva tecnología inalámbrica de banda ancha. El primer capítulo consiste en una introducción sobre este estándar, su evolución, las diferentes versiones que han ido apareciendo y las características principales de cada una de ellas, seguido de un pequeño comentario sobre su faceta comercial, WiMAX. El IEEE802.16 está empezando a tener relevancia, de modo que se decidió realizar un amplificador capaz de...

  15. The Performance Evaluation of an IEEE 802.11 Network Containing Misbehavior Nodes under Different Backoff Algorithms

    Trong-Minh Hoang

    2017-01-01

    Full Text Available Security of any wireless network is always an important issue due to its serious impacts on network performance. Practically, the IEEE 802.11 medium access control can be violated by several native or smart attacks that result in downgrading network performance. In recent years, there are several studies using analytical model to analyze medium access control (MAC layer misbehavior issue to explore this problem but they have focused on binary exponential backoff only. Moreover, a practical condition such as the freezing backoff issue is not included in the previous models. Hence, this paper presents a novel analytical model of the IEEE 802.11 MAC to thoroughly understand impacts of misbehaving node on network throughput and delay parameters. Particularly, the model can express detailed backoff algorithms so that the evaluation of the network performance under some typical attacks through numerical simulation results would be easy.

  16. IEEE standard requirements for reliability analysis in the design and operation of safety systems for nuclear power generating stations

    Anon.

    1976-01-01

    The purpose of this standard is to provide uniform, minimum acceptable requirements for the performance of reliability analyses for safety-related systems found in nuclear-power generating stations, but not to define the need for an analysis. The need for reliability analysis has been identified in other standards which expand the requirements of regulations (e.g., IEEE Std 379-1972 (ANSI N41.2-1972), ''Guide for the Application of the Single-Failure Criterion to Nuclear Power Generating Station Protection System,'' which describes the application of the single-failure criterion). IEEE Std 352-1975, ''Guide for General Principles of Reliability Analysis of Nuclear Power Generating Station Protection Systems,'' provides guidance in the application and use of reliability techniques referred to in this standard

  17. VLSI implementation of MIMO detection for 802.11n using a novel adaptive tree search algorithm

    Yao Heng; Jian Haifang; Zhou Liguo; Shi Yin

    2013-01-01

    A 4×4 64-QAM multiple-input multiple-output (MIMO) detector is presented for the application of an IEEE 802.11n wireless local area network. The detectoris the implementation of a novel adaptive tree search(ATS) algorithm, and multiple ATS cores need to be instantiated to achieve the wideband requirement in the 802.11n standard. Both the ATS algorithm and the architectural considerations are explained. The latency of the detector is 0.75 μs, and the detector has a gate count of 848 k with a total of 19 parallel ATS cores. Each ATS core runs at 67 MHz. Measurement results show that compared with the floating-point ATS algorithm, the fixed-point implementation achieves a loss of 0.9 dB at a BER of 10 −3 . (semiconductor integrated circuits)

  18. Error detecting capabilities of the shortened Hamming codes adopted for error detection in IEEE Standard 802.3

    Fujiwara, Toru; Kasami, Tadao; Lin, Shu

    1989-09-01

    The error-detecting capabilities of the shortened Hamming codes adopted for error detection in IEEE Standard 802.3 are investigated. These codes are also used for error detection in the data link layer of the Ethernet, a local area network. The weight distributions for various code lengths are calculated to obtain the probability of undetectable error and that of detectable error for a binary symmetric channel with bit-error rate between 0.00001 and 1/2.

  19. Comparison and Analysis of IEEE 344 and IEC 60980 standards for harmonization of seismic qualification of safety-related equipment

    Lee, Young Ok; Kim, Jong Seog; Seo, Jeong Ho; Kim, Myung Jun

    2011-01-01

    The seismic qualification of safety related equipment in nuclear power plants should demonstrate an equipment's ability to perform its safety function during/or after the time it is subjected to the forces resulting from one SSE. In addition, the equipment must withstand the effects of a number of OBEs, preceding the SSE. IEEE 344 and IEC 60980 present the criteria for establishing procedures demonstrating that the Class 1E equipment can meet its performance requirement during seismic events. Currently, IEEE 344 is used for regulation of nuclear power plant in the United State whereas IEC 60980 is mainly used in Europe. In particular, NPPs of France and China apply with RCC-E and GB that are domestic standards, respectively. Equipment supplier and Utility have difficulties because of different applicable standards. Equipment supplier to export S/R components/equipment to other standard area performs additional seismic qualification. For example, equipment are qualifies according to IEC 60980, RCC-E, GB although they have been qualified in accordance with IEEE 344. Also, utility to attempt power up-rate, life extension of NPP constructed under rules of RCC-E such as Ulchin NPP 1 and 2 has similar difficulties. RCC-E endorses IEC 60980 and GB is almost same as IEC 60980 except minor difference of earthquake environment definition. Therefore this paper surveys the similarities and differences between IEEE 344 and IEC 60980. In addition, this paper considers how the two sets of standards may be used in a complementary fashion to be possible using one or the other standard area

  20. Introduction to the special issue on the 2011 Joint IEEE International Frequency Control Symposium and European Frequency and Time Forum.

    Burt, Eric; Gill, Patrick

    2012-03-01

    The 8 invited and 17 contributed papers in this special issue focus on the following topical areas covered at the 2011 Joint IEEE International Frequency Control Symposium and European Frequency and Time Forum, held in San Francisco, California: 1) Materials and Resonators; 2) Oscillators, Synthesizers, and Noise; 3) Microwave Frequency Standards; 4) Sensors and Transducers; 5) Timekeeping and Time and Frequency Transfer; and 6) Optical Frequency Standards.