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Sample records for hybrid gate dielectric

  1. Hybrid gate dielectric materials for unconventional electronic circuitry.

    Science.gov (United States)

    Ha, Young-Geun; Everaerts, Ken; Hersam, Mark C; Marks, Tobin J

    2014-04-15

    Recent advances in semiconductor performance made possible by organic π-electron molecules, carbon-based nanomaterials, and metal oxides have been a central scientific and technological research focus over the past decade in the quest for flexible and transparent electronic products. However, advances in semiconductor materials require corresponding advances in compatible gate dielectric materials, which must exhibit excellent electrical properties such as large capacitance, high breakdown strength, low leakage current density, and mechanical flexibility on arbitrary substrates. Historically, conventional silicon dioxide (SiO2) has dominated electronics as the preferred gate dielectric material in complementary metal oxide semiconductor (CMOS) integrated transistor circuitry. However, it does not satisfy many of the performance requirements for the aforementioned semiconductors due to its relatively low dielectric constant and intransigent processability. High-k inorganics such as hafnium dioxide (HfO2) or zirconium dioxide (ZrO2) offer some increases in performance, but scientists have great difficulty depositing these materials as smooth films at temperatures compatible with flexible plastic substrates. While various organic polymers are accessible via chemical synthesis and readily form films from solution, they typically exhibit low capacitances, and the corresponding transistors operate at unacceptably high voltages. More recently, researchers have combined the favorable properties of high-k metal oxides and π-electron organics to form processable, structurally well-defined, and robust self-assembled multilayer nanodielectrics, which enable high-performance transistors with a wide variety of unconventional semiconductors. In this Account, we review recent advances in organic-inorganic hybrid gate dielectrics, fabricated by multilayer self-assembly, and their remarkable synergy with unconventional semiconductors. We first discuss the principals and functional

  2. Tunable Radiation Response in Hybrid Organic-Inorganic Gate Dielectrics for Low-Voltage Graphene Electronics.

    Science.gov (United States)

    Arnold, Heather N; Cress, Cory D; McMorrow, Julian J; Schmucker, Scott W; Sangwan, Vinod K; Jaber-Ansari, Laila; Kumar, Rajan; Puntambekar, Kanan P; Luck, Kyle A; Marks, Tobin J; Hersam, Mark C

    2016-03-01

    Solution-processed semiconductor and dielectric materials are attractive for future lightweight, low-voltage, flexible electronics, but their response to ionizing radiation environments is not well understood. Here, we investigate the radiation response of graphene field-effect transistors employing multilayer, solution-processed zirconia self-assembled nanodielectrics (Zr-SANDs) with ZrOx as a control. Total ionizing dose (TID) testing is carried out in situ using a vacuum ultraviolet source to a total radiant exposure (RE) of 23.1 μJ/cm(2). The data reveal competing charge density accumulation within and between the individual dielectric layers. Additional measurements of a modified Zr-SAND show that varying individual layer thicknesses within the gate dielectric tuned the TID response. This study thus establishes that the radiation response of graphene electronics can be tailored to achieve a desired radiation sensitivity by incorporating hybrid organic-inorganic gate dielectrics.

  3. PMMA–SiO{sub 2} hybrid films as gate dielectric for ZnO based thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Morales-Acosta, M.D. [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico); Quevedo-López, M.A. [Department of Materials Science and Engineering, The University of Texas at Dallas, Richardson, TX 75083 (United States); Ramírez-Bon, R., E-mail: rrbon@qro.cinvestav.mx [Centro de Investigación y de Estudios Avanzados del IPN, Unidad Querétaro, Apdo. Postal 1-798, Querétaro, Qro. 76001 (Mexico)

    2014-08-01

    In this paper we report a low temperature sol–gel deposition process of PMMA–SiO{sub 2} hybrid films, with variable dielectric properties depending on the composition of the precursor solution, for applications to gate dielectric layers in field-effect thin film transistors (FE-TFT). The hybrid layers were processed by a modified sol–gel route using as precursors Tetraethyl orthosilicate (TEOS) and Methyl methacrylate (MMA), and 3-(Trimethoxysilyl)propyl methacrylate (TMSPM) as the coupling agent. Three types of hybrid films were processed with molar ratios of the precursors in the initial solution 1.0: 0.25, 0.50, 0.75: 1.0 for TEOS: TMSPM: MMA, respectively. The hybrid films were deposited by spin coating of the hybrid precursor solutions onto p-type Si (100) substrates and heat-treated at 90 °C for 24 h. The chemical bonding in the hybrid films was analyzed by Fourier Transform Infrared Spectroscopy to confirm their hybrid nature. The refractive index of the hybrid films as a function of the TMSPM coupling agent concentration, were determined from a simultaneous analysis of optical reflectance and spectroscopic ellipsometry experimental data. The PMMA–SiO{sub 2} hybrid films were studied as dielectric films using metal-insulator-metal structures. Capacitance–Voltage (C–V) and current–voltage (I–V) electrical methods were used to extract the dielectric properties of the different hybrid layers. The three types of hybrid films were tested as gate dielectric layers in thin film transistors with structure ZnO/PMMA–SiO{sub 2}/p-Si with a common bottom gate and patterned Al source/drain contacts, with different channel lengths. We analyzed the output electrical responses of the ZnO-based TFTs to determine their performance parameters as a function of channel length and hybrid gate dielectric layer. - Highlights: • PMMA–SiO{sub 2} hybrid films as dielectric material synthesized by sol–gel process at low temperature. • PMMA–SiO{sub 2

  4. Flexible SiInZnO thin film transistor with organic/inorganic hybrid gate dielectric processed at 150 °C

    Science.gov (United States)

    Choi, J. Y.; Kim, S.; Hwang, B.-U.; Lee, N.-E.; Lee, S. Y.

    2016-12-01

    Silicon indium zinc oxide (SIZO) thin film transistors (TFTs) have been fabricated on a flexible polyimide (PI) substrate by using organic/inorganic hybrid gate dielectrics of poly-4vinyl phenol (PVP) and Al2O3. To improve the mechanical stability, Al2O3 has been used as a buffer layer on the flexible substrate. The Al2O3 layer of hybrid gate dielectrics protected the organic gate dielectric and improved mechanical flexibility. The different surface roughness of the gate dielectrics is investigated. The performance of the device with smooth surface roughness was significantly improved. Finally, the electrical characteristics of the TFTs with hybrid gate dielectrics were measured as well as the promising electrical endurance characteristics at the bending radius of 5 mm.

  5. High permittivity gate dielectric materials

    CERN Document Server

    2013-01-01

    "The book comprehensively covers all the current and the emerging areas of the physics and the technology of high permittivity gate dielectric materials, including, topics such as MOSFET basics and characteristics, hafnium-based gate dielectric materials, Hf-based gate dielectric processing, metal gate electrodes, flat-band and threshold voltage tuning, channel mobility, high-k gate stack degradation and reliability, lanthanide-based high-k gate stack materials, ternary hafnia and lanthania based high-k gate stack films, crystalline high-k oxides, high mobility substrates, and parameter extraction. Each chapter begins with the basics necessary for understanding the topic, followed by a comprehensive review of the literature, and ultimately graduating to the current status of the technology and our scientific understanding and the future prospects."

  6. Synthesis and electrical characterization of low-temperature thermal-cured epoxy resin/functionalized silica hybrid-thin films for application as gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Na, Moonkyong, E-mail: nmk@keri.re.kr [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); System on Chip Chemical Process Research Center, Department of Chemical Engineering, Pohang University of Science and Technology (POSTECH), Pohang, 790-784 (Korea, Republic of); Kang, Young Taec [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Department of Polymer Science and Engineering, Pusan National University, Busan, 609-735 (Korea, Republic of); Kim, Sang Cheol [HVDC Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of); Kim, Eun Dong [Creative and Fundamental Research Division, Korea Electrotechnology Research Institute, Changwon, 642-120 (Korea, Republic of)

    2013-07-31

    Thermal-cured hybrid materials were synthesized from homogenous hybrid sols of epoxy resins and organoalkoxysilane-functionalized silica. The chemical structures of raw materials and obtained hybrid materials were characterized using Fourier transform infrared spectroscopy. The thermal resistance of the hybrids was enhanced by hybridization. The interaction between epoxy matrix and the silica particles, which caused hydrogen bonding and van der Waals force was strengthened by organoalkoxysilane. The degradation temperature of the hybrids was improved by approximately 30 °C over that of the parent epoxy material. The hybrid materials were formed into uniformly coated thin films of about 50 nm-thick using a spin coater. An optimum mixing ratio was used to form smooth-surfaced hybrid films. The electrical property of the hybrid film was characterized, and the leakage current was found to be well below 10{sup −6} A cm{sup −2}. - Highlights: • Preparation of thermal-curable hybrid materials using epoxy resin and silica. • The thermal stability was enhanced through hybridization. • The insulation property of hybrid film was investigated as gate dielectrics.

  7. Materials Fundamentals of Gate Dielectrics

    CERN Document Server

    Demkov, Alexander A

    2006-01-01

    This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

  8. Electric field-induced transport modulation in VO2 FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    Science.gov (United States)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta2O5/organic parylene-C hybrid dielectric-gated VO2 thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO2 through the electrostatic field-induced transport modulation.

  9. Electric field-induced transport modulation in VO{sub 2} FETs with high-k oxide/organic parylene-C hybrid gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Wei, Tingting [Institute of Scientific and Industrial Research, Osaka University, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047 (Japan); Faculty of Science, Kunming University of Science and Technology, Kunming 650093 (China); Kanki, Teruo, E-mail: kanki@sanken.osaka-u.ac.jp, E-mail: h-tanaka@sanken.osaka-u.ac.jp; Chikanari, Masashi; Tanaka, Hidekazu, E-mail: kanki@sanken.osaka-u.ac.jp, E-mail: h-tanaka@sanken.osaka-u.ac.jp [Institute of Scientific and Industrial Research, Osaka University, 8-1 Mihogaoka, Ibaraki, Osaka 567-0047 (Japan); Fujiwara, Kohei [Institute for Materials Research, Tohoku University, Sendai 980-8577 (Japan)

    2016-02-01

    We report on the observation of reversible and immediate resistance switching by high-k oxide Ta{sub 2}O{sub 5}/organic parylene-C hybrid dielectric-gated VO{sub 2} thin films. Resistance change ratios at various temperatures in the insulating regime were demonstrated to occur in the vicinity of phase transition temperature. We also found an asymmetric hole-electron carrier modulation related to the suppression of phase transition temperature. The results in this research provide a possibility for clarifying the origin of metal-insulator transition in VO{sub 2} through the electrostatic field-induced transport modulation.

  10. Electric Field-induced Resistance Switching in VO2 Channels using Hybrid Gate Dielectric of High- k Ta2O5/Organic material Parylene-C

    Science.gov (United States)

    Wei, Tingting; Kanki, Teruo; Fujiwara, Kohei; Chikanari, Masashi; Tanaka, Hidekazu

    Electrostatic approach utilizing field-effect transistor (FET) with correlated electron materials provides an avenue to realize the novel devices (Mott-transistor) and to clarify condensed matter physics. In this study, we have prepared Mott-transistors using vanadium dioxide (VO2) channels and employed hybrid gate dielectric consisted of high- k material Ta2O5 and organic polymer parylene-C to trigger carrier transport modulation in VO2. Obvious resistance modulations were observed in insulating regime through time-dependent resistance measurement at varied square-shaped gate bias (VG) . Contrasting to the hysteretic response in electric double layer transistor (EDLT), an abrupt resistance switching in less than of 2-second-interval enables us to attribute such immediate modulation to pure electrostatic effect. Moreover, the maximum of resistance change was identified to appear around phase transition temperature (TMI) , which confirmed the disordered heterogeneous regime at TMI. Taking advantage of systematic modulation using VO2-based devices, we demonstrated the pronounced shifts of TMI by gate bias. Another fascinating behavior on asymmetric drop in TMI by hole-electron carrier doping was observed.

  11. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  12. Nanocomposites of polyimide and mixed oxide nanoparticles for high performance nanohybrid gate dielectrics in flexible thin film transistors

    Science.gov (United States)

    Kim, Ju Hyun; Hwang, Byeong-Ung; Kim, Do-Il; Kim, Jin Soo; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2017-01-01

    Organic gate dielectrics in thin film transistors (TFTs) for flexible display have advantages of high flexibility yet have the disadvantage of low dielectric constant (low-k). To supplement low-k characteristics of organic gate dielectrics, an organic/inorganic nanocomposite insulator loaded with high-k inorganic oxide nanoparticles (NPs) has been investigated but high loading of high-k NPs in polymer matrix is essential. Herein, compositing of over-coated polyimide (PI) on self-assembled (SA) layer of mixed HfO2 and ZrO2 NPs as inorganic fillers was used to make dielectric constant higher and leakage characteristics lower. A flexible TFT with lower the threshold voltage and high current on/off ratio could be fabricated by using the hybrid gate dielectric structure of the nanocomposite with SA layer of mixed NPs on ultrathin atomic-layer deposited Al2O3.

  13. Analysis and Design of Tri-Gate MOSFET with High Dielectrics Gate

    Directory of Open Access Journals (Sweden)

    Viranjay M. Srivastava

    2012-05-01

    Full Text Available The scaling of simple gate transistors requires the scaling and transistor elements like source/drain junction became difficult to scale further after a limit due to adverse effect of electrostatic and short-channel performance. The solution of the problem is tri-gate where we can increase the performance without increasing the width and without scaling. In this paper we have described the parameter of tri-gate and taking the high dielectric as substrate.

  14. Hetero-gate-Dielectric Symmetric U-shaped gate tunnel FET

    Science.gov (United States)

    Tajally, Mohammad Bagher; Karami, Mohammad Azim

    2017-10-01

    Heterogeneous gate dielectric is used in a nanoscale symmetric U-shaped gate tunnel FET (SUTFET), which resulted in ION, IOFF, subthreshold swing (SS), and Iambipolar enhancement. ION of 1.5 × 10-5 A/μm, IOFF of 6 × 10-12 A/μm, average subthreshold swing of (SS) 19.83 mV/decade from 0 V high-k dielectric close to the source and low-k dielectric in the vicinity of drain. The gate dielectric engineering shows characteristic enhancement in compare to SUTFET with single gate dielectric material. The strong coupling between the gate and transistor channel near the source results in reduced potential barrier width in tunnel junction, which leads to higher ION and lower subthreshold swing. Moreover, the presence of low-k dielectric near the drain reduces ambipolar current by increasing potential barrier height. This improved SUTFET characteristics makes it suitable for the usage in digital circuits due to reduced ambipolar response.

  15. Alternative Gate Dielectrics on Semiconductors for MOSFET Device Applications

    Energy Technology Data Exchange (ETDEWEB)

    Norton, D.P.; Budai, J.D.; Chisholm, M.F.; Pennycook, S.J.; McKee, R.; Walker, F.; Lee, Y.; Park, C.

    1999-12-06

    We have investigated the synthesis and properties of deposited oxides on Si and Ge for use as alternative gate dielectrics in MOSFET applications. The capacitance and leakage current behavior of polycrystalline Y{sub 2}O{sub 3} films synthesized by pulsed-laser deposition is reported. In addition, we also discuss the growth of epitaxial oxide structures. In particular, we have investigated the use of silicide termination for oxide growth on (001) Si using laser-molecular beam epitaxy. In addition, we discuss a novel approach involving the use of hydrogen to eliminate native oxide during initial dielectric oxide nucleation on (001) Ge.

  16. Nanoscale gadolinium oxide capping layers on compositionally variant gate dielectrics

    KAUST Repository

    Alshareef, Husam N.

    2010-11-19

    Metal gate work function enhancement using nanoscale (1.0 nm) Gd2O3 interfacial layers has been evaluated as a function of silicon oxide content in the HfxSiyOz gate dielectric and process thermal budget. It is found that the effective work function tuning by the Gd2O3 capping layer varied by nearly 400 mV as the composition of the underlying dielectric changed from 0% to 100% SiO2, and by nearly 300 mV as the maximum process temperature increased from ambient to 1000 °C. A qualitative model is proposed to explain these results, expanding the existing models for the lanthanide capping layer effect.

  17. Inkjet-printed zinc-tin-oxide TFTs with a solution-processed hybrid dielectric layer

    Science.gov (United States)

    Jang, Hye-Ryun; Kwack, Young-Jin; Choi, Woon-Seop

    2014-11-01

    Sol-gel TiO2 was synthesized and used as a gate dielectric for oxide thin-film transistors (TFTs). A hybrid gate insulator composed of sol-gel TiO2/thermally-grown SiO2 was applied to the inkjet-printed zinc-tin oxide (ZTO) TFTs for the first time. The electrical properties of an inkjet-printed ZTO TFT with a hybrid gate insulator show a mobility of 0.17 cm2/Vs, an on-to-off current ratio of 5 × 104, a subthreshold slope of 0.8 V/dec, and a threshold voltage of 0.6 V. The hybrid gate insulator for the inkjet-printed ZTO TFT shows a much improved operating voltage and subthreshold slope and a lower mobility compared to the SiO2 gate insulator.

  18. Fullerene thin-film transistors fabricated on polymeric gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Puigdollers, J. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)], E-mail: jpuigd@eel.upc.edu; Voz, C. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain); Cheylan, S. [ICFO - Mediterranean Technology Park, Avda del Canal Olimpic s/n, 08860-Castelldefels (Spain); Orpella, A.; Vetter, M.; Alcubilla, R. [Micro and Nano Technology Group (MNT), Dept. Enginyeria Electronica, Universitat Politecnica Catalunya, C/ Jordi Girona 1-3, Modul C4, 08034-Barcelona (Spain)

    2007-07-16

    Thin-film transistors with fullerene as n-type organic semiconductor have been fabricated. A polymeric gate dielectric, polymethyl methacrylate, has been used as an alternative to usual inorganic dielectrics. No significant differences in the microstructure of fullerene thin-films grown on polymethyl methacrylate were observed. Devices with either gold or aluminium top electrodes have been fabricated. Although the lower work-function of aluminium compared to gold should favour electron injection, similar field-effect mobilities in the range of 10{sup -2} cm{sup 2} V{sup -1} s{sup -1} were achieved in both cases. Actually, the output characteristics indicate that organic thin-film transistors behave more linearly with gold than with aluminium electrodes. These results confirm that not only energy barriers determine carrier injection at metal/organic interfaces, but also chemical interactions.

  19. Thermally grown thin nitride films as a gate dielectric

    CERN Document Server

    Shin, H C; Hwang, T K; Lee, K R

    1998-01-01

    High-quality very thin films ( <=6 nm) of silicon nitride were thermally grown in ammonia atmosphere with an IR (Infrared) gold image furnace. As-grown nitride film was analyzed using AES(Auger Emission Spectroscopy). Using MIS (Metal-Insulator-Semiconductor) devices, the growth rate was calculated using CV (Capacitance-Voltage) measurements and various electrical characteristics were obtained using CV, IV (Current-Voltage), trapping, time-dependent breakdown, high-field stress, constant current injection stress and dielectric breakdown techniques. These characteristics showed that very thin thermal silicon nitride films can be used as gate dielectrics for future highly scaled-down ULSI (Ultra Large Scale Integrated) devices, especially for EEPROM (Electrically Erasable and Programmable ROM)'s.

  20. Carbon nanotube transistors with graphene oxide films as gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    Carbon nanomaterials,including the one-dimensional(1-D) carbon nanotube(CNT) and two-dimensional(2-D) graphene,are heralded as ideal candidates for next generation nanoelectronics.An essential component for the development of advanced nanoelectronics devices is processing-compatible oxide.Here,in analogy to the widespread use of silicon dioxide(SiO2) in silicon microelectronic industry,we report the proof-of-principle use of graphite oxide(GO) as a gate dielectrics for CNT field-effect transistor(FET) via a fast and simple solution-based processing in the ambient condition.The exceptional transistor characteristics,including low operation voltage(2 V),high carrier mobility(950 cm2/V-1 s-1),and the negligible gate hysteresis,suggest a potential route to the future all-carbon nanoelectronics.

  1. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    Energy Technology Data Exchange (ETDEWEB)

    Sangwan, Vinod K.; Jariwala, Deep; McMorrow, Julian J.; He, Jianting; Lauhon, Lincoln J. [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Everaerts, Ken [Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States); Grayson, Matthew [Department of Electrical Engineering and Computer Science, Northwestern University, Evanston, Illinois 60208 (United States); Marks, Tobin J., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu; Hersam, Mark C., E-mail: t-marks@northwestern.edu, E-mail: m-hersam@northwestern.edu [Department of Materials Science and Engineering, Northwestern University, Evanston, Illinois 60208 (United States); Department of Chemistry, Northwestern University, Evanston, Illinois 60208 (United States)

    2014-02-24

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10{sup −5} Torr), and overall improved performance compared to control devices on conventional SiO{sub 2} gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  2. Wafer-scale solution-derived molecular gate dielectrics for low-voltage graphene electronics

    Science.gov (United States)

    Sangwan, Vinod K.; Jariwala, Deep; Everaerts, Ken; McMorrow, Julian J.; He, Jianting; Grayson, Matthew; Lauhon, Lincoln J.; Marks, Tobin J.; Hersam, Mark C.

    2014-02-01

    Graphene field-effect transistors are integrated with solution-processed multilayer hybrid organic-inorganic self-assembled nanodielectrics (SANDs). The resulting devices exhibit low-operating voltage (2 V), negligible hysteresis, current saturation with intrinsic gain >1.0 in vacuum (pressure < 2 × 10-5 Torr), and overall improved performance compared to control devices on conventional SiO2 gate dielectrics. Statistical analysis of the field-effect mobility and residual carrier concentration demonstrate high spatial uniformity of the dielectric interfacial properties and graphene transistor characteristics over full 3 in. wafers. This work thus establishes SANDs as an effective platform for large-area, high-performance graphene electronics.

  3. Metal-dielectric hybrid surfaces as integrated optoelectronic interfaces

    Energy Technology Data Exchange (ETDEWEB)

    Narasimhan, Vijay K.; Hymel, Thomas M.; Lai, Ruby A.; Cui, Yi

    2017-01-03

    An optoelectronic device has a hybrid metal-dielectric optoelectronic interface including an array of nanoscale dielectric resonant elements (e.g., nanopillars), and a metal film disposed between the dielectric resonant elements and below a top surface of the resonant elements such that the dielectric resonant elements protrude through the metal film. The device may also include an anti-reflection coating. The device may further include a metal film layer on each of the dielectric resonant elements.

  4. Vibron and phonon hybridization in dielectric nanostructures.

    Science.gov (United States)

    Preston, Thomas C; Signorell, Ruth

    2011-04-05

    Plasmon hybridization theory has been an invaluable tool in advancing our understanding of the optical properties of metallic nanostructures. Through the prism of molecular orbital theory, it allows one to interpret complex structures as "plasmonic molecules" and easily predict and engineer their electromagnetic response. However, this formalism is limited to conducting particles. Here, we present a hybridization scheme for the external and internal vibrations of dielectric nanostructures that provides a straightforward understanding of the infrared signatures of these particles through analogy to existing hybridization models of both molecular orbitals and plasmons extending the range of applications far beyond metallic nanostructures. This method not only provides a qualitative understanding, but also allows for the quantitative prediction of vibrational spectra of complex nanoobjects from well-known spectra of their primitive building blocks. The examples of nanoshells illustrate how spectral features can be understood in terms of symmetry, number of nodal planes, and scale parameters.

  5. High-density carrier-accumulated and electrically stable oxide thin-film transistors from ion-gel gate dielectric

    Science.gov (United States)

    Fujii, Mami N.; Ishikawa, Yasuaki; Miwa, Kazumoto; Okada, Hiromi; Uraoka, Yukiharu; Ono, Shimpei

    2015-12-01

    The use of indium-gallium-zinc oxide (IGZO) has paved the way for high-resolution uniform displays or integrated circuits with transparent and flexible devices. However, achieving highly reliable devices that use IGZO for low-temperature processes remains a technological challenge. We propose the use of IGZO thin-film transistors (TFTs) with an ionic-liquid gate dielectric in order to achieve high-density carrier-accumulated IGZO TFTs with high reliability, and we discuss a distinctive mechanism for the degradation of this organic-inorganic hybrid device under long-term electrical stress. Our results demonstrated that an ionic liquid or gel gate dielectric provides highly reliable and low-voltage operation with IGZO TFTs. Furthermore, high-density carrier accumulation helps improve the TFT characteristics and reliability, and it is highly relevant to the electronic phase control of oxide materials and the degradation mechanism for organic-inorganic hybrid devices.

  6. Simulation-based study of negative capacitance double-gate junctionless transistors with ferroelectric gate dielectric

    Science.gov (United States)

    Jiang, Chunsheng; Liang, Renrong; Wang, Jing; Xu, Jun

    2016-12-01

    In this work, a kind of negative capacitance double-gate junctionless transistor (NC-DG-JLT) with ferroelectric (FE) gate dielectric and metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure is proposed. It is demonstrated that NC-DG-JLTs can lower off-state current, improve on-state drain current, and lower subthreshold swing at the same time compared with its conventional DG JLT counterpart using numerical simulation. The steep subthreshold swing (SS detail. The low off-state current and high on/off current ratio could be obtained even for ultra-small transistors by optimizing the device parameters. NC-DG-JLTs have a great potential for low power dissipation applications.

  7. Current Progress of Hf (Zr)-Based High-k Gate Dielectric Thin Films

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    With the continued downscaling of complementary metal-oxide-semiconductor field effect transistor dimensions, high-dielectric constant (high-k) gate materials, as alternatives to SiO2, have been extensively investigated. Hf (Zr)-based high-k gate dielectric thin films have been regarded as the most promising candidates for high-k gate dielectric according to the International Technology Roadmap for Semiconductor due to their excellent physical properties and performance. This paper reviews the recent progress on Hf (Zr)-based high-k gate dielectrics based on PVD (physical vapor deposition) process. This article begins with a survey of various methods developed for generating Hf (Zr)-based high-k gate dielectrics, and then mainly focuses on microstructure, synthesis, characterization, formation mechanisms of interfacial layer, and optical properties of Hf (Zr)-based high-k gate dielectrics. Finally, this review concludes with personal perspectives towards future research on Hf (Zr)-based high-k gate dielectrics.

  8. Organic/Inorganic Nano-hybrids with High Dielectric Constant for Organic Thin Film Transistor Applications

    Science.gov (United States)

    Yu, Yang-Yen; Jiang, Ai-Hua; Lee, Wen-Ya

    2016-11-01

    The organic material soluble polyimide (PI) and organic-inorganic hybrid PI-barium titanate (BaTiO3) nanoparticle dielectric materials (IBX, where X is the concentration of BaTiO3 nanoparticles in a PI matrix) were successfully synthesized through a sol-gel process. The effects of various BaTiO3 contents on the hybrid film performance and performance optimization were investigated. Furthermore, pentacene-based organic thin film transistors (OTFTs) with PI-BaTiO3/polymethylmethacrylate or cyclic olefin copolymer (COC)-modified gate dielectrics were fabricated and examined. The hybrid materials showed effective dispersion of BaTiO3 nanoparticles in the PI matrix and favorable thermal properties. X-ray diffraction patterns revealed that the BaTiO3 nanoparticles had a perovskite structure. The hybrid films exhibited high formability and planarity. The IBX hybrid dielectric films exhibited tunable insulating properties such as the dielectric constant value and capacitance in ranges of 4.0-8.6 and 9.2-17.5 nF cm-2, respectively. Adding the modified layer caused the decrease of dielectric constant values and capacitances. The modified dielectric layer without cross-linking displayed a hydrophobic surface. The electrical characteristics of the pentacene-based OTFTs were enhanced after the surface modification. The optimal condition for the dielectric layer was 10 wt% hybrid film with the COC-modified layer; moreover, the device exhibited a threshold voltage of 0.12 V, field-effect mobility of 4.32 × 10-1 cm2 V-1 s-1, and on/off current of 8.4 × 107.

  9. Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

    Institute of Scientific and Technical Information of China (English)

    Xinhua Zhu; Jianmin Zhu; Aidong Li; Zhiguo Liu; Naiben Ming

    2009-01-01

    The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric

  10. Plasmonic Antennas Hybridized with Dielectric Waveguides

    CERN Document Server

    Arango, Felipe Bernal; Koenderink, A Femius

    2013-01-01

    For the purpose of using plasmonics in an integrated scheme where single emitters can be probed efficiently, we experimentally and theoretically study the scattering properties of single nano-rod gold antennas as well as antenna arrays placed on one-dimensional dielectric silicon nitride waveguides. Using real space and Fourier microscopy correlated with waveguide transmission measurements, we quantify the spectral properties, absolute strength and directivity of scattering. The scattering processes can be well understood in the framework of the physics of dipolar objects placed on a planar layered environment with a waveguiding layer. We use the single plasmonic structures on top of the waveguide as dipolar building blocks for new types of antennas where the waveguide enhances the coupling between antenna elements. We report on waveguide hybridized Yagi-Uda antennas which show directionality in out-coupling of guided modes as well as directionality for in-coupling into the waveguide of localized excitations ...

  11. Natural radioactivity consideration for high- dielectrics and metal gates choice in nanoelectronic devices

    OpenAIRE

    Gedion, Michael; Wrobel, Frédéric; Saigné, Frédéric

    2010-01-01

    Abstract In order to face downscaling, new chemical elements are used and suggested for the semiconductor industry. However, some of these elements have natural radioactive isotopes, which may cause reliability issues in nanoelectronic devices by triggering soft errors. In this paper, we focus on high-? dielectric materials and metal gates. We show that beside physical, chemical and mechanical properties of high-? dielectrics and metal gates, natural radioactivity is also a crucial propert...

  12. Characteristics of high-quality HfSiON gate dielectric prepared by physical vapour deposition

    Institute of Scientific and Technical Information of China (English)

    Xu Gao-Bo; Xu Qiu-Xia

    2009-01-01

    This paper presents a method using simple physical vapour deposition to form high-quality hafnium silicon oxyni-tride (HfSiON) on ultrathin SiO2 buffer layer. The gate dielectric with 10A (1/A = 0.1 nm) equivalent oxide thickness is obtained. The experimental results indicate that the prepared HfSiON gate dielectric exhibits good physical and electrical characteristics, including very good thermal stability up to 1000℃, excellent interface properties, high dielec-tric constant (k = 14) and low gate-leakage current (Ig= 1.9×10-3 A/cm2@Vg = Vfb-1V for EOT of 10A). TaN metal gate electrode is integrated with the HfSiON gate dielectric.The effective work function of TaN on HfSiON is 4.3eV, meeting the requirements of NMOS for the metal gate. And, the impacts of sputtering ambient and annealing temperature on the electrical properties of HfSiON gate dielectric are investigated.

  13. Fermi level pinning effects at gate-dielectric interfaces influenced by interface state densities

    Institute of Scientific and Technical Information of China (English)

    洪文婷; 韩伟华; 吕奇峰; 王昊; 杨富华

    2015-01-01

    The dependences of Fermi-level pinning on interface state densities for the metal–dielectric, ploycrystalline silicon–dielectric, and metal silicide–dielectric interfaces are investigated by calculating their effective work functions and their pinning factors. The Fermi-level pinning factors and effective work functions of the metal–dielectric interface are observed to be more susceptible to the increasing interface state densities, differing significantly from that of the ploycrystalline silicon–dielectric interface and the metal silicide–dielectric interface. The calculation results indicate that metal silicide gates with high-temperature resistance and low resistivity are a more promising choice for the design of gate materials in metal-oxide semiconductor (MOS) technology.

  14. Nanostructure and nanochemistry of gate dielectrics and processing of tunable dielectrics by chemical vapor deposition

    Science.gov (United States)

    Wang, Chang-Gong

    2002-01-01

    PbTiO3-SrTiO3 (PST) thin films that are voltage tunable were developed for high-frequency application by a metal-organic chemical vapor deposition technique at rates of 10--15 nm/min. PST films (90--150nm) were deposited on Pt/TiO2/SiO2/Si and Sapphire (0001) substrates and characterized by various techniques to control the composition and structure. The tunability and dielectric loss (tandelta) of a 90nm PST film were 37% and 0.02, respectively, at 1MHz and 3V in a parallel plates capacitor (Pt/PST/Pt) configuration. PST films on (0001) Sapphire were epitaxial with an orientation relationship of PST [1 1 1]// Sapphire [0 0 0 1], and in-plane alignment of PST [1 i 0]// Sapphire [2 i i 0] and PST [i i 2]// Sapphire [0 1 i 0]. A coplanar waveguide structure was used to determine the tunability (31.3%) and figure of merit (13 degrees/dB) of an epitaxial 100nm PST film on Sapphire at 12 GHz. The tandelta, derived from transmission-type resonator, is explained in terms of composition inhomogeneities and in-plane biaxial stress due to lattice mismatch between PST and Sapphire. A 4nm-ZrOx/1.2nm-SiOx layer structure was formed on 200mm Si wafers by a manufacturable atomic layer chemical vapor deposition (ALCVD) technique for advanced metal oxide semiconductor gate dielectrics. The nanostructure and nanochemistry of this gate stack were investigated by various techniques, before and after oxygen annealing (700°C). The results showed that a multiphase and heterogeneous structure evolved, defined as Zr-O/interlayer(IL)/Si stack. The critical parameters that control the nanostructural and nanochemical evolution are discussed using some simple mechanistic explanations and literature data. The stacks were characterized for their dielectric and electrical properties using a Pt/Zr-O/IL/Si capacitor configuration. The flat band shift (DeltaV FB), capacitance voltage hysteresis, and leakage current density were correlated with defects and roughness of the interface, thickness of IL

  15. Plasmonic antennas hybridized with dielectric waveguides.

    Science.gov (United States)

    Bernal Arango, Felipe; Kwadrin, Andrej; Koenderink, A Femius

    2012-11-27

    For the purpose of using plasmonics in an integrated scheme where single emitters can be probed efficiently, we experimentally and theoretically study the scattering properties of single nanorod gold antennas as well as antenna arrays placed on one-dimensional dielectric silicon nitride waveguides. Using real space and Fourier microscopy correlated with waveguide transmission measurements, we quantify the spectral properties, absolute strength, and directivity of scattering. The scattering processes can be well understood in the framework of the physics of dipolar objects placed on a planar layered environment with a waveguiding layer. We use the single plasmonic structures on top of the waveguide as dipolar building blocks for new types of antennas where the waveguide enhances the coupling between antenna elements. We report on waveguide hybridized Yagi-Uda antennas which show directionality in out-coupling of guided modes as well as directionality for in-coupling into the waveguide of localized excitations positioned at the feed element. These measurements together with simulations demonstrate that this system is ideal as a platform for plasmon quantum optics schemes as well as for fluorescence lab-on-chip applications.

  16. Performance of pentacene-based organic field effect transistors using different polymer gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    WU Ren-lei; CHENG Xiao-man; ZHENG Hong; YIN Shou-gen

    2009-01-01

    Pentacene-based organic field effect transistors (OFETs) are fabricated using poly(methyl methacrylate) (PMMA) and polyimide (PI) as gate dielectrics, respectively. The fabricated OFETs exhibit reasonable device characteristics. The field-effect mobility, threshold voltage, and on/off current radio are determined to be 3.214 × 10-2 cm2 / Vs, -28 V, and 1 × 103 respectively for OFETs with PMMA as gate dielectrics, and 7.306×10-3cm2 / Vs, -21 V, and 2 ×102 for OFETs with PI. Furthermore, the dielectric properties of gate insulator layer are tested and the dipole effect at the semiconductor/dielectrics interface is also analyzed by a model of energy level diagram.

  17. Fabrication and characteristics of high-K HfO2 gate dielectrics on n-germanium

    Institute of Scientific and Technical Information of China (English)

    Han De-Dong; Kang Jin-Feng; Liu Xiao-Yan; Sun Lei; Luo Hao; Han Ru-Qi

    2007-01-01

    This paper reports that the high-K HfO2 gate dielectrics are fabricated on n-germanium substrates by sputtering Hf on Ge and following by a furnace annealing. The impacts of sputtering ambient, annealing ambient and annealing temperature on the electrical properties of high-K HfO2 gate dielectrics on germanium substrates are investigated.Experimental results indicate that high-K HfO2 gate dielectrics on germanium substrates with good electrical characteristics are obtained, the electrical properties of high-K HfO2 gate dielectrics is strongly correlated with sputtering ambient, annealing ambient and annealing temperature.

  18. Mismatch of dielectric constants at the interface of nanometer metal-oxide-semiconductor devices with high- gate dielectric impacts on the inversion charge density

    Indian Academy of Sciences (India)

    Ling-Feng Mao

    2011-04-01

    The comparison of the inversion electron density between a nanometer metal-oxidesemiconductor (MOS) device with high- gate dielectric and a SiO2 MOS device with the same equivalent oxide thickness has been discussed. A fully self-consistent solution of the coupled Schrödinger–Poisson equations demonstrates that a larger dielectric-constant mismatch between the gate dielectric and silicon substrate can reduce electron density in the channel of a MOS device under inversion bias. Such a reduction in inversion electron density of the channel will increase with increase in gate voltage. A reduction in the charge density implies a reduction in the inversion electron density in the channel of a MOS device. It also implies that a larger dielectric constant of the gate dielectric might result in a reduction in the source–drain current and the gate leakage current.

  19. Dielectric properties of PMMA-SiO2 hybrid films

    KAUST Repository

    Morales-Acosta, M. D.

    2010-03-01

    Organic-inorganic hybrid films were synthesized by a modified sol-gel process. PMMASiO2 films were prepared using methylmethacrylate (MMA), tetraethil-orthosilicate (TEOS) as silicon dioxide source, and 3-trimetoxi-silil-propil-methacrylate (TMSPM) as coupling agent. FTIR measurements were performed on the hybrid films to confirm the presence of PMMA-SiO2 bonding. In addition, metal-insulator-metal (MIM) devices were fabricated to study the dielectric constant of the films as function of frequency (1 KHz to 1 MHz). Electrical results show a weak trend of the dielectric constant of the hybrid films with MMA molar ratio. More importantly, the PMMA-SiO2 hybrid films showed a higher dielectric constant than SiO2 and PMMA layers, which is likely due to the presence of additional C-O-C bond. © (2010) Trans Tech Publications.

  20. Current Tunnelling in MOS Devices with Al2O3/SiO2 Gate Dielectric

    Directory of Open Access Journals (Sweden)

    A. Bouazra

    2008-01-01

    Full Text Available With the continued scaling of the SiO2 thickness below 2 nm in CMOS devices, a large direct-tunnelling current flow between the gate electrode and silicon substrate is greatly impacting device performance. Therefore, higher dielectric constant materials are desirable for reducing the gate leakage while maintaining transistor performance for very thin dielectric layers. Despite its not very high dielectric constant (∼10, Al2O3 has emerged as one of the most promising high-k candidates in terms of its chemical and thermal stability as its high-barrier offset. In this paper, a theoretical study of the physical and electrical properties of Al2O3 gate dielectric is reported including I(V and C(V characteristics. By using a stack of Al2O3/SiO2 with an appropriate equivalent oxide thickness of gate dielectric MOS, the gate leakage exhibits an important decrease. The effect of carrier trap parameters (depth and width at the Al2O3/SiO2 interface is also discussed.

  1. Nanocrystalline cellulose applied simultaneously as the gate dielectric and the substrate in flexible field effect transistors.

    Science.gov (United States)

    Gaspar, D; Fernandes, S N; de Oliveira, A G; Fernandes, J G; Grey, P; Pontes, R V; Pereira, L; Martins, R; Godinho, M H; Fortunato, E

    2014-03-07

    Cotton-based nanocrystalline cellulose (NCC), also known as nanopaper, one of the major sources of renewable materials, is a promising substrate and component for producing low cost fully recyclable flexible paper electronic devices and systems due to its properties (lightweight, stiffness, non-toxicity, transparency, low thermal expansion, gas impermeability and improved mechanical properties).Here, we have demonstrated for the first time a thin transparent nanopaper-based field effect transistor (FET) where NCC is simultaneously used as the substrate and as the gate dielectric layer in an 'interstrate' structure, since the device is built on both sides of the NCC films; while the active channel layer is based on oxide amorphous semiconductors, the gate electrode is based on a transparent conductive oxide.Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility (>7 cm(2) V (-1) s(-1)), drain-source current on/off modulation ratio higher than 10(5), enhancement n-type operation and subthreshold gate voltage swing of 2.11 V/decade. The NCC film FET characteristics have been measured in air ambient conditions and present good stability, after two weeks of being processed, without any type of encapsulation or passivation layer. The results obtained are comparable to ones produced for conventional cellulose paper, marking this out as a promising approach for attaining high-performance disposable electronics such as paper displays, smart labels, smart packaging, RFID (radio-frequency identification) and point-of-care systems for self-analysis in bioscience applications, among others.

  2. Nanocrystalline cellulose applied simultaneously as the gate dielectric and the substrate in flexible field effect transistors

    Science.gov (United States)

    Gaspar, D.; Fernandes, S. N.; de Oliveira, A. G.; Fernandes, J. G.; Grey, P.; Pontes, R. V.; Pereira, L.; Martins, R.; Godinho, M. H.; Fortunato, E.

    2014-03-01

    Cotton-based nanocrystalline cellulose (NCC), also known as nanopaper, one of the major sources of renewable materials, is a promising substrate and component for producing low cost fully recyclable flexible paper electronic devices and systems due to its properties (lightweight, stiffness, non-toxicity, transparency, low thermal expansion, gas impermeability and improved mechanical properties). Here, we have demonstrated for the first time a thin transparent nanopaper-based field effect transistor (FET) where NCC is simultaneously used as the substrate and as the gate dielectric layer in an ‘interstrate’ structure, since the device is built on both sides of the NCC films; while the active channel layer is based on oxide amorphous semiconductors, the gate electrode is based on a transparent conductive oxide. Such hybrid FETs present excellent operating characteristics such as high channel saturation mobility (>7 cm2 V -1 s-1), drain-source current on/off modulation ratio higher than 105, enhancement n-type operation and subthreshold gate voltage swing of 2.11 V/decade. The NCC film FET characteristics have been measured in air ambient conditions and present good stability, after two weeks of being processed, without any type of encapsulation or passivation layer. The results obtained are comparable to ones produced for conventional cellulose paper, marking this out as a promising approach for attaining high-performance disposable electronics such as paper displays, smart labels, smart packaging, RFID (radio-frequency identification) and point-of-care systems for self-analysis in bioscience applications, among others.

  3. Second harmonic generation spectroscopy on hybrid plasmonic/dielectric nanoantennas

    Institute of Scientific and Technical Information of China (English)

    Heiko Linnenbank; Yevgen Grynko; Jens F(o)rstner; Stefan Linden

    2016-01-01

    Plasmonic nanoantennas provide unprecedented opportunities to concentrate light fields in subwavelength-sized volumes.By placing a nonlinear dielectric nanoparticle in such a hot spot,one can hope to take advantage of beth the field enhancement provided by nanoantennas and the large,nonlinear optical susceptibility of dielectric nanoparticles.To test this concept,we combine gold gap nanoantennas with second-order,nonlinear zinc sulfide nanoparticles,and perform second harmonic generation (SHG) spectroscopy onthe combined hybrid dielectric/plasmonic nanoantennas as well as on the individual constituents.We find that SHG from the bare gold nanoantennas,even though it should be forbidden due to symmetry reasons,is several orders of magnitude larger than that of the bare zinc sulfide nanoparticles.Even stronger second harmonic signals are generated by the hybrid dielectric/plasmonic nanoantennas.Control experiments with nanoantennas containing linear lanthanum fluoride nanoparticles reveal;however,that the increased SHG efficiency of the hybrid dielectric/plasmonic nanoantennas does not depend on the nonlinear optical susceptibility of the dielectric nanoparticles but is an effect of the modification of the dielectric environment.The combination of a hybrid dielectric/plasmonic nanoantenna,which is only resonant for the incoming pump light field,with a second nanoantenna,which is resonant for the generated second harmonic light,allows for a further increase in the efficiency of SHG.As the second nanoantenna mediates the coupling of the second harmonic light to the far field,this double-resonant approach also provides us with control over the polarization of the generated light.

  4. Polymer thin-film transistor based on a high dielectric constant gate insulator

    Institute of Scientific and Technical Information of China (English)

    Lü Wen; Peng Jun-Biao; Yang Kai-Xia; Lan Lin-Feng; Niu Qiao-Li; Cao Yong

    2007-01-01

    In this paper full polymer thin-film transistors (PTFTs) based on Poly (acrylonitrile) (PAN) as the gate dielectric and poly (2-methoxy-5-(2'-ethyl-hexyloxy)-1,4-phenylene-vinylene) (MEH-PPV) as the semiconductor layer were investigated by using different channel width/length ratios. Relatively high dielectric constant of the polymer dielectric layer (6.27) can remarkably reduce the threshold voltage of the transistors to below-3 V. Hole field-effect mobility of MEH-PPV of the PTFTs was about 4.8 × 10-4 cm2/Vs, and on/off current ratio was larger than 102, which was comparable with that of transistors with widely used Poly (4-vinyl phenol) (PVP) or SiO2 as gate dielectrics.

  5. All-Optical Reversible Hybrid New Gate using TOAD

    Directory of Open Access Journals (Sweden)

    Goutam Kumar Maity

    2014-03-01

    Full Text Available Reversible logic is emerged as a promising computing paradigm with applications in low-power CMOS, quantum computing, optical computing and nanotechnology. Optical logic gates become potential component to work at macroscopic (light pulses carry information, or quantum (single photon carries information levels with high efficiency. In this paper, we propose a novel scheme of Hybrid new gate realization in all-optical domain. Simulation results verify the functionality of the gate as well as reversibility. Approximate insertion power loss in dB is also reported for the Gaussian incident and control pulse.

  6. Utilizing self-assembled-monolayer-based gate dielectrics to fabricate molybdenum disulfide field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Kawanago, Takamasa, E-mail: kawanago.t.ab@m.titech.ac.jp; Oda, Shunri [Quantum Nanoelectronics Research Center (QNERC), Tokyo Institute of Technology, 2-12-1 Ookayama, Meguro-ku, Tokyo, 152-8550 (Japan)

    2016-01-25

    In this study, we apply self-assembled-monolayer (SAM)-based gate dielectrics to the fabrication of molybdenum disulfide (MoS{sub 2}) field-effect transistors. A simple fabrication process involving the selective formation of a SAM on metal oxides in conjunction with the dry transfer of MoS{sub 2} flakes was established. A subthreshold slope (SS) of 69 mV/dec and no hysteresis were demonstrated with the ultrathin SAM-based gate dielectrics accompanied by a low gate leakage current. The small SS and no hysteresis indicate the superior interfacial properties of the MoS{sub 2}/SAM structure. Cross-sectional transmission electron microscopy revealed a sharp and abrupt interface of the MoS{sub 2}/SAM structure. The SAM-based gate dielectrics are found to be applicable to the fabrication of low-voltage MoS{sub 2} field-effect transistors and can also be extended to various layered semiconductor materials. This study opens up intriguing possibilities of SAM-based gate dielectrics in functional electronic devices.

  7. Top-gate dielectric induced doping and scattering of charge carriers in epitaxial graphene

    Science.gov (United States)

    Puls, Conor P.; Staley, Neal E.; Moon, Jeong-Sun; Robinson, Joshua A.; Campbell, Paul M.; Tedesco, Joseph L.; Myers-Ward, Rachael L.; Eddy, Charles R.; Gaskill, D. Kurt; Liu, Ying

    2011-07-01

    We show that an e-gun deposited dielectric impose severe limits on epitaxial graphene-based device performance based on Raman spectroscopy and low-temperature transport measurements. Specifically, we show from studies of epitaxial graphene Hall bars covered by SiO2 that the measured carrier density is strongly inhomogenous and predominantly induced by charged impurities at the grapheme/dielectric interface that limit mobility via Coulomb interactions. Our work emphasizes that material integration of epitaxial graphene and a gate dielectric is the next major road block towards the realization of graphene-based electronics.

  8. Enhanced ZnO Thin-Film Transistor Performance Using Bilayer Gate Dielectrics

    KAUST Repository

    Alshammari, Fwzah H.

    2016-08-24

    We report ZnO TFTs using Al2O3/Ta2O5 bilayer gate dielectrics grown by atomic layer deposition. The saturation mobility of single layer Ta2O5 dielectric TFT was 0.1 cm2 V-1 s-1, but increased to 13.3 cm2 V-1 s-1 using Al2O3/Ta2O5 bilayer dielectric with significantly lower leakage current and hysteresis. We show that point defects present in ZnO film, particularly VZn, are the main reason for the poor TFT performance with single layer dielectric, although interfacial roughness scattering effects cannot be ruled out. Our approach combines the high dielectric constant of Ta2O5 and the excellent Al2O3/ZnO interface quality, resulting in improved device performance. © 2016 American Chemical Society.

  9. High dielectric constant materials and their application to IC gate stack systems

    Institute of Scientific and Technical Information of China (English)

    TU; Hailing

    2005-01-01

    High dielectric constant (high-k) materials are vital tothe nanoelectronic devices.The paper reviews research development of high-k materials, describes a variety of manufacture technologies and discusses the application of the gate stack systems to non-classical device structures.

  10. Organic Thin Film Field Effect Transistors with PMMA-GMA Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    JIANG Wen-Hai; DU Guo-Tong; YU Shu-Kun; WANG Wei; CHANG Yu-Chun; WANG Xu

    2006-01-01

    @@ We fabricate organic thin films using the copolymer of methyl methacrylate and glycidyl methacrylate (PMMA-GMA) as a gate dielectric with a simple top-contact structure. Copper phthalocyanine (CuPc) TFTs are fabricated and the influences of annealing on the performance are studied. The mobilities increase from 2.5 ×103 cm2/Vs to 4.2 × 103 cm2/Vs and threshold voltages decrease from -18 V to -10 V after annealing. The good performances of the devices approach those obtained with inorganic gate dielectric materials such as silicon dioxide under the same technical conditions. It is fully proven that PMMA-GMA is a competitive candidate as an excellent gate insulation layer.

  11. Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor

    Directory of Open Access Journals (Sweden)

    Fatima Zohra Rahou

    2016-11-01

    Full Text Available The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN, which giving better subthreshold swing (SS, drain-induced barrier lowing (DIBL, leakage current Ioff and Ion/Ioff ratio.

  12. The origin of excellent gate-bias stress stability in organic field-effect transistors employing fluorinated-polymer gate dielectrics.

    Science.gov (United States)

    Kim, Jiye; Jang, Jaeyoung; Kim, Kyunghun; Kim, Haekyoung; Kim, Se Hyun; Park, Chan Eon

    2014-11-12

    Tuning of the energetic barriers to charge transfer at the semiconductor/dielectric interface in organic field-effect transistors (OFETs) is achieved by varying the dielectric functionality. Based on this, the correlation between the magnitude of the energy barrier and the gate-bias stress stability of the OFETs is demonstrated, and the origin of the excellent device stability of OFETs employing fluorinated dielectrics is revealed.

  13. Yttrium scandate thin film as alternative high-permittivity dielectric for germanium gate stack formation

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

    2015-08-17

    We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.

  14. SiC Power MOSFET with Improved Gate Dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Sbrockey, Nick M; Tompa, Gary S; Spencer, Michael G; Chandrashekhar, Chandra MVS

    2010-08-23

    In this STTR program, Structured Materials Industries (SMI), and Cornell University are developing novel gate oxide technology, as a critical enabler for silicon carbide (SiC) devices. SiC is a wide bandgap semiconductor material, with many unique properties. SiC devices are ideally suited for high-power, highvoltage, high-frequency, high-temperature and radiation resistant applications. The DOE has expressed interest in developing SiC devices for use in extreme environments, in high energy physics applications and in power generation. The development of transistors based on the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) structure will be critical to these applications.

  15. A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics

    Institute of Scientific and Technical Information of China (English)

    Cui Ning; Liang Renrong; Wang Jing; Zhou Wei; Xu Jun

    2012-01-01

    A PNPN tunnel field effect transistor (TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced.The effects of the gate and fringe electric fields on the TFET's performance were investigated through two-dimensional simulations.The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel,while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability.The TFET device with the proposed structure has good switching characteristics,enhanced on-state current,and high process tolerance.It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.

  16. Generalization of Dielectric-Dependent Hybrid Functionals to Finite Systems

    Science.gov (United States)

    Brawand, Nicholas P.; Vörös, Márton; Govoni, Marco; Galli, Giulia

    2016-10-01

    The accurate prediction of electronic and optical properties of molecules and solids is a persistent challenge for methods based on density functional theory. We propose a generalization of dielectric-dependent hybrid functionals to finite systems where the definition of the mixing fraction of exact and semilocal exchange is physically motivated, nonempirical, and system dependent. The proposed functional yields ionization potentials, and fundamental and optical gaps of many, diverse molecular systems in excellent agreement with experiments, including organic and inorganic molecules and semiconducting nanocrystals. We further demonstrate that this hybrid functional gives the correct alignment between energy levels of the exemplary TTF-TCNQ donor-acceptor system.

  17. Electrical Properties of Ultrathin Hf-Ti-O Higher k Gate Dielectric Films and Their Application in ETSOI MOSFET

    Science.gov (United States)

    Xiong, Yuhua; Chen, Xiaoqiang; Wei, Feng; Du, Jun; Zhao, Hongbin; Tang, Zhaoyun; Tang, Bo; Wang, Wenwu; Yan, Jiang

    2016-11-01

    Ultrathin Hf-Ti-O higher k gate dielectric films ( 2.55 nm) have been prepared by atomic layer deposition. Their electrical properties and application in ETSOI (fully depleted extremely thin SOI) PMOSFETs were studied. It is found that at the Ti concentration of Ti/(Ti + Hf) 9.4%, low equivalent gate oxide thickness (EOT) of 0.69 nm and acceptable gate leakage current density of 0.61 A/cm2 @ ( V fb - 1) V could be obtained. The conduction mechanism through the gate dielectric is dominated by the F-N tunneling in the gate voltage range of -0.5 to -2 V. Under the same physical thickness and process flow, lower EOT and higher I on/ I off ratio could be obtained while using Hf-Ti-O as gate dielectric compared with HfO2. With Hf-Ti-O as gate dielectric, two ETSOI PMOSFETs with gate width/gate length ( W/ L) of 0.5 μm/25 nm and 3 μm/40 nm show good performances such as high I on, I on/ I off ratio in the magnitude of 105, and peak transconductance, as well as suitable threshold voltage (-0.3 -0.2 V). Particularly, ETSOI PMOSFETs show superior short-channel control capacity with DIBL swing <70 mV/decade.

  18. Electrical Characteristics of MOS Capacitors with HfTiON as Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    CHEN Weibing; XU Jingping; LAI Puito; LI Yanping; XU Shengguo; CHAN Chulok

    2009-01-01

    HfTiN film was deposited by co-reactive sputtering and then was annealed in dif-ferent gas ambients at temperature of 650 ℃ for 2 min to form HfTiON film. Capacitance-voltage and gate-leakage characteristics were investigated. The N2O-annealed sample exhibited small inter-face-state and oxide-charge densities, and enhanced reliability, which was attributed to the fact that nitridation could create strong Si≡N bonds to passivate dangling Si bonds and replaced strained Si-O bonds, thus forming a hardened dielectric/Si interface with high reliability. As a result, it is possible to prepare high-quality HfTiON gate dielectric of small-scaling CMOS devices in the industry-preferred N2O environment.

  19. Preparation of a new gate dielectric material HfTiON film

    Institute of Scientific and Technical Information of China (English)

    YU Guo-yi; ZOU Xue-cheng; CHEN Wei-bing

    2007-01-01

    A new gate dielectric material HfTiON is deposited by reactive co-sputtering of Hf and Ti targets in N2/O2 ambient,followed by annealing in N2 at 600℃ and 800℃ respectively for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared for different anneal conditions. The results indicate that the sample annealed at 800 ℃ exhibits lower interface-state and oxide-charge densities, and better device reliability. This is attributed to the fact that the rapid thermal annealing at the higher temperature of 800 ℃ can effectively remove the damage-induced precipitation, forming a hardened dielectric/Si interface with high reliability.

  20. Investigation of terbium scandate as an alternative gate dielectric in fully depleted transistors

    Science.gov (United States)

    Roeckerath, M.; Lopes, J. M. J.; Özben, E. Durǧun; Urban, C.; Schubert, J.; Mantl, S.; Jia, Y.; Schlom, D. G.

    2010-01-01

    Terbium scandate thin films were deposited by e-gun evaporation on (100) silicon substrates. Rutherford backscattering spectrometry and x-ray diffraction studies revealed homogeneous chemical compositions of the films. A dielectric constant of 26 and CV-curves with small hystereses were measured as well as low leakage current densities of <1 nA/cm2. Fully depleted n-type field-effect transistors on thin silicon-on-insulator substrates with terbium scandate gate dielectrics were fabricated with a gate-last process. The devices show inverse subthreshold slopes of 80 mV/dec and a carrier mobility for electrons of 225 cm2/V•s was extracted.

  1. HfO2 Gate Dielectrics for Future Generation of CMOS Device Application

    Institute of Scientific and Technical Information of China (English)

    H.Y.Yu; J.F.Kang; Ren Chi; M.F.Li; D.L.Kwong

    2004-01-01

    The material and electrical properties of HfO2 high-k gate dielectric are reported.In the first part,the band alignment of HfO2 and (HfO2)x(Al2O3)1-x to (100)Si substrate and their thermal stability are studied by X-ray photoelectron spectroscopy and TEM.The energy gap of (HfO2)x(Al2O3)1-x,the valence band offset,and the conduction band offset between (HfO2)x(Al2O3)1-x and the Si substrate as functions of x are obtained based on the XPS results.Our XPS results also demonstrate that both the thermal stability and the resistance to oxygen diffusion of HfO2 are improved by adding Al to form Hf aluminates.In the second part,a thermally stable and high quality HfN/HfO2 gate stack is reported.Negligible changes in equivalent oxide thickness (EOT),gate leakage,and work function (close to Si mid-gap) of HfN/HfO2 gate stack are demonstrated even after 1000℃ post-metal annealing(PMA),which is attributed to the superior oxygen diffusion barrier of HfN as well as the thermal stability of the HfN/HfO2 interface.Therefore,even without surface nitridation prior to HfO2 deposition,the EOT of HfN/HfO2 gate stack has been successfully scaled down to less than 1nm after 1000℃ PMA with excellent leakage and long-term reliability.The last part demonstrates a novel replacement gate process employing a HfN dummy gate and sub-1nm EOT HfO2 gate dielectric.The excellent thermal stability of the HfN/HfO2 gate stack enables its use in high temperature CMOS processes.The replacement of HfN with other metal gate materials with work functions adequate for n- and p-MOS is facilitated by a high etch selectivity of HfN with respect to HfO2,without any degradation to the EOT,gate leakage,or TDDB characteristics of HfO2.

  2. Silicon electro-optic modulator with high-permittivity gate dielectric layer

    Institute of Scientific and Technical Information of China (English)

    Mengxia Zhu; Zhiping Zhou; Dingshan Gao

    2009-01-01

    A high-permittivity (high-k) material is applied as the gate dielectric layer in a silicon metal-oxidesemiconductor (MOS) capacitor to form a special electro-optic (EO) modulator.Both induced charge density and modulation efficiency in the proposed modulator are improved due to the special structure design and the application of the high-k material.The device has an ultra-compact dimension of 691 μm in length.

  3. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    Science.gov (United States)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  4. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Energy Technology Data Exchange (ETDEWEB)

    Besleaga, C.; Stan, G.E.; Pintilie, I. [National Institute of Materials Physics, 405A Atomistilor, 077125 Magurele-Ilfov (Romania); Barquinha, P.; Fortunato, E. [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal); Martins, R., E-mail: rm@uninova.pt [CENIMAT/I3N, Departamento de Ciência dos Materiais, Faculdade de Ciências e Tecnologia, FCT, Universidade Nova de Lisboa, and CEMOP-UNINOVA, 2829-516 Caparica (Portugal)

    2016-08-30

    Highlights: • TFTs based on IGZO channel semiconductor and AlN gate dielectric were fabricated. • AlN films – a viable and cheap gate dielectric alternative for transparent TFTs. • Influence of gate dielectric layer thickness on TFTs electrical characteristics. • No degradation of AlN gate dielectric was observed during devices stress testing. - Abstract: The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium–gallium–zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium–gallium–zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  5. Interfacial reaction and electrical properties of HfO2 film gate dielectric prepared by pulsed laser deposition in nitrogen: role of rapid thermal annealing and gate electrode.

    Science.gov (United States)

    Wang, Yi; Wang, Hao; Ye, Cong; Zhang, Jun; Wang, Hanbin; Jiang, Yong

    2011-10-01

    The high-k dielectric HfO(2) thin films were deposited by pulsed laser deposition in nitrogen atmosphere. Rapid thermal annealing effect on film surface roughness, structure and electrical properties of HfO(2) film was investigated. The mechanism of interfacial reaction and the annealing atmosphere effect on the interfacial layer thickness were discussed. The sample annealed in nitrogen shows an amorphous dominated structure and the lowest leakage current density. Capacitors with high-k HfO(2) film as gate dielectric were fabricated, using Pt, Au, and Ti as the top gate electrode whereas Pt constitutes the bottom side electrode. At the gate injection case, the Pt- and Au-gated metal oxide semiconductor devices present a lower leakage current than that of the Ti-gated device, as well as similar leakage current conduction mechanism and interfacial properties at the metal/HfO(2) interface, because of their close work function and chemical properties.

  6. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  7. Highly stable organic field-effect transistors with engineered gate dielectrics (Conference Presentation)

    Science.gov (United States)

    Kippelen, Bernard; Wang, Cheng-Yin; Fuentes-Hernandez, Canek; Yun, Minseong; Singh, Ankit K.; Dindar, Amir; Choi, Sangmoo; Graham, Samuel

    2016-11-01

    Organic field-effect transistors (OFETs) have the potential to lead to low-cost flexible displays, wearable electronics, and sensors. While recent efforts have focused greatly on improving the maximum charge mobility that can be achieved in such devices, studies about the stability and reliability of such high performance devices are relatively scarce. In this talk, we will discuss the results of recent studies aimed at improving the stability of OFETs under operation and their shelf lifetime. In particular, we will focus on device architectures where the gate dielectric is engineered to act simultaneously as an environmental barrier layer. In the past, our group had demonstrated solution-processed top-gate OFETs using TIPS-pentacene and PTAA blends as a semiconductor layer with a bilayer gate dielectric layer of CYTOP/Al2O3, where the oxide layer was fabricated by atomic layer deposition, ALD. Such devices displayed high operational stability with little degradation after 20,000 on/off scan cycles or continuous operation (24 h), and high environmental stability when kept in air for more than 2 years, with unchanged carrier mobility. Using this stable device geometry, simple circuits and sensors operating in aqueous conditions were demonstrated. However, the Al2O3 layer was found to degrade due to corrosion under prolonged exposure in aqueous solutions. In this talk, we will report on the use of a nanolaminate (NL) composed of Al2O3 and HfO2 by ALD to replace the Al2O3 single layer in the bilayer gate dielectric use in top-gate OFETs. Such OFETs were found to operate under harsh condition such as immersion in water at 95 °C. This work was funded by the Department of Energy (DOE) through the Bay Area Photovoltaics Consortium (BAPVC) under Award Number DE-EE0004946.

  8. Solution-Processed Rare-Earth Oxide Thin Films for Alternative Gate Dielectric Application.

    Science.gov (United States)

    Zhuang, Jiaqing; Sun, Qi-Jun; Zhou, Ye; Han, Su-Ting; Zhou, Li; Yan, Yan; Peng, Haiyan; Venkatesh, Shishir; Wu, Wei; Li, Robert K Y; Roy, V A L

    2016-11-16

    Previous investigations on rare-earth oxides (REOs) reveal their high possibility as dielectric films in electronic devices, while complicated physical methods impede their developments and applications. Herein, we report a facile route to fabricate 16 REOs thin insulating films through a general solution process and their applications in low-voltage thin-film transistors as dielectrics. The formation and properties of REOs thin films are analyzed by atomic force microscopy (AFM), X-ray diffraction (XRD), spectroscopic ellipsometry, water contact angle measurement, X-ray photoemission spectroscopy (XPS), and electrical characterizations, respectively. Ultrasmooth, amorphous, and hydrophilic REO films with thickness around 10 nm have been obtained through a combined spin-coating and postannealing method. The compositional analysis results reveal the formation of RE hydrocarbonates on the surface and silicates at the interface of REOs films annealed on Si substrate. The dielectric properties of REO films are investigated by characterizing capacitors with a Si/Ln2O3/Au (Ln = La, Gd, and Er) structure. The observed low leakage current densities and large areal capacitances indicate these REO films can be employed as alternative gate dielectrics in transistors. Thus, we have successfully fabricated a series of low-voltage organic thin-film transistors based on such sol-gel derived REO films to demonstrate their application in electronics. The optimization of REOs dielectrics in transistors through further surface modification has also been studied. The current study provides a simple solution process approach to fabricate varieties of REOs insulating films, and the results reveal their promising applications as alternative gate dielectrics in thin-film transistors.

  9. Inducing transparency with large magnetic response and group indices by hybrid dielectric metamaterials.

    Science.gov (United States)

    Chen, Cheng-Kuang; Lai, Yueh-Chun; Yang, Yu-Hang; Chen, Chia-Yun; Yen, Ta-Jen

    2012-03-26

    We present metamaterial-induced transparency (MIT) phenomena with enhanced magnetic fields in hybrid dielectric metamaterials. Using two hybrid structures of identical-dielectric-constant resonators (IDRs) and distinct-dielectric-constant resonators (DDRs), we demonstrate a larger group index (ng~354), better bandwidth-delay product (BDP~0.9) than metallic-type metamaterials. The keys to enable these properties are to excite either the trapped mode or the suppressed mode resonances, which can be managed by controlling the contrast of dielectric constants between the dielectric resonators in the hybrid metamaterials.

  10. High-Performance Wrap-Gated InGaAs Nanowire Field-Effect Transistors with Sputtered Dielectrics

    OpenAIRE

    Li-Fan Shen; SenPo Yip; Zai-xing Yang; Ming Fang; TakFu Hung; Pun, Edwin Y. B.; Ho, Johnny C.

    2015-01-01

    Although wrap-gated nanowire field-effect-transistors (NWFETs) have been explored as an ideal electronic device geometry for low-power and high-frequency applications, further performance enhancement and practical implementation are still suffering from electron scattering on nanowire surface/interface traps between the nanowire channel and gate dielectric as well as the complicated device fabrication scheme. Here, we report the development of high-performance wrap-gated InGaAs NWFETs using c...

  11. Hybrid energy harvesting systems, using piezoelectric elements and dielectric polymers

    Science.gov (United States)

    Cornogolub, Alexandru; Cottinet, Pierre-Jean; Petit, Lionel

    2016-09-01

    Interest in energy harvesting applications has increased a lot during recent years. This is especially true for systems using electroactive materials like dielectric polymers or piezoelectric materials. Unfortunately, these materials despite multiple advantages, present some important drawbacks. For example, many dielectric polymers demonstrated high energy densities; they are cheap, easy to process and can be easily integrated in many different structures. But at the same time, dielectric polymer generators require an external energy supply which could greatly compromise their autonomy. Piezoelectric systems, on the other hand, are completely autonomous and can be easily miniaturized. However, most common piezoelectric materials present a high rigidity and are brittle by nature and therefore their integration could be difficult. This paper investigates the possibility of using hybrid systems combining piezoelectric elements and dielectric polymers for mechanical energy harvesting applications and it is focused mainly on the problem of electrical energy transfer. Our objective is to show that such systems can be interesting and that it is possible to benefit from the advantages of both materials. For this, different configurations were considered and the problem of their optimization was addressed. The experimental work enabled us to prove the concept and identify the main practical limitations.

  12. Gate-Bias Stability Behavior Tailored by Dielectric Polymer Stereostructure in Organic Transistors.

    Science.gov (United States)

    Lee, Junghwi; Min, Honggi; Park, Namwoo; Jeong, Heejeong; Han, Singu; Kim, Se Hyun; Lee, Hwa Sung

    2015-11-18

    Understanding charge trapping in a polymer dielectric is critical to the design of high-performance organic field-effect transistors (OFETs). We investigated the OFET stability as a function of the dielectric polymer stereostructure under a gate bias stress and during long-term operation. To this end, iso-, syn-, and atactic poly(methyl methacrylate) (PMMA) polymers with identical molecular weights and polydispersity indices were selected. The PMMA stereostructure was found to significantly influence the charge trapping behavior and trap formation in the polymer dielectrics. This influence was especially strong in the bulk region rather than in the surface region. The regular configurational arrangements (isotactic > syntactic > atactic) of the pendant groups on the PMMA backbone chain facilitated closer packing between the polymer interchains and led to a higher crystallinity of the polymer dielectric, which caused a reduction in the free volumes that act as sites for charge trapping and air molecule absorption. The PMMA dielectrics with regular stereostructures (iso- and syn-stereoisomers) exhibited more stable OFET operation under bias stress compared to devices prepared using irregular a-PMMA in both vacuum and air.

  13. Hybrid dual gate ferroelectric memory for multilevel information storage

    KAUST Repository

    Khan, Mohammad A.

    2015-01-01

    Here, we report hybrid organic/inorganic ferroelectric memory with multilevel information storage using transparent p-type SnO semiconductor and ferroelectric P(VDF-TrFE) polymer. The dual gate devices include a top ferroelectric field-effect transistor (FeFET) and a bottom thin-film transistor (TFT). The devices are all fabricated at low temperatures (∼200°C), and demonstrate excellent performance with high hole mobility of 2.7 cm2 V-1 s-1, large memory window of ∼18 V, and a low sub-threshold swing ∼-4 V dec-1. The channel conductance of the bottom-TFT and the top-FeFET can be controlled independently by the bottom and top gates, respectively. The results demonstrate multilevel nonvolatile information storage using ferroelectric memory devices with good retention characteristics.

  14. Dielectric properties of hybrid perovskites and drift-diffusion modeling of perovskite cells

    OpenAIRE

    Pedesseau, Laurent; Kepenekian, M.; Sapori, Daniel; Huang, Y.; Rolland, Alain; Beck, Alexandre; C. Cornet; Durand, Olivier; Wang, Shijian; Katan, Claudine; Even, Jacky

    2016-01-01

    International audience; A method based on DFT is used to obtained dielectric profiles. The high frequency ε∞(z) and the static εs(z) dielectric profiles are compared for 3D, 2D-3D and 2D Hybrid Organic Perovskites (HOP). A dielectric confinement is observed for the 2D materials between the high dielectric constant of the inorganic part and the low dielectric constant of the organic part. The effect of the ionic contribution on the dielectric constant is also shown. The quantum and dielectric ...

  15. Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-K gate dielectric

    Institute of Scientific and Technical Information of China (English)

    Li Cong; Zhuang Yi-Qi; Zhang Li; Bao Jun-Lin

    2012-01-01

    By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates,an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-κ gate dielectric has been developed.Using the derived model,the influences of fringing-induced barrier lowering (FIBL) on surface potential,subthreshold current,DIBL,and subthreshold swing are investigated.It is found that for the same equivalent oxide thickness,the gate insulator with high-κ dielectric degrades the short-channel performance of the DMSG MOSFET.The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

  16. Graphene-on-dielectric micromembrane for optoelectromechanical hybrid devices

    DEFF Research Database (Denmark)

    Schmid, Silvan; Bagci, Tolga; Zeuthen, Emil;

    2013-01-01

    Due to their exceptional mechanical and optical properties, dielectric silicon nitride (SiN) micromembranes have become the centerpiece of many optomechanical experiments. Efficient capacitive coupling of the membrane to an electrical system would facilitate exciting hybrid optoelectromechanical ...... devices. However, capacitive coupling of such SiN membranes is rather weak. Here we add a single layer of graphene on SiN micromembranes (SiN-G) and compare the electromechanical coupling and mechanical properties to bare SiN membranes and to membranes coated with an aluminium layer (Si...

  17. Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

    Institute of Scientific and Technical Information of China (English)

    Wu Chia-Song; Liu Hsing-Chung

    2009-01-01

    This paper investigates the feasibility of using a lanthanum oxide thin film (La_2O_3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La_2O_3 thickness. The thin La_2O_3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively.La_2O_3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 ℃ because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La_2O_3 thin film was thermally stable.The DC and RF characteristics of Pt/La_2O_3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined.The measurements indicated that the transistor with the Pt/La_2O_3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La_2O_3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

  18. Multiple orbital angular momentum generated by dielectric hybrid phase element

    Science.gov (United States)

    Wang, Xuewen; Kuchmizhak, Aleksandr; Hu, Dejiao; Li, Xiangping

    2017-09-01

    Vortex beam carrying multiple orbital angular momentum provides a new degree of freedom to manipulate light leading to the various exciting applications as trapping, quantum optics, information multiplexing, etc. Helical wavefront can be generated either via the geometric or the dynamic phase arising from a space-variant birefringence (q-plate) or from phase accumulation through propagation (spiral-phase-plate), respectively. Using fast direct laser writing technique we fabricate and characterize novel hybrid q-plate generating vortex beam simultaneously carrying two different high-order topological charges, which arise from the spin-orbital conversion and the azimuthal height variation of the recorded structures. We approve the versatile concept to generate multiple-OAM vortex beams combining the spin-orbital interaction and the phase accumulation in a single micro-scale device, a hybrid dielectric phase plate.

  19. Temperature Effects on a-IGZO Thin Film Transistors Using HfO2 Gate Dielectric Material

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2014-01-01

    Full Text Available This study investigated the temperature effect on amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using hafnium oxide (HfO2 gate dielectric material. HfO2 is an attractive candidate as a high-κ dielectric material for gate oxide because it has great potential to exhibit superior electrical properties with a high drive current. In the process of integrating the gate dielectric and IGZO thin film, postannealing treatment is an essential process for completing the chemical reaction of the IGZO thin film and enhancing the gate oxide quality to adjust the electrical characteristics of the TFTs. However, the hafnium atom diffused the IGZO thin film, causing interface roughness because of the stability of the HfO2 dielectric thin film during high-temperature annealing. In this study, the annealing temperature was optimized at 200°C for a HfO2 gate dielectric TFT exhibiting high mobility, a high ION/IOFF ratio, low IOFF current, and excellent subthreshold swing (SS.

  20. MBE and ALD grown High k Dielectrics Gate Stacks on GaN

    Science.gov (United States)

    Chang, Y. C.; Lee, K. Y.; Lee, W. C.; Lin, T. D.; Lee, Y. J.; Huang, M. L.; Hong, M.; Kwo, J.; Wang, Y. H.

    2007-03-01

    III-nitride compound semiconductors are attractive for high-temperature and high-power MOSFET applications due to their intrinsic properties of wide band gap, high breakdown field, and high saturation velocity under high fields. In this work GaN-based high k MOS diodes were fabricated using MBE-grown Ga2O3(Gd2O3), MBE-grown HfO2 and ALD-grown HfO2 as the gate dielectrics with dielectric constants of 14.7, 17.4 and 16.5, respectively. All MOS diodes exhibited low leakage (XPS and with the bandgaps of the oxides. For example, the ALD-grown HfO2-GaN at the interfaces gave approximately δEC and δEV of 1.2 eV and 1.1 eV, respectively.

  1. Analytical modeling of label free biosensor using charge plasma based gate underlap dielectric modulated MOSFET

    Science.gov (United States)

    Chanda, Manash; Das, Rahul; Kundu, Atanu; Sarkar, Chandan K.

    2017-04-01

    In this paper charge plasma based dielectric modulated four gated MOSFET (CP-GUDM-MOSFET) has been proposed for the efficacy of label free electrical detection of the biomolecules. To achieve low thermal budgeting, charge-plasma concept is employed using appropriate metal work function electrodes. Extensive simulations have been done using the Sentaurus TCAD to validate the proposed architecture. An analytical modeling has also been done on surface potential and drain current to consolidate the feasibility of the structure. Significant improvements in the on current (ION) and threshold voltage have been observed in presence of the charged biomolecules. The performance of proposed structure is found to be sensitive to gate-oxide thickness variations. High sensitivity of the proposed CP-GUDM-MOSFET based biosensor with low thermal budgeting scheme; simple structure and its compatibility with the existing CMOS processes make it an exciting alternative to the conventional FET-based biosensors.

  2. Gate-Defined Quantum Devices Realized in InGaAs/InP by Incorporating a High-κ Layer as Gate Dielectric

    Science.gov (United States)

    Sun, Jie; Larsson, Marcus; Xu, H. Q.

    2011-12-01

    Single and double quantum dot devices are realized in InGaAs/InP heterostructures by top gating technology with incorporated High-κ HfO2 gate dielectric layers. At 300 mK, Coulomb blockade effects are observed in as-fabricated devices, and the charge states can be measured by the integrated quantum point contacts. The developed technology should stimulate the research on quantum devices made from materials to which the gating technology is often difficult to apply due to low Schottky barrier height.

  3. Organic thin film transistors with polymer brush gate dielectrics synthesized by atom transfer radical polymerization

    DEFF Research Database (Denmark)

    Pinto, J.C.; Whiting, G.L.; Khodabakhsh, S.

    2008-01-01

    , synthesized by atom transfer radical polymerization (ATRP), were used to fabricate low voltage OFETs with both evaporated pentacene and solution deposited poly(3-hexylthiophene). The semiconductor-dielectric interfaces in these systems were studied with a variety of methods including scanning force microscopy......Low operating voltage is an important requirement that must be met for industrial adoption of organic field-effect transistors (OFETs). We report here solution fabricated polymer brush gate insulators with good uniformity, low surface roughness and high capacitance. These ultra thin polymer films...

  4. Performance investigations of novel dual-material gate(DMG) MOSFET with dielectric pockets(DP)

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    Dual-material gate MOSFET with dielectric pockets (DMGDP MOSFET) is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond. The short-channel effects (SCE) can be effectively suppressed by the insulator near the source/drain regions. And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate. The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied. Compared to the experimental data from Jurczak et al., the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET. The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node. The higher fT of 390 GHz is achieved, which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm. Finally, the design guideline and the optimal regions of the DMGDP MOSFET are discussed.

  5. Performance investigations of novel dual-material gate (DMG)MOSFET with dielectric pockets(DP)

    Institute of Scientific and Technical Information of China (English)

    LUAN SuZhen; LIU HongXia; JIA RenXu

    2009-01-01

    Dual-material gate MOSFET with dielectric pockets(DMGDP MOSFET)is proposed to eliminate the potential weakness of the DP MOSFET for CMOS scaling toward the 32 nm gate length and beyond.The short-channel effects(SCE)can be effectively suppressed by the insulator near the source/drain regions.And the suppression capability can be even better than the DP MOSFET due to the drain bias absorbed by the screen gate.The speed performance and electronic characteristics of the DMGDP MOSFET are comprehensively studied.Compared to the experimental data from Jurczak et al.,the DMGDP PMOSFET exhibits good subthreshold characteristics and the on-state current is almost the twice that of the DP PMOSFET.The intrinsic delay of the NMOS reaches 21% greater than the DP MOSFET for 32 nm node.The higher fT of 390 GHz is achieved,which is a 32% enhancement in comparison with the DP MOSFET when the gate length is 50 nm.Finally,the design guideline and the opUmal regions of the DMGDP MOSFET are discussed.

  6. Effect of spacer dielectric engineering on Asymmetric Source Underlapped Double Gate MOSFET using Gate Stack

    Science.gov (United States)

    Chattopadhyay, Ankush; Dasgupta, Arpan; Das, Rahul; Kundu, Atanu; Sarkar, Chandan K.

    2017-01-01

    In this paper, the use of high-k spacers in a source underlapped nMOSFET is explored. The effects have been reported by varying the dielectric constant of the spacer from 3.9 to 22.5 and the study includes a comparison of analog parameters such as transconductance, transconductance generation factor, intrinsic gain, and RF parameters such as parasitic capacitances, resistances, and cut-off frequency. The RF parameters are calculated using the Non-Quasi Static (NQS) Approach which is required for sub 20 nm technology node. The device with high-k spacers features an improvement of 33% in DIBL, significantly increases the on current and reducing the off current by 60%. However, there is a slight compromise in the RF performance of the device, owing to an increase in intrinsic capacitance by about 0.35 fF. The Voltage Transfer Characteristics (VTC) and AC gain analysis of the circuit is also done in this paper. The circuit performance using single stage amplifier with the proposed device as the driver MOS has been analysed. High-k spacers also account for 19% improvement in small signal gain when used in a single stage amplifier circuit.

  7. Gate bias stress stability under light irradiation for indium zinc oxide thin-film transistors based on anodic aluminium oxide gate dielectrics

    Science.gov (United States)

    Li, Min; Lan, Linfeng; Xu, Miao; Wang, Lei; Xu, Hua; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Yao, Rihui; Peng, Junbiao

    2011-11-01

    Thin-film transistors (TFTs) using indium zinc oxide as the active layer and anodic aluminium oxide (Al2O3) as the gate dielectric layer were fabricated. The device showed an electron mobility of as high as 10.1 cm2 V-1 s-1, an on/off current ratio of as high as ~108, and a turn-on voltage (Von) of only -0.5 V. Furthermore, this kind of TFTs was very stable under positive bias illumination stress. However, when the device experienced negative bias illumination stress, the threshold voltage shifted to the positive direction. It was found that the instability under negative bias illumination stress (NBIS) was due to the electrons from the Al gate trapping into the Al2O3 dielectric when exposed to the illuminated light. Using a stacked structure of Al2O3/SiO2 dielectrics, the device became more stable under NBIS.

  8. Influence of Gate Dielectric and Its Surface Treatment on Electrical Characteristics of Solution-Processed ZnO Transistors.

    Science.gov (United States)

    Song, Dong-Seok; Kim, Jae-Hyun; Jung, Ji-Hoon; Bae, Jin-Hyuk; Zhang, Xue; Park, Ji-Ho; Park, Jaehoon

    2016-02-01

    We report how interface treatments affect electrical performance, including subthreshold characteristics, in solution-processed transparent metal oxide thin-film transistors (TFTs) with SiO2 and SiNx gate dielectrics. Ultra-violet (UV) ozone treatment and O2 plasma treatment are carried out as a surface treatment of the interface between a spin-coated zinc oxide (ZnO) layer and a gate dielectric. With the SiO2 dielectric, UV ozone treatment dominantly affects subthreshold characteristics, while O2 plasma treatment produces enhanced mobility and lower threshold voltage shift. With the SiNx dielectric, every electrical parameter including mobility, threshold voltage shift, and subthreshold characteristics is enhanced by 02 plasma treatment. Our experimental results demonstrate that interface engineering treatments variously influence the electrical performance in solution-processed ZnO TFTs.

  9. Layer-by-layer structured polymer/TiO2 thin film and its gate dielectric application.

    Science.gov (United States)

    Park, Bong Jun; Park, Jae Hoon; Choi, Jong Sun; Choi, Hyoung Jin

    2010-07-01

    Composite materials of the polymer and inorganic dielectric material have been investigated due to synergistic effect of both flexible properties of the polymer and dielectric properties of the inorganic material. In this study, poly(methyl methacrylate-co-methacrylic acid)/titanium dioxide (PMMA-co-MAA/TiO2) bilayer films were fabricated using a spin coating method followed by a self assembled sol-gel process and then examined for a gate dielectric application of the OTFT. Fracture and surface morphologies of the bilayer film on silicon wafer was observed via both SEM and AFM. Dielectric constant of the composite film synthesized was found to be larger than that of pure polymer film. In addition, with pentacene as a conducting layer, device performance of the composite film was characterized, and it was found that the threshold gate voltage was reduced while the field induced current was increased.

  10. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    Science.gov (United States)

    Tari, Alireza; Lee, Czang-Ho; Wong, William S.

    2015-07-01

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO2, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiNx, and (3) a PECVD SiOx/SiNx dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the Vo concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiNx (high Vo) and SiO2 (low Vo) had the highest and lowest conductivity, respectively. A PECVD SiOx/SiNx dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  11. Dielectric engineered symmetric underlap double gate tunnel FET (DGTFET): An investigation towards variation of dielectric materials

    Science.gov (United States)

    Mallikarjunarao; Ranjan, Rajeev; Pradhan, K. P.; Sahu, P. K.

    2016-08-01

    In this article, an underlap silicon n-channel Tunnel Field Effect Transistor (n-TFET) i.e., symmetric single-k spacer (SSS) Double Gate N-TFET (DGTFET) is proposed to improve the performance of the device by using different spacer materials. A detailed investigation has been made on the proposed device characteristics with the help of extensive 2-D TCAD simulations. It is demonstrated that an optimized underlap length is chosen for a significant on-state current (Ion) without deteriorating the off-state current (Ioff) and sub-threshold swing (SS). The proposed model with different spacer materials has been extensively analyzed by using transfer characteristics, output characteristics, and analog/RF characteristics. The structure is optimized based on the comparison among various performance metrics like Ion, Ioff, SS, on-off ratio (Ion/Ioff), threshold (or) cut-off frequency (fT), and intrinsic delay with considering different spacer materials like SiO2 (k = 3.9), Si3N4 (k = 7.5), and HfO2 (k = 25).

  12. Fluorinated polyimide gate dielectrics for the advancing the electrical stability of organic field-effect transistors.

    Science.gov (United States)

    Baek, Yonghwa; Lim, Sooman; Yoo, Eun Joo; Kim, Lae Ho; Kim, Haekyoung; Lee, Seung Woo; Kim, Se Hyun; Park, Chan Eon

    2014-09-10

    Organic field-effect transistors (OFETs) that operated with good electrical stability were prepared by synthesizing fluorinated polyimide (PI) gate dielectrics based on 6FDA-PDA-PDA PI and 6FDA-CF3Bz-PDA PI. 6FDA-PDA-PDA PI and 6FDA-CF3Bz-PDA PI contain 6 and 18 fluorine atoms per repeat unit, respectively. These fluorinated polymers provided smooth surface topographies and surface energies that decreased as the number of fluorine atoms in the polymer backbone increased. These properties led to a better crystalline morphology in the semiconductor film grown over their surfaces. The number of fluorine atoms in the PI backbone increased, the field-effect mobility improved, and the threshold voltage shifted toward positive values (from -0.38 to +2.21 V) in the OFETs with pentacene and triethylsilylethynyl anthradithiophene. In addition, the highly fluorinated polyimide dielectric showed negligible hysteresis and a notable gate bias stability under both a N2 environment and ambient air.

  13. Fabrication of Pentacene Thin-Film Transistors with Patterned Polyimide Photoresist as Gate Dielectrics and Research of Their Degradation

    Institute of Scientific and Technical Information of China (English)

    LIANG Yan; DONG Gui-Fang; HU Yuan-Chuan; HU Yan; WANG Li-Duo; QIU Yong

    2004-01-01

    @@ Pentacene organic thin-film transistors using commercial photoresist as gate dielectrics were fabricated. The photoresist was spin-coated and directly patterned by photolithography. As a result, the fabrication processes were greatly reduced. With the characteristics of the transistors measured, the degradation of the transistors was investigated. In the search for the factors causing degradation, a transistor using poly(methyl methacrylate)as the gate dielectric was also fabricated. It is regarded that the degradation is caused by the changes at the interface between photoresist and pentacene film.

  14. Low-Temperature Solution-Processed Gate Dielectrics for High-Performance Organic Thin Film Transistors

    Directory of Open Access Journals (Sweden)

    Jaekyun Kim

    2015-10-01

    Full Text Available A low-temperature solution-processed high-k gate dielectric layer for use in a high-performance solution-processed semiconducting polymer organic thin-film transistor (OTFT was demonstrated. Photochemical activation of sol-gel-derived AlOx films under 150 °C permitted the formation of a dense film with low leakage and relatively high dielectric-permittivity characteristics, which are almost comparable to the results yielded by the conventionally used vacuum deposition and high temperature annealing method. Octadecylphosphonic acid (ODPA self-assembled monolayer (SAM treatment of the AlOx was employed in order to realize high-performance (>0.4 cm2/Vs saturation mobility and low-operation-voltage (<5 V diketopyrrolopyrrole (DPP-based OTFTs on an ultra-thin polyimide film (3-μm thick. Thus, low-temperature photochemically-annealed solution-processed AlOx film with SAM layer is an attractive candidate as a dielectric-layer for use in high-performance organic TFTs operated at low voltages.

  15. Ternary rare-earth based alternative gate-dielectrics for future integration in MOSFETs

    Energy Technology Data Exchange (ETDEWEB)

    Schubert, Juergen; Lopes, Joao Marcelo; Durgun Oezben, Eylem; Luptak, Roman; Lenk, Steffi; Zander, Willi; Roeckerath, Martin [IBN 1-IT, Forschungszentrum Juelich, 52425 Juelich (Germany)

    2009-07-01

    The dielectric SiO{sub 2} has been the key to the tremendous improvements in Si-based metal-oxide-semiconductor (MOS) device performance over the past four decades. It has, however, reached its limit in terms of scaling since it exhibits a leakage current density higher than 1 A/cm{sup 2} and does not retain its intrinsic physical properties at thicknesses below 1.5 nm. In order to overcome these problems and keep Moore's law ongoing, the use of higher dielectric constant (k) gate oxides has been suggested. These high-k materials must satisfy numerous requirements such as the high k, low leakage currents, suitable band gap und offsets to silicon. Rare-earth based dielectrics are promising materials which fulfill these needs. We will review the properties of REScO{sub 3} (RE = La, Dy, Gd, Sm, Tb) and LaLuO{sub 3} thin films, grown with pulsed laser deposition, e-gun evaporation or molecular beam deposition, integrated in capacitors and transistors. A k > 20 for the REScO{sub 3} (RE = Dy, Gd) and around 30 for (RE = La, Sm, Tb) and LaLuO{sub 3} are obtained. Transistors prepared on SOI and sSOI show mobility values up to 380 cm{sup 2}/Vs on sSOI, which are comparable to such prepared with HfO{sub 2}.

  16. Investigation of high-k yttrium copper titanate thin films as alternative gate dielectrics

    Science.gov (United States)

    Grazia Monteduro, Anna; Ameer, Zoobia; Rizzato, Silvia; Martino, Maurizio; Caricato, Anna Paola; Tasco, Vittorianna; Chaitanya Lekshmi, Indira; Hazarika, Abhijit; Choudhury, Debraj; Sarma, D. D.; Maruccio, Giuseppe

    2016-10-01

    Nearly amorphous high-k yttrium copper titanate thin films deposited by laser ablation were investigated in both metal-oxide-semiconductor (MOS) and metal-insulator-metal (MIM) junctions in order to assess the potentialities of this material as a gate oxide. The trend of dielectric parameters with film deposition shows a wide tunability for the dielectric constant and AC conductivity, with a remarkably high dielectric constant value of up to 95 for the thick films and conductivity as low as 6  ×  10-10 S cm-1 for the thin films deposited at high oxygen pressure. The AC conductivity analysis points out a decrease in the conductivity, indicating the formation of a blocking interface layer, probably due to partial oxidation of the thin films during cool-down in an oxygen atmosphere. Topography and surface potential characterizations highlight differences in the thin film microstructure as a function of the deposition conditions; these differences seem to affect their electrical properties.

  17. Electrical and Structural Characteristics of High-k Gate Dielectrics with Epitaxial Si3N4 Interfacial Layer on Si(111)

    Science.gov (United States)

    Sim, Hyunjun; Samantaray, Chandan B.; Lee, Taeho; Yeom, Hanwoong; Hwang, Hyunsang

    2004-12-01

    In this study, the electrical and structural characteristics of Gd2O3 gate dielectrics with an epitaxial Si3N4 interfacial layer grown on Si(111) were investigated. Compared with control Gd2O3 gate dielectrics deposited on HF-last treated Si (111), the Gd2O3 gate dielectrics with an epitaxial Si3N4 interfacial layer exhibited excellent electrical characteristics such as low leakage current density and low interface state density. These characteristics are due to a high-quality interfacial layer formation on Si. Transmission electron microscopy (TEM), X-ray photoelectron spectroscopy (XPS) and Fourier transform infrared (FTIR) spectroscopy were employed to analyze the structures of the gate dielectrics and interfacial layer. High-k gate dielectrics with an epitaxial Si3N4 interfacial layer have considerable potential for future use in sub-0.1 μm metal oxide semiconductor field-effect transistors (MOSFETs).

  18. Gate-tunable electron interaction in high-κ dielectric films

    Science.gov (United States)

    Kondovych, Svitlana; Luk’Yanchuk, Igor; Baturina, Tatyana I.; Vinokur, Valerii M.

    2017-02-01

    The two-dimensional (2D) logarithmic character of Coulomb interaction between charges and the resulting logarithmic confinement is a remarkable inherent property of high dielectric constant (high-κ) thin films with far reaching implications. Most and foremost, this is the charge Berezinskii-Kosterlitz-Thouless transition with the notable manifestation, low-temperature superinsulating topological phase. Here we show that the range of the confinement can be tuned by the external gate electrode and unravel a variety of electrostatic interactions in high-k films. We find that by reducing the distance from the gate to the film, we decrease the spatial range of the 2D long-range logarithmic interaction, changing it to predominantly dipolar or even to exponential one at lateral distances exceeding the dimension of the film-gate separation. Our findings offer a unique laboratory for the in-depth study of topological phase transitions and related phenomena that range from criticality of quantum metal- and superconductor-insulator transitions to the effects of charge-trapping and Coulomb scalability in memory nanodevices.

  19. Role of deposition and annealing of the top gate dielectric in a-IGZO TFT-based dual-gate ion-sensitive field-effect transistors

    Science.gov (United States)

    Kumar, Narendra; Sutradhar, Moitri; Kumar, Jitendra; Panda, Siddhartha

    2017-03-01

    The deposition of the top gate dielectric in thin film transistor (TFT)-based dual-gate ion-sensitive field-effect transistors (DG ISFETs) is critical, and expected not to affect the bottom gate TFT characteristics, while providing a higher pH sensitive surface and efficient capacitive coupling between the gates. Amorphous Ta2O5, in addition to having good sensing properties, possesses a high dielectric constant of ∼25 making it well suited as the top gate dielectric in a DG ISFET by providing higher capacitive coupling (ratio of C top/C bottom) leading to higher amplification. To avoid damage of the a-IGZO channel reported to be caused by plasma exposure, deposition of Ta2O5 by e-beam evaporation followed by annealing was investigated in this work to obtain sensitivity over the Nernst limit. The deteriorated bottom gate TFT characteristics, indicated by an increase in the channel conductance, confirmed that plasma exposure is not the sole contributor to the changes. Oxygen vacancies at the Ta2O5/a-IGZO interface, which emerged during processing, increased the channel conductivity, became filled by optimum annealing in oxygen at 400 °C for 1 h, which was confirmed by an x-ray photoelectron spectroscopy depth profiling analysis. The obtained pH sensitivity of the TFT-based DG ISFET was 402 mV pH‑1, which is about 6.8 times the Nernst limit (59 mV pH‑1). The concept of capacitive coupling was also demonstrated by simulating an a-IGZO-based DG TFT structure. Here, the exposure of the top gate dielectric to the electrolyte without applying any top gate bias led to changes in the measured threshold voltage of the bottom gate TFT, and this obviated the requirement of a reference electrode needed in conventional ISFETs and other reported DG ISFETs. These devices, with high sensitivities and requiring low volumes (∼2 μl) of analyte solution, could be potential candidates for utilization as chemical sensors and biosensors.

  20. Approaching Defect-free Amorphous Silicon Nitride by Plasma-assisted Atomic Beam Deposition for High Performance Gate Dielectric

    Science.gov (United States)

    Tsai, Shu-Ju; Wang, Chiang-Lun; Lee, Hung-Chun; Lin, Chun-Yeh; Chen, Jhih-Wei; Shiu, Hong-Wei; Chang, Lo-Yueh; Hsueh, Han-Ting; Chen, Hung-Ying; Tsai, Jyun-Yu; Lu, Ying-Hsin; Chang, Ting-Chang; Tu, Li-Wei; Teng, Hsisheng; Chen, Yi-Chun; Chen, Chia-Hao; Wu, Chung-Lin

    2016-06-01

    In the past few decades, gate insulators with a high dielectric constant (high-k dielectric) enabling a physically thick but dielectrically thin insulating layer, have been used to replace traditional SiOx insulator and to ensure continuous downscaling of Si-based transistor technology. However, due to the non-silicon derivative natures of the high-k metal oxides, transport properties in these dielectrics are still limited by various structural defects on the hetero-interfaces and inside the dielectrics. Here, we show that another insulating silicon compound, amorphous silicon nitride (a-Si3N4), is a promising candidate of effective electrical insulator for use as a high-k dielectric. We have examined a-Si3N4 deposited using the plasma-assisted atomic beam deposition (PA-ABD) technique in an ultra-high vacuum (UHV) environment and demonstrated the absence of defect-related luminescence; it was also found that the electronic structure across the a-Si3N4/Si heterojunction approaches the intrinsic limit, which exhibits large band gap energy and valence band offset. We demonstrate that charge transport properties in the metal/a-Si3N4/Si (MNS) structures approach defect-free limits with a large breakdown field and a low leakage current. Using PA-ABD, our results suggest a general strategy to markedly improve the performance of gate dielectric using a nearly defect-free insulator.

  1. Analysis of Non-Conventional Hybrid MOSFET Structure for Gate Leakage Current

    Directory of Open Access Journals (Sweden)

    RANA Ashwani K.

    2011-10-01

    Full Text Available A non-conventional hybrid MOSFET (HMOSstructure has been proposed to reduce the gate leakagecurrent. This non-conventional hybrid MOSFET consistsof source/drain-to-gate non-overlap region and high-kgate stack. The gate leakage behaviour of HMOS hasbeen investigated with the help of compact analyticalmodel, which is backed by Sentaurus Simulation. Ourmodel sustains a very good agreement between the modeland TCAD result. It is found that HMOS structure hasreduced the gate leakage current to great extent ascompared to conventional overlapped MOSFETstructure.

  2. Triple-wavelength infrared plasmonic thermal emitter using hybrid dielectric materials in periodic arrangement

    Science.gov (United States)

    Huang, Wei-Lun; Hsiao, Hui-Hsin; Tang, Ming-Ru; Lee, Si-Chen

    2016-08-01

    This paper presents a triple-wavelength infrared plasmonic thermal emitter using a periodic arrangement of hybrid dielectric materials within a tri-layer metal/dielectric/metal structure. The proposed arrangement makes it possible to sustain multiple resonance of localized surface plasmons (LSP), thereby providing an additional degree of freedom by which to vary the resonant wavelengths in the medium infrared region. Variations in the effective refractive index due to the different modal distribution within dielectric gratings results in multiple LSP resonances, and the resonant wavelengths can be easily tuned by altering the compositions of hybrid dielectric materials. The measured dispersion relation diagram and the finite difference time domain simulation indicated that the resonances were localized. They also indicate that the magnetic fields generated by the multiple LSP modes exhibit distribution patterns similar to that of a standing wave in the periodic arrangement of the hybrid dielectric layer, each of which presents an emission peak corresponding to a different modal order.

  3. Investigation of Ultraviolet Light Curable Polysilsesquioxane Gate Dielectric Layers for Pentacene Thin Film Transistors.

    Science.gov (United States)

    Shibao, Hideto; Nakahara, Yoshio; Uno, Kazuyuki; Tanaka, Ichiro

    2016-04-01

    Polysilsesquioxane (PSQ) comprising 3-methacryloxypropyl groups was investigated as an ultraviolet (UV)-light curable gate dielectric-material for pentacene thin film transistors (TFTs). The surface of UV-light cured PSQ films was smoother than that of thermally cured ones, and the pentacene layers deposited on the UV-Iight cured PSQ films consisted of larger grains. However, carrier mobility of the TFTs using the UV-light cured PSQ films was lower than that of the TFTs using the thermally cured ones. It was shown that the cross-linker molecules, which were only added to the UV-light cured PSQ films, worked as a major mobility-limiting factor for the TFTs.

  4. Ultimate Scaling of High-κ Gate Dielectrics: Higher-κ or Interfacial Layer Scavenging?

    Directory of Open Access Journals (Sweden)

    Takashi Ando

    2012-03-01

    Full Text Available Current status and challenges of aggressive equivalent-oxide-thickness (EOT scaling of high-κ gate dielectrics via higher-κ ( > 20 materials and interfacial layer (IL scavenging techniques are reviewed. La-based higher-κ materials show aggressive EOT scaling (0.5–0.8 nm, but with effective workfunction (EWF values suitable only for n-type field-effect-transistor (FET. Further exploration for p-type FET-compatible higher-κ materials is needed. Meanwhile, IL scavenging is a promising approach to extend Hf-based high-κ dielectrics to future nodes. Remote IL scavenging techniques enable EOT scaling below 0.5 nm. Mobility-EOT trends in the literature suggest that short-channel performance improvement is attainable with aggressive EOT scaling via IL scavenging or La-silicate formation. However, extreme IL scaling (e.g., zero-IL is accompanied by loss of EWF control and with severe penalty in reliability. Therefore, highly precise IL thickness control in an ultra-thin IL regime ( < 0.5 nm will be the key technology to satisfy both performance and reliability requirements for future CMOS devices.

  5. Current saturation in submicrometer graphene transistors with thin gate dielectric: experiment, simulation, and theory.

    Science.gov (United States)

    Han, Shu-Jen; Reddy, Dharmendar; Carpenter, Gary D; Franklin, Aaron D; Jenkins, Keith A

    2012-06-26

    Recently, graphene field-effect transistors (FET) with cutoff frequencies (f(T)) between 100 and 300 GHz have been reported; however, the devices showed very weak drain current saturation, leading to an undesirably high output conductance (g(ds)= dI(ds)/dV(ds)). A crucial figure-of-merit for analog/RF transistors is the intrinsic voltage gain (g(m)/g(ds)) which requires both high g(m) (primary component of f(T)) and low g(ds). Obtaining current saturation has become one of the key challenges in graphene device design. In this work, we study theoretically the influence of the dielectric thickness on the output characteristics of graphene FETs by using a surface-potential-based device model. We also experimentally demonstrate that by employing a very thin gate dielectric (equivalent oxide thickness less than 2 nm), full drain current saturation can be obtained for large-scale chemical vapor deposition graphene FETs with short channels. In addition to showing intrinsic voltage gain (as high as 34) that is comparable to commercial semiconductor FETs with bandgaps, we also demonstrate high frequency AC voltage gain and S21 power gain from s-parameter measurements.

  6. MOS Ge Diodes Based on High κ Gate Dielectrics Grown by MBE and ALD

    Science.gov (United States)

    Lee, Kun Yu; Lee, W. C.; Lin, T. D.; Lee, C. S.; Chang, Y. C.; Lee, Y. J.; Huang, M. L.; Wu, Y. D.; Hong, M.; Kwo, J.

    2007-03-01

    Germanium-based CMOS technology is gaining importance due to its high carrier mobility. In this work high κ gate-dielectrics, Al2O3, HfO2, Y2O3 and Ga2O3(Gd2O3) grown by MBE and ALD were investigated as passivation layers on n type Ge(100). Thermal stability of the MOS diodes was examined after various anneals. Prior to dielectric depositions surface pretreatments were applied to reduce the unwanted GeOx interfacial layer, and to improve electrical properties. Frequency dispersion of C-V curves was reduced by using a 350^oC preclean process, compared to the sample without precleaning. The leakage current density of ALD grown HfO2 (6.8nm) is 4.6×10-6 A/cm^2 with κ of 10.5. The improved CV curve was attributed to less GeOx formed at substrate and oxide interface, as confirmed by XPS analysis. However, with higher cleaning temperature over 400^oC, the CV curves showed additional inversion capacitance, possibly due to minority carriers from defect states near the interface.

  7. Hafnium germanosilicate thin films for gate and capacitor dielectric applications: thermal stability studies

    Science.gov (United States)

    Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

    2003-03-01

    The use of SiO_2-GeO2 mixtures in gate and capacitor dielectric applications is hampered by the inherent thermodynamic instability of germanium oxide. Studies to date have confirmed that germanium oxide is readily converted to elemental germanium [1,2]. In sharp contrast, germanium oxide is known to form stable compounds with transition metal oxides such as hafnium oxide (hafnium germanate, HfGeO_4) [3]. Thus, the incorporation of hafnium in SiO_2-GeO2 may be expected to enhance the thermal stability of germanium oxide via Hf-O-Ge bond formation. In addition, the introduction of a transition metal would simultaneously enhance the capacitance of the dielectric thereby permitting a thicker dielectric which reduces leakage current [4]. In this study, the thermal stability of PVD-grown hafnium germanosilicate (HfGeSiO) films was investigated. XPS, HR-TEM, C-V and I-V results of films after deposition and subsequent annealing treatments will be presented. The results indicate that the presence or formation of elemental germanium drastically affects the stability of the HfGeSiO films. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [2] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995) [3] P. M. Lambert, Inorganic Chemistry, 37, 1352 (1998) [4] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001)

  8. Universal logic gates via liquid-electronic hybrid divider

    KAUST Repository

    Zhou, Bingpu

    2012-01-01

    We demonstrated two-input microdroplet-based universal logic gates using a liquid-electronic hybrid divider. All 16 Boolean logic functions have been realized by manipulating the applied voltages. The novel platform consists of a microfluidic chip with integrated microdroplet detectors and external electronic components. The microdroplet detectors act as the communication media for fluidic and electronic information exchange. The presence or absence of microdroplets at the detector translates into the binary signal 1 or 0. The embedded micro-mechanical pneumatically actuated valve (PAV), fabricated using the well-developed multilayer soft lithography technique, offers biocompatibility, flexibility and accuracy for the on-chip realization of different logic functions. The microfluidic chip can be scaled up to construct large-scale microfluidic logic computation. On the other hand, the microfluidic chip with a specific logic function can be applied to droplet-based chemical reactions for on-demand bio or chemical analysis. Our experimental results have presented an autonomously driven, precision-controlled microfluidic chip for chemical reactions based on the IF logic function. © 2012 The Royal Society of Chemistry.

  9. The impact of gate dielectric materials on the light-induced bias instability in Hf-In-Zn-O thin film transistor

    Science.gov (United States)

    Kwon, Jang-Yeon; Jung, Ji Sim; Son, Kyoung Seok; Lee, Kwang-Hee; Park, Joon Seok; Kim, Tae Sang; Park, Jin-Seong; Choi, Rino; Jeong, Jae Kyeong; Koo, Bonwon; Lee, Sang Yoon

    2010-11-01

    This study examined the effect of gate dielectric materials on the light-induced bias instability of Hf-In-Zn-O (HIZO) transistor. The HfOx and SiNx gated devices suffered from a huge negative threshold voltage (Vth) shift (>11 V) during the application of negative-bias-thermal illumination stress for 3 h. In contrast, the HIZO transistor exhibited much better stability (<2.0 V) in terms of Vth movement under identical stress conditions. Based on the experimental results, we propose a plausible degradation model for the trapping of the photocreated hole carrier either at the channel/gate dielectric or dielectric bulk layer.

  10. Implementation of nanoscale circuits using dual metal gate engineered nanowire MOSFET with high-k dielectrics for low power applications

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Ajayan, J.

    2016-09-01

    This work covers the impact of dual metal gate engineered Junctionless MOSFET with various high-k dielectric in Nanoscale circuits for low power applications. Due to gate engineering in junctionless MOSFET, graded potential is obtained and results in higher electron velocity of about 31% for HfO2 than SiO2 in the channel region, which in turn improves the carrier transport efficiency. The simulation is done using sentaurus TCAD, ON current, OFF current, ION/IOFF ratio, DIBL, gain, transconductance and transconductance generation factor parameters are analysed. When using HfO2, DIBL shows a reduction of 61.5% over SiO2. The transconductance and transconductance generation factor shows an improvement of 44% and 35% respectively. The gain and output resistance also shows considerable improvement with high-k dielectrics. Using this device, inverter circuit is implemented with different high-k dielectric material and delay have been decreased by 4% with HfO2 when compared to SiO2. In addition, a significant reduction in power dissipation of the inverter circuit is obtained with high-k dielectric Dual Metal Surround Gate Junctionless Transistor than SiO2 based device. From the analysis, it is found that HfO2 will be a better alternative for the future nanoscale device.

  11. Effect of gate dielectrics on the performance of p-type Cu2O TFTs processed at room temperature

    KAUST Repository

    Al-Jawhari, Hala A.

    2013-12-01

    Single-phase Cu2O films with p-type semiconducting properties were successfully deposited by reactive DC magnetron sputtering at room temperature followed by post annealing process at 200°C. Subsequently, such films were used to fabricate bottom gate p-channel Cu2O thin film transistors (TFTs). The effect of using high-κ SrTiO3 (STO) as a gate dielectric on the Cu2O TFT performance was investigated. The results were then compared to our baseline process which uses a 220 nm aluminum titanium oxide (ATO) dielectric deposited on a glass substrate coated with a 200 nm indium tin oxide (ITO) gate electrode. We found that with a 150 nm thick STO, the Cu2O TFTs exhibited a p-type behavior with a field-effect mobility of 0.54 cm2.V-1.s-1, an on/off ratio of around 44, threshold voltage equaling -0.62 V and a sub threshold swing of 1.64 V/dec. These values were obtained at a low operating voltage of -2V. The advantages of using STO as a gate dielectric relative to ATO are discussed. © (2014) Trans Tech Publications, Switzerland.

  12. A study of GaN MOSFETs with atomic-layer-deposited Al2O3 as the gate dielectric

    Institute of Scientific and Technical Information of China (English)

    Feng Qian; Xing Tao; Wang Qiang; Feng Qing; Li Qian; Bi Zhi-Wei; Zhang Jin-Cheng; Hao Yue

    2012-01-01

    Accumulation-type GaN metal-oxide-semiconductor field-effect transistors (MOSFETs) with atomic-layerdeposited Al2O3 gate dielectrics are fabricated.The device,with atomic-layer-deposited Al2O3 as the gate dielectric,presents a drain current of 260 mA/mm and a broad maximum transconductance of 34 mS/mm,which are better than those reported previously with Al2O3 as the gate dielectric.Furthermore,the device shows negligible current collapse in a wide range of bias voltages,owing to the effective passivation of the GaN surface by the Al2O3 film.The gate drain breakdown voltage is found to be about 59.5 V,and in addition the channel mobility of the n-GaN layer is about 380 cm2/Vs,which is consistent with the Hall result,and it is not degraded by atomic-layer-deposition Al2Oa growth and device fabrication.

  13. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2015-01-01

    Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

  14. Low-voltage polymer thin-film transistors with high-k HfTiO gate dielectric annealed in NH3 or N2

    OpenAIRE

    Choi, HW; Lai, PT; Xu, JP; Deng, LF; Liu, YR

    2009-01-01

    OTFTs with P3HT as organic semiconductor and HfTiO as gate dielectric have been studied in this work. The HfTiO dielectric film was prepared by RF sputtering of Hf and DC sputtering of Ti at room temperature. Subsequently, the dielectric film was annealed in an NH3 or N2 ambient at 200 °C. Then a layer of OTS was deposited by spin-coating method to improve the surface characteristics of the gate dielectric. Afterwards, P3HT was deposited by spin-coating method. The OTFTs were characterized by...

  15. Improved performance of pentacene OTFTs with HfLaO gate dielectric by using fluorination and nitridation

    OpenAIRE

    Choi, HW; Che, CM; Lai, PT; Deng, LF; Liu, YR

    2012-01-01

    Pentacene organic thin-film transistors (OTFTs) with fluorinated high-κ HfLaO as gate insulator were fabricated. The dielectrics were prepared by sputtering method and then annealed in N 2 or NH 3 at 400 °C. Subsequently, the dielectrics were treated by fluorine plasma for different durations (100, 300, and 900 s). The N 2 and NH 3-annealed OTFTs with a 100-s plasma treatment achieve a carrier mobility of 0.62 and 0.66 cm 2V̇s, respectively, which are higher than those of the OTFTs without pl...

  16. ZnO-based thin film transistors employing aluminum titanate gate dielectrics deposited by spray pyrolysis at ambient air.

    Science.gov (United States)

    Afouxenidis, Dimitrios; Mazzocco, Riccardo; Vourlias, Georgios; Livesley, Peter J; Krier, Anthony; Milne, William I; Kolosov, Oleg; Adamopoulos, George

    2015-04-08

    The replacement of SiO2 gate dielectrics with metal oxides of higher dielectric constant has led to the investigation of a wide range of materials with superior properties compared with SiO2. Despite their attractive properties, these high-k dielectrics are usually manufactured using costly vacuum-based techniques. To overcome this bottleneck, research has focused on the development of alternative deposition methods based on solution-processable metal oxides. Here we report the application of spray pyrolysis for the deposition and investigation of Al2x-1·TixOy dielectrics as a function of the [Ti(4+)]/[Ti(4+)+2·Al(3+)] ratio and their implementation in thin film transistors (TFTs) employing spray-coated ZnO as the active semiconducting channels. The films are studied by UV-visible absorption spectroscopy, spectroscopic ellipsometry, impedance spectroscopy, atomic force microscopy, X-ray diffraction and field-effect measurements. Analyses reveal amorphous Al2x-1·TixOy dielectrics that exhibit a wide band gap (∼4.5 eV), low roughness (∼0.9 nm), high dielectric constant (k ∼ 13), Schottky pinning factor S of ∼0.44 and very low leakage currents (<5 nA/cm(2)). TFTs employing stoichiometric Al2O3·TiO2 gate dielectrics and ZnO semiconducting channels exhibit excellent electron transport characteristics with low operating voltages (∼10 V), negligible hysteresis, high on/off current modulation ratio of ∼10(6), subthreshold swing (SS) of ∼550 mV/dec and electron mobility of ∼10 cm(2) V(-1) s(-1).

  17. High carrier mobility of CoPc wires based field-effect transistors using bi-layer gate dielectric

    Directory of Open Access Journals (Sweden)

    Murali Gedda

    2013-11-01

    Full Text Available Polyvinyl alcohol (PVA and anodized Al2O3 layers were used as bi-layer gate for the fabrication of cobalt phthalocyanine (CoPc wire base field-effect transistors (OFETs. CoPc wires were grown on SiO2 surfaces by organic vapor phase deposition method. These devices exhibit a field-effect carrier mobility (μEF value of 1.11 cm2/Vs. The high carrier mobility for CoPc molecules is attributed to the better capacitive coupling between the channel of CoPc wires and the gate through organic-inorganic dielectric layer. Our measurements also demonstrated the way to determine the thicknesses of the dielectric layers for a better process condition of OFETs.

  18. Transparent field-effect transistors based on AlN-gate dielectric and IGZO-channel semiconductor

    Science.gov (United States)

    Besleaga, C.; Stan, G. E.; Pintilie, I.; Barquinha, P.; Fortunato, E.; Martins, R.

    2016-08-01

    The degradation of thin-film transistors (TFTs) caused by the self-heating effect constitutes a problem to be solved for the next generation of displays. Aluminum nitride (AlN) is a viable alternative for gate dielectric of TFTs due to its good thermal conductivity, matching coefficient of thermal expansion to indium-gallium-zinc-oxide, and excellent stability at high temperatures. Here, AlN thin films of different thicknesses were fabricated by a low temperature reactive radio-frequency magnetron sputtering process, using a low cost, metallic Al target. Their electrical properties have been thoroughly assessed. Furthermore, the 200 nm and 500 nm thick AlN layers have been integrated as gate-dielectric in transparent TFTs with indium-gallium-zinc-oxide as channel semiconductor. Our study emphasizes the potential of AlN thin films for transparent electronics, whilst the functionality of the fabricated field-effect transistors is explored and discussed.

  19. UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence

    Energy Technology Data Exchange (ETDEWEB)

    Erickson, Paul

    2012-05-31

    This is the final report of the UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence which spanned from 2005-2012. The U.S. Department of Energy (DOE) established the Graduate Automotive Technology Education (GATE) Program, to provide a new generation of engineers and scientists with knowledge and skills to create advanced automotive technologies. The UC Davis Fuel Cell, Hydrogen, and Hybrid Vehicle (FCH2V) GATE Center of Excellence established in 2005 is focused on research, education, industrial collaboration and outreach within automotive technology. UC Davis has had two independent GATE centers with separate well-defined objectives and research programs from 1998. The Fuel Cell Center, administered by ITS-Davis, has focused on fuel cell technology. The Hybrid-Electric Vehicle Design Center (HEV Center), administered by the Department of Mechanical and Aeronautical Engineering, has focused on the development of plug-in hybrid technology using internal combustion engines. The merger of these two centers in 2005 has broadened the scope of research and lead to higher visibility of the activity. UC Davis's existing GATE centers have become the campus's research focal points on fuel cells and hybrid-electric vehicles, and the home for graduate students who are studying advanced automotive technologies. The centers have been highly successful in attracting, training, and placing top-notch students into fuel cell and hybrid programs in both industry and government.

  20. A physics-based potential and electric field model of a nanoscale rectangular high-K gate dielectric HEMT

    Indian Academy of Sciences (India)

    Das B; Goswami R; Bhowmick B

    2016-04-01

    In this paper, we have developed a physics-based model for surface potential, channel potential, electric field and drain current for AlGaN/GaN high electron mobility transistor with high-K gate dielectric using two-dimensional Poisson equation under full depletion approximation with the inclusion of effect of polarization charges. The accuracy of the model has been verified and is found to be in good agreement with the simulated results.

  1. Scanning transmission electron microscopy of gate stacks with HfO2 dielectrics and TiN electrodes

    OpenAIRE

    Agustin, Melody P.; Fonseca, Leo R. C.; Hooker, Jacob C.; Stemmer, Susanne

    2005-01-01

    High-angle annular dark-field (HAADF) imaging and electron energy-loss spectroscopy (EELS) in scanning transmission electron microscopy were used to investigate HfO2 gate dielectrics grown by atomic layer deposition on Si substrates, and their interfaces with TiN electrodes and silicon, as a function of annealing temperature. Annealing at high temperatures (900 °C) caused significant roughening of both bottom (substrate) and top (electrode) interface. At the bottom interface, HAADF images s...

  2. Enhanced dielectric performance in polymer composite films with carbon nanotube-reduced graphene oxide hybrid filler.

    Science.gov (United States)

    Kim, Jin-Young; Kim, TaeYoung; Suk, Ji Won; Chou, Harry; Jang, Ji-Hoon; Lee, Jong Ho; Kholmanov, Iskandar N; Akinwande, Deji; Ruoff, Rodney S

    2014-08-27

    The electrical conductivity and the specific surface area of conductive fillers in conductor-insulator composite films can drastically improve the dielectric performance of those films through changing their polarization density by interfacial polarization. We have made a polymer composite film with a hybrid conductive filler material made of carbon nanotubes grown onto reduced graphene oxide platelets (rG-O/CNT). We report the effect of the rG-O/CNT hybrid filler on the dielectric performance of the composite film. The composite film had a dielectric constant of 32 with a dielectric loss of 0.051 at 0.062 wt% rG-O/CNT filler and 100 Hz, while the neat polymer film gave a dielectric constant of 15 with a dielectric loss of 0.036. This is attributed to the increased electrical conductivity and specific surface area of the rG-O/CNT hybrid filler, which results in an increase in interfacial polarization density between the hybrid filler and the polymer.

  3. Fabrication and characteristics of ZnO MOS capacitors with high-K HfO2 gate dielectrics

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    ZnO thin films are first deposited on n-type silicon by radio frequency (rf) magnetron sputtering at room temperature.And high-K HfO2 gate dielectrics thin films are deposited on ZnO films to form metal-oxide semiconductor (MOS) capacitors.The temperature to fabricate ZnO MOS capacitors is 400°C,and the low temperature process is applicable for thin film transistors,flat-panel display (FPD),flexible display,etc.The electronic availability of ZnO thin films,which serve as a semiconductor material for MOS capacitors with HfO2 gate dielectric is investigated.High frequency (1 MHz) capacitance-voltage (C-V) and current-voltage (I-V) characteristics of ZnO-based MOS capacitors are measured.The thermal stability and electronic stability of the ZnO capacitors are investigated,respectively.Experimental results indicate that good electrical characteristics can be obtained on ZnO substrates with high-K HfO2 gate dielectrics.Besides,the ZnO capacitors can exhibit high thermal and electronic stabilities.

  4. Effects of Annealing Time on the Performance of OTFT on Glass with ZrO2 as Gate Dielectric

    Directory of Open Access Journals (Sweden)

    W. M. Tang

    2012-01-01

    Full Text Available Copper phthalocyanine-based organic thin-film transistors (OTFTs with zirconium oxide (ZrO2 as gate dielectric have been fabricated on glass substrates. The gate dielectric is annealed in N2 at different durations (5, 15, 40, and 60 min to investigate the effects of annealing time on the electrical properties of the OTFTs. Experimental results show that the longer the annealing time for the OTFT, the better the performance. Among the devices studied, OTFTs with gate dielectric annealed at 350°C in N2 for 60 min exhibit the best device performance. They have a small threshold voltage of −0.58 V, a low subthreshold slope of 0.8 V/decade, and a low off-state current of 0.73 nA. These characteristics demonstrate that the fabricated device is suitable for low-voltage and low-power operations. When compared with the TFT samples annealed for 5 min, the ones annealed for 60 min have 20% higher mobility and nearly two times smaller the subthreshold slope and off-state current. The extended annealing can effectively reduce the defects in the high-k film and produces a better insulator/organic interface. This results in lower amount of carrier scattering and larger CuPc grains for carrier transport.

  5. Design of Higher-k and More Stable Rare Earth Oxides as Gate Dielectrics for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Yi Zhao

    2012-08-01

    Full Text Available High permittivity (k gate dielectric films are widely studied to substitute SiO2 as gate oxides to suppress the unacceptable gate leakage current when the traditional SiO2 gate oxide becomes ultrathin. For high-k gate oxides, several material properties are dominantly important. The first one, undoubtedly, is permittivity. It has been well studied by many groups in terms of how to obtain a higher permittivity for popular high-k oxides, like HfO2 and La2O3. The second one is crystallization behavior. Although it’s still under the debate whether an amorphous film is definitely better than ploy-crystallized oxide film as a gate oxide upon considering the crystal boundaries induced leakage current, the crystallization behavior should be well understood for a high-k gate oxide because it could also, to some degree, determine the permittivity of the high-k oxide. Finally, some high-k gate oxides, especially rare earth oxides (like La2O3, are not stable in air and very hygroscopic, forming hydroxide. This topic has been well investigated in over the years and significant progresses have been achieved. In this paper, I will intensively review the most recent progresses of the experimental and theoretical studies for preparing higher-k and more stable, in terms of hygroscopic tolerance and crystallization behavior, Hf- and La-based ternary high-k gate oxides.

  6. Electrical characteristics of MOS capacitor with HfTiON gate dielectric and HfTiSiON interlayer

    Institute of Scientific and Technical Information of China (English)

    Chen Wei-Bing; Xu Jing-Ping; Lai Pui-To; Li Yan-Ping; Xu Sheng-Guo; Chan Chu-Lok

    2006-01-01

    The paper reports that HfTiO dielectric is deposited by reactive co-sputtering of Hf and Ti targets in an Ar/O2 ambience, followed by an annealing in different gas ambiences of N2, NO and NHa at 600°C for 2 min. Capacitance-voltage and gate-leakage properties are characterized and compared. The results indicate that the NO-annealed sample exhibits the lowest interface-state and dielectric-charge densities and best device reliability. This is attributed to the fact that nitridation can create strong Si≡N bonds to passivate dangling Si bonds and replace strained Si- O bonds, thus the sample forms a hardened dielectric/Si interface with high reliability.

  7. Physically responsive field-effect transistors with giant electromechanical coupling induced by nanocomposite gate dielectrics.

    Science.gov (United States)

    Tien, Nguyen Thanh; Trung, Tran Quang; Seoul, Young Gug; Kim, Do Il; Lee, Nae-Eung

    2011-09-27

    Physically responsive field-effect transistors (physi-FETs) that are sensitive to physical stimuli have been studied for decades. The important issue for separating the responses of sensing materials from interference by other subcomponents in a FET transducer under global physical stimuli has not been completely resolved. In addition, challenges remain with regard to the design and employment of smart materials for flexible physi-FETs with a large electro-physical coupling effect. In this article, we propose the direct integration of nanocomposite (NC) gate dielectrics of barium titanate (BT) nanoparticles (NPs) and highly crystalline poly(vinylidene fluoride-trifluoroethylene) (P(VDF-TrFE)) into flexible organic FETs to achieve a large electro-physical coupling effect. Additionally, a new alternating current biasing method is proposed for precise extraction and quantification of tiny variations in the remnant polarization of NCs caused by mechanical stimuli. An investigation of physi-FETs under static mechanical stimuli revealed the first ever reported giant, positive piezoelectric coefficients of d(33) up to 960 pC/N in the NCs. The large coefficients are presumably due to the significant contributions of the intrinsic positive piezoelectricity of the BT NPs and P(VDF-TrFE) crystallites. © 2011 American Chemical Society

  8. Electrical dependence on the chemical composition of the gate dielectric in indium gallium zinc oxide thin-film transistors

    Energy Technology Data Exchange (ETDEWEB)

    Tari, Alireza, E-mail: atari@uwaterloo.ca; Lee, Czang-Ho; Wong, William S. [Department of Electrical and Computer Engineering, University of Waterloo, 200 University Avenue West, Waterloo, Ontario N2L 3G1 (Canada)

    2015-07-13

    Bottom-gate thin-film transistors were fabricated by depositing a 50 nm InGaZnO (IGZO) channel layer at 150 °C on three separate gate dielectric films: (1) thermal SiO{sub 2}, (2) plasma-enhanced chemical-vapor deposition (PECVD) SiN{sub x}, and (3) a PECVD SiO{sub x}/SiN{sub x} dual-dielectric. X-ray photoelectron and photoluminescence spectroscopy showed the V{sub o} concentration was dependent on the hydrogen concentration of the underlying dielectric film. IGZO films on SiN{sub x} (high V{sub o}) and SiO{sub 2} (low V{sub o}) had the highest and lowest conductivity, respectively. A PECVD SiO{sub x}/SiN{sub x} dual-dielectric layer was effective in suppressing hydrogen diffusion from the nitride layer into the IGZO and resulted in higher resistivity films.

  9. Decoherence-protected quantum gates for a hybrid solid-state spin register.

    Science.gov (United States)

    van der Sar, T; Wang, Z H; Blok, M S; Bernien, H; Taminiau, T H; Toyli, D M; Lidar, D A; Awschalom, D D; Hanson, R; Dobrovitski, V V

    2012-04-04

    Protecting the dynamics of coupled quantum systems from decoherence by the environment is a key challenge for solid-state quantum information processing. An idle quantum bit (qubit) can be efficiently insulated from the outside world by dynamical decoupling, as has recently been demonstrated for individual solid-state qubits. However, protecting qubit coherence during a multi-qubit gate is a non-trivial problem: in general, the decoupling disrupts the interqubit dynamics and hence conflicts with gate operation. This problem is particularly salient for hybrid systems, in which different types of qubit evolve and decohere at very different rates. Here we present the integration of dynamical decoupling into quantum gates for a standard hybrid system, the electron-nuclear spin register. Our design harnesses the internal resonance in the coupled-spin system to resolve the conflict between gate operation and decoupling. We experimentally demonstrate these gates using a two-qubit register in diamond operating at room temperature. Quantum tomography reveals that the qubits involved in the gate operation are protected as accurately as idle qubits. We also perform Grover's quantum search algorithm, and achieve fidelities of more than 90% even though the algorithm run-time exceeds the electron spin dephasing time by two orders of magnitude. Our results directly allow decoherence-protected interface gates between different types of solid-state qubit. Ultimately, quantum gates with integrated decoupling may reach the accuracy threshold for fault-tolerant quantum information processing with solid-state devices.

  10. AlGaN/GaN MISHEMTs with AlN gate dielectric grown by thermal ALD technique.

    Science.gov (United States)

    Liu, Xiao-Yong; Zhao, Sheng-Xun; Zhang, Lin-Qing; Huang, Hong-Fan; Shi, Jin-Shan; Zhang, Chun-Min; Lu, Hong-Liang; Wang, Peng-Fei; Zhang, David Wei

    2015-01-01

    Recently, AlN plasma-enhanced atomic layer deposition (ALD) passivation technique had been proposed and investigated for suppressing the dynamic on-resistance degradation behavior of high-electron-mobility transistors (HEMTs). In this paper, a novel gate dielectric and passivation technique for GaN-on-Si AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMTs) is presented. This technique features the AlN thin film grown by thermal ALD at 400°C without plasma enhancement. A 10.6-nm AlN thin film was grown upon the surface of the HEMT serving as the gate dielectric under the gate electrode and as the passivation layer in the access region at the same time. The MISHEMTs with thermal ALD AlN exhibit enhanced on/off ratio, reduced channel sheet resistance, reduction of gate leakage by three orders of magnitude at a bias of 4 V, reduced threshold voltage hysteresis of 60 mV, and suppressed current collapse degradation.

  11. Electrical properties and reliability of HfO2 gate-dielectric MOS capacitors with trichloroethylene surface pretreatment

    Institute of Scientific and Technical Information of China (English)

    Xu Jing-Ping; Chen Wei-Bing; Lai Pui-To; Li Yan-Ping; Chan Chu-Lok

    2007-01-01

    Trichloroethylene (TCE) pretreatment of Si surface prior to HfO2 deposition is employed to fabricate HfO2 gatedielectric MOS capacitors. Influence of this processing procedure on interlayer growth, HfO2/Si interface properties,gate-oxide leakage and device reliability is investigated. Among the surface pretreatments in NH3, NO, N2O and TCE ambients, the TCE pretreatment gives the least interlayer growth, the lowest interface-state density, the smallest gate leakage and the highest reliability. All these improvements should be ascribed to the passivation effects of Cl2 and Hclon the structural defects in the interlayer and at the interface, and also their gettering effects on the ion contamination in the gate dielectric.

  12. Low-loss and high-symmetry negative refractive index media by hybrid dielectric resonators.

    Science.gov (United States)

    Lai, Yueh-Chun; Chen, Cheng-Kuang; Yang, Yu-Hang; Yen, Ta-Jen

    2012-01-30

    Based on Maxwell's equations and Mie theory, strong sub-wavelength artificial magnetic and electric dipole resonances can be excited within dielectric resonators, and their resonant frequencies can be tailored simply by scaling the size of the dielectric resonators. Therefore, in this work we hybridize commercially available zirconia and alumina structures to harvest their individual artificial magnetic and electric response simultaneously, presenting a negative refractive index medium (NRIM). Comparing with the conventional NRIM constructed by metallic structures, the demonstrated all-dielectric NRIM possesses low-loss and high-symmetry advantages, thus benefiting practical applications in communication components, perfect lenses, invisible cloaking and other novel electromagnetic devices.

  13. Hybrid surface waves in semi-infinite metal-dielectric lattices

    CERN Document Server

    Miret, Juan J; Jaksic, Zoran; Vukovic, Slobodan; Belic, Milivoj R

    2012-01-01

    We investigate surface waves at the boundary between a semi-infinite layered metal-dielectric nanostructure cut normally to the layers and a semi-infinite dielectric. Spatial dispersion properties of such a nanostructure can be dramatically affected by coupling of surface plasmons polaritons at different metal-dielectric interfaces. As a consequence, the effective medium approach is not applicable in general. It is demonstrated that Dyakonov-like surface waves with hybrid polarization can propagate in an angular range substantially enlarged compared to conventional birefringent materials. Our numerical simulations for an Ag-GaAs stack in contact with glass show a low to moderate influence of losses.

  14. Hybrid quantum gates between flying photon and diamond nitrogen-vacancy centers assisted by optical microcavities

    Science.gov (United States)

    Wei, Hai-Rui; Lu Long, Gui

    2015-01-01

    Hybrid quantum gates hold great promise for quantum information processing since they preserve the advantages of different quantum systems. Here we present compact quantum circuits to deterministically implement controlled-NOT, Toffoli, and Fredkin gates between a flying photon qubit and diamond nitrogen-vacancy (NV) centers assisted by microcavities. The target qubits of these universal quantum gates are encoded on the spins of the electrons associated with the diamond NV centers and they have long coherence time for storing information, and the control qubit is encoded on the polarizations of the flying photon and can be easily manipulated. Our quantum circuits are compact, economic, and simple. Moreover, they do not require additional qubits. The complexity of our schemes for universal three-qubit gates is much reduced, compared to the synthesis with two-qubit entangling gates. These schemes have high fidelities and efficiencies, and they are feasible in experiment. PMID:26271899

  15. Effects of Elevated Source/Drain and Side Spacer Dielectric on the Drivability Optimization of Non-abrupt Ultra Shallow Junction Gate Underlap DG MOSFETs

    Science.gov (United States)

    Singh, Kunal; Kumar, Sanjay; Goel, Ekta; Singh, Balraj; Dubey, Sarvesh; Jit, Satyabrata

    2017-01-01

    The effects of drain/source elevation height ( h SD) and side spacer dielectric between the gate and source/drain regions on the drivability performance of the non-abrupt ultra-shallow-junction gate underlap double gate metal oxide field effect transistor of 18 nm gate length has been investigated in terms of the on-state ( I on), off-state ( I off) drain currents, and I on/ I off ratio. Among the Air, SiO2, Si3N4, and HfO2 used as spacer dielectrics, while both I on and I on/ I off are increased with the elevation height ( h SD) and permittivity of the spacer dielectric, interestingly, an inverse relation between the I on and I off for all h SD below ˜32.5 nm is observed only for the SiO2 spacer dielectric. Another new observation is the increase in I off with the h SD and permittivity of the spacer dielectric due to the enhancement of gate-induced drain leakage current owing to the increased vertical electric field at the drain side. For the most commonly used dielectrics SiO2 and HfO2 in the spacer region, the I on/ I off ratio is increased by ˜277% (at h SD = 32.5 nm) and ˜516% (at h SD = 9.5 nm) with respect to their corresponding values at zero elevation, respectively.

  16. Amorphous Strontium Titanate Film as Gate Dielectric for Higher Performance and Low Voltage Operation of Transparent and Flexible Organic Field Effect Transistor.

    Science.gov (United States)

    Yadav, Sarita; Ghosh, Subhasis

    2016-04-27

    We report that the pervoskite material, strontium titanate (STO) can be used as a gate dielectric layer of flexible and low voltage organic field effect transistor (OFET). The crystallinity, dielectric constant, and surface morphology of STO films can be controlled by the engineering of the growth condition. Under optimized growth condition, amorphous films of STO show a much better gate dielectric compared to other gate dielectrics used to date, with very small leakage current density for flexible and low voltage (transistors with amorphous STO gate dielectric show high mobility of 2 cm(2)/(V s), on/off ratio of 10(6), subthreshold swing of 0.3 V/dec and low interface trap density. Similarly excellent performance has been obtained in copper phthalocyanine (CuPc) based OFETs with on/off ratio ∼10(5) and carrier mobility ∼5.9 × 10(-2) cm(2)/(V s). Moreover, the operating voltage (∼5 V) has been reduced by more than one order of magnitude. It has been demonstrated that the low processing temperature of amorphous STO makes it the most suitable gate dielectric for flexible and transparent organic devices to operate under low voltage.

  17. New Gate Dielectric Oxides for GaAs and Other Semiconductors*

    Science.gov (United States)

    Hong, M.

    2000-03-01

    It is well known that electrons move much faster in GaAs than in Si, and this attribute makes the GaAs-based metal oxide semiconductor field effect transistors (MOSFETs) very attractive for high-frequency, high-speed circuits applications. However, identifying a proper insulating oxide for GaAs has been a problem puzzling researchers over 35 years. Recently we discovered that the use of a mixed oxide dielectric Ga_2O_3(Gd_2O_3)^1 formed inversion and accumulation channels on GaAs surfaces, with a low interfacial density of states (D_it) of mid-10^10 cm-2eV-1. Subsequently, we have demonstrated the p- and n- inversion channel MOSFETs^2 and CMOS circuits^3. All oxides in this work were prepared by ultrahigh vacuum deposition from e-beam sources. The initial growth ( 10 Åof Ga_2O_3(Gd_2O_3) film on GaAs takes place from nucleating a thin epitaxial layer of pure Gd_2O_3. In fact, mono-domain, single crystalline Gd_2O3 films (ɛ =12) can be grown on GaAs (100) surface in the (110) Mn_2O3 structure, and that show leakage currents as low as 10-4 A/cm^2 at 10 MV/cm for a film only 25 Åthick^4. We have extended our studies to other rare earth oxides and other semiconductors. For example, low-D_it GaN MOS diodes and GaN MOSFETs operated at 400^circC were obtained. The GaN MOSFET has potential applications in high power switching and high temperature device operation. More remarkably, we have found recently that another rare earth oxide, Y_2O3 (ɛ = 18) showed excellent electrical properties as a gate dielectric for Si, to replace the current SiO_2, where the thickness is now approaching the quantum limit^5. *In collaboration with J. Kwo, A. R. Kortan, J. N. Baillargeon, J. P. Mannaerts, F. Ren, Y. C. Wang, T. S. Lay, H. Ng, R. Opila, K. L. Queeney, Y. J. Chabal, T. Boone, J. J. Krajewski, A. M. Sergent, J. M. Rosamilia, M. Passlack, D. W. Murphy, and A. Y. Cho. 1. M. Hong, et al, J. Vac. Sci. Technol. B14, 2297, (1996). 2. F. Ren et al, IEDM Technical Digest, p.943, (1996

  18. Reduced Subthreshold Characteristics and Flicker Noise of an AlGaAs/InGaAs PHEMT Using Liquid Phase Deposited TiO2 as a Gate Dielectric

    Directory of Open Access Journals (Sweden)

    Kai-Yuen Lam

    2016-10-01

    Full Text Available This study presents the fabrication and improved properties of an AlGaAs/InGaAs metal-oxide-semiconductor pseudomorphic high-electron-mobility transistor (MOS-PHEMT using liquid phase deposited titanium dioxide (LPD-TiO2 as a gate dielectric. Sulfur pretreatment and postoxidation rapid thermal annealing (RTA were consecutively employed before and after the gate dielectric was deposited to fill dangling bonds and therefore release interface trapped charges. Compared with a benchmark PHEMT, the AlGaAs/InGaAs MOS-PHEMT using LPD-TiO2 exhibited larger gate bias operation, higher breakdown voltage, suppressed subthreshold characteristics, and reduced flicker noise. As a result, the device with proposed process and using LPD-TiO2 as a gate dielectric is promising for high-speed applications that demand little noise at low frequencies.

  19. Onset of Bonding Plasmon Hybridization Preceded by Gap Modes in Dielectric Splitting of Metal Disks

    DEFF Research Database (Denmark)

    Frederiksen, Maj; Bochenkov, Vladimir; Ogaki, Ryosuke;

    2013-01-01

    Dielectric splitting of nanoscale disks was studied experimentally and via finite-difference time-domain (FDTD) simulations through systematic introduction of multiple ultrathin dielectric layers. Tunable, hybridized dark bonding modes were seen with first-order gap modes preceding the appearance...... of bonding dipole−dipole disk modes. The observed bright dipolar mode did not show the energy shift expected from plasmon hybridization but activated dark higher order gap modes. Introducing lateral asymmetry was shown to remodel the field distribution resulting in 3D asymmetry that reoriented the dipole...

  20. Hybrid metal-dielectric nanostructures for advanced light-field manipulation (Conference Presentation)

    Science.gov (United States)

    Staude, Isabelle; Guo, Rui; Rusak, Evgenia; Dominguez, Jason; Decker, Manuel; Rockstuhl, Carsten; Brener, Igal; Neshev, Dragomir N.; Pertsch, Thomas; Kivshar, Yuri S.

    2017-02-01

    All-dielectric and plasmonic nanostructures have complementary advantages regarding their capabilities for controlling light fields at the nanoscale [1]. While all-dielectric nanostructures can provide near-unity efficiency, plasmonic nanostructures are more compact and offer strong near-field enhancement. Combination of photonic nanostructures of both types offers a promising route towards compact optical elements that unify low absorption losses with small footprints, while at the same time providing a high versatility in engineering the optical response of the hybrid system towards specific functionalities. This talk aims to review our recent progress in coupling designed plasmonic nanoantennas to high-index dielectric nanostructures. Following a general analysis of coupling of plasmonic and high-refractive-index dielectric nanoresonators, various specific hybrid nanostructure designs will be discussed. For the fabrication of designed hybrid metal-dielectric nanostructures we use a two-step electron-beam lithography (EBL) procedure [2]. The first step of EBL is used in combination with reactive-ion etching to define the dielectric nanostructures. The second step of EBL is followed by evaporation of gold and a lift-off process, and serves to define the plasmonic elements. Between the two steps, a precision alignment procedure is performed in order to allow for the precise positioning of the gold nanostructures with respect to the silicon nanostructures. Using this approach, we realize and optically characterize various hybrid metal-dielectric nanostructures designed to support a range of novel functionalities, including directional emission enhancement [2] and on-chip light routing. [1] E. Rusak et al., Appl. Phys. Lett. 105, 221109 (2014). [2] R. Guo et al., ACS Photonics 3, 349-353 (2016).

  1. Novel negative tone photodefinable low dielectric constant hybrid films

    Science.gov (United States)

    Markley, Thomas J.; Weigel, Scott J.; Kretz, Chris P.

    2005-05-01

    Multifunctional films have the potential to reduce the number of processing steps to prepare various complex electronic devices and thereby reduce the cost of manufacturing the device and increase the throughput of the process. By combining low dielectric thin film and photoresist technologies into one material, such an advantage could be provided to electronics device markets. Air Products and Chemicals has discovered negative tone photodefinable films having dielectric constant values less than 3.0 that are developable in water and/or aqueous TMAH solutions. The low dielectric films produced via a novel reaction pathway involving the use of photoacid generators (PAGs) provides a versatile link to various feature sizes depending on the choice of radiation source and PAG used. Specific examples of film properties and processing latitude will be presented for these developmental materials.

  2. Impactful study of dual work function, underlap and hetero gate dielectric on TFET with different drain doping profile for high frequency performance estimation and optimization

    Science.gov (United States)

    Yadav, Dharmendra Singh; Sharma, Dheeraj; Raad, Bhagwan Ram; Bajaj, Varun

    2016-08-01

    This manuscript presents a comparative study of different combination for the dual workfunction gate material, underlap and hetero gate dielectric tunnel field-effect transistors (TFET's). Their performances have been analyzed in terms of ON-state current, ambipolar behaviour and RF response along with different drain doping profile. For this, the Dual work function of gate provides enhancement in ON-state current by reducing the tunnel barrier width at source/channel interface. Whereas, the underlap of gate is done near to the drain region, helps in reduction of ambipolar conduction by creating deficiency of hole for the conduction, which is major hurdle for TFET. Further, the combinations of the dual workfunction and underlap give combine advantages of both such as improve ON-state current and suppressed ambipolar current. Apart from this, the combination of hetero gate dielectric dual workfunction under lapping leads to superior device performance in terms of ON-state current and ambipolar behaviour. The use of hetero gate dielectric and Gaussian doping profile with gate underlap reduces the gate to drain capacitance that also improves the RF parameters of the device.

  3. Tri-gate InGaAs-OI junctionless FETs with PE-ALD Al2O3 gate dielectric and H2/Ar anneal

    Science.gov (United States)

    Djara, Vladimir; Czornomaz, Lukas; Deshpande, Veeresh; Daix, Nicolas; Uccelli, Emanuele; Caimi, Daniele; Sousa, Marilyne; Fompeyrine, Jean

    2016-01-01

    We present a tri-gate In0.53Ga0.47As-on-insulator (InGaAs-OI) junctionless field-effect transistor (JLFET) architecture. The fabricated devices feature a 20-nm-thick n-In0.53Ga0.47As channel doped to 1018/cm3 obtained by metal organic chemical vapor phase deposition and direct wafer bonding along with a 3.5-nm-thick Al2O3 gate dielectric deposited by plasma-enhanced atomic layer deposition (PE-ALD). The PE-ALD Al2O3 presents a bandgap of 7.0 eV, a k-value of 8.1 and a breakdown field of 8-10.5 MV/cm. A post-fabrication H2/Ar anneal applied to the PE-ALD Al2O3/In0.53Ga0.47As-OI gate stack yielded a low density of interface traps (Dit) of 7 × 1011/cm2 eV at Ec - E = -0.1 eV along with lower border trap density values than recently reported PE-ALD bi-layer Al2O3/HfO2 and thermal ALD HfO2 gate stacks deposited on In0.53Ga0.47As. The H2/Ar anneal also improved the subthreshold performance of the tri-gate InGaAs-OI JLFETs. After H2/Ar anneal, the long-channel (10 μm) device featured a threshold voltage (VT) of 0.25 V, a subthreshold swing (SS) of 88 mV/dec and a drain-induced barrier lowering (DIBL) of 65 mV/V, while the short-channel (160 nm) device exhibited a VT of 0.1 V, a SS of 127 mV/dec and a DIBL of 218 mV/V. Overall, the tri-gate InGaAs-OI JLFETs showed the best compromise in terms of VT, SS and DIBL compared to the other III-V JLFET architectures reported to date. However, a 15× increase in access resistance was observed after H2/Ar anneal, significantly degrading the maximum drain current of the tri-gate InGaAs-OI JLFETs.

  4. The Post—deposition Anneal Effects on the Electrical Properties of HfO2 Gate Dielectric Deposited by Ion Beam Sputtering at Room Temperature

    Institute of Scientific and Technical Information of China (English)

    KANGJinfeng; LIUXiaoyan; TIANDayu; WANGWei; LIANGuijun; XIONGGuangcheng; HANRuqi

    2003-01-01

    HfO2 high K gate dielectric films were fab-ricated on p-Si(100) substrates by ion beam sputtering at room temperature followed by a post-deposition anneal-ing (PDA). The PDA effects on the electrical properties of HfO2 gate dielectric films were studied. High quality HfO2 gate dielectric with small equivalent oxide thickness (EOT = 2.3nm), small hystereis (△VFB<50mV), and lowleakage current (< 1× 10-4A/cm2@lV) was fabricated.The studies of PDA effects on the electrical properties in-dicate that the PDA process in nitrogen ambient will be necessary for the HfO2 gate dielectric films deposited by ion beam sputtering the sintered target at room temper-ature in order to obtain small equivalent oxide thickness and low leakage currents, whereas a PDA in oxygen ambi-ent will be not required. The results also means that there is less oxygen vacancy defect produced in the HfO2 gate dielectric films during the deposition at room temperature.

  5. Compact quantum gates for hybrid photon-atom systems assisted by Faraday rotation

    Science.gov (United States)

    Song, Guo-Zhu; Yang, Guo-Jian; Zhang, Mei

    2017-02-01

    We present some compact circuits for a deterministic quantum computing on the hybrid photon-atom systems, including the Fredkin gate and SWAP gate. These gates are constructed by exploiting the optical Faraday rotation induced by an atom trapped in a single-sided optical microcavity. The control qubit of our gates is encoded on the polarization states of the single photon, and the target qubit is encoded on the ground states of an atom confined in an optical microcavity. Since the decoherence of the flying qubit with atmosphere for a long distance is negligible and the stationary qubits are trapped inside single-sided microcavities, our gates are robust. Moreover, ancillary single photon is not needed and only some linear-optical devices are adopted, which makes our protocols efficient and practical. Our schemes need not meet the condition that the transmission for the uncoupled cavity is balanceable with the reflectance for the coupled cavity, which is different from the quantum computation with a double-sided optical microcavity. Our calculations show that the fidelities of the two hybrid quantum gates are high with the available experimental technology.

  6. Comparative study of CNT, silicon nanowire and fullerene embedded multilayer high-k gate dielectric MOS memory devices

    Energy Technology Data Exchange (ETDEWEB)

    Sengupta, Amretashis; Sarkar, Chandan Kumar [Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata-700 032 (India); Requejo, Felix G, E-mail: amretashis@gmail.com [INIFTA, Departmento de Quimica and Departmento de Fisica, Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC/67-1900, La Plata (Argentina)

    2011-10-12

    Here, we present a comparative theoretical study on stacked (multilayer) gate dielectric MOS memory devices, having a metallic/semiconducting carbon nanotube (CNT), silicon nanowire (Si NW) and fullerene (C60) embedded nitride layer acting as a floating gate. Two types of devices, one with HfO{sub 2}-SiO{sub 2} stack (stack-1) and the other with La{sub 2}O{sub 3}-SiO{sub 2} stack (stack-2) as the tunnel oxide were compared. We evaluated the effective barrier height, the dielectric constant and the effective electron mobility in the composite gate dielectric with the Maxwell-Garnett effective medium theory. Thereafter applying the WKB approximation, we simulated the Fowler-Nordheim (F-N) tunnelling/writing current and the direct tunnelling/leakage current in these devices. We evaluated the I-V characteristics, the charge decay and also the impact of CNT/Si NW aspect ratio and the volume fraction on the effective barrier height and the write voltage, respectively. We also simulated the write time, retention time and the erase time of these MOS devices. Based on the simulation results, it was concluded that the metallic CNT embedded stack-1 device offered the best performance in terms of higher F-N tunnelling current, lower direct tunnelling current and lesser write voltage and write time compared with the other devices. In case of direct tunnelling leakage and retention time it was found that the met CNT embedded stack-2 device showed better characteristics. For erasing, however, the C60 embedded stack-1 device showed the smallest erase time. When compared with earlier reports, it was seen that CNT, C60 and Si NW embedded devices all performed better than nanocrystalline Si embedded MOS non-volatile memories.

  7. Solution-based formation of high-quality gate dielectrics on epitaxial graphene by microwave-assisted annealing

    Science.gov (United States)

    Kim, Kwan-Soo; Park, Goon-Ho; Fukidome, Hirokazu; Suemitsu, Tetsuya; Otsuji, Taiichi; Cho, Won-Ju; Suemitsu, Maki

    2017-06-01

    We propose a damage-free formation method for high-quality gate dielectrics on epitaxial graphene (EG), which involves solution-based Al2O3 coating combined with microwave-assisted annealing (MW-sol-Al2O3). This method substantially preserves the pristine properties of EG with minimized hole doping and strain induction. The MW-sol-Al2O3 showed a surface roughness of ˜0.237 nm and a dielectric constant of 7.5. A leakage current of 8.7 × 10-6 A/cm2, which is 3 orders of magnitude smaller than that of natural Al2O3 at the same electric field, was obtained. These excellent MW-sol-Al2O3 properties are ascribed to the effective elimination of hydroxyl- and carboxyl-related components from the film by microwave-assisted annealing.

  8. Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    YU Ai-Fang; QI Qiong; JIANG Peng; JIANG Chao

    2009-01-01

    Carrier mobifity enhancement from 0.09 to 0.59cm2/Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO2 surface is believed to be the origin of the excellent carrier mobifity of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski-Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility.

  9. Structural and Electrical Characterization of SiO2 Gate Dielectrics Deposited from Solutions at Moderate Temperatures in Air.

    Science.gov (United States)

    Esro, Mazran; Kolosov, Oleg; Jones, Peter J; Milne, William I; Adamopoulos, George

    2017-01-11

    Silicon dioxide (SiO2) is the most widely used dielectric for electronic applications. It is usually produced by thermal oxidation of silicon or by using a wide range of vacuum-based techniques. By default, the growth of SiO2 by thermal oxidation of silicon requires the use of Si substrates whereas the other deposition techniques either produce low quality or poor interface material and mostly require high deposition or annealing temperatures. Recent investigations therefore have focused on the development of alternative deposition paradigms based on solutions. Here, we report the deposition of SiO2 thin film dielectrics deposited by spray pyrolysis in air at moderate temperatures of ≈350 °C from pentane-2,4-dione solutions of SiCl4. SiO2 dielectrics were investigated by means of UV-vis absorption spectroscopy, spectroscopic ellipsometry, XPS, XRD, UFM/AFM, admittance spectroscopy, and field-effect measurements. Data analysis reveals smooth (RRMS spray-coated SiO2 gate dielectrics and C60 and pentacene semiconducting channels exhibit excellent transport characteristics, i.e., negligible hysteresis, low leakage currents, high on/off current modulation ratio on the order of 10(6), and high carrier mobility.

  10. Hybrid Electric Power Train and Control Strategies Automotive Technology Education (GATE) Program

    Energy Technology Data Exchange (ETDEWEB)

    Andrew Frank

    2006-05-31

    Plug-in hybrid electric vehicles (PHEV) offer societal benefits through their ability to displace the use of petroleum fuels. Petroleum fuels represent a polluting and politically destabilizing energy carrier. PHEV technologies can move transportation away from petroleum fuel sources by enabling domestically generated electricity and liquids bio-fuels to serve as a carrier for transportation energy. Additionally, the All-Electric-Range (AER) offered by PHEVs can significantly reduce demand for expensive and polluting liquid fuels. The GATE funding received during the 1998 through 2004 funding cycle by the UC Davis Hybrid Electric Vehicle Center (HEVC) was used to advance and train researchers in PHEV technologies. GATE funding was used to construct a rigorous PHEV curriculum, provide financial support for HEVC researchers, and provide material support for research efforts. A rigorous curriculum was developed through the UC Davis Mechanical and Aeronautical Engineering Department to train HEVC researchers. Students' research benefited from this course work by advancing the graduate student researchers' understanding of key PHEV design considerations. GATE support assisted HEVC researchers in authoring technical articles and producing patents. By supporting HEVC researchers multiple Master's theses were written as well as journal articles and publications. The topics from these publications include Continuously Variable Transmission control strategies and PHEV cross platform controls software development. The GATE funding has been well used to advance PHEV systems. The UC Davis Hybrid Electric Vehicle Center is greatly appreciative for the opportunities GATE funding provided. The goals and objectives for the HEVC GATE funding were to nourish engineering research in PHEV technologies. The funding supplied equipment needed to allow researchers to investigate PHEV design sensitivities and to further optimize system components. Over a dozen PHEV

  11. Design of Pass Band Filter in Hybrid Architecture Planar/Non-Radiative Dielectric Waveguide Integration Technology

    Directory of Open Access Journals (Sweden)

    Harizi Hanen

    2012-01-01

    Full Text Available Problem statement: The expansion of RF, microwave and millimeter devices has revolutionized today’s ommunication and sensor systems. Low-cost, high-performance and mass producible millimeter wave technologies are vital for commercial broadband systems. Challenging issues are commonly faced in the design of low-loss integrated circuits for example high-Q band pass filter, which the planar technique is fundamentally limited in performance. Approach: In this study, we present a design of a nonradiative dielectric waveguide band pass filter based on hybrid architecture of micro strip line and non-radiative dielectric waveguide. Results: The simulation with High Frequency Structure Simulator (HFSS three dimensional analyses is presented. Conclusion: The non radiative dielectric resolves most of the drawbacks of dielectric waveguide in connection with the radiation loss."

  12. One-Dimensional Dielectric/Metallic Hybrid Materials for Photonic Applications.

    Science.gov (United States)

    Li, Yong Jun; Xiong, Xiao; Zou, Chang-Ling; Ren, Xi Feng; Zhao, Yong Sheng

    2015-08-01

    Explorations of 1D nanostructures have led to great progress in the area of nanophotonics in the past decades. Based on either dielectric or metallic materials, a variety of 1D photonic devices have been developed, such as nanolasers, waveguides, optical switches, and routers. What's interesting is that these dielectric systems enjoy low propagation losses and usually possess active optical performance, but they have a diffraction-limited field confinement. Alternatively, metallic systems can guide light on deep subwavelength scales, but they suffer from high metallic absorption and can work as passive devices only. Thus, the idea to construct a hybrid system that combines the merits of both dielectric and metallic materials was proposed. To date, unprecedented optical properties have been achieved in various 1D hybrid systems, which manifest great potential for functional nanophotonic devices. Here, the focus is on recent advances in 1D dielectric/metallic hybrid systems, with a special emphasis on novel structure design, rational fabrication techniques, unique performance, as well as their wide application in photonic components. Gaining a better understanding of hybrid systems would benefit the design of nanophotonic components aimed at optical information processing.

  13. Impact of Gate Dielectric in Carrier Mobility in Low Temperature Chalcogenide Thin Film Transistors for Flexible Electronics

    KAUST Repository

    Salas-Villasenor, A. L.

    2010-06-29

    Cadmium sulfide thin film transistors were demonstrated as the n-type device for use in flexible electronics. CdS thin films were deposited by chemical bath deposition (70° C) on either 100 nm HfO2 or SiO2 as the gate dielectrics. Common gate transistors with channel lengths of 40-100 μm were fabricated with source and drain aluminum top contacts defined using a shadow mask process. No thermal annealing was performed throughout the device process. X-ray diffraction results clearly show the hexagonal crystalline phase of CdS. The electrical performance of HfO 2 /CdS -based thin film transistors shows a field effect mobility and threshold voltage of 25 cm2 V-1 s-1 and 2 V, respectively. Improvement in carrier mobility is associated with better nucleation and growth of CdS films deposited on HfO2. © 2010 The Electrochemical Society.

  14. Hafnium silicate and hafnium silicon oxynitride gate dielectrics for strained Si_xGe_1-x: Interface stability

    Science.gov (United States)

    Addepalli, Swarna; Sivasubramani, Prasanna; El-Bouanani, Mohamed; Kim, Moon; Gnade, Bruce; Wallace, Robert

    2003-03-01

    Strained Si_xGe_1-x layers have gained considerable attention due to hole mobility enhancement, and ease of integration with Si-based CMOS technology. The deposition of stable high-κ dielectrics [1] such as hafnium silicate and hafnium silicon oxynitride in direct contact with SiGe would simultaneously improve the capacitance of the gate stack and lower the leakage current for high performance SiGe devices. However, the oxidation of the Si_xGe_1-x substrate either during dielectric deposition or post-deposition processing would degrade device performance due to the thermodynamic instability of germanium oxide [2,3]. Results from XPS, HR-TEM, and C-V, and I-V analyses after various annealing treatments will be presented for hafnium silicate and hafnium silicon oxynitride films deposited on strained Si_xGe_1-x(100), and correlated with dielectric-Si_xGe_1-x(100) interface stability. Implications to the introduction of these oxides as viable gate dielectric candidates for SiGe-based CMOS technology will be discussed. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program. References: [1] G. D. Wilk, R. M. Wallace and J. M. Anthony, Journal of Applied Physics, 89, 5243 (2001) [2] W. S. Liu, J .S. Chen, M.-A. Nicolet, V. Arbet-Engels, K. L. Wang, Journal of Applied Physics, 72, 4444 (1992), and, Applied Physics Letters, 62, 3321 (1993) [3] W. S. Liu, M. -A. Nicolet, H. -H. Park, B. -H. Koak, J. -W. Lee, Journal of Applied Physics, 78, 2631 (1995)

  15. A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

    Directory of Open Access Journals (Sweden)

    D.Nirmal

    2014-07-01

    Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

  16. Linear and Nonlinear Rheology Combined with Dielectric Spectroscopy of Hybrid Polymer Nanocomposites for Semiconductive Applications

    Science.gov (United States)

    Kádár, Roland; Abbasi, Mahdi; Figuli, Roxana; Rigdahl, Mikael; Wilhelm, Manfred

    2017-01-01

    The linear and nonlinear oscillatory shear, extensional and combined rheology-dielectric spectroscopy of hybrid polymer nanocomposites for semiconductive applications were investigated in this study. The main focus was the influence of processing conditions on percolated poly(ethylene-butyl acrylate) (EBA) nanocomposite hybrids containing graphite nanoplatelets (GnP) and carbon black (CB). The rheological response of the samples was interpreted in terms of dispersion properties, filler distortion from processing, filler percolation, as well as the filler orientation and distribution dynamics inside the matrix. Evidence of the influence of dispersion properties was found in linear viscoelastic dynamic frequency sweeps, while the percolation of the nanocomposites was detected in nonlinearities developed in dynamic strain sweeps. Using extensional rheology, hybrid samples with better dispersion properties lead to a more pronounced strain hardening behavior, while samples with a higher volume percentage of fillers caused a drastic reduction in strain hardening. The rheo-dielectric time-dependent response showed that in the case of nanocomposites containing only GnP, the orientation dynamics leads to non-conductive samples. However, in the case of hybrids, the orientation of the GnP could be offset by the dispersing of the CB to bridge the nanoplatelets. The results were interpreted in the framework of a dual PE-BA model, where the fillers would be concentrated mainly in the BA regions. Furthermore, better dispersed hybrids obtained using mixing screws at the expense of filler distortion via extrusion processing history were emphasized through the rheo-dielectric tests. PMID:28336857

  17. Linear and Nonlinear Rheology Combined with Dielectric Spectroscopy of Hybrid Polymer Nanocomposites for Semiconductive Applications.

    Science.gov (United States)

    Kádár, Roland; Abbasi, Mahdi; Figuli, Roxana; Rigdahl, Mikael; Wilhelm, Manfred

    2017-01-24

    The linear and nonlinear oscillatory shear, extensional and combined rheology-dielectric spectroscopy of hybrid polymer nanocomposites for semiconductive applications were investigated in this study. The main focus was the influence of processing conditions on percolated poly(ethylene-butyl acrylate) (EBA) nanocomposite hybrids containing graphite nanoplatelets (GnP) and carbon black (CB). The rheological response of the samples was interpreted in terms of dispersion properties, filler distortion from processing, filler percolation, as well as the filler orientation and distribution dynamics inside the matrix. Evidence of the influence of dispersion properties was found in linear viscoelastic dynamic frequency sweeps, while the percolation of the nanocomposites was detected in nonlinearities developed in dynamic strain sweeps. Using extensional rheology, hybrid samples with better dispersion properties lead to a more pronounced strain hardening behavior, while samples with a higher volume percentage of fillers caused a drastic reduction in strain hardening. The rheo-dielectric time-dependent response showed that in the case of nanocomposites containing only GnP, the orientation dynamics leads to non-conductive samples. However, in the case of hybrids, the orientation of the GnP could be offset by the dispersing of the CB to bridge the nanoplatelets. The results were interpreted in the framework of a dual PE-BA model, where the fillers would be concentrated mainly in the BA regions. Furthermore, better dispersed hybrids obtained using mixing screws at the expense of filler distortion via extrusion processing history were emphasized through the rheo-dielectric tests.

  18. Enhancement mode AlGaN/GaN MOS high-electron-mobility transistors with ZrO2 gate dielectric deposited by atomic layer deposition

    Science.gov (United States)

    Anderson, Travis J.; Wheeler, Virginia D.; Shahin, David I.; Tadjer, Marko J.; Koehler, Andrew D.; Hobart, Karl D.; Christou, Aris; Kub, Francis J.; Eddy, Charles R., Jr.

    2016-07-01

    Advanced applications of AlGaN/GaN high-electron-mobility transistors (HEMTs) in high-power RF and power switching are driving the need for insulated gate technology. We present a metal-oxide-semiconductor (MOS) gate structure using atomic-layer-deposited ZrO2 as a high-k, high-breakdown gate dielectric for reduced gate leakage and a recessed barrier structure for enhancement mode operation. Compared to a Schottky metal-gate HEMT, the recessed MOS-HEMT structure demonstrated a reduction in the gate leakage current by 4 orders of magnitude and a threshold voltage shift of +6 V to a record +3.99 V, enabled by a combination of a recessed barrier structure and negative oxide charge.

  19. Solution-deposited sodium beta-alumina gate dielectrics for low-voltage and transparent field-effect transistors.

    Science.gov (United States)

    Pal, Bhola N; Dhar, Bal Mukund; See, Kevin C; Katz, Howard E

    2009-11-01

    Sodium beta-alumina (SBA) has high two-dimensional conductivity, owing to mobile sodium ions in lattice planes, between which are insulating AlO(x) layers. SBA can provide high capacitance perpendicular to the planes, while causing negligible leakage current owing to the lack of electron carriers and limited mobility of sodium ions through the aluminium oxide layers. Here, we describe sol-gel-beta-alumina films as transistor gate dielectrics with solution-deposited zinc-oxide-based semiconductors and indium tin oxide (ITO) gate electrodes. The transistors operate in air with a few volts input. The highest electron mobility, 28.0 cm2 V(-1) s(-1), was from zinc tin oxide (ZTO), with an on/off ratio of 2 x 10(4). ZTO over a lower-temperature, amorphous dielectric, had a mobility of 10 cm2 V(-1) s(-1). We also used silicon wafer and flexible polyimide-aluminium foil substrates for solution-processed n-type oxide and organic transistors. Using poly(3,4-ethylenedioxythiophene) poly(styrenesulphonate) conducting polymer electrodes, we prepared an all-solution-processed, low-voltage transparent oxide transistor on an ITO glass substrate.

  20. Deposition-power-modulated optical and electrical properties of sputtering-derived HfTiO{sub x} gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Jin, P. [School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei, 230601 (China); He, G., E-mail: cheriling16@126.com [School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei, 230601 (China); Liu, M. [Key Laboratory of Materials Physics, Anhui Key Laboratory of Nanomaterials and, Nanostructure, Institute of Solid State Physics, Chinese Academy of Sciences, Hefei, 230031 (China); Xiao, D.Q.; Gao, J.; Chen, X.F. [School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei, 230601 (China); Ma, R. [Key Laboratory of Materials Physics, Anhui Key Laboratory of Nanomaterials and, Nanostructure, Institute of Solid State Physics, Chinese Academy of Sciences, Hefei, 230031 (China); Zhang, J.W.; Zhang, M.; Sun, Z.Q.; Liu, Y.M. [School of Physics and Materials Science, Radiation Detection Materials & Devices Lab, Anhui University, Hefei, 230601 (China)

    2015-11-15

    High-k gate dielectric HfTiO{sub x} thin films have been deposited on Si and quartz substrate by radio frequency (RF) magnetron sputtering. The structural and optical properties of HfTiO{sub x} thin films related to deposition power are investigated by X-ray diffraction (XRD), ultraviolet–visible spectroscopy (UV–Vis), and spectroscopic ellipsometry (SE). Results indicate that the as-deposited HfTiO{sub x} thin films are amorphous state regardless of the deposition power. The increase of band gap of the samples is observed with the increase of deposition power. Moreover, the increase of the thickness, deposition rate, refractive index (n) and the decrease of the extinction coefficient with the increase of deposition power are also confirmed. Additionally, the electrical properties of films are analyzed by measurement of high frequency capacitance–voltage (C–V) and leakage current density-voltage (J-V) characteristics. And the leakage current conduction mechanisms are also discussed. - Highlights: • Sputtering-derived HfTiO{sub x} gate dielectrics have been deposited on Si substrates. • Increase of band gap is observed with the increase of deposition power. • HfTiO{sub x} thin film deposited at 50 W displays excellent performance. • The leakage current conduction mechanisms are also discussed in detail.

  1. Universal quantum gates for photon-atom hybrid systems assisted by bad cavities.

    Science.gov (United States)

    Wang, Guan-Yu; Liu, Qian; Wei, Hai-Rui; Li, Tao; Ai, Qing; Deng, Fu-Guo

    2016-01-01

    We present two deterministic schemes for constructing a CNOT gate and a Toffoli gate on photon-atom and photon-atom-atom hybrid quantum systems assisted by bad cavities, respectively. They are achieved by cavity-assisted photon scattering and work in the intermediate coupling region with bad cavities, which relaxes the difficulty of their implementation in experiment. Also, bad cavities are feasible for fast quantum operations and reading out information. Compared with previous works, our schemes do not need any auxiliary qubits and measurements. Moreover, the schematic setups for these gates are simple, especially that for our Toffoli gate as only a quarter wave packet is used to interact the photon with each of the atoms every time. These atom-cavity systems can be used as the quantum nodes in long-distance quantum communication as their relatively long coherence time is suitable for multi-time operations between the photon and the system. Our calculations show that the average fidelities and efficiencies of our two universal hybrid quantum gates are high with current experimental technology.

  2. Experimental and theoretical investigation of the effect of SiO2 content in gate dielectrics on work function shift induced by nanoscale capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-09-10

    The impact of SiO2 content in ultrathin gate dielectrics on the magnitude of the effective work function (EWF) shift induced by nanoscale capping layers has been investigated experimentally and theoretically. The magnitude of the effective work function shift for four different capping layers (AlN, Al2O3, La2O3, and Gd2O3) is measured as a function of SiO2 content in the gate dielectric. A nearly linear increase of this shift with SiO2 content is observed for all capping layers. The origin of this dependence is explained using density functional theory simulations.

  3. Low-operating-voltage polymer thin-film transistors based on poly(3-hexylthiophene) with hafnium oxide as the gate dielectric

    OpenAIRE

    Liu, YR; Deng, LF; Yao, RH; Lai, PT

    2010-01-01

    The effects of hafnium oxide $(hbox{HfO}-{2})$ gate dielectric annealing treatment in oxygen $(hbox{O}-{2})$ and ammonia $(hbox{NH}-{3})$ ambient on the electrical performance of polymer thin-film transistors (PTFTs) based on poly(3-hexylthiophene) are investigated. The PTFTs with $hbox{HfO}-{2}$ gate dielectric and also octadecyltrichlorosilane surface modification, prepared by spin-coating process, exhibit good performance, such as a small threshold voltage of $-$0.5 V and an operating volt...

  4. Hybrid Monte Carlo and continuum modeling of electrolytes with concentration-induced dielectric variations

    Science.gov (United States)

    Guan, Xiaofei; Ma, Manman; Gan, Zecheng; Xu, Zhenli; Li, Bo

    2016-11-01

    The distribution of ions near a charged surface is an important quantity in many biological and material processes, and has been therefore investigated intensively. However, few theoretical and simulation approaches have included the influence of concentration-induced variations in the local dielectric permittivity of an underlying electrolyte solution. Such local variations have long been observed and known to affect the properties of ionic solution in the bulk and around the charged surface. We propose a hybrid computational model that combines Monte Carlo simulations with continuum electrostatic modeling to investigate such properties. A key component in our hybrid model is a semianalytical formula for the ion-ion interaction energy in a dielectrically inhomogeneous environment. This formula is obtained by solving for the Green's function Poisson's equation with ionic-concentration-dependent dielectric permittivity using a harmonic interpolation method and spherical harmonic series. We also construct a self-consistent continuum model of electrostatics to describe the effect of ionic-concentration-dependent dielectric permittivity and the resulting self-energy contribution. With extensive numerical simulations, we verify the convergence of our hybrid simulation scheme, show the qualitatively different structures of ionic distribution due to the concentration-induced dielectric variations, and compare our simulation results with the self-consistent continuum model. In particular, we study the differences between weakly and strongly charged surfaces and multivalencies of counterions. Our hybrid simulations conform particularly the depletion of ionic concentrations near a charged surface and also capture the charge inversion. We discuss several issues and possible further improvement of our approach for simulations of large charged systems.

  5. Metallo-dielectric hybrid antennas for ultrastrong enhancement of spontaneous emission

    CERN Document Server

    Chen, Xue-Wen; Sandoghdar, Vahid

    2012-01-01

    We devise new optical antennas that reduce the excited-state radiative lifetimes of emitters to the order of 100 femtoseconds while maintaining quantum efficiencies of about 80% at a broadband operation. Here, we combine metallic nanoparticles with planar dielectric structures and exploit design strategies from plasmonic nanoantennas and concepts from Cavity Quantum Electrodynamics to maximize the local density of states and minimize the nonradiative losses incurred by the metallic constituents. The proposed metallo-dielectric hybrid antennas promise important impact on various fundamental and applied research fields, including photophysics, ultrafast plasmonics, bright single photon sources and Raman spectroscopy.

  6. Hybrid HVDC circuit breaker with self-powered gate drives

    OpenAIRE

    Effah, Francis Boafo; Watson, Alan James; Ji, Chao; Amankwah, Emmanuel K.; Johnson, Christopher Mark; Davidson, Colin; Clare, Jon C.

    2016-01-01

    The ever increasing electric power demand and the advent of renewable energy sources have revived the interest in high-voltage direct current (HVDC) multi-terminal networks. However, the absence of a suitable circuit breaker or fault tolerant VSC station topologies with the required characteristics (such as operating speed) have, until recently, been an obstacle in the development of large scale multi-terminal networks for HVDC. This paper presents a hybrid HVDC circuit breaker concept which...

  7. Hybrid HVDC circuit breaker with self-powered gate drives

    OpenAIRE

    Effah, Francis Boafo; Watson, Alan James; Ji, Chao; Amankwah, Emmanuel K.; Johnson, Christopher Mark; Davidson, Colin; Clare, Jon C.

    2016-01-01

    The ever increasing electric power demand and the advent of renewable energy sources have revived the interest in high-voltage direct current (HVDC) multi-terminal networks. However, the absence of a suitable circuit breaker or fault tolerant VSC station topologies with the required characteristics (such as operating speed) have, until recently, been an obstacle in the development of large scale multi-terminal networks for HVDC. This paper presents a hybrid HVDC circuit breaker concept which ...

  8. Graduate Automotive Technology Education (GATE) Program: Center of Automotive Technology Excellence in Advanced Hybrid Vehicle Technology at West Virginia University

    Energy Technology Data Exchange (ETDEWEB)

    Nigle N. Clark

    2006-12-31

    This report summarizes the technical and educational achievements of the Graduate Automotive Technology Education (GATE) Center at West Virginia University (WVU), which was created to emphasize Advanced Hybrid Vehicle Technology. The Center has supported the graduate studies of 17 students in the Department of Mechanical and Aerospace Engineering and the Lane Department of Computer Science and Electrical Engineering. These students have addressed topics such as hybrid modeling, construction of a hybrid sport utility vehicle (in conjunction with the FutureTruck program), a MEMS-based sensor, on-board data acquisition for hybrid design optimization, linear engine design and engine emissions. Courses have been developed in Hybrid Vehicle Design, Mobile Source Powerplants, Advanced Vehicle Propulsion, Power Electronics for Automotive Applications and Sensors for Automotive Applications, and have been responsible for 396 hours of graduate student coursework. The GATE program also enhanced the WVU participation in the U.S. Department of Energy Student Design Competitions, in particular FutureTruck and Challenge X. The GATE support for hybrid vehicle technology enhanced understanding of hybrid vehicle design and testing at WVU and encouraged the development of a research agenda in heavy-duty hybrid vehicles. As a result, WVU has now completed three programs in hybrid transit bus emissions characterization, and WVU faculty are leading the Transportation Research Board effort to define life cycle costs for hybrid transit buses. Research and enrollment records show that approximately 100 graduate students have benefited substantially from the hybrid vehicle GATE program at WVU.

  9. Projected equations of motion approach to hybrid quantum/classical dynamics in dielectric-metal composites

    CERN Document Server

    McMillan, Ryan J; Grüning, Myrta

    2016-01-01

    We introduce a hybrid method for dielectric-metal composites that describes the dynamics of the metallic system classically whilst retaining a quantum description of the dielectric. The time-dependent dipole moment of the classical system is mimicked by the introduction of projected equations of motion (PEOM) and the coupling between the two systems is achieved through an effective dipole-dipole interaction. To benchmark this method, we model a test system (semiconducting quantum dot-metal nanoparticle hybrid). We begin by examining the energy absorption rate, showing agreement between the PEOM method and the analytical rotating wave approximation (RWA) solution. We then investigate population inversion and show that the PEOM method provides an accurate model for the interaction under ultrashort pulse excitation where the traditional RWA breaks down.

  10. Tunable electromagnetically induced transparency in hybrid graphene/all-dielectric metamaterial

    Science.gov (United States)

    Zhu, Lei; Dong, Liang; Guo, Jing; Meng, Fan-Yi; Wu, Qun

    2017-03-01

    We proposed a hybrid graphene/dielectric structure to achieve tunable electromagnetically induced transparency (EIT) effect. Unit cell of hybrid structure consists of a graphene strip as bright element and a dielectric split ring resonator (DSRR) as quasi-dark element. The destructive inference between dipolar plasmon resonance induced by graphene strip and Mie resonance induced by DSRR leads to famous EIT effect. By altering physical sizes of two resonant elements and their couplings, EIT resonance can be effectively controlled. In particular, EIT window and effective group index can be dynamically dominated by varying graphene strip's Fermi level. This active manipulation is also confirmed using "two-particle" model. More interestingly, EIT resonance can be also effectively modulated through controlling incident angles for electromagnetic (EM) waves. These results would have promising applications in areas of tunable slow light devices and new filters.

  11. On the origin of third harmonic light from hybrid metal-dielectric nanoantennas

    Science.gov (United States)

    de Ceglia, Domenico; Vincenti, Maria Antonietta; Scalora, Michael

    2016-11-01

    Near field amplification of electric fields magnifies the nonlinear optical signals generated in the metal volume of plasmonic nanoantennas, as well as in the surrounding media. We investigate the third harmonic light emitted by a hybrid nanoantenna composed of two metallic rods separated by a small gap filled with a dielectric. Despite the large cubic nonlinear susceptibility of metals, the presence of a hot spot in the antenna’s gap may easily transform weaker dielectric nonlinearities into the dominant source of third harmonic light. This has led to diverse and sometimes opposite interpretations of the nature of the nonlinear response, which are further complicated by the limited knowledge of the intrinsic nonlinear susceptibilities of the constituent materials. Here, a quantitative description of third harmonic generation is provided as a function of the ratio between the dielectric and the metal nonlinear susceptibilities in a hybrid metal-dielectric nanoantenna. We find a spectral discriminator that allows us to determine the origin of third harmonic light unambiguously.

  12. Hybrid polymer networks as ultra low `k` dielectric layers

    Energy Technology Data Exchange (ETDEWEB)

    Lewicki, James; Worsley, Marcus A.

    2016-02-16

    According to one embodiment, a polymeric material includes at least one polydimethylsiloxane (PDMS) polymer, and at least one polyhedral oligomericsilsequioxane (POSS) molecule. According to another embodiment, a method includes providing at least one polydimethylsiloxane (PDMS) polymer, providing at least one polyhedral oligomericsilsequioxane (POSS) molecule, and coupling the at least one PDSM polymer to the at least one POSS molecule to form a hybrid polymeric material.

  13. Formation of combined partially recessed and multiple fluorinated-dielectric layers gate structures for high threshold voltage GaN-based HEMT power devices

    Science.gov (United States)

    Huang, Huolin; Liang, Yung Chii

    2015-12-01

    The formation of partial AlGaN trench recess filled with multiple fluorinated gate dielectric layers as metal-insulator-semiconductor (MIS) gate structure for GaN-based HEMT power devices is designed, fabricated and experimentally verified. The approach realizes the device normally-off operational mode and at the same time is able to preserve the good mobility in the 2DEG channel for a maximum on-state current. Experimental measurements on the fabricated MIS-HEMT devices indicate a high gate threshold voltage (Vth) at around 5 V and a very low gate leakage current at pA/mm level. This proposed gate structure provides very promising properties for GaN-based power semiconductor devices in future power electronics switching applications.

  14. Effects of Ta incorporation in Y2O3 gate dielectric of InGaZnO thin-film transistor

    Science.gov (United States)

    Song, J. Q.; Qian, L. X.; Lai, P. T.

    2016-10-01

    The effects of Ta incorporation in Y2O3 gate dielectric on the electrical characteristics of InGaZnO thin-film transistor are investigated. With an appropriate Ta content in the Y2O3 gate dielectric, the saturation mobility of the thin-film transistor can be significantly increased, about three times that of the control sample with Y2O3 gate dielectric. Accordingly, the sample with a Ta/Ta+Y ratio of 68.6% presents a high saturation mobility of 33.5 cm2 V-1 s-1, low threshold voltage of 2.0 V, large on/off current ratio of 2.8 × 107, and suppressed hysteresis. This can be attributed to the fact that the Ta incorporation can suppress the hygroscopicity of Y2O3 and thus reduces the Y2O3/InGaZnO interface roughness and also the traps at/near the interface, as supported by atomic force microscopy and low-frequency noise measurement, respectively. However, excessive Ta incorporation in the Y2O3 gate dielectric leads to degradation in device performance because Ta-related defects are generated.

  15. Electrical characteristics of top contact pentacene organic thin film transistors with SiO2 and poly(methyl methacrylate) as gate dielectrics

    Indian Academy of Sciences (India)

    Jaya Lohani; Praveen Saho; Upender Kumar; V R Balakrishnan; P K Basu

    2008-09-01

    Organic thin film transistors (OTFTs) were fabricated using pentacene as the active layer with two different gate dielectrics, namely SiO2 and poly(methyl methacrylate) (PMMA), in top contact geometry for comparative studies. OTFTs with SiO2 as dielectric and gold deposited on the rough side of highly doped silicon (n+ -Si) as gate electrode exhibited reasonable field effect mobilities. To deal with poor stability and large leakage currents between source/drain and gate electrodes in these devices, isolated OTFTs with reduced source/drain contact area were fabricated by selective deposition of pentacene on SiO2/PMMA through shadow mask. This led to almost negligible leakage currents and no degradation in electrical performance even after 14 days of storage under ambient conditions. But, the field effect mobilities obtained were lower than 10-3 cm2 V-1 s-1, whereas by using PMMA as gate dielectric with chromium deposited on the polished side of n+ -Si as gate electrode, improved field effect mobilities (> 0.02 cm2 V-1 s-1) were obtained. PMMA-based OTFTs also exhibited lower leakage currents and reproducible output characteristics even after 30 days of storage under ambient conditions.

  16. The electrical characteristics of a 4H-silicon carbide metal-insulator-semiconductor structure with Al2O3 as the gate dielectric

    Institute of Scientific and Technical Information of China (English)

    Liu Li; Yang Yin-Tang; Ma Xiao-Hua

    2011-01-01

    A 4H-silicon carbide metal-insulator-semiconductor structure with ultra-thin Al2O3 as the gate dielectric,deposited by atomic layer deposition on the epitaxial layer of a 4H-SiC (0001) 8(0)N-/N+ substrate,has been fabricated.The experimental results indicate that the prepared ultra-thin Al2O3 gate dielectric exhibits good physical and electrical characteristics,including a high breakdown electrical field of 25 MV/cm,excellent interface properties (1 × 1014 cm-2)and low gate-leakage current (IG =1 × 10-3 A/cm-2(o)Eox =8 MV/cm).Analysis of the current conduction mechanism on the deposited Al2O3 gate dielectric was also systematically performed.The confirmed conduction mechanisms consisted of Fowler-Nordheim (FN) tunneling,the Frenkel-Poole mechanism,direct tunneling and Schottky emission,and the dominant current conduction mechanism depends on the applied electrical field.When the gate leakage current mechanism is dominated by FN tunneling,the barrier height of SiC/Al2O3 is 1.4 eV,which can meet the requirements of silicon carbide metal-insulator-semiconductor transistor devices.

  17. Effects of annealing on electrical performance of multilayer MoS2 transistors with atomic layer deposited HfO2 gate dielectric

    Science.gov (United States)

    Wen, Ming; Xu, Jingping; Liu, Lu; Lai, Pui-To; Tang, Wing-Man

    2016-09-01

    Atomic layer deposited HfO2 annealed in different ambients (N2, O2, and NH3) is used to replace SiO2 as a gate dielectric for fabricating back-gated multilayer MoS2 transistors. Excellent electrical properties such as a mobility of 15.1 cm2/(V·s), an on/off ratio exceeding 107, and a hysteresis of 0.133 V are achieved for samples annealed in NH3 at 400 °C for 10 min. This is caused by the NH3 annealing passivation effects that reduce defective states in the HfO2 dielectric and the interface. The capacitance equivalent thickness is only 7.85 nm, which is quite small for a back-gated MoS2 transistor and is conducive to the scaling down of the device.

  18. A hydrogel capsule as gate dielectric in flexible organic field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Dumitru, L. M.; Manoli, K.; Magliulo, M.; Torsi, L., E-mail: luisa.torsi@uniba.it [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Ligonzo, T. [Department of Physics, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Palazzo, G. [Department of Chemistry, University of Bari “Aldo Moro”, Via Orabona 4, Bari I-70126 (Italy); Center of Colloid and Surface Science—CSGI—Bari Unit, Via Orabona 4, Bari I-70126 (Italy)

    2015-01-01

    A jellified alginate based capsule serves as biocompatible and biodegradable electrolyte system to gate an organic field-effect transistor fabricated on a flexible substrate. Such a system allows operating thiophene based polymer transistors below 0.5 V through an electrical double layer formed across an ion-permeable polymeric electrolyte. Moreover, biological macro-molecules such as glucose-oxidase and streptavidin can enter into the gating capsules that serve also as delivery system. An enzymatic bio-reaction is shown to take place in the capsule and preliminary results on the measurement of the electronic responses promise for low-cost, low-power, flexible electronic bio-sensing applications using capsule-gated organic field-effect transistors.

  19. Linear and Nonlinear Rheology Combined with Dielectric Spectroscopy of Hybrid Polymer Nanocomposites for Semiconductive Applications

    Directory of Open Access Journals (Sweden)

    Roland Kádár

    2017-01-01

    Full Text Available The linear and nonlinear oscillatory shear, extensional and combined rheology-dielectric spectroscopy of hybrid polymer nanocomposites for semiconductive applications were investigated in this study. The main focus was the influence of processing conditions on percolated poly(ethylene-butyl acrylate (EBA nanocomposite hybrids containing graphite nanoplatelets (GnP and carbon black (CB. The rheological response of the samples was interpreted in terms of dispersion properties, filler distortion from processing, filler percolation, as well as the filler orientation and distribution dynamics inside the matrix. Evidence of the influence of dispersion properties was found in linear viscoelastic dynamic frequency sweeps, while the percolation of the nanocomposites was detected in nonlinearities developed in dynamic strain sweeps. Using extensional rheology, hybrid samples with better dispersion properties lead to a more pronounced strain hardening behavior, while samples with a higher volume percentage of fillers caused a drastic reduction in strain hardening. The rheo-dielectric time-dependent response showed that in the case of nanocomposites containing only GnP, the orientation dynamics leads to non-conductive samples. However, in the case of hybrids, the orientation of the GnP could be offset by the dispersing of the CB to bridge the nanoplatelets. The results were interpreted in the framework of a dual PE-BA model, where the fillers would be concentrated mainly in the BA regions. Furthermore, better dispersed hybrids obtained using mixing screws at the expense of filler distortion via extrusion processing history were emphasized through the rheo-dielectric tests.

  20. Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

    Science.gov (United States)

    Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

    2016-01-01

    Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

  1. 2 MeV electron irradiation effects on bulk and interface of atomic layer deposited high-k gate dielectrics on silicon

    Energy Technology Data Exchange (ETDEWEB)

    García, H., E-mail: hecgar@ele.uva.es [Departamento de Electricidad y Electrónica, ETSI Telecomunicación, Universidad de Valladolid, 47011 Valladolid (Spain); Castán, H.; Dueñas, S.; Bailón, L. [Departamento de Electricidad y Electrónica, ETSI Telecomunicación, Universidad de Valladolid, 47011 Valladolid (Spain); Campabadal, F.; Rafí, J.M.; Zabala, M.; Beldarrain, O. [Institut de Microelectrònica de Barcelona (IMB-CNM), CSIC, Campus UAB, 08193 Bellaterra (Spain); Ohyama, H.; Takakura, K.; Tsunoda, I. [Department of Electronic Engineering, Kumamoto National College of Technology, Kumamoto 861-1102 (Japan)

    2013-05-01

    2 MeV electron irradiation effects on the electrical properties of Al{sub 2}O{sub 3} and HfO{sub 2}-based metal–insulator–semiconductor capacitors have been studied. High-k dielectrics were directly grown on silicon by atomic layer deposition. Capacitors were exposed to three different electron irradiation doses of 0.025, 0.25 and 2.5 MGy. Capacitance–voltage, deep-level transient spectroscopy, conductance transients, flat-band voltage transients and current–voltage techniques were used to characterize the defects induced or activated by irradiation on the dielectric bulk and on the interface with silicon substrate. In all cases, positive charge is trapped in the dielectric bulk after irradiation indicating the existence of hole traps in the dielectric. When the samples are exposed to 2 MeV electron beam (e-beam) irradiation, electron–hole pairs are created and holes are then captured by the hole traps. Insulator/semiconductor interface quality slightly improves for low irradiation doses, but it is degraded for high doses. Irradiation always degrades the dielectric layers in terms of gate leakage current: the trapped holes are mobile charge which can contribute to leakage current by hopping from trap to trap. - Highlights: ► Positive charge accumulates inside dielectrics after electron irradiation. ► Irradiation improves oxide/semiconductor interface for low doses. ► Irradiation increases gate leakage current.

  2. Investigation of light doping and hetero gate dielectric carbon nanotube tunneling field-effect transistor for improved device and circuit-level performance

    Science.gov (United States)

    Wang, Wei; Sun, Yuan; Wang, Huan; Xu, Hongsong; Xu, Min; Jiang, Sitao; Yue, Gongshu

    2016-03-01

    We perform a comparative study (both for device and circuit simulations) of three carbon nanotube tunneling field-effect transistor (CNT-TFET) designs: high-K gate dielectric TFETs (HK-TFETs), hetero gate dielectric TFETs (HTFETs) and a novel CNT-TFET-based combination of light doping and hetero gate dielectric TFETs (LD-HTFETs). At device level, the effects of channel and gate dielectric engineering on the switching and high-frequency characteristics for CNT-TFET have been theoretically investigated using a quantum kinetic model. This model is based on two-dimensional non-equilibrium Green’s functions solved self-consistently with Poisson’s equations. It is revealed that the proposed LD-HTFET structure can significantly reduce leakage current, enhance control ability of the gate on the channel, improve the switching speed, and is more suitable for use in low-power, high-frequency circuits. At circuit level, using HSPICE with look-up table-based Verilog-A models, the performance and reliability of CNT-TFET logic gate circuits is evaluated on the basis of power consumption, average delay, stability, energy consumption and power-delay product (PDP). Simulation results indicate that, compared to a traditional CNT-TFET-based circuit, the one based on LD-HTFET has a significantly better performance (static noise margin, energy, delay, PDP). It is also observed that our proposed design exhibits better robustness under different operational conditions by considering power supply voltage and temperature variations. Our results may be useful for designing and optimizing CNTFET devices and circuits.

  3. In-situ RHEED analysis of atomic layer deposition and characterization of AL203 gate dielectrics

    NARCIS (Netherlands)

    Bankras, R.G.; Aarnink, A.A.I.; Holleman, J.; Schmitz, J.

    2003-01-01

    A new custom designed reactor was realized at the MESA+ cleanroom to fabricate high-k dielectrics using atomic layer deposition (ALD). Key features of the reactor are: a small reactor volume, in-situ RHEED analysis and low background pressure. The effect of precursor and purge pulse times is discuss

  4. Plasmon-gating photoluminescence in graphene/GeSi quantum dots hybrid structures

    Science.gov (United States)

    Chen, Yulu; Wu, Qiong; Ma, Yingjie; Liu, Tao; Fan, Yongliang; Yang, Xinju; Zhong, Zhenyang; Xu, Fei; Lu, Jianping; Jiang, Zuimin

    2015-01-01

    The ability to control light-matter interaction is central to several potential applications in lasing, sensing, and communication. Graphene plasmons provide a way of strongly enhancing the interaction and realizing ultrathin optoelectronic devices. Here, we find that photoluminescence (PL) intensities of the graphene/GeSi quantum dots hybrid structures are saturated and quenched under positive and negative voltages at the excitation of 325 nm, respectively. A mechanism called plasmon-gating effect is proposed to reveal the PL dependence of the hybrid structures on the external electric field. On the contrary, the PL intensities at the excitation of 405 and 795 nm of the hybrid structures are quenched due to the charge transfer by tuning the Fermi level of graphene or the blocking of the excitons recombination by excitons separation effect. The results also provide an evidence for the charge transfer mechanism. The plasmon gating effect on the PL provides a new way to control the optical properties of graphene/QD hybrid structures. PMID:26631498

  5. In-situ RHEED and characterization of ALD Al2O3 gate dielectrics

    NARCIS (Netherlands)

    Bankras, Radko Gerard

    2006-01-01

    In-situ RHEED en karakterisatie van ALD Al2O3 gate diëlektrica Sinds de introductie van de MOSFET transistor (metaal-oxide-silicium veldeffecttransistor) in 1960, heeft de halfgeleidertechnologie een snelle ontwikkeling doorgemaakt. Deze vooruitgang bestond hoofdzakelijk uit de mogelijkheid om trans

  6. Graphene oxide-encapsulated carbon nanotube hybrids for high dielectric performance nanocomposites with enhanced energy storage density.

    Science.gov (United States)

    Wu, Chao; Huang, Xingyi; Wu, Xinfeng; Xie, Liyuan; Yang, Ke; Jiang, Pingkai

    2013-05-07

    Polymer-based materials with a high dielectric constant show great potential for energy storage applications. Since the intrinsic dielectric constant of most polymers is very low, the integration of carbon nanotubes (CNTs) into the polymers provides an attractive and promising way to reach a high dielectric constant owing to their outstanding intrinsic physical performances. However, these CNT-based composites usually suffer from high dielectric loss, low breakdown strength and the difficulty to tailor the dielectric constant. Herein, we have designed and fabricated a new class of candidates composed of graphene oxide-encapsulated carbon nanotube (GO-e-CNT) hybrids. The obtained GO-e-CNT-polymer composites not only exhibit a high dielectric constant and low dielectric loss, but also have a highly enhanced breakdown strength and maximum energy storage density. Moreover, the dielectric constant of the composites can be tuned easily by tailoring the loading of GO-e-CNTs. It is believed that the GO shells around CNTs play an important role in realizing the high dielectric performances of the composites. GO shells can not only effectively improve the dispersion of CNTs, but also act as insulation barriers for suppressing leakage current and increasing breakdown strength. Our strategy provides a new pathway to achieve CNT-based polymer composites with high dielectric performances for energy storage applications.

  7. Thermally oxidized 2D TaS2 as a high-κ gate dielectric for MoS2 field-effect transistors

    Science.gov (United States)

    Chamlagain, Bhim; Cui, Qingsong; Paudel, Sagar; Ming-Cheng Cheng, Mark; Chen, Pai-Yen; Zhou, Zhixian

    2017-09-01

    We report a new approach to integrating high-κ dielectrics in both bottom- and top-gated MoS2 field-effect transistors (FETs) through thermal oxidation and mechanical assembly of layered two-dimensional (2D) TaS2. Combined x-ray photoelectron spectroscopy (XPS), optical microscopy, atomic force microscopy (AFM), and capacitance-voltage (C-V) measurements confirm that multilayer TaS2 flakes can be uniformly transformed to Ta2O5 with a high dielectric constant of ~15.5 via thermal oxidation, while preserving the geometry and ultra-smooth surfaces of 2D TMDs. Top-gated MoS2 FETs fabricated using the thermally oxidized Ta2O5 as gate dielectric demonstrate a high current on/off ratio approaching 106, a subthreshold swing (SS) down to 61 mV/dec, and a field-effect mobility exceeding 60 cm2 V-1 s-1 at room temperature, indicating high dielectric quality and low interface trap density.

  8. Effect of annealing temperature on structural and electrical properties of high-κ YbTixOy gate dielectrics for InGaZnO thin film transistors

    Science.gov (United States)

    Pan, Tung-Ming; Chen, Fa-Hsyang; Hung, Meng-Ning

    2015-01-01

    This paper describes the effect of annealing temperature on the structural properties and electrical characteristics of high-κ YbTixOy gate dielectrics for indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs). X-ray diffraction, x-ray photoelectron spectroscopy and atomic force microscopy were used to study the structural, chemical and morphological features, respectively, of these dielectric films annealed at 200, 300 and 400 °C. The YbTixOy IGZO TFT that had been annealed at 400 °C exhibited better electrical characteristics, such as a small threshold voltage of 0.53 V, a large field-effect mobility of 19.1 cm2 V-1 s-1, a high Ion/Ioff ratio of 2.8 × 107, and a low subthreshold swing of 176 mV dec.-1, relative to those of the systems that had been subjected to other annealing conditions. This result suggests that YbTixOy dielectric possesses a higher dielectric constant as well as lower oxygen vacancies (or defects) in the film. In addition, the instability of YbTixOy IGZO TFT was studied under positive gate-bias stress and negative gate-bias stress conditions.

  9. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    Science.gov (United States)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-09-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems.

  10. Proton Conducting Graphene Oxide/Chitosan Composite Electrolytes as Gate Dielectrics for New-Concept Devices

    Science.gov (United States)

    Feng, Ping; Du, Peifu; Wan, Changjin; Shi, Yi; Wan, Qing

    2016-01-01

    New-concept devices featuring the characteristics of ultralow operation voltages and low fabrication cost have received increasing attention recently because they can supplement traditional Si-based electronics. Also, organic/inorganic composite systems can offer an attractive strategy to combine the merits of organic and inorganic materials into promising electronic devices. In this report, solution-processed graphene oxide/chitosan composite film was found to be an excellent proton conducting electrolyte with a high specific capacitance of ~3.2 μF/cm2 at 1.0 Hz, and it was used to fabricate multi-gate electric double layer transistors. Dual-gate AND logic operation and two-terminal diode operation were realized in a single device. A two-terminal synaptic device was proposed, and some important synaptic behaviors were emulated, which is interesting for neuromorphic systems. PMID:27688042

  11. Fabrication of pentacene organic field-effect transistors with polyimide gate dielectric layer

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    The organic field effect transistors had been fabricated using the pentacene by vacuum evaporation as the active layer, the polyimide by spin coating as insulator layer, and aluminum by vacuum evaporation as gate, source and drain electrodes respectively. The field-effect mobility of 0.079 cm2/V.s was tested at Vds=70 V, and on/off radio up to 1.7×104.

  12. Charge Qubit-Atom Hybrid

    CERN Document Server

    Yu, Deshui; Hufnagel, C; Kwek, L C; Amico, Luigi; Dumke, R

    2016-01-01

    We investigate a novel hybrid system of a superconducting charge qubit interacting directly with a single neutral atom via electric dipole coupling. Interfacing of the macroscopic superconducting circuit with the microscopic atomic system is accomplished by varying the gate capacitance of the charge qubit. To achieve strong interaction, we employ two Rydberg states with an electric-dipole-allowed transition, which alters the polarizability of the dielectric medium of the gate capacitor. Sweeping the gate voltage with different rates leads to a precise control of hybrid quantum states. Furthermore, we show a possible implementation of a universal two-qubit gate.

  13. Electrical analysis of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors on flexible bulk mono-crystalline silicon

    KAUST Repository

    Ghoneim, Mohamed T.

    2015-06-01

    We report on the electrical study of high dielectric constant insulator and metal gate metal oxide semiconductor capacitors (MOSCAPs) on a flexible ultra-thin (25 μm) silicon fabric which is peeled off using a CMOS compatible process from a standard bulk mono-crystalline silicon substrate. A lifetime projection is extracted using statistical analysis of the ramping voltage (Vramp) breakdown and time dependent dielectric breakdown data. The obtained flexible MOSCAPs operational voltages satisfying the 10 years lifetime benchmark are compared to those of the control MOSCAPs, which are not peeled off from the silicon wafer. © 2014 IEEE.

  14. Electrical properties of Ge metal-oxide-semiconductor capacitors with high-k La2O3 gate dielectric incorporated by N or/and Ti

    Science.gov (United States)

    Huoxi, Xu; Jingping, Xu

    2016-06-01

    LaON, LaTiO and LaTiON films are deposited as gate dielectrics by incorporating N or/and Ti into La2O3 using the sputtering method to fabricate Ge MOS capacitors, and the electrical properties of the devices are carefully examined. LaON/Ge capacitors exhibit the best interface quality, gate leakage property and device reliability, but a smaller k value (14.9). LaTiO/Ge capacitors exhibit a higher k value (22.7), but a deteriorated interface quality, gate leakage property and device reliability. LaTiON/Ge capacitors exhibit the highest k value (24.6), and a relatively better interface quality (3.1 × 1011 eV-1 cm-2), gate leakage property (3.6 × 10-3 A/cm2 at V g = 1 V + V fb) and device reliability. Therefore, LaTiON is more suitable for high performance Ge MOS devices as a gate dielectric than LaON and LaTiO materials. Project supported by the National Natural Science Foundation of China (No. 61274112), the Natural Science Foundation of Hubei Province (No. 2011CDB165), and the Scientific Research Program of Huanggang Normal University (No. 2012028803).

  15. Interaction of La2O3 capping layers with HfO2 gate dielectrics

    Science.gov (United States)

    Copel, M.; Guha, S.; Bojarczuk, N.; Cartier, E.; Narayanan, V.; Paruchuri, V.

    2009-11-01

    We report the effect of La2O3 capping layers on HfO2/SiO2/Si dielectrics, proposed for use in threshold voltage tuning of field effect transistors. Depth profiling with medium energy ion scattering shows that an initial surface layer of La2O3 diffuses through the HfO2 at elevated temperatures, ultimately converting some of the thin interfacial SiO2 into a silicate. Core-level photoemission measurements indicate that the additional band-bending induced by the La2O3 only appears after diffusion, and the added charge resides between the HfO2 and the substrate.

  16. Electrical properties and noise characterization of HfO{sub 2} gate dielectrics on strained SiGe layers

    Energy Technology Data Exchange (ETDEWEB)

    Mallik, S., E-mail: sandi.iitkgp@gmail.com [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India); Dept. of Electronics and Telecommunication Engineering, Jadavpur University, Jadavpur, Kolkata 700032 (India); Mukherjee, C.; Mahata, C.; Hota, M.K.; Das, T. [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India); Dalapati, G.K.; GaO, H.; Kumar, M.K.; Chi, D.Z. [Institute of Materials Research and Engineering, A-STAR (Agency for Science, Technology and Research), 3 Research Link, Singapore 117602 (Singapore); Sarkar, C.K. [Dept. of Electronics and Telecommunication Engineering, Jadavpur University, Jadavpur, Kolkata 700032 (India); Maiti, C.K. [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India)

    2012-11-01

    Ultra thin HfO{sub 2} high-k gate dielectric has been deposited directly on strained Si{sub 0.81}Ge{sub 0.19} by atomic layer deposition process. Important electrical properties such as, interface trap density, charge trapping behavior, and low-frequency noise characteristics have been studied in detail. Grazing incidence X-ray diffraction analysis shows that the conversion from amorphous to crystalline phase start to appear in the HfO{sub 2} films when annealed between 400 and 500 Degree-Sign C. Interface trap density was found to be in the range of 4.0-5.6 Multiplication-Sign 10{sup 11} eV{sup -1} cm{sup -2}. Results of internal photoemission studies on pre-existing charge trapping for different processing conditions; without annealing and annealed in O{sub 2}, N{sub 2} and mixed (O{sub 2} and N{sub 2}) ambient are presented. Low-frequency noise characteristics of HfO{sub 2}/Si0{sub .81}Ge{sub 0.19} stacks annealed in different gas ambient have been measured using metal-insulator-semiconductor capacitors (contact area {approx} 2 Multiplication-Sign 10{sup -3} cm{sup 2}). It is found that the sample annealed in N{sub 2} gas ambient shows better electrical properties in general compared to samples annealed in O{sub 2} and/or mixed (O{sub 2} and N{sub 2}) gas ambient. - Highlights: Black-Right-Pointing-Pointer Electrical characterization of ultra thin HfO{sub 2} high-k gate dielectric stacks Black-Right-Pointing-Pointer Study of interface trap density, charge trapping behavior, and low-frequency noise Black-Right-Pointing-Pointer Comparison of electrical properties of samples annealed in N{sub 2}, N{sub 2} + O{sub 2}, O{sub 2} gas Black-Right-Pointing-Pointer Trap locations are estimated from bias dependency of random telegraph signal. Black-Right-Pointing-Pointer Superiority of N{sub 2} annealed sample is demonstrated from electrical characterization.

  17. Sol–gel deposited ceria thin films as gate dielectric for CMOS technology

    Indian Academy of Sciences (India)

    Anil G Khairnar; Ashok M Mahajan

    2013-04-01

    In this work, cerium oxide thin films were prepared using cerium chloride heptahydrate, ethanol and citric acid as an additive by sol–gel spin-coating technique and further characterized to study the various properties. Chemical composition of deposited films has been analysed by FTIR which shows existence of CeO2. The samples have been optically characterized using ellipsometry to find refractive index of 2.18 and physical thickness which is measured to be 5.56 nm. MOS capacitors were fabricated by depositing aluminum (Al) metal using the thermal evaporation technique on the top of CeO2 thin films. Capacitance–voltage measurement was carried out to calculate the dielectric constant, flat-band voltage shift of 18.92, 0.3–0.5V, respectively and conductance–voltage study was carried out to determine the Dit of 1.40 × 1013 eV-1 cm-2 at 1MHz.

  18. Highly stretchable carbon nanotube transistors enabled by buckled ion gel gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Meng-Yin; Chang, Tzu-Hsuan; Ma, Zhenqiang [Department of Electrical and Computer Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Zhao, Juan [School of Optoelectronic Information, University of Electronic Science and Technology of China, Chengdu 610054 (China); Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States); Xu, Feng; Jacobberger, Robert M.; Arnold, Michael S., E-mail: michael.arnold@wisc.edu [Department of Materials Science and Engineering, University of Wisconsin-Madison, Madison, Wisconsin 53706 (United States)

    2015-08-03

    Deformable field-effect transistors (FETs) are expected to facilitate new technologies like stretchable displays, conformal devices, and electronic skins. We previously demonstrated stretchable FETs based on buckled thin films of polyfluorene-wrapped semiconducting single-walled carbon nanotubes as the channel, buckled metal films as electrodes, and unbuckled flexible ion gel films as the dielectric. The FETs were stretchable up to 50% without appreciable degradation in performance before failure of the ion gel film. Here, we show that by buckling the ion gel, the integrity and performance of the nanotube FETs are extended to nearly 90% elongation, limited by the stretchability of the elastomer substrate. The FETs maintain an on/off ratio of >10{sup 4} and a field-effect mobility of 5 cm{sup 2} V{sup −1} s{sup −1} under elongation and demonstrate invariant performance over 1000 stretching cycles.

  19. Strain-Gated Field Effect Transistor of a MoS2-ZnO 2D-1D Hybrid Structure.

    Science.gov (United States)

    Chen, Libo; Xue, Fei; Li, Xiaohui; Huang, Xin; Wang, Longfei; Kou, Jinzong; Wang, Zhong Lin

    2016-01-26

    Two-dimensional (2D) molybdenum disulfide (MoS2) is an exciting material due to its unique electrical, optical, and piezoelectric properties. Owing to an intrinsic band gap of 1.2-1.9 eV, monolayer or a-few-layer MoS2 is used for fabricating field effect transistors (FETs) with high electron mobility and on/off ratio. However, the traditional FETs are controlled by an externally supplied gate voltage, which may not be sensitive enough to directly interface with a mechanical stimulus for applications in electronic skin. Here we report a type of top-pressure/force-gated field effect transistors (PGFETs) based on a hybrid structure of a 2D MoS2 flake and 1D ZnO nanowire (NW) array. Once an external pressure is applied, the piezoelectric polarization charges created at the tips of ZnO NWs grown on MoS2 act as a gate voltage to tune/control the source-drain transport property in MoS2. At a 6.25 MPa applied stimulus on a packaged device, the source-drain current can be tuned for ∼25%, equivalent to the results of applying an extra -5 V back gate voltage. Another type of PGFET with a dielectric layer (Al2O3) sandwiched between MoS2 and ZnO also shows consistent results. A theoretical model is proposed to interpret the received data. This study sets the foundation for applying the 2D material-based FETs in the field of artificial intelligence.

  20. Investigation of high-quality ultra-thin LaAlO{sub 3} films as high-k gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Lu, X B [National Laboratory of Solid State Microstructures, Nanjing University, Hankou Road 22, Nanjing 210093 (China); Liu, Z G [National Laboratory of Solid State Microstructures, Nanjing University, Hankou Road 22, Nanjing 210093 (China); Zhang, X [Institute of Microelectronics, Peking University, Beijing 100871 (China); Huang, R [Institute of Microelectronics, Peking University, Beijing 100871 (China); Zhou, H W [Digital DNA Laboratories, Motorola Inc. (China); Wang, X P [Digital DNA Laboratories, Motorola Inc.(China); Nguyen, Bich-Yen [Digital DNA Laboratories, Motorola Inc. (China)

    2003-12-07

    We have studied the formation of a high-quality LaAlO{sub 3} (LAO) film directly on silicon substrates by the pulsed laser deposition method as a novel high-k gate dielectric. The LAO films can remain amorphous at temperatures up to 850 deg. C. An atomic force microscopy study indicated a very smooth surface of the deposited films with a rms of 0.14 nm for an 8 nm LAO film. The structures and electrical properties of metal-dielectric-semiconductor (Pt/LAO/Si) capacitors were investigated with LAO films deposited under different ambient conditions. High-resolution transmission electron microscopy indicated that interfacial reactions often occur for films of LAO deposited under oxygen ambient. A small effective oxide thickness of 1.2 nm was obtained for those films deposited under 20 Pa nitrogen ambient, with the corresponding leakage current density 17.1 mA cm{sup -2} at +1 V gate voltage. It is proposed that amorphous LAO films are a novel promising alternative high-k gate dielectric material in future ultra-large scale integrated devices.

  1. Measurement based controlled not gate for topological qubits in a Majorana fermion and quantum-dot hybrid system

    Science.gov (United States)

    Xue, Zheng-Yuan

    2013-04-01

    We propose a scheme to implement controlled not gate for topological qubits in a quantum-dot and Majorana fermion hybrid system. Quantum information is encoded on pairs of Majorana fermions, which live on the the interface between topologically trivial and nontrivial sections of a quantum nanowire deposited on an s-wave superconductor. A measurement based two-qubit controlled not gate is produced with the help of parity measurements assisted by the quantum-dot and followed by prescribed single-qubit gates. The parity measurement, on the quantum-dot and a topological qubit, is achieved by the Aharonov-Casher effect.

  2. Critical interparticle distance for the remarkably enhanced dielectric constant of BaTiO3-Ag hybrids filled polyvinylidene fluoride composites

    Science.gov (United States)

    Luo, Suibin; Yu, Shuhui; Fang, Fang; Lai, Maobai; Sun, Rong; Wong, Ching-Ping

    2014-06-01

    Discrete nano Ag-deposited BaTiO3 (BT-Ag) hybrids with varied Ag content were synthesized, and the hybrids filled polyvinylidene fluoride (PVDF) composites were prepared. The effect of Ag content on the dielectric properties of the composites were analyzed based on the diffused electrical double layer theory. Results showed that with a higher Ag content in BT-Ag hybrids, the dielectric constant of BT-Ag/PVDF composites increases fast with the filler loading, while the dielectric loss and conductivity showed a suppressed and moderate increase. The dielectric constant of BT-0.61Ag/PVDF (61 wt. % of Ag in BT-Ag hybrid) composites reached 613, with the dielectric loss of 0.29 at 1 kHz. It was deduced that remarkably enhanced dielectric constant appeared when the interparticle distance decreased to a critical value of about 20 nm.

  3. Transcap: A new integrated hybrid supercapacitor and electrolyte-gated transistor device (Presentation Recording)

    Science.gov (United States)

    Santato, Clara

    2015-10-01

    The boom in multifunctional, flexible, and portable electronics and the increasing need of low-energy cost and autonomy for applications ranging from wireless sensor networks for smart environments to biomedical applications are triggering research efforts towards the development of self-powered sustainable electronic devices. Within this context, the coupling of electronic devices (e.g. sensors, transistors) with small size energy storage systems (e.g. micro-batteries or micro-supercapacitors) is actively pursued. Micro-electrochemical supercapacitors are attracting much attention in electronics for their capability of delivering short power pulses with high stability over repeated charge/discharge cycling. For their high specific pseudocapacitance, electronically conducting polymers are well known as positive materials for hybrid supercapacitors featuring high surface carbon negative electrodes. The processability of both polymer and carbon is of great relevance for the development of flexible miniaturised devices. Electronically conducting polymers are even well known to feature an electronic conductivity that depends on their oxidation (p-doped state) and that it is modulated by the polymer potential. This property and the related pseudocapacitive response make polymer very attracting channel materials for electrolyte-gated (EG) transistors. Here, we propose a novel concept of "Trans-capacitor", an integrated device that exhibits the storage properties of a polymer/carbon hybrid supercapacitor and the low-voltage operation of an electrolyte-gated transistor.

  4. The thermal stability and electrical properties of LaErO{sub 3} films as high-k gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Gao Xu; Yin Jiang; Xia Yidong; Yin Kuibo; Gao Ligang; Guo Hongxuan; Liu Zhiguo [National Laboratory of Solid State Microstructure, Nanjing University, Nanjing 210093 (China)], E-mail: jyin@nju.edu.cn

    2008-12-07

    Lanthanum erbium oxide thin films have been deposited on an Si (1 0 0) wafer by using the pulsed laser deposition technique. The thermal and electrical properties of LaErO{sub 3} films were investigated by x-ray diffraction, x-ray photoelectron spectroscopy and high resolution transmission electron microscopy. Capacitance measurements reveal good C-V curves with an equivalent oxide thickness of 1.4 nm and little hysteresis. Transmission electron microscopic images reveal that the 6.5 nm LaErO{sub 3} film shows a thin interfacial layer even after being annealed in N{sub 2} at 700 deg. C for 30 s. X-ray photoelectron spectroscopic spectra indicate that little SiO{sub 2} was formed at the interface during the deposition of LaErO{sub 3} films. The measured thermal and electrical properties of the thin film suggest that the LaErO{sub 3} film should be a promising candidate for future high-k gate dielectrics.

  5. Atom probe tomography studies of Al₂O₃ gate dielectrics on GaN

    Energy Technology Data Exchange (ETDEWEB)

    Mazumder, Baishakhi, E-mail: bmazumder@engineering.ucsb.edu; Wu, Feng; Speck, James S. [Materials Department, University of California, Santa Barbara, California 93106 (United States); Liu, Xiang; Yeluri, Ramya; Mishra, Umesh K. [Electrical and Computer Engineering Department, University of California, Santa Barbara, California 93106 (United States)

    2014-10-07

    Atom probe tomography was used to achieve three-dimensional characterization of in situ Al₂O₃/GaN structures grown by metal organic chemical vapor deposition (MOCVD). Al₂O₃ dielectrics grown at three different temperatures of 700, 900, and 1000 °C were analyzed and compared. A low temperature GaN cap layer grown atop Al₂O₃ enabled a high success rate in the atom probe experiments. The Al₂O₃/GaN interfaces were found to be intermixed with Ga, N, and O over the distance of a few nm. Impurity measurements data showed that the 1000 °C sample contains higher amounts of C (4 × 10¹⁹/cm³) and lower amounts of H (7 × 10¹⁹/cm³), whereas the 700 °C sample exhibits lower C impurities (<10¹⁷/cm³) and higher H incorporation (2.2 × 10²⁰/cm³). On comparing with Al₂O₃ grown by atomic layer deposition (ALD), it was found that the MOCVD Al₂O₃/GaN interface is comparatively abrupt. Scanning transmission electron microscopy data showed that the 900 °C and 1000 °C MOCVD films exhibit polycrystalline nature, while the ALD films were found to be amorphous.

  6. Synthesis of Cerium Dioxide High-k Thin Films as a Gate Dielectric in MOS Capacitor

    Directory of Open Access Journals (Sweden)

    Anil G. Khairnar

    2013-07-01

    Full Text Available In the present study, the Al/CeO2 / p-Si MOS capacitor was fabricated by depositing the Aluminium (Al metal layer by thermal evaporation technique on sol-gel derived CeO2 high-k thin films on p-Si substrate. The deposited CeO2 films were characterized by Ellipsometer to study the refractive index that is determined to be 3.62. The FTIR analysis was carried out to obtain chemical bonding characteristics. Capacitance-voltage measurements of Al/CeO2 /p-Si MOS capacitor were carried out to determine the dielectric constant, equivalent oxide thickness (EOT and flat band shift (VFB for the deposited CeO2 film of 16.22, 1.62 nm and 0.7 V respectively. The conductance voltage curve was used to determine the interface trap density (Dit at the CeO2 / p-Si interface that is calculated to be 1.29 × 1013 cm – 2 eV – 1 for measurement frequency of 500 kHz.

  7. A Compact Wide-Band Hybrid Dielectric Resonator Antenna with Enhanced Gain and Low Cross-Polarization

    Directory of Open Access Journals (Sweden)

    Feibiao Dong

    2017-01-01

    Full Text Available By loading two printed patches to the dielectric resonator antenna (DRA, a compact wide-band hybrid dielectric resonator antenna with enhanced gain and low cross-polarization is presented. The proposed antenna utilizes a combination of a rectangular dielectric resonator and two printed patches. Due to the hybrid design, multiple resonances were obtained. By adding two air layers between the dielectric resonator and the printed patches, the bandwidth has been significantly improved. Compared to the traditional hybrid dielectric resonator antenna, the proposed antenna can achieve wide bandwidth, high gain, low cross-polarization, and even small size simultaneously. The prototype of the proposed antenna has been fabricated and tested. The measured −10 dB return loss bandwidth is 25.6% (1.7–2.2 GHz. The measured antenna gains are about 6.3 and 8.2 dBi in the operating frequency band. Low cross-polarization levels of less than −28.5 dB and −43 dB in the E-plane and H-plane are achieved. Moreover, the overall dimensions of the antenna are only 67 × 67 × 34 (mm3. The proposed antenna is especially attractive for small base antenna applications.

  8. Graduate Automotive Technology Education (GATE) Center for Hybrid Electric Drivetrains and Control Strategies

    Energy Technology Data Exchange (ETDEWEB)

    David Holloway

    2005-09-30

    Beginning the fall semester of 1999, The University of Maryland, Departments of Mechanical and Electrical Engineering and the Institute for Systems Research served as a U.S. Department of Energy (USDOE) Graduate Automotive Technology Education (GATE) Center for Hybrid Electric Drivetrains and Control Strategies. A key goal was to produce a graduate level education program that educated and prepared students to address the technical challenges of designing and developing hybrid electric vehicles, as they progressed into the workforce. A second goal was to produce research that fostered the advancement of hybrid electric vehicles, their controls, and other related automotive technologies. Participation ended at the University of Maryland after the 2004 fall semester. Four graduate courses were developed and taught during the course of this time, two of which evolved into annually-taught undergraduate courses, namely Vehicle Dynamics and Control Systems Laboratory. Five faculty members from Mechanical Engineering, Electrical Engineering, and the Institute for Systems Research participated. Four Ph.D. degrees (two directly supported and two indirectly supported) and seven Master's degrees in Mechanical Engineering resulted from the research conducted. Research topics included thermoelectric waste heat recovery, fuel cell modeling, pre- and post-transmission hybrid powertrain control and integration, hybrid transmission design, H{sub 2}-doped combustion, and vehicle dynamics. Many of the participating students accepted positions in the automotive industry or government laboratories involved in automotive technology work after graduation. This report discusses the participating faculty, the courses developed and taught, research conducted, the students directly and indirectly supported, and the publication list. Based on this collection of information, the University of Maryland firmly believes that the key goal of the program was met and that the majority of the

  9. Dielectric property determination of hybrid Al2O3-filled MWCNT buckypaper by the rectangular cavity perturbation technique

    Science.gov (United States)

    Miao, Hsin-Yuan; Liu, Jih-Hsin; Saravanan, L.; Tsao, Che-Wei; Pan, Jui-Wen

    2015-04-01

    This study investigated the complex dielectric permittivity of freestanding multiwalled carbon nanotube buckypaper (MWCNT-BP) and a synthesized hybrid alumina-filled buckypaper (Al2O3-BP) composite with different alumina loadings (5-30 wt%). The non-destructive microwave transmission technique for complex permittivity determination involving cavity perturbation was employed to characterize a set of Al2O3-BP sheets. This was done by filling a rectangular cavity resonator with a standard dielectric Teflon sample and then performing permittivity measurements for the buckypaper (BP) samples in the X-band frequency range (7-12 GHz). Field-emission scanning electron microscopy (FESEM) was used to analyze the morphology of the MWCNT-BP and the alumina-loaded BP composites. DC electrical resistivity measurements clearly demonstrated conductor-insulator transition. The effect of alumina loadings on the dielectric properties of the synthesized hybrid Al2O3-BP sheet is discussed.

  10. Semiconductor/Piezoelectrics Hybrid Heterostructures with Highly Effective Gate-Tunable Electrotransport and Magnetic Behaviors.

    Science.gov (United States)

    Chen, Lei; Zhao, Wei-Yao; Wang, Jing; Gao, Guan-Yin; Zhang, Jin-Xing; Wang, Yu; Li, Xiao-Min; Cao, Shi-Xun; Li, Xiao-Guang; Luo, Hao-Su; Zheng, Ren-Kui

    2016-10-12

    We report the epitaxial growth of oxygen deficient titanium dioxide thin films on 0.7Pb(Mg1/3Nb2/3)O3-0.3PbTiO3 (PMN-PT) single crystals and realized highly effective in situ electrostatic manipulation of electrotransport and magnetism of TiO2-δ films via gate voltages. Upon the polarization switching in the PMN-PT, the carrier density of the TiO2-δ film could be reversibly modified, resulting in a large nonvolatile resistivity modulation by ∼51% at T = 300 K, approximately 4-12 times larger than that of other transition-metal oxide film/PMN-PT structures. By taking advantage of in situ manipulation of the carrier density via gate voltages, we found that competition between the trap of electrons by the Ti(3+)-VO pairs and that by the positive polarization charges at the interface results in a significant resistivity relaxation upon the polarization switching, and revealed that magnetization is inversely correlated with the carrier density of the TiO2-δ film. Such hybrid structures combining materials with dissimilar functionalities may have potential applications in multifunctional devices which can take advantage of the useful and unique properties of both materials.

  11. Hybrid semiconductor-dielectric metamaterial modulation for switchable bi-directional THz absorbers

    Science.gov (United States)

    Le, Ly Nguyen; Thang, Nguyen Manh; Thuy, Le Minh; Tung, Nguyen Thanh

    2017-01-01

    There is an increasing interest for electromagnetic metamaterials that show mutable absorption properties with real-time and dynamic control. In this paper, we investigate a modulation of bi-directional metamaterial absorbers that is thermally switchable at terahertz frequencies. The metamaterial absorber is composed of symmetric hybrid semiconductor-dielectric cut-wire-pair structures, whose electromagnetic responses can be actively manipulated by utilizing an external heat source. As increasing the temperature of metamaterials from 300 to 350 K, we demonstrate that the magnetic resonance can be systematically blue-shifted and overlapped with the electric resonance, which is unaffectedly settled at about 0.8 THz. This superposition provides an effective mechanism to control the absorption intensity from 43% to nearly 95%. Finite integration simulation technique, standard retrieval method, and equivalent circuit model are employed to elaborate our idea.

  12. Hybrid metal-dielectric, slow wave structure with magnetic coupling and compensation

    Energy Technology Data Exchange (ETDEWEB)

    Smirnov, A.V., E-mail: asmirnov@radiabeam.com [RadiaBeam Systems LLC, 1713 Stewart St., Santa Monica, CA 90404 (United States); Savin, E. [RadiaBeam Systems LLC, 1713 Stewart St., Santa Monica, CA 90404 (United States); National Research Nuclear University “MEPhI”, Moscow 115409 (Russian Federation)

    2016-06-01

    A number of electron beam vacuum devices such as small radiofrequency (RF) linear accelerators (linacs) and microwave traveling wave tubes (TWTs) utilize slow wave structures which are usually rather complicated in production and may require multi-step brazing and time consuming tuning. Fabrication of these devices becomes challenging at centimeter wavelengths, at large number of cells, and when a series or mass production of such structures is required. A hybrid, metal-dielectric, periodic structure for low gradient, low beam current applications is introduced here as a modification of Andreev’s disk-and-washer (DaW) structure. Compensated type of coupling between even and odd TE01 modes in the novel structure results in negative group velocity with absolute values as high as 0.1c–0.2c demonstrated in simulations. Sensitivity to material imperfections and electrodynamic parameters of the disk-and-ring (DaR) structure are considered numerically using a single cell model.

  13. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    Science.gov (United States)

    Tsai, Meng-Chen; Lee, Min-Hung; Kuo, Chin-Lung; Lin, Hsin-Chih; Chen, Miin-Jang

    2016-11-01

    Amorphous and crystalline ZrO2 gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (Jg) of ∼7 × 10-4 A/cm2 with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiOxNy in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO2 from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar Jg of ∼1.4 × 10-5 A/cm2 as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO2 gate dielectrics, and the nitrogen incorporation at the top of crystalline ZrO2 is an effective approach to scale the CET and Jg, as well as to improve the reliability.

  14. Effect of gate-dielectrics on the electrical characteristics of solution-processed single-wall-carbon-nanotube thin-film transistors

    Science.gov (United States)

    Ha, Tae-Jun

    2017-02-01

    High performance of solution-processed, single-wall-carbon-nanotube (SWCNT) thin-film transistors (TFTs) is investigated through the use in the different gate-dielectrics of silicon dioxide (SiO2), silicon nitride (SiNx), the bilayers of SiO2 and SiNx, and hexagonal boron-nitride (h-BN) thin films. The different interfacial characteristics affect the electrical characteristics of the SWCNT-TFTs including key device metrics. Significantly, the hysteresis window that is normally observed in drop-casted SWCNT-TFTs was majorly suppressed by the employment of a thin lower dielectric-constant material on a higher dielectricconstant material. Sub-2V operating SWCNT-TFTs with solution-processed h-BN gate dielectrics with good above- and sub-threshold characteristics are also investigated on the basis of interfacial characteristics underlying the device physics. Such performance can be realized by the suppressed interfacial impurity scattering through the chemically clean interface combined with optimized solution-process below 100 °C. [Figure not available: see fulltext.

  15. Effects of Y incorporation in TaON gate dielectric on electrical performance of GaAs metal-oxide-semiconductor capacitor

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Li Ning; Choi, Hoi Wai; Lai, Pui To [Department of Electrical and Electronic Engineering, The University of Hong Kong (China); Xu, Jing Ping [School of Optical and Electronic Information, Huazhong University of Science and Technology, Wuhan (China)

    2016-09-15

    In this study, GaAs metal-oxide-semiconductor (MOS) capacitors using Y-incorporated TaON as gate dielectric have been investigated. Experimental results show that the sample with a Y/(Y + Ta) atomic ratio of 27.6% exhibits the best device characteristics: high k value (22.9), low interfacestate density (9.0 x 10{sup 11} cm{sup -2} eV{sup -1}), small flatband voltage (1.05 V), small frequency dispersion and low gate leakage current (1.3 x 10{sup -5}A/cm{sup 2} at V{sub fb} + 1 V). These merits should be attributed to the complementary properties of Y{sub 2}O{sub 3} and Ta{sub 2}O{sub 5}:Y can effectively passivate the large amount of oxygen vacancies in Ta{sub 2}O{sub 5}, while the positively-charged oxygen vacancies in Ta{sub 2}O{sub 5} are capable of neutralizing the effects of the negative oxide charges in Y{sub 2}O{sub 3}. This work demonstrates that an appropriate doping of Y content in TaON gate dielectric can effectively improve the electrical performance for GaAs MOS devices. (copyright 2016 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  16. Novel high dielectric constant hybrid elastomers based on glycerol-insilicone emulsions

    DEFF Research Database (Denmark)

    Mazurek, Piotr Stanislaw; Skov, Anne Ladegaard

    2016-01-01

    distributed within PDMS in shape of discrete droplets thus acting as a high dielectric constant filler efficiently enhancing the dielectric constant of the composites. Low- and high-voltage dielectric spectroscopy measurements were conducted in order to verify applicability of the composites as dielectric...

  17. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Energy Technology Data Exchange (ETDEWEB)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A., E-mail: steven.vitale@ll.mit.edu [Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, Massachusetts 02420 (United States)

    2015-07-28

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  18. Comparison of gate dielectric plasma damage from plasma-enhanced atomic layer deposited and magnetron sputtered TiN metal gates

    Science.gov (United States)

    Brennan, Christopher J.; Neumann, Christopher M.; Vitale, Steven A.

    2015-07-01

    Fully depleted silicon-on-insulator transistors were fabricated using two different metal gate deposition mechanisms to compare plasma damage effects on gate oxide quality. Devices fabricated with both plasma-enhanced atomic-layer-deposited (PE-ALD) TiN gates and magnetron plasma sputtered TiN gates showed very good electrostatics and short-channel characteristics. However, the gate oxide quality was markedly better for PE-ALD TiN. A significant reduction in interface state density was inferred from capacitance-voltage measurements as well as a 1200× reduction in gate leakage current. A high-power magnetron plasma source produces a much higher energetic ion and vacuum ultra-violet (VUV) photon flux to the wafer compared to a low-power inductively coupled PE-ALD source. The ion and VUV photons produce defect states in the bulk of the gate oxide as well as at the oxide-silicon interface, causing higher leakage and potential reliability degradation.

  19. Detection of a magnetic bead by hybrid nanodevices using scanning gate microscopy

    Directory of Open Access Journals (Sweden)

    H. Corte-León

    2016-05-01

    Full Text Available Hybrid ferromagnetic(Py/non-magnetic metal(Au junctions with a width of 400 nm are studied by magnetotransport measurements, magnetic scanning gate microscopy (SGM with a magnetic bead (MB attached to the probe, and micromagnetic simulations. In the transverse geometry, the devices demonstrate a characteristic magnetoresistive behavior that depends on the direction of the in plane magnetic field, with minimum/maximum variation when the field is applied parallel/perpendicular to the Py wire. The SGM is performed with a NdFeB bead of 1.6 μm diameter attached to the scanning probe. Our results demonstrate that the hybrid junction can be used to detect this type of MB. A rough approximation of the sensing volume of the junction has the shape of elliptical cylinder with the volume of ∼1.51 μm3. Micromagnetic simulations coupled to a magnetotransport model including anisotropic magnetoresistance and planar Hall effects are in good agreement with the experimental findings, enabling the interpretation of the SGM images.

  20. Detection of a magnetic bead by hybrid nanodevices using scanning gate microscopy

    Science.gov (United States)

    Corte-León, H.; Krzysteczko, P.; Marchi, F.; Motte, J.-F.; Manzin, A.; Schumacher, H. W.; Antonov, V.; Kazakova, O.

    2016-05-01

    Hybrid ferromagnetic(Py)/non-magnetic metal(Au) junctions with a width of 400 nm are studied by magnetotransport measurements, magnetic scanning gate microscopy (SGM) with a magnetic bead (MB) attached to the probe, and micromagnetic simulations. In the transverse geometry, the devices demonstrate a characteristic magnetoresistive behavior that depends on the direction of the in plane magnetic field, with minimum/maximum variation when the field is applied parallel/perpendicular to the Py wire. The SGM is performed with a NdFeB bead of 1.6 μm diameter attached to the scanning probe. Our results demonstrate that the hybrid junction can be used to detect this type of MB. A rough approximation of the sensing volume of the junction has the shape of elliptical cylinder with the volume of ˜1.51 μm3. Micromagnetic simulations coupled to a magnetotransport model including anisotropic magnetoresistance and planar Hall effects are in good agreement with the experimental findings, enabling the interpretation of the SGM images.

  1. High temperature (1000 °C) compatible Y-La-Si-O silicate gate dielectric in direct contact with Si with 7.7 A˚ equivalent oxide thickness

    Science.gov (United States)

    Dubourdieu, C.; Cartier, E.; Bruley, J.; Hopstaken, M.; Frank, M. M.; Narayanan, V.

    2011-06-01

    Yttrium lanthanum silicate was formed in direct contact with silicon after a rapid thermal annealing at 1000 °C in metal-oxide-semiconductor capacitors leading to an equivalent oxide thickness (EOT) of 7.7 Å. This represents one of the lowest EOT value reported for a gate-first process with non Hf-based dielectric. The silicate is formed by interdiffusion of La2O3 and YOx layers and interfacial SiO2 consumption. Yttrium incorporation reduces the leakage current density as well as the large negative flatband voltage (Vfb) shift that is associated with lanthanide-based dielectrics. The Vfb value can be appropriately tuned for n-type field-effect transistor operation by changing the silicate composition.

  2. High-temperature studies of multiple fluorinated traps within an Al2O3 gate dielectric for E-Mode AlGaN/GaN power MIS-HEMTs

    Science.gov (United States)

    Wang, Yun-Hsiang; Liang, Yung C.; Samudra, Ganesh S.; Chu, Po-Ju; Liao, Ya-Chu; Huang, Chih-Fang; Kuo, Wei-Hung; Lo, Guo-Qiang

    2016-02-01

    Normally-off AlGaN/GaN MIS-HEMT devices with multiple fluorinated ALD-Al2O3 layers as the gate dielectric have been reported to achieve a high threshold voltage for normally-off operations with satisfactory performance for both on and off states at room temperature. However, a large swing in gate threshold voltage is found when devices operate at elevated temperatures. Hence, further study of the gate dielectric on the distribution of fluorinated trap states in the energy band are required to assess the gate function at higher temperatures. Through the use of the charge analytical model and Poole-Frenkel trap emission theory, the gate voltage stressing measurement was carried out to accurately find the effective trap state distribution within the Al2O3 energy bandgap created by fluorinated treatments. For the samples fabricated and used in the investigation, we found that a higher population of fluorinated trap states located deeper than 1.1 eV corresponding to emission levels above 200 °C would allow more trapped charges to remain in the dielectric at high temperature for better threshold voltage retention. We also discovered that a higher fluorine treatment power on the gate dielectric could yield a higher trap state density at deeper levels, resulting in better temperature stability.

  3. Improved thermal stability and electrical properties of atomic layer deposited HfO{sub 2}/AlN high-k gate dielectric stacks on GaAs

    Energy Technology Data Exchange (ETDEWEB)

    Cao, Yan-Qiang; Li, Xin; Zhu, Lin; Cao, Zheng-Yi; Wu, Di; Li, Ai-Dong, E-mail: adli@nju.edu.cn [National Laboratory of Solid State Microstructures and Department of Materials Science and Engineering, College of Engineering and Applied sciences, Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2015-01-15

    The thermal stability and electrical properties of atomic layer deposited HfO{sub 2}/AlN high-k gate dielectric stacks on GaAs were investigated. Compared to HfO{sub 2}/Al{sub 2}O{sub 3} gate dielectric, significant improvements in interfacial quality as well as electrical characteristics after postdeposition annealing are confirmed by constructing HfO{sub 2}/AlN dielectric stacks. The chemical states were carefully explored by the x-ray photoelectron spectroscopy, which indicates the AlN layers effectively prevent from the formation of defective native oxides at elevated temperatures. In addition, it is found that NH{sub 3} plasma during AlN plasma-enhanced atomic layer deposition also has the self-cleaning effect as Al(CH{sub 3}){sub 3} in removing native oxides. The passivating AlN layers suppress the formation of interfacial oxide and trap charge, leading to the decrease of capacitance equivalent thickness after annealing. Moreover, HfO{sub 2}/AlN/GaAs sample has a much lower leakage current density of 2.23 × 10{sup −4} A/cm{sup 2} than HfO{sub 2}/Al{sub 2}O{sub 3}/GaAs sample of 2.58 × 10{sup −2} A/cm{sup 2}. For the HfO{sub 2}/AlN/GaAs sample annealed at 500 °C, it has a lowest interface trap density value of 2.11 × 10{sup 11} eV{sup −1} cm{sup −2}. These results indicate that adopting HfO{sub 2}/AlN dielectric stacks may be a promising approach for the realization of high quality GaAs-based transistor devices.

  4. Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-/metal gate last process

    Institute of Scientific and Technical Information of China (English)

    王艳蓉; 朱慧珑; 赵超; 陈大鹏; 叶甜春; 杨红; 徐昊; 王晓磊; 罗维春; 祁路伟; 张淑祥; 王文武; 闫江

    2015-01-01

    A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the depo-sition/annealing (D&A) cycles, the D&A time, and the total annealing time. The results show that the increases of the number of D&A cycles (from 1 to 2) and D&A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D&A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 ˚A and the TTF of PMOS worsen. Moreover, different D&A times and numbers of D&A cycles induce different breakdown mechanisms.

  5. Anticrossing double Fano resonances generated in metallic/dielectric hybrid nanostructures using nonradiative anapole modes for enhanced nonlinear optical effects.

    Science.gov (United States)

    Zhai, Wu-Chao; Qiao, Tie-Zhu; Cai, Dong-Jin; Wang, Wen-Jie; Chen, Jing-Dong; Chen, Zhi-Hui; Liu, Shao-Ding

    2016-11-28

    Third-harmonic generation with metallic or dielectric nanoparticles often suffer from, respectively, small modal volumes and weak near-field enhancements. This study propose and demonstrate that a metallic/dielectric hybrid nanostructure composed of a silver double rectangular nanoring and a silicon square nanoplate can be used to overcome these obstacles for enhanced third-harmonic generation. It is shown that the nonradiative anapole mode of the Si plate can be used as a localized source to excite the dark subradiant octupole mode of the Ag ring, and the mode hybridization leads to the formation of an antibonding and a bonding subradiant collective mode, thereby forming anticrossing double Fano resonances. With the strong coupling between individual particles and the effectively suppressed radiative losses of the Fano resonances, several strong hot spots are generated around the Ag ring due to the excitation of the octupole mode, and electromagnetic fields within the Si plate are also strongly amplified, making it possible to confine more incident energy inside the dielectric nanoparticle. Calculation results reveal that the confined energy inside the Si plate and the Ag ring for the hybrid structures can be about, respectively, more than three times and four orders stronger than that of the corresponding isolated nanoparticles, which makes the designed hybrid nanostructure a promising platform for enhanced third-harmonic generation.

  6. Hybrid metal-dielectric ring resonators for homogenizable optical metamaterials with strong magnetic response at short wavelengths down to the ultraviolet range.

    Science.gov (United States)

    Tang, Jianwei; He, Sailing

    2013-10-07

    We derive an analytical LC model from Maxwell's equations for the magnetic resonance of subwavelength ring resonators. Using the LC model, we revisit the scaling of split-ring resonators. Inspired by the LC model, we propose a hybrid metal-dielectric ring resonator mainly composed of high index dielectric material (e.g., TiO₂) with some gaps filled with metal (e.g., Ag). The saturation frequency of magnetic response for the hybrid metal-dielectric ring resonator is much higher (up to the ultraviolet range) than that for split-ring resonators, and can be controlled by the metal fraction in the ring. The hybrid metal-dielectric ring resonator can also overcome the homogenization problem of all-dielectric magnetic resonators, and therefore can form homogenizable magnetic metamaterials at short wavelengths down to the ultraviolet range.

  7. Depletion-mode In 0.2Ga 0.8As/GaAs MOSFET with molecular beam epitaxy grown Al 2O 3/Ga 2O 3(Gd 2O 3) as gate dielectrics

    Science.gov (United States)

    Lin, C. A.; Lin, T. D.; Chiang, T. H.; Chiu, H. C.; Chang, P.; Hong, M.; Kwo, J.

    2009-03-01

    Depletion-mode In 0.2Ga 0.8As/GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated with molecular beam epitaxy (MBE) grown Al 2O 3/Ga 2O 3(Gd 2O 3) as the gate dielectric in two comparable processes. In the "metal-gate-last" process, a 12 μm gate-length depletion-mode n-channel InGaAs/GaAs MOSFET with a Ga 2O 3(Gd 2O 3) gate oxide 6 nm thick shows an accumulated drain current density of 135 mA/mm at Vg=2 V. In the other process of "metal-gate-first" process, the device with same gate dielectric, channel, and gate length exhibits a larger drain current density of 175 mA/mm at the same gate bias. In addition, there is a broader transfer characteristics and higher extrinsic peak transconductance of 48 mS/mm in the metal-gate-first process. MOS capacitors from both processes have exhibited excellent capacitance-voltage ( C- V) characteristics with minor dispersion, negligible hysteresis, and κ values of 13.7-13.9 in Ga 2O 3(Gd 2O 3).

  8. Multi-hybrid method for investigation of EM scattering from inhomogeneous object above a dielectric rough surface

    Science.gov (United States)

    Li, Jie; Guo, LiXin; He, Qiong; Wei, Bing

    2012-10-01

    An iterative strategy combining Kirchhoff approximation^(KA) with the hybrid finite element-boundary integral (FE-BI) method is presented in this paper to study the interactions between the inhomogeneous object and the underlying rough surface. KA is applied to study scattering from underlying rough surfaces, whereas FE-BI deals with scattering from the above target. Both two methods use updated excitation sources. Huygens equivalence principle and an iterative strategy are employed to consider the multi-scattering effects. This hybrid FE-BI-KA scheme is an improved and generalized version of previous hybrid Kirchhoff approximation-method of moments (KA-MoM). This newly presented hybrid method has the following advantages: (1) the feasibility of modeling multi-scale scattering problems (large scale underlying surface and small scale target); (2) low memory requirement as in hybrid KA-MoM; (3) the ability to deal with scattering from inhomogeneous (including coated or layered) scatterers above rough surfaces. The numerical results are given to evaluate the accuracy of the multi-hybrid technique; the computing time and memory requirements consumed in specific numerical simulation of FE-BI-KA are compared with those of MoM. The convergence performance is analyzed by studying the iteration number variation caused by related parameters. Then bistatic scattering from inhomogeneous object of different configurations above dielectric Gaussian rough surface is calculated and the influences of dielectric compositions and surface roughness on the scattering pattern are discussed.

  9. Amorphous indium-gallium-zinc-oxide thin-film transistors using organic-inorganic hybrid films deposited by low-temperature plasma-enhanced chemical vapor deposition for all dielectric layers

    Science.gov (United States)

    Hsu, Chao-Jui; Chang, Ching-Hsiang; Chang, Kuei-Ming; Wu, Chung-Chih

    2017-01-01

    We investigated the deposition of high-performance organic-inorganic hybrid dielectric films by low-temperature (close to room temperature) inductively coupled plasma chemical vapor deposition (ICP-CVD) with hexamethyldisiloxane (HMDSO)/O2 precursor gas. The hybrid films exhibited low leakage currents and high breakdown fields, suitable for thin-film transistor (TFT) applications. They were successfully integrated into the gate insulator, the etch-stop layer, and the passivation layer for bottom-gate staggered amorphous In-Ga-Zn-O (a-IGZO) TFTs having the etch-stop configuration. With the double-active-layer configuration having a buffer a-IGZO back-channel layer grown in oxygen-rich atmosphere for better immunity against plasma damage, the etch-stop-type bottom-gate staggered a-IGZO TFTs with good TFT characteristics were successfully demonstrated. The TFTs showed good field-effect mobility (μFE), threshold voltage (V th), subthreshold swing (SS), and on/off ratio (I on/off) of 7.5 cm2 V-1 s-1, 2.38 V, 0.38 V/decade, and 2.2 × 108, respectively, manifesting their usefulness for a-IGZO TFTs.

  10. Parametric study of dielectric loaded surface plasmon polariton add-drop filters for hybrid silicon/plasmonic optical circuitry

    Science.gov (United States)

    Dereux, A.; Hassan, K.; Weeber, J.-C.; Djellali, N.; Bozhevolnyi, S. I.; Tsilipakos, O.; Pitilakis, A.; Kriezis, E.; Papaioannou, S.; Vyrsokinos, K.; Pleros, N.; Tekin, T.; Baus, M.; Kalavrouziotis, D.; Giannoulis, G.; Avramopoulos, H.

    2011-01-01

    Surface plasmons polaritons are electromagnetic waves propagating along the surface of a conductor. Surface plasmons photonics is a promising candidate to satisfy the constraints of miniaturization of optical interconnects. This contribution reviews an experimental parametric study of dielectric loaded surface plasmon waveguides ring resonators and add-drop filters within the perspective of the recently suggested hybrid technology merging plasmonic and silicon photonics on a single board (European FP7 project PLATON "Merging Plasmonic and Silicon Photonics Technology towards Tb/s routing in optical interconnects"). Conclusions relevant for dielectric loaded surface plasmon switches to be integrated in silicon photonic circuitry will be drawn. They rely on the opportunity offered by plasmonic circuitry to carry optical signals and electric currents through the same thin metal circuitry. The heating of the dielectric loading by the electric current enables to design low foot-print thermo-optical switches driving the optical signal flow.

  11. 2D-ordered dielectric sub-micron bowls on a metal surface: a useful hybrid plasmonic-photonic structure

    Science.gov (United States)

    Lan, Yue; Wang, Shiqiang; Yin, Xianpeng; Liang, Yun; Dong, Hao; Gao, Ning; Li, Jian; Wang, Hui; Li, Guangtao

    2016-07-01

    Recently, it has been demonstrated that the combination of periodic dielectric structures with metallic structures provides an efficient means to yield a synergetic optical response or functionality in the resultant hybrid plasmonic-photonic systems. In this work, a new hybrid plasmonic-photonic structure of 2D-ordered dielectric sub-micron bowls on a flat gold surface was proposed, prepared, and theoretically and experimentally characterized. This hybrid structure supports two types of modes: surface plasmon polaritons bound at the metallic surface and waveguided mode of light confined in the cavity of bowls. Optical responses of this hybrid structure as well as the spatial electric field distribution of each mode are found to be strongly dependent on the structural parameters of this system, and thus could be widely modified on demand. Importantly, compared to the widely studied hybrid systems, namely the flat metallic surface coated with a monolayer array of latex spheres, the waveguided mode with strong field enhancement appearing in the cavities of bowls is more facilely accessible and thus suitable for practical use. For demonstration, a 2D-ordered silica sub-micron bowl array deposited on a flat gold surface was fabricated and used as a regenerable platform for fluorescence enhancement by simply accommodating emitters in bowls. All the simulation and experiment results indicate that the 2D-ordered dielectric sub-micron bowls on a metal surface should be a useful hybrid plasmonic-photonic system with great potential for applications such as sensors or tunable emitting devices if appropriate periods and materials are employed.Recently, it has been demonstrated that the combination of periodic dielectric structures with metallic structures provides an efficient means to yield a synergetic optical response or functionality in the resultant hybrid plasmonic-photonic systems. In this work, a new hybrid plasmonic-photonic structure of 2D-ordered dielectric sub

  12. Solid-State Densification of Spun-Cast Self-Assembled Monolayers for Use in Ultra-Thin Hybrid Dielectrics.

    Science.gov (United States)

    Hutchins, Daniel O; Acton, Orb; Weidner, Tobias; Cernetic, Nathan; Baio, Joe E; Castner, David G; Ma, Hong; Jen, Alex K-Y

    2012-11-15

    Ultra-thin self-assembled monolayer (SAM)-oxide hybrid dielectrics have gained significant interest for their application in low-voltage organic thin film transistors (OTFTs). A [8-(11-phenoxy-undecyloxy)-octyl]phosphonic acid (PhO-19-PA) SAM on ultrathin AlOx (2.5 nm) has been developed to significantly enhance the dielectric performance of inorganic oxides through reduction of leakage current while maintaining similar capacitance to the underlying oxide structure. Rapid processing of this SAM in ambient conditions is achieved by spin coating, however, as-cast monolayer density is not sufficient for dielectric applications. Thermal annealing of a bulk spun-cast PhO-19-PA molecular film is explored as a mechanism for SAM densification. SAM density, or surface coverage, and order are examined as a function of annealing temperature. These SAM characteristics are probed through atomic force microscopy (AFM), X-ray photoelectron spectroscopy (XPS), and near edge X-ray absorption fine structure spectroscopy (NEXAFS). It is found that at temperatures sufficient to melt the as-cast bulk molecular film, SAM densification is achieved; leading to a rapid processing technique for high performance SAM-oxide hybrid dielectric systems utilizing a single wet processing step. To demonstrate low-voltage devices based on this hybrid dielectric (with leakage current density of 7.7×10(-8) A cm(-2) and capacitance density of 0.62 µF cm(-2) at 3 V), pentacene thin-film transistors (OTFTs) are fabricated and yield sub 2 V operation and charge carrier mobilites of up to 1.1 cm(2) V(-1) s(-1).

  13. 2D-ordered dielectric sub-micron bowls on a metal surface: a useful hybrid plasmonic-photonic structure.

    Science.gov (United States)

    Lan, Yue; Wang, Shiqiang; Yin, Xianpeng; Liang, Yun; Dong, Hao; Gao, Ning; Li, Jian; Wang, Hui; Li, Guangtao

    2016-07-21

    Recently, it has been demonstrated that the combination of periodic dielectric structures with metallic structures provides an efficient means to yield a synergetic optical response or functionality in the resultant hybrid plasmonic-photonic systems. In this work, a new hybrid plasmonic-photonic structure of 2D-ordered dielectric sub-micron bowls on a flat gold surface was proposed, prepared, and theoretically and experimentally characterized. This hybrid structure supports two types of modes: surface plasmon polaritons bound at the metallic surface and waveguided mode of light confined in the cavity of bowls. Optical responses of this hybrid structure as well as the spatial electric field distribution of each mode are found to be strongly dependent on the structural parameters of this system, and thus could be widely modified on demand. Importantly, compared to the widely studied hybrid systems, namely the flat metallic surface coated with a monolayer array of latex spheres, the waveguided mode with strong field enhancement appearing in the cavities of bowls is more facilely accessible and thus suitable for practical use. For demonstration, a 2D-ordered silica sub-micron bowl array deposited on a flat gold surface was fabricated and used as a regenerable platform for fluorescence enhancement by simply accommodating emitters in bowls. All the simulation and experiment results indicate that the 2D-ordered dielectric sub-micron bowls on a metal surface should be a useful hybrid plasmonic-photonic system with great potential for applications such as sensors or tunable emitting devices if appropriate periods and materials are employed.

  14. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11,000 cm(2)/V·s.

    Science.gov (United States)

    Smith, Casey; Qaisi, Ramy; Liu, Zhihong; Yu, Qingkai; Hussain, Muhammad Mustafa

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11,000 cm(2)/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low tox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance.

  15. Low-voltage back-gated atmospheric pressure chemical vapor deposition based graphene-striped channel transistor with high-κ dielectric showing room-temperature mobility > 11 000 cm2/V·s

    KAUST Repository

    Smith, Casey

    2013-07-23

    Utilization of graphene may help realize innovative low-power replacements for III-V materials based high electron mobility transistors while extending operational frequencies closer to the THz regime for superior wireless communications, imaging, and other novel applications. Device architectures explored to date suffer a fundamental performance roadblock due to lack of compatible deposition techniques for nanometer-scale dielectrics required to efficiently modulate graphene transconductance (gm) while maintaining low gate capacitance-voltage product (CgsVgs). Here we show integration of a scaled (10 nm) high-κ gate dielectric aluminum oxide (Al2O3) with an atmospheric pressure chemical vapor deposition (APCVD)-derived graphene channel composed of multiple 0.25 μm stripes to repeatedly realize room-temperature mobility of 11 000 cm 2/V·s or higher. This high performance is attributed to the APCVD graphene growth quality, excellent interfacial properties of the gate dielectric, conductivity enhancement in the graphene stripes due to low t ox/Wgraphene ratio, and scaled high-κ dielectric gate modulation of carrier density allowing full actuation of the device with only ±1 V applied bias. The superior drive current and conductance at Vdd = 1 V compared to other top-gated devices requiring undesirable seed (such as aluminum and poly vinyl alcohol)-assisted dielectric deposition, bottom gate devices requiring excessive gate voltage for actuation, or monolithic (nonstriped) channels suggest that this facile transistor structure provides critical insight toward future device design and process integration to maximize CVD-based graphene transistor performance. © 2013 American Chemical Society.

  16. Enhanced dielectric properties of poly(vinylidene fluoride) composites filled with nano iron oxide-deposited barium titanate hybrid particles

    Science.gov (United States)

    Zhang, Changhai; Chi, Qingguo; Dong, Jiufeng; Cui, Yang; Wang, Xuan; Liu, Lizhu; Lei, Qingquan

    2016-09-01

    We report enhancement of the dielectric permittivity of poly(vinylidene fluoride) (PVDF) generated by depositing magnetic iron oxide (Fe3O4) nanoparticles on the surface of barium titanate (BT) to fabricate BT–Fe3O4/PVDF composites. This process introduced an external magnetic field and the influences of external magnetic field on dielectric properties of composites were investigated systematically. The composites subjected to magnetic field treatment for 30 min at 60 °C exhibited the largest dielectric permittivity (385 at 100 Hz) when the BT–Fe3O4 concentration is approximately 33 vol.%. The BT–Fe3O4 suppressed the formation of a conducting path in the composite and induced low dielectric loss (0.3) and low conductivity (4.12 × 10‑9 S/cm) in the composite. Series-parallel model suggested that the enhanced dielectric permittivity of BT–Fe3O4/PVDF composites should arise from the ultrahigh permittivity of BT–Fe3O4 hybrid particles. However, the experimental results of the BT–Fe3O4/PVDF composites treated by magnetic field agree with percolation theory, which indicates that the enhanced dielectric properties of the BT–Fe3O4/PVDF composites originate from the interfacial polarization induced by the external magnetic field. This work provides a simple and effective way for preparing nanocomposites with enhanced dielectric properties for use in the electronics industry.

  17. Origin of mobility enhancement by chemical treatment of gate-dielectric surface in organic thin-film transistors: Quantitative analyses of various limiting factors in pentacene thin films

    Science.gov (United States)

    Matsubara, R.; Sakai, Y.; Nomura, T.; Sakai, M.; Kudo, K.; Majima, Y.; Knipp, D.; Nakamura, M.

    2015-11-01

    For the better performance of organic thin-film transistors (TFTs), gate-insulator surface treatments are often applied. However, the origin of mobility increase has not been well understood because mobility-limiting factors have not been compared quantitatively. In this work, we clarify the influence of gate-insulator surface treatments in pentacene thin-film transistors on the limiting factors of mobility, i.e., size of crystal-growth domain, crystallite size, HOMO-band-edge fluctuation, and carrier transport barrier at domain boundary. We quantitatively investigated these factors for pentacene TFTs with bare, hexamethyldisilazane-treated, and polyimide-coated SiO2 layers as gate dielectrics. By applying these surface treatments, size of crystal-growth domain increases but both crystallite size and HOMO-band-edge fluctuation remain unchanged. Analyzing the experimental results, we also show that the barrier height at the boundary between crystal-growth domains is not sensitive to the treatments. The results imply that the essential increase in mobility by these surface treatments is only due to the increase in size of crystal-growth domain or the decrease in the number of energy barriers at domain boundaries in the TFT channel.

  18. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors.

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-12-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade(-1) and 3.62 × 10(11) eV(-1) cm(-2), respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  19. Atomic Layer Deposition of Gallium Oxide Films as Gate Dielectrics in AlGaN/GaN Metal-Oxide-Semiconductor High-Electron-Mobility Transistors

    Science.gov (United States)

    Shih, Huan-Yu; Chu, Fu-Chuan; Das, Atanu; Lee, Chia-Yu; Chen, Ming-Jang; Lin, Ray-Ming

    2016-04-01

    In this study, films of gallium oxide (Ga2O3) were prepared through remote plasma atomic layer deposition (RP-ALD) using triethylgallium and oxygen plasma. The chemical composition and optical properties of the Ga2O3 thin films were investigated; the saturation growth displayed a linear dependence with respect to the number of ALD cycles. These uniform ALD films exhibited excellent uniformity and smooth Ga2O3-GaN interfaces. An ALD Ga2O3 film was then used as the gate dielectric and surface passivation layer in a metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT), which exhibited device performance superior to that of a corresponding conventional Schottky gate HEMT. Under similar bias conditions, the gate leakage currents of the MOS-HEMT were two orders of magnitude lower than those of the conventional HEMT, with the power-added efficiency enhanced by up to 9 %. The subthreshold swing and effective interfacial state density of the MOS-HEMT were 78 mV decade-1 and 3.62 × 1011 eV-1 cm-2, respectively. The direct-current and radio-frequency performances of the MOS-HEMT device were greater than those of the conventional HEMT. In addition, the flicker noise of the MOS-HEMT was lower than that of the conventional HEMT.

  20. Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

    Science.gov (United States)

    Mohanbabu, A.; Mohankumar, N.; Godwin Raj, D.; Sarkar, Partha; Saha, Samar K.

    2017-03-01

    The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

  1. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

    2016-11-30

    Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

  2. Sodium beta-alumina thin films as gate dielectrics for AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors

    Institute of Scientific and Technical Information of China (English)

    Tian Ben-Lang; Chen Chao; Li Yan-Rong; Zhang Wan-Li; Liu Xing-Zhao

    2012-01-01

    Sodium beta-alumina (SBA) is deposited on AlGaN/GaN by using a co-deposition process with sodium and Al2O3 as the precursors.The X-ray diffraction (XRD) spectrum reveals that the deposited thin film is amorphous.The binding energy and composition of the deposited thin film,obtained from the X-ray photoelectron spectroscopy (XPS)measurement,are consistent with those of SBA.The dielectric constant of the SBA thin film is about 50.Each of the capacitance-voltage characteristics obtained at five different frequencies shows a high-quality interface between SBA and A1GaN.The interface trap density of metal-insulator-semiconductor high-electron-mobility transistor (MISHEMT)is measured to be (3.5~9.5)× 1010 cm-2.eV-1 by the conductance method.The fixed charge density of SBA dielectric is on the order of 2.7x1012 cm-2.Compared with the AlGaN/GaN metal semiconductor hetcrostructure high-electron-mobility transistor (MESHEMT),the AlGaN/GaN MISHEMT usually has a threshold voltage that shifts negatively.However,the threshold voltage of the AlGaN/GaN MISHEMT using SBA as the gate dielectric shifts positively from -5.5 V to-3.5 V.From XPS results,the surface valence-band maximum (VBM-EF) of AlGaN is found to decrease from 2.56 eV to 2.25 eV after the SBA thin film deposition.The possible reasons why the threshold voltage of AlGaN/GaN MISHEMT with the SBA gate dielectric shifts positively are the influence of SBA on surface valence-band maximum (VBM-EF),the reduction of interface traps and the effects of sodium ions,and/or the fixed charges in SBA on the two-dimensional electron gas (2DEG).

  3. Environmentally stable flexible metal-insulator-metal capacitors using zirconium-silicate and hafnium-silicate thin film composite materials as gate dielectrics.

    Science.gov (United States)

    Meena, Jagan Singh; Chu, Min-Ching; Wu, Chung-Shu; Ravipati, Srikanth; Ko, Fu-Hsiang

    2011-08-01

    Fully flexible metal-insulator-metal (MIM) capacitors fabricated on 25 microm thin polyimide (PI) substrates via the surface sol-gel process using 10-nm-thick zirconium-silicate (ZrSixOy) and hafnium-silicate (HfSimOn) films as gate dielectrics. The surface morphology of the ZrSixOy and HfSimOn films were investigated using atomic force microscopy and scanning electron microscopy, which confirmed that continuous and crack-free surface growth had occurred on the PI. Both the films treated with oxygen (O2) plasma and annealing (ca. 250 degrees C) consisted of amorphous phase; confirmed by X-ray diffraction. We employed X-ray photoelectron spectroscopy (XPS) at high resolution to examine the chemical composition of the films subjected to various treatment conditions. The shift of the XPS peaks towards higher binding energy revealed the O2 plasma-pretreatment followed by annealing was the most effective process to the surface oxidation at relatively low-temperature, for further passivate the grease traps and making dielectric films thermally stable. The ZrSixOy and HfSimOn films in sandwich-like MIM configuration on the PI substrates exhibited the low leakage current densities of 7.1 x 10(-9) and 8.4 x 10(-9) A/cm2 at applied electric field of 10 MV/cm and maximum capacitance densities of 7.5 and 5.3 fF/microm2 at 1 MHz, respectively. In addition, the ZrSixOy and HfSimOn films in MIM capacitors showed the estimated dielectric constants of 8.2 and 6.0, respectively. Prior to use of flexible MIM capacitors in advanced flexible electronic devices; the reliability test was studied by applying day-dependent leakage current density measurements up to 30 days. These films of silicate-surfactant mesostructured materials have special interest to be used as gate dielectrics in future for flexible metal-oxide-semiconductor devices.

  4. Synthesis of titanium oxide nanoparticles using DNA-complex as template for solution-processable hybrid dielectric composites

    Energy Technology Data Exchange (ETDEWEB)

    Ramos, J.C. [Center for Sustainable Materials Chemistry, 153 Gilbert Hall, Oregon State University, Corvallis, OR (United States); Mejia, I.; Murphy, J.; Quevedo, M. [Department of Materials Science and Engineering, University of Texas at Dallas, Dallas, TX (United States); Garcia, P.; Martinez, C.A. [Engineering and Technology Institute, Autonomous University of Ciudad Juarez, Ciudad Juarez, Chihuahua (Mexico)

    2015-09-15

    Highlights: • We developed a synthesis method to produce TiO{sub 2} nanoparticles using a DNA complex. • The nanoparticles were anatase phase (~6 nm diameter), and stable in alcohols. • Composites showed a k of 13.4, 4.6 times larger than the k of polycarbonate. • Maximum processing temperature was 90 °C. • Low temperature enables their use in low-voltage, low-cost, flexible electronics. - Abstract: We report the synthesis of TiO{sub 2} nanoparticles prepared by the hydrolysis of titanium isopropoxide (TTIP) in the presence of a DNA complex for solution processable dielectric composites. The nanoparticles were incorporated as fillers in polycarbonate at low concentrations (1.5, 5 and 7 wt%) to produce hybrid dielectric films with dielectric constant higher than thermally grown silicon oxide. It was found that the DNA complex plays an important role as capping agent in the formation and suspension stability of nanocrystalline anatase phase TiO{sub 2} at room temperature with uniform size (∼6 nm) and narrow distribution. The effective dielectric constant of spin-cast polycarbonate thin-films increased from 2.84 to 13.43 with the incorporation of TiO{sub 2} nanoparticles into the polymer host. These composites can be solution processed with a maximum temperature of 90 °C and could be potential candidates for its application in low-cost macro-electronics.

  5. Protonic/electronic hybrid oxide transistor gated by chitosan and its full-swing low voltage inverter applications

    Energy Technology Data Exchange (ETDEWEB)

    Chao, Jin Yu [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn; Xiao, Hui [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Yuan, Zhi Guo, E-mail: ncityzg@163.com [Shanxi Province Key Laboratory High Gravity Chemical Engineering, North University of China, Taiyuan 030051 (China)

    2015-12-21

    Modulation of charge carrier density in condensed materials based on ionic/electronic interaction has attracted much attention. Here, protonic/electronic hybrid indium-zinc-oxide (IZO) transistors gated by chitosan based electrolyte were obtained. The chitosan-based electrolyte illustrates a high proton conductivity and an extremely strong proton gating behavior. The transistor illustrates good electrical performances at a low operating voltage of ∼1.0 V such as on/off ratio of ∼3 × 10{sup 7}, subthreshold swing of ∼65 mV/dec, threshold voltage of ∼0.3 V, and mobility of ∼7 cm{sup 2}/V s. Good positive gate bias stress stabilities are obtained. Furthermore, a low voltage driven resistor-loaded inverter was built by using an IZO transistor in series with a load resistor, exhibiting a linear relationship between the voltage gain and the supplied voltage. The inverter is also used for decreasing noises of input signals. The protonic/electronic hybrid IZO transistors have potential applications in biochemical sensors and portable electronics.

  6. Enhanced electrical percolation due to interconnection of three-dimensional pentacene islands in thin films on low surface energy polyimide gate dielectrics.

    Science.gov (United States)

    Yang, Sang Yoon; Shin, Kwonwoo; Kim, Se Hyun; Jeon, Hayoung; Kang, Jin Ho; Yang, Hoichang; Park, Chan Eon

    2006-10-19

    The role of lateral interconnections between three-dimensional pentacene islands on low surface energy polyimide gate dielectrics was investigated by the measurement of the surface coverage dependence of the charge mobility and the use of conducting-probe atomic force microscopy (CP-AFM). From the correlation between the electrical characteristics and the morphological evolution of the three-dimensionally grown pentacene films-based field-effect transistors, we found that during film growth, the formation of interconnections between the three-dimensional pentacene islands that are isolated at the early stage contributes significantly to the enhancement process of charge mobility. The CP-AFM current mapping images of the pentacene films also indicate that the lateral interconnections play an important role in the formation of good electrical percolation pathways between the three-dimensional pentacene islands.

  7. Series resistance effect on time zero dielectrics breakdown characteristics of MOSCAP with ultra-thin EOT high-k/metal gate stacks

    Science.gov (United States)

    Hao, Xu; Hong, Yang; Yanrong, Wang; Wenwu, Wang; Guangxing, Wan; Shangqing, Ren; Weichun, Luo; Luwei, Qi; Chao, Zhao; Dapeng, Chen; Xinyu, Liu; Tianchun, Ye

    2016-05-01

    The time zero dielectric breakdown characteristics of MOSCAP with ultra-thin EOT high-k metal gate stacks are studied. The TZDB results show an abnormal area dependence due to the series resistance effect. The series resistance components extracted from the Fowler-Nordheim tunneling relation are attributed to the spreading resistance due to the asymmetry electrodes. Based on a series model to eliminate the series resistance effect, an area acceleration dependence is obtained by correcting the TZDB results. The area dependence follows Poisson area scaling rules, which indicates that the mechanism of TZDB is the same as TDDB and could be considered as a trap generation process. Project supported by the National High Technology Research and Development Program (863 Program) of China (No. SS2015AA010601), the National Natural Science Foundation of China (Nos. 61176091, 61306129), and the Opening Project of the Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences.

  8. Influence of source and drain contacts on the properties of the indium-zinc oxide thin-film transistors based on anodic aluminum oxide gate dielectrics

    Science.gov (United States)

    Lan, Linfeng; Xu, Miao; Peng, Junbiao; Xu, Hua; Li, Min; Luo, Dongxiang; Zou, Jianhua; Tao, Hong; Wang, Lei; Yao, Rihui

    2011-11-01

    Thin-film transistors (TFTs) based on indium-zinc oxide (IZO) active layer and anodic aluminum oxide (Al2O3) gate dielectric layer were fabricated. The influence of source and drain (S/D) contacts on TFT performance was investigated by comparing IZO-TFTs with different S/D electrodes. The TFT with Mo S/D electrodes had higher output current and lower threshold voltage, but had poorer subthreshold swing and lower effective electron mobility compared to that with ITO S/D electrodes. By using x-ray photoelectron spectroscopy (XPS) depth profile analyzing method, it was observed that Mo was diffusing seriously into IZO, resulting in the variation of the effective channel length, thereby causing serious short-channel effect, poor subshreshold swing, and bad uniformity of the TFTs with Mo S/D electrodes.

  9. Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO{sub 2}/SiO{sub 2} gate dielectric stacks

    Energy Technology Data Exchange (ETDEWEB)

    Taube, Andrzej [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Mroczynski, Robert, E-mail: rmroczyn@elka.pw.edu.pl [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Korwin-Mikke, Katarzyna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Gieraltowska, Sylwia [Institute of Physics, Polish Academy of Sciences, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Szmidt, Jan [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Piotrowska, Anna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland)

    2012-09-01

    In this work, we report on effects of post-deposition annealing on electrical characteristics of metal-insulator-semiconductor (MIS) structures with HfO{sub 2}/SiO{sub 2} double gate dielectric stacks. Obtained results have shown the deterioration of electro-physical properties of MIS structures, e.g. higher interface traps density in the middle of silicon forbidden band (D{sub itmb}), as well as non-uniform distribution and decrease of breakdown voltage (U{sub br}) values, after annealing above 400 Degree-Sign C. Two potential hypothesis of such behavior were proposed: the formation of interfacial layer between hafnia and silicon dioxide and the increase of crystallinity of HfO{sub 2} due to the high temperature treatment. Furthermore, the analysis of conduction mechanisms in investigated stacks revealed Poole-Frenkel (P-F) tunneling at broad range of electric field intensity.

  10. Structure-Triggered High Quantum Yield Luminescence and Switchable Dielectric Properties in Manganese(II) Based Hybrid Compounds.

    Science.gov (United States)

    Wang, Zhong-Xia; Li, Peng-Fei; Liao, Wei-Qiang; Tang, Yuanyuan; Ye, Heng-Yun; Zhang, Yi

    2016-04-01

    Two new manganese(II) based organic-inorganic hybrid compounds, C11H21Cl3MnN2 (1) and C11H22Cl4MnN2 (2), with prominent photoluminescence and dielectric properties were synthesized by solvent modulation. Compound 1 with novel trigonal bipyramidal geometry exhibits bright red luminescence with a lifetime of 2.47 ms and high quantum yield of 35.8 %. Compound 2 with tetrahedral geometry displays intense long-lived (1.54 ms) green light emission with higher quantum yield of 92.3 %, accompanied by reversible solid-state phase transition at 170 K and a distinct switchable dielectric property. The better performance of 2 results from the structure, including a discrete organic cation moiety and inorganic metal anion framework, which gives the cations large freedom of motion.

  11. Thermally Stable Siloxane Hybrid Matrix with Low Dielectric Loss for Copper-Clad Laminates for High-Frequency Applications.

    Science.gov (United States)

    Kim, Yong Ho; Lim, Young-Woo; Kim, Yun Hyeok; Bae, Byeong-Soo

    2016-04-06

    We report vinyl-phenyl siloxane hybrid material (VPH) that can be used as a matrix for copper-clad laminates (CCLs) for high-frequency applications. The CCLs, with a VPH matrix fabricated via radical polymerization of resin blend consisting of sol-gel-derived linear vinyl oligosiloxane and bulky siloxane monomer, phenyltris(trimethylsiloxy)silane, achieve low dielectric constant (Dk) and dissipation factor (Df). The CCLs with the VPH matrix exhibit excellent dielectric performance (Dk = 2.75, Df = 0.0015 at 1 GHz) with stability in wide frequency range (1 MHz to 10 GHz) and at high temperature (up to 275 °C). Also, the VPH shows good flame resistance without any additives. These results suggest the potential of the VPH for use in high-speed IC boards.

  12. Temperature dependent study of Fin-FET drain current through optimization of controlling gate parameters and dielectric material

    Science.gov (United States)

    Das, Rinku Rani; Maity, Santanu; Muchahary, Deboraj; Bhunia, Chandan Tilak

    2017-03-01

    Various limitations, such as gate leakage through hot carrier tunnelling, parasitic resistance and capacitance, Drain Induced Barrier Lowering (DIBL), subthreshold slope (SS), and threshold voltage roll-off are present due to size reduction. Improvements in transistor speed and performance while, reducing the device dimensions is possible using the concept of Multiple-gate Field Effect phenomenon. Temperature dependency in thin fin transistor has been systematically studied with respect to the dependence on the fin width, fin height, and gate length. In this paper the performance of miniaturized Fin-FET structure is optimized. Also, temperature (300K, 400K and 500K) dependent performances on DIBL, SS and threshold voltage are observed and optimized.

  13. Dipole controlled metal gate with hybrid low resistivity cladding for gate-last CMOS with low Vt

    KAUST Repository

    Hinkle, Christopher L.

    2010-06-01

    In this contribution, NMOS and PMOS band edge effective work function (EWF) and correspondingly low Vt are demonstrated using standard fab materials and processes in a gate-last scheme. For NMOS, the use of an Al cladding layer results in Vt = 0.08 V consistent with NMOS EWF = 4.15 eV. Migration of the Al cladding into the TiN and a relatively low oxygen concentration near the TiN/HfO2 interface are responsible for the low EWF. For PMOS, employing a W cladding layer along with a post-TiN anneal in an oxidizing ambient results in elevated oxygen concentration near the TiN/HfO2 interface and Vt = -0.20 V consistent with a PMOS EWF = 5.05 eV. First-principles calculations indicate N atoms displaced from the TiN during the oxidizing anneal form dipoles at the TiN/HfO2 interface that play a critical role in determining the PMOS EWF. © 2010 IEEE.

  14. Low voltage and high ON/OFF ratio field-effect transistors based on CVD MoS2 and ultra high-k gate dielectric PZT.

    Science.gov (United States)

    Zhou, Changjian; Wang, Xinsheng; Raju, Salahuddin; Lin, Ziyuan; Villaroman, Daniel; Huang, Baoling; Chan, Helen Lai-Wa; Chan, Mansun; Chai, Yang

    2015-05-21

    MoS2 and other atomic-level thick layered materials have been shown to have a high potential for outperforming Si transistors at the scaling limit. In this work, we demonstrate a MoS2 transistor with a low voltage and high ON/OFF ratio. A record small equivalent oxide thickness of ∼1.1 nm has been obtained by using ultra high-k gate dielectric Pb(Zr0.52Ti0.48)O3. The low threshold voltage (swing of 85.9 mV dec(-1), the high ON/OFF ratio of ∼10(8) and the negligible hysteresis ensure a high performance of the MoS2 transistor operating at 1 V. The extracted field-effect mobility of 1-10 cm(2) V(-1) s(-1) suggests a high crystalline quality of the CVD-grown MoS2 flakes. The combination of the two-dimensional layered semiconductor and the ultra high-k dielectric may enable the development of low-power electronic applications.

  15. Solution processed self-assembled monolayer gate dielectrics for low-voltage organic transistors. : Section Title: Electric Phenomena

    NARCIS (Netherlands)

    Ball, James; Wobkenberg, Paul H.; Colleaux, Florian; Kooistra, Floris B.; Hummelen, Jan C.; Bradley, Donal D. C.; Anthopoulos, Thomas D.

    2008-01-01

    Low-voltage org. transistors are sought for implementation in high vol. low-power portable electronics of the future. Here we assess the suitability of three phosphonic acid based self-assembling mols. for use as ultra-thin gate dielecs. in low-voltage soln. processable org. field-effect

  16. Design of Highly Efficient Hybrid Si-Au Taper for Dielectric Strip Waveguide to Plasmonic Slot Waveguide Mode Converter

    CERN Document Server

    Chen, Chin-Ta; Hosseini, Amir; Pan, Zeyu; Subbaraman, Harish; Zhang, Xingyu; Chen, Ray T

    2015-01-01

    In this paper, we design a dielectric-to-plasmonic slot waveguide mode converter based on the hybrid silicon-gold taper. The effects of mode matching, the effective index matching, and the metallic absorption loss on the conversion efficiency are studied. Consequently, a metallic taper-funnel coupler with an overall length of 1.7um is designed to achieve a very high conversion efficiency of 93.3% at 1550 nm. The configuration limitations for not allowing this mode converter to achieve a 100% conversion efficiency are also investigated. Such a high-efficiency converter can provide practical routes to realize ultracompact integrated circuits.

  17. Laser ablative decoration of micro-diamonds by gold nanoparticles for fabrication of hybrid plasmonic-dielectric antennae

    Science.gov (United States)

    Ivanova, A. K.; Ionin, A. A.; Khmelnitskii, R. A.; Kudryashov, S. I.; Levchenko, A. O.; Mel'nik, N. N.; Rudenko, A. A.; Saraeva, I. N.; Umanskaya, S. P.; Zayarny, D. A.; Nguyen, L. V.; Nguyen, T. T. H.; Pham, M. H.; Pham, D. V.; Do, T. H.

    2017-06-01

    Hybrid plasmonic-dielectric antennae are fabricated by laser ablation of gold in water sols of micro-diamonds. Electron microscopy and energy-dispersive x-ray spectroscopy of their deposits on a silicon wafer surface indicate close proximity of gold nanoparticles and micro-diamonds, which is supported by photoluminescence studies demonstrating strong (eight-fold) damping of micro-diamond luminescence owing to the attachment of the gold nanoparticles. UV-near-IR spectroscopy of their sols reveals a considerable plasmonic effect, related to red spectral shifts of surface plasmon resonance for the gold nanoparticles in the laser-ablation-fabricated antennae.

  18. High K capacitors and OFET gate dielectrics from self-assembled BaTiO{sub 3} and (Ba,Sr)TiO{sub 3} nanocrystals in the superparaelectric limit

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Limin; O' Brien, Stephen [Department of Chemistry, City University of New York, City College of New York 1131 Marshak Building, New York, NY 10031 (United States); Jia, Zhang; Kymissis, Ioannis [Department of Electrical Engineering, Columbia University New York, NY (United States)

    2010-02-22

    Nanodielectrics is an emerging field with applications in capacitors, gate dielectrics, energy storage, alternatives to Li-ion batteries, and frequency modulation in communications devices. Self-assembly of high k dielectric nanoparticles is a highly attractive means to produce nanostructured films with improved performance - namely dielectric tunability, low leakage, and low loss - as a function of size, composition, and structure. One of the major challenges is conversion of the nanoparticle building block into a reliable thin film device at conditions consistent with integrated device manufacturing or plastic electronics. Here, the development of BaTiO{sub 3} and (Ba,Sr)TiO{sub 3} superparaelectric uniform nanocrystal (8-12 nm) films prepared at room temperature by evaporative driven assembly with no annealing step is reported. Thin film inorganic and polymer composite capacitors show dielectric constants in the tunable range of 10-30, dependent on composition, and are confirmed to be superparaelectric. Organic thin film transistor (TFT) devices on flexible substrates demonstrate the readiness of nanoparticle-assembled films as gate dielectrics in device fabrication. (Abstract Copyright [2010], Wiley Periodicals, Inc.)

  19. Effects of packing materials on the sensitivity of RadFET with HfO2 gate dielectric for electron and photon sources

    Science.gov (United States)

    Kahraman, A.; Yilmaz, E.; Kaya, S.; Aktag, A.

    2015-10-01

    The radiation sensing field effect transistor (RadFET) with SiO2 gate oxide has been commonly used as a device component or dosimetry system in the radiation applications such as space research, radiotherapy, and high-energy physics experiments. However, alternative gate oxides and more suitable packaging materials are still demanded for these dosimeters. HfO2 is one of the most attractive gate oxide materials that are currently under investigation by many researchers. In this study, Monte Carlo simulations of the average deposited energy in RadFET dosimetry systems with different package lid materials for point electron and photon sources were performed with the aim of evaluating the effects of package lids on the sensitivity of the RadFET by using HfO2 as a gate dielectric material. The RadFET geometry was defined in a PENGEOM package and electron-photon transport was simulated by a PENELOPE code. The relatively higher average deposited energies in the sensitive region (HfO2 layer) for electron energies of 250 keV-20 MeV were obtained from the RadFET with the Al2O3 package lid despite of some deviations from the general tendency. For the photon energies of 20-100 keV, the average amount of energy deposited in RadFET with Al2O3 package was higher compared with the other capped devices. The average deposited energy in the sensitive region was quite close to each other at 200 keV for both capped and uncapped devices. The difference in the average deposited energy of the RadFET with different package lid materials was not high for photon energies of 200-1200 keV. The increase in the average deposited energy in the HfO2 layer of the RadFET with Ta package lid was higher compared with the other device configurations above 3 MeV.

  20. Organic/inorganic hybrid synaptic transistors gated by proton conducting methylcellulose films

    Energy Technology Data Exchange (ETDEWEB)

    Wan, Chang Jin; Wan, Qing, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China); Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Zhu, Li Qiang [Ningbo Institute of Material Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China); Wan, Xiang; Shi, Yi, E-mail: wanqing@nju.edu.cn, E-mail: yshi@nju.edu.cn [School of Electronic Science & Engineering, and Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093 (China)

    2016-01-25

    The idea of building a brain-inspired cognitive system has been around for several decades. Recently, electric-double-layer transistors gated by ion conducting electrolytes were reported as the promising candidates for synaptic electronics and neuromorphic system. In this letter, indium-zinc-oxide transistors gated by proton conducting methylcellulose electrolyte films were experimentally demonstrated with synaptic plasticity including paired-pulse facilitation and spatiotemporal-correlated dynamic logic. More importantly, a model based on proton-related electric-double-layer modulation and stretched-exponential decay function was proposed, and the theoretical results are in good agreement with the experimentally measured synaptic behaviors.

  1. Enhanced saturation current sensitivities to charge trapping and illumination in MOS tunnel diode by inserting metal in gate dielectric

    Science.gov (United States)

    Chen, Jun-Yao; Kao, Wei-Chih; Hwu, Jenn-Gwo

    2016-06-01

    The enlarged two-state phenomenon in the current-voltage (I-V) characteristic of metal-oxide-semiconductor (MOS) tunnel diode (TD) after negative/positive constant voltage stress (negative/positive CVS) was investigated. It was found that the reverse saturation tunnel current of MOS TD is proportional to the Schottky barrier height of holes, which is determined by the intensity of fringing field (FF) at device edge. With the aid of high permittivity dielectric and screening effect by embedded metal in the MOS structure, the FF was enhanced, which was confirmed by TCAD simulations. Because of the FF enhancement, after proper electrical treatments of voltage stressing, the intensified quantity of electron trapping/de-trapping was found at device edge, which augmented the modulation of Schottky barrier height of holes. As a result, much variation of reverse saturation tunnel current was exhibited, and hence, the enlarged two-state behavior was achieved. The endurance characteristics were also demonstrated to show that the trapped electrons are more stable in the MOS structure with embedded aluminum. Moreover, benefited from FF enhancement, the enlarged photosensitivity of the I-V characteristics of the sample with high permittivity dielectric and embedded aluminum was obtained. The mechanisms of the enlarged split of current behaviors after suitable CVS and illumination treatments are also discussed for these observations.

  2. Gate tunability and collapse of superconductivity in hybrid tin-graphene Josephson junction arrays

    Science.gov (United States)

    Bouchiat, Vincent

    The accessible and surface-exposed 2D electron gas offered by graphene provides indeed an ideal platform on which to tune, via application of an electrostatic gate, the coupling between adsorbates deposited on its surface. We have experimentally studied the case of graphene transistors which channel is decorated with an array of superconducting tin nanoparticles. They induce via percolation of proximity effect a global 2D superconducting state which critical temperature Tc can be tuned by gate voltage. When the Graphene show strong disorder, it is possible to tune via the applied gate voltage the system towards an insulating state, demonstrating the possibility to trigger a superconducting to insulator transition, which features ressembles those found in granular superconductors. In this work, graphene monolayers are surface-conjugated to regular arrays of superconducting disk-shaped metal islands, whose inter-island distances were patterned to be in the quasi-ballistic limit of the underlying 2D electron gas. Arrays can be made on a large range of geometry and density, up to the highly diluted limit with less than 5% surface coverage and few micrometers in between islands. In the lower temperature limit (graphene sheet. Interestingly, the superconducting state vanishes exponentially in gate voltage and rests in a metallic state, caused by quantum fluctuations of phase is found for diluted and regular arrays. This peculiar behaviour provides evidence for recently developed theory, and may provide a hint to the understanding of long-standing issue of ``zero-temperature'' bosonic metallic state

  3. Investigating compositional effects of atomic layer deposition ternary dielectric Ti-Al-O on metal-insulator-semiconductor heterojunction capacitor structure for gate insulation of InAlN/GaN and AlGaN/GaN

    Energy Technology Data Exchange (ETDEWEB)

    Colon, Albert; Stan, Liliana; Divan, Ralu; Shi, Junxia

    2016-11-01

    Gate insulation/surface passivation in AlGaN/GaN and InAlN/GaN heterojunction field-effect transistors is a major concern for passivation of surface traps and reduction of gate leakage current. However, finding the most appropriate gate dielectric materials is challenging and often involves a compromise of the required properties such as dielectric constant, conduction/valence band-offsets, or thermal stability. Creating a ternary compound such as Ti-Al-O and tailoring its composition may result in a reasonably good gate material in terms of the said properties. To date, there is limited knowledge of the performance of ternary dielectric compounds on AlGaN/GaN and even less on InAlN/GaN. To approach this problem, the authors fabricated metal-insulator-semiconductor heterojunction (MISH) capacitors with ternary dielectrics Ti-Al-O of various compositions, deposited by atomic layer deposition (ALD). The film deposition was achieved by alternating cycles of TiO2 and Al2O3 using different ratios of ALD cycles. TiO2 was also deposited as a reference sample. The electrical characterization of the MISH capacitors shows an overall better performance of ternary compounds compared to the pure TiO2. The gate leakage current density decreases with increasing Al content, being similar to 2-3 orders of magnitude lower for a TiO2:Al2O3 cycle ratio of 2:1. Although the dielectric constant has the highest value of 79 for TiO2 and decreases with increasing the number of Al2O3 cycles, it is maintaining a relatively high value compared to an Al2O3 film. Capacitance voltage sweeps were also measured in order to characterize the interface trap density. A decreasing trend in the interface trap density was found while increasing Al content in the film. In conclusion, our study reveals that the desired high-kappa properties of TiO2 can be adequately maintained while improving other insulator performance factors. The ternary compounds may be an excellent choice as a gate material for both

  4. Local field enhancement on demand based on hybrid plasmonic-dielectric directional coupler.

    Science.gov (United States)

    Adhem, Kholod; Avrutsky, Ivan

    2016-03-21

    The concept of local field enhancement using conductor-gap-dielectric-substrate (CGDS) waveguide structure is proposed. The dispersion equation is derived analytically and solved numerically. The solution of the dispersion equation reveals the anti-crossing behavior of coupled modes. the optimal gap layer thickness and the coupling length of the guided modes are obtained. The mechanism of the CGDS works as follows: Light waves are guided by conventional low-loss dielectric waveguides and, upon demand, they are transformed into highly confined plasmonic modes with strong local field enhancement, and get transformed back into low-loss dielectric modes. As an example, in a representative CGDS structure, the optimal plasmonic gap size is 17 nm, the local light intensity is found to be more than one order of magnitude stronger than the intensity of the dielectric mode at the film surface. The coupling length is only 2.1 μm at a wavelength of 632.8 nm. Such a local field confinement on demand is expected to facilitate efficient light-matter interaction in integrated photonic devices while minimizing losses typical for plasmonic structures.

  5. Modeling and estimation of process-induced stress in the nanowire field-effect-transistors (NW-FETs) on Insulator-on-Silicon substrates with high-k gate-dielectrics

    Science.gov (United States)

    Chatterjee, Sulagna; Chattopadhyay, Sanatan

    2016-10-01

    An analytical model including the simultaneous impact of lattice and thermo-elastic constant mismatch-induced stress in nanowires on Insulator-on-Silicon substrate is developed. It is used to calibrate the finite-element based software, ANSYS, which is subsequently employed to estimate process-induced stress in the sequential steps of NW-FET fabrication. The model considers crystal structures and orientations for both the nanowires and substrates. In-plane stress components along nanowire-axis are estimated for different radii and fractions of insertion. Nature of longitudinal stress is observed to change when inserted fraction of nanowires is changed. Effect of various high-k gate-dielectrics is also investigated. A longitudinal tensile stress of 2.4 GPa and compressive stress of 1.89 GPa have been obtained for NW-FETs with 1/4th and 3/4th insertions with La2O3 and TiO2 as the gate-dielectrics, respectively. Therefore, it is possible to achieve comparable values of electron and hole mobility in NW-FETs by judiciously choosing gate-dielectrics and fractional insertion of the nanowires.

  6. Patchable, flexible heat-sensing hybrid ionic gate nanochannel modified with a wax-composite

    Science.gov (United States)

    Chun, Kyoung-Yong; Choi, Wook; Roh, Sung-Cheoul; Han, Chang-Soo

    2015-07-01

    Heat-driven ionic gate nanochannels have been recently demonstrated, which exploit temperature-responsive polymer brushes based on wettability. These heat-sensing artificial nanochannels operate in a broad temperature-response boundary and fixed liquid cell environment, thereby experiencing limited system operation in the flat and solid state. Here we have developed a patchable and flexible heat-sensing artificial ionic gate nanochannel, which can operate in the range of the human body temperature. A wax-elastic copolymer, coated onto a commercial nanopore membrane by a controlled-vacuum filtration method, was used for the construction of temperature-responsive nanopores. The robust and flexible nanochannel heat sensor, which is combined with an agarose gel electrolyte, can sustain reversible thermo-responsive ionic gating based on the volumetric work of the wax-composite layers in a selective temperature range. The ionic current is also effectively distinguished in the patchable bandage-type nanochannel for human heat-sensing.Heat-driven ionic gate nanochannels have been recently demonstrated, which exploit temperature-responsive polymer brushes based on wettability. These heat-sensing artificial nanochannels operate in a broad temperature-response boundary and fixed liquid cell environment, thereby experiencing limited system operation in the flat and solid state. Here we have developed a patchable and flexible heat-sensing artificial ionic gate nanochannel, which can operate in the range of the human body temperature. A wax-elastic copolymer, coated onto a commercial nanopore membrane by a controlled-vacuum filtration method, was used for the construction of temperature-responsive nanopores. The robust and flexible nanochannel heat sensor, which is combined with an agarose gel electrolyte, can sustain reversible thermo-responsive ionic gating based on the volumetric work of the wax-composite layers in a selective temperature range. The ionic current is also

  7. Effect of reverse body bias on hot-electron-induced punchthrough reliability of pMOSFETs with thin gate dielectric at high temperatures

    Science.gov (United States)

    Kang, YongHa; Kim, JongKyun; Lee, NamHyun; Oh, MinGeon; Hwang, YuChul; Moon, ByungMoo

    2016-06-01

    The effect of the reverse body bias V SB on the hot-electron-induced punch-through (HEIP) reliability of pMOSFETs with a thin gate dielectric at high temperatures was investigated for the first time. Experimental results indicate that the reverse V SB increased the HEIP degradation for a thin pMOSFET because of the increase in the maximum electric field E m due to the increase in the threshold voltage V th. The sensitivity of HEIP degradation to V SB increased with increasing body effect coefficient γ at a given oxide thickness T ox. However, a thin device (22 Å) showed a much stronger dependence of HEIP degradation on V SB due to the decrease in the velocity saturation length l, although it had a smaller γ than a thick device (60 Å). These new observations suggest that the body bias technique for improving circuit performance can cause a reliability problem of nanoscale pMOSFETs at high temperatures and impose a significant limitation on CMOS device scaling.

  8. Study on Preparation of High-k Organic-Inorganic Thin Film for Organic-Inorganic Thin Film Transistor Gate Dielectric Application

    Science.gov (United States)

    Lee, Wen-Hsi; Liu, Chao-Te; Lee, Ying-Chieh

    2012-06-01

    A simple solution-based deposition technique combined with spin-coating is a plausible way to prepare ultra-thin organic-inorganic nanocomposite films. In this study, we describe the spin-coating deposition of a colloidal nanoparticle suspension to obtain an ultra-thin organic-inorganic composite film as a gate insulator for organic thin film transistor (O-TFT) application. To obtain a homogenous organic-inorganic composite film, well-dispersed TiO2 nanoparticles in γ-butyrolactone and polyimide are important; therefore, several dispersants were assessed on the basis of the measurement of the rheological behavior of slurries. The thickness of the organic-inorganic composite film is mainly determined by the speed of spin-coating and viscosity of slurries. An approximately 4000-Å-thick nanocomposite film with homogeneous distribution of TiO2 nanoparticles in polyimide and low roughness was obtained after curing at 200 °C, resulting in a low leakage current density of the nano-composite film, when less than 2 vol % TiO2 nanoparticles were well dispersed in polyimide slurry. The dielectric constant of the organic-inorganic nanocomposite increases with increasing TiO2 content in polyimide, being situated in the range between 4 and 5.

  9. Fabrication and Characteristics of AIInN/A1N/GaN MOS-HEMTs with Ultra-Thin Atomic Layer Deposited Al2O3 Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    MAO Wei; BI Zhi-Wei; LIANG Xiao-Zhen; ZHANG Jin-Feng; KUANG Xian-Wei; ZHANG Jin-Cheng; XUE Jun-Shuai; HAO Yao; MA Xiao-Hua; WANG Chong; LIU Hong-Xia; XU Sheng-Rui; YANG Lin-An

    2010-01-01

    @@ Al0.85In0.15N/AlN/GaN metal-oxide-semiconductor high electron mobility transistors(MOS-HEMTs)employing a 3-nm ultra-thin atomic-layer deposited(ALD)Al2O3 gate dielectric layer are reported.Devices with 0.6μm gate lengths exhibit an improved maximum drain current density of 1227mA/mm at a gate bias of 3 V,a peak transconductance of 328 mS/mm,a cutoff frequency fT of 16 GHz,a maximum frequency of oscillation fmax of45 GHz,as well as significant gate leakage suppression in both reverse and forward directions,compared with the conventional Al0.85In0.15N/AlN/GaN HEMT.Negligible C-V hysteresis,together with a smaller pinch-off voltage shift,is observed,demonstrating few bulk traps in the dielectric and high quality of the Al2O3/AlInN interface.It is most notable that not only the transconductance profile of the MOS-HEMT is almost the same as that of the conventional HEMT with a negative shift,but also the peak transconductance of the MOS-HEMT is increased slightly.It is an exciting improvement in the transconductance performance.

  10. Field effect transistor with HfO2/Parylene-C bilayer hybrid gate insulator

    Science.gov (United States)

    Kumar, Neeraj; Kito, Ai; Inoue, Isao

    2015-03-01

    We have investigated the electric field control of the carrier density and the mobility at the surface of SrTiO3, a well known transition-metal oxide, in a field effect transistor (FET) geometry. We have used a Parylene-C (8 nm)/HfO2 (20 nm) double-layer gate insulator (GI), which can be a potential candidate for a solid state GI for the future Mott FETs. So far, only examples of the Mott FET used liquid electrolyte or ferroelectric oxides for the GI. However, possible electrochemical reaction at the interface causes damage to the surface of the Mott insulator. Thus, an alternative GI has been highly desired. We observed that even an ultra thin Parylene-C layer is effective for keeping the channel surface clean and free from oxygen vacancies. The 8 nm Parylene-C film has a relatively low resistance and consequentially its capacitance does not dominate the total capacitance of the Parylene-C/HfO2 GI. The breakdown gate voltage at 300 K is usually more than 10 V (~ 3.4 MV/cm). At gate voltage of 3 V the carrier density measured by the Hall effect is about 3 ×1013 cm-2, competent to cause the Mott transition. Moreover, the field effect mobility reaches in the range of 10 cm2/Vs indicating the Parylene-C passivated surface is actually very clean.

  11. New adders using hybrid circuit consisting of three-gate single-electron transistors (TG-SETs) and MOSFETs.

    Science.gov (United States)

    Yu, YunSeop; Choi, JungBum

    2007-11-01

    A half-adder (HA) and a full-adder (FA) using hybrid circuits combining three-gate single-electron transistors (TG-SETs) with metal-oxide-semiconductor field-effect-transistors (MOSFETs) are proposed. The proposed HA consists of three TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs, and the proposed FA consists of eight TG-SETs, two enhanced-mode NMOSFETs, and two depletion-mode NMOSFETs. The complexities in the HA and the FA are 7 and 12, respectively, and the worst-case delays in the HA and the FA are 1.48 ns and 2.25 ns, respectively. Compared with the conventional CMOS FA with 0.35 microm technology, the proposed FA can be constructed with 0.43 of devices, and can operate with 3.5 of worst-case delay, 1/534 of average power consumption, and 1/152 of power-delay-product (PDP). The proposed HA and FA can be operated as a half-subtractor (HS) and a full-subtractor (FS) in the case when the levels of the control gates in the HA and the FA are fitly determined. The basic operations of the proposed HA and the proposed FA have been successfully confirmed through SPICE circuit simulation based on the physical device model of TG-SETs.

  12. POWER OPTIMIZED DATAPATH UNITS OF HYBRID EMBEDDED CORE ARCHITECTURE USING CLOCK GATING TECHNIQUE

    National Research Council Canada - National Science Library

    T.Subhashini; M.Kamaraju

    2015-01-01

    ...% of the total power dissipation. The main goal of this work is to implement a prototype power optimized datapath unit and ALU of Hybrid Embedded Controller Architecture targeted on to the FPGA chip and analyze the power consumption...

  13. Band structure of magneto-metallo-dielectric photonic crystals with hybrid one- and two-dimensional periodicity

    Energy Technology Data Exchange (ETDEWEB)

    Reyes-Ayona, E. [Instituto de Fisica, Benemerita Universidad Autonoma de Puebla, Apartado Postal J-48, Puebla 72570 (Mexico); Instituto Nacional de Astrofisica Optica y Electronica, Apartado Postal 51, Puebla 72000 (Mexico); Halevi, P. [Instituto Nacional de Astrofisica Optica y Electronica, Apartado Postal 51, Puebla 72000 (Mexico)

    2012-06-15

    We calculate the band structure of a magneto-metallo-dielectric photonic crystal (PC) with hybrid one- and two-dimensional periodicity. Namely, the permittivity (permeability) is periodic in a plane (single direction). The metallic and magnetic properties are described, respectively, by means of the Drude model and a specific permeability model for Barium-M ferrite. Because of the dispersion of both the permeability and the permittivity, we obtain a non-standard eigenvalue problem which is possible to solve by means of a linearization technique. We found that the first band of this PC is very sensitive to the filling fraction of the magnetic component: by changing this fraction from 0.20 to 0.16 the slope - and effective index of refraction - changes from positive to negative. (Copyright copyright 2012 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  14. Energy dissipation in dielectrics after swift heavy-ion impact: A hybrid model

    Science.gov (United States)

    Osmani, O.; Medvedev, N.; Schleberger, M.; Rethfeld, B.

    2011-12-01

    The energy dissipation after irradiation of dielectrics with swift heavy ions is studied applying a combination of the Monte Carlo (MC) method and the two-temperature model (TTM). Within the MC calculation the transient dynamics of the electrons in the excited dielectric is described: the primary excitation and relaxation of the target electrons as well as the creation of secondary electrons. From the MC data, it was observed that the electron system can be considered as thermalized after a time of t≈100 fs after the ion impact. Then the TTM is applied to calculate the spatial and temporal evolution of the electron and lattice temperature via the electron-phonon coupling using the MC data as initial conditions. Additionally, this MC-TTM combination allows to compute material parameters of strongly excited matter.

  15. 25 GHz embedded-gate graphene transistors with high-k dielectrics on extremely flexible plastic sheets.

    Science.gov (United States)

    Lee, Jongho; Ha, Tae-Jun; Li, Huifeng; Parrish, Kristen N; Holt, Milo; Dodabalapur, Ananth; Ruoff, Rodney S; Akinwande, Deji

    2013-09-24

    Despite the widespread interest in graphene electronics over the past decade, high-performance graphene field-effect transistors (GFETs) on flexible substrates have been rarely achieved, even though this atomic sheet is widely understood to have greater prospects for flexible electronic systems. In this article, we report detailed studies on the electrical and mechanical properties of vapor synthesized high-quality monolayer graphene integrated onto flexible polyimide substrates. Flexible graphene transistors with high-k dielectric afforded intrinsic gain, maximum carrier mobilities of 3900 cm(2)/V·s, and importantly, 25 GHz cutoff frequency, which is more than a factor of 2.5 times higher than prior results. Mechanical studies reveal robust transistor performance under repeated bending, down to 0.7 mm bending radius, whose tensile strain is a factor of 2-5 times higher than in prior studies. In addition, integration of functional coatings such as highly hydrophobic fluoropolymers combined with the self-passivation properties of the polyimide substrate provides water-resistant protection without compromising flexibility, which is an important advancement for the realization of future robust flexible systems based on graphene.

  16. Controllable Threshold Voltage in Organic Complementary Logic Circuits with an Electron-Trapping Polymer and Photoactive Gate Dielectric Layer.

    Science.gov (United States)

    Dao, Toan Thanh; Sakai, Heisuke; Nguyen, Hai Thanh; Ohkubo, Kei; Fukuzumi, Shunichi; Murata, Hideyuki

    2016-07-20

    We present controllable and reliable complementary organic transistor circuits on a PET substrate using a photoactive dielectric layer of 6-[4'-(N,N-diphenylamino)phenyl]-3-ethoxycarbonylcoumarin (DPA-CM) doped into poly(methyl methacrylate) (PMMA) and an electron-trapping layer of poly(perfluoroalkenyl vinyl ether) (Cytop). Cu was used for a source/drain electrode in both the p-channel and n-channel transistors. The threshold voltage of the transistors and the inverting voltage of the circuits were reversibly controlled over a wide range under a program voltage of less than 10 V and under UV light irradiation. At a program voltage of -2 V, the inverting voltage of the circuits was tuned to be at nearly half of the supply voltage of the circuit. Consequently, an excellent balance between the high and low noise margins (NM) was produced (64% of NMH and 68% of NML), resulting in maximum noise immunity. Furthermore, the programmed circuits showed high stability, such as a retention time of over 10(5) s for the inverter switching voltage. Our findings bring about a flexible, simple way to obtain robust, high-performance organic circuits using a controllable complementary transistor inverter.

  17. Leakage current mechanisms of ultrathin high-k Er{sub 2}O{sub 3} gate dielectric film

    Energy Technology Data Exchange (ETDEWEB)

    Wu Deqi; Yao Jincheng; Zhao Hongsheng; Chang Aimin; Li Feng, E-mail: changam@ms.xjb.ac.c [Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Urumqi 830011 (China)

    2009-10-15

    A series of high dielectric material Er{sub 2}O{sub 3} thin films with different thicknesses were deposited on p-type Si (100) substrate by pulse laser deposition at different temperatures. Phase structures of the films were determined by means of X-ray diffraction (XRD) and high resolution transmission electron microscopy (HRTEM). Leakage current density was measured with an HP4142B semiconductor parameter analyzer. The XRD and HRTEM results reveal that Er{sub 2}O{sub 3} thin films deposited below 400 {sup 0}C are amorphous, while films deposited from 400 to 840 {sup 0} are well crystallized with (111)-preferential crystallographic orientation. I-V curves show that, for ultrathin crystalline Er{sub 2}O{sub 3} films, the leakage current density increases by almost one order of magnitude from 6.20 x 10{sup -5} to 6.56 x 10{sup -4} A/cm{sup 2}, when the film thickness decreases by only 1.9 nm from 5.7 to 3.8 nm. However the leakage current density of ultrathin amorphous Er{sub 2}O{sub 3} films with a thickness of 3.8 nm is only 1.73 x 10{sup -5} A/cm{sup 2}. Finally, analysis of leakage current density showed that leakage of ultrathin Er{sub 2}O{sub 3} films at high field is mainly caused by Fowler-Nordheim tunneling, and the large leakage of ultrathin crystalline Er{sub 2}O{sub 3} films could arise from impurity defects at the grain boundary.

  18. Hybrid integration of synthesized dielectric image waveguides in substrate integrated circuit technology and its millimeter wave applications

    Science.gov (United States)

    Patrovsky, Andreas

    This thesis deals with a novel type of integrated dielectric waveguide which is synthesized on a planar grounded substrate by perforation of the zones adjacent to a guiding channel in the center. The resulting Substrate Integrated Image Guide (SIIG) not only allows for low-loss guidance of electromagnetic waves in a similar way as the standard image guide, but also meets the requirements of low cost and ease of integration. A first objective was the detailed analysis of the propagation properties of fundamental and higher order modes in this waveguide structure, regarding attenuation, dispersion behavior, bandwidth, leakage effects, and the impact of fabrication tolerances. For this purpose, specifically adapted techniques of analysis are presented, since established methods for the conventional image guide can not be applied to the more complex periodic SIIG. Commercial electromagnetic full-wave software is used along with a dual-line approach involving a subsequent extraction of the propagation constant from simulated S-parameters. Alternatively, the solution of the eigenmode problem of a single SIIG unit cell also performs the task. Both techniques are in good agreement and provide accurate results, which is supported by measurements on laser-fabricated prototypes. It is shown that the achievable attenuation is much lower than in the standard integrated technologies and that losses mainly depend on the chosen dielectric material. As a consequence, the SIIG also is an attractive technology for applications beyond the mmW band, i. e. in the terahertz range. Design recommendations for the geometric parameters of the SIIG are discussed and a simplified equivalent model with homogeneous dielectric regions is introduced to speed up the design of passive components. Low-loss transitions between dissimilar waveguide structures are indispensable key components for a hybrid integrated platform. In order to enable the connection of standard measurement equipment in the W

  19. Direct Electrical Detection of DNA Hybridization Based on Electrolyte-Gated Graphene Field-Effect Transistor

    Science.gov (United States)

    Ohno, Yasuhide; Okamoto, Shogo; Maehashi, Kenzo; Matsumoto, Kazuhiko

    2013-11-01

    DNA hybridization was electrically detected by graphene field-effect transistors. Probe DNA was modified on the graphene channel by a pyrene-based linker material. The transfer characteristic was shifted by the negative charges on the probe DNA, and the drain current was changed by the full-complementary DNA while no current change was observed after adding noncomplementary DNA, indicating that the graphene field-effect transistor detected the DNA hybridization. In addition, the number of DNAs was estimated by the simple plate capacitor model. As a result, one probe DNA was attached on the graphene channel per 10×10 nm2, indicating their high density functionalization. We estimated that 30% of probe DNA on the graphene channel was hybridized with 200 nM full-complementary DNA while only 5% of probe DNA was bound to the noncomplementary DNA. These results will help to pave the way for future biosensing applications based on graphene FETs.

  20. Si{sub 1-x}Ge{sub x} metal-oxide-semiconductor capacitors with HfTaO{sub x} gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Mallik, S., E-mail: sandi.iitkgp@gmail.com [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India); Mahata, C.; Hota, M.K. [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India); Sarkar, C.K. [Dept. of Electronics and Telecommunication Engineering, Jadavpur University, Jadavpur, Kolkata 700032 (India); Maiti, C.K. [Dept. of Electronics and ECE, Indian Institute of Technology, Kharagpur 721302 (India)

    2011-10-31

    Interfacial reactions and electrical properties of RF sputter deposited HfTaO{sub x} high-k gate dielectric films on Si{sub 1-x}Ge{sub x} (x = 19%) are investigated. X-ray photoelectron spectroscopic analyses indicate an interfacial layer containing GeO{sub x}, Hf silicate, SiO{sub x} (layer of Hf-Si-Ge-O) formation during deposition of HfTaO{sub x}. No evidence of Ta-silicate or Ta incorporation was found at the interface. The crystallization temperature of HfTaO{sub x} film is found to increase significantly after annealing beyond 500 deg. C (for 5 min) along with the incorporation of Ta. HfTaO{sub x} films (with 18% Ta) remain amorphous up to about 500 deg. C anneal. Electrical characterization of post deposition annealed (in oxygen at 600 deg. C) samples showed; capacitance equivalent thickness of {approx} 4.3-5.7 nm, hysteresis of 0.5-0.8 V, and interface state density = 1.2-3.8 x 10{sup 12} cm{sup -2} eV{sup -1}. The valence and conduction band offsets were determined from X-ray photoelectron spectroscopy spectra after careful analyses of the experimental data and removal of binding energy shift induced by differential charging phenomena occurring during X-ray photoelectron spectroscopic measurements. The valence and conduction band offsets were found to be 2.45 {+-} 0.05 and 2.31 {+-} 0.05 eV, respectively, and a band gap of 5.8 {+-} 05 eV was found for annealed samples.

  1. Electrical characteristics of AlO sub x N sub y prepared by oxidation of sub-10-nm-thick AlN films for MOS gate dielectric applications

    CERN Document Server

    Jeon, S H; Kim, H S; Noh, D Y; Hwang, H S

    2000-01-01

    In this research, the feasibility of ultrathin AlO sub x N sub y prepared by oxidation of sub 100-A-thick AlN thin films for metal-oxide-semiconductor (MOS) gate dielectric applications was investigated. Oxidation of 51-A-and 98-A-thick as-deposited AlN at 800 .deg. C was used to form 72-A-and 130-A-thick AlO sub x N sub y , respectively. Based on the capacitance-voltage (C-V) measurements of the MOS capacitor, the dielectric constants of 72 A-thick and 130 A-thick Al-oxynitride were 5.15 and 7, respectively. The leakage current of Al-oxynitride at low field was almost the same as that of thermal SiO sub 2. based on the CV data, the interface state density of Al-oxynitride was relatively higher than that of SiO sub 2. Although process optimization is still necessary, the Al-oxynitride exhibits some possibility for future MOS gate dielectric applications.

  2. Biocompatible/Degradable Silk Fibroin:Poly(Vinyl Alcohol)-Blended Dielectric Layer Towards High-Performance Organic Field-Effect Transistor

    Science.gov (United States)

    Zhuang, Xinming; Huang, Wei; Yang, Xin; Han, Shijiao; Li, Lu; Yu, Junsheng

    2016-10-01

    Biocompatible silk fibroin (SF):poly(vinyl alcohol) (PVA) blends were prepared as the dielectric layers of organic field-effect transistors (OFETs). Compared with those with pure SF dielectric layer, an optimal threshold voltage of ~0 V, high on/off ratio of ~104, and enhanced field-effect mobility of 0.22 cm2/Vs of OFETs were obtained by carefully controlling the weight ratio of SF:PVA blends to 7:5. Through the morphology characterization of dielectrics and organic semiconductors by utilizing atom force microscopy and electrical characterization of the devices, the performance improvement of OFETs with SF:PVA hybrid gate dielectric layers were attributed to the smooth and homogeneous morphology of blend dielectrics. Furthermore, due to lower charge carrier trap density, the OFETs based on SF:PVA-blended dielectric exhibited a higher bias stability than those based on pure SF dielectric.

  3. Hybrid analytic-numeric calculation method for light through a bounded planar dielectric

    NARCIS (Netherlands)

    Nicolau, J.B.; Groesen, van E.

    2005-01-01

    We present a hybrid analytic-numeric method to calculate the transmission and reflection of light that is fluxed into a bounded complicated optical structure surrounded by air. The solution is obtained by numerical calculations inside a square containing the structure and by analytical calculations

  4. Installing logic-gate responses to a variety of biological substances in supramolecular hydrogel-enzyme hybrids.

    Science.gov (United States)

    Ikeda, Masato; Tanida, Tatsuya; Yoshii, Tatsuyuki; Kurotani, Kazuya; Onogi, Shoji; Urayama, Kenji; Hamachi, Itaru

    2014-06-01

    Soft materials that exhibit stimuli-responsive behaviour under aqueous conditions (such as supramolecular hydrogels composed of self-assembled nanofibres) have many potential biological applications. However, designing a macroscopic response to structurally complex biochemical stimuli in these materials still remains a challenge. Here we show that redox-responsive peptide-based hydrogels have the ability to encapsulate enzymes and still retain their activities. Moreover, cooperative coupling of enzymatic reactions with the gel response enables us to construct unique stimuli-responsive soft materials capable of sensing a variety of disease-related biomarkers. The programmable gel-sol response (even to biological samples) is visible to the naked eye. Furthermore, we built Boolean logic gates (OR and AND) into the hydrogel-enzyme hybrid materials, which were able to sense simultaneously plural specific biochemicals and execute a controlled drug release in accordance with the logic operation. The intelligent soft materials that we have developed may prove valuable in future medical diagnostics or treatments.

  5. Polyimide/nanosized CaCu3Ti4O12 functional hybrid films with high dielectric permittivity

    Science.gov (United States)

    Yang, Yang; Zhu, Ben-Peng; Lu, Zhi-Hong; Wang, Zi-Yu; Fei, Chun-Long; Yin, Di; Xiong, Rui; Shi, Jing; Chi, Qing-Guo; Lei, Qing-Quan

    2013-01-01

    This work reports the high dielectric permittivity of polyimide (PI) embedded with CaCu3Ti4O12 (CCTO) nanoparticles. The dielectric behavior has been investigated over a frequency of 100 Hz-1 MHz. High dielectric permittivity (ɛ = 171) and low dielectric loss (tan δ = 0.45) at 100 Hz have been observed near the percolation threshold. The experimental results fit well with the Percolation theory. We suggest that the high dielectric permittivity originates from the large interface area and the remarkable Maxwell-Wagner-Sillars effect at percolation in which nomadic charge carriers are blocked at internal interfaces between CCTO nanoparticles and the polyimide matrix.

  6. Thin film transistors for flexible electronics: contacts, dielectrics and semiconductors.

    Science.gov (United States)

    Quevedo-Lopez, M A; Wondmagegn, W T; Alshareef, H N; Ramirez-Bon, R; Gnade, B E

    2011-06-01

    The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed.

  7. Thin film transistors for flexible electronics: Contacts, dielectrics and semiconductors

    KAUST Repository

    Quevedo-López, Manuel Angel Quevedo

    2011-06-01

    The development of low temperature, thin film transistor processes that have enabled flexible displays also present opportunities for flexible electronics and flexible integrated systems. Of particular interest are possible applications in flexible sensor systems for unattended ground sensors, smart medical bandages, electronic ID tags for geo-location, conformal antennas, radiation detectors, etc. In this paper, we review the impact of gate dielectrics, contacts and semiconductor materials on thin film transistors for flexible electronics applications. We present our recent results to fully integrate hybrid complementary metal oxide semiconductors comprising inorganic and organic-based materials. In particular, we demonstrate novel gate dielectric stacks and semiconducting materials. The impact of source and drain contacts on device performance is also discussed. Copyright © 2011 American Scientific Publishers.

  8. Papery solar cells based on dielectric/metal hybrid transparent cathode

    Energy Technology Data Exchange (ETDEWEB)

    Wang, Fei; Chen, Zhijian; Xiao, Lixin; Qu, Bo; Gong, Qihuang [State Key Laboratory for Mesoscopic Physics and Department of Physics, Peking University, Beijing 100871 (China)

    2010-07-15

    Poly(3-hexylthiophene) (P3HT):1-(3-methoxycarbonyl)-propyl-1-phenyl-(6,6)C{sub 61} (PCBM) photovoltaic devices based on ordinary paper as substrate were fabricated. Au layer deposited on paper by RF magnetron sputtering was used as anode. The hybrid layer of LiF co-evaporated with Al was used for transparent cathode, and the light transmittance could reach to {proportional_to}70%. By optimizing the mass proportion of LiF and Al, we could get the best papery solar cells with the short current density and open circuit voltage 0.1 mA/cm{sup 2} and 0.39 V, respectively. The corresponding power conversion efficiency was measured to be 0.13 permille illuminated with 100 mW/cm{sup 2} air mass 1.5 global (AM 1.5 G) simulated sunlight. (author)

  9. Hybrid Cleaning Technology for Enhanced Post-Cu/Low-Dielectric Constant Chemical Mechanical Planarization Cleaning Performance

    Science.gov (United States)

    Ramachandran, Manivannan; Cho, Byoung-Jun; Kwon, Tae-Young; Park, Jin-Goo

    2013-05-01

    During chemical mechanical planarization (CMP), a copper/low-k surface is often contaminated by abrasive particles, organic materials and other additives. These contaminants need to be removed in the subsequent cleaning process with minimum material loss. In this study, a dilute amine-based alkaline cleaning solution is used along with physical force in the form of megasonic energy to remove particles and organic contaminants. Tetramethylammonium hydroxide (TMAH) and monoethanolamine (MEA) are used as an organic base and complexing agent, respectively, in the proposed solution. Ethanolamine acts as a corrosion inhibitor in the solution. Organic residue removal was confirmed through contact angle measurements and X-ray photoelectron spectroscopy analysis. Electrochemical studies showed that the proposed solution increases protection against corrosion, and that the hybrid cleaning technology resulted in higher particle removal efficiency from both the copper and low-k surfaces.

  10. Tunable Dielectric Responses Triggered by Dimensionality Modification in Organic-Inorganic Hybrid Phase Transition Compounds (C5H6N)CdnCl2n+1 (n = 1 and 2).

    Science.gov (United States)

    Sun, Xiao-Fen; Wang, Zhongxia; Li, Peng-Fei; Liao, Wei-Qiang; Ye, Heng-Yun; Zhang, Yi

    2017-03-20

    Two hybrids (C5H6N)CdCl3 (1) and (C5H6N)Cd2Cl5 (2) were synthesized by stoichiometric regulation of reactants. 1 with a one-dimensional chain-like structure shows a step-like dielectric anomaly at around 158 K. 2 with a layered structure undergoes a prominent phase transition in the vicinity of 182 K, accompanying obvious dielectric relaxation behavior in a broad temperature range. Systematic characterization, such as differential scanning calorimetry (DSC), single-crystal X-ray diffraction, and dielectric measurements, has demonstrated that the phase transitions of 1 and 2 are both attributable to the dynamic motion of the organic cation. Significantly, dimensionality modulation triggers the tunable dielectric responses in these two compounds. Thus, regulation of the phase transition temperature and dielectric responses in the various dimensions of the structure is a potentially effective method to construct tunable dielectric phase transition materials.

  11. Polyaniline coated carbon nanotube/graphene "sandwich" hybrid and its high-k epoxy composites with low dielectric loss and percolation threshold

    Science.gov (United States)

    Wang, Tongxing; Yuan, Li; Liang, Guozheng; Gu, Aijuan

    2015-12-01

    Fabricating high-k conductor/polymer composites with low dielectric loss and percolation threshold is still a challenge, while the electric conductor is the key factor of determining the dielectric behavior of composites. A novel hybridized conductor with "sandwich" structure (rPANI@CNT-rGO) and active groups was prepared by introducing polyaniline coated carbon nanotube (rPANI@CNT) on the surface of reduced graphene oxide (rGO) through electrostatic and π-π conjugate forces. And the rPANI@CNT-rGO hybrids with different loadings of rPANI@CNT were introduced into epoxy resin (EP) to prepare a series of rPANI@CNT-0.75rGO/EP composites; meanwhile rPANI@CNT and rGO were mechanically blended with EP to prepare rPANI@CNT/0.75rGO/EP composites for comparison. rPANI@CNT/0.75rGO/EP composites have low dielectric constant (10-20), whereas the dielectric constant at 100 Hz of the 7rPANI@CNT-0.75rGO/EP composite with 0.75 wt% rPANI@CNT is as high as 210, much larger than those of rPANI@CNT/EP, 0.75rGO/EP and rPANI@CNT/0.75rGO/EP composites. Meanwhile, the dielectric loss at 100 Hz of 7rPANI@CNT-0.75rGO/EP composite is only 17% of that of 0.75rGO/EP, indicating that the dielectric behavior of rPANI@CNT-0.75rGO/EP composites is not originated from a simple addition of basic components, but has an obvious synergistic effect. The percolation threshold of rPANI@CNT-0.75rGO/EP composites is only 1.1 wt%. The origin of these attractive dielectric properties was revealed through systematically discussing the structures and simulated circuits of rPANI@CNT-0.75rGO/EP composites.

  12. DNA-Hybrid-Gated Photothermal Mesoporous Silica Nanoparticles for NIR-Responsive and Aptamer-Targeted Drug Delivery.

    Science.gov (United States)

    Zhang, Yuanxin; Hou, Zhiyao; Ge, Yakun; Deng, Kerong; Liu, Bei; Li, Xuejiao; Li, Quanshun; Cheng, Ziyong; Ma, Ping'an; Li, Chunxia; Lin, Jun

    2015-09-23

    Near-infrared light is an attractive stimulus due to its noninvasive and deep tissue penetration. Particularly, NIR light is utilized for cancer thermotherapy and on-demand release of drugs by the disruption of the delivery carriers. Here we have prepared a novel NIR-responsive DNA-hybrid-gated nanocarrier based on mesoporous silica-coated Cu1.8S nanoparticles. Cu1.8S nanoparticles, possessing high photothermal conversion efficiency under a 980 nm laser, were chosen as photothermal agents. The mesoporous silica structure could be used for drug storage/delivery and modified with aptamer-modified GC-rich DNA-helix as gatekeepers, drug vectors, and targeting ligand. Simultaneously, the as-produced photothermal effect caused denaturation of DNA double strands, which triggered the drug release of the DNA-helix-loaded hydrophilic drug doxorubicin and mesopore-loaded hydrophobic drug curcumin, resulting in a synergistic therapeutic effect. The Cu1.8S@mSiO2 nanocomposites endocytosed by cancer cells through the aptamer-mediated mode are able to generate rational release of doxorubicin/curcumin under NIR irradiation, strongly enhancing the synergistic growth-inhibitory effect of curcumin against doxorubicin in MCF-7 cells, which is associated with a strong mitochondrial-mediated cell apoptosis progression. The underlying mechanism of apoptosis showed a strong synergistic inhibitory effect both on the expression of Bcl-2, Bcl-xL, Mcl-1, and upregulated caspase 3/9 activity and on the expression level of Bak and Bax. Therefore, Cu1.8S@mSiO2 with efficient synergistic therapeutic efficiency is a potential multifunctional cancer therapy nanoplatform.

  13. Mechanism of high dielectric performance of polymer composites induced by BaTiO3-supporting Ag hybrid fillers

    Science.gov (United States)

    Fang, Fang; Yang, Wenhu; Yu, Shuhui; Luo, Suibin; Sun, Rong

    2014-03-01

    BaTiO3-supporting Ag hybrid particles (BT-Ag) with varied fraction of Ag were synthesized by reducing silver nitrate in the glycol solution containing BaTiO3 (BT) suspensions. The Ag nano particles with a size of about 20 nm were discretely grown on the surface of the BT. The dielectric performance of the composites containing the BT-Ag as fillers in the matrix of polyvinylidene fluoride (PVDF) was investigated. The relative permittivity (ɛr) of the BT-Ag/PVDF composites increased prominently with the increase of BT-Ag loading amount, and the typical conductive path of the conductor/polymer system was not observed even with a high loading of BT-Ag. The ɛr at 100 Hz for the three BT-(0.31, 0.49, 0.61)Ag/PVDF composites at room temperature were 283, 350, and 783, respectively. The ɛr of the composites was enhanced by more than 3 times compared with that of the composite containing untreated BT nanoparticles at frequencies over 1 kHz and the loss tangent (tan δ) was less than 0.1 which should be attributed to the low conductivity of the composites. Theoretical calculations based on the effective medium percolation theory model and series-parallel model suggested that the enhanced permittivity of BT-Ag/PVDF composites should arise from the ultrahigh permittivity of BT-Ag fillers, which was over 104 and associated with the content of Ag deposited on the surface of BT.

  14. Low-voltage operation of ZrO2-gated n-type thin-film transistors based on a channel formed by hybrid phases of SnO and SnO2.

    Science.gov (United States)

    Chu, Hsin-Chueh; Shen, Yung-Shao; Hsieh, Ching-Heng; Huang, Jia-Hong; Wu, Yung-Hsien

    2015-07-22

    With SnO typically regarded as a p-type oxide semiconductor, an oxide semiconductor formed by hybrid phases of mainly SnO and a small amount of SnO2 with an average [O]/[Sn] ratio of 1.1 was investigated as a channel material for n-type thin-film transistors (TFTs). Furthermore, an appropriate number of oxygen vacancies were introduced into the oxide during annealing at 400 °C in ambient N2, making both SnO and SnO2 favorable for current conduction. By using high-κ ZrO2 with a capacitance equivalent thickness of 13.5 nm as the gate dielectric, the TFTs processed at 400 °C demonstrated a steep subthreshold swing (SS) of 0.21 V/dec, and this can be ascribed to the large gate capacitance along with a low interface trap density (Dit) value of 5.16 × 10(11) cm(-2) eV(-1). In addition, the TFTs exhibit a relatively high electron mobility of 7.84 cm(2)/V·s, high ON/OFF current ratios of up to 2.5 × 10(5), and a low gate leakage current at a low operation voltage of 3 V. The TFTs also prove its high reliability performance by showing negligible degradation of SS and threshold voltage (VT) against high field stress (-10 MV/cm). When 3% oxygen annealing is combined with a thinner channel thickness, TFTs with even higher ION/IOFF ratios exceeding 10(7) can also be obtained. With these promising characteristics, the overall performance of the TFTs displays competitive advantages compared with other n-type TFTs formed on binary or even some multicomponent oxide semiconductors and paves a promising and economic avenue to implement an n-type oxide semiconductor without doping for production-worthy TFT technology. Most importantly, when combined with the typical SnO-based p-type oxide semiconductor, it would usher in a new era in achieving high-performance complementary metal oxide semiconductor circuits by using the same SnO-based oxide semiconductor.

  15. Fluorinated and Thermo-Cross-Linked Polyhedral Oligomeric Silsesquioxanes: New Organic-Inorganic Hybrid Materials for High-Performance Dielectric Application.

    Science.gov (United States)

    Wang, Jiajia; Sun, Jing; Zhou, Junfeng; Jin, Kaikai; Fang, Qiang

    2017-04-12

    A fluorinated and thermo-cross-linked polyhedral oligomeric silsesquioxane (POSS) has been successfully synthesized by thermal polymerization of a fluorinated POSS monomer having an inorganic silsesquioxane core and organic side chains bearing thermo-cross-linkable trifluorovinyl ether groups. This new inorganic-organic hybrid polymer shows high thermostability with a 5 wt % loss temperature of 436 °C, as well as good transparency (a sheet with an average thickness of 1.5 mm shows high transmittance of 92% varying from 400 to 1100 nm). Moreover, the polymer exhibits both low dielectric constant (polymer also shows low water uptake (polymer is very suitable to be utilized as a high-performance dielectric material for fabrication of high-frequency printed circuit boards or encapsulation resins for integrated circuit dies in the microelectronic industry. Furthermore, this work also provides a route for the preparation of fluorinated POSS-based polymers.

  16. Research Update: Polyimide/CaCu3Ti4O12 nanofiber functional hybrid films with improved dielectric properties

    Science.gov (United States)

    Yang, Yang; Wang, Ziyu; Ding, Yi; Lu, Zhihong; Sun, Haoliang; Li, Ya; Wei, Jianhong; Xiong, Rui; Shi, Jing; Liu, Zhengyou; Lei, Qingquan

    2013-11-01

    This work reports the excellent dielectric properties of polyimide (PI) embedded with CaCu3Ti4O12 (CCTO) nanofibers. The dielectric behaviors were investigated over a frequency of 100 Hz-1 MHz. It is shown that embedding CCTO nanofibers with high aspect ratio (67) is an effective means to enhance the dielectric permittivity and reduce the percolation threshold. The dielectric permittivity of PI/CCTO nanofiber composites is 85 with 1.5 vol.% loading of filler, also the dielectric loss is only 0.015 at 100 Hz. Monte Carlo simulation was used to investigate the percolation threshold of CCTO nanofibers reinforced polyimide matrix by using excluded volume theory and soft, hard-core models. The results are in good agreement with the percolation theory and the hard-core model can well explain the percolation phenomena in PI/CCTO nanofiber composites. The dielectric properties of the composites will meet the practical requirements for the application in high dielectric constant capacitors and high energy density materials.

  17. Research Update: Polyimide/CaCu3Ti4O12 nanofiber functional hybrid films with improved dielectric properties

    Directory of Open Access Journals (Sweden)

    Yang Yang

    2013-11-01

    Full Text Available This work reports the excellent dielectric properties of polyimide (PI embedded with CaCu3Ti4O12 (CCTO nanofibers. The dielectric behaviors were investigated over a frequency of 100 Hz–1 MHz. It is shown that embedding CCTO nanofibers with high aspect ratio (67 is an effective means to enhance the dielectric permittivity and reduce the percolation threshold. The dielectric permittivity of PI/CCTO nanofiber composites is 85 with 1.5 vol.% loading of filler, also the dielectric loss is only 0.015 at 100 Hz. Monte Carlo simulation was used to investigate the percolation threshold of CCTO nanofibers reinforced polyimide matrix by using excluded volume theory and soft, hard-core models. The results are in good agreement with the percolation theory and the hard-core model can well explain the percolation phenomena in PI/CCTO nanofiber composites. The dielectric properties of the composites will meet the practical requirements for the application in high dielectric constant capacitors and high energy density materials.

  18. Universal quantum gates for hybrid system assisted by atomic ensembles embedded in double-sided optical cavities

    Science.gov (United States)

    Liu, A.-Peng; Cheng, Liu-Yong; Guo, Qi; Zhang, Shou; Zhao, Ming-Xia

    2017-01-01

    We propose deterministic schemes for controlled-NOT (CNOT), Toffoli, and Fredkin gates between flying photon qubits and the collective spin wave (magnon) of an atomic ensemble inside double-sided optical microcavities. All the gates can be accomplished with 100% success probability in principle and no additional qubit is required. Atomic ensemble is employed so that light-matter coupling is remarkably improved by collective enhancement. We qualified the performance of the gates and the results show that they can be faithfully constituted with current experimental techniques. PMID:28272548

  19. Simulation of temperature dependent dielectric breakdown in n+-polySi/SiO2/n-6H-SiC structures during Poole-Frenkel stress at positive gate bias

    Science.gov (United States)

    Samanta, Piyas; Mandal, Krishna C.

    2016-08-01

    We present for the first time a thorough investigation of trapped-hole induced gate oxide deterioration and simulation results of time-dependent dielectric breakdown (TDDB) of thin (7-25 nm) silicon dioxide (SiO2) films thermally grown on (0 0 0 1) silicon (Si) face of n-type 6H-silicon carbide (n-6H-SiC). Gate oxide reliability was studied during both constant voltage and current stress with positive bias on the degenerately doped n-type poly-crystalline silicon (n+-polySi) gate at a wide range of temperatures between 27 and 225 °C. The gate leakage current was identified as the Poole-Frenkel (PF) emission of electrons trapped at an energy 0.92 eV below the SiO2 conduction band. Holes were generated in the n+-polySi anode material as well as in the oxide bulk via band-to-band ionization depending on the film thickness tox and the energy of the hot-electrons (emitted via PF mechanism) during their transport through oxide films at oxide electric fields Eox ranging from 5 to 10 MV/cm. Our simulated time-to-breakdown (tBD) results are in excellent agreement with those obtained from time consuming TDDB measurements. It is observed that irrespective of stress temperatures, the tBD values estimated in the field range between 5 and 9 MV/cm better fit to reciprocal field (1/E) model for the thickness range studied here. Furthermore, for a 10 year projected device lifetime, a good reliability margin of safe operating field from 8.5 to 7.5 MV/cm for 7 nm and 8.1 to 6.9 MV/cm for 25 nm thick SiO2 was observed between 27 and 225 °C.

  20. Band Alignment and Optical Properties of (ZrO20.66(HfO20.34 Gate Dielectrics Thin Films on p-Si (100

    Directory of Open Access Journals (Sweden)

    Dahlang Tahir

    2011-11-01

    Full Text Available (ZrO20.66(HfO20.34 dielectric films on p-Si (100 were grown by atomic layer deposition method, for which the conduction band offsets, valence band offsets and band gaps were obtained by using X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy. The band gap, valence and conduction band offset values for (ZrO20.66(HfO20.34 dielectric thin film, grown on Si substrate were about 5.34, 2.35 and 1.87 eV respectively. This band alignment was similar to that of ZrO2. In addition, The dielectric function ε (k, ω, index of refraction n and the extinction coefficient k for the (ZrO20.66(HfO20.34 thin films were obtained from a quantitative analysis of REELS data by comparison to detailed dielectric response model calculations using the QUEELS-ε (k,ω-REELS software package. These optical properties are similar with ZrO2 dielectric thin films.

  1. Amorphous TiO2-coated reduced graphene oxide hybrid nanostructures for polymer composites with low dielectric loss

    Science.gov (United States)

    Tong, Wangshu; Zhang, Yihe; Yu, Li; Lv, Fengzhu; Liu, Leipeng; Zhang, Qian; An, Qi

    2015-10-01

    Nanocomposite of poly(vinylidene fluoride-co-hexafluoropropylene) incorporated with titanium dioxide-modified reduced graphene oxide sheets (rGO-TiO2/PVDF-HFP) was prepared by in situ assembling TiO2 on graphene oxide (GO), and its dielectric properties were carefully characterized. The GO layers were completely coated with amorphous TiO2. The dielectric permittivity increased stably as rGO-TiO2 content increased, and the loss was low at low frequencies. TiO2 inter-layer acted as an inter-particle barrier to prevent direct contact of rGO, which provided a new simple way for tuning the dielectric properties of polymer composites with low dielectric loss by controlling the structure of fillers.

  2. Enhanced tunneling in stacked gate dielectrics with ultra-thin HfO{sub 2} layers sandwiched between thicker SiO{sub 2} layers

    Energy Technology Data Exchange (ETDEWEB)

    Hinkle, C.L.; Fulton, C.; Nemanich, R.J.; Lucovsky, G

    2004-07-15

    There has been a search for alternative dielectrics with significantly increased dielectric constants, K, which increases physical thickness in proportion to K, and therefore would significantly reduce direct tunneling. However, increases in K to values of 15-25 in transition metal and rare earth oxides are generally accompanied by decreases in the conduction band offset energy with respect to Si, E{sub B}, and the effective electron tunneling mass, m{sub eff}, which mitigate gains from increased thickness. A novel technique, based on stacked dielectrics, is used to obtain the tunneling mass-conduction band offset energy product. When combined with optical measurements of tunneling barriers, this yields direct estimates of the tunneling mass.

  3. Structural and optical properties of ZnO films grown on silicon and their applications in MOS devices in conjunction with ZrO2 as a gate dielectric

    Indian Academy of Sciences (India)

    S K Nandi; S Chakraborty; M K Bera; C K Maiti

    2007-06-01

    Photoluminescence (PL) properties of undoped ZnO thin films grown by rf magnetron sputtering on silicon substrates have been investigated. ZnO/Si substrates are characterized by Rutherford backscattering (RBS), X-ray diffraction (XRD), Fourier transform infrared (FTIR), and X-ray photoelectron spectroscopy (XPS). ZrO2 thin films have been deposited on ZnO using microwave plasma enhanced chemical vapour deposition at a low temperature (150°C). Using metal insulator semiconductor (MIS) capacitor structures, the reliability and the leakage current characteristics of ZrO2 films have been studied both at room and high temperatures. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Good electrical and reliability properties suggest the suitability of deposited ZrO2 thin films as an alternative as gate dielectric on ZnO/-Si heterostructure for future device applications.

  4. Improved linearity and reliability in GaN metal-oxide-semiconductor high-electron-mobility transistors using nanolaminate La2O3/SiO2 gate dielectric

    Science.gov (United States)

    Hsu, Ching-Hsiang; Shih, Wang-Cheng; Lin, Yueh-Chin; Hsu, Heng-Tung; Hsu, Hisang-Hua; Huang, Yu-Xiang; Lin, Tai-Wei; Wu, Chia-Hsun; Wu, Wen-Hao; Maa, Jer-Shen; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-04-01

    Improved device performance to enable high-linearity power applications has been discussed in this study. We have compared the La2O3/SiO2 AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors (MOS-HEMTs) with other La2O3-based (La2O3/HfO2, La2O3/CeO2 and single La2O3) MOS-HEMTs. It was found that forming lanthanum silicate films can not only improve the dielectric quality but also can improve the device characteristics. The improved gate insulation, reliability, and linearity of the 8 nm La2O3/SiO2 MOS-HEMT were demonstrated.

  5. Thermally deposited Ag-doped CdS thin film transistors with high-k rare-earth oxide Nd{sub 2}O{sub 3} as gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Gogoi, P., E-mail: paragjyoti_g@rediffmail.com [Sibsagar College, Material Science Laboratory, Department of Physics (India)

    2013-03-15

    The performance of thermally deposited CdS thin film transistors doped with Ag has been reported. Ag-doped CdS thin films have been prepared using chemical method. High dielectric constant rare earth oxide Nd{sub 2}O{sub 3} has been used as gate insulator. The thin film trasistors are fabricated in coplanar electrode structure on ultrasonically cleaned glass substrates with a channel length of 50 {mu}m. The thin film transistors exhibit a high mobility of 4.3 cm{sup 2} V{sup -1} s{sup -1} and low threshold voltage of 1 V. The ON-OFF ratio of the thin film transistors is found as 10{sup 5}. The TFTs also exhibit good transconductance and gain band-width product of 1.15 Multiplication-Sign 10{sup -3} mho and 71 kHz respectively.

  6. 基于微孔SiO2栅介质的透明氧化物薄膜晶体管%Transparent Oxide Thin Film Transistors Based on Microporous SiO2 Gate Dielectric

    Institute of Scientific and Technical Information of China (English)

    颜钟惠; 王瑶; 吴国栋; 轩瑞杰; 李想

    2013-01-01

    Using microporous SiO2 film deposited by plasma enhanced chemical vapor deposition (PECVD) as the gate dielectric, transparent oxide thin film transistors were prepared. The samples were characterized by field emission scanning electron microscopy (FESEM), impedance analyzer, and semiconductor parameter analyzer. The results exhibit that the microporous SiO2 gate dielectric has a large electric-double-layer effect", and the thin film transistors show a good performance with an ultralow operating voltage, a large on-off ratio. What more, light transmit-tance and stability of the thin film transistors are also excellent.%采用等离子增强化学气相沉积(PECVD)法制备微孔SiO2薄膜并将其作为栅介质,制作了基于微孔SiO2栅介质层的透明氧化物薄膜晶体管.利用场发射扫描电镜、阻抗分析仪以及半导体分析仪对样品进行表征.结果表明,微孔SiO2栅介质具有双电层效应,这种微孔SiO2栅介质透明氧化物薄膜晶体管器件具有工作电压低,开关电流比大,透光性高,稳定性强等良好性能.

  7. Gated supramolecular chemistry in hybrid mesoporous silica nanoarchitectures: controlled delivery and molecular transport in response to chemical, physical and biological stimuli.

    Science.gov (United States)

    Alberti, Sebastián; Soler-Illia, Galo J A A; Azzaroni, Omar

    2015-04-11

    This review presents and discusses recent advances in the emerging field of "gated nanochemistry", outlining the substantial progress made so far. The development of hybrid mesoporous silica with complex tailored pore nanoarchitectures bridges the gap between molecular materials and the requirements of nanodevices for controlled nanoscale chemistry. In the last decade, membranes, particles and thin film porous architectures have been designed, synthesized and selectively modified by molecular, polymeric, organometallic or biologically active groups. The exquisite manipulation of mesopore morphology and interconnection combined with molecular or supramolecular functionalities, and the intrinsic biological compatibility of silica have made these materials a potential platform for selective sensing and drug delivery. The wide répertoire of these hard-soft architectures permit us to envisage sophisticated intelligent nano-systems that respond to a variety of external stimuli such as pH, redox potential, molecule concentration, temperature, or light. Transduction of these stimuli into a predefined response implies exploiting spatial and physico-chemical effects such as charge distribution, steric constraints, equilibria displacements, or local changes in ionic concentration, just to name a few examples. As expected, this "positional mesochemistry" can be only attained through the concerted control of assembly, surface tailoring and, confinement conditions, thus giving birth to a new class of stimuli-responsive materials with modulable transport properties. As a guiding framework the emerging field of "gated nanochemistry" offers methodologies and tools for building up stimuli-sensitive porous architectures equipped with switchable entities whose transport properties can be triggered at will. The gated nanoscopic hybrid materials discussed here not only herald a new era in the integrative design of "smart" drug delivery systems, but also give the reader a perspective of

  8. High-permitivity cerium oxide prepared by molecular beam deposition as gate dielectric and passivation layer and applied to AlGaN/GaN power high electron mobility transistor devices

    Science.gov (United States)

    Chiu, Yu Sheng; Liao, Jen Ting; Lin, Yueh Chin; Chien Liu, Shin; Lin, Tai Ming; Iwai, Hiroshi; Kakushima, Kuniyuki; Chang, Edward Yi

    2016-05-01

    High-κ cerium oxide (CeO2) was applied to AlGaN/GaN high-electron-mobility transistors (HEMTs) as a gate insulator and a passivation layer by molecular beam deposition (MBD) for high-power applications. From capacitance-voltage (C-V) measurement results, the dielectric constant of the CeO2 film was 25.2. The C-V curves showed clear accumulation and depletion behaviors with a small hysteresis (20 mV). Moreover, the interface trap density (D it) was calculated to be 5.5 × 1011 eV-1 cm-2 at 150 °C. A CeO2 MOS-HEMT was fabricated and demonstrated a low subthreshold swing (SS) of 87 mV/decade, a high ON/OFF drain current ratio (I ON/I OFF) of 1.14 × 109, and a low gate leakage current density (J leakage) of 2.85 × 10-9 A cm-2 with an improved dynamic ON-resistance (R ON), which is about one order of magnitude lower than that of a conventional HEMT.

  9. Electrical characteristics of metal–insulator–semiconductor and metal–insulator–semiconductor–insulator–metal capacitors under different high-$k$ gate dielectrics investigated in the semi-classical and quantum mechanical models

    Indian Academy of Sciences (India)

    SLAH HLALI; NEILA HIZEM; ADEL KALBOUSSI

    2017-02-01

    In this paper the electrical characteristics of metal–insulator–semiconductor (MIS) and metal–insulator–semiconductor–insulator–metal (MISIM) capacitors with (100)-oriented p-type silicon as a substrate under different high-$k$ gate dielectrics (SiO$_2$, HfO$_2$, La$_2$O$_3$ and TiO$_2$) are investigated in the semi-classical and quantum mechanical models. We review the quantum correction in the inversion layer charge density for p-doped structures. The purpose of this paper is to point out the differences between the semi-classical and quantum mechanical charge descriptions at the insulator–semiconductor interface and the effect of the type of oxide and their position (gate oxide or buried oxide) in our structures. In particular, capacitance–voltage ($C–V$), relative position of the sub-band energies and their wavefunctions are studied to examine qualitatively and quantitatively the electron states and charging mechanisms in our devices. We find that parameters such as threshold voltage and device trans-conductance are enormously sensitive to the proper treatment of quantization effects.

  10. Impact of gate geometry on ionic liquid gated ionotronic systems

    Science.gov (United States)

    Wong, A. T.; Noh, J. H.; Pudasaini, P. R.; Wolf, B.; Balke, N.; Herklotz, A.; Sharma, Y.; Haglund, A. V.; Dai, S.; Mandrus, D.; Rack, P. D.; Ward, T. Z.

    2017-04-01

    Ionic liquid electrolytes are gaining widespread application as a gate dielectric used to control ion transport in functional materials. This letter systematically examines the important influence that device geometry in standard "side gate" 3-terminal geometries plays in device performance of a well-known oxygen ion conductor. We show that the most influential component of device design is the ratio between the area of the gate electrode and the active channel, while the spacing between these components and their individual shapes has a negligible contribution. These findings provide much needed guidance in device design intended for ionotronic gating with ionic liquids.

  11. Physical and electrical characteristics of AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistors with rare earth Er{sub 2}O{sub 3} as a gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Lin, Ray-Ming, E-mail: rmlin@mail.cgu.edu.tw; Chu, Fu-Chuan; Das, Atanu; Liao, Sheng-Yu; Chou, Shu-Tsun; Chang, Liann-Be

    2013-10-01

    In this study, the rare earth erbium oxide (Er{sub 2}O{sub 3}) was deposited using an electron beam onto an AlGaN/GaN heterostructure to fabricate metal-oxide-semiconductor high-electron-mobility transistors (MOS–HEMTs) that exhibited device performance superior to that of a conventional HEMT. Under similar bias conditions, the gate leakage currents of these MOS–HEMT devices were four orders of magnitude lower than those of conventional Schottky gate HEMTs. The measured sub-threshold swing (SS) and the effective trap state density (N{sub t}) of the MOS–HEMT were 125 mV/decade and 4.3 × 10{sup 12} cm{sup −2}, respectively. The dielectric constant of the Er{sub 2}O{sub 3} layer in this study was 14, as determined through capacitance–voltage measurements. In addition, the gate–source reverse breakdown voltage increased from –166 V for the conventional HEMT to –196 V for the Er{sub 2}O{sub 3} MOS–HEMT. - Highlights: ► GaN/AlGaN/Er{sub 2}O{sub 3} metal-oxide semiconductor high electron mobility transistor ► Physical and electrical characteristics are presented. ► Electron beam evaporated Er{sub 2}O{sub 3} with excellent surface roughness ► Device exhibits reduced gate leakage current and improved I{sub ON}/I{sub OFF} ratio.

  12. Organic Field-Effect Transistors Based on a Liquid-Crystalline Polymeric Semiconductor using SU-8 Gate Dielectrics onFlexible Substrates

    Directory of Open Access Journals (Sweden)

    Kornelius Tetzner

    2014-10-01

    Full Text Available In this work, the insulating properties of poly(4-vinylphenol (PVP and SU-8 (MicroChem, Westborough, MA, USA dielectrics are analyzed and compared with each other. We further investigate the performance behavior of organic field-effect transistors based on a semiconducting liquid-crystal polymer (LCP using both dielectric materials and evaluate the results regarding the processability. Due to the lower process temperature needed for the SU-8 deposition, the realization of organic transistors on flexible substrates is demonstrated showing comparable charge carrier mobilities to devices using PVP on glass. In addition, a µ-dispensing procedure of the LCP on SU-8 is presented, improving the switching behavior of the organic transistors, and the promising stability data of the SU-8/LCP stack are verified after storing the structures for 60 days in ambient air showing negligible irreversible degradation of the organic semiconductor.

  13. Laminated CeO2/HfO2 High-K Gate Dielectrics Grown by Pulsed Laser Deposition in Reducing Ambient

    NARCIS (Netherlands)

    Karakaya, K.; Barcones, B.; Zinine, A.; Rittersma, Z.M.; Graat, P.; Berkum, van J.G.M.; Verheijen, M.A.; Rijnders, G.; Blank, D.H.A.

    2006-01-01

    CeO2 and HfO2 dielectric layers were deposited in an Ar+(5%)H2 gas mixture by Pulsed Laser Deposition (PLD) on Si (100). A CeO2-Ce2O3 transformation is achieved by deposition in reducing ambient. It is also shown that in-situ post deposition anneal efficiently oxidizes Ce2O3 layers to CeO2. The prop

  14. Growth and characterization of MMA/SiO2 hybrid low- thin films for interlayer dielectric applications

    Indian Academy of Sciences (India)

    Bhavana N Joshi; M A More; A M Mahajan

    2010-06-01

    The methylmethacrylate (MMA) incorporated SiO2 thin films having low dielectric constant ( = 2.97) were deposited successfully to realize new interlayer material for the enhancement of electrical performance of on-chip wiring in very large scale integrated (VLSI) circuits. We have successfully incorporated MMA monomer and eliminated the polymerization step to lower the dielectric constant of deposited thin film. The presence of peak of C=C bond in Fourier transform infrared (FTIR) spectra and carbon peak in energy dispersive (EDAX) spectra confirms the incorporation of carbon in the film due to MMA. The concentration of MMA has great impact on the peak area and full width at half maxima (FWHM) of the Si–O–Si bond, which decreases the density by low atomic weight elements and consequently decreases the dielectric constant. The surface morphology analysed by scanning electron microscopic (SEM) image shows excellent uniformity of the film. The refractive index of 1.31 was measured by ellipsometer for 0.5 ml MMA concentration film. These deposited thin films having low refractive index and dielectric constant are widely applicable for the optical interconnects and interlayer applications in integrated optical circuits and VLSI circuits.

  15. Evolution of interface chemistry and dielectric properties of HfO2/Ge gate stack modulated by Gd incorporation and thermal annealing

    Directory of Open Access Journals (Sweden)

    Gang He

    2016-02-01

    Full Text Available In current work, effects of rapid thermal annealing (RTA on the interface chemistry and electrical properties of Gd-doped HfO2 (HGO/Ge stack have been investigated systematically. It has been demonstrated that the presence of GeOx interfacial layer between HfGdO and Ge is unavoidable and appropriate annealing can improve metal-oxide-semiconductor device characteristics such as interface state density, accumulation capacitance, frequency dispersion, and leakage current. The involved leakage current conduction mechanisms for metal-oxide-semiconductor (MOS capacitors based on sputtered HGO/Ge gate stacks with optimal annealed temperature also have been discussed in detail. As a result, the Al/HGO barrier height and the band offset of HGO/Ge gate stack have been determined precisely.

  16. A threshold voltage model for high-κgate-dielectric MOSFETs considering fringing-field effect

    Institute of Scientific and Technical Information of China (English)

    Ji Feng; Xu Jing-Ping; Lai Pui-To

    2007-01-01

    In this paper, a threshold voltage model for high-κgate-dielectric metal-oxide-semiconductor field-effect transistors (MOSFETs) is developed, with more accurate boundary conditions of the gate dielectric derived through a conformal mapping transformation method to consider the fringing-field effects including the influences of high-κgate-dielectric and sidewall spacer. Comparing with similar models, the proposed model can be applied to general situations where the gate dielectric and sidewall spacer can have different dielectric constants. The influences of sidewall spacer and high-κgate dielectric on fringing field distribution of the gate dielectric and thus threshold voltage behaviours of a MOSFET are discussed in detail.

  17. Gate stack technology for nanoscale devices

    Directory of Open Access Journals (Sweden)

    Byoung Hun Lee

    2006-06-01

    Full Text Available Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS field-effect transistors (FETs of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

  18. The low threshold voltage n-type silicon transistors based on a polymer/silica nanocomposite gate dielectric: The effect of annealing temperatures on their operation

    Science.gov (United States)

    Hashemi, Adeleh; Bahari, Ali; Ghasemi, Shahram

    2017-09-01

    In this work, povidone/silica nanocomposite dielectric layers were deposited on the n-type Si (100) substrates for application in n-type silicon field-effect transistors (FET). Thermogravimetric analysis (TGA) indicated that strong chemical interactions between polymer and silica nanoparticles were created. In order to examine the effect of annealing temperatures on chemical interactions and nanostructure properties, annealing process was done at 423-513 K. Atomic force microscopy (AFM) images show the very smooth surfaces with very low surface roughness (0.038-0.088 nm). The Si2p and C1s core level photoemission spectra were deconvoluted to the chemical environments of Si and C atoms respectively. The obtained results of deconvoluted X-ray photoelectron spectroscopy (XPS) spectra revealed a high percentage of silanol hydrogen bonds in the sample which was not annealed. These bonds were inversed to stronger covalence bonds (siloxan bonds) at annealing temperature of 423 K. By further addition of temperature, siloxan bonds were shifted to lower binding energy of about 1 eV and their intensity were abated at annealing temperature of 513 K. The electrical characteristics were extracted from current-Voltage (I-V) and capacitance-voltage (C-V) measurements in metal-insulator-semiconductor (MIS) structure. The all n-type Si transistors showed very low threshold voltages (-0.24 to 1 V). The formation of the strongest cross-linking at nanostructure of dielectric film annealed at 423 K caused resulted in an un-trapped path for the transport of charge carriers yielding the lowest threshold voltage (0.08 V) and the highest electron mobility (45.01 cm2/V s) for its FET. By increasing the annealing temperature (473 and 513 K) on the nanocomposite dielectric films, the values of the average surface roughness, the capacitance and the FET threshold voltage increased and the value of FET electron field-effect mobility decreased.

  19. Self-aligned inversion n-channel In 0.2Ga 0.8As/GaAs metal-oxide-semiconductor field-effect-transistors with TiN gate and Ga 2O 3(Gd 2O 3) dielectric

    Science.gov (United States)

    Chen, C. P.; Lin, T. D.; Lee, Y. J.; Chang, Y. C.; Hong, M.; Kwo, J.

    2008-10-01

    A self-aligned process for fabricating inversion n-channel metal-oxide-semiconductor field-effect-transistors (MOSFET's) of strained In 0.2Ga 0.8As on GaAs using TiN as gate metal and Ga 2O 3(Gd 2O 3) as high κ gate dielectric has been developed. A MOSFET with a 4 μm gate length and a 100 μm gate width exhibits a drain current of 1.5 mA/mm at Vg = 4 V and Vd = 2 V, a low gate leakage of extrinsic transconductance of 1.7 mS/mm at Vg = 3 V, Vd = 2 V, and an on/off ratio of ˜10 5 in drain current. For comparison, a TiN/Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As MOS diode after rapid thermal annealing (RTA) to high temperatures of 750 °C exhibits excellent electrical and structural performances: a low leakage current density of 10 -8-10 -9 A/cm 2, well-behaved capacitance-voltage ( C- V) characteristics giving a high dielectric constant of ˜16 and a low interfacial density of state of ˜(2˜6) × 10 11 cm -2 eV -1, and an atomically sharp smooth Ga 2O 3(Gd 2O 3)/In 0.2Ga 0.8As interface.

  20. Gate-Induced Thermally Stimulated Current on the Ferroelectric-like Dielectric Properties of (BEDT-TTF(TCNQ Crystalline Field Effect Transistor

    Directory of Open Access Journals (Sweden)

    Kazuhiro Kudo

    2012-06-01

    Full Text Available A gate-induced thermally stimulated current (TSC on β′-(BEDT-TTF(TCNQ crystalline FET were conducted to elucidate the previously observed ferroelectric-like behaviors. TSC which is symmetric for the polarization of an applied VPG and has a peak at around 285 K was assigned as a pyroelectric current. By integrating the pyroelectric current, temperature dependence of the remnant polarization charge was obtained and the existence of the ferroelectric phase transition at 285 K was clearly demonstrated. We have tentatively concluded that the phase transition between dimer Mott insulator and charge ordered phase occurred at around the interface of organic crystal and substrate.

  1. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    Directory of Open Access Journals (Sweden)

    H. Hussin

    2014-01-01

    Full Text Available We present a simulation study on negative bias temperature instability (NBTI induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2 and hafnium oxide (HfO2 layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

  2. All-optical logic gate based on transient grating from disperse red 1 doped organic-inorganic hybrid films with an improved figure of merit

    Energy Technology Data Exchange (ETDEWEB)

    Gao, Tianxi; Que, Wenxiu, E-mail: wxque@mail.xjtu.edu.cn; Shao, Jinyou [Electronic Materials Research Laboratory, Key Laboratory of the Ministry of Education, International Center for Dielectric Research, School of Electronic and Information Engineering, State Key Laboratory for Manufacturing Systems Engineering, Xi' an Jiaotong University, Xi' an 710049, Shaanxi (China); Wang, Yushu [School of Materials Science and Engineering, Georgia Institute of Technology, 500 Tenth Street NW, Atlanta, Georgia 30318 (United States)

    2015-10-21

    Azobenzene dyes have large refractive index near their main resonance, but the poor figure of merit (FOM) limits their potential for all-optical applications. To improve this situation, disperse red 1 (DR1) molecules were dispersed in a sol-gel germanium/Ormosil organic-inorganic hybrid matrix. Z-scan measurement results showed a good compatibility between the dopant and the matrix, and also, an improved FOM was obtained as compared to the DR1/polymer films reported previously. To demonstrate the all-optical signal processing effect, a cw Nd:YAG laser emitting at 532 nm and a He-Ne laser emitting at 632.8 nm were used as pump and probe beams, respectively. DR1 acts as an initiator of the photo-induced transient holographic grating, which is attributed to the trans-cis-trans photoisomerization. Thus, a three inputs AND all-optical logic gate was achieved by using choppers with different frequencies. The detailed mechanism of operation is discussed. These results indicate that the DR1 doped germanium/Ormosil organic-inorganic hybrid film with an improved FOM has a great potential in all-optical devices around its main resonance.

  3. Microwave absorption of a TiO2@PPy hybrid and its nonlinear dielectric resonant attenuation mechanism

    Science.gov (United States)

    Jiang, Wanchun; Wang, Yu; Xie, Aming; Wu, Fan

    2016-09-01

    We report on a high-performance electromagnetic absorption material (TiO2@PPy) developed via a facile in situ polymerization process, where lower than  -60 dB maximum absorption and 6.56 dB effective absorption bandwidth (lower than  -10 dB) can be obtained under low thickness. The excellent electromagnetic wave absorption ability is attributed to the synthetic effect of improved impedance matching and the dual loss mechanism, which originates from the polarization relaxations of dipoles induced by vacancy defects and a conductive network constructed by aerogels. An equivalent circuit model is established to explicate the nonlinear dielectric resonant attenuation mechanism.

  4. Growth and Current Leakage Characteristics of SrHfON High-k Gate Dielectric Films%SrHfON高κ栅介质薄膜的漏电特性研究

    Institute of Scientific and Technical Information of China (English)

    王雪梅; 刘正堂; 冯丽萍

    2013-01-01

    采用射频反应磁控溅射法在p-Si(100)衬底上成功制备出SrHfON高k栅介质薄膜,并研究了Au/SrHfON/Si MOS电容的漏电流机制及应力感应漏电流(SILC)效应.结果表明,MOS电容的漏电流密度随N2流量的增加而减小.在正栅压下,漏电流主要由Schottky发射机制引起;在负栅压下,漏电流机制在低、中、高栅电场区时分别为Schottky发射、F-P发射和F-N隧穿机制.同时,Au/SrHfON/Si MOS电容表现出明显的SILC效应,经恒压应力后薄膜在正栅压下的漏电流由Schouky发射和F-P发射机制共同作用,且后者占主导地位.%The SrHfON high-κ gate dielectric films,deposited by RF reactive magnetron sputtering on p-type Si (100)substrates,were used to fabricate the Au/SrHfON/Si MOS capacitor.The impacts of the growth conditions on the leakage current density were evaluated with X-ray photoelectron spectroscopy and conventional proves.The leakage current conduction mechanisms and the stress induced leakage current(SILC) effect of the MOS capacitor were studied.The leakage current density of the MOS capacitor was found to decrease with an increase of N2 flow rate.At a positive bias of the metal gate,the leakage current mainly originated from Schottky emission,but at a negative bias,the leakage current in the low-,medium-and high-gate voltage ranges resulted from Schottky emission,Poole-Franel (F-P) emission and Fowler-Nord-heim (F-N) tunneling,respectively.In addition,the SILC effect was found to dominate the Au/SrHfON/Si MOS capacitor;but after being stressel by a constant voltage,Schottky emission outperforms F-P emission in generating the leakage current.

  5. Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high-k metal gate NMOSFET with kMC TDDB simulations

    Science.gov (United States)

    Xu, Hao; Yang, Hong; Luo, Wei-Chun; Xu, Ye-Feng; Wang, Yan-Rong; Tang, Bo; Wang, Wen-Wu; Qi, Lu-Wei; Li, Jun-Feng; Yan, Jiang; Zhu, Hui-Long; Zhao, Chao; Chen, Da-Peng; Ye, Tian-Chun

    2016-08-01

    The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high-k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it/N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. Project supported by the National High Technology Research and Development Program of China (Grant No. SS2015AA010601), the National Natural Science Foundation of China (Grant Nos. 61176091 and 61306129), and the Opening Project of Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of MicroElectronics of Chinese Academy of Sciences.

  6. Abnormal positive bias stress instability of In–Ga–Zn–O thin-film transistors with low-temperature Al{sub 2}O{sub 3} gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Chang, Yu-Hong; Yu, Ming-Jiue; Lin, Ruei-Ping; Hsu, Chih-Pin; Hou, Tuo-Hung, E-mail: thhou@mail.nctu.edu.tw [Department of Electronics Engineering and Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan (China)

    2016-01-18

    Low-temperature atomic layer deposition (ALD) was employed to deposit Al{sub 2}O{sub 3} as a gate dielectric in amorphous In–Ga–Zn–O thin-film transistors fabricated at temperatures below 120 °C. The devices exhibited a negligible threshold voltage shift (ΔV{sub T}) during negative bias stress, but a more pronounced ΔV{sub T} under positive bias stress with a characteristic turnaround behavior from a positive ΔV{sub T} to a negative ΔV{sub T}. This abnormal positive bias instability is explained using a two-process model, including both electron trapping and hydrogen release and migration. Electron trapping induces the initial positive ΔV{sub T}, which can be fitted using the stretched exponential function. The breakage of residual AlO-H bonds in low-temperature ALD Al{sub 2}O{sub 3} is triggered by the energetic channel electrons. The hydrogen atoms then diffuse toward the In–Ga–Zn–O channel and induce the negative ΔV{sub T} through electron doping with power-law time dependence. A rapid partial recovery of the negative ΔV{sub T} after stress is also observed during relaxation.

  7. Penn State DOE GATE Program

    Energy Technology Data Exchange (ETDEWEB)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  8. An amphidynamic inorganic-organic hybrid crystal of bromoplumbate with 1,5-bis(1-methylimidazolium)pentane exhibiting multi-functionality of a dielectric anomaly and temperature-dependent dual band emissions.

    Science.gov (United States)

    Tong, Yuan-Bo; Ren, Li-Te; Duan, Hai-Bao; Liu, Jian-Lan; Ren, Xiao-Ming

    2015-10-28

    Organic-inorganic hybrid crystals, [1,5-bis(1-methylimidazolium)pentane][PbBr3]2 (1), were achieved through the mutual diffusion of a bi-imidazolium based ionic liquid and PbBr2 solution of DMF in a glass tube. The hybrid solid crystallizes in the orthorhombic space group Fdd2 at room temperature; and is composed of one-dimensional [PbBr3]∞ chains where the neighbouring PbBr6 coordination octahedra are linked together via the face-sharing mode and the inorganic chains are surrounded by organic cations. The hybrid solid exhibits a dielectric anomaly around 443 K and dielectric relaxation above 400 K, the dielectric response mechanism was investigated using variable-temperature X-ray single crystal and powder diffraction as well as DSC techniques. Fascinatingly, this hybrid solid shows dual band emissions, moreover, the fluorescence nature of the two emission bands exhibits a distinct response to temperature, leading to a temperature-dependent fluorescence color, this feature has promising application in the emission temperature-sensing field.

  9. Al2O3绝缘栅SiC MIS结构基本特性的研究%Fundamental characteristics of SiC MIS structure with Al2O3 as gate dielectric

    Institute of Scientific and Technical Information of China (English)

    刘莉; 杨银堂; 马晓华

    2011-01-01

    采用原子层淀积(ALD)方法在4H-SiC(0001)8°N-/N+外延层上制备了超薄(~4 nm)Al2O3绝缘栅高介电常数SiC MIS电容.通过对Al2O3介质膜以及Al2O3/SiC界面微结构和电学特性分析表明,实验所得Al2O3介质膜具有较好的体特性和界面特性,Al2O3薄膜的击穿电场为25MV/cm,并且在可以接受的界面态密度(2×1013 cm-2)下具有较小的栅泄漏电流(8 MV/cm电场下漏电流密度为l×10-3A/cm-2).电流-电压测试分析表明,在FN隧穿条件下,SiC/A12O3之间的势垒高度为1.4 eV,已达到制作SiC MISFET器件的要求.同时,在整个栅压区域也受Frenkel-Poole和Schottkv机制的共同影响.%SiC MIS structure with ultra-thin Al2O3 as gate dielectric deposited by atomic layer deposition (ALD) on epitaxial layer of 4H-SiC(0001)8°N-/N+ substrate is fabricated.The microstructure and electrical characteristics analysis on the film and Al2O3/SiC interface has shown that Al2O3 deposited has a good bulk characteristics and a good quality between Al2O3 and SiC.The breakdown electrical field of Al2O3 film is 25 MV/cm; the MIS capacitor has a fairly low gate leakage current (current density of 1×10-3A/cm-2 with a electric field of 8 MV/cm) under acceptable interface effective charge (2× 1013 cm-2).Current-voltage measurement and analysis has shown that when the gate leakage current mechanism is dominated by FN tunneling, the barrier height of SiC/Al2O3 is 1.4 eV,which can meet the requirement of SiC MISFET devices.Besides this, the gate leakage current is co-influenced by both of Frenkel-Poole mechanism and Schottky emission.

  10. Computational Fluid Dynamics Study of Molten Steel Flow Patterns and Particle-Wall Interactions Inside a Slide-Gate Nozzle by a Hybrid Turbulent Model

    Science.gov (United States)

    Mohammadi-Ghaleni, Mahdi; Asle Zaeem, Mohsen; Smith, Jeffrey D.; O'Malley, Ronald

    2016-10-01

    Melt flow patterns and turbulence inside a slide-gate throttled submerged entry nozzle (SEN) were studied using Detached-Eddy Simulation (DES) model, which is a combination of Reynolds-Averaged Navier-Stokes (RANS) and Large-Eddy Simulation (LES) models. The DES switching criterion between RANS and LES was investigated to closely reproduce the flow structures of low and high turbulence regions similar to RANS and LES simulations, respectively. The melt flow patterns inside the nozzle were determined by k- ɛ (a RANS model), LES, and DES turbulent models, and convergence studies were performed to ensure reliability of the results. Results showed that the DES model has significant advantages over the standard k- ɛ model in transient simulations and in regions containing flow separation from the nozzle surface. Moreover, due to applying a hybrid approach, DES uses a RANS model at wall boundaries which resolves the extremely fine mesh requirement of LES simulations, and therefore it is computationally more efficient. Investigation of particle distribution inside the nozzle and particle adhesion to the nozzle wall also reveals that the DES model simulations predict more particle-wall interactions compared to LES model.

  11. Quasi-two-dimensional subthreshold current model of deep submicrometer SOI drive-in gate controlled hybrid transistors with lateral non-uniform doping profile

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    We have analyzed the operating mechanism of the novel deep submicrometer SOI drive-in gate controlled hybrid transistor (DGCHT), which can effectively alleviate the contradiction between speed enhancement and power reduction in conventional MOS devices and can improve the output resistance. On the basis of this, the subthreshold current model of DGCHTs is proposed. The model takes into account the impact of lateral non-uniform doping profile on body effect, short-channel effect and carrier mobility. Considering the mobile charge, two-dimensional Poisson equation is solved with quasi-two-dimensional analysis and parabolic approximation of surface potential. With the surface potential obtained, the subthreshold current is figured out, including both the diffusion and drift component. The calculated results are in good agreement with the MEDICI numerical simulation results, indicating the correct description of the current characteristics of SOI DGCHT by the presented model. The model can also be considered as an important reference to the current simulation of deep submicrometer MOSFET with pocket implantation.

  12. Impact of Gd{sub 2}O{sub 3} passivation layer on interfacial and electrical properties of atomic-layer-deposited ZrO{sub 2} gate dielectric on GaAs

    Energy Technology Data Exchange (ETDEWEB)

    Gong, Youpin; Zhai, Haifa; Liu, Xiaojie; Kong, Jizhou; Wu, Di; Li, Aidong, E-mail: adli@nju.edu.cn

    2014-02-01

    ZrO{sub 2} gate dielectric films were fabricated on n-GaAs substrates by atomic layer deposition (ALD), using metal organic chemical vapor deposition (MOCVD)-derived ultrathin Gd{sub 2}O{sub 3} film as interfacial control layer between ZrO{sub 2} and n-GaAs. The interfacial structure, capacitance–voltage and current–voltage properties of ZrO{sub 2}/n-GaAs and ZrO{sub 2}/Gd{sub 2}O{sub 3}/n-GaAs metal-oxide-semiconductor (MOS) capacitors have been investigated. The introduction of an ultrathin Gd{sub 2}O{sub 3} control layer can effectively suppress the formation of As oxides and high valence Ga oxide at the high k/GaAs interface which evidently improved the electrical properties of GaAs-based MOS capacitors, such as higher accumulation capacitance and lower leakage current density. It was found that the current conduction mechanism of MOS capacitors varied from Poole–Frenkel emission to Schottky–Richardson emission after introducing the thin Gd{sub 2}O{sub 3} layer. The band alignments of interfaces for ZrO{sub 2}/GaAs and ZrO{sub 2}/Gd{sub 2}O{sub 3}/GaAs were established, which indicates that the conduction band offset (CBO) for ZrO{sub 2}/GaAs and ZrO{sub 2}/Gd{sub 2}O{sub 3}/GaAs stacks are ∼1.45 and ∼1.62 eV, correspondingly.

  13. Forward gated-diode method for parameter extraction of MOSFETs*

    Institute of Scientific and Technical Information of China (English)

    Zhang Chenfei; Ma Chenyue; Guo Xinjie; Zhang Xiufang; He Jin; Wang Guozeng; Yang Zhang; Liu Zhiwei

    2011-01-01

    The forward gated-diode method is used to extract the dielectric oxide thickness and body doping concentration of MOSFETs, especially when both of the variables are unknown previously. First, the dielectric oxide thickness and the body doping concentration as a function of forward gated-diode peak recombination-generation (R-G) current are derived from the device physics. Then the peak R-G current characteristics of the MOSFETs with different dielectric oxide thicknesses and body doping concentrations are simulated with ISE-Dessis for parameter extraction. The results from the simulation data demonstrate excellent agreement with those extracted from the forward gated-diode method.

  14. Characterization of high-k gate dielectrics by atomic-resolution electron microscopy: current progress and future prospects%高k栅介质原子分辨率的电镜表征:研究进展和展望

    Institute of Scientific and Technical Information of China (English)

    朱信华; 朱健民; 刘治国; 闵乃本

    2009-01-01

    -resolution spectroscopy techniques such as EELS and EDS are first introduced. Second, applications of HRTEM/STEM to structural characterizing high-k gate materials, including Hf-bnsed oxides, rare-earth oxides, and epitaxial perovskite oxides, are critically reviewed. Finally, we conclude this review with personal perspectives towards the future prospects of the characterization of highk gate dielectrics at sub-angstrom level.%随着特征尺寸不断缩小,CMOS器件已步入纳米尺度范围,因此纳米尺度器件的结构表征变得尤为关键.完备的半导体器件结构分析,要求确定原子位置、局部化学元素组成及局域电子结构.高分辨(分析型)透射电镜及其显微分析技术,能够提供衍衬像(振幅衬度像)、高分辨像(相位衬度像)、选区电子衍射和会聚束电子衍射、X射线能谱(EDS)及电子能量损失谱(EELS)等分析手段,已作为半导体器件结构表征的基本工具.配有高角度环形暗场探测器的扫描透射电镜(STEM),因其像的强度近似正比于原子序数(Z)的平方,它可在原子尺度直接确定材料的结构和化学组成.利用Z-衬度像配合高分辨电子能量损失谱技术,可确定新型CMOS堆垛层中的界面结构、界面及界面附近的元素分布及化学环境.近年来新开发的球差校正器使得HRTEM/STEM的分辨率得到革命性提高(空间分辨率优于0.08 nm,能量分辨率优于0.2 ev),在亚埃尺度上实现单个纳米器件的结构表征.装备球差校正器的新一代HRTEM和STEM,使得高k栅介质材料的研究进入一个新时代.本文首先介绍了-原子分辨率电镜(HRTEM和STEM)的基本原理和关键特征,对相关高分辨谱分析技术(如EDS和EELS)加以比较;然后综述了HRTEMISTEM在高k栅介质材料(如铪基氧化物、稀土氧化物和外延钙钛矿结构氧化物)结构表征方面的最新进展;最后对亚埃分辨率高k栅介质材料的结构表征进行了展望.

  15. Study on Nanometer Hybrid Low Dielectric Constant Materials from Polyhedral Oligosilsesquioixanes%多面体笼型倍半硅氧烷纳米杂化低介电材料的研究

    Institute of Scientific and Technical Information of China (English)

    徐洪耀; 严正权; 张超; 苏新艳; 光善仪

    2011-01-01

    多面体笼型倍半硅氧烷( POSS)由O-Si-O链接的纳米尺寸的笼型无机芯[(SiO1.5)n]和外围有机取代基团(活性或惰性)组成,这种独特的结构为杂化功能材料的制备提供了重要的平台与基础.本文从低介电材料结构对其件能的影响以及低介电性能的形成机理等方面综述了低介电材料的制备方法,尤其是POSS在低介电材料控制制备的研究进展,为该领域新材料的设计提供借鉴.%Polyhedral oligosilsesquioixanes(POSS) is a nanosized organic-inorganic hybrid molecule, which consists of a well-defined cage-like nano inorganic core[ (SiO1.5) ? ] surrounded by organic corner groups. The unique structure of POSS molecules provide an important platform for controllable preparation of hybrid nano-composites in molecular level dispersion. In this paper, the influence of hybrid molecular structure on properties and forming mechanism of low dielectric constant, in particular, the research progress of POSS-based nanocomposite low dielectric constant materials were summarized.

  16. Paired-pulse facilitation achieved in protonic/electronic hybrid indium gallium zinc oxide synaptic transistors

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Li Qiang, E-mail: guoliqiang@ujs.edu.cn; Ding, Jian Ning; Huang, Yu Kai [Micro/Nano Science & Technology Center, Jiangsu University, Zhenjiang, 212013 (China); Zhu, Li Qiang, E-mail: lqzhu@nimte.ac.cn [Ningbo Institute of Materials Technology and Engineering, Chinese Academy of Sciences, Ningbo 315201 (China)

    2015-08-15

    Neuromorphic devices with paired pulse facilitation emulating that of biological synapses are the key to develop artificial neural networks. Here, phosphorus-doped nanogranular SiO{sub 2} electrolyte is used as gate dielectric for protonic/electronic hybrid indium gallium zinc oxide (IGZO) synaptic transistor. In such synaptic transistors, protons within the SiO{sub 2} electrolyte are deemed as neurotransmitters of biological synapses. Paired-pulse facilitation (PPF) behaviors for the analogous information were mimicked. The temperature dependent PPF behaviors were also investigated systematically. The results indicate that the protonic/electronic hybrid IGZO synaptic transistors would be promising candidates for inorganic synapses in artificial neural network applications.

  17. Electrical characterization of advanced gate dielectrics

    NARCIS (Netherlands)

    Degraeve, R.; Schmitz, J.; Pantisano, L.; Simoen, E.; Houssa, M.; Kaczer, B.; Groeseneken, G.; Baklanov, M.; Green, M.; Maex, K.

    2007-01-01

    The topic of thin films is an area of increasing importance in materials science, electrical engineering and applied solid state physics; with both research and industrial applications in microelectronics, computer manufacturing, and physical devices. Advanced, high-performance computers, high-defin

  18. Determination of the electronic, dielectric, and optical properties of sillenite Bi12TiO20 and perovskite-like Bi4Ti3O12 materials from hybrid first-principle calculations

    KAUST Repository

    Lardhi, Sheikha F.

    2016-04-05

    Density functional theory calculation was conducted to determine the optoelectronic properties of bismuthtitanate sillenite (Bi12TiO20) and perovskite-like (Bi4Ti3O12) structures. The lattice parameters were experimentally obtained from Rietveld analysis. The density functional perturbation theory approach was used with the standard Perdew–Burke–Ernzerhof functional and screened Coulomb hybrid Heyd–Scuseria–Ernzerhof functional to investigate the electronic structure and absorption coefficient. Both compounds have good carrier transport properties, low effective hole and electron masses, high dielectric constant, and low exciton binding energy.

  19. Dielectric Metamaterials

    Science.gov (United States)

    2015-05-29

    Final Report  29 May 2015 Dielectric Metamaterials SRI Project P21340 ONR Contract N00014-12-1-0722 Prepared by: Srini Krishnamurthy...2 2. Theory of Metamaterials ....................................................................................................... 2 2.1...accurately assess the impact of various forms of disorder on metamaterials (MMs) (both dielectric and metal inclusions); and (5) identify designs

  20. Electrical Characteristics of Copper Phthalocyanine Thin-Film Transistors with Polyamide-6/Polytetrafluoroethylene Gate Insulator

    Institute of Scientific and Technical Information of China (English)

    YU Shun-Yang; XU Shi-Ai; MA Dong-Ge

    2007-01-01

    Polyamide-6(PA 6)/polytetrafluoroethylene is studied as a potential gate dielectric for flexible organic thin film transistors.The salne method used for the formation of organic semiconductor and gate dielectric films greatly simplifies the fabrication process of devices.The fabricated transistors show good electrical characteristics.Ambipolar behaviour is observed even when the device is operated in air.

  1. Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta2O5)x(Al2O3)1-x as potential gate dielectrics for GaN/AlxGa1-xN/GaN high electron mobility transistors

    Science.gov (United States)

    Partida-Manzanera, T.; Roberts, J. W.; Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Sedghi, N.; Tripathy, S.; Potter, R. J.

    2016-01-01

    This paper describes a method to optimally combine wide band gap Al2O3 with high dielectric constant (high-κ) Ta2O5 for gate dielectric applications. (Ta2O5)x(Al2O3)1-x thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped AlxGa1-xN/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta2O5 molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al2O3 to 4.6 eV for pure Ta2O5. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al2O3 up to 25.6 for Ta2O5. The effect of post-deposition annealing in N2 at 600 °C on the interfacial properties of undoped Al2O3 and Ta-doped (Ta2O5)0.12(Al2O3)0.88 films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al2O3/GaN-HEMT and (Ta2O5)0.16(Al2O3)0.84/GaN-HEMT samples increased by ˜1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al2O3 can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

  2. Phase transitions and dielectric properties of a hexagonal ABX3 perovskite-type organic-inorganic hybrid compound: [C3H4NS][CdBr3].

    Science.gov (United States)

    Liao, Wei-Qiang; Ye, Heng-Yun; Zhang, Yi; Xiong, Ren-Gen

    2015-06-21

    A new organic-inorganic hexagonal perovskite-type compound with the formula ABX3, thiazolium tribromocadmate(ii) (1), in which thiazolium cations are situated in the space between the one-dimensional chains of face-sharing CdBr(6) octahedra, has been successfully synthesized. Systematic characterizations including differential scanning calorimetry measurements, variable-temperature structural analyses, and dielectric measurements reveal that it undergoes two structural phase transitions, at 180 and 146 K. These phase transitions are accompanied by remarkable dielectric relaxation and anisotropy. The thiazolium cations remain orientationally disordered during the two phase transition processes. The origins of the phase transitions at 180 and 146 K are ascribed to the slowing down and reorientation of the molecular motions of the cations, respectively. Moreover, the dielectric relaxation process well described by the Cole-Cole equation and the prominent dielectric anisotropy are also connected with the dynamics of the dipolar thiazolium cations.

  3. Study of HV Dielectrics for High Frequency Operation in Linear & Nonlinear Transmission Lines & Simulation & Development of Hybrid Nonlinear Lines for RF Generation

    Science.gov (United States)

    2015-08-27

    The high voltage diodes D5 to D10 are used to protect the HV switch against negative back swing voltage, while D4 diode for reverse current ...AFRL-AFOSR-CL-TR-2015-0001 STUDY OF HV DIELECTRICS FOR HIGH FREQUENCY OPERATION IN LINEAR & NONLINEAR TRANSMISSION LINES & SIMULATION & DEVELOPMENT...AFOSR Final Performance Report Study of HV Dielectrics for High Frequency Operation in Linear and Nonlinear Transmission Lines and Simulation

  4. Study of HV Dielectrics for High Frequency Operation in Linear and Nonlinear Transmission Lines (NLTLs) and Simulation and Development of Hybrid Nonlinear Lines for RF Generation

    Science.gov (United States)

    2016-01-27

    have better performance than BT-based dielectrics in this frequency range because of the PZT lower loss tangent. The reason is that PZT dielectric...during pulse formation the top of the reflected voltage pulse travels faster along the line than its bottom distorting the voltage step into a ramp... inductances due to component geometry or terminals limits the output frequency in NLTLs. As shown in Fig. 6, as expected the permittivity for all

  5. Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

    Science.gov (United States)

    Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

    2014-02-01

    High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery.

  6. Electrical properties of NiO/PVC nano hybrid composites for organic field effect transistors

    Science.gov (United States)

    Hayati, A.; Bahari, A.

    2015-01-01

    In this study, NiO/PVC nano hybrid composites have been synthesized through sol-gel method. Nano crystallites phases, crystallinity and electrical properties have been characterized using X-ray diffraction, Fourier transfer infrared radiation, scanning electron microscopy and atomic force microscopy techniques. The dielectric constant of the samples has been calculated through measuring the capacity of samples by application of GPS 132 A. Obtained results have indicated that an NiO/PVC sample with 5 g NiO and 0.02 g PVC, equivalent to 0.4 %wt PVC, in weight synthesis, at a temperature of 80 °C has a higher dielectric constant, better surface morphology, less rough surface, less leakage current, and thus has potential to be suggested as a possible gate dielectric material for future organic field effect transistor devices.

  7. New trends in Brunner's relation: dielectric levels

    Science.gov (United States)

    Trouiller, Yorick; Didiergeorges, Anne; Fanget, Gilles L.; Laviron, Cyrille; Comboure, Corinne; Quere, Yves

    1999-07-01

    The goal of this paper is to understand the optical phenomena at dielectric levels. The purpose is also to quantify the impact of dielectric and resist thickness variations on the CD range with and without Bottom Anti Reflective COating (BARC). First we will show how all dielectric levels can be reduced to the stack metal/oxide/BARC/resist, and what are the contributions to resists and dielectric thickness range for each levels. Then a simple model will be developed to understand CD variation in this tack: by extending the Perot/Fabry model to the dielectric levels, developed by Brunner for the gate level, we can obtain a simple relation between the CD variation and all parameters. Experimentally CD variation for Damascene line level on 0.18micrometers technology has been measured depending on oxide thickness and resist thickness and can confirm this model. UV5 resist, AR2 BARC from Shipley and Top ARC from JSR have been used for these experiments. The main conclusions are: (1) Depending on your dielectric deposition and CMP processes, if resist thickness is controlled, a standard BARC process used for the gate is adapted to remove oxide thickness variation influence providing the optimized resist thickness is used. (2) If both resist thickness and dielectric thickness are uncontrolled, a more absorbent BARC is required.

  8. Utilization of a Buffered Dielectric to Achieve High Field-Effect Carrier Mobility in Graphene Transistors

    OpenAIRE

    Farmer, Damon B.; Chiu, Hsin-Ying; Lin, Yu-Ming; Jenkins, Keith A.; Xia, Fengnian; Avouris, Phaedon

    2009-01-01

    We utilize an organic polymer buffer layer between graphene and conventional gate dielectrics in top-gated graphene transistors. Unlike other insulators, this dielectric stack does not significantly degrade carrier mobility, allowing for high field-effect mobilities to be retained in top-gate operation. This is demonstrated in both two-point and four-point analysis, and in the high-frequency operation of a graphene transistor. Temperature dependence of the carrier mobility suggests that phono...

  9. Self-aligned local electrolyte gating of 2D materials with nanoscale resolution

    CERN Document Server

    Peng, Cheng; Nanot, Sebastien; Shiue, Ren-Jye; Grosso, Gabriele; Yang, Yafang; Hempel, Marek; Jarillo-Herrero, Pablo; Kong, Jing; Koppens, Frank H L; Englund, Dirk

    2016-01-01

    In the effort to make 2D materials-based devices smaller, faster, and more efficient, it is important to control charge carrier at lengths approaching the nanometer scale. Traditional gating techniques based on capacitive coupling through a gate dielectric cannot generate strong and uniform electric fields at this scale due to divergence of the fields in dielectrics. This field divergence limits the gating strength, boundary sharpness, and pitch size of periodic structures, and restricts possible geometries of local gates (due to wire packaging), precluding certain device concepts, such as plasmonics and transformation optics based on metamaterials. Here we present a new gating concept based on a dielectric-free self-aligned electrolyte technique that allows spatially modulating charges with nanometer resolution. We employ a combination of a solid-polymer electrolyte gate and an ion-impenetrable e-beam-defined resist mask to locally create excess charges on top of the gated surface. Electrostatic simulations ...

  10. Automatic parameter extraction technique for gate leakage current modeling in double gate MOSFET

    Science.gov (United States)

    Darbandy, Ghader; Gneiting, Thomas; Alius, Heidrun; Alvarado, Joaquín; Cerdeira, Antonio; Iñiguez, Benjamin

    2013-11-01

    Direct Tunneling (DT) and Trap Assisted Tunneling (TAT) gate leakage current parameters have been extracted and verified considering automatic parameter extraction approach. The industry standard package IC-CAP is used to extract our leakage current model parameters. The model is coded in Verilog-A and the comparison between the model and measured data allows to obtain the model parameter values and parameters correlations/relations. The model and parameter extraction techniques have been used to study the impact of parameters in the gate leakage current based on the extracted parameter values. It is shown that the gate leakage current depends on the interfacial barrier height more strongly than the barrier height of the dielectric layer. There is almost the same scenario with respect to the carrier effective masses into the interfacial layer and the dielectric layer. The comparison between the simulated results and available measured gate leakage current transistor characteristics of Trigate MOSFETs shows good agreement.

  11. Dual-gate thin-film transistors, integrated circuits and sensors

    NARCIS (Netherlands)

    Spijkman, M.-J.; Myny, K.; Smits, E.C.P.; Heremans, P.; Blom, P.W.M.; Leeuw, D.M. de

    2011-01-01

    The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the f

  12. Dual-Gate Thin-Film Transistors, Integrated Circuits and Sensors

    NARCIS (Netherlands)

    Spijkman, Mark-Jan; Myny, Kris; Smits, Edsger C. P.; Heremans, Paul; Blom, Paul W. M.; de Leeuw, Dago M.

    2011-01-01

    The first dual-gate thin-film transistor (DGTFT) was reported in 1981 with CdSe as the semiconductor. Other TFT technologies such as a-Si:H and organic semiconductors have led to additional ways of making DGTFTs. DGTFTs contain a second gate dielectric with a second gate positioned opposite of the f

  13. Hybrid quantum information processing

    Energy Technology Data Exchange (ETDEWEB)

    Furusawa, Akira [Department of Applied Physics, School of Engineering, The University of Tokyo (Japan)

    2014-12-04

    I will briefly explain the definition and advantage of hybrid quantum information processing, which is hybridization of qubit and continuous-variable technologies. The final goal would be realization of universal gate sets both for qubit and continuous-variable quantum information processing with the hybrid technologies. For that purpose, qubit teleportation with a continuousvariable teleporter is one of the most important ingredients.

  14. Dielectric and Thermodynamic Signatures of Low-Temperature Glassy Dynamics in the Hybrid Perovskites CH3NH3PbI3 and HC(NH2)2PbI3.

    Science.gov (United States)

    Fabini, Douglas H; Hogan, Tom; Evans, Hayden A; Stoumpos, Constantinos C; Kanatzidis, Mercouri G; Seshadri, Ram

    2016-02-04

    Hybrid main group halide perovskites hold great technological promise in optoelectronic applications and present rich and complex evolution of structure and dynamics. Here we present low-temperature dielectric measurements and calorimetry of APbI3 [A = CH3NH3(+), HC(NH2)2(+)] that suggest glassy behavior on cooling. In both compounds, the dielectric loss displays frequency-dependent peaks below 100 K characteristic of a glassy slowing of relaxation dynamics, with HC(NH2)2PbI3 exhibiting greater glass fragility. Consistent with quenched disorder, the low-temperature heat capacity of both perovskites deviates substantially from the ∼T(3) acoustic phonon contribution predicted by the Debye model. We suggest that static disorder of the A-site molecular cation, potentially coupled to local distortions of the Pb-I sublattice, is responsible for these phenomena. The distinct low-temperature dynamics observed in these two perovskites suggest qualitative differences in the interaction between the molecular cation and the surrounding inorganic framework, with potential implications for defect screening and device performance at ambient temperatures.

  15. Chemical Gated Field Effect Transistor by Hybrid Integration of One-Dimensional Silicon Nanowire and Two-Dimensional Tin Oxide Thin Film for Low Power Gas Sensor.

    Science.gov (United States)

    Han, Jin-Woo; Rim, Taiuk; Baek, Chang-Ki; Meyyappan, M

    2015-09-30

    Gas sensors based on metal-oxide-semiconductor transistor with the polysilicon gate replaced by a gas sensitive thin film have been around for over 50 years. These are not suitable for the emerging mobile and wearable sensor platforms due to operating voltages and powers far exceeding the supply capability of batteries. Here we present a novel approach to decouple the chemically sensitive region from the conducting channel for reducing the drive voltage and increasing reliability. This chemically gated field effect transistor uses silicon nanowire for the current conduction channel with a tin oxide film on top of the nanowire serving as the gas sensitive medium. The potential change induced by the molecular adsorption and desorption allows the electrically floating tin oxide film to gate the silicon channel. As the device is designed to be normally off, the power is consumed only during the gas sensing event. This feature is attractive for the battery operated sensor and wearable electronics. In addition, the decoupling of the chemical reaction and the current conduction regions allows the gas sensitive material to be free from electrical stress, thus increasing reliability. The device shows excellent gas sensitivity to the tested analytes relative to conventional metal oxide transistors and resistive sensors.

  16. Organic nanodielectrics for low voltage carbon nanotube thin film transistors and complementary logic gates.

    Science.gov (United States)

    Hur, Seung-Hyun; Yoon, Myung-Han; Gaur, Anshu; Shim, Moonsub; Facchetti, Antonio; Marks, Tobin J; Rogers, John A

    2005-10-12

    We report the implementation of three dimensionally cross-linked, organic nanodielectric multilayers as ultrathin gate dielectrics for a type of thin film transistor device that uses networks of single-walled carbon nanotubes as effective semiconductor thin films. Unipolar n- and p-channel devices are demonstrated by use of polymer coatings to control the behavior of the networks. Monolithically integrating these devices yields complementary logic gates. The organic multilayers provide exceptionally good gate dielectrics for these systems and allow for low voltage, low hysteresis operation. The excellent performance characteristics suggest that organic dielectrics of this general type could provide a promising path to SWNT-based thin film electronics.

  17. Theory aided design and analysis of dielectric and semiconductor components for organic field-effect transistors

    Science.gov (United States)

    Dibenedetto, Sara Arlene

    Perfluoroacyl/acyl-derivatized quaterthiophens are developed and synthesized. The frontier molecular orbital energies of these compounds are studied by optical spectroscopy and electrochemistry while solid-state/film properties are investigated by thermal analysis, x-ray diffraction, and scanning electron microscopy. Organic thin film transistors (OTFTs) performance parameters are discussed in terms of the interplay between semiconductor molecular energetics and film morphologies/microstructures. The majority charge carrier type and mobility exhibit a strong correlation with the regiochemistry of perfluoroarene incorporation. In quaterthiophene-based semiconductors, carbonyl-functionalization allows tuning of the majority carrier type from p-type to ambipolar and to n-type. In situ conversion of a p-type semiconducting film to n-type film is also demonstrated. The design of chemical and film microstructural alternative hybrid organic-inorganic gate dielectrics is described using the classic Clausius-Mossotti relation. The Maxwell-Wagner effective medium model is used to compute the effective dielectric permittivity of two types of dielectrics self-assembled nanodielectrics (SANDs) and crosslinked polymer blends (CPBs). In these calculations showing good agreement between theory and experiment, it is found that greater capacitances should be achievable with mixed composites than with layered composites. With this insight, a series of mixed metal oxide-polyolefin nanocomposites is synthesized via in-situ olefin polymerization using the single-site metallocene catalysts. By integrating organic and inorganic constituents, the resulting hybrid material exhibit high permittivity (from the inorganic inclusions) and high breakdown strength, mechanical flexibility, and facile processability (from the polymer matrices). In order to better optimize the capacitance and leakage current of hybrid organic-inorganic dielectrics, the capacitance, leakage current and OFET gate

  18. Comparative analysis of the effects of tantalum doping and annealing on atomic layer deposited (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} as potential gate dielectrics for GaN/Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistors

    Energy Technology Data Exchange (ETDEWEB)

    Partida-Manzanera, T., E-mail: sgtparti@liv.ac.uk [Centre for Materials and Structures, School of Engineering, University of Liverpool, Liverpool, L69 3GH (United Kingdom); Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research), Innovis, 2 Fusionopolis way, Singapore 138634 (Singapore); Roberts, J. W.; Sedghi, N.; Potter, R. J. [Centre for Materials and Structures, School of Engineering, University of Liverpool, Liverpool, L69 3GH (United Kingdom); Bhat, T. N.; Zhang, Z.; Tan, H. R.; Dolmanan, S. B.; Tripathy, S. [Institute of Materials Research and Engineering, A*STAR (Agency for Science, Technology and Research), Innovis, 2 Fusionopolis way, Singapore 138634 (Singapore)

    2016-01-14

    This paper describes a method to optimally combine wide band gap Al{sub 2}O{sub 3} with high dielectric constant (high-κ) Ta{sub 2}O{sub 5} for gate dielectric applications. (Ta{sub 2}O{sub 5}){sub x}(Al{sub 2}O{sub 3}){sub 1−x} thin films deposited by thermal atomic layer deposition (ALD) on GaN-capped Al{sub x}Ga{sub 1−x}N/GaN high electron mobility transistor (HEMT) structures have been studied as a function of the Ta{sub 2}O{sub 5} molar fraction. X-ray photoelectron spectroscopy shows that the bandgap of the oxide films linearly decreases from 6.5 eV for pure Al{sub 2}O{sub 3} to 4.6 eV for pure Ta{sub 2}O{sub 5}. The dielectric constant calculated from capacitance-voltage measurements also increases linearly from 7.8 for Al{sub 2}O{sub 3} up to 25.6 for Ta{sub 2}O{sub 5}. The effect of post-deposition annealing in N{sub 2} at 600 °C on the interfacial properties of undoped Al{sub 2}O{sub 3} and Ta-doped (Ta{sub 2}O{sub 5}){sub 0.12}(Al{sub 2}O{sub 3}){sub 0.88} films grown on GaN-HEMTs has been investigated. These conditions are analogous to the conditions used for source/drain contact formation in gate-first HEMT technology. A reduction of the Ga-O to Ga-N bond ratios at the oxide/HEMT interfaces is observed after annealing, which is attributed to a reduction of interstitial oxygen-related defects. As a result, the conduction band offsets (CBOs) of the Al{sub 2}O{sub 3}/GaN-HEMT and (Ta{sub 2}O{sub 5}){sub 0.16}(Al{sub 2}O{sub 3}){sub 0.84}/GaN-HEMT samples increased by ∼1.1 eV to 2.8 eV and 2.6 eV, respectively, which is advantageous for n-type HEMTs. The results demonstrate that ALD of Ta-doped Al{sub 2}O{sub 3} can be used to control the properties of the gate dielectric, allowing the κ-value to be increased, while still maintaining a sufficient CBO to the GaN-HEMT structure for low leakage currents.

  19. Organic transistors making use of room temperature ionic liquids as gating medium

    Science.gov (United States)

    Hoyos, Jonathan Javier Sayago

    The ability to couple ionic and electronic transport in organic transistors, based on pi conjugated organic materials for the transistor channel, can be particularly interesting to achieve low voltage transistor operation, i.e. below 1 V. The operation voltage in typical organic transistors based on conventional dielectrics (200 nm thick SiO2) is commonly higher than 10 V. Electrolyte-gated (EG) transistors, i.e. employing an electrolyte as the gating medium, permit current modulations of several orders of magnitude at relatively low gate voltages thanks to the exceptionally high capacitance at the electrolyte/transistor channel interface, in turn due to the low thickness (ca. 3 nm) of the electrical double layers forming at the electrolyte/semiconductor interface. Electrolytes based on room temperature ionic liquids (RTILs) are promising in EG transistor applications for their high electrochemical stability and good ionic conductivity. The main motivation behind this work is to achieve low voltage operation in organic transistors by making use of RTILs as gating medium. First we demonstrate the importance of the gate electrode material in the EG transistor performance. The use of high surface area carbon gate electrodes limits undesirable electrochemical processes and renders unnecessary the presence of a reference electrode to monitor the channel potential. This was demonstrated using activated carbon as gate electrode, the electronic conducting polymer MEH-PPV, poly[2-methoxy-5-(2'-ethylhexyloxy)-1,4-phenylene vinylene] channel material, and the ionic liquid [EMIM][TFSI] (1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide), as gating medium. Using high surface area gate electrodes resulted in sub-1 V operation and charge carrier mobilities of (1.0 +/- 0.5) x 10-2 cm2V -1s-1. A challenge in the field of EG transistors is to decrease their response time, a consequence of the slow ion redistribution in the transistor channel upon application of electric

  20. Fabrication of Ultrathin SiO2 Gate Dielectric by Direct Nitrogen Implantation into Silicon Substrate%硅衬底注氮方法制备超薄SiO2栅介质

    Institute of Scientific and Technical Information of China (English)

    许晓燕; 程行之; 黄如; 张兴

    2005-01-01

    Nitrogen implantation in silicon substrate at fixed energy of 35keV and split dose of 1014~5×1014cm-2 is performed before gate oxidation.The experiment results indicate that with the increasing of implantation dose of nitrogen,oxidation rate of gate decreases.The retardation in oxide growth is weakened due to thermal annealing after nitrogen implantation.After nitrogen is implanted at the dose of 2×1014cm-2,initial O2 injection method which is composed of an O2 injection/N2 annealing/main oxidation,is applied for preparation of 3.4nm gate oxide.Compared with the control process,which is composed of N2 annealing/main oxidation,initial O2 injection process suppresses leakage current of the gate oxide.But Qbd and HF C-V characteristics are almost identical for the samples fabricated by two different oxidation processes.%利用栅氧化前在硅衬底内注氮可抑制氧化速率的方法,制得3.4nm厚的SiO2栅介质,并将其应用于MOS电容样品的制备.研究了N+注入后在Si/SiO2中的分布及热退火对该分布的影响;考察了不同注氮剂量对栅氧化速率的影响.对MOS电容样品的I-V特性,恒流应力下的Qbd,SILC及C-V特性进行了测试,分析了不同氧化工艺条件下栅介质的性能.实验结果表明:注氮后的热退火过程会使氮在Si/SiO2界面堆积;硅衬底内注入的氮的剂量越大,对氧化速率的抑制作用越明显;高温栅氧化前进行低温预氧化的注氮样品较不进行该工艺步骤的注氮样品具有更低的低场漏电流和更小的SILC电流密度,但二者恒流应力下的Qbd值及高频C-V特性相近.

  1. Atomic-scale photonic hybrids for mid-infrared and terahertz nanophotonics

    Science.gov (United States)

    Caldwell, Joshua D.; Vurgaftman, Igor; Tischler, Joseph G.; Glembocki, Orest J.; Owrutsky, Jeffrey C.; Reinecke, Thomas L.

    2016-01-01

    The field of nanophotonics focuses on the ability to confine light to nanoscale dimensions, typically much smaller than the wavelength of light. The goal is to develop light-based technologies that are impossible with traditional optics. Subdiffractional confinement can be achieved using either surface plasmon polaritons (SPPs) or surface phonon polaritons (SPhPs). SPPs can provide a gate-tunable, broad-bandwidth response, but suffer from high optical losses; whereas SPhPs offer a relatively low-loss, crystal-dependent optical response, but only over a narrow spectral range, with limited opportunities for active tunability. Here, motivated by the recent results from monolayer graphene and multilayer hexagonal boron nitride heterostructures, we discuss the potential of electromagnetic hybrids -- materials incorporating mixtures of SPPs and SPhPs -- for overcoming the limitations of the individual polaritons. Furthermore, we also propose a new type of atomic-scale hybrid the crystalline hybrid -- where mixtures of two or more atomic-scale (~3 nm or less) polar dielectric materials lead to the creation of a new material resulting from hybridized optic phonon behaviour of the constituents, potentially allowing direct control over the dielectric function. These atomic-scale hybrids expand the toolkit of materials for mid-infrared to terahertz nanophotonics and could enable the creation of novel actively tunable, yet low-loss optics at the nanoscale.

  2. Water-gel for gating graphene transistors.

    Science.gov (United States)

    Kim, Beom Joon; Um, Soong Ho; Song, Woo Chul; Kim, Yong Ho; Kang, Moon Sung; Cho, Jeong Ho

    2014-05-14

    Water, the primary electrolyte in biology, attracts significant interest as an electrolyte-type dielectric material for transistors compatible with biological systems. Unfortunately, the fluidic nature and low ionic conductivity of water prevents its practical usage in such applications. Here, we describe the development of a solid state, megahertz-operating, water-based gate dielectric system for operating graphene transistors. The new electrolyte systems were prepared by dissolving metal-substituted DNA polyelectrolytes into water. The addition of these biocompatible polyelectrolytes induced hydrogelation to provide solid-state integrity to the system. They also enhanced the ionic conductivities of the electrolytes, which in turn led to the quick formation of an electric double layer at the graphene/electrolyte interface that is beneficial for modulating currents in graphene transistors at high frequencies. At the optimized conditions, the Na-DNA water-gel-gated flexible transistors and inverters were operated at frequencies above 1 MHz and 100 kHz, respectively.

  3. Controlling the threshold voltage of SnO2 nanowire transistors with dual in-plane-gate structures gated by chitosan proton conductors

    Science.gov (United States)

    Liu, Huixuan; Tan, Rongri

    2017-05-01

    We fabricated novel dual in-plane-gate electric-double-layer (EDL) SnO2 nanowire transistors gated by chitosan using only one transmission electron microscopy (TEM) nickel grid mask at room temperature, and we successfully controlled its threshold voltage. By changing the second in-plane gate bias from 1.0 to -1.0 V, we tuned the threshold voltage of these transistors from -0.35 to 0.21 V. Their operation voltage was 1.0 V, because the EDL gate dielectric can lead to high gate dielectric capacitance (4.24 µF/cm2). These dual in-plane-gate nanowire transistors could pave the way to useful low-voltage nanoelectronic devices.

  4. Physical Modeling of Gate-Controlled Schottky Barrier Lowering of Metal-Graphene Contacts in Top-Gated Graphene Field-Effect Transistors.

    Science.gov (United States)

    Mao, Ling-Feng; Ning, Huansheng; Huo, Zong-Liang; Wang, Jin-Yan

    2015-12-17

    A new physical model of the gate controlled Schottky barrier height (SBH) lowering in top-gated graphene field-effect transistors (GFETs) under saturation bias condition is proposed based on the energy conservation equation with the balance assumption. The theoretical prediction of the SBH lowering agrees well with the experimental data reported in literatures. The reduction of the SBH increases with the increasing of gate voltage and relative dielectric constant of the gate oxide, while it decreases with the increasing of oxide thickness, channel length and acceptor density. The magnitude of the reduction is slightly enhanced under high drain voltage. Moreover, it is found that the gate oxide materials with large relative dielectric constant (>20) have a significant effect on the gate controlled SBH lowering, implying that the energy relaxation of channel electrons should be taken into account for modeling SBH in GFETs.

  5. PI/AIN纳米复合薄膜结构与介电性能研究%Structure and Dielectric Properties of PI/AIN Hybrid Film

    Institute of Scientific and Technical Information of China (English)

    李广; 殷景华; 刘晓旭; 冯宇; 田付强; 雷清泉

    2011-01-01

    采用原位聚合法制备了聚酰亚胺/氮化铝(PI/AlN)纳米复合薄膜,用小角散射(SAXS)、扫描电镜(SEM)对薄膜进行表征,研究了不同纳米掺杂量对材料电阻率、介电常数(ε)和介质损耗因数(tanδ)的影响.结果表明,随着纳米AlN含量的增加,分形结构由质量分形转变为表面分形,当AlN含量为1%时,复合薄膜的介电常数达到最低值,电阻率提高了一个数量级;介质损耗在低频范围内明显增加;AlN的掺杂提高了纳米复合薄膜的绝缘性能.%A polyimide/aluminum nitride(PI/A1N) nano-composite film was prepared by in-situ poly merization method. The microscopic structure of the film was characterized by small angle scat tering (SAXS) and scanning electron microscope (SEM) . The effects of nano-AIN content on the volume resistivity, permittivity(e) and dielectric loss of the film were studied. The results show that with increasing the nano-AIN content, the fractal structure changes from quality fractal to surface fractal. The permittivity of the film attains the minimum value when the nano-AIN content is 1%. The volume resistivity is increased by one order of magnitude, and the dielectric loss in creases obviously in low frequency range, which indicates that the addition of A1N can improve the insulation performance.

  6. Solution-pro cessed high p erformance HIZO thin film transistor with AZO gate dielectric%溶胶凝胶法制备高性能锆铝氧化物作为绝缘层的薄膜晶体管

    Institute of Scientific and Technical Information of China (English)

    高娅娜; 李喜峰; 张建华

    2014-01-01

    本文采用溶胶凝胶法制备了锆掺杂铝氧化物(锆铝氧化物)和铪铟锌氧化物薄膜,并用于制造薄膜晶体管的绝缘层和有源层.锆铝氧化物绝缘层具有较高的介电常数,其相对介电常数为19.67,且薄膜表面光滑,致密,其表面粗糙度仅为0.31 nm.获得的薄膜晶体管具备良好的器件性能,当器件宽长比为5时,器件的饱和迁移率为21.3 cm2/V·s,阈值电压为0.3 V,开关比可以达到4.3×107,亚阈值摆幅仅有0.32 V/dec.%Hafnium indium zinc oxide (HIZO) thin film transistors with zirconium aluminum oxide (AZO) gate dielectric were fabricated by solution-process. The HIZO and AZO oxide thin films have smooth surfaces with root-mean-square roughness of 0.62 nm and 0.35 nm respectively. The thin film transistor with channel length = 6 µm and the ratio of width/length=5 exhibits a high saturation field-effect mobility of 21.3 cm2/V·s, a low threshold voltage of 0.3 V, a high on-off ratio of 4.3 × 107 and a small subthreshold swing of 0.32 V/dec. All these properties of TFT may be impacted by highly-coherent and of low trapping states interface between the AZO dielectric and HIZO semiconductors.

  7. Nonlinear metal-dielectric nanoantennas for light switching and routing

    CERN Document Server

    Noskov, R E; Kivshar, Yu S

    2012-01-01

    We introduce a novel hybrid metal-dielectric nanoantenna composed of dielectric (crystalline silicon) and metal (silver) nanoparticles. A high-permittivity dielectric nanoparticle allows to achieve effective light harvesting, and nonlinearity of a metal nanoparticle controls the radiation direction. We show that the radiation pattern of such a nanoantenna can be switched between the forward and backward directions by varying only the light intensity around the level of 11 MW/cm$^2$, with the characteristic switching time of 260 fs.

  8. Electrical properties of GaAs metal-oxide-semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal-organic vapor deposition/atomic layer deposition hybrid system

    Science.gov (United States)

    Aoki, Takeshi; Fukuhara, Noboru; Osada, Takenori; Sazawa, Hiroyuki; Hata, Masahiko; Inoue, Takayuki

    2015-08-01

    This paper presents a compressive study on the fabrication and optimization of GaAs metal-oxide-semiconductor (MOS) structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD), with an AlN interfacial passivation layer prepared in situ via metal-organic chemical vapor deposition (MOCVD). The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA) conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance-voltage (C-V) characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit) near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm-2 eV-1. Using a (111)A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  9. Electrical properties of GaAs metal–oxide–semiconductor structure comprising Al2O3 gate oxide and AlN passivation layer fabricated in situ using a metal–organic vapor deposition/atomic layer deposition hybrid system

    Directory of Open Access Journals (Sweden)

    Takeshi Aoki

    2015-08-01

    Full Text Available This paper presents a compressive study on the fabrication and optimization of GaAs metal–oxide–semiconductor (MOS structures comprising a Al2O3 gate oxide, deposited via atomic layer deposition (ALD, with an AlN interfacial passivation layer prepared in situ via metal–organic chemical vapor deposition (MOCVD. The established protocol afforded self-limiting growth of Al2O3 in the atmospheric MOCVD reactor. Consequently, this enabled successive growth of MOCVD-formed AlN and ALD-formed Al2O3 layers on the GaAs substrate. The effects of AlN thickness, post-deposition anneal (PDA conditions, and crystal orientation of the GaAs substrate on the electrical properties of the resulting MOS capacitors were investigated. Thin AlN passivation layers afforded incorporation of optimum amounts of nitrogen, leading to good capacitance–voltage (C–V characteristics with reduced frequency dispersion. In contrast, excessively thick AlN passivation layers degraded the interface, thereby increasing the interfacial density of states (Dit near the midgap and reducing the conduction band offset. To further improve the interface with the thin AlN passivation layers, the PDA conditions were optimized. Using wet nitrogen at 600 °C was effective to reduce Dit to below 2 × 1012 cm−2 eV−1. Using a (111A substrate was also effective in reducing the frequency dispersion of accumulation capacitance, thus suggesting the suppression of traps in GaAs located near the dielectric/GaAs interface. The current findings suggest that using an atmosphere ALD process with in situ AlN passivation using the current MOCVD system could be an efficient solution to improving GaAs MOS interfaces.

  10. Top-gate zinc tin oxide thin-film transistors with high bias and environmental stress stability

    Science.gov (United States)

    Fakhri, M.; Theisen, M.; Behrendt, A.; Görrn, P.; Riedl, T.

    2014-06-01

    Top gated metal-oxide thin-film transistors (TFTs) provide two benefits compared to their conventional bottom-gate counterparts: (i) The gate dielectric may concomitantly serve as encapsulation layer for the TFT channel. (ii) Damage of the dielectric due to high-energetic particles during channel deposition can be avoided. In our work, the top-gate dielectric is prepared by ozone based atomic layer deposition at low temperatures. For ultra-low gas permeation rates, we introduce nano-laminates of Al2O3/ZrO2 as dielectrics. The resulting TFTs show a superior environmental stability even at elevated temperatures. Their outstanding stability vs. bias stress is benchmarked against bottom-gate devices with encapsulation.

  11. Optimization of silver-dielectric-silver nanoshell for sensing applications

    Science.gov (United States)

    Shirzaditabar, Farzad; Saliminasab, Maryam

    2013-08-01

    In this paper, resonance light scattering (RLS) properties of a silver-dielectric-silver nanoshell, based on quasi-static approach and plasmon hybridization theory, are investigated. Scattering spectrum of silver-dielectric-silver nanoshell has two intense and clearly separated RLS peaks and provides a potential for biosensing based on surface plasmon resonance and surface-enhanced Raman scattering. The two RLS peaks in silver-dielectric-silver nanoshell are optimized by tuning the geometrical dimensions. In addition, the optimal geometry is discussed to obtain the high sensitivity of silver-dielectric-silver nanoshell. As the silver core radius increases, the sensitivity of silver-dielectric-silver nanoshell decreases whereas increasing the middle dielectric thickness increases the sensitivity of silver-dielectric-silver nanoshell.

  12. Optimization of silver-dielectric-silver nanoshell for sensing applications

    Energy Technology Data Exchange (ETDEWEB)

    Shirzaditabar, Farzad; Saliminasab, Maryam [Department of Physics, Razi University, Kermanshah 67144-15111 (Iran, Islamic Republic of)

    2013-08-15

    In this paper, resonance light scattering (RLS) properties of a silver-dielectric-silver nanoshell, based on quasi-static approach and plasmon hybridization theory, are investigated. Scattering spectrum of silver-dielectric-silver nanoshell has two intense and clearly separated RLS peaks and provides a potential for biosensing based on surface plasmon resonance and surface-enhanced Raman scattering. The two RLS peaks in silver-dielectric-silver nanoshell are optimized by tuning the geometrical dimensions. In addition, the optimal geometry is discussed to obtain the high sensitivity of silver-dielectric-silver nanoshell. As the silver core radius increases, the sensitivity of silver-dielectric-silver nanoshell decreases whereas increasing the middle dielectric thickness increases the sensitivity of silver-dielectric-silver nanoshell.

  13. Evaluation of nanocomposite gate insulators for flexible organic thin-film transistors.

    Science.gov (United States)

    Kim, Jin Soo; Cho, Sung Won; Kim, Ii; Hwang, Byeong Ung; Seol, Young Gug; Kim, Tae Woong; Lee, Nae-Eung

    2014-11-01

    To develop physically flexible electronics, high performance and mechanical stability of component materials and devices are required. For a flexible display, a backplane with flexible thin-film transistors (TFTs) must be developed. Gate insulating materials with excellent electrical and mechanical properties are highly important to the development of flexible TFTs. We investigated nanocomposite gate dielectrics composed of polyimide (PI) because of their superior thermal stability, as well as different inorganic HfO2, TiO2, and Al2O3 nanoparticles with high dielectric constants. Nanocomposite gate dielectrics of HfO2 nanoparticles and PI lowered leakage current density and increased the relative dielectric constant compared to PI solely because of a high degree of dispersion. Pentacene TFTs with HfO2 nanocomposite gate insulators also showed higher field-effect mobility (μ), smaller subthreshold swing, and an enhanced on/off current ratio (I(on/off)) compared to those of the PI gate dielectric. In addition, mechanical cyclic bending tests involving bending cycles of 2 x 10(5) time sat a bending radius of 5 mm showed improvement in electrical stability of nanocomposite gate insulators with a change in leakage current density of nanocomposite gate insulators below 30%.

  14. Dielectric metasurfaces

    Science.gov (United States)

    Valentine, Jason

    While plasmonics metasurfaces have seen much development over the past several years, they still face throughput limitations due to ohmic losses. On the other hand, dielectric resonators and associated metasurfaces can eliminate the issue of ohmic loss while still providing the freedom to engineer the optical properties of the composite. In this talk, I will present our recent efforts to harness this freedom using metasurfaces formed from silicon and fabricated using CMOS-compatible techniques. Operating in the telecommunications band, I will discuss how we have used this platform to realize a number of novel functionalities including wavefront control, near-perfect reflection, and high quality factor resonances. In many cases the optical performance of these silicon-based metasurfaces can surpass their plasmonic counterparts. Furthermore, for some cases the surfaces are more amenable to large-area fabrication techniques.

  15. Highly stable carbon nanotube top-gate transistors with tunable threshold voltage

    NARCIS (Netherlands)

    Wang, H.; Cobb, B.; Breemen, A. van; Gelinck, G.H.; Bao, Z.

    2014-01-01

    Carbon-nanotube top-gate transistors with fluorinated dielectrics are presented. With PTrFE as the dielectric, the devices have absent or small hysteresis at different sweep rates and excellent bias-stress stability under ambient conditions. Ambipolar single-walled carbon nanotube (SWNT) transistors

  16. Hydrothermal synthesis, characterization by single crystal XRD, structural discussion and electric, dielectrical properties of (C6H9N2)2(Hg0.12Zn0.88)Cl4 hybrid compound

    Science.gov (United States)

    Elwej, R.; Hlel, F.

    2016-10-01

    The new hybrid compound "Bis-2-amino-4-picolinium tetrachloro-mercurate-zincate ((C6H9N2)2(Hg0.12Zn0.88)Cl4)" was prepared by hydrothermal method using HCl as solvent and characterized by XRD, NMR-MAS 13C and electrical impedance spectroscopy. The XRD reveals that the compound was crystallized in the triclinic system, centrosymetric space group P 1 bar and the lattice parameters a=7.578(1)Å, b=8.559(1)Å, c=15.418(2)Å, α=84.443(1)°, β=89.506(1)°, γ=68.615(1)° and Z=2. The AC electrical conductivity and the dielectric relaxation properties were measured in the frequency range of 209 Hz-5 MHz at different temperature. The alternating current (AC) conductivity of the investigated compound obeys the Jonscher law: σ(ω)=σdc+Aωn. Furthermore, the temperature dependence of the Jonscher's exponent shows that the conduction inside the studied material is insured by the model: overlapping-large polaron tunneling (OLPT) model.

  17. Quantum Gates and Circuits

    CERN Document Server

    Di Vincenzo, D P

    1997-01-01

    A historical review is given of the emergence of the idea of the quantum logic gate from the theory of reversible Boolean gates. I highlight the quantum XOR or controlled NOT as the fundamental two-bit gate for quantum computation. This gate plays a central role in networks for quantum error correction.

  18. Flexural-Phonon Scattering Induced by Electrostatic Gating in Graphene

    DEFF Research Database (Denmark)

    Gunst, Tue; Kaasbjerg, Kristen; Brandbyge, Mads

    2017-01-01

    Graphene has an extremely high carrier mobility partly due to its planar mirror symmetry inhibiting scattering by the highly occupied acoustic flexural phonons. Electrostatic gating of a graphene device can break the planar mirror symmetry, yielding a coupling mechanism to the flexural phonons.......We examine the effect of the gate-induced one-phonon scattering on the mobility for several gate geometries and dielectric environments using first-principles calculations based on density functional theory and the Boltzmann equation. We demonstrate that this scattering mechanism can be a mobility...

  19. Multimode directionality in all-dielectric metasurfaces

    CERN Document Server

    Yang, Yuanqing; Kostinski, Sarah V; Odit, Mikhail; Kapitanova, Polina; Qiu, Min; Kivshar, Yuri

    2016-01-01

    All-dielectric resonant nanophotonics has emerged recently as a new direction of research aiming at the manipulation of strong optically-induced electric and magnetic Mie resonances in dielectric nanoparticles with high refractive index, for a design of metadevices with reduced dissipative losses and large resonant enhancement of both electric and magnetic fields. Usually, the geometry of dielectric nanoparticles is considered to be close to either sphere or rod, so the exact Mie solutions of the scattering problem are applied. Here we study nanoparticles with a large aspect ratio (such as nanobars) and describe a novel type of hybrid Mie-Fabry-Perot modes responsible for the existence of multiple magnetic dipole resonances. The multiple magnetic dipoles originate from a combination of a magnetic dipolar mode and a number of standing waves of an elongated anisotropic nanobar. We reveal that these novel hybrid modes can interfere constructively with the induced electric dipoles and thereby lead to multimode un...

  20. The dielectric genome of van der Waals heterostructures

    DEFF Research Database (Denmark)

    Andersen, Kirsten; Latini, Simone; Thygesen, Kristian Sommer

    2015-01-01

    with ab-initio accuracy using a multi-scale approach where the dielectric functions of the individual layers (the dielectric building blocks) are coupled simply via their long-range Coulomb interaction. We use the method to illustrate the 2D- 3D dielectric transition in multi-layer MoS2 crystals......, the hybridization of quantum plasmons in large graphene/hBN heterostructures, and to demonstrate the intricate effect of substrate screening on the non-Rydberg exciton series in supported WS2. The dielectric building blocks for a variety of 2D crystals are available in an open database together with the software...

  1. Cleaning Challenges of High-κ/Metal Gate Structures

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-12-20

    High-κ/metal gates are used as transistors for advanced logic applications to improve speed and eliminate electrical issues associated with polySi and SiO2 gates. Various integration schemes are possible and will be discussed, such as dual gate, gate-first, and gate-last, both of which require specialized cleaning and etching steps. Specific areas of discussion will include cleaning and conditioning of the silicon surface, forming a high-quality chemical oxide, removal of the high-κ dielectric with selectivity to the SiO2 layer, cleaning and residue removal after etching, and prevention of galvanic corrosion during cleaning. © 2011 Scrivener Publishing LLC. All rights reserved.

  2. Dynamic Electric Potential Redistribution And Its Influence On The Development Of A Dielectric Barrier Plasma Jet

    Science.gov (United States)

    2012-05-01

    dielectric barrier discharge (DBD) devices. The dielectric barrier plasma jet represents a hybrid between streamer corona and conventional DBD sources...capillary tip and beyond indicating a transition away from a DBD to what was essentially a classical streamer corona discharge drawing current directly...plasma jet generated in a single-electrode dielectric barrier configuration at atmospheric pressure. The influence of dielectric boundary conditions

  3. Graduate Automotive Technology Education (GATE) Center

    Energy Technology Data Exchange (ETDEWEB)

    Jeffrey Hodgson; David Irick

    2005-09-30

    The Graduate Automotive Technology Education (GATE) Center at the University of Tennessee, Knoxville has completed its sixth year of operation. During this period the Center has involved thirteen GATE Fellows and ten GATE Research Assistants in preparing them to contribute to advanced automotive technologies in the center's focus area: hybrid drive trains and control systems. Eighteen GATE students have graduated, and three have completed their course work requirements. Nine faculty members from three departments in the College of Engineering have been involved in the GATE Center. In addition to the impact that the Center has had on the students and faculty involved, the presence of the center has led to the acquisition of resources that probably would not have been obtained if the GATE Center had not existed. Significant industry interaction such as internships, equipment donations, and support for GATE students has been realized. The value of the total resources brought to the university (including related research contracts) exceeds $4,000,000. Problem areas are discussed in the hope that future activities may benefit from the operation of the current program.

  4. New gate opening hours

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  5. Hybrid Aging Delay Model Considering the PBTI and TDDB

    Institute of Scientific and Technical Information of China (English)

    Yong Miao; Mao-Xiang Yi; Gui-Mao Zhang; Da-Wen Xu

    2015-01-01

    Abstract-With a 45nm process technique, the shrinking silicon feature size brings in a high-k/metal gate which significantly exacerbates the positive bias temperature instability (PBTI) and time-dependent dielectric breakdown (TDDB) effects of a NMOS transistor. However, previous works presented delay models to characterize the PBTI or TDDB individually. This paper demonstrates that the delay caused by the joint effects of PBTI and TDDB widely differs from the cumulated result of the delay caused by the PBTI and TDDB, respectively, with the experiments on an inverter chain. This paper proposes a hybrid aging delay model comprising both the PBTI and TDDB effects by analyzing the relationship between the aging propagation delay and the inherent delay of the gate. Experimental results on the logic gates under 45nm, 32 nm, 22nm, and 16nm CMOS technologies show that the maximum error between the proposed model and the actual value is less than 2.5%, meanwhile the average error is about 1.5%.

  6. Dielectric screening in semiconductors

    Science.gov (United States)

    Harrison, Walter A.; Klepeis, John E.

    1988-01-01

    Intra-atomic and interatomic Coulomb interactions are incorporated into bond-orbital theory, based upon universal tight-binding parameters, in order to treat the effects of charge redistribution in semiconductor bonds. The dielectric function ɛ(q) is obtained for wave numbers in a [100] direction. The screening of differences in average hybrid energy across a heterojunction is calculated in detail, indicating that the decay length for the potential depends upon the relative values of Madelung and intra-atomic Coulomb terms. The parameters used here predict an imaginary decay length and thus an oscillating potential near the interface. The same theory is applied to point defects by imbedding a cluster in a matrix lattice, taking charges in that lattice to be consistent with continuum theory. Illustrating the theory with a phosphorus impurity in silicon, it is seen that the impurity and its neighboring atoms have charges on the order of only one-tenth of an electronic charge, alternating in sign from neighbor to neighbor as for planar defects. Although there are shifts in the term values on the order of a volt, the difference in these shifts for neighboring atoms is much smaller so that the effect on the bonds is quite small. This behavior is analogous to the response of a dielectric continuum to a point charge: The medium is locally neutral except at the center of the cluster and there are slowly varying potentials e2/ɛr. Because of this slow variation, free-atom term values should ordinarily suffice for the calculation of bond properties and bond lengths at impurities. Corrections are larger for homovalent substitutions such as carbon in silicon.

  7. Electrical prop erties of LaTiO high-k gate dielectric Ge MOS capacitor and Ti content optimization%LaTiO高k栅介质Ge MOS电容电特性及Ti 含量优化∗

    Institute of Scientific and Technical Information of China (English)

    徐火希; 徐静平

    2016-01-01

    采用共反应溅射法将Ti添加到La2 O3中,制备了LaTiO/Ge 金属-氧化物-半导体电容,并就Ti含量对器件电特性的影响进行了仔细研究.由于Ti-基氧化物具有极高的介电常数, LaTiO栅介质能够获得高k值;然而由于界面/近界面缺陷随着Ti含量的升高而增加,添加Ti 使界面质量恶化,进而使栅极漏电流增大、器件可靠性降低.因此,为了在器件电特性之间实现协调,对Ti含量进行优化显得尤为重要.就所研究的Ti/La2O3比率而言,18.4%的Ti/La2O3比率最合适.该比率导致器件呈现出高k值(22.7)、低Dit (5.5×1011 eV−1·cm−2)、可接受的Jg (Vg=1 V, Jg=7.1×10−3 A·cm−2)和良好的器件可靠性.%Ti is intentionally added into La2O3 to prepare LaTiO gate dielectric Ge metal-oxide-semiconductor (MOS) capac-itor with both high k value and good interface quality. In order to examine the effects of Ti content on the electrical properties of the device, LaTiO films with different Ti/La2O3 ratios (10.6%, 18.4%, 25.7%and 31.5%) are deposited by reactively co-sputtering Ti and La2O3 targets. Capacitance-voltage curves, gate-leakage current properties and high-field stress characteristics of the devices are measured and analyzed. It is found that some electrical properties, such as interface-sate density, gate-leakage current, device reliability and k value, strongly depend on Ti content incorporated into La2O3. Ti incorporation can significantly increase the k value: the higher the Ti content, the larger the k value is. The relevant mechanism lies in the fact that higher Ti content leads to an increase of Ti-based oxide in the LaTi-based oxide, because Ti-based oxide has larger k value than La-based oxide. On the contrary, interface quality, gate-leakage current and device reliability deteriorate as Ti content increases because Ti-induced defects at and near the interface increase with Ti content increasing. Of the Ti/La2O3 ratios in the examined range, the

  8. Ultralow-voltage in-plane-gate indium-tin-oxide thin-film transistors made of P-doped SiO2 dielectrics*%基于P掺杂SiO2为栅介质的超低压侧栅薄膜晶体管*

    Institute of Scientific and Technical Information of China (English)

    朱德明; 门传玲†; 曹敏; 吴国栋

    2013-01-01

    A new kind of indium-tin-oxide thin-film transistors made of P-doped SiO2 dielectrics in an in-plane-gate structure is fabricated at room temperature. Indium-tin-oxide (ITO) channel and ITO electrodes (gate, source, and drain) can be deposited simultaneously without precise photolithography and alignment process by using only one nickel shadow mask. So the thin film transistors (TFTs) have a lot of advantages, such as the simple device process、low cost etc. Such TFTs exhibit a good performance at an ultralow operation voltage of 1 V, a high field-effect mobility of 18.35 cm2/Vs , a small subthreshold swing of 82 mV/decade, and a large on-off ratio of 1.1 × 106, because of the huge electric-double-layer (EDL) capacitance (8 µF/cm2) between the interface of P-doped SiO2 dielectrics and ITO channel. So the TFTs are very promising for the application of low-power and portable electronic products and sensors in the future.%  在室温下利用等离子体增强化学气相沉积法(PECVD)制备的颗粒膜P掺杂SiO2为栅介质,使用磁控溅射方法利用一步掩模法制备出一种新型结构的侧栅薄膜晶体管.由于侧栅薄膜晶体管具有独特的结构,在射频磁控溅射过程中,仅仅利用一块镍掩模板,无需复杂的光刻步骤,就可同时沉积出氧化铟锡(ITO)源、漏、栅电极和沟道,因此,这种方法极大地简化了制备流程,降低了工艺成本.实验结果表明,在P掺杂SiO2栅介质层与沟道层界面处形成了超大的双电层电容(8µF/cm2),这使得这类晶体管具有超低的工作电压1 V,小的亚阈值摆幅82 mV/dec、高的迁移率18.35 cm2/V·s和大的开关电流比1.1×106.因此,这种P掺杂SiO2双电层超低压薄膜晶体管将有望应用于低能耗便携式电子产品以及新型传感器领域.

  9. Mobility enhancement of SnO2 nanowire transistors gated with a nanogranular SiO2 solid electrolyte.

    Science.gov (United States)

    Sun, Jia; Huang, Wenlong; Qian, Chuan; Yang, Junliang; Gao, Yongli

    2014-01-21

    Field-effect transistors (FETs) based on semiconducting nanowires are the most fundamental electronic elements for exploring charge transport as well as possible applications in functional nanoelectronics. Here, we report the effect of different gate dielectrics on the electrical performance of SnO2 nanowire FETs. By using solid-electrolytes with large electric-double-layer (EDL) capacitance as gate dielectrics, both low-voltage operation and high gating efficiency can be obtained. Electrical transport measurements indicate that the nanowire FETs gated by solid-electrolytes show improved electrical performances in terms of on-current, sub-threshold swing, and mobility, in comparison to those gated by traditional thermally grown dielectrics. The observed performance improvement is possibly due to the reduction of the contact-resistance and the Schottky barrier at the semiconductor/metal junctions.

  10. Core-shell structured polystyrene/BaTiO3 hybrid nanodielectrics prepared by in situ RAFT polymerization: a route to high dielectric constant and low loss materials with weak frequency dependence.

    Science.gov (United States)

    Yang, Ke; Huang, Xingyi; Xie, Liyuan; Wu, Chao; Jiang, Pingkai; Tanaka, Toshikatsu

    2012-11-23

    A novel route to prepare core-shell structured nanocomposites with excellent dielectric performance is reported. This approach involves the grafting of polystyrene (PS) from the surface of BaTiO(3) by an in situ RAFT polymerization. The core-shell structured PS/BaTiO(3) nanocomposites not only show significantly increased dielectric constant and very low dielectric loss, but also have a weak frequency dependence of dielectric properties over a wide range of frequencies. In addition, the dielectric constant of the nanocomposites can also be easily tuned by varying the thickness of the PS shell. Our method is very promising for preparing high-performance nanocomposites used in energy-storage devices.

  11. Dielectrics in electric fields

    CERN Document Server

    Raju, Gorur G

    2003-01-01

    Discover nontraditional applications of dielectric studies in this exceptionally crafted field reference or text for seniors and graduate students in power engineering tracks. This text contains more than 800 display equations and discusses polarization phenomena in dielectrics, the complex dielectric constant in an alternating electric field, dielectric relaxation and interfacial polarization, the measurement of absorption and desorption currents in time domains, and high field conduction phenomena. Dielectrics in Electric Fields is an interdisciplinary reference and text for professionals and students in electrical and electronics, chemical, biochemical, and environmental engineering; physical, surface, and colloid chemistry; materials science; and chemical physics.

  12. Lattices of dielectric resonators

    CERN Document Server

    Trubin, Alexander

    2016-01-01

    This book provides the analytical theory of complex systems composed of a large number of high-Q dielectric resonators. Spherical and cylindrical dielectric resonators with inferior and also whispering gallery oscillations allocated in various lattices are considered. A new approach to S-matrix parameter calculations based on perturbation theory of Maxwell equations, developed for a number of high-Q dielectric bodies, is introduced. All physical relationships are obtained in analytical form and are suitable for further computations. Essential attention is given to a new unified formalism of the description of scattering processes. The general scattering task for coupled eigen oscillations of the whole system of dielectric resonators is described. The equations for the  expansion coefficients are explained in an applicable way. The temporal Green functions for the dielectric resonator are presented. The scattering process of short pulses in dielectric filter structures, dielectric antennas  and lattices of d...

  13. Transport Properties of Hydrogen-Terminated Silicon Surface Controlled by Ionic-Liquid Gating

    Science.gov (United States)

    Sasama, Yosuke; Yamaguchi, Takahide; Tanaka, Masashi; Takeya, Hiroyuki; Takano, Yoshihiko

    2017-01-01

    We fabricated electric double-layer transistors on the hydrogen-terminated (111)-oriented surface of non-doped silicon using ionic liquid as a gate dielectric. We introduced hole carriers into silicon with the application of a negative gate voltage. The sheet resistance of silicon was controlled by more than three orders of magnitude at 220 K by changing the gate voltage. The temperature dependence of sheet resistance became weak as the gate voltage was increased, suggesting the approach to an insulator-metal transition.

  14. Nonlinear electroelastic deformations of dielectric elastomer composites: II - Non-Gaussian elastic dielectrics

    Science.gov (United States)

    Lefèvre, Victor; Lopez-Pamies, Oscar

    2017-02-01

    This paper presents an analytical framework to construct approximate homogenization solutions for the macroscopic elastic dielectric response - under finite deformations and finite electric fields - of dielectric elastomer composites with two-phase isotropic particulate microstructures. The central idea consists in employing the homogenization solution derived in Part I of this work for ideal elastic dielectric composites within the context of a nonlinear comparison medium method - this is derived as an extension of the comparison medium method of Lopez-Pamies et al. (2013) in nonlinear elastostatics to the coupled realm of nonlinear electroelastostatics - to generate in turn a corresponding solution for composite materials with non-ideal elastic dielectric constituents. Complementary to this analytical framework, a hybrid finite-element formulation to construct homogenization solutions numerically (in three dimensions) is also presented. The proposed analytical framework is utilized to work out a general approximate homogenization solution for non-Gaussian dielectric elastomers filled with nonlinear elastic dielectric particles that may exhibit polarization saturation. The solution applies to arbitrary (non-percolative) isotropic distributions of filler particles. By construction, it is exact in the limit of small deformations and moderate electric fields. For finite deformations and finite electric fields, its accuracy is demonstrated by means of direct comparisons with finite-element solutions. Aimed at gaining physical insight into the extreme enhancement in electrostriction properties displayed by emerging dielectric elastomer composites, various cases wherein the filler particles are of poly- and mono-disperse sizes and exhibit different types of elastic dielectric behavior are discussed in detail. Contrary to an initial conjecture in the literature, it is found (inter alia) that the isotropic addition of a small volume fraction of stiff (semi

  15. Dielectric influence on IV curve of graphene field effect transistor

    Science.gov (United States)

    Shostachenko, Stanislav A.; Zakharchenko, Roman V.; Zebrev, Gennady I.; Stanishevskiy, Yaroslav M.; Kargin, Nikolay I.

    2016-12-01

    In this article, we have studied the influence of Si3N4 and SiO2 thin film gate dielectrics on the current-voltage characteristics of the graphene-based transistor. The test structure of graphene transistor was fabricated with the top and back gate. Graphene has been produced by chemical vapor deposition, and then transferred to the silicon dioxide on a silicon wafer. The channel of the transistor has been formed by etching in oxygen plasma through a photolithographic mask. Metals electrodes of the drain, source, and gate were deposited by resistive evaporation in a vacuum. It was used titanium / aluminum with a thickness of 50/200 nm. In the case of the back gate, silicon dioxide was used, obtained by thermal oxidation of the silicon substrate. For top gate was used silicon nitride deposited by plasma chemical deposition. It was demonstrated that field effect is more pronounced for the case of SiO2 back gate compare to the Si3N4 top gate. For the SiO2 back gate we have observed that the source- drain current decreases, from 2 mA to 3 mA, with increasing the gate voltage, from 0 to 40 V, at constant source-drain voltage, 2 V. In case of Si3N4 top gate the modulation of source-drain current was not significant for the comparable electric field strength. Based on the value of gate voltage for current minima in transfer function the poor quality of Si3N4 -graphene interface is concluded.

  16. Controlling flow-induced vibrations of flood barrier gates with data-driven and finite-element modelling

    NARCIS (Netherlands)

    Erdbrink, C.D.; Krzhizhanovskaya, V.V.; Sloot, P.M.A.; Klijn, F.; Schweckendiek, T.

    2012-01-01

    Operation of flood barrier gates is sometimes hampered by flow-induced vibrations. Although the physics is understood for specific gate types, it remains challenging to judge dynamic gate behaviour for unanticipated conditions. This paper presents a hybrid modelling system for predicting vibrations

  17. Characterization of dielectric materials

    Energy Technology Data Exchange (ETDEWEB)

    King, Danny J.; Babinec, Susan; Hagans, Patrick L.; Maxey, Lonnie C.; Payzant, Edward A.; Daniel, Claus; Sabau, Adrian S.; Dinwiddie, Ralph B.; Armstrong, Beth L.; Howe, Jane Y.; Wood, III, David L.; Nembhard, Nicole S.

    2017-06-27

    A system and a method for characterizing a dielectric material are provided. The system and method generally include applying an excitation signal to electrodes on opposing sides of the dielectric material to evaluate a property of the dielectric material. The method can further include measuring the capacitive impedance across the dielectric material, and determining a variation in the capacitive impedance with respect to either or both of a time domain and a frequency domain. The measured property can include pore size and surface imperfections. The method can still further include modifying a processing parameter as the dielectric material is formed in response to the detected variations in the capacitive impedance, which can correspond to a non-uniformity in the dielectric material.

  18. Effects of annealing conditions on the dielectric properties of solution-processed Al2O3 layers for indium-zinc-tin-oxide thin-film transistors.

    Science.gov (United States)

    Kim, Yong-Hoon; Kim, Kwang-Ho; Park, Sung Kyu

    2013-11-01

    In this paper, the effects of annealing conditions on the dielectric properties of solution-processed aluminum oxide (Al2O3) layers for indium-zinc-tin-oxide (IZTO) thin-film transistors (TFTs) have been investigated. The dielectric properties of Al2O3 layers such as leakage current density and dielectric strength were largely affected by their annealing conditions. In particular, oxygen partial pressure in rapid thermal annealing, and the temperature profile of hot plate annealing had profound effects on the dielectric properties. From a refractive index analysis, the enhanced dielectric properties of Al2O3 gate dielectrics can be attributed to higher film density depending on the annealing conditions. With the low-temperature-annealed Al2O3 gate dielectric at 350 degrees C, solution-processed IZTO TFTs with a field-effect mobility of approximately 2.2 cm2/Vs were successfully fabricated.

  19. Resonant dielectric metamaterials

    Science.gov (United States)

    Loui, Hung; Carroll, James; Clem, Paul G; Sinclair, Michael B

    2014-12-02

    A resonant dielectric metamaterial comprises a first and a second set of dielectric scattering particles (e.g., spheres) having different permittivities arranged in a cubic array. The array can be an ordered or randomized array of particles. The resonant dielectric metamaterials are low-loss 3D isotropic materials with negative permittivity and permeability. Such isotropic double negative materials offer polarization and direction independent electromagnetic wave propagation.

  20. Accelerating Dielectrics Design Using Thinking Machines

    Science.gov (United States)

    Ramprasad, R.

    2013-03-01

    High energy density capacitors are required for several pulsed power and energy storage applications, including food preservation, nuclear test simulations, electric propulsion of ships and hybrid electric vehicles. The maximum electrostatic energy that can be stored in a capacitor dielectric is proportional to its dielectric constant and the square of its breakdown field. The current standard material for capacitive energy storage is polypropylene which has a large breakdown field but low dielectric constant. We are involved in a search for new classes of polymers superior to polypropylene using first principles computations combined with statistical and machine learning methods. Essential to this search are schemes to efficiently compute the dielectric constant of polymers and the intrinsic dielectric breakdown field, as well as methods to determine the stable structures of new classes of polymers and strategies to efficiently navigate through the polymer chemical space offered by the periodic table. These methodologies have been combined with statistical learning paradigms in order to make property predictions rapidly, and promising classes of polymeric systems for energy storage applications have been identified. This work is being supported by the Office of Naval Research.

  1. Study of the tunnelling initiated leakage current through the carbon nanotube embedded gate oxide in metal oxide semiconductor structures

    Energy Technology Data Exchange (ETDEWEB)

    Chakraborty, Gargi; Sarkar, C K [Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata (India); Lu, X B; Dai, J Y [Department of Applied Physics and Materials Research Center, Hong Kong Polytechnic University, Hong Kong (China)], E-mail: gargichakraborty0@yahoo.co.in, E-mail: phyhod@yahoo.co.in

    2008-06-25

    The tunnelling currents through the gate dielectric partly embedded with semiconducting single-wall carbon nanotubes in a silicon metal-oxide-semiconductor (MOS) structure have been investigated. The application of the gate voltage to such an MOS device results in the band bending at the interface of the partly embedded oxide dielectric and the surface of the silicon, initiating tunnelling through the gate oxide responsible for the gate leakage current whenever the thickness of the oxide is scaled. A model for silicon MOS structures, where carbon nanotubes are confined in a narrow layer embedded in the gate dielectric, is proposed to investigate the direct and the Fowler-Nordheim (FN) tunnelling currents of such systems. The idea of embedding such elements in the gate oxide is to assess the possibility for charge storage for memory device applications. Comparing the FN tunnelling onset voltage between the pure gate oxide and the gate oxide embedded with carbon nanotubes, it is found that the onset voltage decreases with the introduction of the nanotubes. The direct tunnelling current has also been studied at very low gate bias, for the thin oxide MOS structure which plays an important role in scaling down the MOS transistors. The FN tunnelling current has also been studied with varying nanotube diameter.

  2. Synthesis and Dielectric Studies of Monoclinic Nanosized Zirconia

    Directory of Open Access Journals (Sweden)

    I. Flavia Princess Nesamani

    2014-01-01

    Full Text Available Zirconium dioxide is a prospective high-κ material that can replace silicon dioxide. Zirconium dioxide nanoparticle has been synthesized using sol-gel process at room temperature. The structural and morphological characterization of the nanoscaled zirconium dioxide is done using FTIR, SEM, X-ray diffraction, and TEM. The particle size of the synthesized ZrO2 is observed in the range of 50–80 nm with an average crystallite size of 2–10 nm. The results are compared with commercial coarse zirconia which showed a particle size in the range of 900 nm–2.13 µm and crystallite size of 5.3 nm–20 nm. It is expected that both nanoscaling and the high dielectric constant of ZrO2 would be useful in replacing the low-κ SiO2 dielectric with high-κ ZrO2 for CMOS fabrication technology. The synthesized ZrO2 is subjected to impedance analysis and it exhibited a dielectric constant of 25 to find its application in short channel devices like multiple gate FinFETS and as a suitable alternative for the conventional gate oxide dielectric SiO2 with dielectric value of 3.9, which cannot survive the challenge of an end of oxide thickness ≤ 1 nm.

  3. Reliable passivation of black phosphorus by thin hybrid coating

    Science.gov (United States)

    Gamage, S.; Fali, A.; Aghamiri, N.; Yang, L.; Ye, P. D.; Abate, Y.

    2017-06-01

    Black phosphorus (BP) possesses several extraordinary physical properties, which include in-plane anisotropy, thickness dependent direct bandgap and high carrier mobility. These physical properties make BP highly desirable from the point of view of fundamental science and modern optoelectronics applications. The excitement about this material has always been accompanied by unreserved skepticism due to its extraordinary degradation under ambient conditions. Here we show ambient degradation of exfoliated BP can be effectively suppressed using thin layer of hybrid metal organic chemical vapor deposition coating of boron nitride (BN) followed by atomic layer deposition coating of Al2O3. We have extensively studied the time dependent surface, optical and electrical properties of BP encapsulated by BN and/or Al2O3 using nanoscale infrared imaging and I-V characterizations. Our results show hybrid thin layer (˜5 nm) BN/Al2O3 coated BP exfoliated on SiO2 substrate is protected from degradation in ambient for over 6 months, much longer than those coated only by BN or Al2O3 layers. Our theoretical modeling of the experimental degradation growth pattern shows that the influence of neighboring elements on the degradation of a given element is minimal for BP flakes with hybrid coating. Electrical characterization further confirms the effectiveness of BN/Al2O3 as encapsulation layer and gate dielectrics with minor changes after several weeks.

  4. Method of making dielectric capacitors with increased dielectric breakdown strength

    Energy Technology Data Exchange (ETDEWEB)

    Ma, Beihai; Balachandran, Uthamalingam; Liu, Shanshan

    2017-05-09

    The invention is directed to a process for making a dielectric ceramic film capacitor and the ceramic dielectric laminated capacitor formed therefrom, the dielectric ceramic film capacitors having increased dielectric breakdown strength. The invention increases breakdown strength by embedding a conductive oxide layer between electrode layers within the dielectric layer of the capacitors. The conductive oxide layer redistributes and dissipates charge, thus mitigating charge concentration and micro fractures formed within the dielectric by electric fields.

  5. Implementation of a two-qubit controlled-U gate based on unconventional geometric phase with a constant gating time

    CERN Document Server

    Yabu-uti, Bruno F C

    2011-01-01

    We propose an alternative scheme to implement a two-qubits Controlled-U gate in the hybrid system atom-$CCA$ (coupled cavities array). Our scheme results in a constant gating time and, with an adjustable qubit-bus coupling (atom-resonator), one can specify a particular transformation $U$ on the target qubit. We believe that this proposal may open promising perspectives for networking quantum information processors and implementing distributed and scalable quantum computation.

  6. Implementation of a two-qubit controlled-rotation gate based on unconventional geometric phase with a constant gating time

    Energy Technology Data Exchange (ETDEWEB)

    Yabu-uti, B.F.C., E-mail: yabuuti@ifi.unicamp.br [Instituto de Fisica ' Gleb Wataghin' , Universidade Estadual de Campinas, 13083-970 Campinas, SP (Brazil); Roversi, J.A., E-mail: roversi@ifi.unicamp.br [Instituto de Fisica ' Gleb Wataghin' , Universidade Estadual de Campinas, 13083-970 Campinas, SP (Brazil)

    2011-08-22

    We propose an alternative scheme to implement a two-qubit controlled-R (rotation) gate in the hybrid atom-CCA (coupled cavities array) system. Our scheme results in a constant gating time and, with an adjustable qubit-bus coupling (atom-resonator), one can specify a particular rotation R on the target qubit. We believe that this proposal may open promising perspectives for networking quantum information processors and implementing distributed and scalable quantum computation. -- Highlights: → We propose an alternative two-qubit controlled-rotation gate implementation. → Our gate is realized in a constant gating time for any rotation. → A particular rotation on the target qubit can be specified by an adjustable qubit-bus coupling. → Our proposal may open promising perspectives for implementing distributed and scalable quantum computation.

  7. Contemporary dielectric materials

    CERN Document Server

    Saravanan, R

    2016-01-01

    This book deals with experimental results of the physical characterization of several important, dielectric materials of great current interest. The experimental tools used for the analysis of these materials include X-ray diffraction, dielectric measurements, magnetic measurements using a vibrating sample magnetometer, optical measurements using a UV-Visible spectrometer etc.

  8. Dielectric material for dosimeters

    Energy Technology Data Exchange (ETDEWEB)

    Moran, P.R.; Podgorsak, E.; Fullerton, G.D.; Fuller, G.E.

    1976-01-27

    A RITAD dosimeter is described having a dielectric material such as sapphire wherein the efficiency as measured by mean drift distance and trapping efficiency is increased by making use of a dielectric material in which the total active impurity does not exceed 50 ppm and in which any one active impurity does not exceed 10 ppm.

  9. Light in complex dielectrics

    NARCIS (Netherlands)

    Schuurmans, F.J.P.

    1999-01-01

    In this thesis the properties of light in complex dielectrics are described, with the two general topics of "modification of spontaneous emission" and "Anderson localization of light". The first part focuses on the spontaneous emission rate of an excited atom in a dielectric host with variable refra

  10. Dependence of Pentacene Crystal Growth on Dielectric Roughness for Fabrication of Flexible Field-Effect Transistors

    Energy Technology Data Exchange (ETDEWEB)

    Yang, H.; Yang, C; Kim, S; Jang, M; Park, C

    2010-01-01

    The dependence of pentacene nanostructures on gate dielectric surfaces were investigated for flexible organic field-effect transistor (OFET) applications. Two bilayer types of polymer/aluminum oxide (Al{sub 2}O{sub 3}) gate dielectrics were fabricated on commercial Al foils laminated onto a polymer back plate. Some Al foils were directly used as gate electrodes, and others were smoothly polished by an electrolytic etching. These Al surfaces were then anodized and coated with poly({alpha}-methyl styrene) (PAMS). For PAMS/Al{sub 2}O{sub 3} dielectrics onto etched Al foils, surface roughness up to 1 nm could be reached, although isolated dimples with a lateral diameter of several micrometers were still present. On PAMS/Al{sub 2}O{sub 3} dielectrics (surface roughness >40 nm) containing mechanical grooves of Al foil, average hole mobility ({mu}FET) of 50 nm thick pentacene-FETs under the low operating voltages (|V| < 6 V) was {approx}0.15 cm{sup 2} V{sup -1} s{sup -1}. In contrast, pentacene-FETs employing the etched Al gates exhibited {mu}FET of 0.39 cm{sup 2} V{sup -1} s{sup -1}, which was comparable to that of reference samples with PAMS/Al{sub 2}O{sub 3} dielectrics onto flat sputtered Al gates. Conducting-probe atomic force microscopy and two-dimensional X-ray diffraction of pentacene films with various thicknesses revealed different out-of-plane and in-plane crystal orderings of pentacene, depending on the surface roughness of the gate dielectrics.

  11. Theoretical evaluation of zirconia and hafnia as gate oxides for si microelectronics.

    Science.gov (United States)

    Fiorentini, Vincenzo; Gulleri, Gianluca

    2002-12-23

    Parameters determining the performance of the crystalline oxides zirconia (ZrO2) and hafnia (HfO2) as gate insulators in nanometric Si electronics are estimated via ab initio calculations of the energetics, dielectric properties, and band alignment of bulk and thin-film oxides on Si (001). With their large dielectric constants, stable and low-formation-energy interfaces, large valence offsets, and reasonable (though not optimal) conduction offsets (electron injection barriers), zirconia and hafnia appear to have considerable potential as gate oxides for Si electronics.

  12. Experimental realization of a terahertz all-dielectric metasurface absorber.

    Science.gov (United States)

    Liu, Xinyu; Fan, Kebin; Shadrivov, Ilya V; Padilla, Willie J

    2017-01-09

    Metamaterial absorbers consisting of metal, metal-dielectric, or dielectric materials have been realized across much of the electromagnetic spectrum and have demonstrated novel properties and applications. However, most absorbers utilize metals and thus are limited in applicability due to their low melting point, high Ohmic loss and high thermal conductivity. Other approaches rely on large dielectric structures and / or a supporting dielectric substrate as a loss mechanism, thereby realizing large absorption volumes. Here we present a terahertz (THz) all dielectric metasurface absorber based on hybrid dielectric waveguide resonances. We tune the metasurface geometry in order to overlap electric and magnetic dipole resonances at the same frequency, thus achieving an experimental absorption of 97.5%. A simulated dielectric metasurface achieves a total absorption coefficient enhancement factor of FT=140, with a small absorption volume. Our experimental results are well described by theory and simulations and not limited to the THz range, but may be extended to microwave, infrared and optical frequencies. The concept of an all-dielectric metasurface absorber offers a new route for control of the emission and absorption of electromagnetic radiation from surfaces with potential applications in energy harvesting, imaging, and sensing.

  13. Charge Transport in Hybrid Halide Perovskite Field-Effect Transistors

    Science.gov (United States)

    Jurchescu, Oana

    Hybrid organic-inorganic trihalide perovskite (HTP) materials exhibit a strong optical absorption, tunable band gap, long carrier lifetimes and fast charge carrier transport. These remarkable properties, coupled with their reduced complexity processing, make the HTPs promising contenders for large scale, low-cost thin film optoelectronic applications. But in spite of the remarkable demonstrations of high performance solar cells, light-emitting diodes and field-effect transistor devices, all of which took place in a very short time period, numerous questions related to the nature and dynamics of the charge carriers and their relation to device performance, stability and reliability still remain. This presentation describes the electrical properties of HTPs evaluated from field-effect transistor measurements. The electrostatic gating of provides an unique platform for the study of intrinsic charge transport in these materials, and, at the same time, expand the use of HTPs towards switching electronic devices, which have not been explored previously. We fabricated FETs on SiO2 and polymer dielectrics from spin coating, thermal evaporation and spray deposition and compare their properties. CH3NH3PbI3-xClx can reach balanced electron and hole mobilities of 10 cm2/Vs upon tuning the thin-film microstructure, injection and the defect density at the semiconductor/dielectric interface. The work was performed in collaboration with Yaochuan Mei (Wake Forest University), Chuang Zhang, and Z. Valy Vardeny (University of Utah). The work is supported by ONR Grant N00014-15-1-2943.

  14. High mobility and low density of trap states in dual-solid-gated PbS nanocrystal field-effect transistors.

    Science.gov (United States)

    Nugraha, Mohamad Insan; Häusermann, Roger; Bisri, Satria Zulkarnaen; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria Antonietta

    2015-03-25

    Dual-gated PbS nanocrystal field-effect transistors employing SiO2 and Cytop as gate dielectrics are fabricated. The obtained electron mobility (0.2 cm(2) V(-1) s(-1) ) and the high on/off ratio (10(5) -10(6) ), show that the controlled nanocrystal assembly (obtained with self-assembled monolayers), as well as the trap density reduction (using Cytop as dielectric), are crucial steps for the future application of nanocrystals.

  15. Entangling Gate of Dipolar Molecules Coupled to a Photonic Crystal

    Institute of Scientific and Technical Information of China (English)

    XUE Peng

    2011-01-01

    A hybrid entangling gate is proposed by using the coherent interaction between dipolar molecules and a photonic crystal microcavity, which is effected by virtual electric dipole transitions. Noise is included in the present model and high feasibility of the scheme with current experimental conditions is shown.%@@ A hybrid entangling gate is proposed by using the coherent interaction between dipolar molecules and a photonic crystal microcavity,which is effected by virtual electric dipole transitions.Noise is included in the present model and high feasibility of the scheme with current experimental conditions is shown.

  16. Intrinsic multistate switching of gold clusters through electrochemical gating

    DEFF Research Database (Denmark)

    Albrecht, Tim; Mertens, S.F.L.; Ulstrup, Jens

    2007-01-01

    The electrochemical behavior of small metal nanoparticles is governed by Coulomb-like charging and equally spaced charge-transfer transitions. Using electrochemical gating at constant bias voltage, we show, for the first time, that individual nanoparticles can be operated as multistate switches...... in condensed media at room temperature, displaying distinct peak features in the tunneling current. The tunneling conductance increases with particle charge, suggesting that solvent reorganization and dielectric saturation become increasingly important....

  17. Low pull-in voltage electrostatic MEMS switch using liquid dielectric

    KAUST Repository

    Zidan, Mohammed A.

    2014-08-01

    In this paper, we present an electrostatic MEMS switch with liquids as dielectric to reduce the actuation voltage. The concept is verified by simulating a lateral dual gate switch, where the required pull-in voltage is reduced by more than 8 times after using water as a dielectric, to become as low as 5.36V. The proposed switch is simulated using COMSOL multiphysics using various liquid volumes to study their effect on the switching performance. Finally, we propose the usage of the lateral switch as a single switch XOR logic gate.

  18. Atomic layer deposition of dielectrics on graphene using reversibly physisorbed ozone.

    Science.gov (United States)

    Jandhyala, Srikar; Mordi, Greg; Lee, Bongki; Lee, Geunsik; Floresca, Carlo; Cha, Pil-Ryung; Ahn, Jinho; Wallace, Robert M; Chabal, Yves J; Kim, Moon J; Colombo, Luigi; Cho, Kyeongjae; Kim, Jiyoung

    2012-03-27

    Integration of graphene field-effect transistors (GFETs) requires the ability to grow or deposit high-quality, ultrathin dielectric insulators on graphene to modulate the channel potential. Here, we study a novel and facile approach based on atomic layer deposition through ozone functionalization to deposit high-κ dielectrics (such as Al(2)O(3)) without breaking vacuum. The underlying mechanisms of functionalization have been studied theoretically using ab initio calculations and experimentally using in situ monitoring of transport properties. It is found that ozone molecules are physisorbed on the surface of graphene, which act as nucleation sites for dielectric deposition. The physisorbed ozone molecules eventually react with the metal precursor, trimethylaluminum to form Al(2)O(3). Additionally, we successfully demonstrate the performance of dual-gated GFETs with Al(2)O(3) of sub-5 nm physical thickness as a gate dielectric. Back-gated GFETs with mobilities of ~19,000 cm(2)/(V·s) are also achieved after Al(2)O(3) deposition. These results indicate that ozone functionalization is a promising pathway to achieve scaled gate dielectrics on graphene without leaving a residual nucleation layer.

  19. Improved linearity in AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors with nonlinear polarization dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Gao, Tao [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China); Xu, Ruimin [Fundamental Science on EHF Laboratory, University of Electronic Science and Technology of China (UESTC), Chengdu 611731 (China); Kong, Yuechan, E-mail: kycfly@163.com; Zhou, Jianjun; Kong, Cen; Dong, Xun; Chen, Tangsheng [Science and Technology on Monolithic Integrated Circuits and Modules Laboratory, Nanjing Electronic Devices Institute, Nanjing 210016 (China)

    2015-06-15

    We demonstrate highly improved linearity in a nonlinear ferroelectric of Pb(Zr{sub 0.52}Ti{sub 0.48})-gated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistor (MIS-HEMT). Distinct double-hump feature in the transconductance-gate voltage (g{sub m}-V{sub g}) curve is observed, yielding remarkable enhancement in gate voltage swing as compared to MIS-HEMT with conventional linear gate dielectric. By incorporating the ferroelectric polarization into a self-consistent calculation, it is disclosed that in addition to the common hump corresponding to the onset of electron accumulation, the second hump at high current level is originated from the nonlinear polar nature of ferroelectric, which enhances the gate capacitance by increasing equivalent dielectric constant nonlinearly. This work paves a way for design of high linearity GaN MIS-HEMT by exploiting the nonlinear properties of dielectric.

  20. Role of Interface Charges on High-k Based Poly-Si and Metal Gate Nano-Scale MOSFETs

    Directory of Open Access Journals (Sweden)

    N. Shashank

    2011-01-01

    Full Text Available The characteristics of typical sub-100 nm high K gate dielectrics MOSFET with different gate materials are simulated by two dimensional device simulators (ATLAS and ATHENA. The impact of interface charges on the characteristics of Poly-Si and TiN metal gate MOSFETs are investigated. The simulation results shows that, at high interface charge densities, the devices with Poly-Si gate degrade much compared to metal gate MOSFET structures. Emphasis is given to study the mobility degradation which stands as a major hurdle with the implementation of high-k dielectrics in nano-scale devices. The advantages of using Watt model over other models for the extraction of channel mobility is also clearly explained. The performance of the high-k MOSFET with metal electrode and poly-silicon electrode is also compared for various interface state charges.

  1. Ballistic Thermal Transistor of Dielectric Four-terminal Nanostructures

    OpenAIRE

    Yang, Ping; Hu, Bambi

    2009-01-01

    We report a theoretical model for a thermal transistor in dielectric four-terminal nanostructures based on mesoscopic ballistic phonon transport, in which a steady thermal flow condition of system is obtained to set up the temperature field effect of gate. In the environment, thermal flow shows the transisting behaviors at low temperatures: saturation, asymmetry, and rectification. The phenomena can be explained reasonably by the nonlinear variation of the temperature dependence of propagatin...

  2. Hybrid nanoantennas for directional emission enhancement

    Energy Technology Data Exchange (ETDEWEB)

    Rusak, Evgenia; Staude, Isabelle, E-mail: isabelle.staude@anu.edu.au; Decker, Manuel; Sautter, Jürgen; Miroshnichenko, Andrey E.; Powell, David A.; Neshev, Dragomir N.; Kivshar, Yuri S. [Nonlinear Physics Centre and Centre for Ultrahigh Bandwidth Devices for Optical Systems (CUDOS), Research School of Physics and Engineering, The Australian National University, Canberra, ACT 2601 (Australia)

    2014-12-01

    Plasmonic and dielectric nanoparticles offer complementary strengths regarding their use as optical antenna elements. While plasmonic nanoparticles are well-known to provide strong decay rate enhancement for localized emitters, all-dielectric nanoparticles can enable high directivity combined with low losses. Here, we suggest a hybrid metal-dielectric nanoantenna consisting of a gold nanorod and a silicon nanodisk, which combines all these advantages. Our numerical analysis reveals a giant enhancement of directional emission together with simultaneously high radiation efficiency (exceeding 70%). The suggested hybrid nanoantenna has a subwavelength footprint, and all parameters and materials are chosen to be compatible with fabrication by two-step electron-beam lithography.

  3. Electronic band structure effects in monolayer, bilayer, and hybrid graphene structures

    Science.gov (United States)

    Puls, Conor

    Since its discovery in 2005, graphene has been the focus of intense theoretical and experimental study owing to its unique two-dimensional band structure and related electronic properties. In this thesis, we explore the electronic properties of graphene structures from several perspectives including the magnetoelectrical transport properties of monolayer graphene, gap engineering and measurements in bilayer graphene, and anomalous quantum oscillation in the monolayer-bilayer graphene hybrids. We also explored the device implications of our findings, and the application of some experimental techniques developed for the graphene work to the study of a complex oxide, Ca3Ru2O7, exhibiting properties of strongly correlated electrons. Graphene's high mobility and ballistic transport over device length scales, make it suitable for numerous applications. However, two big challenges remain in the way: maintaining high mobility in fabricated devices, and engineering a band gap to make graphene compatible with logical electronics and various optical devices. We address the first challenge by experimentally evaluating mobilities in scalable monolayer graphene-based field effect transistors (FETs) and dielectric-covered Hall bars. We find that the mobility is limited in these devices, and is roughly inversely proportional to doping. By considering interaction of graphene's Dirac fermions with local charged impurities at the interface between graphene and the top-gate dielectric, we find that Coulomb scattering is responsible for degraded mobility. Even in the cleanest devices, a band gap is still desirable for electronic applications of graphene. We address this challenge by probing the band structure of bilayer graphene, in which a field-tunable energy band gap has been theoretically proposed. We use planar tunneling spectroscopy of exfoliated bilayer graphene flakes demonstrate both measurement and control of the energy band gap. We find that both the Fermi level and

  4. Method of stress and measurement modes for research of thin dielectric films of MIS structures

    Science.gov (United States)

    Andreev, Vladimir V.; Maslovsky, Vladimir M.; Andreev, Dmitrii V.; Stolyarov, Alexander A.

    2016-12-01

    The paper proposes a new method of stress and measurement modes for research of thin dielectric films of MIS structures. The method realizes injection of the most part of charge into gate dielectric in one of stress modes: either current owing through dielectric is constant or voltage applied to gate is constant. In order to acquire an additional information about changing of charge state of MIS structure, the stress condition is interrupted in certain time ranges and during these time ranges the mode, in which structure is, is the mode of measurement. In measurement mode, changing of electric fields at interfaces between dielectric and semiconductor is monitored. By using these data, density of charge, which is accumulated in gate dielectric, and its centroid are calculated. Besides, by using these data, one studies processes of generation and relaxation of charge in dielectric. In order to raise precision of the method and reduce an influence of switching effects in measurement mode, density of measurement current should be much lower than density of stress current.

  5. Trapping of hydrogen in hafnium-based high kappa dielectric thin films for advanced CMOS applications

    Science.gov (United States)

    Ukirde, Vaishali

    In recent years, advanced high kappa gate dielectrics are under serious consideration to replace SiO2 and SiON in semiconductor industry. Hafnium-based dielectrics such as hafnium oxides, oxynitrides and Hf-based silicates/nitrided silicates are emerging as some of the most promising alternatives to SiO2/SiON gate dielectrics in complementary metal oxide semiconductor (CMOS) devices. Extensive efforts have been taken to understand the effects of hydrogen impurities in semiconductors and its behavior such as incorporation, diffusion, trapping and release with the aim of controlling and using it to optimize the performance of electronic device structures. In this dissertation, a systematic study of hydrogen trapping and the role of carbon impurities in various alternate gate dielectric candidates, HfO2/Si, HfxSi1-xO2/Si, HfON/Si and HfON(C)/Si is presented. It has been shown that processing of high kappa dielectrics may lead to some crystallization issues. Rutherford backscattering spectroscopy (RBS) for measuring oxygen deficiencies, elastic recoil detection analysis (ERDA) for quantifying hydrogen and nuclear reaction analysis (NRA) for quantifying carbon, X-ray diffraction (XRD) for measuring degree of crystallinity and X-ray photoelectron spectroscopy (XPS) were used to characterize these thin dielectric materials. ERDA data are used to characterize the evolution of hydrogen during annealing in hydrogen ambient in combination with preprocessing in oxygen and nitrogen.

  6. Analog and RF Performance Evaluation of Dual Metal Double Gate High-k Stack (DMDG-HKS MOSFETs

    Directory of Open Access Journals (Sweden)

    Santosh K. Gupta

    2013-07-01

    Full Text Available Dual Metal Gate (DMG technology was proposed to reduce the short channel effects (SCE’s of double gate MOSFETs. But, DMG alone is not enough to rectify the problem of gate tunneling current due to thinning of oxide layer with device downscaling. So, the use of high-k dielectric as gate oxide is considered to overcome the gate tunneling effect. But, high gate dielectric thickness leads to higher fringing fields leading to undesirable higher gate capacitance. So, the use of oxide stack i.e. a combination of silicon dioxide and high-k dielectric material is preferred as gate oxide. This paper presents the evaluation of the analog performance of nMOS dual metal double gate with high-k oxide stack (DMDG-HKS MOSFETs, comparing their performance with those exhibited by dual metal double gate (DMDG transistors and single metal double gate (SMDG transistors of identical dimensions. The analog performance has been investigated in subthreshold regime of operation by varying the channel length, gate oxide stack and considering different analog parameters extracted from the 2-D device simulations. It has been observed that the DMDG-HKS devices offer better transconductance gm, early voltage Va, intrinsic gain gm / gd, drain conductance gd, transconductance generation factor gm / Id, transition frequency fT, etc. The variation of these analog parameters has also been investigated by changing the equivalent oxide thickness (EOT and channel length of the DMDG-HKS transistor and has been observed that above parameters tends to improve with channel length and EOT as well.

  7. Allowable Generalized Quantum Gates

    Institute of Scientific and Technical Information of China (English)

    LONG Gui-Lu; LIU Yang; WANG Chuan

    2009-01-01

    In this paper, we give the most general duality gates, or generalized quantum gates in duality quantum computers. Here we show by explicit construction that a n-bit duality quantum computer with d slits can be simulated perfectly with an ordinary quantum computer with n qubits and one auxiliary qudit. Using this model, we give the most general form of duality gates which is of the form Σ(d-1)(i=0)piUi, and the Pi's are complex numbers with module less or equal to I and constrained by |Σipi|≤1.

  8. Study of GaN MOS-HEMT using ultrathin Al2O3 dielectric grown by atomic layer deposition

    Institute of Scientific and Technical Information of China (English)

    2009-01-01

    We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD) Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication process,a device with maximum transconductance of 150 mS/mm was produced. The drain current of this 0.8 μm gate-length MOS-HEMT could reach 800 mA/mm at +3.0 V gate bias. Compared to a conventional AlGaN/GaN HEMT of similar design,better interface property,lower leakage current,and smaller capacitance-voltage (C-V) hysteresis were obtained,and the superiority of this MOS-HEMT device structure with ALD Al2O3 gate dielectric was exhibited.

  9. Study of GaN MOS-HEMT using ultrathin Al2O3 dielectric grown by atomic layer deposition

    Institute of Scientific and Technical Information of China (English)

    YUE YuanZheng; HAO Yue; FENG Qian; ZHANG JinCheng; MA XiaoHua; NI JinYu

    2009-01-01

    We report on a GaN metal-oxide-semiconductor high electron mobility transistor (MOS-HEMT) using atomic-layer deposited (ALD) Al2O3 as the gate dielectric. Through further decreasing the thickness of the gate oxide to 3.5 nm and optimizing the device fabrication process, a device with maximum transconductance of 150 mS/mm was produced. The drain current of this 0.8 μm gate-length MOS-HEMT could reach 800 mA/mm at +3.0 V gate bias. Compared to a conventional AIGaN/GaN HEMT of similar design, better interface property, lower leakage current, and smaller capacitance-voltage (C-V) hysteresis were obtained, and the superiority of this MOS-HEMT device structure with ALD Al2O3 gate dielectric was exhibited.

  10. MoS2 based dual input logic AND gate

    Science.gov (United States)

    Martinez, Luis M.; Pinto, Nicholas J.; Naylor, Carl H.; Johnson, A. T. Charlie

    2016-12-01

    Crystalline monolayers of CVD MoS2 are used as the active semiconducting channel in a split-gate field effect transistor. The device demonstrates logic AND functionality that is controlled by independently addressing each gate terminal with ±10V. When +10V was simultaneously applied to both gates, the device was conductive (ON), while any other combination of gate voltages rendered the device resistive (OFF). The ON/OFF ratio of the device was ˜ 35 and the charge mobility using silicon nitride as the gate dielectric was 1.2cm2/V-s and 0.1cm2/V-s in the ON and OFF states respectively. Clear discrimination between the two states was observed when a simple circuit containing a load resistor was used to test the device logic AND functionality at 10Hz. One advantage is that split gate technology can reduce the number of devices required in complex circuits, leading to compact electronics and large scale integration based on intrinsic 2-D semiconducting materials.

  11. Physics-based surface potential, electric field and drain current model of a δp+ Si1-xGex gate-drain underlap nanoscale n-TFET

    Science.gov (United States)

    Goswami, Rupam; Bhowmick, Brinda; Baishya, Srimanta

    2016-09-01

    This article develops a 2-D model for surface potential, electric field and drain current for a nanoscale silicon tunnel field effect transistors (TFET) with a ?? layer at source-channel tunnel junction. Mathematical formulation based on the TFET physics has been carried out throughout the text taking into consideration the various parameters involving the mole-fraction-dependent ? layer. Both lateral and vertical electric fields have been modelled. A comparison is conducted between the modelled and the simulated values for three cases: polysilicon gate with silicon dioxide as gate dielectric, aluminium gate with alumina as gate dielectric and aluminium gate with hafnium oxide as gate dielectric. The model is found to be valid for all the three cases.

  12. Flexural-Phonon Scattering Induced by Electrostatic Gating in Graphene

    Science.gov (United States)

    Gunst, Tue; Kaasbjerg, Kristen; Brandbyge, Mads

    2017-01-01

    Graphene has an extremely high carrier mobility partly due to its planar mirror symmetry inhibiting scattering by the highly occupied acoustic flexural phonons. Electrostatic gating of a graphene device can break the planar mirror symmetry, yielding a coupling mechanism to the flexural phonons. We examine the effect of the gate-induced one-phonon scattering on the mobility for several gate geometries and dielectric environments using first-principles calculations based on density functional theory and the Boltzmann equation. We demonstrate that this scattering mechanism can be a mobility-limiting factor, and show how the carrier density and temperature scaling of the mobility depends on the electrostatic environment. Our findings may explain the high deformation potential for in-plane acoustic phonons extracted from experiments and, furthermore, suggest a direct relation between device symmetry and resulting mobility.

  13. Slide Gate Bricks

    Institute of Scientific and Technical Information of China (English)

    Wang Jing; Peng Xigao

    2010-01-01

    @@ 1 Scope This standard specifies the classification,shape,dimension,technical requirements,test methods,quality appraisal procedures,packing,marking,transportation,storage,and quality certificate of slide gate bricks.

  14. Gate current modeling and optimal design of nanoscale non-overlapped gate to source/drain MOSFET

    Institute of Scientific and Technical Information of China (English)

    Ashwani K.Rana; Narottam Chand; Vinod Kapoor

    2011-01-01

    A novel nanoscale MOSFET with a source/drain-to-gate non-overlapped and high-k spacer structure has been demonstrated to reduce the gate leakage current for the first time.The gate leakage behaviour of the novel MOSFET structure has been investigated with the help of a compact analytical model and Sentaurus simulation.A fringing gate electric field through the dielectric spacer induces an inversion layer in the non-overlap region to act as an extended S/D (source/drain) region.It is found that an optimal source/drain-to-gate non-overlapped and high-k spacer structure has reduced the gate leakage current to a great extent as compared to those of an overlapped structure.Further,the proposed structure had improved off current,subthreshold slope and drain induced barrier lowering (DIBL) characteristics.It is concluded that this structure solves the problem of high leakage current without introducing extra series resistance.

  15. Dielectric materials for electrical engineering

    CERN Document Server

    Martinez-Vega, Juan

    2013-01-01

    Part 1 is particularly concerned with physical properties, electrical ageing and modeling with topics such as the physics of charged dielectric materials, conduction mechanisms, dielectric relaxation, space charge, electric ageing and life end models and dielectric experimental characterization. Part 2 concerns some applications specific to dielectric materials: insulating oils for transformers, electrorheological fluids, electrolytic capacitors, ionic membranes, photovoltaic conversion, dielectric thermal control coatings for geostationary satellites, plastics recycling and piezoelectric poly

  16. High Mobility and Low Density of Trap States in Dual-Solid-Gated PbS Nanocrystal Field-Effect Transistors

    NARCIS (Netherlands)

    Nugraha, Mohamad Insan; Haeusermann, Roger; Bisri, Satria Zulkarnaen; Matsui, Hiroyuki; Sytnyk, Mykhailo; Heiss, Wolfgang; Takeya, Jun; Loi, Maria Antonietta

    2015-01-01

    Dual-gated PbS nanocrystal field-effect transistors employing SiO2 and Cytop as gate dielectrics are fabricated. The obtained electron mobility (0.2 cm(2) V-1 s(-1)) and the high on/off ratio (10(5)-10(6)), show that the controlled nanocrystal assembly (obtained with self-assembled monolayers), as w

  17. Screening-induced surface polar optical phonon scattering in dual-gated graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Hu, Bo, E-mail: hubo2011@semi.ac.cn

    2015-03-15

    The effect of surface polar optical phonons (SOs) from the dielectric layers on electron mobility in dual-gated graphene field effect transistors (GFETs) is studied theoretically. By taking into account SO scattering of electron as a main scattering mechanism, the electron mobility is calculated by the iterative solution of Boltzmann transport equation. In treating scattering with the SO modes, the dynamic dielectric screening is included and compared to the static dielectric screening and the dielectric screening in the static limit. It is found that the dynamic dielectric screening effect plays an important role in the range of low net carrier density. More importantly, in-plane acoustic phonon scattering and charged impurity scattering are also included in the total mobility for SiO{sub 2}-supported GFETs with various high-κ top-gate dielectric layers considered. The calculated total mobility results suggest both Al{sub 2}O{sub 3} and AlN are the promising candidate dielectric layers for the enhancement in room temperature mobility of graphene in the future.

  18. Hot plasma dielectric tensor

    NARCIS (Netherlands)

    Westerhof, E.

    1996-01-01

    The hot plasma dielectric tensor is discussed in its various approximations. Collisionless cyclotron resonant damping and ion/electron Bernstein waves are discussed to exemplify the significance of a kinetic description of plasma waves.

  19. Advanced insulated gate bipolar transistor gate drive

    Science.gov (United States)

    Short, James Evans; West, Shawn Michael; Fabean, Robert J.

    2009-08-04

    A gate drive for an insulated gate bipolar transistor (IGBT) includes a control and protection module coupled to a collector terminal of the IGBT, an optical communications module coupled to the control and protection module, a power supply module coupled to the control and protection module and an output power stage module with inputs coupled to the power supply module and the control and protection module, and outputs coupled to a gate terminal and an emitter terminal of the IGBT. The optical communications module is configured to send control signals to the control and protection module. The power supply module is configured to distribute inputted power to the control and protection module. The control and protection module outputs on/off, soft turn-off and/or soft turn-on signals to the output power stage module, which, in turn, supplies a current based on the signal(s) from the control and protection module for charging or discharging an input capacitance of the IGBT.

  20. On controlling the electronic states of shallow donors using a finite-size metal gate

    Energy Technology Data Exchange (ETDEWEB)

    Levchuk, E. A., E-mail: liauchuk@bsu.by; Makarenko, L. F. [Belarusian State University (Belarus)

    2016-01-15

    The effect of an external electric field on the states of a shallow donor near a semiconductor surface is numerically simulated. A disk-shaped metal gate is considered as an electric-field source. The wavefunctions and energies of bound states are determined by the finite-element method. The critical characteristics of electron relocation between the donor and gate are determined for various gate diameters and boundary conditions, taking into account dielectric mismatch. The empirical dependences of these characteristics on the geometrical parameters and semiconductor properties are obtained. A simple trial function is proposed, which can be used to calculate the critical parameters using the Ritz variational method.

  1. Temperature dependence of the dielectric constant of acrylic dielectric elastomer

    Energy Technology Data Exchange (ETDEWEB)

    Sheng, Junjie; Chen, Hualing; Li, Bo; Chang, Longfei [Xi' an Jiaotong University, State Key Laboratory for Strength and Vibration of Mechanical Structures, Xi' an (China); Xi' an Jiaotong University, School of Mechanical Engineering, Xi' an (China)

    2013-02-15

    The dielectric constant is an essential electrical parameter to the achievable voltage-induced deformation of the dielectric elastomer. This paper primarily focuses on the temperature dependence of the dielectric constant (within the range of 173 K to 373 K) for the most widely used acrylic dielectric elastomer (VHB 4910). First the dielectric constant was investigated experimentally with the broadband dielectric spectrometer (BDS). Results showed that the dielectric constant first increased with temperature up to a peak value and then dropped to a relative small value. Then by analyzing the fitted curves, the Cole-Cole dispersion equation was found better to characterize the rising process before the peak values than the Debye dispersion equation, while the decrease process afterward can be well described by the simple Debye model. Finally, a mathematical model of dielectric constant of VHB 4910 was obtained from the fitted results which can be used to further probe the electromechanical stability of the dielectric elastomers. (orig.)

  2. Dielectric spectroscopy in agrophysics

    Science.gov (United States)

    Skierucha, W.; Wilczek, A.; Szypłowska, A.

    2012-04-01

    The paper presents scientific foundation and some examples of agrophysical applications of dielectric spectroscopy techniques. The aim of agrophysics is to apply physical methods and techniques for studies of materials and processes which occur in agriculture. Dielectric spectroscopy, which describes the dielectric properties of a sample as a function of frequency, may be successfully used for examinations of properties of various materials. Possible test materials may include agrophysical objects such as soil, fruit, vegetables, intermediate and final products of the food industry, grain, oils, etc. Dielectric spectroscopy techniques enable non-destructive and non-invasive measurements of the agricultural materials, therefore providing tools for rapid evaluation of their water content and quality. There is a limited number of research in the field of dielectric spectroscopy of agricultural objects, which is caused by the relatively high cost of the respective measurement equipment. With the fast development of modern technology, especially in high frequency applications, dielectric spectroscopy has great potential of expansion in agrophysics, both in cognitive and utilitarian aspects.

  3. THERMALLY CLEAVABLE HYBRID MATERIALS

    Directory of Open Access Journals (Sweden)

    Constantin Gaina

    2011-12-01

    Full Text Available Thermally cleavable hybrid materials were prepared by the Diels-Alder cycloaddition reaction of poly(vinyl furfural to N phenylmaleimido-N’-(triethoxysilylpropylurea followed by the sol-gel condensation reaction of trietoxysilyl groups with water and acetic acid. Thermal and dynamic mechanical analysis, dielectric and FTIR spectroscopy were used to characterize the structure and properties of the composites. The size of the inorganic silica particles in the hybrid material varied dependent on the silica content. The DSC study of the prepared materials revealed that the cleavage process of the formed cycloadducts takes place at temperatures varying between 143-165°C and is an endothermic process.

  4. Attosecond clocking of scattering dynamics in dielectrics

    Science.gov (United States)

    Kling, Matthias

    2016-05-01

    In the past few years electronic-device scaling has progressed rapidly and miniaturization has reached physical gate lengths below 100 nm, heralding the age of nanoelectronics. Besides the effort in size scaling of integrated circuits, tremendous progress has recently been made in increasing the switching speed where strong-field-based ``dielectric-electronics'' may push it towards the petahertz frontier. In this contest, the investigation of the electronic collisional dynamics occurring in a dielectric material is of primary importance to fully understand the transport properties of such future devices. Here, we demonstrate attosecond chronoscopy of electron collisions in SiO2. In our experiment, a stream of isolated aerodynamically focused SiO2 nanoparticles of 50 nm diameter was delivered into the laser interaction region. Photoemission is initiated by an isolated 250 as pulse at 35 eV and the electron dynamics is traced by attosecond streaking using a delayed few-cycle laser pulse at 700 nm. Electrons were detected by a kilohertz, single-shot velocity-map imaging spectrometer, permitting to separate frames containing nanoparticle signals from frames containing the response of the reference gas only. We find that the nanoparticle photoemission exhibits a positive temporal shift with respect to the reference. In order to understand the physical origin of the shift we performed semi-classical Monte-Carlo trajectory simulations taking into account the near-field distributions in- and outside the nanoparticles as obtained from Mie theory. The simulations indicate a pronounced dependence of the streaking time shift near the highest measured electron energies on the inelastic scattering time, while elastic scattering only shows a small influence on the streaking time shift for typical dielectric materials. We envision our approach to provide direct time-domain access to inelastic scattering for a wide range of dielectrics.

  5. High performance top-gated indium–zinc–oxide thin film transistors with in-situ formed HfO{sub 2} gate insulator

    Energy Technology Data Exchange (ETDEWEB)

    Song, Yang, E-mail: yang_song@brown.edu [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); Zaslavsky, A. [Department of Physics, Brown University, 182 Hope Street, Providence, RI 02912 (United States); School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States); Paine, D.C. [School of Engineering, Brown University, 184 Hope Street, Providence, RI 02912 (United States)

    2016-09-01

    We report on top-gated indium–zinc–oxide (IZO) thin film transistors (TFTs) with an in-situ formed HfO{sub 2} gate dielectric insulator. Building on our previous demonstration of high-performance IZO TFTs with Al{sub 2}O{sub 3}/HfO{sub 2} gate dielectric, we now report on a one-step process, in which Hf is evaporated onto the 20 nm thick IZO channel, forming a partially oxidized HfO{sub x} layer, without any additional insulator in-between. After annealing in air at 300 °C, the in-situ reaction between partially oxidized Hf and IZO forms a high quality HfO{sub 2} gate insulator with a low interface trapped charge density N{sub TC} ~ 2.3 × 10{sup 11} cm{sup −2} and acceptably low gate leakage < 3 × 10{sup −7} A/cm{sup 2} at gate voltage V{sub G} = 1 V. The annealed TFTs with gate length L{sub G} = 50 μm have high mobility ~ 95 cm{sup 2}/V ∙ s (determined via the Y-function technique), high on/off ratio ~ 10{sup 7}, near-zero threshold voltage V{sub T} = − 0.02 V, and a subthreshold swing of 0.062 V/decade, near the theoretical limit. The on-current of our proof-of-concept TFTs is relatively low, but can be improved by reducing L{sub G}, indicating that high-performance top-gated HfO{sub 2}-isolated IZO TFTs can be fabricated using a single-step in-situ dielectric formation approach. - Highlights: • High-performance indium–zinc–oxide (IZO) thin film transistors (TFTs). • Single-step in-situ dielectric formation approach simplifies fabrication process. • During anneal, reaction between HfO{sub x} and IZO channel forms a high quality HfO{sub 2} layer. • Gate insulator HfO{sub 2} shows low interface trapped charge and small gate leakage. • TFTs have high mobility, near-zero threshold voltage, and a low subthreshold swing.

  6. High dielectric, dynamic mechanical and thermal properties of polyimide composite film filled with carbon-coated silver nanowires

    Science.gov (United States)

    Wang, Lisi; Piao, Xiaoyu; Zou, Heng; Wang, Ya; Li, Hengfeng

    2015-01-01

    High dielectric permittivity materials are much desirable in the electric industry. Filling polymer matrix with conductive powders to form percolative composites is one of the most promising methods to achieve high dielectric permittivity. However, they do not always provide high mechanical properties and thermal stability, which seriously limit their applications. In this study, we present the preparation of functional core-shell structured silver nanowires/polyimide (AgNWs/PI) hybrid film with high dielectric permittivity and low loss dielectric. The core-shell structure of AgNWs was characterized by transmission electric microscopy. The dynamical mechanical analysis showed that AgNWs/PI hybrid films had relative high dynamic mechanical properties with storage modules over 1 Gpa. Moreover, the hybrid films exhibited excellent thermal stability with 5 % weight-loss temperature above 500 °C. The dielectric properties of the carbon-coated AgNWs hybrid films were remarkably improved. The maximum dielectric permittivity of hybrid films is 126 at 102 Hz, which was 39 times higher than that of pure PI matrix, while the dielectric loss of that is still remained at a low value. This study showed a new method to improve the dielectric, dynamic mechanical and thermal properties of films.

  7. Maximizing the dielectric response of molecular thin films via quantum chemical design.

    Science.gov (United States)

    Heitzer, Henry M; Marks, Tobin J; Ratner, Mark A

    2014-12-23

    Developing high-capacitance organic gate dielectrics is critical for advances in electronic circuitry based on unconventional semiconductors. While high-dielectric constant molecular substances are known, the mechanism of dielectric response and the fundamental chemical design principles are not well understood. Using a plane-wave density functional theory formalism, we show that it is possible to map the atomic-scale dielectric profiles of molecule-based materials while capturing important bulk characteristics. For molecular films, this approach reveals how basic materials properties such as surface coverage density, molecular tilt angle, and π-system planarity can dramatically influence dielectric response. Additionally, relatively modest molecular backbone and substituent variations can be employed to substantially enhance film dielectric response. For dense surface coverages and proper molecular alignment, conjugated hydrocarbon chains can achieve dielectric constants of >8.0, more than 3 times that of analogous saturated chains, ∼2.5. However, this conjugation-related dielectric enhancement depends on proper molecular orientation and planarization, with enhancements up to 60% for proper molecular alignment with the applied field and an additional 30% for conformations such as coplanarity in extended π-systems. Conjugation length is not the only determinant of dielectric response, and appended polarizable high-Z substituents can increase molecular film response more than 2-fold, affording estimated capacitances of >9.0 μF/cm2. However, in large π-systems, polar substituent effects are substantially attenuated.

  8. Electrostatic fields in hybrid heterojunctions: Field-effect transistor, topological insulator, & thermoelectronic application

    Science.gov (United States)

    Ireland, Robert Matthew

    overall structure in order to further interrogate and modify device behavior. The additional gate is provided by introducing a polymer dielectric layer and embedding charges in this dielectric by corona charging method. This work will lead to improved design of hybrid devices because we can obtain benefits of both materials to achieve new performance records (ZT>0.1 in thermoelectric polymer-particle composites) and capabilities (topological insulator behavior), and also use heterojunctions as a basis to study and design materials or systems (tellurium/OSC transistors).

  9. A single dielectric nanolaser

    Science.gov (United States)

    Huang, Tsung-Yu; Yen, Ta-Jen

    2016-09-01

    To conquer Ohmic losses from metal and enhance pump absorption efficiency of a nanolaser based on surface plasmon polariton, we theoretically calculate the first magnetic and electric scattering coefficient of a dielectric sphere under a plane wave excitation with a dielectric constant of around 12. From this calculation, we could retrieve both negative effective permittivity and permeability of the sphere simultaneously at frequencies around 153 THz in the aids of Lewin's theory and the power distribution clearly demonstrate the expected negative Goos-Hänchen effect, which usually occurred in a negative refractive waveguide, thus creating two energy vortices to trap incident energy and then promoting the pump absorption efficiency. Meanwhile, a magnetic lasing mode at 167.3 THz is demonstrated and reveals a magnetic dipole resonance mode and a circulating energy flow within the dielectric sphere, providing a possible stopped light feedback mechanism to enable the all-dielectric nanolaser. More importantly, the corresponding mode volume is reduced to 0.01λ3 and a gain threshold of 5.1×103 is obtained. To validate our design of all-dielectric nanolaser, we employ finite-difference-time-domain simulation software to examine the behavior of the nanolaser. From simulation, we could obtain a pinned-down population inversion of 0.001 and a lasing peak at around 166.5 THz, which is very consistent with the prediction of Mie theory. Finally, according to Mie theory, we can regard the all-dielectric nanolaser as the excitation of material polariton and thus could make an analogue between lasing modes of the dielectric and metallic nanoparticles.

  10. A nanomechanical Fredkin gate.

    Science.gov (United States)

    Wenzler, Josef-Stefan; Dunn, Tyler; Toffoli, Tommaso; Mohanty, Pritiraj

    2014-01-08

    Irreversible logic operations inevitably discard information, setting fundamental limitations on the flexibility and the efficiency of modern computation. To circumvent the limit imposed by the von Neumann-Landauer (VNL) principle, an important objective is the development of reversible logic gates, as proposed by Fredkin, Toffoli, Wilczek, Feynman, and others. Here, we present a novel nanomechanical logic architecture for implementing a Fredkin gate, a universal logic gate from which any reversible computation can be built. In addition to verifying the truth table, we demonstrate operation of the device as an AND, OR, NOT, and FANOUT gate. Excluding losses due to resonator dissipation and transduction, which will require significant improvement in order to minimize the overall energy cost, our device requires an energy of order 10(4) kT per logic operation, similar in magnitude to state-of-the-art transistor-based technologies. Ultimately, reversible nanomechanical logic gates could play a crucial role in developing highly efficient reversible computers, with implications for efficient error correction and quantum computing.

  11. Preparation and property of graphene oxide core-shell hybrid particles/silicone rubber dielectric elastomer composites%氧化石墨烯核-壳杂化粒子/硅橡胶介电弹性体复合材料的制备与性能

    Institute of Scientific and Technical Information of China (English)

    王明路; 宁南英; 张静; 张立群; 田明

    2016-01-01

    采用阳离子聚电解质聚二烯丙基二甲基氯化铵(PDDA)改性 SiO2,再通过静电自组装制备了 SiO2-PD-DA-氧化石墨烯(GO)核-壳杂化粒子。采用溶液共混法将 SiO2-PDDA-GO引入到高温硫化硅橡胶(SR)中,制备了SiO2-PDDA-GO/SR介电弹性体复合材料。结果表明:该方法能实现 GO 在 SiO2表面大面积的包覆,解决了 GO容易自聚集的问题,且PDDA具有还原 GO的作用,无需再对 GO核-壳杂化粒子/SR复合材料进行原位热还原,简化了实验方案,节能环保。SiO2-PDDA-GO填充量为60wt%时,在100 Hz 频率下,SiO2-PDDA-GO/SR 介电弹性体复合材料的介电常数为21.53,是 SR的11.6倍,介电损耗保持较低值,同时,复合材料的模量保持在较低水平。在电场强度为2.48 kV/mm时,60wt%的SiO2-PDDA-GO/SR介电弹性体复合材料横向电致形变在同一电场强度下与 SR相比增加了15倍。%Cationic polyelectrolyte poly(diallyldimethylammonium chloride)(PDDA)was used to modify SiO2 ,and SiO2-PDDA-graphite oxide (GO)core-shell hybrid particles were prepared by electrostatic self-assembly.By intro-ducing SiO2-PDDA-GO into high-temperature vulcanization silicone rubber (SR)with solution blending method, SiO2-PDDA-GO/SR dielectric elastomer composites were prepared.Results show that this method can realize GO large surface coating on surface of SiO2 to prevent GO from self-agglomerating.GO core-shell hybrid particles/SR composites were obtained without in-situ thermal reduction because PDDA can reduce GO,made experimental scheme simple and environmental protection.The dielectric constant of SiO2-PDDA-GO/SR dielectric composite at 100 Hz increases to 21.53 with 60wt% SiO2-PDDA-GO which is 11.6 times than SR,and dielectric loss remains at low level.Meanwhile,modulus of composites remains low level.The lateral actuation strain of SiO2-PDDA-GO/SR dielectric elastomer composites with 60wt% SiO2-PDDA-GO at 2.48 kV/mm compared with pure SR increases 15 fold under same

  12. Hysteresis-Free Nanosecond Pulsed Electrical Characterization of Top-Gated Graphene Transistors

    Science.gov (United States)

    Carrion, Enrique A.; Serov, Andrey Y.; Islam, Sharnali; Behnam, Ashkan; Malik, Akshay; Xiong, Feng; Bianchi, Massimiliano; Sordan, Roman; Pop, Eric

    2014-05-01

    We measure top-gated graphene field effect transistors (GFETs) with nanosecond-range pulsed gate and drain voltages. Due to high-k dielectric or graphene imperfections, the drain current decreases ~10% over time scales of ~10 us, consistent with charge trapping mechanisms. Pulsed operation leads to hysteresis-free I-V characteristics, which are studied with pulses as short as 75 ns and 150 ns at the drain and gate, respectively. The pulsed operation enables reliable extraction of GFET intrinsic transconductance and mobility values independent of sweep direction, which are up to a factor of two higher than those obtained from simple DC characterization. We also observe drain-bias-induced charge trapping effects at lateral fields greater than 0.1 V/um. In addition, using modeling and capacitance-voltage measurements we extract charge trap densities up to 10^12 1/cm^2 in the top gate dielectric (here Al2O3). Our study illustrates important time- and field-dependent imperfections of top-gated GFETs with high-k dielectrics, which must be carefully considered for future developments of this technology

  13. Experimental study on the dielectric properties of polyacrylate dielectric elastomer

    Science.gov (United States)

    Qiang, Junhua; Chen, Hualing; Li, Bo

    2012-02-01

    The dielectric constant of elastomeric dielectric material is an essential physical parameter, whose value may affect the electromechanical deformation of a dielectric elastomer actuator. Since the dielectric constant is influenced by several external factors as reported before, and no certain value has been confirmed to our knowledge, in the present paper, on the basis of systematical comparison of recent past literature, we conducted extensive works on the measurement of dielectric properties of VHB films, involving five influencing factors: prestretch (both equal and unequal biaxial), electrical frequency, electrode material, stress relaxation time and temperature. Experimental results directly show that the dielectric response changes according to these factors, based on which we investigate the significance of each factor, especially the interaction of two external conditions on the dielectric constant of deformable dielectric, by presenting a physical picture of the mechanism of polarization.

  14. Chemical sensitivity of Mo gate Mos capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Lombardi, R.M.; Aragon, R. [Laboratorio de Peliculas delgadas, Facultad de Ingenieria, Paseo Colon 850, 1063, Buenos Aires (Argentina)

    2006-07-01

    Mo gate Mos capacitors exhibit a negative shift of their C-V characteristic by up to 240 mV, at 125 C, in response to 1000 ppm hydrogen, in controlled nitrogen atmospheres. The experimental methods for obtaining capacitance and conductance, as a function of polarisation voltage, as well as the relevant equivalent circuits are reviewed. The single-state interface state density, at the semiconductor-dielectric interface, decreases from 2.66 x 10{sup 11} cm{sup -2} e-v{sup -1}, in pure nitrogen, to 2.5 x 10{sup 11} cm{sup -2} e-v{sup -1} in 1000 ppm hydrogen in nitrogen mixtures, at this temperature. (Author)

  15. The Gates at Pipe Spring National Monument, Arizona (gates)

    Data.gov (United States)

    National Park Service, Department of the Interior — This is an Arc/Info coverage consisting of 7 points representing gates at Pipe Spring National Monument, Arizona. The gates were collected by a Trimble GeoXT GPS...

  16. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  17. High-Sensitivity, Highly Transparent, Gel-Gated MoS2 Phototransistor on Biodegradable Nanopaper

    KAUST Repository

    Zhang, Qing

    2016-06-21

    Transition metal dichalcogenides hold great promise for a variety of novel electrical, optical and mechanical devices and applications. Among them, molybdenum disulphide (MoS2) is gaining increasing attention as the gate dielectric and semiconductive channel for high-perfomance field effect transistors. Here we report on the first MoS2 phototransistor built on flexible, transparent and biodegradable substrate with electrolyte gate dielectric. We have carried out systematic studies on its electrical and optoelectronic properties. The MoS2 phototransistor exhibited excellent photo responsivity of ~1.5 kA/W, about two times higher compared to typical back-gated devices reported in previous studies. The device is highly transparent at the same time with an average optical transmittance of 82%. Successful fabrication of phototransistors on flexible cellulose nanopaper with excellent performance and transparency suggests that it is feasible to achieve an ecofriendly, biodegradable phototransistor with great photoresponsivity, broad spectral range and durable flexibility.

  18. Thickness and dielectric constant determination of thin dielectric layers

    NARCIS (Netherlands)

    Bruijn, de Helene E.; Minor, Marcel; Kooyman, Rob P.H.; Greve, Jan

    1993-01-01

    We derive a method for the determination of the dielectric constant and thickness of a thin dielectric layer, deposited on top of a thick dielectric layer which is in turn present on a metal film. Reflection of p- and s-polarized light from the metal layer yields minima for certain angles of inciden

  19. Controlling birefringence in dielectrics

    Science.gov (United States)

    Danner, Aaron J.; Tyc, Tomáš; Leonhardt, Ulf

    2011-06-01

    Birefringence, from the very essence of the word itself, refers to the splitting of light rays into two parts. In natural birefringent materials, this splitting is a beautiful phenomenon, resulting in the perception of a double image. In optical metamaterials, birefringence is often an unwanted side effect of forcing a device designed through transformation optics to operate in dielectrics. One polarization is usually implemented in dielectrics, and the other is sacrificed. Here we show, with techniques beyond transformation optics, that this need not be the case, that both polarizations can be controlled to perform useful tasks in dielectrics, and that rays, at all incident angles, can even follow different trajectories through a device and emerge together as if the birefringence did not exist at all. A number of examples are shown, including a combination Maxwell fisheye/Luneburg lens that performs a useful task and is achievable with current fabrication materials.

  20. Dielectric assist accelerating structure

    Science.gov (United States)

    Satoh, D.; Yoshida, M.; Hayashizaki, N.

    2016-01-01

    A higher-order TM02 n mode accelerating structure is proposed based on a novel concept of dielectric loaded rf cavities. This accelerating structure consists of ultralow-loss dielectric cylinders and disks with irises which are periodically arranged in a metallic enclosure. Unlike conventional dielectric loaded accelerating structures, most of the rf power is stored in the vacuum space near the beam axis, leading to a significant reduction of the wall loss, much lower than that of conventional normal-conducting linac structures. This allows us to realize an extremely high quality factor and a very high shunt impedance at room temperature. A simulation of a 5 cell prototype design with an existing alumina ceramic indicates an unloaded quality factor of the accelerating mode over 120 000 and a shunt impedance exceeding 650 M Ω /m at room temperature.

  1. Dielectrically Loaded Biconical Antennas

    Science.gov (United States)

    Nusseibeh, Fouad Ahmed

    1995-01-01

    Biconical antennas are of great interest to those who deal with broadband applications including the transmission/reception of pulses. In particular, wide-angle conical antennas are an attractive choice in many applications including Electronic Support Measures (ESM) and the measurements of transient surface currents and charge densities on aircraft. Dielectric loading in the interior region of a conical antenna can be used to reduce the size of the antenna especially at low frequencies and/or for structural strength. Therefore, having an analytical solution for the input impedance and the frequency response is very helpful in optimizing the design and understanding the behavior of the antenna. From the quasi-analytical solution for the input impedance and the electric field of a wide-angle conical antenna, it can be seen that the dielectric loading in the antenna region improves the input impedance at low frequencies, but increases the number of resonance points and the magnitude of these peaks. When an inhomogeneous dielectric load is used, the magnitude of the resonance peaks is decreased (depending on the way the load is distributed), improving the input impedance of the antenna significantly. Introducing a dielectric load in the interior region of an electrically short receiving cone makes the antenna behave as an electrically longer antenna. However, this is not true for the case for electrical1y long antennas. For the case of pulse transmission, the dielectric load affects only the amplitude. Of course, if the dielectric fills the whole space, both transmitting and receiving antennas behave as electrically longer antennas.

  2. Absorption in dielectric models

    CERN Document Server

    Churchill, R J

    2015-01-01

    We develop a classical microscopic model of a dielectric. The model features nonlinear interaction terms between polarizable dipoles and lattice vibrations. The lattice vibrations are found to act as a pseudo-reservoir, giving broadband absorption of electromagnetic radiation without the addition of damping terms in the dynamics. The effective permittivity is calculated using a perturbative iteration method and is found to have the form associated with real dielectrics. Spatial dispersion is naturally included in the model and we also calculate the wavevector dependence of the permittivity.

  3. Optics of dielectric microstructures

    DEFF Research Database (Denmark)

    Søndergaard, Thomas

    2002-01-01

    microstructures, will be presented in the part I of this thesis consisting of the chapters 2-5. An introductions is given in chapter 2. In part I three methods are presented for calculating spontaneous and classical emission from sources in dielectric microstructures. The first method presented in chapter 3...... near fields and far fields generated by a dipole emitter in finite-sized dielectric disks. A collection of results obtained within the second topic, planar photonic crystal waveguides, are presented in part II of this thesis consisting of the chapters 6-10. Chapter 6 contains a further introduction...

  4. Thermally switchable dielectrics

    Science.gov (United States)

    Dirk, Shawn M.; Johnson, Ross S.

    2013-04-30

    Precursor polymers to conjugated polymers, such as poly(phenylene vinylene), poly(poly(thiophene vinylene), poly(aniline vinylene), and poly(pyrrole vinylene), can be used as thermally switchable capacitor dielectrics that fail at a specific temperature due to the non-conjugated precursor polymer irreversibly switching from an insulator to the conjugated polymer, which serves as a bleed resistor. The precursor polymer is a good dielectric until it reaches a specific temperature determined by the stability of the leaving groups. Conjugation of the polymer backbone at high temperature effectively disables the capacitor, providing a `built-in` safety mechanism for electronic devices.

  5. Effects of gate-last and gate-first process on deep submicron inversion-mode InGaAs n-channel metal-oxide-semiconductor field effect transistors

    Science.gov (United States)

    Gu, J. J.; Wu, Y. Q.; Ye, P. D.

    2011-03-01

    Recently, encouraging progress has been made on surface-channel inversion-mode In-rich InGaAs NMOSFETs with superior drive current, high transconductance and minuscule gate leakage, using atomic layer deposited (ALD) high-k dielectrics. Although gate-last process is favorable for high-k/III-V integration, high-speed logic devices require a self-aligned gate-first process for reducing the parasitic resistance and overlap capacitance. On the other hand, a gate-first process usually requires higher thermal budget and may degrade the III-V device performance. In this paper, we systematically investigate the thermal budget of gate-last and gate-first process for deep-submicron InGaAs MOSFETs. We conclude that the thermal instability of (NH4)2S as the pretreatment before ALD gate dielectric formation leads to the potential failure of enhancement-mode operation and deteriorates interface quality in the gate-first process. We thus report on the detailed study of scaling metrics of deep-submicron self-aligned InGaAs MOSFET without sulfur passivation, featuring optimized threshold voltage and negligible off-state degradation.

  6. Scanning Gate Spectroscopy on Nanoclusters

    OpenAIRE

    Gurevich, L.; Canali, L.; Kouwenhoven, L.P.

    1999-01-01

    A gated probe for scanning tunnelling microscopy (STM) has been developed. The probe extends normal STM operations by means of an additional electrode fabricated next to the tunnelling tip. The extra electrode does not make contact with the sample and can be used as a gate. We report on the recipe used for fabricating the tunnelling tip and the gate electrode on a silicon nitride cantilever. We demonstrate the functioning of the scanning gate probes by performing single-electron tunnelling sp...

  7. Capacitance of graphene in aqueous electrolytes: The effects of dielectric saturation of water and finite size of ions

    Science.gov (United States)

    Sharma, P.; Mišković, Z. L.

    2014-09-01

    We present a theoretical model for electrolytically top-gated graphene, in which we analyze the effects of dielectric saturation of water due to possibly strong electric fields near the surface of a highly charged graphene, as well as the steric effects due to the finite size of salt ions in an aqueous electrolyte. By combining two well-established analytical models for those two effects, we show that the total capacitance of the solution-gated graphene is dominated by its quantum capacitance for gating potentials ≲1V, which is the range of primary interest for most sensor applications of graphene. On the other hand, at the potentials ≳1V the total capacitance is dominated by a universal capacitance of the electric double layer in the electrolyte, which exhibits a dramatic decrease of capacitance with increasing gating potential due to the interplay of a fully saturated dielectric constant of water and ion crowding near graphene.

  8. Stanford, Duke, Rice,... and Gates?

    Science.gov (United States)

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  9. Stanford, Duke, Rice,... and Gates?

    Science.gov (United States)

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  10. The four-gate transistor

    Science.gov (United States)

    Mojarradi, M. M.; Cristoveanu, S.; Allibert, F.; France, G.; Blalock, B.; Durfrene, B.

    2002-01-01

    The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

  11. Gate-tunable high mobility remote-doped InSb/In1−xAlxSb quantum well

    NARCIS (Netherlands)

    Yi, W.; Kiselev, A.A.; Thorp, J.; Noah, R.; Nguyen, B.M.; Bui, S.; Rajavel, R.D.; Hussain, T.; Gyure, M.F.; Kratz, P.; Qian, Q.; Manfra, M.J.; Pribiag, V.S.; Kouwenhoven, L.P.; Marcus, C.M.; Sokolich, M.

    2015-01-01

    Gate-tunable high-mobility InSb/In1−xAlxSb quantum wells (QWs) grown on GaAs substrates are reported. The QW two-dimensional electron gas (2DEG) channel mobility in excess of 200 000 cm2/V s is measured at T = 1.8 K. In asymmetrically remote-doped samples with an HfO2 gate dielectric formed by atomi

  12. Impact of implantation on the properties of N 2O-nitrided oxides of p +- and n +-gate MOS devices

    Science.gov (United States)

    Naumova, O. V.; Fomin, B. I.; Sakharova, N. V.; Ilnitsky, M. A.; Popov, V. P.

    2009-05-01

    The impact of the gate implantation on properties of N2O-nitrided thermal oxides MOS dielectric layers were evaluated in this study via current-voltage, j-ramp and current-temperature techniques. The data obtained show that implantation with boron of poly-Si gates can result in generation of border traps in oxides. The energy position of traps generated in the oxides after Fowler-Nordheim voltage stress and after hard breakdown treatments were evaluated.

  13. Flexible Dielectric Nanocomposites with Ultrawide Zero-Temperature Coefficient Windows for Electrical Energy Storage and Conversion under Extreme Conditions.

    Science.gov (United States)

    Shehzad, Khurram; Xu, Yang; Gao, Chao; Li, Hanying; Dang, Zhi-Min; Hasan, Tawfique; Luo, Jack; Duan, Xiangfeng

    2017-03-01

    Polymer dielectrics offer key advantages over their ceramic counterparts such as flexibility, scalability, low cost, and high breakdown voltages. However, a major drawback that limits more widespread application of polymer dielectrics is their temperature-dependent dielectric properties. Achieving dielectric constants with low/zero-temperature coefficient (L/0TC) over a broad temperature range is essential for applications in diverse technologies. Here, we report a hybrid filler strategy to produce polymer composites with an ultrawide L/0TC window of dielectric constant, as well as a significantly enhanced dielectric value, maximum energy storage density, thermal conductivity, and stability. By creating a series of percolative polymer composites, we demonstrated hybrid carbon filler based composites can exhibit a zero-temperature coefficient window of 200 °C (from -50 to 150 °C), the widest 0TC window for all polymer composite dielectrics reported to date. We further show the electric and dielectric temperature coefficient of the composites is highly stable against stretching and bending, even under AC electric field with frequency up to 1 MHz. We envision that our method will push the functional limits of polymer dielectrics for flexible electronics in extreme conditions such as in hybrid vehicles, aerospace, power electronics, and oil/gas exploration.

  14. Microstructural and dielectric susceptibility effects on predictions of dielectric properties

    Energy Technology Data Exchange (ETDEWEB)

    Ferris, K.F.; Exarhos, G.J. [Pacific Northwest National Lab., Richland, WA (United States); Risser, S.M. [Texas A& M Univ., Commerce, TX (United States)

    1997-12-01

    In modeling the dielectric properties of inhomogeneous materials, the treatment of the electric field interactions differentiate the usual modeling formalisms (such as the Maxwell-Garnett and Bruggeman effective medium methods) and their accuracy. In this paper, we show that the performance of effective medium methods is dependent upon a number of variables - defect concentration, alignment, and the dielectric constant of the material itself. Using our previously developed finite element model of an inhomogeneous dielectric, we have developed models for a number of dielectric films of varying dielectric constant and microstructures. Alignment of defects parallel to the applied field and the larger defect aspect ratios increase the overall dielectric constant. The extent of these effects is dependent on the dielectric constant of the bulk component.

  15. Construction of a fuzzy and all Boolean logic gates based on DNA

    DEFF Research Database (Denmark)

    M. Zadegan, Reza; Jepsen, Mette D E; Hildebrandt, Lasse

    2015-01-01

    computing and biosensing. The ideal logic gate system should provide a wide selection of logical operations, and be integrable in multiple copies into more complex structures. Here we show the successful construction of a small DNA-based logic gate complex that produces fluorescent outputs corresponding......Logic gates are devices that can perform logical operations by transforming a set of inputs into a predictable single detectable output. The hybridization properties, structure, and function of nucleic acids can be used to make DNA-based logic gates. These devices are important modules in molecular...... to the operation of the six Boolean logic gates AND, NAND, OR, NOR, XOR, and XNOR. The logic gate complex is shown to work also when implemented in a three-dimensional DNA origami box structure, where it controlled the position of the lid in a closed or open position. Implementation of multiple microRNA sensitive...

  16. Dielectric Waveguide lasers

    NARCIS (Netherlands)

    Pollnau, Markus; Orlovic, V.A.; Pachenko, V.; Scherbakov, I.A.

    2007-01-01

    Our recent results on planar and channel waveguide fabrication and lasers in the dielectric oxide materials Ti:sapphire and rare-earth-ion-doped potassium yttrium double tungstate (KYW) are reviewed. We have employed waveguide fabrication methods such as liquid phase epitaxy and reactive ion etching

  17. Interfaces: nanometric dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Lewis, T J [School of Informatics, University of Wales Bangor, Dean Street, Bangor, Gwynedd, LL70 9PX (United Kingdom)

    2005-01-21

    The incorporation of nanometric size particles in a matrix to form dielectric composites shows promise of materials (nanodielectrics) with new and improved properties. It is argued that the properties of the interfaces between the particles and the matrix, which will themselves be of nanometric dimensions, will have an increasingly dominant role in determining dielectric performance as the particle size decreases. The forces that determine the electrical and dielectric properties of interfaces are considered, with emphasis on the way in which they might influence composite behaviour. A number of examples are given in which interfaces at the nanometric level exercise both passive and active control over dielectric, optical and conductive properties. Electromechanical properties are also considered, and it is shown that interfaces have important electrostrictive and piezoelectric characteristics. It is demonstrated that the process of poling, namely subjecting macroscopic composite materials to electrical stress and raised temperatures to create piezoelectric materials, can be explained in terms of optimizing the collective response of the nanometric interfaces involved. If the electrical and electromechanical features are coupled to the long-established electrochemical properties, interfaces represent highly versatile active elements with considerable potential in nanotechnology.

  18. Interfaces: nanometric dielectrics

    Science.gov (United States)

    Lewis, T. J.

    2005-01-01

    The incorporation of nanometric size particles in a matrix to form dielectric composites shows promise of materials (nanodielectrics) with new and improved properties. It is argued that the properties of the interfaces between the particles and the matrix, which will themselves be of nanometric dimensions, will have an increasingly dominant role in determining dielectric performance as the particle size decreases. The forces that determine the electrical and dielectric properties of interfaces are considered, with emphasis on the way in which they might influence composite behaviour. A number of examples are given in which interfaces at the nanometric level exercise both passive and active control over dielectric, optical and conductive properties. Electromechanical properties are also considered, and it is shown that interfaces have important electrostrictive and piezoelectric characteristics. It is demonstrated that the process of poling, namely subjecting macroscopic composite materials to electrical stress and raised temperatures to create piezoelectric materials, can be explained in terms of optimizing the collective response of the nanometric interfaces involved. If the electrical and electromechanical features are coupled to the long-established electrochemical properties, interfaces represent highly versatile active elements with considerable potential in nanotechnology.

  19. Dielectric elastomer memory

    Science.gov (United States)

    O'Brien, Benjamin M.; McKay, Thomas G.; Xie, Sheng Q.; Calius, Emilio P.; Anderson, Iain A.

    2011-04-01

    Life shows us that the distribution of intelligence throughout flexible muscular networks is a highly successful solution to a wide range of challenges, for example: human hearts, octopi, or even starfish. Recreating this success in engineered systems requires soft actuator technologies with embedded sensing and intelligence. Dielectric Elastomer Actuator(s) (DEA) are promising due to their large stresses and strains, as well as quiet flexible multimodal operation. Recently dielectric elastomer devices were presented with built in sensor, driver, and logic capability enabled by a new concept called the Dielectric Elastomer Switch(es) (DES). DES use electrode piezoresistivity to control the charge on DEA and enable the distribution of intelligence throughout a DEA device. In this paper we advance the capabilities of DES further to form volatile memory elements. A set reset flip-flop with inverted reset line was developed based on DES and DEA. With a 3200V supply the flip-flop behaved appropriately and demonstrated the creation of dielectric elastomer memory capable of changing state in response to 1 second long set and reset pulses. This memory opens up applications such as oscillator, de-bounce, timing, and sequential logic circuits; all of which could be distributed throughout biomimetic actuator arrays. Future work will include miniaturisation to improve response speed, implementation into more complex circuits, and investigation of longer lasting and more sensitive switching materials.

  20. Mixed-Species Logic Gates and High-Fidelity Universal Gate Set for Trapped-Ion Qubits

    Science.gov (United States)

    Tan, Ting Rei

    2016-05-01

    Precision control over hybrid physical systems at the quantum level is important for the realization of many quantum-based technologies. For trapped-ions, a hybrid system formed of different species introduces extra degrees of freedom that can be exploited to expand and refine the control of the system. We demonstrate an entangling gate between two atomic ions of different elements that can serve as an important building block of quantum information processing (QIP), quantum networking, precision spectroscopy, metrology, and quantum simulation. An entangling geometric phase gate between a 9 Be+ ion and a 25 Mg+ ion is realized through an effective spin-spin interaction generated by state-dependent forces. A mixed-species Bell state is thereby created with a fidelity of 0 . 979(1) . We use the gate to construct a SWAP gate that interchanges the quantum states of the two dissimilar qubits. We also report a high-fidelity universal gate set for 9 Be+ ion qubits, achieved through a combination of improved laser beam quality and control, improved state preparation, and reduced electric potential noise on trap electrodes. Supported by Office of the Director of National Intelligence (ODNI) Intelligence Advanced Research Projects Activity (IARPA), ONR, and the NIST Quantum Information Program.

  1. High-performance SEGISFET pH Sensor using the structure of double-gate a-IGZO TFTs with engineered gate oxides

    Science.gov (United States)

    Pyo, Ju-Young; Cho, Won-Ju

    2017-03-01

    In this paper, we propose a high-performance separative extended gate ion-sensitive field-effect transistor (SEGISFET) that consists of a tin dioxide (SnO2) SEG sensing part and a double-gate structure amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with tantalum pentoxide/silicon dioxide (Ta2O5/SiO2)-engineered top-gate oxide. To increase sensitivity, we maximized the capacitive coupling ratio by applying high-k dielectric at the top-gate oxide layer. As an engineered top-gate oxide, a stack of 25 nm-thick Ta2O5 and 10 nm-thick SiO2 layers was found to simultaneously satisfy a small equivalent oxide thickness (˜17.14 nm), a low leakage current, and a stable interfacial property. The threshold-voltage instability, which is a fundamental issue in a-IGZO TFTs, was improved by low-temperature post-deposition annealing (˜87 °C) using microwave irradiation. The double-gate structure a-IGZO TFTs with engineered top-gate oxide exhibited high mobility, small subthreshold swing, high drive current, and larger on/off current ratio. The a-IGZO SEGISFETs with a dual-gate sensing mode showed a pH sensitivity of 649.04 mV pH-1, which is far beyond the Nernst limit. The non-ideal behavior of ISFETs, hysteresis, and drift effect also improved. These results show that the double-gate structure a-IGZO TFTs with engineered top-gate oxide can be a good candidate for cheap and disposable SEGISFET sensors.

  2. Improving pH sensitivity by field-induced charge regulation in flexible biopolymer electrolyte gated oxide transistors

    Science.gov (United States)

    Liu, Ning; Gan, Lu; Liu, Yu; Gui, Weijun; Li, Wei; Zhang, Xiaohang

    2017-10-01

    Electrical manipulation of charged ions in electrolyte-gated transistors is crucial for enhancing the electric-double-layer (EDL) gating effect, thereby improving their sensing abilities. Here, indium-zinc-oxide (IZO) based thin-film-transistors (TFTs) are fabricated on flexible plastic substrate. Acid doped chitosan-based biopolymer electrolyte is used as the gate dielectric, exhibiting an extremely high EDL capacitance. By regulating the dynamic EDL charging process with special gate potential profiles, the EDL gating effect of the chitosan-gated TFT is enhanced, and then resulting in higher pH sensitivities. An extremely high sensitivity of ∼57.8 mV/pH close to Nernst limit is achieved when the gate bias of the TFT sensor sweeps at a rate of 10 mV/s. Additionally, an enhanced sensitivity of 2630% in terms of current variation with pH range from 11 to 3 is realized when the device is operated in the ion depletion mode with a negative gate bias of -0.7 V. Robust ionic modulation is demonstrated in such chitosan-gated sensors. Efficiently driving the charged ions in the chitosan-gated IZO-TFT provides a new route for ultrasensitive, low voltage, and low-cost biochemical sensing technologies.

  3. Cascadable and reconfigurable photonic logic gates based on linear lightwave interference and non-linear phase erasure.

    Science.gov (United States)

    Larom, Bar; Nazarathy, Moshe; Rudnitsky, Arkady; Nevet, Amir; Zalevsky, Zeev

    2010-06-21

    Feasibility of cascading and reconfiguring a pair of linear-nonlinear all-optical logic gate structures is experimentally demonstrated using RF photonics. Progress in highly integrated O/E/O repeaters over Si/InP hybrid platforms enables large-scale reconfigurable gate arrays.

  4. Antenna with Dielectric Having Geometric Patterns

    Science.gov (United States)

    Dudley, Kenneth L. (Inventor); Elliott, Holly A. (Inventor); Cravey, Robin L. (Inventor); Connell, John W. (Inventor); Ghose, Sayata (Inventor); Watson, Kent A. (Inventor); Smith, Jr., Joseph G. (Inventor)

    2013-01-01

    An antenna includes a ground plane, a dielectric disposed on the ground plane, and an electrically-conductive radiator disposed on the dielectric. The dielectric includes at least one layer of a first dielectric material and a second dielectric material that collectively define a dielectric geometric pattern, which may comprise a fractal geometry. The radiator defines a radiator geometric pattern, and the dielectric geometric pattern is geometrically identical, or substantially geometrically identical, to the radiator geometric pattern.

  5. Noise Gating Solar Images

    Science.gov (United States)

    DeForest, Craig; Seaton, Daniel B.; Darnell, John A.

    2017-08-01

    I present and demonstrate a new, general purpose post-processing technique, "3D noise gating", that can reduce image noise by an order of magnitude or more without effective loss of spatial or temporal resolution in typical solar applications.Nearly all scientific images are, ultimately, limited by noise. Noise can be direct Poisson "shot noise" from photon counting effects, or introduced by other means such as detector read noise. Noise is typically represented as a random variable (perhaps with location- or image-dependent characteristics) that is sampled once per pixel or once per resolution element of an image sequence. Noise limits many aspects of image analysis, including photometry, spatiotemporal resolution, feature identification, morphology extraction, and background modeling and separation.Identifying and separating noise from image signal is difficult. The common practice of blurring in space and/or time works because most image "signal" is concentrated in the low Fourier components of an image, while noise is evenly distributed. Blurring in space and/or time attenuates the high spatial and temporal frequencies, reducing noise at the expense of also attenuating image detail. Noise-gating exploits the same property -- "coherence" -- that we use to identify features in images, to separate image features from noise.Processing image sequences through 3-D noise gating results in spectacular (more than 10x) improvements in signal-to-noise ratio, while not blurring bright, resolved features in either space or time. This improves most types of image analysis, including feature identification, time sequence extraction, absolute and relative photometry (including differential emission measure analysis), feature tracking, computer vision, correlation tracking, background modeling, cross-scale analysis, visual display/presentation, and image compression.I will introduce noise gating, describe the method, and show examples from several instruments (including SDO

  6. A quantum Fredkin gate.

    Science.gov (United States)

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  7. The effect of gate control on the electrical conductivity of InAs nanowires

    Energy Technology Data Exchange (ETDEWEB)

    Weis, Karl; Volk, Christian; Wirths, Stephan; Estevez Hernandez, Sergio; Akabori, Masashi; Sladek, Kamil; Penz, Andreas; Trellenkamp, Stefan; Schubert, Juergen; Schaepers, Thomas; Hardtdegen, Hilde; Gruetzmacher, Detlev [Institut fuer Bio- und Nanosysteme (IBN-1), Forschungszentrum Juelich (Germany); JARA, Fundamentals of Future Information Technology (Germany)

    2010-07-01

    Semiconductor nanowires are an interesting step on the road to zero-dimensional systems. InAs is an especially suitable material because ohmic contacts can be prepared straightforwardly. Provided sufficient gate control, quantum dots can be formed. Here, the electronic transport properties of nominally undoped InAs nanowires grown by metal-organic vapour phase epitaxy are examined. Their typical length and diameter are 5 {mu}m and 100 nm, respectively. The gate control is studied for different gate geometries, e. g. fingers, back- and top-gates. Furthermore, we compare the performance of high-k dielectrics, e. g. GdScO{sub 3} or LaLuO{sub 3}, with standard dielectrics like SiO{sub 2} or Si{sub 3}N{sub 4}. Four-terminal transport measurements are performed both at room temperature as well as at low temperatures down to 30 mK. Field effect transistor measurements performed at room temperature show that by using high-k dielectrics, the I{sub on}/I{sub off} ratio can be improved by at least one order of magnitude.

  8. Carrier localization on surfaces of organic semiconductors gated with electrolytes.

    Science.gov (United States)

    Xia, Yu; Xie, Wei; Ruden, P Paul; Frisbie, C Daniel

    2010-07-16

    Organic semiconductor single crystals gated with electrolytes exhibit a pronounced maximum in channel conductance at hole densities >10(13)   cm(-2). The cause is a strong decrease in the hole mobility with increasing charge density, which is explained in terms of a percolation model that incorporates trapping of holes by ions at the semiconductor-electrolyte interface. In the case of rubrene crystals, the peak channel conductance occurs at hole densities near 3 × 10(13)  cm(-2). The magnitude of the effect will be large for semiconductors with low dielectric constants and narrow bandwidths, and thus is likely to be a general phenomenon in organic semiconductors gated with electrolytes.

  9. Threshold-Voltage Shifts in Organic Transistors Due to Self-Assembled Monolayers at the Dielectric: Evidence for Electronic Coupling and Dipolar Effects.

    Science.gov (United States)

    Aghamohammadi, Mahdieh; Rödel, Reinhold; Zschieschang, Ute; Ocal, Carmen; Boschker, Hans; Weitz, R Thomas; Barrena, Esther; Klauk, Hagen

    2015-10-21

    The mechanisms behind the threshold-voltage shift in organic transistors due to functionalizing of the gate dielectric with self-assembled monolayers (SAMs) are still under debate. We address the mechanisms by which SAMs determine the threshold voltage, by analyzing whether the threshold voltage depends on the gate-dielectric capacitance. We have investigated transistors based on five oxide thicknesses and two SAMs with rather diverse chemical properties, using the benchmark organic semiconductor dinaphtho[2,3-b:2',3'-f]thieno[3,2-b]thiophene. Unlike several previous studies, we have found that the dependence of the threshold voltage on the gate-dielectric capacitance is completely different for the two SAMs. In transistors with an alkyl SAM, the threshold voltage does not depend on the gate-dielectric capacitance and is determined mainly by the dipolar character of the SAM, whereas in transistors with a fluoroalkyl SAM the threshold voltages exhibit a linear dependence on the inverse of the gate-dielectric capacitance. Kelvin probe force microscopy measurements indicate this behavior is attributed to an electronic coupling between the fluoroalkyl SAM and the organic semiconductor.

  10. Dielectric Properties of Polyimide Hybrid Film Doped with Nano Zirconium/Aluminum Oxide%纳米锆/铝氧化物杂化聚酰亚胺薄膜的介电性能

    Institute of Scientific and Technical Information of China (English)

    袁征; 范勇; 陈昊; 韩笑笑

    2011-01-01

    采用热液法制备了一系列不同Zr和Al比例的纳米粒子分散液,用原位聚合法分别制备了无机纳米杂化聚酰亚胺薄膜,并进行了SEM分析、电气强度和耐电晕测试.结果表明:Zr和A1的掺杂比例对杂化薄膜的耐电晕寿命及击穿场强影响较大,其耐电晕寿命最大可达Kapton100CR薄膜的4倍.%A series of nano-dispersions with different ratio of Zr and Al was prepared by hydrothermal method, and the corresponding inorganic nano-hybrid polyimide films were prepared through in-situ polymerization method. The hybrid film was characterized by SEM, electric strength and corona-resistant test. The results show that the doping ratio of Al and Zr has great effects on the corona-resistant life and breakdown strength of the hybrid film, and the maximum corona-resistant life is 4 times of that of Kapton 100 CR film.

  11. Dynamic dielectric recovery characteristics of hybrid circuit breaker based on vacuum interrupter and SF6 interrupter in series%基于真空灭弧室与SF6灭弧室串联的混合断路器动态介质恢复特性

    Institute of Scientific and Technical Information of China (English)

    程显; 廖敏夫; 段雄英; 邹积岩

    2012-01-01

    论述了基于真空灭弧室和SF6灭弧室串联的混合断路器开断能力提高的原理,分析了混合断路器两灭弧室的介质恢复过程.结合混合断路器开断能力提高的机理提出了混合断路器对其操动控制机构的要求,设计了一种基于真空灭弧室与SF6灭弧室串联的光控模块式混合断路器实验模型.实验模型能满足分析混合断路器中真空灭弧室与SF6灭弧室在不同时刻协同动作开断容量增益特性的要求,其协同动作时间分散性在微秒级.实验对比了SF6断路器与基于相同SF6灭弧室串联真空灭弧室的混合断路器短路电流开断能力,证明在不增加SF6气体使用量的前提下,混合断路器具有比SF6断路器更加优越的开断能力.%The principle of breaking capacity improvement of hybrid circuit breaker with serial vacuum interrupter and SF6 interrupter is discussed and the dielectric recovery process of two interrupters is analyzed. Based on the improvement of breaking capacity,the requirements of hybrid circuit breaker for its control mechanism are proposed. The experimental model of hybrid circuit breaker based on optical control modules is designed,which meets the research requirement for the breaking capacity gain characteristic of coordinating operation at different moments between vacuum interrupter and SF6 interrupter, and the time dispersion is microsecond level. Experimental results show that,if the usage of SF6 gas is same,the breaking capacity of hybrid circuit breaker is higher than that of SF6 circuit breaker.

  12. Broadband local dielectric spectroscopy

    Science.gov (United States)

    Labardi, M.; Lucchesi, M.; Prevosto, D.; Capaccioli, S.

    2016-05-01

    A route to extend the measurement bandwidth of local dielectric spectroscopy up to the MHz range has been devised. The method is based on a slow amplitude modulation at a frequency Ω of the excitation field oscillating at a frequency ω and the coherent detection of the modulated average electric force or force gradient at Ω. The cantilever mechanical response does not affect the measurement if Ω is well below its resonant frequency; therefore, limitations on the excitation field frequency are strongly reduced. Demonstration on a thin poly(vinyl acetate) film is provided, showing its structural relaxation spectrum on the local scale up to 45 °C higher than glass temperature, and nanoscale resolution dielectric relaxation imaging near conductive nanowires embedded in the polymer matrix was obtained up to 5 MHz frequency, with no physical reason to hinder further bandwidth extension.

  13. All-dielectric metamaterials.

    Science.gov (United States)

    Jahani, Saman; Jacob, Zubin

    2016-01-01

    The ideal material for nanophotonic applications will have a large refractive index at optical frequencies, respond to both the electric and magnetic fields of light, support large optical chirality and anisotropy, confine and guide light at the nanoscale, and be able to modify the phase and amplitude of incoming radiation in a fraction of a wavelength. Artificial electromagnetic media, or metamaterials, based on metallic or polar dielectric nanostructures can provide many of these properties by coupling light to free electrons (plasmons) or phonons (phonon polaritons), respectively, but at the inevitable cost of significant energy dissipation and reduced device efficiency. Recently, however, there has been a shift in the approach to nanophotonics. Low-loss electromagnetic responses covering all four quadrants of possible permittivities and permeabilities have been achieved using completely transparent and high-refractive-index dielectric building blocks. Moreover, an emerging class of all-dielectric metamaterials consisting of anisotropic crystals has been shown to support large refractive index contrast between orthogonal polarizations of light. These advances have revived the exciting prospect of integrating exotic electromagnetic effects in practical photonic devices, to achieve, for example, ultrathin and efficient optical elements, and realize the long-standing goal of subdiffraction confinement and guiding of light without metals. In this Review, we present a broad outline of the whole range of electromagnetic effects observed using all-dielectric metamaterials: high-refractive-index nanoresonators, metasurfaces, zero-index metamaterials and anisotropic metamaterials. Finally, we discuss current challenges and future goals for the field at the intersection with quantum, thermal and silicon photonics, as well as biomimetic metasurfaces.

  14. Dielectric Metamaterial Reflector

    Science.gov (United States)

    2017-02-14

    induced plasma coupled to a fluidized bed reactor have been utilized at SRI for 20+ years. As such, it would seem that Si particles may be easier to... etching process limits this process to cm2 areas. There have been several studies and demonstrations of the optical properties of dilute as well...magnetic optical response in a dielectric nanoparticle by ultrafast photoexcitation of dense electron–hole plasma . Nano letters, 15(9), pp.6187-6192. 34

  15. All-dielectric metamaterials

    Science.gov (United States)

    Jahani, Saman; Jacob, Zubin

    2016-01-01

    The ideal material for nanophotonic applications will have a large refractive index at optical frequencies, respond to both the electric and magnetic fields of light, support large optical chirality and anisotropy, confine and guide light at the nanoscale, and be able to modify the phase and amplitude of incoming radiation in a fraction of a wavelength. Artificial electromagnetic media, or metamaterials, based on metallic or polar dielectric nanostructures can provide many of these properties by coupling light to free electrons (plasmons) or phonons (phonon polaritons), respectively, but at the inevitable cost of significant energy dissipation and reduced device efficiency. Recently, however, there has been a shift in the approach to nanophotonics. Low-loss electromagnetic responses covering all four quadrants of possible permittivities and permeabilities have been achieved using completely transparent and high-refractive-index dielectric building blocks. Moreover, an emerging class of all-dielectric metamaterials consisting of anisotropic crystals has been shown to support large refractive index contrast between orthogonal polarizations of light. These advances have revived the exciting prospect of integrating exotic electromagnetic effects in practical photonic devices, to achieve, for example, ultrathin and efficient optical elements, and realize the long-standing goal of subdiffraction confinement and guiding of light without metals. In this Review, we present a broad outline of the whole range of electromagnetic effects observed using all-dielectric metamaterials: high-refractive-index nanoresonators, metasurfaces, zero-index metamaterials and anisotropic metamaterials. Finally, we discuss current challenges and future goals for the field at the intersection with quantum, thermal and silicon photonics, as well as biomimetic metasurfaces.

  16. Dielectric spectroscopy of polyaniline

    Energy Technology Data Exchange (ETDEWEB)

    Calleja, R.D.; Matveeva, E.M. [Polytechnical Univ. of Valencia, (Spain)

    1993-12-31

    Polyaniline films (PANI) are being considered as attractive new galvanic sources, electrochromic displays, chemical sensors, etc. So far much work has been done to study their optical, electrochemical and electrical properties. However, there are still doubts about the basic electric conductivity mechanisms of PANI. The aim of this paper is to study the influence of water molecules and acid anions on the properties of PANI films by dielectric spectroscopy.

  17. Hybrid nanowire ion-to-electron transducers for integrated bioelectronic circuitry (Conference Presentation)

    Science.gov (United States)

    Carrad, Damon J.; Mostert, Bernard; Meredith, Paul; Micolich, Adam P.

    2016-09-01

    A key task in bioelectronics is the transduction between ionic/protonic signals and electronic signals at high fidelity. This is a considerable challenge since the two carrier types exhibit intrinsically different physics. We present our work on a new class of organic-inorganic transducing interface utilising semiconducting InAs and GaAs nanowires directly gated with a proton transporting hygroscopic polymer consisting of undoped polyethylene oxide (PEO) patterned to nanoscale dimensions by a newly developed electron-beam lithography process [1]. Remarkably, we find our undoped PEO polymer electrolyte gate dielectric [2] gives equivalent electrical performance to the more traditionally used LiClO4-doped PEO [3], with an ionic conductivity three orders of magnitude higher than previously reported for undoped PEO [4]. The observed behaviour is consistent with proton conduction in PEO. We attribute our undoped PEO-based devices' performance to the small external surface and high surface-to-volume ratio of both the nanowire conducting channel and patterned PEO dielectric in our devices, as well as the enhanced hydration afforded by device processing and atmospheric conditions. In addition to studying the basic transducing mechanisms, we also demonstrate high-fidelity ionic to electronic conversion of a.c. signals at frequencies up to 50 Hz. Moreover, by combining complementary n- and p-type transducers we demonstrate functional hybrid ionic-electronic circuits can achieve logic (NOT operation), and with some further engineering of the nanowire contacts, potentially also amplification. Our device structures have significant potential to be scaled towards realising integrated bioelectronic circuitry. [1] D.J. Carrad et al., Nano Letters 14, 94 (2014). [2] D.J. Carrad et al., Manuscript in preparation (2016). [3] S.H. Kim et al., Advanced Materials 25, 1822 (2013). [4] S.K. Fullerton-Shirey et al., Macromolecules 42, 2142 (2009).

  18. Electrical characterization of chemical and dielectric passivation of InAs nanowires

    Science.gov (United States)

    Holloway, Gregory W.; Haapamaki, Chris M.; Kuyanov, Paul; LaPierre, Ray R.; Baugh, Jonathan

    2016-11-01

    The native oxide at the surface of III-V nanowires, such as InAs, can be a major source of charge noise and scattering in nanowire-based electronics, particularly for quantum devices operated at low temperatures. Surface passivation provides a means to remove the native oxide and prevent its regrowth. Here, we study the effects of surface passivation and conformal dielectric deposition by measuring electrical conductance through nanowire field effect transistors treated with a variety of surface preparations. By extracting field effect mobility, subthreshold swing, threshold shift with temperature, and the gate hysteresis for each device, we infer the relative effects of the different treatments on the factors influencing transport. It is found that a combination of chemical passivation followed by deposition of an aluminum oxide dielectric shell yields the best results compared to the other treatments, and comparable to untreated nanowires. Finally, it is shown that an entrenched, top-gated device using an optimally treated nanowire can successfully form a stable double quantum dot at low temperatures. The device has excellent electrostatic tunability owing to the conformal dielectric layer and the combination of local top gates and a global back gate.

  19. Processing and performance of organic insulators as a gate layer in organic thin film transistors fabricated on polyethylene terephthalate substrate

    Indian Academy of Sciences (India)

    Saumen Mandal; Monica Katiyar

    2013-08-01

    Fabrication of organic thin film transistor (OTFT) on flexible substrates is a challenge, because of its low softening temperature, high roughness and flexible nature. Although several organic dielectrics have been used as gate insulator, it is difficult to choose one in absence of a comparative study covering processing of dielectric layer on polyethylene terephthalate (PET), characterization of dielectric property, pentacene film morphology and OTFT characterization. Here, we present the processing and performance of three organic dielectrics, poly(4-vinylphenol) (PVPh), polyvinyl alcohol (PVA) and poly(methylmethacrylate) (PMMA), as a gate layer in pentacene-based organic thin film transistor on PET substrate. We have used thermogravimetric analysis of organic dielectric solution to determine annealing temperature for spin-coated films of these dielectrics. Comparison of the leakage currents for the three dielectrics shows PVA exhibiting lowest leakage (in the voltage range of −30 to +30 V). This is partly because solvent is completely eliminated in the case of PVA as observed by differential thermogravimetric analysis (DTGA). We propose that DTGA can be a useful tool to optimize processing of dielectric layers. From organic thin film transistor point of view, crystal structure, morphology and surface roughness of pentacene film on all the dielectric layers were studied using X-ray diffraction (XRD), atomic force microscopy (AFM) and scanning electron microscopy (SEM).We observe pyramidal pentacene on PVPh whereas commonly observed dendritic pentacene on PMMA and PVA surface. Pentacene morphology development is discussed in terms of surface roughness, surface energy and molecular nature of the dielectric layer.

  20. Tunable dielectric properties of ferrite-dielectric based metamaterial.

    Science.gov (United States)

    Bi, K; Huang, K; Zeng, L Y; Zhou, M H; Wang, Q M; Wang, Y G; Lei, M

    2015-01-01

    A ferrite-dielectric metamaterial composed of dielectric and ferrite cuboids has been investigated by experiments and simulations. By interacting with the electromagnetic wave, the Mie resonance can take place in the dielectric cuboids and the ferromagnetic precession will appear in the ferrite cuboids. The magnetic field distributions show the electric Mie resonance of the dielectric cuboids can be influenced by the ferromagnetic precession of ferrite cuboids when a certain magnetic field is applied. The effective permittivity of the metamaterial can be tuned by modifying the applied magnetic field. A good agreement between experimental and simulated results is demonstrated, which confirms that these metamaterials can be used for tunable microwave devices.