The H1 SPACAL time-to-digital converter system

International Nuclear Information System (INIS)

Eisenhandler, E.; Landon, M.; Thompson, G.

1995-01-01

This paper describes a pipelined 1,400-channel Time-to-Digital Converter (TDC) system for the H1 Scintillating Fiber Calorimeter, which will soon be installed in the H1 experiment at DESY. The main task of the TDC system is to determine the time of arrival of energy depositions, and send this information from bunch crossings that satisfy the event trigger into the H1 data acquisition system. In addition, the TDC system must monitor the timing trigger, which vetoes bunch crossings that contain too much background energy. Products of the interaction are separated from background on the basis of their different times of arrival with respect to the bunch crossing clock. For this monitoring the TDC system uses automatic on-board histogramming hardware that produces a family of histograms for each of 1,400 channels. The TDC function is performed by the TMC1004 ASIC. The system digitizes over a range of 32ns per bunch crossing with 1ns bins and a precision of 1ns. Because of the way the TMC1004 is designed, it is possible to vary the size of the bins between 0.6ns and 3ns by trading off measurement range for bin size. The system occupies two 9U VME crates

Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

International Nuclear Information System (INIS)

Sano, K.; Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N.; Zen, N.; Ohkubo, M.

2014-01-01

Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach

Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

Energy Technology Data Exchange (ETDEWEB)

Sano, K., E-mail: sano-kyosuke-cw@ynu.jp [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N. [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Zen, N.; Ohkubo, M. [Research Institute of Instrumentation Frontier, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba 305-8568 (Japan)

2014-09-15

Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach.

Combined analog-to-digital converter

International Nuclear Information System (INIS)

Zhukov, A.V.; Rzhendinskaya, S.N.

1983-01-01

A 10-bit analog-to-digital converter (ADC) designed for operating in spectrometers with time-dependent filters is described. The ADC operation is based on combining the parallel reading and sequential counting methods. At maximum conversion time of 12 μs, timing series frequency of 25 MHz and foUr reference levels the differential nonlinearity withoUt statistical smoothing (maximum relative channel width deviation from average value) is not more than 4%

Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers.

Science.gov (United States)

Bengtsson, Lars E

2012-04-01

This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation. © 2012 American Institute of Physics

A high speed digital-to-analogue converter

International Nuclear Information System (INIS)

Hallgren, B.I.

1974-02-01

An 8-bit Digital-to-Analogue converter of the current-weighting type has been constructed using 8 monolithic integrated circuit transistor arrays -one for each bit. The D/A-converter has a voltage output within the range 0 to -2V. The settling time to within half of the least significant bit is about 50 nsec. The temperature dependence and transient response of the converter has been analysed using computer aided design techniques. A comparison is made between the experimental and simulated transient performance. (Auth.)

Radiation-tolerant delta-sigma time-to-digital converters

CERN Document Server

Cao, Ying; Steyaert, Michiel

2015-01-01

This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.   · �...

Graphical Evaluation of Time-Delay Compensation Techniques for Digitally Controlled Converters

DEFF Research Database (Denmark)

Lu, Minghui; Wang, Xiongfei; Loh, Poh Chiang

2018-01-01

A main design constraint of the digitally controlled power electronics converters is the time delay of control systems, which may lead to the reduced control loop bandwidth and even unstable dynamics. Numerous time-delay compensation methods have been developed, of which the model-free schemes...

A method to increase optical timing spectra measurement rates using a multi-hit TDC

International Nuclear Information System (INIS)

Moses, W.W.

1993-01-01

A method is presented for using a modern time to digital converter (TDC) to increase the data collection rate for optical timing measurements such as scintillator decay times. It extends the conventional delayed coincidence method, where a synchronization signal ''starts'' a TDC and a photomultiplier tube (PMT) sampling the optical signal ''stops'' the TDC. Data acquisition rates are low with the conventional method because ε, the light collection efficiency of the ''stop'' PMT, is artificially limited to ε∼0.01 photons per ''start'' signal to reduce the probability of detecting more than one photon during the sampling period. With conventional TDCs, these multiple photon events bias the time spectrum since only the first ''stop'' pulse is digitized. The new method uses a modern TDC to detect whether additional ''stop'' signals occur during the sampling period, and actively reject these multiple photon events. This allows ε to be increased to almost 1 photon per ''start'' signal, which maximizes the data acquisition rate at a value nearly 20 times higher. Multi-hit TDCs can digitize the arrival times of n ''stop'' signals per ''start'' signal, which allows ε to be increased to ∼3n/4. While overlap of the ''stop'' signals prevents the full gain in data collection rate to be realized, significant improvements are possible for most applications. (orig.)

A PCI time digitizer for the new JET time-of-flight neutron spectrometer

International Nuclear Information System (INIS)

Sousa, J.; Batista, A.J.N.; Combo, A.; Pereira, R.; Cruz, N.; Carvalho, P.; Varandas, C.A.F.; Conroy, S.; Ericsson, G.; Kaellne, J.

2004-01-01

A PCI time digitizer module with eight independent time-to-digital converter (TDC) channels is being developed for the new time-of-flight spectrometer designed for optimized rate (TOFOR) which diagnoses deuterium plasmas of the EFDA-JET tokamak. The module shall measure with high accuracy the flight-times of 2.5 MeV neutrons in the 100 ns range as given by two groups of scintillation detectors operating at average event rates from the expected 500 kHz up to 5 MHz. The module stores up to 64 million hit-times with a resolution of 0.4 ns and incorporates a digital signal processor and a system-on-chip device which performs the data transfer, the device control/monitoring and may perform statistical, data reduction or control algorithms in real-time

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

Energy Technology Data Exchange (ETDEWEB)

Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

2015-01-21

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

A new delay line loops shrinking time-to-digital converter in low-cost FPGA

International Nuclear Information System (INIS)

Zhang, Jie; Zhou, Dongming

2015-01-01

The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

International Nuclear Information System (INIS)

Perktold, L; Christiansen, J

2014-01-01

The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

High-speed and high-resolution analog-to-digital and digital-to-analog converters

NARCIS (Netherlands)

van de Plassche, R.J.

1989-01-01

Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog

Time-to-code converter with selection of time intervals on duration

International Nuclear Information System (INIS)

Atanasov, I.Kh.; Rusanov, I.R.; )

2001-01-01

Identification of elementary particles on the basis of time-of-flight represents the important approach of the preliminary selection procedure. Paper describes a time-to-code converter with preliminary selection of the measured time intervals as to duration. It consists of a time-to-amplitude converter, an analog-to-digital converter, a unit of selection of time intervals as to duration, a unit of total reset and CAMAC command decoder. The time-to-code converter enables to measure time intervals with 100 ns accuracy within 0-100 ns range. Output code capacity is of 10. Selection time constitutes 50 ns [ru

A 41 ps ASIC time-to-digital converter for physics experiments

International Nuclear Information System (INIS)

Russo, Stefano; Petra, Nicola; De Caro, Davide; Barbarino, Giancarlo; Strollo, Antonio G.M.

2011-01-01

We present a novel Time-to-Digital (TDC) converter for physics experiments. Proposed TDC is based on a synchronous counter and an asynchronous fine interpolator. The fine part of the measurement is obtained using NORA inverters that provide improved resolution. A prototype IC was fabricated in 180 nm CMOS technology. Experimental measurements show that proposed TDC features 41 ps resolution associated with 0.35LSB differential non-linearity, 0.77LSB integral non-linearity and a negligible single shot precision. The whole dynamic range is equal to 18μs. The proposed TDC is designed using a flash architecture that reduces dead time. Data reported in the paper show that our design is well suited for present and future particle physics experiments.

Development of a fast time-to-digital converter (TDC) using a programmable gate array

International Nuclear Information System (INIS)

Mine, Shun-ichi; Tokushuku, Katsuo; Yamada, Sakue.

1994-09-01

A fast time-to-digital converter with a 5 ns step was designed and tested by utilizing a user-programmable gate array. The stabilities against temperature and supply voltage variation were measured. A module was built with this TDC, and was successfully used in the first-level trigger system of the ZEUS detector to reject proton-beam induced background events. (author)

High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

Directory of Open Access Journals (Sweden)

Hai Wang

2017-01-01

Full Text Available This paper presents the design and implementation of a new digital-to-time converter (DTC. The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL and integral nonlinearity (INL are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA chip.

A Capacitance-To-Digital Converter for MEMS Sensors for Smart Applications.

Science.gov (United States)

Pérez Sanjurjo, Javier; Prefasi, Enrique; Buffa, Cesare; Gaggl, Richard

2017-06-07

The use of MEMS sensors has been increasing in recent years. To cover all the applications, many different readout circuits are needed. To reduce the cost and time to market, a generic capacitance-to-digital converter (CDC) seems to be the logical next step. This work presents a configurable CDC designed for capacitive MEMS sensors. The sensor is built with a bridge of MEMS, where some of them function with pressure. Then, the capacitive to digital conversion is realized using two steps. First, a switched-capacitor (SC) preamplifier is used to make the capacitive to voltage (C-V) conversion. Second, a self-oscillated noise-shaping integrating dual-slope (DS) converter is used to digitize this magnitude. The proposed converter uses time instead of amplitude resolution to generate a multibit digital output stream. In addition it performs noise shaping of the quantization error to reduce measurement time. This article shows the effectiveness of this method by measurements performed on a prototype, designed and fabricated using standard 0.13 µm CMOS technology. Experimental measurements show that the CDC achieves a resolution of 17 bits, with an effective area of 0.317 mm², which means a pressure resolution of 1 Pa, while consuming 146 µA from a 1.5 V power supply.

Diamond-Shaped Semiconductor Ring Lasers for Analog to Digital Photonic Converters

National Research Council Canada - National Science Library

Green, Malcolm

2004-01-01

Photonic/ optoelectronic analog to digital converters (ADCs) have advantages in areas such as precise sampling times, narrow sampling apertures, and the ability to sample without contaminating the incident signal...

Monolitic integrated circuit for the strobed charge-to-time converter

International Nuclear Information System (INIS)

Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

1985-01-01

The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

A Calibration Method for Nonlinear Mismatches in M-Channel Time-Interleaved Analog-to-Digital Converters Based on Hadamard Sequences

Directory of Open Access Journals (Sweden)

Husheng Liu

2016-11-01

Full Text Available The time-interleaved analog-to-digital converter (TIADC is an architecture used to achieve a high sampling rate and high dynamic performance. However, estimation and compensation methods are required to maintain the dynamic performance of the constituent analog-to-digital converters (ADCs due to channel mismatches. This paper proposes a blind adaptive method to calibrate the nonlinear mismatches in M-channel TIADCs (M-TIADCs. The nonlinearity-induced error signal is reconstructed by the proposed multiplier Hadamard transform (MHT structure, and the nonlinear parameters are estimated by the filtered-X least-mean square (FxLMS algorithm. The performance of cascade calibration is also analyzed. The numerical simulation results show that the proposed method consumes much less hardware resources while maintaining the calibration performance.

Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA

Science.gov (United States)

Sano, Y.; Horii, Y.; Ikeno, M.; Sasaki, O.; Tomoto, M.; Uchida, T.

2017-12-01

Time-to-digital converters (TDCs) are used in various fields, including high-energy physics. One advantage of implementing TDCs in field-programmable gate arrays (FPGAs) is the flexibility on the modification of the logics, which is useful to cope with the changes in the experimental conditions. Recent FPGAs make it possible to implement TDCs with a time resolution less than 10 ps. On the other hand, various drift chambers require a time resolution of O(0.1) ns, and a simple and easy-to-implement TDC is useful for a robust operation. Herein an eight-channel TDC with a variable bin size down to 0.28 ns is implemented in a Xilinx Kintex-7 FPGA and tested. The TDC is based on a multisampling scheme with quad phase clocks synchronised with an external reference clock. Calibration of the bin size is unnecessary if a stable reference clock is available, which is common in high-energy physics experiments. Depending on the channel, the standard deviation of the differential nonlinearity for a 0.28 ns bin size is 0.13-0.31. The performance has a negligible dependence on the temperature. The power consumption and the potential to extend the number of channels are also discussed.

A high-resolution, multi-stop, time-to-digital converter for nuclear time-of-flight measurements

International Nuclear Information System (INIS)

Spencer, D.F.; Cole, J.; Drigert, M.; Aryaeinejad, R.

2006-01-01

A high-resolution, multi-stop, time-to-digital converter (TDC) was designed and developed to precisely measure the times-of-flight (TOF) of incident neutrons responsible for induced fission and capture reactions on actinide targets. The minimum time resolution is ±1 ns. The TDC design was implemented into a single, dual-wide CAMAC module. The CAMAC bus is used for command and control as well as an alternative data output. A high-speed ECL interface, compatible with LeCroy FERA modules, was also provided for the principle data output path. An Actel high-speed field programmable gate array (FPGA) chip was incorporated with an external oscillator and an internal multiple clock phasing system. This device implemented the majority of the high-speed register functions, the state machine for the FERA interface, and the high-speed counting circuit used for the TDC conversion. An external microcontroller was used to monitor and control system-level changes. In this work we discuss the performance of this TDC module as well as its application

Quantum walks with infinite hitting times

International Nuclear Information System (INIS)

Krovi, Hari; Brun, Todd A.

2006-01-01

Hitting times are the average time it takes a walk to reach a given final vertex from a given starting vertex. The hitting time for a classical random walk on a connected graph will always be finite. We show that, by contrast, quantum walks can have infinite hitting times for some initial states. We seek criteria to determine if a given walk on a graph will have infinite hitting times, and find a sufficient condition, which for discrete time quantum walks is that the degeneracy of the evolution operator be greater than the degree of the graph. The set of initial states which give an infinite hitting time form a subspace. The phenomenon of infinite hitting times is in general a consequence of the symmetry of the graph and its automorphism group. Using the irreducible representations of the automorphism group, we derive conditions such that quantum walks defined on this graph must have infinite hitting times for some initial states. In the case of the discrete walk, if this condition is satisfied the walk will have infinite hitting times for any choice of a coin operator, and we give a class of graphs with infinite hitting times for any choice of coin. Hitting times are not very well defined for continuous time quantum walks, but we show that the idea of infinite hitting-time walks naturally extends to the continuous time case as well

Reference-Free CMOS Pipeline Analog-to-Digital Converters

CERN Document Server

Figueiredo, Michael; Evans, Guiomar

2013-01-01

This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

Energy savings assessment for digital-to-analog converter boxes

International Nuclear Information System (INIS)

Cheung, Hoi Ying; Meier, Alan; Brown, Richard

2011-01-01

The Digital Television (DTV) Converter Box Coupon Program was administered by the U.S. government to subsidize purchases of digital-to-analog converter boxes, with up to two $40 coupons for each eligible household. In order to qualify as Coupon Eligible Converter Boxes (CECBs), these devices had to meet a number of minimum performance specifications, including energy efficiency standards. The Energy Star Program also established voluntary energy efficiency specifications that are more stringent than the CECB requirements. In this study, we measured the power and energy consumptions for a sample of 12 CECBs (including 6 Energy Star labeled models) in-use in homes and estimated aggregate energy savings produced by the energy efficiency policies. Based on the 35 million coupons redeemed through the end of the program, our analysis indicates that between 2500 and 3700 GWh per year are saved as a result of the energy efficiency policies implemented on digital-to-analog converter boxes. The energy savings generated are equivalent to the annual electricity use of 280,000 average US homes. - Research highlights: → We examined energy efficiency policies on digital-to-analog converter boxes in US. → The government assistance program resulted in high participation. → 35 million coupons were redeemed for the purchases of energy efficient DTAs. → Between 2500 and 3700 GWh per year are saved as a result of the policies. → Savings are equivalent to the annual electricity use of 280,000 average US homes.

A 13-Bits wilkinson analog-digital converter for NIM acquisition system

International Nuclear Information System (INIS)

Acosta Toledo, R.; Osorio Deliz, J.; Arista Romeu, E.; Fernandez, J.

1994-01-01

A new 13-bits Wilkinson analog-digital converter is described. The aim of this work is to describe the circuits of sample and hold, memory condensator loading and releasing PROM based control memory logic, zero level detection and correction. The converter is designed for the digital measurement of the peak amplitudes of pulses with statistical or periodical time distribution. The analog-digital converter may be used in spectrometric systems, multi-channel analysers or any similar PC based system

Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

International Nuclear Information System (INIS)

Nishigai, T.; Ito, M.; Yoshikawa, N.; Fujimaki, A.; Terai, H.; Yorozu, S.

2005-01-01

We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm 2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

Inverter-based successive approximation capacitance-to-digital converter

KAUST Repository

Omran, Hesham

2017-03-23

An energy-efficient capacitance-to-digital converter (CDC) is provided that utilizes a capacitance-domain successive approximation (SAR) technique. Unlike SAR analog- to-digital converters (ADCs), analysis shows that for SAR CDCs, the comparator offset voltage will result in signal-dependent and parasitic-dependent conversion errors, which necessitates an op-amp-based implementation. The inverter-based SAR CDC contemplated herein provides robust, energy-efficient, and fast operation. The inverter- based SAR CDC may include a hybrid coarse-fine programmable capacitor array. The design of example embodiments is insensitive to analog references, and thus achieves very low temperature sensitivity without the need for calibration. Moreover, this design achieves improved energy efficiency.

High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

International Nuclear Information System (INIS)

Pan, Weibin; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

2014-01-01

The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km 2 areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper

High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

Energy Technology Data Exchange (ETDEWEB)

Pan, Weibin, E-mail: pwb.thu@gmail.com; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

2014-02-21

The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km{sup 2} areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Flasck, J.M.; Levi, M.E.

1996-01-01

Phase-locked loops have been employed in the past to obtain sub-nanosecond time resolution in high energy physics and nuclear science applications. An alternative solution based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Mueller C-element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multichannel, time-to-digital converter (TDC) targeted for one specific frequency. The two circuits, DLL and TDC, are implemented in CMOS 1.2 microm and 0.8 microm technologies, respectively. Test results show a timing jitter of less than 30 ps for the DLL circuit and less than 190 ps integral and differential nonlinearity for the TDC circuit

A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Saxena, Pooja; Chandratre, V.B.; Pithawa, C.K.

2014-01-01

A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

Large-scale digitizer system, analog converters

International Nuclear Information System (INIS)

Althaus, R.F.; Lee, K.L.; Kirsten, F.A.; Wagner, L.J.

1976-10-01

Analog to digital converter circuits that are based on the sharing of common resources, including those which are critical to the linearity and stability of the individual channels, are described. Simplicity of circuit composition is valued over other more costly approaches. These are intended to be applied in a large-scale processing and digitizing system for use with high-energy physics detectors such as drift-chambers or phototube-scintillator arrays. Signal distribution techniques are of paramount importance in maintaining adequate signal-to-noise ratio. Noise in both amplitude and time-jitter senses is held sufficiently low so that conversions with 10-bit charge resolution and 12-bit time resolution are achieved

High-Speed Universal Frequency-to-Digital Converter for Quasi-Digital Sensors and Transducers

Directory of Open Access Journals (Sweden)

Sergey Y. Yurish

2007-06-01

Full Text Available New fast, accurate universal integrated frequency-to-digital converter (UFDC-1M-16 is described in the article. It is based on the novel patented modified method of the dependent count and has non-redundant conversion time from 6.25 ms to 6.25 ms for 1 to 0.001 % relative errors respectively, comparable with conversion time for successive-approximation and S-D ADC. The IC can work with different sensors, transducers and encoders, which have frequency, period, duty-cycle, PWM, phase shift, pulse number, etc. output.

A CMOS delay locked loop and sub-nanosecond time-to-digital converter chip

International Nuclear Information System (INIS)

Santos, D.M.; Dow, S.F.; Levi, M.E.

1995-12-01

Many high energy physics and nuclear science applications require sub-nanosecond time resolution measurements over many thousands of detector channels. Phase-locked loops have been employed in the past to obtain accurate time references for these measurements. An alternative solution, based on a delay-locked loop (DLL) is described. This solution allows for a very high level of integration yet still offers resolution in the sub-nanosecond regime. Two variations on this solution are outlined. A novel phase detector, based on the Muller C element, is used to implement a charge pump where the injected charge approaches zero as the loop approaches lock on the leading edge of an input clock reference. This greatly reduces timing jitter. In the second variation the loop locks to both the leading and trailing clock edges. In this second implementation, software coded layout generators are used to automatically layout a highly integrated, multi-channel, time to digital converter (TDC). Complex clock generation can be, achieved by taking symmetric taps off the delay elements. The two circuits, DLL and TDC, were implemented in a CMOS 1.2μm and 0.8μm technology, respectively. Test results show a timing jitter of less than 35 ps for the DLL circuit and better solution for the TDC circuit

Designed cell consortia as fragrance-programmable analog-to-digital converters.

Science.gov (United States)

Müller, Marius; Ausländer, Simon; Spinnler, Andrea; Ausländer, David; Sikorski, Julian; Folcher, Marc; Fussenegger, Martin

2017-03-01

Synthetic biology advances the rational engineering of mammalian cells to achieve cell-based therapy goals. Synthetic gene networks have nearly reached the complexity of digital electronic circuits and enable single cells to perform programmable arithmetic calculations or to provide dynamic remote control of transgenes through electromagnetic waves. We designed a synthetic multilayered gaseous-fragrance-programmable analog-to-digital converter (ADC) allowing for remote control of digital gene expression with 2-bit AND-, OR- and NOR-gate logic in synchronized cell consortia. The ADC consists of multiple sampling-and-quantization modules sensing analog gaseous fragrance inputs; a gas-to-liquid transducer converting fragrance intensity into diffusible cell-to-cell signaling compounds; a digitization unit with a genetic amplifier circuit to improve the signal-to-noise ratio; and recombinase-based digital expression switches enabling 2-bit processing of logic gates. Synthetic ADCs that can remotely control cellular activities with digital precision may enable the development of novel biosensors and may provide bioelectronic interfaces synchronizing analog metabolic pathways with digital electronics.

Wide-range time-to-digital converters with a high resolution

International Nuclear Information System (INIS)

Aul'chenko, V.M.

1977-01-01

A combined time-number converter in which measurements of time intervals to within a period of clock frequency are made directly and those within a period are by a time-amplitude-code conversion is described. It allows time intervals up to 4 mcsec with a resolution of 100 psec to be measured. The differential nonlinearity of conversion is not greater than +-1.5%, and the integral error from measurements of time intervals is not greater than +-100 psec

Digitally Controlled Point of Load Converter with Very Fast Transient Response

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only......This paper presents a new Digital Self-Oscillating Modulator (DiSOM) that allows the duty cycle to be changed instantly. The DiSOM modulator is shown to have variable switching that is a function of the duty cycle. Compared to a more traditional digital PWM modulator based on a counter...... and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of the DiSOM modulator makes it possible to design a digitally controlled DC/DC converter with linear...

Mismatch-Shaping Serial Digital-to-Analog Converter

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper; Moon, Un-Ku; Temes, Gabor C.

1999-01-01

A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal...

Development of a time-to-digital converter ASIC for the upgrade of the ATLAS Monitored Drift Tube detector

Science.gov (United States)

Wang, Jinhong; Liang, Yu; Xiao, Xiong; An, Qi; Chapman, John W.; Dai, Tiesheng; Zhou, Bing; Zhu, Junjie; Zhao, Lei

2018-02-01

The upgrade of the ATLAS muon spectrometer for the high-luminosity LHC requires new trigger and readout electronics for various elements of the detector. We present the design of a time-to-digital converter (TDC) ASIC prototype for the ATLAS Monitored Drift Tube (MDT) detector. The chip was fabricated in a GlobalFoundries 130 nm CMOS technology. Studies indicate that its timing and power dissipation characteristics meet the design specifications, with a timing bin variation of ±40 ps for all 48 TDC slices and a power dissipation of about 6.5 mW per slice.

A time-to-amplitude converter with constant fraction timing discriminators for short time interval measurements

International Nuclear Information System (INIS)

Kostamovaara, J.; Myllylae, R.

1985-01-01

The construction and the performance of a time-to-amplitude converter equipped with constant fraction discriminators is described. The TAC consists of digital and analog parts which are constructed on two printed circuit boards, both of which are located in a single width NIM module. The dead time of the TAC for a start pulse which is not followed by a stop pulse within the time range of the device (proportional100 ns) is only proportional100 ns, which enables one to avoid counting rate saturation even with a high random input signal rate. The differential and integral nonlinearities of the TAC are better than +-1.5% and 0.05%, respectively. The resolution for input timing pulses of constant shape is 20 ps (fwhm), and less than 10 ps (fwhm) with a modification in the digital part. The walk error of the constant fraction timing discriminators is presented and various parameters affecting it are discussed. The effect of the various disturbances in linearity caused by the fast ECL logic and their minimization are also discussed. The time-to-amplitude converter has been used in positron lifetime studies and for laser range finding. (orig.)

An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Directory of Open Access Journals (Sweden)

Chao Chen

2014-01-01

Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

International Nuclear Information System (INIS)

Cao, Y.; Leroux, P.; De Cock, W.; Steyaert, M.

2011-01-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma (ΔΣ) TDC structure is proposed. The converter, implemented in 0.13 μm, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm 2 . Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g m biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

Design and assessment of a 6 ps-resolution time-to-digital converter with 5 MGy gamma-dose tolerance for nuclear instrumentation

Energy Technology Data Exchange (ETDEWEB)

Cao, Y. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Leroux, P. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium); ICT-RELIC Div., Katholieke Hogeschool Kempen, B-2440 Geel (Belgium); De Cock, W. [SCK.CEN, Belgian Nuclear Research Centre, B-2400 Mol (Belgium); Steyaert, M. [ESAT-MICAS Div., Katholieke Universiteit Leuven, B-3001 Heverlee (Belgium)

2011-07-01

Time-to-Digital Converters (TDCs) are key building blocks in time-based mixed-signal systems, used for the digitization of analog signals in time domain. A short survey on state-of-the-art TDCs is given. In order to realize a TDC with picosecond time resolution as well as multi MGy gamma-dose radiation tolerance, a novel multi-stage noise-shaping (MASH) delta-sigma ({Delta}{Sigma}) TDC structure is proposed. The converter, implemented in 0.13 {mu}m, achieves a time resolution of 5.6 ps and an ENOB of 11 bits, when the over sampling ratio (OSR) is 250. The TDC core consumes only 1.7 mW, and occupies an area of 0.11 mm{sup 2}. Owing to the usage of circuit level radiation hardened-by-design techniques, such as passive RC oscillators and constant-g{sub m} biasing, the TDC exhibits enhanced radiation tolerance. At a low dose rate of 1.2 kGy/h, the frequency of the counting clock in the TDC remains constant up to at least 160 kGy. Even after a total dose of 3.4 MGy at a high dose rate of 30 kGy/h, the TDC still achieves a time resolution of 10.5 ps with an OSR of 250. (authors)

Frequency to digital converter for IUAC Linac control system

International Nuclear Information System (INIS)

Jain, Mamta; Subramaiam, E.T.; Sahu, B.K.

2015-01-01

A frequency to digital converter CAMAC module has been designed and developed for LINAC control systems. This module is used to see the frequency difference of master clock and the resonator frequency digitally without using the oscilloscope. Later on this can be used for automatic tuning and locking of the cavities using piezoelectric actuator based tunner control. This module has eight independent channels to fulfill the need of all the eight cavities of the cryostat. A Schmitt trigger along with level converaccepts almost any form of pulse train, with 30 Vp-p. The time period is measured by counters clocked from a high resolution clock (10 MHz +/- 250 ps). The counter values are cross checked at both the input levels. Frequency is obtained from the computed time period by a special divisor core implemented inside the FPGA. The major task was the implementation of eight individual divisor cores and routing inside one Spartan 3s500E FPGA chip

Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA)

International Nuclear Information System (INIS)

Jinyuan Wu; Zonghan Shi; Irena Y Wang

2003-01-01

A Time-to-Digital Converter (TDC) implemented in general purpose field-programmable gate array (FPGA) for the Fermilab CKM experiment will be presented. The TDC uses a delay chain and register array structure to produce lower bits in addition to higher bits from a clock counter. Lacking the direct controls custom chips, the FPGA implementation of the delay chain and register array structure had to address two major problems: (1) the logic elements used for the delay chain and register array structure must be placed and routed by the FPGA compiler in a predictable manner, to assure uniformity of the TDC binning and short-term stability. (2) The delay variation due to temperature and power supply voltage must be compensated for to assure long-term stability. They used the chain structures in the existing FPGAs that the venders designed for general purpose such as carry algorithm or logic expansion to solve the first problem. To compensate for delay variations, they studied several digital compensation strategies that can be implemented in the same FPGA device. Some bench-top test results will also be presented in this document

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

International Nuclear Information System (INIS)

Tamborini, D.; Portaluppi, D.; Villa, F.; Tosi, A.; Tisa, S.

2014-01-01

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

Energy Technology Data Exchange (ETDEWEB)

Tamborini, D., E-mail: davide.tamborini@polimi.it; Portaluppi, D.; Villa, F.; Tosi, A. [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Tisa, S. [Micro Photon Devices, via Stradivari 4, 39100 Bolzano (Italy)

2014-11-15

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs.

Science.gov (United States)

Tamborini, D; Portaluppi, D; Villa, F; Tisa, S; Tosi, A

2014-11-01

We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

Prototype of time digitizing system for BESⅢ endcap TOF upgrade

International Nuclear Information System (INIS)

Cao Ping; Sun Weijia; Fan Huanhuan; Wang Siyu; Liu Shubin; An Qi; Ji Xiaolu

2014-01-01

The prototype of a time digitizing system for the BESⅢ endcap TOF (ETOF) upgrade is introduced in this paper. The ETOF readout electronics has a distributed architecture. Hit signals from the multi-gap resistive plate chamber (MRPC) are signaled as LVDS by front-end electronics (FEE) and are then sent to the back-end time digitizing system via long shield differential twisted pair cables. The ETOF digitizing system consists of two VME crates, each of which contains modules for time digitization, clock, trigger, fast control, etc. The time digitizing module (TDIG) of this prototype can support up to 72 electrical channels for hit information measurement. The fast control (FCTL) module can operate in barrel or endcap mode. The barrel FCTL fans out fast control signals from the trigger system to the endcap FCTLs, merges data from the endcaps and then transfers to the trigger system. Without modifying the barrel TOF (BTOF) structure, this time digitizing architecture benefits from improved ETOF performance without degrading the BTOF performance. Lab experiments show that the time resolution of this digitizing system can be lower than 20 ps, and the data throughput to the DAQ can be about 92 Mbps. Beam experiments show that the total time resolution can be lower than 45 ps. (authors)

Digital control of high-frequency switched-mode power converters

CERN Document Server

Corradini, Luca; Mattavelli, Paolo; Zane, Regan

This book is focused on the fundamental aspects of analysis, modeling and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner Comprehensive treatment of digital control theory for power converters Verilog and VHDL sample codes are provided Enables readers to successfully analyze, model, design, and implement voltage, current, or multi-loop digital feedback loops around switched-mode power converters Practical examples are used throughout the book to illustrate applications of the techniques developed Matlab examples are also

CMOS based capacitance to digital converter circuit for MEMS sensor

Science.gov (United States)

Rotake, D. R.; Darji, A. D.

2018-02-01

Most of the MEMS cantilever based system required costly instruments for characterization, processing and also has large experimental setups which led to non-portable device. So there is a need of low cost, highly sensitive, high speed and portable digital system. The proposed Capacitance to Digital Converter (CDC) interfacing circuit converts capacitance to digital domain which can be easily processed. Recent demand microcantilever deflection is part per trillion ranges which change the capacitance in 1-10 femto farad (fF) range. The entire CDC circuit is designed using CMOS 250nm technology. Design of CDC circuit consists of a D-latch and two oscillators, namely Sensor controlled oscillator (SCO) and digitally controlled oscillator (DCO). The D-latch is designed using transmission gate based MUX for power optimization. A CDC design of 7-stage, 9-stage and 11-stage tested for 1-18 fF and simulated using mentor graphics Eldo tool with parasitic. Since the proposed design does not use resistance component, the total power dissipation is reduced to 2.3621 mW for CDC designed using 9-stage SCO and DCO.

All-optical analog-to-digital converter based on Kerr effect in photonic crystal

Science.gov (United States)

Jafari, Dariush; Nurmohammadi, Tofiq; Asadi, Mohammad Javad; Abbasian, Karim

2018-05-01

In this paper, a novel all-optical analog-to-digital converter (AOADC) is proposed and simulated for proof of principle. This AOADC is designed to operate in the range of telecom wavelength (1550 nm). A cavity made of nonlinear Kerr material in photonic crystal (PhC), is designed to achieve an optical analog-to-digital conversion with 1 Tera sample per second (TS/s) and the total footprint of 42 μm2 . The simulation is done using finite-difference time domain (FDTD) method.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

International Nuclear Information System (INIS)

Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-01-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

Energy Technology Data Exchange (ETDEWEB)

Wang, Yonggang, E-mail: wangyg@ustc.edu.cn; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

2017-03-01

A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

CERN Document Server

Pickering, J.

2015-06-15

This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.

Application of digital control techniques for satellite medium power DC-DC converters

Science.gov (United States)

Skup, Konrad R.; Grudzinski, Pawel; Nowosielski, Witold; Orleanski, Piotr; Wawrzaszek, Roman

2010-09-01

The objective of this paper is to present a work concerning a digital control loop system for satellite medium power DC-DC converters that is done in Space Research Centre. The whole control process of a described power converter bases on a high speed digital signal processing. The paper presents a development of a FPGA digital controller for voltage mode stabilization that was implemented using VHDL. The described controllers are a classical digital PID controller and a bang-bang controller. The used converter for testing is a simple model of 5-20 W, 200 kHz buck power converter. A high resolution digital PWM approach is presented. Additionally a simple and effective solution of filtering of an analog-to-digital converter output is presented.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

International Nuclear Information System (INIS)

Chen, Yuan-Ho

2017-01-01

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

A counting-weighted calibration method for a field-programmable-gate-array-based time-to-digital converter

Energy Technology Data Exchange (ETDEWEB)

Chen, Yuan-Ho, E-mail: chenyh@mail.cgu.edu.tw [Department of Electronic Engineering, Chang Gung University, Tao-Yuan 333, Taiwan (China); Department of Radiation Oncology, Chang Gung Memorial Hospital, Tao-Yuan 333, Taiwan (China); Center for Reliability Sciences and Technologies, Chang Gung University, Tao-Yuan 333, Taiwan (China)

2017-05-11

In this work, we propose a counting-weighted calibration method for field-programmable-gate-array (FPGA)-based time-to-digital converter (TDC) to provide non-linearity calibration for use in positron emission tomography (PET) scanners. To deal with the non-linearity in FPGA, we developed a counting-weighted delay line (CWD) to count the delay time of the delay cells in the TDC in order to reduce the differential non-linearity (DNL) values based on code density counts. The performance of the proposed CWD-TDC with regard to linearity far exceeds that of TDC with a traditional tapped delay line (TDL) architecture, without the need for nonlinearity calibration. When implemented in a Xilinx Vertix-5 FPGA device, the proposed CWD-TDC achieved time resolution of 60 ps with integral non-linearity (INL) and DNL of [−0.54, 0.24] and [−0.66, 0.65] least-significant-bit (LSB), respectively. This is a clear indication of the suitability of the proposed FPGA-based CWD-TDC for use in PET scanners.

Digitized self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe

2016-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise...... frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints...... updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported....

Very High-Performance Advanced Filter Bank Analog-to-Digital Converter (AFB ADC) Project

National Research Council Canada - National Science Library

Velazquez, Scott

1999-01-01

... of the art by using a parallel array of individual commercial off the shelf converters. The significant performance improvements afforded by the Advanced Filter Bank Analog to Digital Converter (AFB ADC...

A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

International Nuclear Information System (INIS)

Yang Weidong; Pu Jie; Zhang Ruitao; Chen Chao; Zang Jiandong; Li Tiehu; Luo Pu

2015-01-01

This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB and INL less than ±4.3 LSB after the chip is calibrated. (paper)

Mixed Hitting-Time Models

NARCIS (Netherlands)

Abbring, J.H.

2009-01-01

We study mixed hitting-time models, which specify durations as the first time a Levy process (a continuous-time process with stationary and independent increments) crosses a heterogeneous threshold. Such models of substantial interest because they can be reduced from optimal-stopping models with

Ultra-Low-Power Analog-to-Digital Converters for Medical Applications

OpenAIRE

Zhang, Dai

2014-01-01

Biomedical systems are commonly attached to or implanted into human bodies, and powered by harvested energy or small batteries. In these systems, analog-to-digital converters (ADCs) are key components as the interface between the analog world and the digital domain. Conversion of the low frequency bioelectric signals does not require high speed, but ultralow- power operation. This combined with the required conversion accuracy makes the design of such ADCs a major challenge. Among prevalent A...

Implementation of Power Efficient Flash Analogue-to-Digital Converter

Directory of Open Access Journals (Sweden)

Taninki Sai Lakshmi

2014-01-01

Full Text Available An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL value of −0.30 LSB and differential nonlinearity (DNL value of −0.24 LSB, of the flash ADC.

Two applications of direct digital down converters in beam diagnostics

International Nuclear Information System (INIS)

Powers, Tom; Flood, Roger; Hovater, Curt; Musson, John

2000-01-01

The technologies of direct digital down converters, digital frequency synthesis, and digital signal processing are being used in many commercial applications. Because of this commercialization, the component costs are being reduced to the point where they are economically viable for large scale accelerator applications. This paper will discuss two applications of these technologies to beam diagnostics. In the first application the combination of direct digital frequency synthesis and direct digital down converters are coupled with digital signal processor technology in order to maintain the stable gain environment required for a multi-electrode beam position monitoring system. This is done by injecting a CW reference signal into the electronics as part of the front-end circuitry. In the second application direct digital down converters are used to provide a novel approach to the measurement of beam intensity using cavity current monitors. In this system a pair of reference signals are injected into the cavity through an auxiliary port. The beam current is then calculated as the ratio of the beam signal divided by the average of the magnitude of the two reference signals

Analysis and characterization of cyclic-scale compensated analog-to-digital converters

International Nuclear Information System (INIS)

Gatti, E.; Manfredi, P.F.; Marino, D.

1979-01-01

The authors discuss characteristics and limitations of cyclic-scale compensated analog-to-digital converters. After summarizing the behaviour of the method implemented in an ideal way, they show how the inaccuracies in the auxillary analog levels affect the real design. Having stated under what approximations and with what cares a cyclic-scale compensated converter approaches the ideal case of channels having equal profiles, the consequences of this property, are studied. (Auth.)

Digital regulation of a phase controlled power converter

International Nuclear Information System (INIS)

Schultheiss, C.; Haque, T.

1995-01-01

The Relativistic Heavy Ion Collider, now in construction at Brookhaven National Laboratory, will use phase controlled power converters for the main dipole and quadrupole magnet strings. The rectifiers in these power supplies will be controlled by a digital regulator based on the TI 320C30 Digital Signal Processor (DSP). The DSP implements the current loop, the voltage loop, and a system to actively reduce the sub-harmonic ripple components. Digital firing circuits consisting of a phase locked lop and counters are used to fire the SCRs. Corrections for the sub-harmonic reduction are calculated by the DSP and stored in registers in the firing circuit. These corrections are added in hardware, to the over-all firing count provided by the DSP. the resultant count is compared to a reference counter to fire the SCRs. This combination of a digital control system and the digital firing circuits allows the correction of the sub-harmonics in a real-time sense. A prototype of the regulator has been constructed, and the preliminary testing indicates a sub-harmonic reduction of 60 dB

Design of a 12-bit 80MS/s pipeline analog-to-digital converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, Juan F.; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s pipeline Analog-to-Digital converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation, synthesis and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog Converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is based on a 10-stage pipeline preceded by a sample/hold with bootstrapping technique. Each stage gives 1.5 effective bits, except for the first one which provides 2.5 effective bits to improve linearity. The Analog-to-Digital architecture uses redundant bits for digital correction, it is planned to be implemented without using calibration and employs a subranging pipeline look-ahead technique to increase speed. Substrate biased MOSFETs in the depletion region are used as capacitors, linearized by a series compensation. Simulation results show that the Multi-Tone Power Ratio is higher than 56dB for several DMT test signals and the estimated Signal-to-Noise Ratio yield is supposed to be better than 62 dB from DC to Nyquist frequency. The converter dissipates less than 150mW from a 3.3V supply and occupies less than 4 mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

Resonant Tunneling Analog-To-Digital Converter

Science.gov (United States)

Broekaert, T. P. E.; Seabaugh, A. C.; Hellums, J.; Taddiken, A.; Tang, H.; Teng, J.; vanderWagt, J. P. A.

1995-01-01

As sampling rates continue to increase, current analog-to-digital converter (ADC) device technologies will soon reach a practical resolution limit. This limit will most profoundly effect satellite and military systems used, for example, for electronic countermeasures, electronic and signal intelligence, and phased array radar. New device and circuit concepts will be essential for continued progress. We describe a novel, folded architecture ADC which could enable a technological discontinuity in ADC performance. The converter technology is based on the integration of multiple resonant tunneling diodes (RTD) and hetero-junction transistors on an indium phosphide substrate. The RTD consists of a layered semiconductor hetero-structure AlAs/InGaAs/AlAs(2/4/2 nm) clad on either side by heavily doped InGaAs contact layers. Compact quantizers based around the RTD offer a reduction in the number of components and a reduction in the input capacitance Because the component count and capacitance scale with the number of bits N, rather than by 2 (exp n) as in the flash ADC, speed can be significantly increased, A 4-bit 2-GSps quantizer circuit is under development to evaluate the performance potential. Circuit designs for ADC conversion with a resolution of 6-bits at 25GSps may be enabled by the resonant tunneling approach.

A multi-channel time-to-digital converter chip for drift chamber readout

International Nuclear Information System (INIS)

Santos, D.M.; Chau, A.; DeBusshere, D.; Dow, S.; Flasck, J.; Levi, M.; Kirsten, F.; Su, E.

1995-12-01

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8μ triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz

Mathematical Modeling and Digital Control of A Hybrid Switching Buck Converter

Directory of Open Access Journals (Sweden)

Muhammad Umar Abbasi

2017-06-01

Full Text Available The aim of this paper is to describe mathematical modeling and digital control of a hybrid switching buck converter. This converter belongs to a class of so called hybrid switching converters and contains a resonant capacitor, resonant inductor and a diode in addition to original buck converter components. The dc gain of this converter is shown to be independent of resonant branch parameters. Moreover the dc conversion ratio is derived for both ideal case and including main inductor dc resistance. Small signal model of the converter is derived and is shown to be similar to conventional buck converter. Simulation results in SIMPLIS Software as well as experimental results of digital control using an 8 bit STM microcontroller are presented. The potential advantages and applications of this converter are discussed.

VHDL Implementation of Sigma-Delta Analog To Digital Converter

Science.gov (United States)

Chavan, R. N.; Chougule, D. G.

2010-11-01

Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

Lead generation and examples opinion regarding how to follow up hits.

Science.gov (United States)

Orita, Masaya; Ohno, Kazuki; Warizaya, Masaichi; Amano, Yasushi; Niimi, Tatsuya

2011-01-01

In fragment-based drug discovery (FBDD), not only identifying the starting fragment hit to be developed but also generating a drug lead from that starting fragment hit is important. Converting fragment hits to leads is generally similar to a high-throughput screening (HTS) hits-to-leads approach in that properties associated with activity for a target protein, such as selectivity against other targets and absorption, distribution, metabolism, excretion, and toxicity (ADME/Tox), and physicochemical properties should be taken into account. However, enhancing the potency of the fragment hit is a key requirement in FBDD, unlike HTS, because initial fragment hits are generally weak. This enhancement is presently achieved by adding additional chemical groups which bind to additional parts of the target protein or by joining or combining two or more hit fragments; however, strategies for effecting greater improvements in effective activity are needed. X-ray analysis is a key technology attractive for converting fragments to drug leads. This method makes it clear whether a fragment hit can act as an anchor and provides insight regarding introduction of functional groups to improve fragment activity. Data on follow-up chemical synthesis of fragment hits has allowed for the differentiation of four different strategies: fragment optimization, fragment linking, fragment self-assembly, and fragment evolution. Here, we discuss our opinion regarding how to follow up on fragment hits, with a focus on the importance of fragment hits as an anchor moiety to so-called hot spots in the target protein using crystallographic data. Copyright © 2011 Elsevier Inc. All rights reserved.

A study of analog-to digital sliding scale. Converter utilization

Energy Technology Data Exchange (ETDEWEB)

Maddaleno, F; Rossi, M

1996-12-31

The well-known Sliding Scale technique provides a statistical linearization of the Analog to Digital Converter, obtaining a high differential linearity. This technique sums at each conversion a known and uncorrelated variable signal (offset) to the analog input signal, and then subs tract numerically the offset from the conversion result. 2 refs.

A Fast Time-to-Pulse Height Converter

Energy Technology Data Exchange (ETDEWEB)

Aspelund, O

1962-12-15

A fast time-to-pulse height converter representing a development of Green and Bell's gated beam converter is described. The converter is compatible with 2 input pulses in the stop channel and exhibits excellent linearity and time resolution properties. High stability and large output pulses are obtained by using a large time constant in the converting network.

Proposition of a scheme for adaptive/intelligent analog-to-digital converters

International Nuclear Information System (INIS)

Vaidya, P.P.; Kataria, S.K.

2001-01-01

The paper proposes design of a new class of Analog to Digital Converters (ADC's) which we call as Intelligent ADC's with moving resolution. Unlike presently available ADC's which are designed for specific range of applications and give fixed resolution and conversion time, the intelligent ADC's described here can adjust their resolution during the process of conversion, depending upon nature of input signal to make optimum use of the hard-ware. It is possible to use an intelligent ADC to give resolution ranging from 8 bit to 16 bit and conversion time ranging from few nano sec. to few micro secs. These ADC's have significant advantages over conventional ones when used for nuclear pulse spectroscopy as well as for process control applications. (author)

New technologies for radiation-hardening analog to digital converters

International Nuclear Information System (INIS)

Gauthier, M.K.

1982-12-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years

New technologies for radiation-hardening analog to digital converters

Science.gov (United States)

Gauthier, M. K.

1982-01-01

Surveys of available Analog to Digital Converters (ADC) suitable for precision applications showed that none have the proper combination of accuracy and radiation hardness to meet space and/or strategic weapon requirements. A development program which will result in an ADC device which will serve a number of space and strategic applications. Emphasis was placed on approaches that could be integrated onto a single chip within three to five years.

Unified Digital Periodic Signal Filters for Power Converter Systems

DEFF Research Database (Denmark)

Yang, Yongheng; Xin, Zhen; Zhou, Keliang

2017-01-01

Periodic signal controllers like repetitive and resonant controllers have demonstrated much potential in the control of power electronic converters, where periodic signals (e.g., ac voltages and currents) can be precisely regulated to follow references. Beyond the control of periodic signals, ac...... signal processing (e.g., in synchronization and pre-filtering) is also very important for power converter systems. Hence, this paper serves to unify digital periodic signal filters so as to maximize their roles in power converter systems (e.g., enhance the control of ac signals). The unified digital...... periodic signal filters behave like a comb filter, but it can also be configured to selectively filter out the harmonics of interest (e.g., the odd-order harmonics in single-phase power converter systems). Moreover, a virtual variable-sampling-frequency unit delay that enables frequency adaptive periodic...

Low-Power, Low-Voltage Resistance-to-Digital Converter for Sensing Applications

Directory of Open Access Journals (Sweden)

Sergey Y. YURISH

2016-09-01

Full Text Available IC (ASIP of Universal Sensors and Transducers Interface (USTI-MOB with low power consumption, working in the resistive measurement mode (one of 26 possible measuring modes is described in the article. The proposed IC has 20 W to 4.5 M W range of measurement, relative error< ±0.04 %, 0.85 mA supply current and 1.2 V supply voltage. The worst-case error of about< ±1.54 % is observed. IC has three popular serial interfaces: I2C, SPI and RS232/USB. Due to high metrological performance and technical characteristics the USTI- MOB is well suitable for such application as: sensor systems for IoT, wearable and mobile devices, and digital multimeters. The ICs can also work with any quasi-digital resistive converters, in which the resistance is converted to frequency, period, duty-cycle or pulse width.

8-bit serial-parallel analog-to-digital converter for fast transient recorder

International Nuclear Information System (INIS)

Kulka, Z.; Nadachowski, M.; Zimek, Z.

1990-08-01

An 8-bit serial-parallel analog-to-digital converter with a sampling frequency 5 MHz is described. The most important circuits of the device are described and parameters are given. The converter is a central part of a transient recorder type TR-1 designed for recording pulse waveforms in measurements of the kinetics of chemical reactions which are radiation-induced using an electron linear accelerator. 9 refs., 9 figs. (author)

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham

2014-08-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

KAUST Repository

Omran, Hesham; Arsalan, Muhammad; Salama, Khaled N.

2014-01-01

In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter

NARCIS (Netherlands)

Kashmiri, S.M.; Xia, S.; Makinwa, K.A.A.

2009-01-01

This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread

A multi-channel time-to-digital converter chip for drift chamber readout

International Nuclear Information System (INIS)

Chau, A.; DeBusschere, D.; Dow, S.F.; Flasck, J.; Levi, M.E.; Kirsten, F.; Su, E.; Santos, D.M.

1996-01-01

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e., 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 microm triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral nonlinearities of the TDC and the FADC are 230 ps and 9 mV, respectively

Multisensor transducer based on a parallel fiber optic digital-to-analog converter

Directory of Open Access Journals (Sweden)

Grechishnikov Vladimir

2017-01-01

Full Text Available Considered possibility of creating a multisensory information converter (MSPI based on new fiber-optic functional element-digital-to-analog (DAC fiber optic converter. The use of DAC fiber-optic provides jamming immunity combined with low weight and cost of indicators .Because of that MSPI scheme was developed based on parallel DAC fiber-optic (Russian Federation Patent 157416. We came up with an equation for parallel DAC fiber-optic. An eleborate general mathematical model of the proposed converter. Developed a method for reducing conversion errors by placing the DAC transfer function between i and i + 1 ADC quantization levels. By using this model it allows you to obtain reliable information about the technical capabilities of a converter without the need for costly experiments.

A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology

Energy Technology Data Exchange (ETDEWEB)

Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong, E-mail: yujinshan@yeah.net [National Laboratory of Analog IC' s, Chongqing 400060 (China)

2011-01-15

A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-{mu}m CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input. (semiconductor integrated circuits)

FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

DEFF Research Database (Denmark)

Taeed, Fazel; Salam, Z.; Ayob, S.

2012-01-01

converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA.......) and applied on a 50-W boost converter. The SIFLC is compared to the proportional-integral controller; the simulation and practical results indicate that SIFLC exhibits excellent performance for step load and input reference changes. Another feature of this work is the absence of an external analog-to-digital...

A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

International Nuclear Information System (INIS)

Chen Kai; Liu Shubin; An Qi

2010-01-01

In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

Design of a 12-bit 80-MS/s CMOS digital-to-analog converter for PLC-VDSL applications

Science.gov (United States)

Ruiz-Amaya, Jesus; Delgado-Restituto, Manuel; Fernandez-Bootello, J. Francisco; de la Rosa, Jose M.

2005-06-01

This paper describes the design of a 12-bit 80MS/s Digital-to-Analog converter implemented in 0.13mm CMOS logic technology. The design has been computer-aided by a developed toolbox for the simulation and verification of Nyquist-Rate Analog-to-Digital and Digital-to-Analog converters in MATLAB. The embedded simulator uses SIMULINK C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time and makes the proposed tool an advantageous alternative for fast exploration of requirements and as a design validation tool. The converter is segmented in a unary current-cell matrix for 8 MSB's and a binary-weighted array for 4 LSB's. Current sources of the converter are laid out separately from current-cell switching matrix core block and distribute in double centroid to reduce random errors and transient noise coupling. The linearity errors caused by remaining gradient errors are reduced by a modified Q2 Random-Walk switching sequence. Simulation results show that the Spurious-Free Dynamic-Range is better than 58.5dB up to 80MS/s. The estimated Signal-to-Noise Distortion Ratio yield is 99.7% and it is supposed to be better than 58dB from DC to Nyquist frequency. Multi-Tone Power Ratio is higher 59dB for several DMT test signals. The converter dissipates less than 129mW from a 3.3V supply and occupies less than 1.7mm2 die area. The results have been checked with all process corners from -40° to 85° and power supply from 3V to 3.6V.

A fast DSP-based calorimeter hit scanning system

International Nuclear Information System (INIS)

Sekikawa, S.; Arai, I.; Suzuki, A.; Watanabe, A.; Marlow, D.R.; Mindas, C.R.; Wixted, R.L.

1997-01-01

A custom made digital signal processor (DSP) based system has been developed to scan calorimeter hits read by a 32-channel FASTBUS waveform recorder board. The scanner system identifies hit calorimeter elements by surveying their discriminated outputs. This information is used to generate a list of addresses, which guides the read-out process. The system is described and measurements of the scan times are given. (orig.)

A broad-application microchannel-plate detector system for advanced particle or photon detection tasks large area imaging, precise multi-hit timing information and high detection rate

CERN Document Server

Jagutzki, O; Mergel, V; Schmidt-Böcking, H; Spielberger, L; Spillmann, U; Ullmann-Pfleger, K

2002-01-01

New applications for single particle and photon detection in many fields require both large area imaging performance and precise time information on each detected particle. Moreover, a very high data acquisition rate is desirable for most applications and eventually the detection and imaging of more than one particle arriving within a microsecond is required. Commercial CCD systems lack the timing information whereas other electronic microchannel plate (MCP) read-out schemes usually suffer from a low acquisition rate and complicated and sometimes costly read-out electronics. We have designed and tested a complete imaging system consisting of an MCP position readout with helical wire delay-lines, single-unit amplifier box and PC-controlled time-to-digital converter (TDC) readout. The system is very flexible and can detect and analyse position and timing information at single particle rates beyond 1 MHz. Alternatively, multi-hit events can be collected and analysed at about 20 kHz rate. We discuss the advantage...

Simple Digital Control of a Two-Stage PFC Converter Using DSPIC30F Microprocessor

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2010-01-01

The use of dsPIC digital signal controllers (DSC) in Switch Mode Power Supply (SMPS) applications opens new perspectives for cheap and flexible digital control solutions. This paper presents the digital control of a two stage power factor corrector (PFC) converter. The PFC circuit is designed...... and built for 70W rated output power. Average current mode control for boost converter and current programmed control for forward converter are implemented on a dsPIC30F1010. Pulse Width Modulation (PWM) technique is used to drive the switching MOSFETs. Results show that digital solutions with ds...

The characterization and application of a low resource FPGA-based time to digital converter

Energy Technology Data Exchange (ETDEWEB)

Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

2014-03-01

Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

Digitally Controlled Offline Converter with Galvanic Isolation Based on an 8-bit Microcontroller

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

2007-01-01

This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side of the co......This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side...

10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements

Energy Technology Data Exchange (ETDEWEB)

Markovic, B.; Tamborini, D.; Villa, F.; Tisa, S.; Tosi, A.; Zappa, F. [Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci 32, 20133 Milano (Italy)

2012-07-15

We present a compact high performance time-to-digital converter (TDC) module that provides 10 ps timing resolution, 160 ns dynamic range and a differential non-linearity better than 1.5% LSB{sub rms}. The TDC can be operated either as a general-purpose time-interval measurement device, when receiving external START and STOP pulses, or in photon-timing mode, when employing the on-chip SPAD (single photon avalanche diode) detector for detecting photons and time-tagging them. The instrument precision is 15 ps{sub rms} (i.e., 36 ps{sub FWHM}) and in photon timing mode it is still better than 70 ps{sub FWHM}. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via an user-friendly software interface. The module proves to be the best candidate for a wide variety of applications such as: fluorescence lifetime imaging, time-of-flight ranging measurements, time-resolved positron emission tomography, single-molecule spectroscopy, fluorescence correlation spectroscopy, diffuse optical tomography, optical time-domain reflectometry, quantum optics, etc.

The RHIC general purpose multiplexed analog to digital converter system

International Nuclear Information System (INIS)

Michnoff, R.

1995-01-01

A general purpose multiplexed analog to digital converter system is currently under development to support acquisition of analog signals for the Relativistic Heavy Ion Collider (RHIC) at Brookhaven National Laboratory. The system consists of a custom intelligent VME based controller module (V113) and a 14-bit 64 channel multiplexed A/D converter module (V114). The design features two independent scan groups, where one scan group is capable of acquiring 64 channels at 60 Hz, concurrently with the second scan group acquiring data at an aggregate rate of up to 80 k samples/second. An interface to the RHIC serially encoded event line is used to synchronize acquisition. Data is stored in a circular static RAM buffer on the controller module, then transferred to a commercial VMEbus CPU board and higher level workstations for plotting, report Generation, analysis and storage

Time-interleaved high-speed D/A converters

NARCIS (Netherlands)

Olieman, E.

2016-01-01

This thesis is on power efficient very high-speed digital-to-analog converters (DACs) in CMOS technology, intended to generate signals from DC to RF. Components in RF signal chains are nowadays often moved from the analog domain to the digital domain. This allows for more flexibility and better

Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

Directory of Open Access Journals (Sweden)

Lei Sun

2014-01-01

Full Text Available This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs of successive approximation register analog-to-digital converter (ADC. Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V(cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL/integral non linearity (INL performance.

A time digitizer for the microstrip detectors of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Riccardi, Alberto; Brinkmann, Kai-Thomas; Di Pietro, Valentino [II. Physikalisches Institut, Justus-Liebig-Universitaet Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2015-07-01

In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrain the maximum dynamic range of the ADC. Still, the energy information can be obtained with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short, this implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation an overview of the analog part of the PASTA (PANDA strip ASIC) is presented.

Analog-to-digital conversion

CERN Document Server

Pelgrom, Marcel J M

2010-01-01

The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

Energy Technology Data Exchange (ETDEWEB)

Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

2009-11-11

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

International Nuclear Information System (INIS)

Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

2009-01-01

A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

Science.gov (United States)

Gauthier, M. K.; Perret, J.; Evans, K. C.

1981-01-01

The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

Data readout system on the base of CAMAC time-to-digital converters with time resolution 2 ns for a drift chamber; Sistema s{sup e}ma informatsii s drejfovykh kamer na osnove vremyatsmfrovykh preobrazovatelej s 2 ns razresheniem v standarte KAMAK

Energy Technology Data Exchange (ETDEWEB)

Sidorkin, V V

1996-12-31

Data readout system for drift chambers consists of time-to-digital converter (TDS), timer-generator (TG) and sub controller. Maximal time of conversion constitutes 12.5 m ks. Block-circuits of TDC and TG are presented and their functioning under calibration and measuring is studied as well. 4 refs.

Real-time digital x-ray subtraction imaging

International Nuclear Information System (INIS)

Mistretta, C.A.; Kruger, R.A.; Houk, T.L.

1982-01-01

A method of producing visible difference images derived from an x-ray image of an anatomical subject is described. X-rays are directed through the subject, and the image is converted into television fields comprising trains of analog video signals. The analog signals are converted into digital signals, which are then integrated over a predetermined time corresponding to several television fields. Difference video signals are produced by performing a subtraction between the ongoing video signals and the corresponding integrated signals, and are converted into visible television difference images representing changes in the x-ray image

Converting Topographic Maps into Digital Form to Aid in Archeological Research in the Peten, Guatemala

Science.gov (United States)

Aldrich, Serena R.

1999-01-01

The purpose of my project was to convert a topographical map into digital form so that the data can be manipulated and easily accessed in the field. With the data in this particular format, Dr. Sever and his colleagues can highlight the specific features of the landscape that they require for their research of the ancient Mayan civilization. Digital elevation models (DEMs) can also be created from the digitized contour features adding another dimension to their research.

Energy-Efficient Capacitance-to-Digital Converters for Smart Sensor Applications

KAUST Repository

Alhoshany, Abdulaziz

2017-12-01

One of the key requirements in the design of wireless sensor nodes and miniature biomedical devices is energy efficiency. For a sensor node, which is a sensor and readout circuit, to survive on limited energy sources such as a battery or harvested energy, its energy consumption should be minimized. Capacitive sensors are candidates for use in energy-constrained applications, as they do not consume static power and can be used in a wide range of applications to measure different physical, chemical or biological quantities. However, the energy consumption is dominated by the capacitive interface circuit, i.e. the capacitance-to-digital converter (CDC). Several energy-efficient CDC architectures are introduced in this dissertation to meet the demand for high resolution and energy efficiency in smart capacitive sensors. First, we propose an energy-efficient CDC based on a differential successive-approximation data converter. The proposed differential CDC employs an energy-efficient operational transconductance amplifier (OTA) based on an inverter. A wide capacitance range with fine absolute resolution is implemented in the proposed coarse-fine DAC architecture which saves 89% of silicon area. The proposed CDC achieves an energy efficiency figure-of-merit () of 45.8fJ/step, which is the best reported energy efficiency to date. Second, we propose an energy efficient CDC for high-precision capacitive resolution by using oversampling and noise shaping. The proposed CDC achieves 150 aF absolute resolution and an energy efficiency of 187fJ/conversion-step which outperforms state of the art high-precision differential CDCs. In the third and last part, we propose an in-vitro cancer diagnostic biosensor-CMOS platform for low-power, rapid detection, and low cost. The introduced platform is the first to demonstrate the ability to screen and quantify the spermidine/spermine N1 acetyltransferase (SSAT) enzyme which reveals the presence of early-stage cancer, on the surface of a

Converting analog interpretive data to digital formats for use in database and GIS applications

Science.gov (United States)

Flocks, James G.

2004-01-01

database and GIS software as point, vector or text information is commonly lost. Sediment core descriptions and interpretation of geophysical profiles are usually portrayed as lines, curves, symbols and text information. They have vertical and horizontal dimensions associated with depth, category, time, or geographic position. These dimensions are displayed in consistent positions, which can be digitized and converted to a digital format, such as a spreadsheet. Once this data is in a digital, tabulated form it can easily be made available to a wide variety of imaging and data manipulation software for compilation and world-wide dissemination.

4 Channel Digital Down Converter – DDC (EDA-00991)

CERN Document Server

BLAS, A; DELONG, J (BNL)

2012-01-01

A novel rf beam control architecture has been successfully tested in the LEIR synchrotron. The design is based on a VME 64X carrier board, including a DSP (digital signal processor), into which different daughter cards can be plugged in. The DDC (Digital Down Converter) is one of them. Hardware wise it has the features of a four-channel ADC (analogue-to-digital converter) which outputs drive a powerful FPGA (field programmable logic array); the latter is connected to the DSP on the carrier board via high-speed connectors. Mainly, this unit will acquire rf signals to analyze their phase and amplitude at a specified harmonic of the revolution. The main sampling clock feeding the mezzanine board is at a high harmonic of the particle’s revolution frequency. In the PSB, this frequency is varying along the accelerating cycle and this choice allows analyzing the rf signals from the cavities or from the beam without changing any parameter along the cycle. The sampling clock is tagged at the revolution rate allowing...

Adaptive Reference Levels in a Level-Crossing Analog-to-Digital Converter

Directory of Open Access Journals (Sweden)

Andrew C. Singer

2008-11-01

Full Text Available Level-crossing analog-to-digital converters (LC ADCs have been considered in the literature and have been shown to efficiently sample certain classes of signals. One important aspect of their implementation is the placement of reference levels in the converter. The levels need to be appropriately located within the input dynamic range, in order to obtain samples efficiently. In this paper, we study optimization of the performance of such an LC ADC by providing several sequential algorithms that adaptively update the ADC reference levels. The accompanying performance analysis and simulation results show that as the signal length grows, the performance of the sequential algorithms asymptotically approaches that of the best choice that could only have been chosen in hindsight within a family of possible schemes.

Radiation-hard analog-to-digital converters for space and strategic applications

Science.gov (United States)

Gauthier, M. K.; Dantas, A. R. V.

1985-01-01

During the course of the Jet Propulsion Laboratory's program to study radiation-hardened analog-to-digital converters (ADCs), numerous milestones have been reached in manufacturers' awareness and technology development and transfer, as well as in user awareness of these developments. The testing of ADCs has also continued with twenty different ADCs from seven manufacturers, all tested for total radiation dose and three tested for neutron effects. Results from these tests are reported.

Number-to-voltage converter on commutated condensers

International Nuclear Information System (INIS)

Grekhov, Yu.N.

1975-01-01

A code-voltage converter using precision voltage dividers based on commutated capacitors [1] is described which is distinguished by the absence of precision elements. Each digit includes eight field-effect transistors in two 1KT682 microcircuit assemblies and three microcapacitors with a conventional unstable capacitance 6200 pF +- 50%. The converter has a speed of response that is not inferior to that of converters based on R-2R matrices, while in time stability of the characteristics, low interference level, and low output impedance it is superior to such converters

A high-resolution TDC-based board for a fully digital trigger and data acquisition system in the NA62 experiment at CERN

CERN Document Server

Pedreschi, Elena; Angelucci, Bruno; Avanzini, Carlo; Galeotti, Stefano; Lamanna, Gianluca; Magazzù, Guido; Pinzino, Jacopo; Piandani, Roberto; Sozzi, Marco; Spinella, Franco; Venditti, Stefano

2015-01-01

A Time to Digital Converter (TDC) based system, to be used for most sub-detectors in the high-flux rare-decay experiment NA62 at CERN SPS, was built as part of the NA62 fully digital Trigger and Data AcQuisition system (TDAQ), in which the TDC Board (TDCB) and a general-purpose motherboard (TEL62) will play a fundamental role. While TDCBs, housing four High Performance Time to Digital Converters (HPTDC), measure hit times from sub-detectors, the motherboard processes and stores them in a buffer, produces trigger primitives from different detectors and extracts only data related to the lowest trigger level decision, once this is taken on the basis of the trigger primitives themselves. The features of the TDCB board developed by the Pisa NA62 group are extensively discussed and performance data is presented in order to show its compliance with the experiment requirements.

Analog-to-digital conversion using custom CMOS analog memory for the EOS time projection chamber

International Nuclear Information System (INIS)

Lee, K.L.; Arthur, A.A.; Jones, R.W.; Matis, H.S.; Nakamura, M.; Kleinfelder, S.A.; Ritter, H.G.; Wienman, H.H.

1990-01-01

This paper describes the multiplexing scheme of custom CMOS analog memory integrated circuits, 16 channels x 256 cells, into analog to digital converters (ADC's) to handle 15,360 signal channels of a time projection, chamber detector system. Primary requirements of this system are high density, low power and large dynamic range. The analog memory device multiplexing scheme was designed to digitize the information stored in the memory cells. The digitization time of the ADC's and the settling times for the memory unit were carefully interleaved to optimize the performance and timing during the multiplexing operation. This kept the total number of ADC's, a costly and power dissipative component, to an acceptable minimum

Research of digital controlled DC/DC converter based on STC12C5410AD

Science.gov (United States)

Chen, Dan-Jiang; Jin, Xin; Xiao, Zhi-Hong

2010-02-01

In order to study application of digital control technology on DC/DC converter, principle of increment mode PID control algorithm was analyzed in the paper. Then, a SCM named STC12C5410AD was introduced with its internal resources and characteristics. The PID control algorithm can be implemented easily based on it. The output of PID control was used to change the value of a variable that is 255 times than duty cycle, and this reduced the error of calculation. The valid of the presented algorithm was verified by an experiment for a BUCK DC/DC converter. The experimental results indicated that output voltage of the BUCK converter is stable with low ripple.

A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Bruun, Erik

2003-01-01

In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power...... bits performance. Expected power consumption for the prototype is approx. 170 μW....

Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps

Energy Technology Data Exchange (ETDEWEB)

Doerry, Armin Walter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Dubbert, Dale F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tise, Bertice L. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

2014-07-01

Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.

Digitally-controlled PC-interfaced Boost Converter for Educational Purposes

DEFF Research Database (Denmark)

Ljusev, Petar; Andersen, Michael A. E.

2004-01-01

This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server program is established for easier downloading of compensator parameters and current and voltage waveform...

Drift chamber electronics with multi-hit capability for time and current division measurements

Energy Technology Data Exchange (ETDEWEB)

Manarin, A; Pregernig, L; Rabany, M; Saban, R; Vismara, G

1983-11-15

Drift chambers have been installed for luminosity measurements in intersection 5 of the SPS accelerator working in panti p colliding mode. The required electronics is described. The system is able to process up to 16 hits per wire with a double pulse resolution of 40 ns; drift time and current division, with 1.25 ns and 1.6% resolution respectively, are recorded. Transconductance preamplifiers and discriminators are directly mounted on the chamber; 160 m of twisted-apir cable bring the signals to the digitizer unit. Coarse time is measured using RAM techniques, while fine time is obtained by means of a microstrip delay associated with a 100 K ECL priority encoder. Current division used a single 50 MHz Flash ADC which alows 26 dB dynamic range with 6 bit resolution. First operational results are reported.

Algorithmic impediments filtration using the α-truncated mean method in resolver-to-digital converter

Directory of Open Access Journals (Sweden)

Gordiyenko V. I.

2009-02-01

Full Text Available A test diagram of the microcontroller-type resolver-to-digital converter and algorithms for impediments filtration therein are developed. Experimental verification of the α-truncated mean algorithm intended for the suppression of impulse and noise interference is conducted. The test results are given.

LDRD final report: photonic analog-to-digital converter (ADC) technology; TOPICAL

International Nuclear Information System (INIS)

Bowers, M; Deri, B; Haigh, R; Lowry, M; Sargis, P; Stafford, R; Tong, T

1999-01-01

We report on an LDRD seed program of novel technology development (started by an FY98 Engineering Tech-base project) that will enable extremely high-fidelity analog-to-digital converters for a variety of national security missions. High speed (l0+ GS/s ), high precision (l0+ bits) ADC technology requires extremely short aperture times ((approx)1ps ) with very low jitter requirements (sub 10fs ). These fundamental requirements, along with other technological barriers, are difficult to realize with electronics: However, we outline here, a way to achieve these timing apertures using a novel multi-wavelength optoelectronic short-pulse optical source. Our approach uses an optoelectronic feedback scheme with high optical Q to produce an optical pulse train with ultra-low jitter ( sub 5fs) and high amplitude stability ( and lt;10(sup 10)). This approach requires low power and can be integrated into an optoelectronic integrated circuit to minimize the size. Under this seed program we have demonstrated that the optical feedback mechanism can be used to generate a high Q resonator. This has reduced the technical risk for further development, making it an attractive candidate for outside funding

Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux

Science.gov (United States)

Nogrette, F.; Heurteau, D.; Chang, R.; Bouton, Q.; Westbrook, C. I.; Sellem, R.; Clément, D.

2015-11-01

We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 106 s-1 and three-dimensional reconstruction of the coordinates up to 3.2 × 106 particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 105 particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

Traceable calibration for a digital real-time oscilloscope with time interleaving architecture

Science.gov (United States)

Kim, Dongju; Lee, Joo-Gwang; Lee, Dong-Joon; Cho, Chihyun

2018-01-01

Impairments of analog-to-digital converters (ADCs) used in digital real-time oscilloscopes (DRTO) have caused inevitable signal distortions in measurements. To calibrate these errors with traceability, we propose a novel method that consists of two steps. First, each transfer function of the ADCs is measured using pulse trains from a photodiode calibrated up to 110 GHz. Each data set of the ADCs is superimposed to convert the repetitive pulse to a single pulse to solve the under-sampling problem of the separated data depending on each ADC. Then, the signals of the device under test (DUT) are also separated and superimposed depending on the ADCs, and they are calibrated in the frequency domain based on the measured transfer functions. After a calibration process, the data set is reconverted to the time domain to achieve traceable calibration. To verify our method, we have measured the output of another 70 GHz photodiode with a calibrated DRTO. In terms of results, time-interleaved errors are suppressed by more than 24 dB up to the bandwidth of the DRTO.

Design of integrated all optical digital to analog converter (DAC) using 2D photonic crystals

Science.gov (United States)

Moniem, Tamer A.; El-Din, Eman S.

2017-11-01

A novel design of all optical 3 bit digital to analog (DAC) converter will be presented in this paper based on 2 Dimension photonic crystals (PhC). The proposed structure is based on the photonic crystal ring resonators (PCRR) with combining the nonlinear Kerr effect on the PCRR. The total size of the proposed optical 3 bit DAC is equal to 44 μm × 37 μm of 2D square lattice photonic crystals of silicon rods with refractive index equal to 3.4. The finite different time domain (FDTD) and Plane Wave Expansion (PWE) methods are used to back the overall operation of the proposed optical DAC.

Digital to Analog Converter Description

NARCIS (Netherlands)

van Tuijl, Adrianus Johannes Maria

2002-01-01

A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1,

Real-time digital X-ray subtraction imaging

International Nuclear Information System (INIS)

Mistretta, C.A.; Kruger, R.A.; Houk, T.L.

1979-01-01

A diagnostic anatomical X-ray apparatus comprising a converter and a television camera for converting an X-ray image of a subject into a series of television fields of video signals is described in detail. A digital memory system stores and integrates the video signals over a time interval corresponding to a plurality of successive television fields. The integrated video signals are recovered from storage and fed to a digital or analogue subtractor, the resulting output being displayed on a television monitor. Thus the display represents on-going changes in the anatomical X-ray image. In a modification, successive groups of fields are stored and integrated in three memories, cyclically, and subtractions are performed between successive pieces of integrated signals to provide a display of successive alterations in the X-ray image. For investigations of the heart, the integrating interval should be of the order of one cardiac cycle. (author)

A new 12-bit spectroscopy analog-to-digital converter type SAA intended for CAMAC acquisition systems

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A new 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for CAMAC acquisition systems is decsribed. ADC type SAA initiates new series of spectroscopy ADC's based on a binary-approximation method in which differential nonlinearity is corrected by a statistical channel width averaging method. The structure and principle of operation, as well as some circuit realizations and specifications of the new converter are described. 41 refs., 5 figs. (author)

Mixed Linear/Square-Root Encoded Single Slope Ramp Provides a Fast, Low Noise Analog to Digital Converter with Very High Linearity for Focal Plane Arrays

Science.gov (United States)

Wrigley, Christopher James (Inventor); Hancock, Bruce R. (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor)

2014-01-01

An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

State trajectories used to observe and control dc-to-dc converters

Science.gov (United States)

Burns, W. W., III; Wilson, T. G.

1976-01-01

State-plane analysis techniques are employed to study the voltage stepup energy-storage dc-to-dc converter. Within this framework, an example converter operating under the influence of a constant on-time and a constant frequency controller is examined. Qualitative insight gained through this approach is used to develop a conceptual free-running control law for the voltage stepup converter which can achieve steady-state operation in one on/off cycle of control. Digital computer simulation data are presented to illustrate and verify the theoretical discussions presented.

An orthogonal-polynomial approach to first-hitting times of birth-death processes

NARCIS (Netherlands)

van Doorn, Erik A.

In a recent paper [J. Theor. Probab. 25 (2012) 950-980] Gong, Mao and Zhang, using the theory of Dirichlet forms, extended Karlin and McGregor's classical results on first-hitting times of a birth-death process on the nonnegative integers by establishing a representation for the Laplace transform

Performance of the Lep Time Digitizer (LTD)

International Nuclear Information System (INIS)

Berst, J.D.; Colledani, C.; Loukas, D.

1988-01-01

Performance of the fastbus digitizer to be used for signal digitizing in the DELPHI detectors is described. Two prototypes, a 128 multihit capability device and a 256 capability device were tested. Test results show that the digitizer works properly. A very good stability is achieved in the range of + 150 mV from the nominal (-2V) supply with the total number of lost hits of the order of 10 -6 either in veto or non veto mode. The optimum clock frequency strongly depends on the gates used as delay elements. With the gates of the first prototype, the optimum frequencies obtained are 117 MHz for the first prototype, and 112 MHz for the second. Output linearity is excellent

Digital parallel-to-series pulse-train converter

Science.gov (United States)

Hussey, J.

1971-01-01

Circuit converts number represented as two level signal on n-bit lines to series of pulses on one of two lines, depending on sign of number. Converter accepts parallel binary input data and produces number of output pulses equal to number represented by input data.

An orthogonal-polynomial approach to first-hitting times of birth-death processes

NARCIS (Netherlands)

van Doorn, Erik A.

In a recent paper in this journal, Gong, Mao and Zhang, using the theory of Dirichlet forms, extended Karlin and McGregor’s classical results on first-hitting times of a birth–death process on the nonnegative integers by establishing a representation for the Laplace transform E[exp(sTij)] of the

Connect high speed analog-digital converter with EPICS based on LabVIEW

International Nuclear Information System (INIS)

Wang Wei; Chi Yunlong

2008-01-01

This paper introduce a method to connect high speed analog-digital converter (ADC212/100) with EPICS on Windows platform using LabVIEW. We use labVIEW to communicate with the converter, then use interface sub-VIs between LabVIEW and EPICS to access the EPICS IOC by Channel Access (CA). For the easy use graph programming language of LabVIEW, this method could shorten the develop period and reduce manpower cost. (authors)

Real-time digital x-ray subtraction imaging

International Nuclear Information System (INIS)

Mistretta, C.A.

1982-01-01

The invention provides a method of producing visible difference images derived from an X-ray image of an anatomical subject, comprising the steps of directing X-rays through the anatomical subject for producing an image, converting the image into television fields comprising trains of on-going video signals, digitally storing and integrating the on-going video signals over a time interval corresponding to several successive television fields and thereby producing stored and integrated video signals, recovering the video signals from storage and producing integrated video signals, producing video difference signals by performing a subtraction between the integrated video signals and the on-going video signals outside the time interval, and converting the difference signals into visible television difference images representing on-going changes in the X-ray image

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor

Directory of Open Access Journals (Sweden)

Mostafa Chakir

2017-01-01

Full Text Available The CMOS Monolithic Active Pixel Sensor (MAPS for the International Linear Collider (ILC vertex detector (VXD expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC. This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18 μm CMOS process with a pixel pitch of 35 μm. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76 μm2. The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/−0.0787 LSB and 0.0811/−0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

A Design of a New Column-Parallel Analog-to-Digital Converter Flash for Monolithic Active Pixel Sensor.

Science.gov (United States)

Chakir, Mostafa; Akhamal, Hicham; Qjidaa, Hassan

2017-01-01

The CMOS Monolithic Active Pixel Sensor (MAPS) for the International Linear Collider (ILC) vertex detector (VXD) expresses stringent requirements on their analog readout electronics, specifically on the analog-to-digital converter (ADC). This paper concerns designing and optimizing a new architecture of a low power, high speed, and small-area 4-bit column-parallel ADC Flash. Later in this study, we propose to interpose an S/H block in the converter. This integration of S/H block increases the sensitiveness of the converter to the very small amplitude of the input signal from the sensor and provides a sufficient time to the converter to be able to code the input signal. This ADC is developed in 0.18  μ m CMOS process with a pixel pitch of 35  μ m. The proposed ADC responds to the constraints of power dissipation, size, and speed for the MAPS composed of a matrix of 64 rows and 48 columns where each column ADC covers a small area of 35 × 336.76  μ m 2 . The proposed ADC consumes low power at a 1.8 V supply and 100 MS/s sampling rate with dynamic range of 125 mV. Its DNL and INL are 0.0812/-0.0787 LSB and 0.0811/-0.0787 LSB, respectively. Furthermore, this ADC achieves a high speed more than 5 GHz.

Ionoluminescence analysis of glass scintillators and application to single-ion-hit real-time detection

Energy Technology Data Exchange (ETDEWEB)

Yokoyama, Akihito, E-mail: yokoyama.akihito@jaea.go.jp [Graduate School of Science and Technology, Gunma University, 1-5-1 Tenjin-cho, Kiryu, Gunma 376-8515 (Japan); Takasaki Advanced Radiation Research Institute (TARRI), Japan Atomic Energy Agency (JAEA), 1233 Watanuki-machi, Takasaki, Gunma 370-1292 (Japan); Kada, Wataru [Graduate School of Science and Technology, Gunma University, 1-5-1 Tenjin-cho, Kiryu, Gunma 376-8515 (Japan); Satoh, Takahiro; Koka, Masashi [Takasaki Advanced Radiation Research Institute (TARRI), Japan Atomic Energy Agency (JAEA), 1233 Watanuki-machi, Takasaki, Gunma 370-1292 (Japan); Shimada, Keisuke; Yokoata, Yuya; Miura, Kenta; Hanaizumi, Osamu [Graduate School of Science and Technology, Gunma University, 1-5-1 Tenjin-cho, Kiryu, Gunma 376-8515 (Japan)

2016-03-15

In this paper, we propose and test a real-time detection system for single-ion hits using mega-electronvolt (MeV)-heavy ions. The system was constructed using G2000 and G9 glass scintillators, as well as an electron-multiplying charge-coupled device (EMCCD) camera combined with an inverted microscope with a 10× objective lens. Commercially available G2000 and G9 glass scintillators, which have been reported to exhibit strong photoluminescence at 489, 543, 585, and 622 nm as a result of the Tb{sup 3+} f–f transition, were employed for highly accurate ionized particle detection. The EMCCD camera had a resolution of 512 × 512 pixels, each with a size of 16 μm × 16 μm, and a maximum linear gain of 8 × 10{sup 5} electrons. For 260-MeV Ne, 3 ion hits/s were detected by our system. The intensity of the ionoluminescence (IL) peak induced by the heavy ions was 140 times the noise intensity. In contrast, the luminous diameter at the full width at half maximum (FWHM) in both the horizontal and vertical directions was calculated to be approximately 4.5 μm. These results suggest that our detection system can accurately detect single-ion hits with a diameter of the order of 1 μm.

Precise digital integration in wide time range: theory and realization

International Nuclear Information System (INIS)

Batrakov, A.M.; Pavlenko, A.V.

2017-01-01

The digital integration method based on using high-speed precision analog-to-digital converters (ADC) has become widely used over the recent years. The paper analyzes the limitations of this method that are caused by the signal properties, ADC sampling rate and noise spectral density of the ADC signal path. This analysis allowed creating digital integrators with accurate synchronization and achieving an integration error of less than 10 −5 in the time range from microseconds to tens of seconds. The structure of the integrator is described and its basic parameters are presented. The possibilities of different ADC chips in terms of their applicability to digital integrators are discussed. A comparison with other integrating devices is presented.

A time to voltage converter and analog memory unit for straw tracking detectors

International Nuclear Information System (INIS)

Callewaert, L.; Eyckmans, W.; Sansen, W.; Stevens, A.; Van der Spiegel, J.; Van Berg, R.; Williams, H.H.; Yau, T.Y.

1990-01-01

In a high precision drift tube or straw tracking system, one measures the time of arrival of the first electron at the anode. While many possible schemes exist, the authors initial judgment was that an analog time measurement would offer both lower power and greater resolution than an equally complex digital system. In addition, they believe that it will be necessary to incorporate all of the system features such as connection to the trigger and DAQ systems in any usable design in order to keep the power, mass and complexity of the final system under control. A low power, sub-nanosecond accuracy, quick recovery, data-driven, multiple sample Time to Voltage Converter suitable for use on high rate straw tracking detectors is described. The described TVC includes virtual storage of analog data in both Level 1 and Level 2 queues and an on board ADC with first order correction for capacitance variations and non-linearities

Real-time digital simulation of power electronics systems with Neutral Point Piloted multilevel inverter using FPGA

Energy Technology Data Exchange (ETDEWEB)

Rakotozafy, Mamianja [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France); Poure, Philippe [Laboratoire d' Instrumentation Electronique de Nancy (LIEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Saadate, Shahrokh [Groupe de Recherches en Electrotechnique et Electronique de Nancy (GREEN), Faculte des Sciences et Techniques, BP 70239, 54506 Vandoeuvre Cedex (France); Bordas, Cedric; Leclere, Loic [CONVERTEAM SAS, Parc d' activites Techn' hom, 24 avenue du Marechal Juin, BP 40437, 90008 Belfort Cedex (France)

2011-02-15

Most of actual real time simulation platforms have practically about ten microseconds as minimum calculation time step, mainly due to computation limits such as processing speed, architecture adequacy and modeling complexities. Therefore, simulation of fast switching converters' instantaneous models requires smaller computing time step. The approach presented in this paper proposes an answer to such limited modeling accuracies and computational bandwidth of the currently available digital simulators.As an example, the authors present a low cost, flexible and high performance FPGA-based real-time digital simulator for a complete complex power system with Neutral Point Piloted (NPP) three-level inverter. The proposed real-time simulator can model accurately and efficiently the complete power system, reducing costs, physical space and avoiding any damage to the actual equipment in the case of any dysfunction of the digital controller prototype. The converter model is computed at a small fixed time step as low as 100 ns. Such a computation time step allows high precision account of the gating signals and thus avoids averaging methods and event compensations. Moreover, a novel high performance model of the NPP three-level inverter has also been proposed for FPGA implementation. The proposed FPGA-based simulator models the environment of the NPP converter: the dc link, the RLE load and the digital controller and gating signals. FPGA-based real time simulation results are presented and compared with offline results obtained using PLECS software. They validate the efficiency and accuracy of the modeling for the proposed high performance FPGA-based real-time simulation approach. This paper also introduces new potential FPGA-based applications such as low cost real time simulator for power systems by developing a library of flexible and portable models for power converters, electrical machines and drives. (author)

Process and circuiting arrangement for the conversion of analog signals to digital signals and digital signals to analog signals

International Nuclear Information System (INIS)

Wintzer, K.

1977-01-01

Process for analog-to-digital and digital-to-analog conversion in telecommunication systems whose outstations each have an analog transmitter and an analog receiver. The invention illustrates a method of reducing the power demand of the converters at times when no conversion processes take place. (RW) [de

Digital Fuzzy logic and PI control of phase-shifted full-bridge current-doubler converter

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2011-01-01

Simple digital fuzzy logic voltage control of a phaseshifted full-bridge (PSFB) converter is proposed in this article. A comparison of the fuzzy controller and the classical PI voltage controller is presented and their effects on the converter dynamics are analyzed. Simulation model of the conver...... of the converter was built in Matlab/Simulink using PLECS. A 600W PSFB convert was designed and built and the control strategies were implemented in a 16 bit fixed point dsPIC microcontroller. The advantages and disadvantages of using Fuzzy logic control are highlighted....

Data input from an analog-to-digital converter into the M-6000 computer

International Nuclear Information System (INIS)

Kalashnikov, A.M.; Sheremet'ev, A.K.

1978-01-01

A device for spectrometric data input from the ADC-4096 into the M-6000 computer memory operating in the information storage regime is described. The input device made on integrated circuits coordinates signal levels of the fast response analog-to-digital converter and computer with the help of resistors and inverters. Besides, the input forms a strobe to trigger an increment channel used to record information into the computer memory. The use of the input device permits to get rid of the intermediate information storage in the analyzer memory and ensures fast response of the devices

Reconstruction of hit time and hit position of annihilation quanta in the J-PET detector using the Mahalanobis distance

Directory of Open Access Journals (Sweden)

Sharma Neha Gupta

2015-12-01

Full Text Available The J-PET detector being developed at the Jagiellonian University is a positron emission tomograph composed of the long strips of polymer scintillators. At the same time, it is a detector system that will be used for studies of the decays of positronium atoms. The shape of photomultiplier signals depends on the hit time and hit position of the gamma quantum. In order to take advantage of this fact, a dedicated sampling front-end electronics that enables to sample signals in voltage domain with the time precision of about 20 ps and novel reconstruction method based on the comparison of examined signal with the model signals stored in the library has been developed. As a measure of the similarity, we use the Mahalanobis distance. The achievable position and time resolution depend on the number and values of the threshold levels at which the signal is sampled. A reconstruction method as well as preliminary results are presented and discussed.

Amplitude-to-frequency converter of radioisotope instruments

International Nuclear Information System (INIS)

Demchenkov, V.P.; Korobkov, I.N.

1988-01-01

An amplitude-to-frequency converter designed for signal processing of radioisotope relay devices is descibed. The basic elements of the converter are a scaling amplifier, an analog-to-digital converter, a code-to-frequency converter, a null-organ, a delay unit and a clock-pulse generator. The designed amplitude-to-frequency converter takes into account a prior information about the signal shape of the energy spectrum. The converter processes input pulses of 0.10 V amplitude and duration more than 2μs. The energy channel number is 64

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham

2016-11-16

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

KAUST Repository

Omran, Hesham; Alhoshany, Abdulaziz; Alahmadi, Hamzah; Salama, Khaled N.

2016-01-01

A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

The Strip Silicon Photo-Multiplier: An innovation for enhanced time and position measurement

Energy Technology Data Exchange (ETDEWEB)

Doroud, K., E-mail: Katayoun.Doroud@cern.ch [CERN, Geneva (Switzerland); Williams, M.C.S. [CERN, Geneva (Switzerland); INFN, Bologna (Italy); Yamamoto, K. [Solid State Division, Hamamatsu Photonics K.K., Hamamatsu (Japan)

2017-05-01

There is considerable R&D concerning precise time measurement from a variety of detectors, and in particular for the Silicon PhotoMultiplier (SiPM). In this paper we discuss a new geometry for the SiPM in the form of a strip. A strip can be read out at both end, with each end coupled to an individual TDC (time to digital converter). The time difference is related to the position of the firing SPAD along the length of the strip, while the average of the two times gives the time of the hit. Results from the testing of the first prototype Strip SiPMs are presented in this paper.

A behavioral simulator for switched-capacitor sigma-delta modulator analog-to-digital converter

International Nuclear Information System (INIS)

San, H. Y.; Rezaul Hasan, S. M.

1998-01-01

In this paper, a PC-based simulator for state of the art oversampled switched-capacitor sigma-delta analog-to-digital converters is presented. The proposed simulator employs behavioral model of switched-capacitor integrator and non-linear quantizer to stimulate the system. The behavioral simulation of the integrator is also verified with SPICE. The simulator is fully integrated and standalone. It integrates an input netlist file interpreter, a behavioral simulator, a generic part library and a powerful post-processor to evaluate the SNR, SDR And TSNR. Both passive and active sensitivities can be investigated by the proposed simulator. The simulator is coded in C++, and is very fast

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz

2016-05-03

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

KAUST Repository

Alhoshany, Abdulaziz; Omran, Hesham; Salama, Khaled N.

2016-01-01

An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

Latin Letters Recognition Using Optical Character Recognition to Convert Printed Media Into Digital Format

Directory of Open Access Journals (Sweden)

Rio Anugrah

2017-12-01

Full Text Available Printed media is still popular now days society. Unfortunately, such media encountered several drawbacks. For example, this type of media consumes large storage that impact in high maintenance cost. To keep printed information more efficient and long-lasting, people usually convert it into digital format. In this paper, we built Optical Character Recognition (OCR system to enable automatic conversion the image containing the sentence in Latin characters into digital text-shaped information. This system consists of several interrelated stages including preprocessing, segmentation, feature extraction, classifier, model and recognition. In preprocessing, the median filter is used to clarify the image from noise and the Otsu’s function is used to binarize the image. It followed by character segmentation using connected component labeling. Artificial neural network (ANN is used for feature extraction to recognize the character. The result shows that this system enable to recognize the characters in the image whose success rate is influenced by the training of the system.

Efficiency and hardware comparison of analog control-based and digital control-based 70 W two-stage power factor corrector and DC-DC converters

DEFF Research Database (Denmark)

Török, Lajos; Munk-Nielsen, Stig

2011-01-01

A comparison of an analog and a digital controller driven 70 W two-stage power factor corrector converter is presented. Both controllers are operated in average current-mode-control for the PFC and peak current control for the DC-DC converter. Digital controller design and converter modeling...... is described. Results show that digital control can compete with the analog one in efficiency, PFC and THD....

Hybrid integrated circuit for charge-to-time interval conversion

Energy Technology Data Exchange (ETDEWEB)

Basiladze, S.G.; Dotsenko, Yu.Yu.; Man' yakov, P.K.; Fedorchenko, S.N. (Joint Inst. for Nuclear Research, Dubna (USSR))

The hybrid integrated circuit for charge-to time interval conversion with nanosecond input fast response is described. The circuit can be used in energy measuring channels, time-to-digital converters and in the modified variant in amplitude-to-digital converters. The converter described consists of a buffer amplifier, a linear transmission circuit, a direct current source and a unit of time interval separation. The buffer amplifier represents a current follower providing low input and high output resistances by the current feedback. It is concluded that the described converter excelled the QT100B circuit analogous to it in a number of parameters especially, in thermostability.

Digital peak current mode control with adaptive slope compensation for DC-DC converters

DEFF Research Database (Denmark)

Andersen, Karsten Holm; Nymand, Morten

2017-01-01

performance and stability of current mode control. The presented method adapt to DC-DC converter operating conditions by estimating the rising and falling inductor current slopes, to apply a current slope compensation value to obtain a constant quality factor. The experimental results verifies the theoretical......This paper presents an adaptive slope compensation method for peak current mode control of digital controlled DC-DC converters, which controls the quality factor of the complex conjugated poles at half the switching frequency. Using quality factor control enables optimization of the dynamic...

A double hit model for the distribution of time to AIDS onset

Science.gov (United States)

Chillale, Nagaraja Rao

2013-09-01

Incubation time is a key epidemiologic descriptor of an infectious disease. In the case of HIV infection this is a random variable and is probably the longest one. The probability distribution of incubation time is the major determinant of the relation between the incidences of HIV infection and its manifestation to Aids. This is also one of the key factors used for accurate estimation of AIDS incidence in a region. The present article i) briefly reviews the work done, points out uncertainties in estimation of AIDS onset time and stresses the need for its precise estimation, ii) highlights some of the modelling features of onset distribution including immune failure mechanism, and iii) proposes a 'Double Hit' model for the distribution of time to AIDS onset in the cases of (a) independent and (b) dependent time variables of the two markers and examined the applicability of a few standard probability models.

PIC microcontroller based external fast analog to digital converter to acquire wide-lined solid NMR spectra by BRUKER DRX and Avance-I spectrometers.

Science.gov (United States)

Koczor, Bálint; Rohonczy, János

2015-01-01

Concerning many former liquid or hybrid liquid/solid NMR consoles, the built in Analog-to-Digital Converters (ADCs) are incapable of digitizing the fids at sampling rates in the MHz range. Regarding both strong anisotropic interactions in the solid state and wide chemical shift dispersion nuclei in solution phase such as (195)Pt, (119)Sn, (207)Pb etc., the spectrum range of interest might be in the MHz range. As determining the informative tensor components of anisotropic NMR interactions requires nonlinear fitting over the whole spectrum including the asymptotic baseline, it is prohibited by low sampling rates of the ADCs. Wide spectrum width is also useful in solution NMR, since windowing of wide chemical shift ranges is avoidable. We built an external analog to digital converter with 10 MHz maximal sampling rate, which can work simultaneously with the built in ADC of the spectrometer. The ADC was tested on both Bruker DRX and Avance-I NMR consoles. In addition to the analog channels it only requires three external digital lines of the NMR console. The ADC sends data to PC via USB. The whole process is controlled by software written in JAVA which is implemented under TopSpin. Copyright © 2015 Elsevier Inc. All rights reserved.

Modules of the SUMMA system for data readout to the oscillograph, digital display devices and digital printing

International Nuclear Information System (INIS)

Bushnin, Yu.B.; Denisenko, A.A.; Dunajtsev, A.F.; Rybakov, V.G.; Sytin, A.N.

1975-01-01

The modules of the ''Summa'' system are described which allow outputting of information to an oscilloscope, a digital tableau, and a digital printing mechanism; they are: a digital-analog converter, a converter that converts a binary code to a binary-decimal code, a digital display module, a block for outputting to a digital printing mechanism, and a block for stipulating the programs during information outputting. The block diagrams of the modules and the block diagram of the information-outputting programs are presented

Static and Dynamic Characteristics of DC-DC Converter Using a Digital Filter

Science.gov (United States)

Kurokawa, Fujio; Okamatsu, Masashi

This paper presents the regulation and dynamic characteristics of the dc-dc converter with digital PID control, the minimum phase FIR filter or the IIR filter, and then the design criterion to improve the dynamic characteristics is discussed. As a result, it is clarified that the DC-DC converter using the IIR filter method has superior performance characteristics. The regulation range is within 1.3%, the undershoot against the step change of the load is less than 2% and the transient time is less than 0.4ms with the IIR filter method. In this case, the switching frequency is 100kHz and the step change of the load R is from 50 Ω to 10 Ω. Further, the superior characteristics are obtained when the first gain, the second gain and the second cut-off frequency are relatively large, and the first cut-off frequency and the passing frequency are relatively low. Moreover, it is important that the gain strongly decreases at the second cut-off frequency because the upper band pass frequency range must be always less than half of the sampling frequency based on the sampling theory.

Decimal multiplication using compressor based-BCD to binary converter

Directory of Open Access Journals (Sweden)

Sasidhar Mukkamala

2018-02-01

Full Text Available The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit using parallel architecture. The proposed converters, along with binary coded decimal (BCD adder and binary to BCD converters, are used in parallel implementation of Urdhva Triyakbhyam (UT-based 32-bit BCD multiplier. To increase the performance, compressor circuits were used in converters and multiplier. The designed hardware circuits were verified by behavioural and post layout simulations. The implementation was carried out using Virtex-6 Field Programmable Gate Array (FPGA and Application Specific Integrated Circuit (ASIC with 90-nm technology library platforms. The results on FPGA shows that compressor based converters and multipliers produced less amount of propagation delay with a slight increase of hardware resources. In case of ASIC implementation, a compressor based converter delay is equivalent to conventional converter with a slight increase of gate count. However, the reduction of delay is evident in case of compressor based multiplier.

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2011-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

Circuit with a successive approximation analog to digital converter

NARCIS (Netherlands)

Louwsma, S.M.; Vertregt, Maarten

2010-01-01

During successive approximation analog to digital conversion a series of successive digital reference values is selected that converges towards a digital representation of an analog input signal. An analog reference signal is generated dependent on the successive digital reference values and

Studies on a Hybrid Full-Bridge/Half-Bridge Bidirectional CLTC Multi-Resonant DC-DC Converter with a Digital Synchronous Rectification Strategy

Directory of Open Access Journals (Sweden)

Shu-huai Zhang

2018-01-01

Full Text Available This study presents a new bidirectional multi-resonant DC-DC converter, which is named CLTC. The converter adds an auxiliary transformer and an extra resonant capacitor based on a LLC resonant DC-DC converter, achieving zero-voltage switching (ZVS for the input inverting switches and zero-current switching (ZCS for the output rectifiers in all load range. The converter also has a wide gain range in two directions. When the load is light, a half-bridge configuration is adopted instead of a full-bridge configuration to solve the problem of voltage regulation. By this method, the voltage gain becomes monotonous and controllable. Besides, the digital synchronous rectification strategy is proposed in forward mode without adding any auxiliary circuit. The conduction time of synchronous rectifiers equals the estimation value of body diodes’ conduction time with the lightest load. Power loss analysis is also conducted in different situations. Finally, the theoretical analysis is validated by a 5 kW prototype.

Adiabatic condition and the quantum hitting time of Markov chains

International Nuclear Information System (INIS)

Krovi, Hari; Ozols, Maris; Roland, Jeremie

2010-01-01

We present an adiabatic quantum algorithm for the abstract problem of searching marked vertices in a graph, or spatial search. Given a random walk (or Markov chain) P on a graph with a set of unknown marked vertices, one can define a related absorbing walk P ' where outgoing transitions from marked vertices are replaced by self-loops. We build a Hamiltonian H(s) from the interpolated Markov chain P(s)=(1-s)P+sP ' and use it in an adiabatic quantum algorithm to drive an initial superposition over all vertices to a superposition over marked vertices. The adiabatic condition implies that, for any reversible Markov chain and any set of marked vertices, the running time of the adiabatic algorithm is given by the square root of the classical hitting time. This algorithm therefore demonstrates a novel connection between the adiabatic condition and the classical notion of hitting time of a random walk. It also significantly extends the scope of previous quantum algorithms for this problem, which could only obtain a full quadratic speedup for state-transitive reversible Markov chains with a unique marked vertex.

Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

Science.gov (United States)

Turqueti, Marcos; Prestemon, Soren; Albright, Robert

LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

Directory of Open Access Journals (Sweden)

Sergio Saponara

2010-01-01

Full Text Available The design of a 10-bit resistor-string digital-to-analog converter (DAC for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode.

Seven channel gated charge to time converter

Energy Technology Data Exchange (ETDEWEB)

Stubbs, R J; Waddoup, W D [Durham Univ. (UK)

1977-11-01

By using a hybrid integrated circuit seven independent gated charge to time converters have been constructed in a single width NIM module. Gate widths from < approximately 10 ns to approximately 300 ns are possible with a resolution of 0.25 pC, linearity is better than +-1 pC over 2.5 decades of input signal height. Together with a multichannel scaling system described in the following paper one has a very powerful multichannel gated ADC system.

High energy ion hit technique to local area using microbeam

Energy Technology Data Exchange (ETDEWEB)

Tanaka, Ryuichi; Kamiya, Tomihiro; Suda, Tamotsu; Sakai, Takuro; Hirao, Toshio; Kobayashi, Yasuhiko; Watanabe, Hiroshi [Japan Atomic Energy Research Inst., Takasaki, Gunma (Japan). Takasaki Radiation Chemistry Research Establishment

1997-03-01

Single energetic ion hit technique has been developed as an application of ion microbeam technique, in order to study the effect of local damage or injury to materials and living organisms. The overall performance is basically defined by those of separate techniques: microbeam formation, microbeam positioning, single ion detection, detection signal processing, hit timing control, and hit verification. Recent progress on the developments of these techniques at JAERI-TIARA facility are reviewed. (author)

Development of a NIM module for time-to-digital conversion

International Nuclear Information System (INIS)

Lin Yanchang; Wang Xiaobin; Chen Shaomin; Gao Yuanning; Jiang Chunhua; Qian Wenbin

2008-01-01

A developed single slot wide NIM module for time-to-digital conversion (TDC) is presented in this paper. This TDC module consists of a CPLD based double edge trigger counter with logic function circuit, a high speed comparator based NIM-to-TTL logic level converter, a processor ARM based data access and communication control unit, and voltage regulators for power supply. There are two input groups available, separately for accepting start and stop signal between two input ports or just from the same input port in sequence. With a 50 MHz reference clock, the available input ranges from 0 to 81.91 μs, and the resolution can reach 10 ns level. This module was tested in a muon lifetime measurement experiment, showing good linearity, simple configuration, low power consumption, good reliability, low cost, and easy upgrade as well. (authors)

Time-of-flight trigger based on the use of the time-to-amplitude converter

International Nuclear Information System (INIS)

Ladygin, V.P.; Man'yakov, P.K.; Reznikov, S.G.

2000-01-01

The method of the time-of-flight trigger realization based on the use of the time-to-amplitude converter is described. Such a trigger has a short decision time and high efficiency of the useful event selection. (author)

Concentrated Hitting Times of Randomized Search Heuristics with Variable Drift

DEFF Research Database (Denmark)

Lehre, Per Kristian; Witt, Carsten

2014-01-01

Drift analysis is one of the state-of-the-art techniques for the runtime analysis of randomized search heuristics (RSHs) such as evolutionary algorithms (EAs), simulated annealing etc. The vast majority of existing drift theorems yield bounds on the expected value of the hitting time for a target...

Post-hit dynamics of price limit hits in the Chinese stock markets

Science.gov (United States)

Wu, Ting; Wang, Yue; Li, Ming-Xia

2017-01-01

Price limit trading rules are useful to cool off traders short-term trading mania on individual stocks. The price dynamics approaching the limit boards are known as the magnet effect. However, the price dynamics after opening price limit hits are not well investigated. Here, we provide a detailed analysis on the price dynamics after the hits of up-limit or down-limit is open based on all A-share stocks traded in the Chinese stock markets. A "W" shape is found in the expected return, which reveals high probability of a continuous price limit hit on the following day. We also find that price dynamics after opening limit hits are dependent on the market trends. The time span of continuously hitting the price limit is found to an influence factor of the expected profit after the limit hit is open. Our analysis provides a better understanding of the price dynamics around the limit boards and contributes potential practical values for investors.

Digital simulation of FM-ZCS-quasi resonant converter fed DD servo drive using Matlab Simulink

Directory of Open Access Journals (Sweden)

Kattamuri Narasimha Rao

2009-01-01

Full Text Available This paper deals with digital simulation of FM-ZCS-quasi resonant converter fed DC servo drive using Matlab Simulink. Quasi Resonant Converter (QRC is fast replacing conventional PWM converters in high frequency operation. The salient feature of QRC is that the switching devices can be either switched on at zero voltage or switched off at zero current, so that switching losses are zero ideally. Switching stresses are low, volumes are low and power density is high. This property imparts high efficiency and high power density to the converters. The output of QRC is regulated by varying the switching frequency of the converter. Hence it is called Frequency modulated Zero current/zero voltage switching quasi resonant converter. The present work deals with simulation of DC Servo motor fed from ZCS-QRC using Matlab. Simulation results show that the ZCS-QRC's have low total harmonic distortion. The ZCS-QRC operating in half wave and full wave modes are simulated successfully. .

Health Information Technology (HIT) Adaptation: Refocusing on the Journey to Successful HIT Implementation.

Science.gov (United States)

Yen, Po-Yin; McAlearney, Ann Scheck; Sieck, Cynthia J; Hefner, Jennifer L; Huerta, Timothy R

2017-09-07

In past years, policies and regulations required hospitals to implement advanced capabilities of certified electronic health records (EHRs) in order to receive financial incentives. This has led to accelerated implementation of health information technologies (HIT) in health care settings. However, measures commonly used to evaluate the success of HIT implementation, such as HIT adoption, technology acceptance, and clinical quality, fail to account for complex sociotechnical variability across contexts and the different trajectories within organizations because of different implementation plans and timelines. We propose a new focus, HIT adaptation, to illuminate factors that facilitate or hinder the connection between use of the EHR and improved quality of care as well as to explore the trajectory of changes in the HIT implementation journey as it is impacted by frequent system upgrades and optimizations. Future research should develop instruments to evaluate the progress of HIT adaptation in both its longitudinal design and its focus on adaptation progress rather than on one cross-sectional outcome, allowing for more generalizability and knowledge transfer. ©Po-Yin Yen, Ann Scheck McAlearney, Cynthia J Sieck, Jennifer L Hefner, Timothy R Huerta. Originally published in JMIR Medical Informatics (http://medinform.jmir.org), 07.09.2017.

Active pixel sensor having intra-pixel charge transfer with analog-to-digital converter

Science.gov (United States)

Fossum, Eric R. (Inventor); Mendis, Sunetra K. (Inventor); Pain, Bedabrata (Inventor); Nixon, Robert H. (Inventor); Zhou, Zhimin (Inventor)

2003-01-01

An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node and an analog-to-digital converter formed in the substrate connected to the output of the readout circuit.

Simulation of a Real-Time Brain Computer Interface for Detecting a Self-Paced Hitting Task.

Science.gov (United States)

Hammad, Sofyan H; Kamavuako, Ernest N; Farina, Dario; Jensen, Winnie

2016-12-01

An invasive brain-computer interface (BCI) is a promising neurorehabilitation device for severely disabled patients. Although some systems have been shown to work well in restricted laboratory settings, their utility must be tested in less controlled, real-time environments. Our objective was to investigate whether a specific motor task could be reliably detected from multiunit intracortical signals from freely moving animals in a simulated, real-time setting. Intracortical signals were first obtained from electrodes placed in the primary motor cortex of four rats that were trained to hit a retractable paddle (defined as a "Hit"). In the simulated real-time setting, the signal-to-noise-ratio was first increased by wavelet denoising. Action potentials were detected, and features were extracted (spike count, mean absolute values, entropy, and combination of these features) within pre-defined time windows (200 ms, 300 ms, and 400 ms) to classify the occurrence of a "Hit." We found higher detection accuracy of a "Hit" (73.1%, 73.4%, and 67.9% for the three window sizes, respectively) when the decision was made based on a combination of features rather than on a single feature. However, the duration of the window length was not statistically significant (p = 0.5). Our results showed the feasibility of detecting a motor task in real time in a less restricted environment compared to environments commonly applied within invasive BCI research, and they showed the feasibility of using information extracted from multiunit recordings, thereby avoiding the time-consuming and complex task of extracting and sorting single units. © 2016 International Neuromodulation Society.

10-bit rapid single flux quantum digital-to-analog converter for ac voltage standard

International Nuclear Information System (INIS)

Maezawa, M; Hirayama, F

2008-01-01

Digital-to-analog (D/A) converters based on rapid single flux quantum (RSFQ) technology are under development for ac voltage standard applications. We present design and test results on a prototype 10-bit version integrated on a single chip. The 10-bit chip includes over 6000 Josephson junctions and consumes a bias current exceeding 1 A. To reduce the effects of the high bias current on circuit operation, a custom design method was employed in part and large circuit blocks were divided into smaller ones. The 10-bit chips were fabricated and tested at low speed. The test results suggested that our design approach could manage large bias currents on the order of 1 A per chip

A fast online hit verification method for the single ion hit system at GSI

International Nuclear Information System (INIS)

Du, G.; Fischer, B.; Barberet, P.; Heiss, M.

2006-01-01

For a single ion hit facility built to irradiate specific targets inside biological cells, it is necessary to prove that the ions hit the selected targets reliably because the ion hits usually cannot be seen. That ability is traditionally tested either indirectly by aiming at pre-etched tracks in a nuclear track detector or directly by making the ion tracks inside cells visible using a stain coupled to special proteins produced in response to ion hits. However, both methods are time consuming and hits can be verified only after the experiment. This means that targeting errors in the experiment cannot be corrected during the experiment. Therefore, we have developed a fast online hit verification method that measures the targeting accuracy electronically with a spatial resolution of ±1 μm before cell irradiation takes place. (authors)

Conception and realization of a multichannel amplitude converter

International Nuclear Information System (INIS)

Bendebiche, L.

1992-11-01

A compact Analog to Digital Converter system suitable for high resolution γ-ray analysers has been developed based on the ADADC84 12-bit converter from Analog Devices. The converter was equipped with a peak detector and a stretcher, and with a memory card providing the sliding scale circuits, the lower threshold, the channel number identification and the zero suppression. The conversion time is 10 μs and the differential non linearity is less than ±1% for a 12-bit resolution. The converter consists of a 12-bit spectroscopy analog-to-digital converter (ADC) while the memory card includes a 8K 24-bit buffer memory. The two cards are plugged into a slot of an IBM PC AT and using an emulation software converts the micro-computer into a full-featured pulse height analyser. In data acquisition mode, the cards can operate independently, making the computer free for other tasks. The software offers acquisition control, visualization, data handling functions and various types of result presentation

Design of a 1 _s real-time low-noise data acquisition for power converters control loop

CERN Document Server

AUTHOR|(SzGeCERN)712364; Arpaia, Pasquale; Cerqueira Bastos, Miguel; Martino, Michele

2015-01-01

The proof of principle of a real-time data acquisition system to be integrated into a digital control loop for controlling the power converters of the Compact LInear Collider is presented. The system is based on an ultra low noise analogue front-end with 1:1 ppm RMS noise (referred to input), and about 1 _s of real-time delay. After the analogue conditioning, a fully-differential analogue-todigital converter is foreseen. The requirements of this system, directly derived from the accelerator performance, are discussed and translated into design specification. The results obtained by means of Pspice simulations are reported in order to prove that the design is feasible with the proposed architecture. Finally, the results of the experimental validation of the prototype, currently under design, will be included in the final paper.

Making the Switch to Digital Audio

Directory of Open Access Journals (Sweden)

Shannon Gwin Mitchell

2004-12-01

Full Text Available In this article, the authors describe the process of converting from analog to digital audio data. They address the step-by-step decisions that they made in selecting hardware and software for recording and converting digital audio, issues of system integration, and cost considerations. The authors present a brief description of how digital audio is being used in their current research project and how it has enhanced the “quality” of their qualitative research.

Real-time pulse deinterleaving using digital delay line techniques

Science.gov (United States)

Lentz, L. F.; Palermo, T. J.

This paper describes an implementation of a tracking pulse sorter based on predictive gating techniques. Real-time pulse sorters or pulse train gating devices have been utilized by the ELINT signal analyst for many years. The more elementary of these devices employed a retriggerable delay interval and an acceptance gate, which were used in predictive fashion to track pulse trains whose PRIs fall within the limits of the programmed delay interval. This design utilizes the pulse hit/miss history of individual track files in a variation of a sequential observer detection algorithm. Use of a digital delay line with pulse history allows multiple pulse trains to be tracked simultaneously and independently without interference. The design also provides flexibility in lock-on and track criteria to allow maintenance of acquisition probability and false alarm rate in dense signal environments and with low SNRs. The hardware provides time interval resolution to 12.5 nsec and covers a PRI range of 50 microsec to 50 msec.

Integrated power electronic converters and digital control

CERN Document Server

Emadi, Ali; Nie, Zhong

2009-01-01

Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

Statistical properties and pre-hit dynamics of price limit hits in the Chinese stock markets.

Science.gov (United States)

Wan, Yu-Lei; Xie, Wen-Jie; Gu, Gao-Feng; Jiang, Zhi-Qiang; Chen, Wei; Xiong, Xiong; Zhang, Wei; Zhou, Wei-Xing

2015-01-01

Price limit trading rules are adopted in some stock markets (especially emerging markets) trying to cool off traders' short-term trading mania on individual stocks and increase market efficiency. Under such a microstructure, stocks may hit their up-limits and down-limits from time to time. However, the behaviors of price limit hits are not well studied partially due to the fact that main stock markets such as the US markets and most European markets do not set price limits. Here, we perform detailed analyses of the high-frequency data of all A-share common stocks traded on the Shanghai Stock Exchange and the Shenzhen Stock Exchange from 2000 to 2011 to investigate the statistical properties of price limit hits and the dynamical evolution of several important financial variables before stock price hits its limits. We compare the properties of up-limit hits and down-limit hits. We also divide the whole period into three bullish periods and three bearish periods to unveil possible differences during bullish and bearish market states. To uncover the impacts of stock capitalization on price limit hits, we partition all stocks into six portfolios according to their capitalizations on different trading days. We find that the price limit trading rule has a cooling-off effect (object to the magnet effect), indicating that the rule takes effect in the Chinese stock markets. We find that price continuation is much more likely to occur than price reversal on the next trading day after a limit-hitting day, especially for down-limit hits, which has potential practical values for market practitioners.

Electronic circuit for rapid digital NMR signal imaging

International Nuclear Information System (INIS)

Jurak, P.; Krejci, I.; Belusa, J.

1992-01-01

The circuit is made up of two analog-to-digital converters whose outputs are connected to a process computer and the synchronization inputs to the clock terminal. The one analog-to-digital converter is connected, via the signal input, to the terminal of the nuclear magnetic resonance locking signal. The signal input of the other analog-to-digital converter is connected to the time base generator, which can be switched off, and to the magnetic field sweep circuit. The assets of this citcuit include easy computerized processing of the digitized information independently of the time base generation, and prevention of interfering signals from penetrating into the magnetic field sweep circuits. (Z.S.). 1 fig

Liquid Argon TPC Signal Formation, Signal Processing and Hit Reconstruction

Energy Technology Data Exchange (ETDEWEB)

Baller, Bruce [Fermilab

2017-03-11

This document describes the early stage of the reconstruction chain that was developed for the ArgoNeuT and MicroBooNE experiments at Fermilab. These experiments study accelerator neutrino interactions that occur in a Liquid Argon Time Projection Chamber. Reconstructing the properties of particles produced in these interactions requires knowledge of the micro-physics processes that affect the creation and transport of ionization electrons to the readout system. A wire signal deconvolution technique was developed to convert wire signals to a standard form for hit reconstruction, to remove artifacts in the electronics chain and to remove coherent noise.

Digital Simulation of Closed Loop Zvs-Zcs Bidirectional Dc-Dc Converter for Fuel Cell and Battery Application

Directory of Open Access Journals (Sweden)

V. V. Subrahmanya Kumar Bhajana

2010-08-01

Full Text Available A closed loop ZVS-ZCS bidirectional dc-dc converter is modeled and appropriate digital simulations are provided. With the ZVS-ZCS concept, the MATLAB simulation results of application to a fuel cell and battery application have been obtained whenever the input voltage exceeds the given 24V, at that time the load voltage will change from 180V to 230V. But due to this usage the load is disturbed and there is instability in the model. Using closed loop the output voltage is stabilized.

Digital device for synchronous storage

International Nuclear Information System (INIS)

Kobzar', Yu.M.; Kovtun, V.G.; Pashechko, N.I.

1991-01-01

Synchronous storage digital device for IR electron-photon emission spectrometer operating with analogue-to-digital converter F4223 or monocrystal converter K572PV1 is described. The device accomplished deduction of noise-background in each storage cycle. Summation and deduction operational time equals 90 ns, device output code discharge - 20, number of storages -2 23

Statistical Properties and Pre-Hit Dynamics of Price Limit Hits in the Chinese Stock Markets

Science.gov (United States)

Wan, Yu-Lei; Xie, Wen-Jie; Gu, Gao-Feng; Jiang, Zhi-Qiang; Chen, Wei; Xiong, Xiong; Zhang, Wei; Zhou, Wei-Xing

2015-01-01

Price limit trading rules are adopted in some stock markets (especially emerging markets) trying to cool off traders’ short-term trading mania on individual stocks and increase market efficiency. Under such a microstructure, stocks may hit their up-limits and down-limits from time to time. However, the behaviors of price limit hits are not well studied partially due to the fact that main stock markets such as the US markets and most European markets do not set price limits. Here, we perform detailed analyses of the high-frequency data of all A-share common stocks traded on the Shanghai Stock Exchange and the Shenzhen Stock Exchange from 2000 to 2011 to investigate the statistical properties of price limit hits and the dynamical evolution of several important financial variables before stock price hits its limits. We compare the properties of up-limit hits and down-limit hits. We also divide the whole period into three bullish periods and three bearish periods to unveil possible differences during bullish and bearish market states. To uncover the impacts of stock capitalization on price limit hits, we partition all stocks into six portfolios according to their capitalizations on different trading days. We find that the price limit trading rule has a cooling-off effect (object to the magnet effect), indicating that the rule takes effect in the Chinese stock markets. We find that price continuation is much more likely to occur than price reversal on the next trading day after a limit-hitting day, especially for down-limit hits, which has potential practical values for market practitioners. PMID:25874716

High-Performance Data Converters

DEFF Research Database (Denmark)

Steensgaard-Madsen, Jesper

-resolution internal D/A converters are required. Unit-element mismatch-shaping D/A converters are analyzed, and the concept of mismatch-shaping is generalized to include scaled-element D/A converters. Several types of scaled-element mismatch-shaping D/A converters are proposed. Simulations show that, when implemented...... in a standard CMOS technology, they can be designed to yield 100 dB performance at 10 times oversampling. The proposed scaled-element mismatch-shaping D/A converters are well suited for use as the feedback stage in oversampled delta-sigma quantizers. It is, however, not easy to make full use of their potential......-order difference of the output signal from the loop filter's first integrator stage. This technique avoids the need for accurate matching of analog and digital filters that characterizes the MASH topology, and it preserves the signal-band suppression of quantization errors. Simulations show that quantizers...

Time-interpolator

International Nuclear Information System (INIS)

Blok, M. de; Nationaal Inst. voor Kernfysica en Hoge-Energiefysica

1990-01-01

This report describes a time-interpolator with which time differences can be measured using digital and analog techniques. It concerns a maximum measuring time of 6.4 μs with a resolution of 100 ps. Use is made of Emitter Coupled Logic (ECL) and analogues of high-frequency techniques. The difficulty which accompanies the use of ECL-logic is keeping as short as possible the mutual connections and closing properly the outputs in order to avoid reflections. The digital part of the time-interpolator consists of a continuous running clock and logic which converts an input signal into a start- and stop signal. The analog part consists of a Time to Amplitude Converter (TAC) and an analog to digital converter. (author). 3 refs.; 30 figs

Digital timing: sampling frequency, anti-aliasing filter and signal interpolation filter dependence on timing resolution

International Nuclear Information System (INIS)

Cho, Sanghee; Grazioso, Ron; Zhang Nan; Aykac, Mehmet; Schmand, Matthias

2011-01-01

The main focus of our study is to investigate how the performance of digital timing methods is affected by sampling rate, anti-aliasing and signal interpolation filters. We used the Nyquist sampling theorem to address some basic questions such as what will be the minimum sampling frequencies? How accurate will the signal interpolation be? How do we validate the timing measurements? The preferred sampling rate would be as low as possible, considering the high cost and power consumption of high-speed analog-to-digital converters. However, when the sampling rate is too low, due to the aliasing effect, some artifacts are produced in the timing resolution estimations; the shape of the timing profile is distorted and the FWHM values of the profile fluctuate as the source location changes. Anti-aliasing filters are required in this case to avoid the artifacts, but the timing is degraded as a result. When the sampling rate is marginally over the Nyquist rate, a proper signal interpolation is important. A sharp roll-off (higher order) filter is required to separate the baseband signal from its replicates to avoid the aliasing, but in return the computation will be higher. We demonstrated the analysis through a digital timing study using fast LSO scintillation crystals as used in time-of-flight PET scanners. From the study, we observed that there is no significant timing resolution degradation down to 1.3 Ghz sampling frequency, and the computation requirement for the signal interpolation is reasonably low. A so-called sliding test is proposed as a validation tool checking constant timing resolution behavior of a given timing pick-off method regardless of the source location change. Lastly, the performance comparison for several digital timing methods is also shown.

Tests of the Monte Carlo simulation of the photon-tagger focal-plane electronics at the MAX IV Laboratory

International Nuclear Information System (INIS)

Preston, M.F.; Myers, L.S.; Annand, J.R.M.; Fissum, K.G.; Hansen, K.; Isaksson, L.; Jebali, R.; Lundin, M.

2014-01-01

Rate-dependent effects in the electronics used to instrument the tagger focal plane at the MAX IV Laboratory were recently investigated using the novel approach of Monte Carlo simulation to allow for normalization of high-rate experimental data acquired with single-hit time-to-digital converters (TDCs). The instrumentation of the tagger focal plane has now been expanded to include multi-hit TDCs. The agreement between results obtained from data taken using single-hit and multi-hit TDCs demonstrate a thorough understanding of the behavior of the detector system

Tests of the Monte Carlo simulation of the photon-tagger focal-plane electronics at the MAX IV Laboratory

Energy Technology Data Exchange (ETDEWEB)

Preston, M.F. [Lund University, SE-221 00 Lund (Sweden); Myers, L.S. [Duke University, Durham, NC 27708 (United States); Annand, J.R.M. [University of Glasgow, Glasgow G12 8QQ, Scotland (United Kingdom); Fissum, K.G., E-mail: kevin.fissum@nuclear.lu.se [Lund University, SE-221 00 Lund (Sweden); Hansen, K.; Isaksson, L. [MAX IV Laboratory, Lund University, SE-221 00 Lund (Sweden); Jebali, R. [Arktis Radiation Detectors Limited, 8045 Zürich (Switzerland); Lundin, M. [MAX IV Laboratory, Lund University, SE-221 00 Lund (Sweden)

2014-04-21

Rate-dependent effects in the electronics used to instrument the tagger focal plane at the MAX IV Laboratory were recently investigated using the novel approach of Monte Carlo simulation to allow for normalization of high-rate experimental data acquired with single-hit time-to-digital converters (TDCs). The instrumentation of the tagger focal plane has now been expanded to include multi-hit TDCs. The agreement between results obtained from data taken using single-hit and multi-hit TDCs demonstrate a thorough understanding of the behavior of the detector system.

Successfully converting mine maps to CAD

Energy Technology Data Exchange (ETDEWEB)

Munn, M.D. (Image Conversion Services, Inc., Salt Lake City, UT (USA))

1991-03-01

Procedures followed by computer service bureaus to convert paper drawing to digital files that can be used by CAD systems are described. The conversion involves laser scanning of original drawings to produce an 'inactive image' (a form suitable for many drawings that do not need to be changed). Using optical character recognition software the image is then vectorized or converted from raster format to geometric elements usable in a CAD system. The vectorized image can then be cleaned up corrected and changed at the CAD workstation. 4 figs.

Neutron time-of-flight ion temperature diagnostic for inertial confinement fusion experiments

International Nuclear Information System (INIS)

Chrien, R.E.; Simmons, D.F.; Holmberg, D.L.

1992-01-01

We are constructing a T i diagnostic for low neutron yield (5 x 10 7 to above 10 9 ) d-d and d-t targets in the Nova facility at Livermore. The diagnostic measures the neutron energy spread with 960 scintillator-photomultiplier detectors located 28 m from the target and operates in the single-hit mode. Each detector can measure a single neutron arrival with time resolution of 1 ns or better. The arrival time distribution is constructed from the results of typically 200--500 detector measurements. The ion temperature is determined from the spread in neutron energy ΔE n ∝ T i 1/2 , which is related to the arrival time spread by Δt/t = 1(1/2 ΔE n /E n ). Each neutron arrival is detected by using a photomultiplier tube to observe the recoil proton from elastic scattering in a fast plastic scintillator. The timing electronics for each channel consist of a novel constant fraction-like discriminator and a multiple hit time-to-digital converter (TDC). The overall system design, together with single channel performance data, is presented

A low-power 10-bit continuous-time CMOS ΣΔ A/D converter

DEFF Research Database (Denmark)

Nielsen, Jannik Hammel; Bruun, Erik

2004-01-01

This paper presents the design of a third-order low-pass ΣΔ analog-to-digital converter (ADC) employing a continuous-time (CT) loop filter. The loop filter is implemented using Gm - C integrators, where the transconductors are implemented using CMOS transistors only. System level as well...... as transistor level design issues for power efficiency is discussed. A prototype ΣΔ ADC intended for weak biological signals restricted to bandwidths below 4 kHz has been manufactured in a standard 0.35 μm CMOS technology. The ADC has a measured resolution of 10 bits and a dynamic range (DR) of 67 d...

Thermal heat-balance mode flow-to-frequency converter

Science.gov (United States)

Pawlowski, Eligiusz

2016-11-01

This paper presents new type of thermal flow converter with the pulse frequency output. The integrating properties of the temperature sensor have been used, which allowed for realization of pulse frequency modulator with thermal feedback loop, stabilizing temperature of sensor placed in the flowing medium. The system assures balancing of heat amount supplied in impulses to the sensor and heat given up by the sensor in a continuous way to the flowing medium. Therefore the frequency of output impulses is proportional to the heat transfer coefficient from sensor to environment. According to the King's law, the frequency of those impulses is a function of medium flow velocity around the sensor. The special feature of presented solution is total integration of thermal sensor with the measurement signal conditioning system. Sensor and conditioning system are not the separate elements of the measurement circuit, but constitute a whole in form of thermal heat-balance mode flow-to-frequency converter. The advantage of such system is easiness of converting the frequency signal to the digital form, without using any additional analogue-to-digital converters. The frequency signal from the converter may be directly connected to the microprocessor input, which with use of standard built-in counters may convert the frequency into numerical value of high precision. Moreover, the frequency signal has higher resistance to interference than the voltage signal and may be transmitted to remote locations without the information loss.

Ultra-fast analog-to-digital converter based on a nonlinear triplexer and an optical coder with a photonic crystal structure.

Science.gov (United States)

Mehdizadeh, Farhad; Soroosh, Mohammad; Alipour-Banaei, Hamed; Farshidi, Ebrahim

2017-03-01

In this paper, we propose what we believe is a novel all-optical analog-to-digital converter (ADC) based on photonic crystals. The proposed structure is composed of a nonlinear triplexer and an optical coder. The nonlinear triplexer is for creating discrete levels in the continuous optical input signal, and the optical coder is for generating a 2-bit standard binary code out of the discrete levels coming from the nonlinear triplexer. Controlling the resonant mode of the resonant rings through optical intensity is the main objective and working mechanism of the proposed structure. The maximum delay time obtained for the proposed structure was about 5 ps and the total footprint is about 1520  μm2.

Digital positron lifetime: the influence of noise

International Nuclear Information System (INIS)

Krille, Arnold; Krause-Rehberg, Reinhard; Anwand, Wolfgang

2011-01-01

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

Digital positron lifetime: the influence of noise

Energy Technology Data Exchange (ETDEWEB)

Krille, Arnold; Krause-Rehberg, Reinhard [Department of Physics, Martin-Luther-University Halle-Wittenberg, 06099 Halle (Germany); Anwand, Wolfgang, E-mail: arnold.krille@physik.uni-halle.de [Institute of Ion Beam Physics, Research Center Dresden-Rossendorf, 01314 Dresden (Germany)

2011-01-10

In contrast to the world around where everything seems to go digital as soon as possible, positron lifetime spectrometers are kind of a 'last sanctuary' for analog measurements. Only a few of the newer spectrometers use the analog-digital-converters directly after the photomultipliers and extract the timing information via computer. Judging from their results it seems as if the current available converters and the timing mathematics are only as good as the conventional analog setup in the timing resolution. As it is decided that EPOS [1] will use digital positron lifetime, we try to find some reasons for limited timing resolution by simulating anode pulses from the photomultipliers and measuring the FWHM. We create pulses similar to current state-of-the-art 4GS/s digitizers but can control the level of noise and the bit-depth independently. We found that especially the noise (that would come from the analog electronics in/before the converters) has a great influence on the timing resolution. Also we try to use lowpass filtering to reduce that influence with great success.

Constructive Technology Assessment for HIT development

DEFF Research Database (Denmark)

Høstgaard, Anna Marie Balling; Bertelsen, Pernille; Petersen, Lone Stub

2013-01-01

Experience and time has shown a need for new evaluation methods for evaluating Health Information Technology (HIT), as summative evaluation methods fail to accommodate the rapid and constant changes in HIT over time and to involve end-users, which has been recognized as an important success facto...... during all the phases in the process. Thereby anumber of problems were prevented to occur later on.Thus, the CTA method and its framework are useful for evaluators and project-management in order to facilitate and support successful HIT development....

State-plane trajectories used to observe and control the behavior of a voltage step-up dc-to-dc converter

Science.gov (United States)

Burns, W. W., III; Wilson, T. G.

1976-01-01

State-plane analysis techniques are employed to study the voltage step up energy storage dc-to-dc converter. Within this framework, an example converter operating under the influence of a constant on time and a constant frequency controller is examined. Qualitative insight gained through this approach is used to develop a conceptual free running control law for the voltage step up converter which can achieve steady state operation in one on/off cycle of control. Digital computer simulation data is presented to illustrate and verify the theoretical discussions presented.

Statistics of hits to bone cell nuclei

International Nuclear Information System (INIS)

Kruglikov, I.L.; Polig, E.; Jee, W.S.S.

1993-01-01

The statistics of hits to the nuclei of bone cells irradiated from alpha sources labeling bone tissue is described. It is shown that the law of remodeling of a bone structural unit (BSU), which describes the distribution of quiescence periodes of this unit, affects the statistics of hits. It the irradiation of bone cells occurs during the whole cell cycle, the mean number of hits is independent of the law of remodeling. In this case the variance of hits has the minimum value for constant quiescence periods of BSUs (deterministic remodeling) and the maximum value for exponentially distributed quiescence periods (random remodeling). For the first generation of bone cells, i.e. for the cells which existed at the moment of the uptake of the nuclide, the mean number of hits depends on the law of remodeling. For random remodeling the mean number is equal to the mean value for the complete remodeling cycle. For deterministic remodeling the mean is only half this value. For the first generation of bone cells, changing the law of remodeling from random to deterministic increases the probability of no hits to the nuclei of bone cells. For the same mean value of hits, the difference does not exceed 13.3% of the total number of cells. For the subsequent generations of bone cells, such a change of the law of remodeling decreases the probability of no hits up to 20.4% of the total number of cells. (orig.)

47 CFR 15.122 - Closed caption decoder requirements for digital television receivers and converter boxes.

Science.gov (United States)

2010-10-01

... 47 Telecommunication 1 2010-10-01 2010-10-01 false Closed caption decoder requirements for digital television receivers and converter boxes. 15.122 Section 15.122 Telecommunication FEDERAL COMMUNICATIONS... code spaces C2, C3, and G3 is optional. All unsupported graphic symbols in the G3 code space are to be...

A standardized way to select, evaluate, and test an analog-to-digital converter for ultrawide bandwidth radiofrequency signals based on user's needs, ideal, published,and actual specifications

Science.gov (United States)

Chang, Daniel Y.; Rowe, Neil C.

2012-06-01

The most important adverse impact on the Electronic Warfare (EW) simulation is that the number of signal sources that can be tested simultaneously is relatively small. When the number of signal sources increases, the analog hardware, complexity and costs grow by the order of N2, since the number of connections among N components is O(N*N) and the signal communication is bi-directional. To solve this problem, digitization of the signal is suggested. In digitizing a radiofrequency signal, an Analog-to-Digital Converter (ADC) is widely used. Most research studies on ADCs are conducted from designer/test engineers' perspective. Some research studies are conducted from market's perspective. This paper presents a generic way to select, evaluate and test ultra high bandwidth COTS ADCs and generate requirements for digitizing continuous time signals from the perspective of user's needs. Based on user's needs, as well as vendor's published, ideal and actual specifications, a decision can be made in selecting a proper ADC for an application. To support our arguments and illustrate the methodology, we evaluate a Tektronix TADC-1000, an 8-bit and 12 gigasamples per second ADC. This project is funded by JEWEL lab, NAWCWD at Point Mugu, CA.

Demonetization to Digitalization: A Step Toward Progress

Directory of Open Access Journals (Sweden)

Harshita Bhatnagar

2017-05-01

Full Text Available Journey from demonetization to digitalization is very hard hitting but not impossible. Recent demonetization in India on November 8, 2016, created lot of panic in the economy but also paved the way to digitalization. Cash crunch and availability of e-sources of transactions compelled many people to use electronic modes of payment. Credit cards, debit cards/RuPay card, USSD/UPI, Internet banking, mobile wallets like Oxigen, Paytm, Mobiwik, aadhar-enabled payment system, POS, and so on are few popular modes of electronic transaction, which are commonly used by the citizen. Digitalization will embrace higher transparency in monetary terms; low-cost maintenance; more convenience in use; and help in financial inclusion and weeding out black money and counterfeit money from the economy. But journey to a destination is always full of roadblocks, and similarly the journey of India toward a digital India is also full of hurdles like a huge illiteracy rate; low bandwidth; more unbanked areas; late adoption of technology; lack of full-time electricity; security concerns like hacking, cybercrime, and safety of personal details; and need for high investments. So, to defend the dream of a digital India, we have to develop well-defined strategies to coach people in using technology like focusing on customer education as well as employee education in technology by conducting workshops, presentations, enforcing strict cyber laws, use of local language, and developing user-friendly websites that leverage technology using the development of simple and smart digital tools, such as the use of a one-time password (OTP. The government has started Vittiya Sakharata Abhiyaan (VISAKA and outreach campaigns like DigiDhan Abhiyan and so on to encourage people to adopt digital tools. Overall demonetization is greasing the wheels of digitalization and transforming India into Digital India.

A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

International Nuclear Information System (INIS)

Iguchi, Kyosuke; Matsuoka, Ayako

2014-01-01

One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2 −13.3  of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nT rms  at 0.1–10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket. (paper)

A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

Science.gov (United States)

Iguchi, Kyosuke; Matsuoka, Ayako

2014-07-01

One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2-13.3 of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nTrms at 0.1-10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket.

Grid converter for LED based intelligent light sources

DEFF Research Database (Denmark)

Török, Lajos

The purpose of this thesis was to investigate the applicability and effects of digital control to line connected switched mode power supplies with power factor correction. The main approach was cost effectiveness with high efficiency. This involved hardware design for increased switching frequency...... and their implemented control algorithms. As digital control has to be competitive with the existing solutions it was investigated what digital signal processing solutions exist. A performance and cost comparison was also presented. The chosen converter topologies were thoroughly analyzed. Different converters were...... chosen for different power levels. At low power simple boost converter as power factor corrector (PFC) and a RCD-clamped forward converter was chosen as DC-DC converter. This with has double output and coupled lter inductor. To design a digital controller with the tools of the classical control theory...

High frequency, high time resolution time-to-digital converter employing passive resonating circuits.

Science.gov (United States)

Ripamonti, Giancarlo; Abba, Andrea; Geraci, Angelo

2010-05-01

A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed.

High frequency, high time resolution time-to-digital converter employing passive resonating circuits

International Nuclear Information System (INIS)

Ripamonti, Giancarlo; Abba, Andrea; Geraci, Angelo

2010-01-01

A method for measuring time intervals accurate to the picosecond range is based on phase measurements of oscillating waveforms synchronous with their beginning and/or end. The oscillation is generated by triggering an LC resonant circuit, whose capacitance is precharged. By using high Q resonators and a final active quenching of the oscillation, it is possible to conjugate high time resolution and a small measurement time, which allows a high measurement rate. Methods for fast analysis of the data are considered and discussed with reference to computing resource requirements, speed, and accuracy. Experimental tests show the feasibility of the method and a time accuracy better than 4 ps rms. Methods aimed at further reducing hardware resources are finally discussed.

Power quality improvement by using multi-pulse AC-DC converters for DC drives: Modeling, simulation and its digital implementation

Directory of Open Access Journals (Sweden)

Mohd Tariq

2014-12-01

Full Text Available The paper presents the modeling, simulation and digital implementation of power quality improvement of DC drives by using multi pulse AC–DC converter. As it is a well-known fact that power quality determines the fitness of electrical power to consumer devices, hence an effort has been made to improve power quality in this work. Simulation and digital implementation with the help of MATLAB/Simulink has been done and results obtained are discussed in detail to verify the theoretical results. The multipulse converter was connected with DC drives and was run at no load condition to find out the transient and steady state performances. FFT analysis has been performed and Total Harmonic Distortion (THD results obtained at different pulses are shown here.

Amplitude-to-code converter for photomultipliers operating at high loadings

International Nuclear Information System (INIS)

Arkhangel'skij, B.V.; Evgrafov, G.N.; Pishchal'nikov, Yu.M.; Shuvalov, R.S.

1982-01-01

An 11-bit amplitude-to-code converter intended for the analysis of photomultiplier pulses under high loadings is described. To decrease the volume of digit electronics in the converter an analog memory on capacities is envisaged. A well-known bridge circuit with diodes on the main carriers is selected as a gating circuit. The gate control is realized by a switching circuit on fast-response transistors with boundary frequency of 1.2-1.5 GHz. The converter main characteristics are given, namely, maximum output signal amplitude equal to -1.5 V, minimum pulse selection duration of 10 ns, maximum number of counts at Usub(input)=-1.0 V and tsub(selection)=50 ns amounting to 1400, integral nonlinearity of +-0.1%, conversion temperature instability of 0.2%/deg C in the temperature range of (+10-+40) deg C, maximum time of data storage equal to 300 ms, conversion coefficient instability of 0.42 counts, number of channels in a unit CAMAC block equal to 12

Simulation of continuously logical base cells (CL BC) with advanced functions for analog-to-digital converters and image processors

Science.gov (United States)

Krasilenko, Vladimir G.; Lazarev, Alexander A.; Nikitovich, Diana V.

2017-10-01

The paper considers results of design and modeling of continuously logical base cells (CL BC) based on current mirrors (CM) with functions of preliminary analogue and subsequent analogue-digital processing for creating sensor multichannel analog-to-digital converters (SMC ADCs) and image processors (IP). For such with vector or matrix parallel inputs-outputs IP and SMC ADCs it is needed active basic photosensitive cells with an extended electronic circuit, which are considered in paper. Such basic cells and ADCs based on them have a number of advantages: high speed and reliability, simplicity, small power consumption, high integration level for linear and matrix structures. We show design of the CL BC and ADC of photocurrents and their various possible implementations and its simulations. We consider CL BC for methods of selection and rank preprocessing and linear array of ADCs with conversion to binary codes and Gray codes. In contrast to our previous works here we will dwell more on analogue preprocessing schemes for signals of neighboring cells. Let us show how the introduction of simple nodes based on current mirrors extends the range of functions performed by the image processor. Each channel of the structure consists of several digital-analog cells (DC) on 15-35 CMOS. The amount of DC does not exceed the number of digits of the formed code, and for an iteration type, only one cell of DC, complemented by the device of selection and holding (SHD), is required. One channel of ADC with iteration is based on one DC-(G) and SHD, and it has only 35 CMOS transistors. In such ADCs easily parallel code can be realized and also serial-parallel output code. The circuits and simulation results of their design with OrCAD are shown. The supply voltage of the DC is 1.8÷3.3V, the range of an input photocurrent is 0.1÷24μA, the transformation time is 20÷30nS at 6-8 bit binary or Gray codes. The general power consumption of the ADC with iteration is only 50÷100μW, if the

Heparin-independent, PF4-dependent binding of HIT antibodies to platelets: implications for HIT pathogenesis.

Science.gov (United States)

Padmanabhan, Anand; Jones, Curtis G; Bougie, Daniel W; Curtis, Brian R; McFarland, Janice G; Wang, Demin; Aster, Richard H

2015-01-01

Antibodies specific for platelet factor 4 (PF4)/heparin complexes are the hallmark of heparin-induced thrombocytopenia and thrombosis (HIT), but many antibody-positive patients have normal platelet counts. The basis for this is not fully understood, but it is believed that antibodies testing positive in the serotonin release assay (SRA) are the most likely to cause disease. We addressed this issue by characterizing PF4-dependent binding of HIT antibodies to intact platelets and found that most antibodies testing positive in the SRA, but none of those testing negative, bind to and activate platelets when PF4 is present without any requirement for heparin (P HIT antibodies recognize PF4 in a complex with heparin, only a subset of these antibodies recognize more subtle epitopes induced in PF4 when it binds to CS, the major platelet glycosaminoglycan. Antibodies having this property could explain "delayed HIT" seen in some individuals after discontinuation of heparin and the high risk for thrombosis that persists for weeks in patients recovered from HIT. © 2015 by The American Society of Hematology.

Application of digital sampling techniques to particle identification

International Nuclear Information System (INIS)

Bardelli, L.; Poggi, G.; Bini, M.; Carraresi, L.; Pasquali, G.; Taccetti, N.

2003-01-01

An application of digital sampling techniques is presented which can greatly simplify experiments involving sub-nanosecond time-mark determinations and energy measurements with nuclear detectors, used for Pulse Shape Analysis and Time of Flight measurements in heavy ion experiments. In this work a 100 M Sample/s, 12 bit analog to digital converter has been used: examples of this technique applied to Silicon and CsI(Tl) detectors in heavy-ions experiments involving particle identification via Pulse Shape analysis and Time of Flight measurements are presented. The system is suited for applications to large detector arrays and to different kinds of detectors. Some preliminary results regarding the simulation of current signals in Silicon detectors are also discussed. (authors)

Understanding delta-sigma data converters

CERN Document Server

Pavan, Shanti; Temes, Gabor C

2017-01-01

This new edition introduces novel analysis and design techniques for delta-sigma (ΔΣ) converters in physical and conceptual terms, and includes new chapters that explore developments in the field over the last decade. This book explains the principles and operation of delta-sigma analog-to-digital converters (ADCs) in physical and conceptual terms in accordance with the most recent developments in the field. The interest of ΔΣ converter designers has shifted significantly over the past decade, due to many new applications for data converters at the far ends of the frequency spectrum. Continuous-time delta-sigma A/D converters with GHz clocks, of both lowpass and bandpass types, are required for wireless applications. At the other extreme, multiplexed ADCs with very narrow (sometimes 10 Hz wide) signal bandwidths, but very high accuracy are needed in the interfaces of biomedical and environmental sensors. To reflect the changing eeds of designers, the second edition includes significant new material on bo...

A 0.8mW 250MS/s time-interleaved asynchronous digital slope ADC

NARCIS (Netherlands)

Harpe, P.J.A.; Zhou, C.; Philips, K.J.P.; Groot, de H.W.H.

2010-01-01

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a non-oversampled clock, thus enabling a much higher

Reaching a few picosecond timing precision with the 16-channel digitizer and timestamper SAMPIC ASIC

Energy Technology Data Exchange (ETDEWEB)

Delagnes, E., E-mail: eric.delagnes@cea.fr [CEA/IRFU/SEDI, Saclay (France); Breton, D. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France); Grabas, H. [CEA/IRFU/SEDI, Saclay (France); Maalmi, J.; Rusquart, P. [Laboratoire de L’accélérateur Linéaire from CNRS/IN2P3, Centre scientifique d’Orsay, Bâtiment 200, 91898, Orsay, Cedex (France)

2015-07-01

SAMPIC is a Time and Waveform to Digital Converter (TWDC) multichannel chip. It integrates 16 channels each including DLL-based TDC providing a raw time associated with an ultra-fast analog memory sampling the signal used for precise timing measurements as well as other parameters of the pulse. Every channel also integrates a discriminator that can trigger it independently or participate to a more complex trigger. After triggering, the analog samples are digitized by on-chip ADCs and are sent serially to the acquisition. The paper describes the architecture of SAMPIC and reports the main performance measured on the first prototype chip with a focus on timing resolution in the range of 15 ps RMS using raw data improved to less than 5 ps RMS after a simple calibration.

Measurements of timing resolution of ultra-fast silicon detectors with the SAMPIC waveform digitizer

Energy Technology Data Exchange (ETDEWEB)

Breton, D. [CNRS/IN2P3/LAL Orsay, Université Paris-Saclay, F-91898 Orsay (France); De Cacqueray, V.; Delagnes, E. [IRFU, CEA, Université Paris-Saclay, F-91191 Gif-sur-Yvette (France); Grabas, H. [Santa Cruz Institute for Particle Physics UC Santa Cruz, CA 95064 (United States); Maalmi, J. [CNRS/IN2P3/LAL Orsay, Université Paris-Saclay, F-91898 Orsay (France); Minafra, N. [Dipartimento Interateneo di Fisica di Bari, Bari (Italy); CERN, Geneva (Switzerland); Royon, C. [University of Kansas, Lawrence (United States); Saimpert, M., E-mail: matthias.saimpert@cern.ch [IRFU, CEA, Université Paris-Saclay, F-91191 Gif-sur-Yvette (France)

2016-11-01

The SAMpler for PICosecond time (SAMPIC) chip has been designed by a collaboration including CEA/IRFU/SEDI, Saclay and CNRS/LAL/SERDI, Orsay. It benefits from both the quick response of a time to digital converter and the versatility of a waveform digitizer to perform accurate timing measurements. Thanks to the sampled signals, smart algorithms making best use of the pulse shape can be used to improve time resolution. A software framework has been developed to analyse the SAMPIC output data and extract timing information by using either a constant fraction discriminator or a fast cross-correlation algorithm. SAMPIC timing capabilities together with the software framework have been tested using pulses generated by a signal generator or by a silicon detector illuminated by a pulsed infrared laser. Under these ideal experimental conditions, the SAMPIC chip has proven to be capable of timing resolutions down to 4 ps with synthesized signals and 40 ps with silicon detector signals.

Computational Physics' Greatest Hits

Science.gov (United States)

Bug, Amy

2011-03-01

The digital computer, has worked its way so effectively into our profession that now, roughly 65 years after its invention, it is virtually impossible to find a field of experimental or theoretical physics unaided by computational innovation. It is tough to think of another device about which one can make that claim. In the session ``What is computational physics?'' speakers will distinguish computation within the field of computational physics from this ubiquitous importance across all subfields of physics. This talk will recap the invited session ``Great Advances...Past, Present and Future'' in which five dramatic areas of discovery (five of our ``greatest hits'') are chronicled: The physics of many-boson systems via Path Integral Monte Carlo, the thermodynamic behavior of a huge number of diverse systems via Monte Carlo Methods, the discovery of new pharmaceutical agents via molecular dynamics, predictive simulations of global climate change via detailed, cross-disciplinary earth system models, and an understanding of the formation of the first structures in our universe via galaxy formation simulations. The talk will also identify ``greatest hits'' in our field from the teaching and research perspectives of other members of DCOMP, including its Executive Committee.

Improvements to the ion Doppler spectrometer diagnostic on the HIT-SI experiments

Science.gov (United States)

Hossack, Aaron; Chandra, Rian; Everson, Chris; Jarboe, Tom

2018-03-01

An ion Doppler spectrometer diagnostic system measuring impurity ion temperature and velocity on the HIT-SI and HIT-SI3 spheromak devices has been improved with higher spatiotemporal resolution and lower error than previously described devices. Hardware and software improvements to the established technique have resulted in a record of 6.9 μs temporal and ≤2.8 cm spatial resolution in the midplane of each device. These allow Ciii and Oii flow, displacement, and temperature profiles to be observed simultaneously. With 72 fused-silica fiber channels in two independent bundles, and an f/8.5 Czerny-Turner spectrometer coupled to a video camera, frame rates of up to ten times the imposed magnetic perturbation frequency of 14.5 kHz were achieved in HIT-SI, viewing the upper half of the midplane. In HIT-SI3, frame rates of up to eight times the perturbation frequency were achieved viewing both halves of the midplane. Biorthogonal decomposition is used as a novel filtering tool, reducing uncertainty in ion temperature from ≲13 to ≲5 eV (with an instrument temperature of 8-16 eV) and uncertainty in velocity from ≲2 to ≲1 km/s. Doppler shift and broadening are calculated via the Levenberg-Marquardt algorithm, after which the errors in velocity and temperature are uniquely specified. Axisymmetric temperature profiles on HIT-SI3 for Ciii peaked near the inboard current separatrix at ≈40 eV are observed. Axisymmetric plasma displacement profiles have been measured on HIT-SI3, peaking at ≈6 cm at the outboard separatrix. Both profiles agree with the upper half of the midplane observable by HIT-SI. With its complete midplane view, HIT-SI3 has unambiguously extracted axisymmetric, toroidal current dependent rotation of up to 3 km/s. Analysis of the temporal phase of the displacement uncovers a coherent structure, locked to the applied perturbation. Previously described diagnostic systems could not achieve such results.

In-depth study of single photon time resolution for the Philips digital silicon photomultiplier

International Nuclear Information System (INIS)

Liu, Z.; Pizzichemi, M.; Ghezzi, A.; Paganoni, M.; Gundacker, S.; Auffray, E.; Lecoq, P.

2016-01-01

The digital silicon photomultiplier (SiPM) has been commercialised by Philips as an innovative technology compared to analog silicon photomultiplier devices. The Philips digital SiPM, has a pair of time to digital converters (TDCs) connected to 12800 single photon avalanche diodes (SPADs). Detailed measurements were performed to understand the low photon time response of the Philips digital SiPM. The single photon time resolution (SPTR) of every single SPAD in a pixel consisting of 3200 SPADs was measured and an average value of 85 ps full width at half maximum (FWHM) was observed. Each SPAD sends the signal to the TDC with different signal propagation time, resulting in a so called trigger network skew. This distribution of the trigger network skew for a pixel (3200 SPADs) has been measured and a variation of 50 ps FWHM was extracted. The SPTR of the whole pixel is the combination of SPAD jitter, trigger network skew, and the SPAD non-uniformity. The SPTR of a complete pixel was 103 ps FWHM at 3.3 V above breakdown voltage. Further, the effect of the crosstalk at a low photon level has been studied, with the two photon time resolution degrading if the events are a combination of detected (true) photons and crosstalk events. Finally, the time response to multiple photons was investigated.

4-bit digital to analog converter using R-2R ladder and binary weighted resistors

Science.gov (United States)

Diosanto, J.; Batac, M. L.; Pereda, K. J.; Caldo, R.

2017-06-01

The use of a 4-bit digital-to-analog converter using two methods; Binary Weighted Resistors and R-2R Ladder is designed and presented in this paper. The main components that were used in constructing both circuits were different resistor values, operational amplifier (LM741) and single pole double throw switches. Both circuits were designed using MULTISIM software to be able to test the circuit for its ideal application and FRITZING software for the layout designing and fabrication to the printed circuit board. The implementation of both systems in an actual circuit benefits in determining and comparing the advantages and disadvantages of each. It was realized that the binary weighted circuit is more efficient DAC, having lower percentage error of 0.267% compared to R-2R ladder circuit which has a minimum of percentage error of 4.16%.

2 GHz self-aligning tandem A/D converter for SAR

DEFF Research Database (Denmark)

Søbjærg, Sten Schmidl; Christensen, Erik Lintz

2001-01-01

digitizing, and the other is to digitize the signal before digital I/Q demodulation. In both cases the digitizing may be performed by a digital front end (DFE) with two parallel analog-to-digital-converters (ADCs) sampling at 1 GHz in phase or in anti-phase respectively, provided the analog bandwidth...... of the ADC is sufficient. In the first case each ADC has to digitize a 0-400 MHz signal, and in the second case both ADCs have to digitize a 100-900 MHz signal. In both cases the sampling time alignment is a critical parameter. The paper addresses some aspects of ADC alignment in the implementation of a DFE...

Converting Taxonomic Descriptions to New Digital Formats

Directory of Open Access Journals (Sweden)

Hong Cui

2008-01-01

Full Text Available Abstract.--The majority of taxonomic descriptions is currently in print format. The majority of digital descriptions are in formats such as DOC, HTML, or PDF and for human readers. These formats do not convey rich semantics in taxonomic descriptions for computer-aided process. Newer digital formats such as XML and RDF accommodate semantic annotations that allow computers to process the rich semantics on human's behalf, thus open up opportunities for a wide range of innovative usages of taxonomic descriptions, such as searching in more precise and flexible ways, integrating with gnomic and geographic information, generating taxonomic keys automatically, and text data mining and information visualization etc. This paper discusses the challenges in automated conversion of multiple collections of descriptions to XML format and reports an automated system, MARTT. MARTT is a machine-learning system that makes use of training examples to tag new descriptions into XML format. A number of utilities are implemented as solutions to the challenges. The utilities are used to reduce the effort for training example preparation, to facilitate the creation of a comprehensive schema, and to predict system performance on a new collection of descriptions. The system has been tested with several plant and alga taxonomic publications including Flora of China and Flora of North America.

Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes

KAUST Repository

Omran, Hesham

2015-11-01

Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications. However, the sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this dissertation, we propose several energy-efficient CDC architectures for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine multislope CDC that employs both current and frequency scaling to achieve significant improvement in energy efficiency. Second, we analyze the limitations of successive approximation (SAR) CDC, and we address these limitations by proposing a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM) of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent energy efficiency for a scalable sample rate. In the second part of this dissertation, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report mismatch measurements for subfemtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors

Image processing by use of the digital cross-correlator

International Nuclear Information System (INIS)

Katou, Yoshinori

1982-01-01

We manufactured for trial an instrument which achieved the image processing using digital correlators. A digital correlator perform 64-bit parallel correlation at 20 MH. The output of a digital correlator is a 7-bit word representing. An A-D converter is used to quantize it a precision of six bits. The resulting 6-bit word is fed to six correlators, wired in parallel. The image processing achieved in 12 bits, whose digital outputs converted an analog signal by a D-A converter. This instrument is named the digital cross-correlator. The method which was used in the image processing system calculated the convolution with the digital correlator. It makes various digital filters. In the experiment with the image processing video signals from TV camera were used. The digital image processing time was approximately 5 μs. The contrast was enhanced and smoothed. The digital cross-correlator has the image processing of 16 sorts, and was produced inexpensively. (author)

Fast collimated neutron flux measurement using stilbene scintillator and flashy analog-to-digital converter in JT-60U

International Nuclear Information System (INIS)

Ishikawa, M.; Itoga, T.; Okuji, T.; Nakhostin, M.; Shinohara, K.; Hayashi, T.; Sukegawa, A.; Baba, M.; Nishitani, T.

2006-01-01

A line-integrated neutron emission profile is routinely measured using the radial neutron collimator system in JT-60U tokamak. Stilbene neuron detectors (SNDs), which combine a stilbene organic crystal scintillation detector (SD) with an analog neutron-gamma pulse shape discrimination (PSD) circuit, have been used to measure collimated neutron flux. Although the SND has many advantages as a neutron detector, the maximum count rate is limited up to ∼1x10 5 counts/s due to the analog PSD circuit. To overcome this issue, a digital signal processing system (DSPS) using a flash analog-to-digital converter (Acqiris DC252, 8 GHz, 10 bits) has been developed at Cyclotron and Radioisotope Center in Tohoku University. In this system anode signals from photomultiplier of the SD are directory stored and digitized. Then, the PSD between neutrons and gamma rays is performed using software. The DSPS has been installed in the vertical neutron collimator system in JT-60U and applied to deuterium experiments. It is confirmed that the PSD is sufficiently performed and collimated neutron flux is successfully measured with count rate up to ∼5x10 5 counts/s without the effect of pileup of detected pulses. The performance of the DSPS as a neutron detector, which supersedes the SND, is demonstrated

Subpicosecond time-resolution image converter the picochron

International Nuclear Information System (INIS)

Butslov, M.M.; Fanchenko, S.D.; Chikin, R.V.

The problem of X-band resonance ultra-high-speed electron image swept in image converters is considered. A time analysis image converter tube is described. It is provided with a circular image-sweeping system, the sweeping speed ranging from 1 up to 2 light velocities. The swept-image intensifier makes it possible to record every electron emerging from the input photocathode. The time analysis electrostatic lens provides an electronic field at the input photocathode, strong enough to obtain a high physical time resolution. The image sweeping system to be described enables one to have a 5.10 -13 s time resolution over on observation period as long as 5.10 -8 s. It requires no precise limiting with the process to observed. The picochron tube design is described together with some results of its testing in Nd-laser experiments. Transitories as short as 0.5-1psec have been detected in ultra-short laser radiation pulses

Digital control of grid connected converters for distributed power generation

Energy Technology Data Exchange (ETDEWEB)

Skjellnes, Tore

2008-07-01

Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of small scale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid. A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the voltage in response to the output current to create an outward appearance of a source impedance. This is called a virtual impedance. This thesis presents a controller for a voltage controlled three phase pulse width modulated converter. This controller enables operation in standalone mode, in parallel with other converters in a micro grid, and in parallel with a strong main grid. A time varying virtual impedance is presented which mainly attenuates reactive currents. A method of investigating the overall impedance including the virtual impedance is presented. New net standards have been introduced, requiring the converter to operate even during severe dips in the grid voltage. Experiments are presented verifying the operation of the controller during voltage dips. (Author). 37 refs., 65 figs., 10 tabs

Current Controller for Multi-level Front-end Converter and Its Digital Implementation Considerations on Three-level Flying Capacitor Topology

Science.gov (United States)

Tekwani, P. N.; Shah, M. T.

2017-10-01

This paper presents behaviour analysis and digital implementation of current error space phasor based hysteresis controller applied to three-phase three-level flying capacitor converter as front-end topology. The controller is self-adaptive in nature, and takes the converter from three-level to two-level mode of operation and vice versa, following various trajectories of sector change with the change in reference dc-link voltage demanded by the load. It keeps current error space phasor within the prescribed hexagonal boundary. During the contingencies, the proposed controller takes the converter in over modulation mode to meet the load demand, and once the need is satisfied, controller brings back the converter in normal operating range. Simulation results are presented to validate behaviour of controller to meet the said contingencies. Unity power factor is assured by proposed controller with low current harmonic distortion satisfying limits prescribed in IEEE 519-2014. Proposed controller is implemented using TMS320LF2407 16-bit fixed-point digital signal processor. Detailed analysis of numerical format to avoid overflow of sensed variables in processor, and per-unit model implementation in software are discussed and hardware results are presented at various stages of signal conditioning to validate the experimental setup. Control logic for the generation of reference currents is implemented in TMS320LF2407A using assembly language and experimental results are also presented for the same.

AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION

International Nuclear Information System (INIS)

O CONNOR, P.; DE GERONIMO, G.; KANDASAMY, A.

2002-01-01

We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates

Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators

Directory of Open Access Journals (Sweden)

Per Löwenborg

2008-02-01

Full Text Available A general formulation based on multirate filterbank theory for analog-to-digital converters using parallel sigmadelta modulators in conjunction with modulation sequences is presented. The time-interleaved modulators (TIMs, Hadamard modulators (HMs, and frequency-band decomposition modulators (FBDMs can be viewed as special cases of the proposed description. The usefulness of the formulation stems from its ability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. Both Nyquist-rate and oversampled systems are considered, and it is shown how the matching requirements between channels can be reduced for oversampled systems. The new formulation is useful also for the derivation of new modulation schemes, and an example is given of how it can be used in this context.

Digitizing paper: the paradoxes of time in digital books

DEFF Research Database (Denmark)

Ebbesen, Toke Riis

In this paper I will analyze three contemporary danish examples of digital book distribution formats in terms of how they are designed with special attention to their use of time. Even though reading digital media in general are often framed in relation to time with notions such as the immediacy...... multiple times in the present, enmeshed in the digital books themselves or in their discourse. Either they look to the past through the use of nostalgia, retro, and appraisals of tradition (Baker, 2013), or to the future, through futuristic calls for renewal through radical design proposals, utopian...... of the present, compression of time (and space) (Virillio), and built-in oblivion(Augé, 1995), connected to moralizing notions of shallowness, restlessness and diseases such as stress (Carr, 2010). I will content, however, that the design of these digital formats – their typography, covers and external...

A 12-bit spectroscopy analog-to-digital converter type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT

International Nuclear Information System (INIS)

Borsuk, S.; Kulka, Z.

1989-12-01

A 12-bit spectroscopy analog-to-digital converter (ADC) type SAA (Successive Approximation type with channel width Averaging) intended for multichannel pulse height analyzer SWAN-1 based on IBM PC/XT/AT has been described. Design principles, specifications and measurements of a fundamental SAA-2 converter version are reported. Finally, two next versions of the converter with introduced modifications are discussed. 6 refs., 7 figs. (author)

42 CFR 495.344 - Approval of the State Medicaid HIT plan, the HIT PAPD and update, the HIT IAPD and update, and...

Science.gov (United States)

2010-10-01

... 42 Public Health 5 2010-10-01 2010-10-01 false Approval of the State Medicaid HIT plan, the HIT PAPD and update, the HIT IAPD and update, and the annual HIT IAPD. 495.344 Section 495.344 Public... Requirements Specific to the Medicaid Program § 495.344 Approval of the State Medicaid HIT plan, the HIT PAPD...

Database for High Throughput Screening Hits (dHITS): a simple tool to retrieve gene specific phenotypes from systematic screens done in yeast.

Science.gov (United States)

Chuartzman, Silvia G; Schuldiner, Maya

2018-03-25

In the last decade several collections of Saccharomyces cerevisiae yeast strains have been created. In these collections every gene is modified in a similar manner such as by a deletion or the addition of a protein tag. Such libraries have enabled a diversity of systematic screens, giving rise to large amounts of information regarding gene functions. However, often papers describing such screens focus on a single gene or a small set of genes and all other loci affecting the phenotype of choice ('hits') are only mentioned in tables that are provided as supplementary material and are often hard to retrieve or search. To help unify and make such data accessible, we have created a Database of High Throughput Screening Hits (dHITS). The dHITS database enables information to be obtained about screens in which genes of interest were found as well as the other genes that came up in that screen - all in a readily accessible and downloadable format. The ability to query large lists of genes at the same time provides a platform to easily analyse hits obtained from transcriptional analyses or other screens. We hope that this platform will serve as a tool to facilitate investigation of protein functions to the yeast community. © 2018 The Authors Yeast Published by John Wiley & Sons Ltd.

38 CFR 1.893 - Establishing and converting part-time positions.

Science.gov (United States)

2010-07-01

... converting part-time positions. 1.893 Section 1.893 Pensions, Bonuses, and Veterans' Relief DEPARTMENT OF VETERANS AFFAIRS GENERAL PROVISIONS Part-Time Career Employment Program § 1.893 Establishing and converting part-time positions. Position management and other internal reviews may indicate that positions may be...

22 CFR 506.3 - Establishing and converting part-time positions.

Science.gov (United States)

2010-04-01

... 22 Foreign Relations 2 2010-04-01 2010-04-01 true Establishing and converting part-time positions. 506.3 Section 506.3 Foreign Relations BROADCASTING BOARD OF GOVERNORS PART-TIME CAREER EMPLOYMENT PROGRAM § 506.3 Establishing and converting part-time positions. Position management and other internal...

45 CFR 1176.4 - Establishing and converting part-time positions.

Science.gov (United States)

2010-10-01

... 45 Public Welfare 3 2010-10-01 2010-10-01 false Establishing and converting part-time positions... FOUNDATION ON THE ARTS AND THE HUMANITIES NATIONAL ENDOWMENT FOR THE HUMANITIES PART-TIME CAREER EMPLOYMENT § 1176.4 Establishing and converting part-time positions. Position management and other internal reviews...

Research on Parallel Three Phase PWM Converters base on RTDS

Science.gov (United States)

Xia, Yan; Zou, Jianxiao; Li, Kai; Liu, Jingbo; Tian, Jun

2018-01-01

Converters parallel operation can increase capacity of the system, but it may lead to potential zero-sequence circulating current, so the control of circulating current was an important goal in the design of parallel inverters. In this paper, the Real Time Digital Simulator (RTDS) is used to model the converters parallel system in real time and study the circulating current restraining. The equivalent model of two parallel converters and zero-sequence circulating current(ZSCC) were established and analyzed, then a strategy using variable zero vector control was proposed to suppress the circulating current. For two parallel modular converters, hardware-in-the-loop(HIL) study based on RTDS and practical experiment were implemented, results prove that the proposed control strategy is feasible and effective.

Clinical Digital Libraries Project: design approach and exploratory assessment of timely use in clinical environments.

Science.gov (United States)

Maccall, Steven L

2006-04-01

The paper describes and evaluates the use of Clinical Digital Libraries Project (CDLP) digital library collections in terms of their facilitation of timely clinical information seeking. A convenience sample of CDLP Web server log activity over a twelve-month period (7/2002 to 6/2003) was analyzed for evidence of timely information seeking after users were referred to digital library clinical topic pages from Web search engines. Sample searches were limited to those originating from medical schools (26% North American and 19% non-North American) and from hospitals or clinics (51% North American and 4% non-North American). Timeliness was determined based on a calculation of the difference between the timestamps of the first and last Web server log "hit" during each search in the sample. The calculated differences were mapped into one of three ranges: less than one minute, one to three minutes, and three to five minutes. Of the 864 searches analyzed, 48% were less than 1 minute, 41% were 1 to 3 minutes, and 11% were 3 to 5 minutes. These results were further analyzed by environment (medical schools versus hospitals or clinics) and by geographic location (North America versus non-North American). Searches reflected a consistent pattern of less than 1 minute in these environments. Though the results were not consistent on a month-by-month basis over the entire time period, data for 8 of 12 months showed that searches shorter than 1 minute predominated and data for 1 month showed an equal number of less than 1 minute and 1 to 3 minute searches. The CDLP digital library collections provided timely access to high-quality Web clinical resources when used for information seeking in medical education and hospital or clinic environments from North American and non-North American locations and consistently provided access to the sought information within the documented two-minute standard. The limitations of the use of Web server data warrant an exploratory assessment. This

Investigations in a drift chamber using 250 MHz analogue-digital-converters

International Nuclear Information System (INIS)

Scharf, F.A.

1993-06-01

The performance of a new 250 MHz FADC module was investigated in a small drift chamber system. Straight tracks were induced in the chamber volume by UV-LASER beams. The time resolution was determined from drift time measurements for four neighbouring signal wires. By use of a beam splitter a pair of parallel beams was produced. An appropriate rotation of this pair relative to the signal wire plane allowed the determination of the double hit resolution. A comparison of the obtained values with the results achieved with 100 MHz FADC modules showed that the new module is well suited for chamber read out. The attainable improvements however are small. (orig.) [de

Experimental demonstration of a real-time high-throughput digital DC blocker for compensating ADC imperfections in optical fast-OFDM receivers.

Science.gov (United States)

Zhang, Lu; Ouyang, Xing; Shao, Xiaopeng; Zhao, Jian

2016-06-27

Performance degradation induced by the DC components at the output of real-time analogue-to-digital converter (ADC) is experimentally investigated for optical fast-OFDM receiver. To compensate this degradation, register transfer level (RTL) circuits for real-time digital DC blocker with 20GS/s throughput are proposed and implemented in field programmable gate array (FPGA). The performance of the proposed real-time digital DC blocker is experimentally investigated in a 15Gb/s optical fast-OFDM system with intensity modulation and direct detection over 40 km standard single-mode fibre. The results show that the fixed-point DC blocker has negligible performance penalty compared to the offline floating point one, and can overcome the error floor of the fast OFDM receiver caused by the DC components from the real-time ADC output.

A digital instantaneous frequency measurement technique utilising high speed analogue to digital converters and field programmable gate arrays

CSIR Research Space (South Africa)

Herselman, PLR

2007-09-01

Full Text Available In modern information and sensor systems, the timely estimation of the carrier frequency of received signals is of critical importance. This paper presents a digital instantaneous frequency measurement (DIFM) technique, which can measure the carrier...

Resonant power converter comprising adaptive dead-time control

DEFF Research Database (Denmark)

2017-01-01

The invention relates in a first aspect to a resonant power converter comprising: a first power supply rail for receipt of a positive DC supply voltage and a second power supply rail for receipt of a negative DC supply voltage. The resonant power converter comprises a resonant network with an input...... terminal for receipt of a resonant input voltage from a driver circuit. The driver circuit is configured for alternatingly pulling the resonant input voltage towards the positive and negative DC supply voltages via first and second semiconductor switches, respectively, separated by intervening dead......-time periods in accordance with one or more driver control signals. A dead-time controller is configured to adaptively adjusting the dead-time periods based on the resonant input voltage....

A 0.8mW 5bit 250MS/s time-interleaved asynchronous digital slope ADC

NARCIS (Netherlands)

Harpe, P.J.A.; Zhou, C.; Philips, K.J.P.; Groot, de H.W.H.

2011-01-01

Slope and digital-ramp converters are normally limited to very low sampling rates, since they require a digital counter at a highly oversampled clock rate. In this work, an asynchronous digital slope architecture is introduced that only requires a nonoversampled clock, thus enabling a much higher

High Performance Low Cost Digitally Controlled Power Conversion Technology

DEFF Research Database (Denmark)

Jakobsen, Lars Tønnes

2008-01-01

in order to reduce the power consumption of servers and datacenters. The work presented in this thesis includes digital control methods for switch-mode converters implemented in microcontrollers, digital signal controllers and field programmable gate arrays. Microcontrollers are cheap devices that can...... be used for real-time control of switch-mode converters. Software design in the assembly language of the microcontroller is important because of the limited resources of the microcontroller. Microcontrollers are best suited for power electronics applications with low bandwidth requirements because...... the execution time of the software algorithm that realises the digital control law will constitute a considerable delay in the control loop. Digital signal controllers are powerful devices capable of performing arithmetic functions much faster than a microcontroller can. Digital signal controllers are well...

Computer Simulation of Phase Shifted Series Resonant DC to DC Converter

Directory of Open Access Journals (Sweden)

P. PARVATHY

2016-01-01

Full Text Available This paper deals with digital simulation of phase shifted series resonant DC to DC converter using Matlab Simulink. The Simulink models for open loop and closed loop systems are developed and they are used for simulation studies. This converter is capable of producing ripple free DC output. Switching losses and switching stresses are reduced by using soft switching. This converter has advantages like high power density and low switching losses. Theoretical predictions are well supported by the simulation results.

Digital Control of a High Voltage (2.5 kV) Bidirectional Flyback DC-DC Converter for Driving a Capacitive Incremental Actuator

DEFF Research Database (Denmark)

Thummala, Prasanth; Maksimovic, Dragan; Zhang, Zhe

2016-01-01

This paper presents a digital control technique to achieve valley switching in a bidirectional flyback converter used to drive a dielectric electro-active polymer based capacitive incremental actuator. The paper also provides the design of a low input voltage (24 V) and variable high output voltage...... on the output high-voltage (HV) side. Experimental results verifying the bidirectional operation of a high voltage flyback converter are presented, using a 3 kV polypropylene film capacitor as the load. The energy loss distributions of the converter when 4 kV and 4.5 kV HV MOSFETs are used on HV side...

Hitting your foothills target the first time

Energy Technology Data Exchange (ETDEWEB)

Ewanek, J. [MI Drilling Fluids Canada, Calgary, AB (Canada); Young, S. [M-I L.L.C., Calgary, AB (Canada)

2001-07-01

As the demand for gas increases, operators are exploring for more long-term gas reserves in the foothills and in more complex structural traps and reservoirs. The high tectonic activity in the foothills has rendered the structural geology complex, making it difficult to hit an exploration target the first time. Costly sidetracking operations are common. The use of oil based fluids is often necessary for drilling in such technically challenging environments. However, dips/structural evaluation tools such as the Formation Micro Imager (FMI) and the GeoVision 675 Logging While Drilling (LWD) tool cannot be used because of the non-conductive nature of oil based fluids. Therefore, a conductive oil based fluid was developed with the recent advances in oil based mud technology, and it is now available. This new conductive oil based fluid allows LWD tools to transmit structural information in real time and FMI logs to give detailed structural information while wireline logging the hole. The combination of LWD and FMI data plus a conductive oil based fluid makes it possible to gather better structural information while drilling. This minimizes sidetracks and leads to a better understanding of the structural geology in that field. It was concluded that the use of this technology well enable better pre-planning on future well sites and will make it possible to reduce costs associated with drilling and oilfield operations in the foothills. 9 refs., 2 tabs., 13 figs.

Fast digital recorders of signal shaping

International Nuclear Information System (INIS)

Meleshko, E.A.

1997-01-01

Methodology of fast digital registration and pulse signals through fast-action analog-to-digital converters is considered. Systems of digital recorders: sampling and storage devices and operational memory units are described. Main attention is paid to developing parallel analog-to-digital converters, making it possible to bring the conversion frequencies up to several gigahertzes are described. Parallel-sequential analog-to-digital converters, combining high action with increased accuracy are also considered. Concrete examples of designing universal and specialized digital signal recorders, applied in experimental physics, are presented. 44 refs., 12 figs

77 FR 32639 - HIT Standards Committee and HIT Policy Committee; Call for Nominations

Science.gov (United States)

2012-06-01

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee and HIT Policy Committee; Call for... Health Information Technology Policy Committee (HITPC). Name of Committees: HIT Standards Committee and HIT Policy Committee. General Function of the Committees: The HITSC is charged to provide...

NIMROD Simulations of the HIT-SI and HIT-SI3 Devices

Science.gov (United States)

Morgan, Kyle; Jarboe, Tom; Hossack, Aaron; Chandra, Rian; Everson, Chris

2017-10-01

The Helicity Injected Torus with Steady Inductive helicity injection (HIT-SI) experiment uses a set of inductively driven helicity injectors to apply non-axisymmetric current drive on the edge of the plasma, driving an axisymmetric spheromak equilibrium in a central confinement volume. Significant improvements have been made to extended MHD modeling of HIT-SI, with both the resolution of disagreement at high injector frequencies in HIT-SI in addition to successes with the new upgraded HIT-SI3 device. Previous numerical studies of HIT-SI, using a zero-beta eMHD model, focused on operations with a drive frequency of 14.5 kHz, and found reduced agreement with both the magnetic profile and current amplification at higher frequencies (30-70 kHz). HIT-SI3 has three helicity injectors which are able to operate with different mode structures of perturbations through the different relative temporal phasing of the injectors. Simulations that allow for pressure gradients have been performed in the parameter regimes of both devices using the NIMROD code and show improved agreement with experimental results, most notably capturing the observed Shafranov-shift due to increased beta observed at higher finj in HIT-SI and the variety of toroidal perturbation spectra available in HIT-SI3. This material is based upon work supported by the U.S. Department of Energy, Office of Science, Office of Fusion Energy Sciences under Award Number DE-FG02- 96ER54361.

76 FR 46297 - HIT Standards Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-08-02

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Standards Committee's... developed by the HIT Policy Committee. Date and Time: The HIT Standards Committee Workgroups will hold the...

Time-amplitude converter; Convertisseur temps-amplitude

Energy Technology Data Exchange (ETDEWEB)

Banner, M [Commissariat a l' Energie Atomique, Saclay (France).Centre d' Etudes Nucleaires

1961-07-01

It is normal in high energy physics to measure the time of flight of a particle in order to determine its mass. This can be done by the method which consists in transforming the time measurement into an analysis of amplitude, which is easier; a time-amplitude converter has therefore been built for this purpose. The apparatus here described uses a double grid control tube 6 BN 6 whose resolution time, as measured with a pulse generator, is 5 x 10{sup -11} s. The analysis of the response of a particle counter, made up of a scintillator and a photomultiplier, indicates that a time of resolution of 5 x 10{sup -10} s. can be obtained. A time of this order of magnitude is obtained experimentally with the converter. This converter has been used in the study of the time of flight of particles in a secondary beam of the accelerator Saturne. It has thus been possible to measure the energy spectrum of {pi}-mesons, of protons, and of deutons emitted from a polyethylene target bombarded by 1,4 and 2 GeV protons. (author) [French] Pour determiner la masse d'une particule, il est courant, en physique des hautes energies, de mesurer le temps de vol de cette particule. Cela peut etre fait par la methode qui consiste a transformer la mesure d'un temps en une analyse d'amplitude, plus aisee; aussi a-t-on, a cet effet, cree un convertisseur temps-amplitude. L'appareillage decrit dans cet article utilise un tube a double grille de commande 6 BN 6 dont le temps de resolution mesure avec un generateur d'impulsion est de 5.10{sup -11} s. L'analyse de la reponse d'un compteur de particules, constitue par un scintillateur et un photomultiplicateur, indique qu'un temps de resolution de 5.10{sup -10} s peut etre obtenu. Un temps de cet ordre est atteint experimentalement avec le convertisseur. Ce convertisseur a servi a l'etude du temps de vol des particules dans un faisceau secondaire de l'accelerateur Saturne. On a mesure ainsi le spectre d'energie des mesons {pi}, des protons, des deutons

Rare transformation to double hit lymphoma in Waldenstrom's macroglobulinemia.

Science.gov (United States)

Okolo, Onyemaechi N; Johnson, Ariel C; Yun, Seongseok; Arnold, Stacy J; Anwer, Faiz

2017-08-01

Waldenström macroglobulinemia (WM) is a lymphoproliferative lymphoma that is characterized by monoclonal immunoglobulin M (IgM) protein and bone marrow infiltration. Its incidence is rare and rarer still is its ability to transform to a B-cell lymphoma, particularly the aggressive diffuse large B-cell lymphoma, which bodes a poor prognosis. When transformation includes mutations of MYC, BCL-2 and/or BCL-6, it is known as a 'double hit' or 'triple hit' lymphoma respectively. This paper presents a rare case of WM with mutations positive for MYC and BCL2, making it a case of double hit B-cell lymphoplasmacytic lymphoma with plasmatic differentiation without morphological transformation to aggressive histology like DLBCL. The paper also broadens to include discussions on current topics in the classification, diagnosis, possible causes of transformation, and treatment of WM, including transformation to double hit lymphoma. The significance of this case lies in that the presence of double hit lymphoma-like genetic mutations in WM have not been previously described in the literature and potentially such changes are harbinger of extra-nodal presentation, aggressive growth, and possibly poor prognosis, if data from other double-hit lymphoma are extrapolated.

The application of standardized control and interface circuits to three dc to dc power converters.

Science.gov (United States)

Yu, Y.; Biess, J. J.; Schoenfeld, A. D.; Lalli, V. R.

1973-01-01

Standardized control and interface circuits were applied to the three most commonly used dc to dc converters: the buck-boost converter, the series-switching buck regulator, and the pulse-modulated parallel inverter. The two-loop ASDTIC regulation control concept was implemented by using a common analog control signal processor and a novel digital control signal processor. This resulted in control circuit standardization and superior static and dynamic performance of the three dc-to-dc converters. Power components stress control, through active peak current limiting and recovery of switching losses, was applied to enhance reliability and converter efficiency.

The detector response simulation for the CBM silicon tracking system as a tool for hit error estimation

Energy Technology Data Exchange (ETDEWEB)

Malygina, Hanna [Goethe Universitaet Frankfurt (Germany); KINR, Kyiv (Ukraine); GSI Helmholtzzentrum fuer Schwerionenforschung GmbH, Darmstadt (Germany); Friese, Volker; Zyzak, Maksym [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH, Darmstadt (Germany); Collaboration: CBM-Collaboration

2016-07-01

The Compressed Baryonic Matter experiment(CBM) at FAIR is designed to explore the QCD phase diagram in the region of high net-baryon densities. As the central detector component, the Silicon Tracking System (STS) is based on double-sided micro-strip sensors. To achieve realistic modelling, the response of the silicon strip sensors should be precisely included in the digitizer which simulates a complete chain of physical processes caused by charged particles traversing the detector, from charge creation in silicon to a digital output signal. The current implementation of the STS digitizer comprises non-uniform energy loss distributions (according to the Urban theory), thermal diffusion and charge redistribution over the read-out channels due to interstrip capacitances. Using the digitizer, one can test an influence of each physical processes on hit error separately. We have developed a new cluster position finding algorithm and a hit error estimation method for it. Estimated errors were verified by the width of pull distribution (expected to be about unity) and its shape.

Algorithms for ADC multi-site test with digital input stimulus

NARCIS (Netherlands)

Sheng, Xiaoqin; Kerkhoff, Hans G.; Zjajo, Amir; Gronthoud, Guido

2009-01-01

This paper reports two novel algorithms based on time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken as

Digital subtraction angiography

International Nuclear Information System (INIS)

Neuwirth, J. Jr.; Bohutova, J.

1987-01-01

The quality of radiodiagnostic methods to a great extent depends on the quality of the resulting image. The basic technical principles are summed up of the different parts of digital subtraction angiography apparatus and of methods of improving the image. The instrument is based on a videochain consisting of an X-ray tube, an intensifier of the radiographic image, optical parts, a video camera, an analog-to-digital converter and a computer. The main advantage of the digitally processed image is the possibility of optimizing the image into a form which will contain the biggest amount of diagnostically valuable information. Described are the mathematical operations for improving the digital image: spatial filtration, pixel shift, time filtration, image integration, time interval differentation and matched filtering. (M.D.). 8 refs., 3 figs

Converter of a continuous code into the Grey code

International Nuclear Information System (INIS)

Gonchar, A.I.; TrUbnikov, V.R.

1979-01-01

Described is a converter of a continuous code into the Grey code used in a 12-charged precision amplitude-to-digital converter to decrease the digital component of spectrometer differential nonlinearity to +0.7% in the 98% range of the measured band. To construct the converter of a continuous code corresponding to the input signal amplitude into the Grey code used is the regularity in recycling of units and zeroes in each discharge of the Grey code in the case of a continuous change of the number of pulses of a continuous code. The converter is constructed on the elements of 155 series, the frequency of continuous code pulse passing at the converter input is 25 MHz

Bidirectional dc-to-dc Power Converter

Science.gov (United States)

Griesbach, C. R.

1986-01-01

Solid-state, series-resonant converter uses high-voltage thyristors. Converter used either to convert high-voltage, low-current dc power to lowvoltage, high current power or reverse. Taking advantage of newly-available high-voltage thyristors to provide better reliability and efficiency than traditional converters that use vacuum tubes as power switches. New converter essentially maintenance free and provides greatly increased mean time between failures. Attractive in industrial applications whether or not bidirectional capability is required.

Complex-Vector Time-Delay Control of Power Converters

DEFF Research Database (Denmark)

Blaabjerg, Frede; Loh, P. C.; Tang, Y.

2008-01-01

Precise controlling of current produced by power converters is an important topic that has attracted interests over the last few decades. With the recent proliferation of grid-tied converters where the control of power flow is indirectly governed by the accuracy of current tracking, motivation...... since only a small amount of memory space for storing time-delayed values and simple arithmetic computations are needed for its physical realization. In addition to that, other advantages of the scheme include its abilities to compensate for negative-sequence, load and grid harmonic components using...

75 FR 21629 - HIT Standards Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2010-04-26

... Technology; HIT Standards Committee's Workgroup Meetings; Notice of Meetings AGENCY: Office of the National... only. Name of Committees: HIT Standards Committee's Workgroups: Clinical Operations Vocabulary... developed by the HIT Policy Committee. Date and Time: The HIT Standards Committee Workgroups will hold the...

Electromagnetic Compatibility of Matrix Converter System

Directory of Open Access Journals (Sweden)

S. Fligl

2006-12-01

Full Text Available The presented paper deals with matrix converters pulse width modulation strategies design with emphasis on the electromagnetic compatibility. Matrix converters provide an all-silicon solution to the problem of converting AC power from one frequency to another, offering almost all the features required of an ideal static frequency changer. They possess many advantages compared to the conventional voltage or current source inverters. A matrix converter does not require energy storage components as a bulky capacitor or an inductance in the DC-link, and enables the bi-directional power flow between the power supply and load. The most of the contemporary modulation strategies are able to provide practically sinusoidal waveforms of the input and output currents with negligible low order harmonics, and to control the input displacement factor. The perspective of matrix converters regarding EMC in comparison with other types of converters is brightly evident because it is no need to use any equipment for power factor correction and current and voltage harmonics reduction. Such converter with proper control is properly compatible both with the supply mains and with the supplied load. A special digital control system was developed for the realized experimental test bed which makes it possible to achieve greater throughput of the digital control system and its variability.

Eyewitness Identification Reforms: Are Suggestiveness-Induced Hits and Guesses True Hits?

Science.gov (United States)

Wells, Gary L; Steblay, Nancy K; Dysart, Jennifer E

2012-05-01

Research-based reforms for collecting eyewitness identification evidence (e.g., unbiased pre-lineup instructions, double-blind administration) have been proposed by psychologists and adopted in increasing numbers of jurisdictions across the United States. It is well known that reducing rates of mistaken identifications can also reduce accurate identification rates (hits). But the reforms are largely designed to reduce the suggestiveness of the procedures they are meant to replace. Accordingly, we argue that it is misleading to label any hits obtained because of suggestive procedures as "hits" and then saddle reforms with the charge that they reduce the rate of these illegitimate hits. Eyewitness identification evidence should be based solely on the independent memory of the witness, not aided by biased instructions, cues from lineup administrators, or the use of lineup fillers who make the suspect stand out. Failure to call out these hits as being illegitimate can give solace to those who are motivated to preserve the status quo. © The Author(s) 2012.

Development of a digital solar simulator based on full-bridge converter

Science.gov (United States)

Liu, Chen; Feng, Jian; Liu, Zhilong; Tong, Weichao; Ji, Yibo

2014-02-01

With the development of solar photovoltaic, distribution schemes utilized in power grid had been commonly application, and photovoltaic (PV) inverter is an essential equipment in grid. In this paper, a digital solar simulator based on full-bridge structure is presented. The output characteristic curve of system is electrically similar to silicon solar cells, which can greatly simplify research methods of PV inverter, improve the efficiency of research and development. The proposed simulator consists on a main control board based on TM320F28335, phase-shifted zero-voltage-switching (ZVS) DC-DC full-bridge converter and voltage and current sampling circuit, that allows emulating the voltage-current curve with the open-circuit voltage (Voc) of 900V and the short-circuit current (Isc) of 18A .When the system connected to a PV inverter, the inverter can quickly track from the open-circuit to the maximum power point and keep stability.

Digital voltmeter

International Nuclear Information System (INIS)

Yohannes Kamadi; Soekarno.

1976-01-01

The electrical voltage measuring equipment with digital display has been made. This equipment uses four digits display with single polarity measurement and integrating system. Pulses from the oscillator will be counted and converted to the staircase voltages, and compared to the voltage measured. When the balance is already achieved, the pulse will appear at the comparator circuit. This pulse will be used to trigger univibrator circuit. The univibrator output is used as signal for stopping the counting, and when reading time T already stops, the counting system will be reset. (authors)

Time concurrency/phase-time synchronization in digital communications networks

Science.gov (United States)

Kihara, Masami; Imaoka, Atsushi

1990-01-01

Digital communications networks have the intrinsic capability of time synchronization which makes it possible for networks to supply time signals to some applications and services. A practical estimation method for the time concurrency on terrestrial networks is presented. By using this method, time concurrency capability of the Nippon Telegraph and Telephone Corporation (NTT) digital communications network is estimated to be better than 300 ns rms at an advanced level, and 20 ns rms at final level.

Reduction of multiple hits in atom probe tomography

International Nuclear Information System (INIS)

Thuvander, Mattias; Kvist, Anders; Johnson, Lars J.S.; Weidow, Jonathan; Andrén, Hans-Olof

2013-01-01

The accuracy of compositional measurements using atom probe tomography is often reduced because some ions are not recorded when several ions hit the detector in close proximity to each other and within a very short time span. In some cases, for example in analysis of carbides, the multiple hits result in a preferential loss of certain elements, namely those elements that frequently field evaporate in bursts or as dissociating molecules. In this paper a method of reducing the effect of multiple hits is explored. A fine metal grid was mounted a few millimeters behind the local electrode, effectively functioning as a filter. This resulted in a decrease in the overall detection efficiency, from 37% to about 5%, but also in a decrease in the fraction of multiple hits. In an analysis of tungsten carbide the fraction of ions originating from multiple hits decreased from 46% to 10%. As a result, the measured carbon concentration increased from 48.2 at%to 49.8 at%, very close to the expected 50.0 at%. The characteristics of the multiple hits were compared for analyses with and without the grid filter. - Highlights: ► APT experiments have been performed with a reduced amount of multiple hits. ► The multiple hits were reduced by placing a grid behind the electrode. ► This resulted in improved carbon measurement of WC

Hit Parade

DEFF Research Database (Denmark)

Backe, Hans-Joachim

2017-01-01

Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Kulturnatten 2017, ITU, Copenhagen, DK, Oct 13, 2017.......Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Kulturnatten 2017, ITU, Copenhagen, DK, Oct 13, 2017....

Hit Parade

DEFF Research Database (Denmark)

Cermak, Daniel; Wrighton, Max Alexander; Backe, Hans-Joachim

2016-01-01

Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Demo Night, ITU, Copenhagen, DK, Oct 5, 2016.......Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Demo Night, ITU, Copenhagen, DK, Oct 5, 2016....

Scaled Data from Digital Ionograms

Data.gov (United States)

National Oceanic and Atmospheric Administration, Department of Commerce — All the data contributed come from 1957 through 1990. They have been digitized, reformatted, converted to universal time (the software also can display the data in...

76 FR 55914 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-09-09

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

76 FR 46297 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-08-02

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

76 FR 22399 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-04-21

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

76 FR 28784 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-05-18

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

76 FR 14974 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-03-18

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

76 FR 50735 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-08-16

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... standards, implementation specifications, and certification criteria are needed. Date and Time: The HIT...

Hit Parade

DEFF Research Database (Denmark)

Cermak, Daniel; Wrighton, Max Alexander; Backe, Hans-Joachim

2016-01-01

Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Kulturnatten 2016, Danish Science Ministry, Copenhagen, DK, Oct 14, 2016.......Daniel Cermak-Sassenrath, Max Alexander Wrighton, Hans-Joachim Backe. Hit Parade. Installation. Kulturnatten 2016, Danish Science Ministry, Copenhagen, DK, Oct 14, 2016....

Single start multiple stop time digitizer

International Nuclear Information System (INIS)

Deshpande, P.A.; Mukhopadhyay, P.K.; Gopalakrishnan, K.R.

1997-01-01

A single start multiple stop time digitizer has been developed which can digitize the time between a start pulse and multiple stop pulses. The system has been designed as a PC add on card. The resolution of the instrument is 10 nSecs and the maximum length of time that it can measure is 1.28 milliseconds. Apart from time digitization, it can also resolve the height of the incoming pulses into 64 levels. After each input pulse the system dead time is less than 300 nSecs. The driver software for this card has been developed on DOS platform. It uses graphical user interface to provide a user friendly environment. The system is intended to be used in time of flight mass spectroscopy experiments. It can also be used for time of flight experiments in nuclear physics. (author). 2 figs

Stability Analysis of a Matrix Converter Drive: Effects of Input Filter Type and the Voltage Fed to the Modulation Algorithm

Directory of Open Access Journals (Sweden)

M. Hosseini Abardeh

2015-03-01

Full Text Available The matrix converter instability can cause a substantial distortion in the input currents and voltages which leads to the malfunction of the converter. This paper deals with the effects of input filter type, grid inductance, voltage fed to the modulation algorithm and the synchronous rotating digital filter time constant on the stability and performance of the matrix converter. The studies are carried out using eigenvalues of the linearized system and simulations. Two most common schemes for the input filter (LC and RLC are analyzed. It is shown that by a proper choice of voltage input to the modulation algorithm, structure of the input filter and its parameters, the need for the digital filter for ensuring the stability can be resolved. Moreover, a detailed model of the system considering the switching effects is simulated and the results are used to validate the analytical outcomes. The agreement between simulation and analytical results implies that the system performance is not deteriorated by neglecting the nonlinear switching behavior of the converter. Hence, the eigenvalue analysis of the linearized system can be a proper indicator of the system stability.

76 FR 46298 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-08-02

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held virtually on August 17, 2011...

76 FR 50734 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-08-16

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on September 28, 2011, from 9...

77 FR 2727 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-01-19

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on February 29, 2012, from 9...

76 FR 70455 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-11-14

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on December 14, 2011, from 9...

77 FR 73661 - HIT Standards Committee Advisory Meetings; Notice of Meetings

Science.gov (United States)

2012-12-11

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meetings; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: These meetings will be held on the following dates and...

76 FR 70454 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2011-11-14

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Policy Committee's Workgroup Meetings; Notice of... be open to the public via dial-in access only. Name of Committees: HIT Policy Committee's Workgroups... certification criteria are needed. Date and Time: The HIT Policy Committee Workgroups will hold the following...

77 FR 65691 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-10-30

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on November 13, 2012, from 9...

77 FR 50690 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-08-22

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on September 19, 2012, from 9...

75 FR 21628 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2010-04-26

... Technology HIT Standards Committee Advisory Meeting; Notice of Meeting AGENCY: Office of the National... Information Technology (ONC). The meeting will be open to the public. Name of Committee: HIT Standards... Strategic Plan, and in accordance with policies developed by the HIT Policy Committee. Date and Time: The...

76 FR 55913 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-09-09

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held virtually on October 21, 2011...

77 FR 65690 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-10-30

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on December 19, 2012, from 9...

The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

Science.gov (United States)

Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

The ALTRO Chip A 16-channel A/D Converter and Digital Processor for Gas Detectors

CERN Document Server

Esteve-Bosch, R; Mota, B; Musa, L

2003-01-01

The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40MHz. After digitisation, a pipelined hardwired Processor is able to remove from the input signal a wide range of systematic and non-systematic perturbations, related to the non-ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Processor is able to suppress the signal tail within 1mus after the pulse pea...

Modular High Voltage Pulse Converter for Short Rise and Decay Times

NARCIS (Netherlands)

Mao, S.

2018-01-01

This thesis explores a modular HV pulse converter technology with short rise and decay times. A systematic methodology to derive and classify HV architectures based on a modularization level of power building blocks of the HV pulse converter is developed to summarize existing architectures and

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

77 FR 16035 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-03-19

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on March 27, 2012, from 9 a.m...

76 FR 79684 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-12-22

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on January 25, 2012, from 9 a...

77 FR 15760 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-03-16

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on April 18, 2012, from 9 a.m...

76 FR 14976 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-03-18

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on April 20, 2011, from 9 a.m...

76 FR 39109 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-07-05

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on July 20, 2011, from 9 a.m...

76 FR 28782 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-05-18

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on June 22, 2011, from 9 a.m...

77 FR 27459 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-05-10

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on June 20, 2012, from 9 a.m...

77 FR 37408 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-06-21

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... be open to the public. Name of Committee: HIT Standards Committee. General Function of the Committee... with policies developed by the HIT Policy Committee. Date and Time: The meeting will be held on July 19...

77 FR 22787 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-04-17

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on May 24, 2012, from 9 a.m...

76 FR 22396 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-04-21

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: to provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on May 18, 2011, from 9 a.m...

77 FR 60438 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-10-03

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on October 17, 2012, from 9 a...

76 FR 9783 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2011-02-22

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on March 29, 2011, from 9 a.m...

77 FR 45353 - HIT Standards Committee Advisory Meeting; Notice of Meeting

Science.gov (United States)

2012-07-31

... DEPARTMENT OF HEALTH AND HUMAN SERVICES HIT Standards Committee Advisory Meeting; Notice of... public. Name of Committee: HIT Standards Committee. General Function of the Committee: To provide... developed by the HIT Policy Committee. Date and Time: The meeting will be held on August 15, 2012, from 9:00...

Novel HIT antibody detection method using Sonoclot® coagulation analyzer.

Science.gov (United States)

Wanaka, Keiko; Asada, Reiko; Miyashita, Kumiko; Kaneko, Makoto; Endo, Hirokazu; Yatomi, Yutaka

2015-01-01

Since heparin-induced thrombocytopenia (HIT), caused by the generation of antibodies against platelet factor 4 (PF4)/heparin complexes (HIT antibodies), may induce serious complications due to thrombosis, a prompt diagnosis is desirable. Functional tests with platelet activation to detect HIT antibodies are useful for diagnosis of HIT, in particular (14)C-selotonin release assay (SRA). However, they are complicated and so can be performed only in limited laboratories. We tested if a blood coagulation test using Sonoclot® analyzer can serve for the detection of HIT antibodies. A murine monoclonal antibody (HIT-MoAb) against PF4/heparin complexes was used as an alternative to human HIT antibodies. To the mixture of HIT-MoAb and heparin (0.5 U/mL, final), whole blood obtained from a healthy volunteer was added, and then the activated clotting time (ACT), clot rate (CR), and area under the curve (AUC) were measured with Sonoclot® analyzer for 30minutes. The HIT-MoAb (30 to 100μg/mL, final) concentration dependently suppressed the anticoagulation activity (prolongation of ACT and decrease of CR and AUC) of heparin. The suppression of anticoagulation effect of heparin by HIT-MoAb was demonstrated by measurements using Sonoclot® analyzer. This method may provide a new tool for screening of HIT antibodies. Copyright © 2014 Elsevier Ltd. All rights reserved.

Noise-shaping all-digital phase-locked loops modeling, simulation, analysis and design

CERN Document Server

Brandonisio, Francesco

2014-01-01

This book presents a novel approach to the analysis and design of all-digital phase-locked loops (ADPLLs), technology widely used in wireless communication devices. The authors provide an overview of ADPLL architectures, time-to-digital converters (TDCs) and noise shaping. Realistic examples illustrate how to analyze and simulate phase noise in the presence of sigma-delta modulation and time-to-digital conversion. Readers will gain a deep understanding of ADPLLs and the central role played by noise-shaping. A range of ADPLL and TDC architectures are presented in unified manner. Analytical and simulation tools are discussed in detail. Matlab code is included that can be reused to design, simulate and analyze the ADPLL architectures that are presented in the book.   • Discusses in detail a wide range of all-digital phase-locked loops architectures; • Presents a unified framework in which to model time-to-digital converters for ADPLLs; • Explains a procedure to predict and simulate phase noise in oscil...

A robust parasitic-insensitive successive approximation capacitance-to-digital converter

KAUST Repository

Omran, Hesham

2014-09-01

In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/oC. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor. © 2014 IEEE.

A robust parasitic-insensitive successive approximation capacitance-to-digital converter

KAUST Repository

Omran, Hesham; Arsalan, Muhammad; Salama, Khaled N.

2014-01-01

In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/oC. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor. © 2014 IEEE.

Design and Simulation of Seido Buffer for Analog to Digital Converter (ADC) on Multichannel Analyzer (MCA) Application

International Nuclear Information System (INIS)

Harzawadi Hasim; Maslina Ibrahim; Nolida Yusop; Mohd Ashhar Khalid

2011-01-01

Most of our electronic equipment has buffer, thus this make buffer as one of importance in electronic gadget. This paper introduced Single Ended Input Differential Output (SEIDO) buffer to predict the bias at approximately 2.5 V. For this purpose, the input range between -1 mV to 4 V was implemented. The software used to cascade SEIDO buffer is called LTspice IV; an open source software developed by Linear Technology Incorporation. The component involve in this development was Operational Amplifier (OP AMP) AD826 from Analog Devices Incorporation, capacitor and resistor. Kirchhoffs Current Law and Kirchhoffs Voltage Law was applied to calculated voltage gain and biasing voltage. All design has been verified by LTspice IV. The result produced from simulation was between -0.3 V to 6.3 V with bias roughly at 2.5 V. These results prove that it was capable to drive Analog Digital Converter (ADC) that can subsequently apply for Multichannel Analyzer (MCA). (author)

Fast digitization and digital receiver technology

International Nuclear Information System (INIS)

Kimball, Ralph C.

2002-01-01

The potentially lucrative wireless market has led to technological advances in mixed signal devices such as high speed, high resolution A/D and D/A converters. This same market has also driven the development of high performance multi-channel digital receiver and digital transmitter ICs. Similarly, advances in semiconductor processes, coupled with the need for reduced time-to-market, has led to the development of large, enhanced performance, in-circuit programmable logic devices. A review of the key characteristics of these mixed-signal, signal processing and programmable logic devices is presented. The application of these devices and technologies to the instrumentation of Accelerators and Storage Rings is discussed and presented by way of examples. Issues relating to the requirements associated with real-time processing, I/O throughput, reconfigurability, reliability, maintainability and packaging requirements are also addressed

Design of High-Voltage Switch-Mode Power Amplifier Based on Digital-Controlled Hybrid Multilevel Converter

Directory of Open Access Journals (Sweden)

Yanbin Hou

2016-01-01

Full Text Available Compared with conventional Class-A, Class-B, and Class-AB amplifiers, Class-D amplifier, also known as switching amplifier, employs pulse width modulation (PWM technology and solid-state switching devices, capable of achieving much higher efficiency. However, PWM-based switching amplifier is usually designed for low-voltage application, offering a maximum output voltage of several hundred Volts. Therefore, a step-up transformer is indispensably adopted in PWM-based Class-D amplifier to produce high-voltage output. In this paper, a switching amplifier without step-up transformer is developed based on digital pulse step modulation (PSM and hybrid multilevel converter. Under the control of input signal, cascaded power converters with separate DC sources operate in PSM switch mode to directly generate high-voltage and high-power output. The relevant topological structure, operating principle, and design scheme are introduced. Finally, a prototype system is built, which can provide power up to 1400 Watts and peak voltage up to ±1700 Volts. And the performance, including efficiency, linearity, and distortion, is evaluated by experimental tests.

Easy digital engineering

International Nuclear Information System (INIS)

Jin, Dal Bok

2002-02-01

This book lists basic of digital engineering, number system and digital code, Boolean algebra and basic logic circuit, simplify of logical expression, combinational circuit, arithmetic circuit, multivibrator circuit, sequential circuit, memory unit of semiconductor and logical element for program, D/A converter and A/D converter, logic element and integrated circuit and logic circuit and micro controller. It has exercises and answers about digital engineering and summary in the end of each chapter.

Broadband analog to digital conversion with spatial-spectral holography

International Nuclear Information System (INIS)

Babbitt, W. Randall; Neifeld, Mark A.; Merkel, Kristian D.

2007-01-01

A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization

Broadband analog to digital conversion with spatial-spectral holography

Energy Technology Data Exchange (ETDEWEB)

Babbitt, W. Randall [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)]. E-mail: babbitt@physics.montana.edu; Neifeld, Mark A. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States); Merkel, Kristian D. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)

2007-11-15

A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization.

Verbs in the lexicon: Why is hitting easier than breaking?

Science.gov (United States)

McKoon, Gail; Love, Jessica

2011-11-01

Adult speakers use verbs in syntactically appropriate ways. For example, they know implicitly that the boy hit at the fence is acceptable but the boy broke at the fence is not. We suggest that this knowledge is lexically encoded in semantic decompositions. The decomposition for break verbs (e.g. crack, smash) is hypothesized to be more complex than that for hit verbs (e.g. kick, kiss). Specifically, the decomposition of a break verb denotes that "an entity changes state as the result of some external force" whereas the decomposition for a hit verb denotes only that "an entity potentially comes in contact with another entity." In this article, verbs of the two types were compared in a lexical decision experiment - Experiment 1 - and they were compared in sentence comprehension experiments with transitive sentences (e.g. the car hit the bicycle and the car broke the bicycle) - Experiments 2 and 3. In Experiment 1, processing times were shorter for the hit than the break verbs and in Experiments 2 and 3, processing times were shorter for the hit sentences than the break sentences, results that are in accord with the complexities of the postulated semantic decompositions.

75 FR 29762 - HIT Policy Committee's Workgroup Meetings; Notice of Meetings

Science.gov (United States)

2010-05-27

... Technology HIT Policy Committee's Workgroup Meetings; Notice of Meetings AGENCY: Office of the National... only. Name of Committees: HIT Policy Committee's Workgroups: Meaningful Use, Privacy & Security Policy... specifications, and certification criteria are needed. Date and Time: The HIT Policy Committee Workgroups will...

MYC/BCL2/BCL6 triple hit lymphoma: a study of 40 patients with a comparison to MYC/BCL2 and MYC/BCL6 double hit lymphomas.

Science.gov (United States)

Huang, Wenting; Medeiros, L Jeffrey; Lin, Pei; Wang, Wei; Tang, Guilin; Khoury, Joseph; Konoplev, Sergej; Yin, C Cameron; Xu, Jie; Oki, Yasuhiro; Li, Shaoying

2018-05-21

High-grade B-cell lymphomas with MYC, BCL2, and BCL6 rearrangements (triple hit lymphoma) are uncommon. We studied the clinicopathologic features of 40 patients with triple hit lymphoma and compared them to 157 patients with MYC/BCL2 double hit lymphoma and 13 patients with MYC/BCL6 double hit lymphoma. The triple hit lymphoma group included 25 men and 15 women with a median age of 61 years (range, 34-85). Nine patients had a history of B-cell lymphoma. Histologically, 23 (58%) cases were diffuse large B-cell lymphoma and 17 cases had features of B-cell lymphoma, unclassifiable, with features intermediate between diffuse large B-cell lymphoma and Burkitt lymphoma. Most cases of triple hit lymphoma were positive for CD10 (100%), BCL2 (95%), BCL6 (82%), MYC (74%), and 71% with MYC and BCL2 coexpression. P53 was overexpressed in 29% of triple hit lymphoma cases. The clinicopathological features of triple hit lymphoma patients were similar to patients with MYC/BCL2 and MYC/BCL6 double hit lymphoma, except that triple hit lymphoma cases were more often CD10 positive compared with MYC/BCL6 double hit lymphoma (p hit lymphoma and double hit lymphoma and overall survival in triple hit lymphoma patients was 17.6 months, similar to the overall survival of patients with double hit lymphoma (p = 0.67). Patients with triple hit lymphoma showing P53 overexpression had significantly worse overall survival compared with those without P53 overexpression (p = 0.04). On the other hand, double expressor status and prior history of B-cell lymphoma did not correlate with overall survival. In conclusion, most patients with triple hit lymphoma have an aggressive clinical course and poor prognosis and these tumors have a germinal center B-cell immunophenotype, similar to patients with double hit lymphomas. P53 expression is a poor prognostic factor in patients with triple hit lymphoma.

ADC multi-site test based on a pre-test with digital input stimulus

NARCIS (Netherlands)

Sheng, Xiaoqin; Metra, C.; Kerkhoff, Hans G.; Zjajo, Amir; Gronthoud, Guido

2012-01-01

This paper describes two novel algorithms based on the time-modulo reconstruction method intended for detection of the parametric faults in analogue-to-digital converters (ADC). In both algorithms, a pulse signal, in its slightly adapted form to allow sufficient time for converter settling, is taken

Method for Converter Synchronization with RF Injection

OpenAIRE

Joshua P. Bruckmeyer; Ivica Kostanic

2015-01-01

This paper presents an injection method for synchronizing analog to digital converters (ADC). This approach can eliminate the need for precision routed discrete synchronization signals of current technologies, such as JESD204. By eliminating the setup and hold time requirements at the conversion (or near conversion) clock rate, higher sample rate systems can be synchronized. Measured data from an existing multiple ADC conversion system was used to evaluate the method. Coherent beams were simu...

Axial Tomography from Digitized Real Time Radiography

Science.gov (United States)

Zolnay, A. S.; McDonald, W. M.; Doupont, P. A.; McKinney, R. L.; Lee, M. M.

1985-01-18

Axial tomography from digitized real time radiographs provides a useful tool for industrial radiography and tomography. The components of this system are: x-ray source, image intensifier, video camera, video line extractor and digitizer, data storage and reconstruction computers. With this system it is possible to view a two dimensional x-ray image in real time at each angle of rotation and select the tomography plane of interest by choosing which video line to digitize. The digitization of a video line requires less than a second making data acquisition relatively short. Further improvements on this system are planned and initial results are reported.

Dirty Hits

OpenAIRE

Clarke, Louise

2010-01-01

Issue 9 of the Saatchi Gallery Magazine: Art&Music is dedicated to Sex. The article Dirty Hits invited a cross-section of contemporary artists and musicians to answer: What makes a dirty hit? As one of the artists invited, I wrote an autobiographical piece to reveal how these fumbling, feral sexual experiences of my childhood landscape, along with irrational superstition and folk law inform my life and underpin my work. The article also included an artwork: Louise Clarke, Sip (2009)

A CAMAC unit for charge measuring and pulse shape recording based on a fast, 8-bit parallel analog-to-digital converter

International Nuclear Information System (INIS)

Kulka, Z.; Kreciejewski, M.; Nadachowski, M.

1990-08-01

A device designed mainly for measuring systems for testing parameters of some type of detectors used in the high energy physics is described. The device is one-module CAMAC unit. It is equipped in a fast, 8-bit parallel analog-to-digital converter ''flash''type with a gated integrator at the input and a static RAM (4096 x 8 bit) at the output. The device enables measurements of the charge in pulses from detectors or registration of the shape of these pulses. The construction, operation and parameters of the circuits of the device are described and the way of programming functions using CAMAC dataway is given. 8 refs., 9 figs. (author)

Optimum phase shift in the self-oscillating loop for piezoelectric transformer-based power converters

DEFF Research Database (Denmark)

Ekhtiari, Marzieh; Zsurzsan, Tiberiu-Gabriel; Andersen, Michael A. E.

2017-01-01

A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitally controlled time delay through the self-oscillating loop results in very precise frequency control...... and ensures optimum operation of the piezoelectric transformer in terms of gain and efficiency. Time delay is implemented digitally for the first time through a 16 bit digital-to-analog converter in the self-oscillating loop. The new design of the delay circuit provides 45 ps time resolution, enabling fine......-grained control of phase in the self-oscillating loop. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. Ultimately, by selecting the optimum phase shift, maximum efficiency under the load and temperature condition is achievable....

Utilization of the voltage frequency converter or digital representation and documentation of transient reactor operation

International Nuclear Information System (INIS)

Doane, Harry J.

1986-01-01

The ease and speed of handling transient data is enhanced by the use of a voltage to frequency converter (VFC). This analogue to digital semiconductor device provides an inexpensive and portable alternative to electro-mechanical recorders and hand entry of data into computer codes. The VFC used at The University of Arizona is a Teledyne Philbrick 4705/01. A zero to positive ten volt input signal provides a zero to one megahertz output signal which is TTL/DTL compatible. VFC is used at the University of Arizona to collect data for super prompt critical TRIGA excursions. The VFC provides a low cost, convenient method of transient data storage and retrieval for experimentation and laboratory demonstration

Contribution of Visual Information about Ball Trajectory to Baseball Hitting Accuracy.

Directory of Open Access Journals (Sweden)

Takatoshi Higuchi

Full Text Available The contribution of visual information about a pitched ball to the accuracy of baseball-bat contact may vary depending on the part of trajectory seen. The purpose of the present study was to examine the relationship between hitting accuracy and the segment of the trajectory of the flying ball that can be seen by the batter. Ten college baseball field players participated in the study. The systematic error and standardized variability of ball-bat contact on the bat coordinate system and pitcher-to-catcher direction when hitting a ball launched from a pitching machine were measured with or without visual occlusion and analyzed using analysis of variance. The visual occlusion timing included occlusion from 150 milliseconds (ms after the ball release (R+150, occlusion from 150 ms before the expected arrival of the launched ball at the home plate (A-150, and a condition with no occlusion (NO. Twelve trials in each condition were performed using two ball speeds (31.9 m·s-1 and 40.3 m·s-1. Visual occlusion did not affect the mean location of ball-bat contact in the bat's long axis, short axis, and pitcher-to-catcher directions. Although the magnitude of standardized variability was significantly smaller in the bat's short axis direction than in the bat's long axis and pitcher-to-catcher directions (p < 0.001, additional visible time from the R+150 condition to the A-150 and NO conditions resulted in a further decrease in standardized variability only in the bat's short axis direction (p < 0.05. The results suggested that there is directional specificity in the magnitude of standardized variability with different visible time. The present study also confirmed the limitation to visual information is the later part of the ball trajectory for improving hitting accuracy, which is likely due to visuo-motor delay.

Application handbook for a Standardized Control Module (SCM) for DC-DC converters, volume 1

Science.gov (United States)

Lee, F. C.; Mahmoud, M. F.; Yu, Y.

1980-04-01

The standardized control module (SCM) was developed for application in the buck, boost and buck/boost DC-DC converters. The SCM used multiple feedback loops to provide improved input line and output load regulation, stable feedback control system, good dynamic transient response and adaptive compensation of the control loop for changes in open loop gain and output filter time constraints. The necessary modeling and analysis tools to aid the design engineer in the application of the SCM to DC-DC Converters were developed. The SCM functional block diagram and the different analysis techniques were examined. The average time domain analysis technique was chosen as the basic analytical tool. The power stage transfer functions were developed for the buck, boost and buck/boost converters. The analog signal and digital signal processor transfer functions were developed for the three DC-DC Converter types using the constant on time, constant off time and constant frequency control laws.

Application handbook for a Standardized Control Module (SCM) for DC-DC converters, volume 1

Science.gov (United States)

Lee, F. C.; Mahmoud, M. F.; Yu, Y.

1980-01-01

The standardized control module (SCM) was developed for application in the buck, boost and buck/boost DC-DC converters. The SCM used multiple feedback loops to provide improved input line and output load regulation, stable feedback control system, good dynamic transient response and adaptive compensation of the control loop for changes in open loop gain and output filter time constraints. The necessary modeling and analysis tools to aid the design engineer in the application of the SCM to DC-DC Converters were developed. The SCM functional block diagram and the different analysis techniques were examined. The average time domain analysis technique was chosen as the basic analytical tool. The power stage transfer functions were developed for the buck, boost and buck/boost converters. The analog signal and digital signal processor transfer functions were developed for the three DC-DC Converter types using the constant on time, constant off time and constant frequency control laws.

Developing Health Information Technology (HIT) Programs and HIT Curriculum: The Southern Polytechnic State University Experience

Science.gov (United States)

Zhang, Chi; Reichgelt, Han; Rutherfoord, Rebecca H.; Wang, Andy Ju An

2014-01-01

Health Information Technology (HIT) professionals are in increasing demand as healthcare providers need help in the adoption and meaningful use of Electronic Health Record (EHR) systems while the HIT industry needs workforce skilled in HIT and EHR development. To respond to this increasing demand, the School of Computing and Software Engineering…

Real Time In-circuit Condition Monitoring of MOSFET in Power Converters

Directory of Open Access Journals (Sweden)

Shakeb A. Khan

2015-03-01

Full Text Available Abstract:This paper presents simple and low-cost, real time in-circuit condition monitoring of MOSFET in power electronic converters. Design metrics requirements like low cost, small size, high power factor, low percentage of total harmonic distortion etc. requires the power electronic systems to operate at high frequencies and at high power density. Failures of power converters are attributed largely by aging of power MOSFETs at high switching frequencies. Therefore, real time in-circuit prognostic of MOSFET needs to be done before their selection for power system design. Accelerated aging tests are performed in different circuits to determine the wear out failure of critical components based on their parametric degradation. In this paper, the simple and low-cost test beds are designed for real time in-circuit prognostics of power MOSFETs. The proposed condition monitoring scheme helps in estimating the condition of MOSFETs at their maximum rated operating condition and will aid the system designers to test their reliability and benchmark them before selecting in power converters.

Development of a precise long-time digital integrator for magnetic measurements in a tokamak

Energy Technology Data Exchange (ETDEWEB)

Kurihara, Kenichi; Kawamata, Youichi [Japan Atomic Energy Research Inst., Naka, Ibaraki (Japan). Naka Fusion Research Establishment

1997-10-01

Long-time D-T burning operation in a tokamak requires that a magnetic sensor must work in an environment of 14-MeV intense neutron field, and that the measurement system must output precise magnetic field values. A method of time-integration of voltage produced in a simple pick-up coil seems to have preferable features of good time response, easy maintenance, and resistance to neutron irradiation. However, an inevitably-produced signal drift makes it difficult to apply the method to the long-time integral operation. To solve this problem, we have developed a new digital integrator (a voltage-to-frequency converter and an up-down counter) with testing the trial boards in the JT-60 magnetic measurements. This reports all of the problems and their measures through the development steps in details, and shows how to apply this method to the ITER operation. (author)

Fixed switching frequency applied in single-phase boost AC to DC converter

International Nuclear Information System (INIS)

Chen, T.-C.; Ren, T.-J.; Ou, J.-C.

2009-01-01

The fixed switching frequency control for a single-phase boost AC to DC converter to achieve a sinusoidal line current and unity power factor is proposed in this paper. The relation between the line current error and the fixed switching frequency was developed. For a limit line current error, the minimum switching frequency for a boost AC to DC converter can be achieved. The proposed scheme was implemented using a 32-bit digital signal processor TMS320C32. Simulations and experimental results demonstrate the feasibility and fast dynamic response of the proposed control strategy.

Digital pulse processor for ion beam microprobe imaging

International Nuclear Information System (INIS)

Bogovac, M.; Jaksic, M.; Wegrzynek, D.; Markowicz, A.

2009-01-01

Capabilities of spectroscopic ion beam analysis (IBA) techniques that are available in ion microprobe facilities can be greatly improved by the use of digital pulse processing. We report here development of a digital multi parameter data acquisition system suitable for IBA imaging applications. Input signals from charge sensitive preamplifier are conditioned by using a simple circuit and digitized with fast ADCs. The digitally converted signals are processed in real time using FPGA. Implementation of several components of the system is presented.

Simultaneous hit finding and timing method for pulse shape analysis of drift chamber signals

Energy Technology Data Exchange (ETDEWEB)

Schaile, D; Schaile, O; Schwarz, J

1986-01-01

An algorithm for the analysis of the digitized signal waveform of drift chamber pulses is described which yields a good multihit resolution and an accurate drift time determination with little processing time. The method has been tested and evaluated with measured pulse shapes from the full size prototype of the OPAL central detector which were digitized by 100 MHz FADCs. (orig.).

Simultaneous hit finding and timing method for pulse shape analysis of drift chamber signals

Energy Technology Data Exchange (ETDEWEB)

Schaile, D; Schaile, O; Schwarz, J

1986-01-01

An algorithm for the analysis of the digitized signal waveform of drift chamber pulses is described which yields a good multihit resolution and an accurate drift time determination with little processing time. The method has been tested and evaluated with measured pulse shapes from the full size prototype of the OPAL central detector which were digitized by 100 MHz FADCs.

Coherent time-stretch transformation for real-time capture of wideband signals.

Science.gov (United States)

Buckley, Brandon W; Madni, Asad M; Jalali, Bahram

2013-09-09

Time stretch transformation of wideband waveforms boosts the performance of analog-to-digital converters and digital signal processors by slowing down analog electrical signals before digitization. The transform is based on dispersive Fourier transformation implemented in the optical domain. A coherent receiver would be ideal for capturing the time-stretched optical signal. Coherent receivers offer improved sensitivity, allow for digital cancellation of dispersion-induced impairments and optical nonlinearities, and enable decoding of phase-modulated optical data formats. Because time-stretch uses a chirped broadband (>1 THz) optical carrier, a new coherent detection technique is required. In this paper, we introduce and demonstrate coherent time stretch transformation; a technique that combines dispersive Fourier transform with optically broadband coherent detection.

Optical timing receiver for the NASA Spaceborne Ranging System. Part II: high precision event-timing digitizer

Energy Technology Data Exchange (ETDEWEB)

Leskovar, Branko; Turko, Bojan

1978-08-01

Position-resolution capabilities of the NASA Spaceborne Laser Ranging System are essentially determined by the timeresolution capabilities of its optical timing receiver. The optical timing receiver consists of a fast photoelectric device; (e.g., photomultiplier or an avalanche photodiode detector), a timing discriminator, a high-precision event-timing digitizer, and a signal-processing system. The time-resolution capabilities of the receiver are determined by the photoelectron time spread of the photoelectric device, the time walk and resolution characteristics of the timing discriminator, and the resolution of the event-timing digitizer. It is thus necessary to evaluate available fast photoelectronic devices with respect to the time-resolution capabilities, and to develop a very low time walk timing discriminator and a high-resolution event-timing digitizer to be used in the high-resolution spaceborne laser ranging system receiver. This part of the report describes the development of a high precision event-timing digitizer. The event-timing digitizer is basically a combination of a very accurate high resolution real time digital clock and an interval timer. The timing digitizer is a high resolution multiple stop clock, counting the time up to 131 days in 19.5 ps increments.

Young Children and Screen Time: Creating a Mindful Approach to Digital Technology

Science.gov (United States)

Neumann, Michelle Margaret

2015-01-01

To effectively address early childhood screen time concerns raised by parents and policy makers it is important to examine the current home digital environments of young children. The present study draws upon research that examined the home digital environment of Australian parents and their children (aged 2 to 4; N = 69). Parents completed a…

Design and debugging of multi-step analog to digital converters

NARCIS (Netherlands)

Zjajo, A.

2010-01-01

With the fast advancement of CMOS fabrication technology, more and more signal-processing functions are implemented in the digital domain for a lower cost, lower power consumption, higher yield, and higher re-configurability. The trend of increasing integration level for integrated circuits has