WorldWideScience

Sample records for high-speed integrated circuits

  1. Nanotechnology: high-speed integrated nanowire circuits.

    Science.gov (United States)

    Friedman, Robin S; McAlpine, Michael C; Ricketts, David S; Ham, Donhee; Lieber, Charles M

    2005-04-28

    Macroelectronic circuits made on substrates of glass or plastic could one day make computing devices ubiquitous owing to their light weight, flexibility and low cost. But these substrates deform at high temperatures so, until now, only semiconductors such as organics and amorphous silicon could be used, leading to poor performance. Here we present the use of low-temperature processes to integrate high-performance multi-nanowire transistors into logical inverters and fast ring oscillators on glass substrates. As well as potentially enabling powerful electronics to permeate all aspects of modern life, this advance could find application in devices such as low-cost radio-frequency tags and fully integrated high-refresh-rate displays.

  2. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  3. High-speed Integrated Circuits for electrical/Optical Interfaces

    DEFF Research Database (Denmark)

    Jespersen, Christoffer Felix

    2008-01-01

    of LC-oscillators with oscillator criteria, phase noise and different topologies are given as background. The theory of PLL circuits is also presented. Guidelines and suggestions for static divider, VCO, LA and CDR design are presented using static divider, 50-100 GHz VCO and 100Gb/s LA+CDR circuits......This thesis is a continuation of the effort to increase the bandwidth of communicationnetworks. The thesis presents the results of the design of several high-speed electrical ircuits for an electrical/optical interface. These circuits have been a contribution to the ESTA project in collaboration...... circuits at the receiver interface, though VCOs are also found in the transmitter where a multitude of independent sources have to be mutually synchronized before multiplexing. The circuits are based on an InP DHBT process (VIP-2) supplied by Vitesse and made publicly available as MPW. The VIP-2 process...

  4. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  5. Review of CMOS Integrated Circuit Technologies for High-Speed Photo-Detection.

    Science.gov (United States)

    Jeong, Gyu-Seob; Bae, Woorham; Jeong, Deog-Kyoon

    2017-08-25

    The bandwidth requirement of wireline communications has increased exponentially because of the ever-increasing demand for data centers and high-performance computing systems. However, it becomes difficult to satisfy the requirement with legacy electrical links which suffer from frequency-dependent losses due to skin effects, dielectric losses, channel reflections, and crosstalk, resulting in a severe bandwidth limitation. In order to overcome this challenge, it is necessary to introduce optical communication technology, which has been mainly used for long-reach communications, such as long-haul networks and metropolitan area networks, to the medium- and short-reach communication systems. However, there still remain important issues to be resolved to facilitate the adoption of the optical technologies. The most critical challenges are the energy efficiency and the cost competitiveness as compared to the legacy copper-based electrical communications. One possible solution is silicon photonics which has long been investigated by a number of research groups. Despite inherent incompatibility of silicon with the photonic world, silicon photonics is promising and is the only solution that can leverage the mature complementary metal-oxide-semiconductor (CMOS) technologies. Silicon photonics can be utilized in not only wireline communications but also countless sensor applications. This paper introduces a brief review of silicon photonics first and subsequently describes the history, overview, and categorization of the CMOS IC technology for high-speed photo-detection without enumerating the complex circuital expressions and terminologies.

  6. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2007-09-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  7. A fully integral, differential, high-speed, low-power consumption CMOS recovery clock circuit

    Directory of Open Access Journals (Sweden)

    Daniel Pacheco Bautista

    2010-04-01

    Full Text Available The clock recovery circuit (CRC plays a fundamental role in electronic information recovery systems (hard disks, DVD and CD read/writeable units and baseband digital communication systems in recovering the clock signal contained in the received data. This signal is necessary for synchronising subsequent information processing. Nowadays, this task is difficult to achieve because of the data’s random nature and its high transfer rate. This paper presents the design of a high-performance integral CMOS technology clock recovery circuit (CRC wor-king at 1.2 Gbps and only consuming 17.4 mW using a 3.3V power supply. The circuit was fully differentially designed to obtain high performance. Circuit architecture was based on a conventional phase lock loop (PLL, current mode logic (MCML and a novel two stage ring-based voltage controlled oscillator (VCO. The design used 0.35 μm CMOS AMS process parameters. Hspice simulation results proved the circuit’s high performance, achieving tracking in less than 300 ns.

  8. Design of a high-speed vertical transition in LTCC for interposers suitable for packaging photonic integrated circuits

    Science.gov (United States)

    Jezzini, M. A.; Marraccini, P. J.; Peters, F. H.

    2016-05-01

    The packaging of high speed Photonic Integrated Circuits (PICs) should maintain the electrical signal integrity. The standard packaging of high speed PICs relies on wire bonds. This is not desirable because wire bonds degrade the quality of the electrical signal. The research presented in this paper proposes to replace wire bonds with an interposer with multilevel transmission lines. By attaching the PIC by flip chip onto the interposer, the use of wire bonds is avoided. The main concern for designing an interposer with multilevel transmission lines is the vertical transition, which must be designed to avoid return and radiation losses. In this paper, a novel design of a high speed vertical transition for Low Temperature Co-fired Ceramic (LTCC) is presented. The proposed vertical transition is simpler than others recently published in the literature, due to eliminating the need for additional ceramic layers or air cavities. A LTCC board was fabricated with several variations of the presented transition to find the optimal dimensions of the structure. The structures were fabricated then characterized and have a 3 dB bandwidth of 37 GHz and an open eye diagram at 44 Gbps. A full wave electromagnetic simulation is described and compared with good agreement to the measurements. The results suggest that an LTCC board with this design can be used for 40 Gbps per channel applications. Keywords: Photonics packaging, Low Temperature Co-Fired Ceramics.

  9. Development of high speed integrated circuit for very high resolution timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Mester, Christian

    2009-10-15

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  10. High-speed coherent silicon modulator module using photonic integrated circuits: from circuit design to packaged module

    Science.gov (United States)

    Bernabé, S.; Olivier, S.; Myko, A.; Fournier, M.; Blampey, B.; Abraham, A.; Menezo, S.; Hauden, J.; Mottet, A.; Frigui, K.; Ngoho, S.; Frigui, B.; Bila, S.; Marris-Morini, D.; Pérez-Galacho, D.; Brindel, P.; Charlet, G.

    2016-05-01

    Silicon photonics technology is an enabler for the integration of complex circuits on a single chip, for various optical link applications such as routing, optical networks on chip, short range links and long haul transmitters. Quadrature Phase Shift Keying (QPSK) transmitters is one of the typical circuits that can be achieved using silicon photonics integrated circuits. The achievement of 25GBd QPSK transmitter modules requires several building blocks to be optimized: the pn junction used to build a BPSK (Binary Shift Phase Keying) modulator, the RF access and the optical interconnect at the package level. In this paper, we describe the various design steps of a BPSK module and the related tests that are needed at every stage of the fabrication process.

  11. Inkjet-printing-based soft-etching technique for high-speed polymer ambipolar integrated circuits.

    Science.gov (United States)

    Khim, Dongyoon; Baeg, Kang-Jun; Kang, Minji; Lee, Seung-Hoon; Kim, Nam-Koo; Kim, Jihong; Lee, Geon-Woong; Liu, Chuan; Kim, Dong-Yu; Noh, Yong-Young

    2013-12-11

    Here, we report the so-called soft-etching process based on an inkjet-printing technique for realizing high-performance printed and flexible organic electronic circuits with conjugated polymer semiconductors. The soft-etching process consists of selective etching of the gate made of a dielectric polymer and deposition of another gate dielectric layer. The method enables the use of a more desirable polymer dielectric layer for the p-channel and n-channel organic field-effect transistors (OFETs) in complementary integrated circuits. We fabricated high-performance ambipolar complementary inverters and ring oscillators (ROs) using poly([N,N'-bis(2-octyldodecyl)-naphthalene-1,4,5,8-bis(dicarboximide)-2,6-diyl]-alt-5,5'-(2,2'-bithiophene)) (P(NDI2OD-T2)) as the active layer as well as poly(vinylidenefluoride-trifluoroethylene) (P(VDF-TrFE)) and polystyrene ((PS)/P(VDF-TrFE)) as dielectric materials for the p-channel (pull-up transistor) and n-channel (pull-down transistor) OFETs, respectively. The PS dielectric polymer was selectively etched by inkjetting of n-butyl acetate as an orthogonal solvent for P(NDI2OD-T2). Employing this methodology, the five-stage ambipolar ROs with P(NDI2OD-T2) exhibited an oscillation frequency of ∼16.7 kHz, which was much higher than that of non-soft-etched ROs with a single dielectric layer (P(VDF-TrFE); ∼3 kHz).

  12. High-speed logic integrated circuits with solution-processed self-assembled carbon nanotubes

    Science.gov (United States)

    Han, Shu-Jen; Tang, Jianshi; Kumar, Bharat; Falk, Abram; Farmer, Damon; Tulevski, George; Jenkins, Keith; Afzali, Ali; Oida, Satoshi; Ott, John; Hannon, James; Haensch, Wilfried

    2017-09-01

    As conventional monolithic silicon technology struggles to meet the requirements for the 7-nm technology node, there has been tremendous progress in demonstrating the scalability of carbon nanotube field-effect transistors down to the size that satisfies the 3-nm node and beyond. However, to date, circuits built with carbon nanotubes have overlooked key aspects of a practical logic technology and have stalled at simple functionality demonstrations. Here, we report high-performance complementary carbon nanotube ring oscillators using fully manufacturable processes, with a stage switching frequency of 2.82 GHz. The circuit was built on solution-processed, self-assembled carbon nanotube arrays with over 99.9% semiconducting purity, and the complementary feature was achieved by employing two different work function electrodes.

  13. High performance multi-channel high-speed I/O circuits

    CERN Document Server

    Oh, Taehyoun

    2013-01-01

    This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancel

  14. High-Speed-/-Hypersonic-Weapon-Development-Tool Integration

    National Research Council Canada - National Science Library

    Duchow, Erin M; Munson, Michael J; Alonge, Jr, Frank A

    2006-01-01

    Multiple tools exist to aid in the design and evaluation of high-speed weapons. This paper documents efforts to integrate several existing tools, including the Integrated Hypersonic Aeromechanics Tool (IHAT)1-7...

  15. Analysis of Hybrid-Integrated High-Speed Electro-Absorption Modulated Lasers Based on EM/Circuit Co-simulation

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Krozer, Viktor; Kazmierski, C.

    2009-01-01

    An improved electromagnetic simulation (EM) based approach has been developed for optimization of the electrical to optical (E/O) transmission properties of integrated electro-absorption modulated lasers (EMLs) aiming at 100 Gbit/s Ethernet applications. Our approach allows for an accurate analysis...

  16. Very High Speed Integrated Circuits (VHSIC).

    Science.gov (United States)

    1987-12-31

    basis. The workshops provided comprehensive training and education in VHSIC technology for defense contractor personnel for the purpose of...lrit (VHSJC) -’-TheA CoRScj ivclude appontdact the submitted to ONO~ foe review under Tecnology Security pw ti fo DAtCuclicld ru~lclause section 1504

  17. Design-for-Delay Testability Techniques for High-Speed Digital Circuits

    NARCIS (Netherlands)

    Vermaak, H.J.

    2005-01-01

    The importance of delay faults is enhanced by the ever increasing clock rates and decreasing geometry sizes of nowadays’ circuits. This thesis focuses on the development of Design-for-Delay-Testability (DfDT) techniques for high-speed circuits and embedded cores. The rising costs of IC testing and

  18. Response characteristic of high-speed on/off valve with double voltage driving circuit

    Science.gov (United States)

    Li, P. X.; Su, M.; Zhang, D. B.

    2017-07-01

    High-speed on/off valve, an important part of turbocharging system, its quick response has a direct impact on the turbocharger pressure cycle. The methods of improving the response characteristic of high speed on/off valve include increasing the magnetic force of armature and the voltage, decreasing the mass and current of coil. The less coil number of turns, the solenoid force is smaller. The special armature structure and the magnetic material will raise cost. In this paper a new scheme of double voltage driving circuit is investigated, in which the original driving circuit of high-speed on/off valve is replaced by double voltage driving circuit. The detailed theoretical analysis and simulations were carried out on the double voltage driving circuit, it showed that the switching time and delay time of the valve respectively are 3.3ms, 5.3ms, 1.9ms and 1.8ms. When it is driven by the double voltage driving circuit, the switching time and delay time of this valve are reduced, optimizing its response characteristic. By the comparison related factors (such as duty cycle or working frequency) about influences on response characteristic, the superior of double voltage driving circuit has been further confirmed.

  19. Preliminary results from the High Speed Airframe Integration Research project

    Science.gov (United States)

    Coen, Peter G.; Sobieszczanski-Sobieski, Jaroslaw; Dollyhigh, Samuel M.

    1992-01-01

    A review is presented of the accomplishment of the near term objectives of developing an analysis system and optimization methods during the first year of the NASA Langley High Speed Airframe Integration Research (HiSAIR) project. The characteristics of a Mach 3 HSCT transport have been analyzed utilizing the newly developed process. In addition to showing more detailed information about the aerodynamic and structural coupling for this type of vehicle, this exercise aided in further refining the data requirements for the analysis process.

  20. An Integrated Hardware Array for Very High Speed Logic Simulation

    Directory of Open Access Journals (Sweden)

    E. Scott Fehr

    1996-01-01

    boolean evaluation and fanout switching circuits, while large scale parallelism is integrated at die level to reduce cost and communication delays. The results of this research form the basis for a multiple order of magnitude improvement in reported state-of-the-art cost-performance merit for hardware gate level simulation accelerators.

  1. Integration and test of high-speed transmitter electronics for free-space laser communications

    Science.gov (United States)

    Soni, Nitin J.; Lizanich, Paul J.

    1994-01-01

    The NASA Lewis Research Center in Cleveland, Ohio, has developed the electronics for a free-space, direct-detection laser communications system demonstration. Under the High-Speed Laser Integrated Terminal Electronics (Hi-LITE) Project, NASA Lewis has built a prototype full-duplex, dual-channel electronics transmitter and receiver operating at 325 megabit S per second (Mbps) per channel and using quaternary pulse-position modulation (QPPM). This paper describes the integration and testing of the transmitter portion for future application in free-space, direct-detection laser communications. A companion paper reviews the receiver portion of the prototype electronics. Minor modifications to the transmitter were made since the initial report on the entire system, and this paper addresses them. The digital electronics are implemented in gallium arsenide integrated circuits mounted on prototype boards. The fabrication and implementation issues related to these high-speed devices are discussed. The transmitter's test results are documented, and its functionality is verified by exercising all modes of operation. Various testing issues pertaining to high-speed circuits are addressed. A description of the transmitter electronics packaging concludes the paper.

  2. Signal Integrity Analysis of High-Speed Interconnects

    CERN Document Server

    Oltean Karlsson, A

    2007-01-01

    LHC detectors and future experiments will produce very large amount of data that will be transferred at multi-Gigabit speeds. At such data rates, signal-integrity effects become important and traditional rules of thumb are no longer enough for the design and layout of the traces. Simulations for signal-integrity effects at board level provide a way to study and validate several scenarios before arriving at a set of optimized design rules prior to building the actual printed circuit board (PCB). This article describes some of the available tools at CERN. Two case studies will be used to highlight the capabilities of these programs.

  3. Efficient modeling of interconnects and capacitive discontinuities in high-speed digital circuits. Thesis

    Science.gov (United States)

    Oh, K. S.; Schutt-Aine, J.

    1995-01-01

    Modeling of interconnects and associated discontinuities with the recent advances high-speed digital circuits has gained a considerable interest over the last decade although the theoretical bases for analyzing these structures were well-established as early as the 1960s. Ongoing research at the present time is focused on devising methods which can be applied to more general geometries than the ones considered in earlier days and, at the same time, improving the computational efficiency and accuracy of these methods. In this thesis, numerically efficient methods to compute the transmission line parameters of a multiconductor system and the equivalent capacitances of various strip discontinuities are presented based on the quasi-static approximation. The presented techniques are applicable to conductors embedded in an arbitrary number of dielectric layers with two possible locations of ground planes at the top and bottom of the dielectric layers. The cross-sections of conductors can be arbitrary as long as they can be described with polygons. An integral equation approach in conjunction with the collocation method is used in the presented methods. A closed-form Green's function is derived based on weighted real images thus avoiding nested infinite summations in the exact Green's function; therefore, this closed-form Green's function is numerically more efficient than the exact Green's function. All elements associated with the moment matrix are computed using the closed-form formulas. Various numerical examples are considered to verify the presented methods, and a comparison of the computed results with other published results showed good agreement.

  4. Integrated design and manufacturing for the high speed civil transport

    Science.gov (United States)

    Lee, Jae Moon; Gupta, Anurag; Mueller, Craig; Morrisette, Monica; Dec, John; Brewer, Jason; Donofrio, Kevin; Sturisky, Hilton; Smick, Doug; An, Meng Lin

    1994-01-01

    In June 1992, the School of Aerospace Engineering at Georgia Tech was awarded a three year NASA University Space Research Association (USRA) Advanced Design Program (ADP) grant to address issues associated with the Integrated Design and Manufacturing of High Speed Civil Transport (HSCT) configurations in its graduate Aerospace Systems Design courses. This report provides an overview of the on-going Georgia Tech initiative to address these design/manufacturing issues during the preliminary design phases of an HSCT concept. The new design methodology presented here has been incorporated in the graduate aerospace design curriculum and is based on the concept of Integrated Product and Process Development (IPPD). The selection of the HSCT as a pilot project was motivated by its potential global transportation payoffs; its technological, environmental, and economic challenges; and its impact on U.S. global competitiveness. This pilot project was the focus of each of the five design courses that form the graduate level aerospace systems design curriculum. This year's main objective was the development of a systematic approach to preliminary design and optimization and its implementation to an HSCT wing/propulsion configuration. The new methodology, based on the Taguchi Parameter Design Optimization Method (PDOM), was established and was used to carry out a parametric study where various feasible alternative configurations were evaluated. The comparison criterion selected for this evaluation was the economic impact of this aircraft, measured in terms of average yield per revenue passenger mile ($/RPM).

  5. Compact, high-speed algorithm for laying out printed circuit board runs

    Science.gov (United States)

    Zapolotskiy, D. Y.

    1985-09-01

    A high speed printed circuit connection layout algorithm is described which was developed within the framework of an interactive system for designing two-sided printed circuit broads. For this reason, algorithm speed was considered, a priori, as a requirement equally as important as the inherent demand for minimizing circuit run lengths and the number of junction openings. This resulted from the fact that, in order to provide psychological man/machine compatibility in the design process, real-time dialog during the layout phase is possible only within limited time frames (on the order of several seconds) for each circuit run. The work was carried out for use on an ARM-R automated work site complex based on an SM-4 minicomputer with a 32K-word memory. This limited memory capacity heightened the demand for algorithm speed and also tightened data file structure and size requirements. The layout algorithm's design logic is analyzed. The structure and organization of the data files are described.

  6. High-speed bridge circuit for InGaAs avalanche photodiode single-photon detector

    Science.gov (United States)

    Hashimoto, Hirofumi; Tomita, Akihisa; Okamoto, Atsushi

    2014-02-01

    Because of low power consumption and small footprint, avalanche photodiodes (APD) have been commonly applied to photon detection. Recently, high speed quantum communication has been demonstrated for high bit-rate quantum key distribution. For the high speed quantum communication, photon detectors should operate at GHz-clock frequencies. We propose balanced detection circuits for GHz-clock operation of InGaAs-APD photon detectors. The balanced single photon detector operates with sinusoidal wave gating. The sinusoidal wave appearing in the output is removed by the subtraction from APD signal without sharp band-elimination filters. Omission of the sharp filters removes the constraint on the operating frequency of the single photon detector. We present two designs, one works with two identical APDs, the other with one APD and a low-pass filter. The sinusoidal gating enables to eliminate the gating noise even with the simple configuration of the latter design. We demonstrated the balanced single photon detector operating with 1.020GHz clock at 233 K, 193 K, and 186.5 K. The dark count probability was 4.0 x 10-4 counts/pulse with the quantum efficiency of 10% at 233K, and 1.6 x 10-4 counts/pulse at 186.5 K. These results were obtained with easily available APDs (NR8300FP-C.C, RENESASS) originally developed for optical time-domain reflectmeters.

  7. Non-contact Real-time heart rate measurements based on high speed circuit technology research

    Science.gov (United States)

    Wu, Jizhe; Liu, Xiaohua; Kong, Lingqin; Shi, Cong; Liu, Ming; Hui, Mei; Dong, Liquan; Zhao, Yuejin

    2015-08-01

    In recent years, morbidity and mortality of the cardiovascular or cerebrovascular disease, which threaten human health greatly, increased year by year. Heart rate is an important index of these diseases. To address this status, the paper puts forward a kind of simple structure, easy operation, suitable for large populations of daily monitoring non-contact heart rate measurement. In the method we use imaging equipment video sensitive areas. The changes of light intensity reflected through the image grayscale average. The light change is caused by changes in blood volume. We video the people face which include the sensitive areas (ROI), and use high-speed processing circuit to save the video as AVI format into memory. After processing the whole video of a period of time, we draw curve of each color channel with frame number as horizontal axis. Then get heart rate from the curve. We use independent component analysis (ICA) to restrain noise of sports interference, realized the accurate extraction of heart rate signal under the motion state. We design an algorithm, based on high-speed processing circuit, for face recognition and tracking to automatically get face region. We do grayscale average processing to the recognized image, get RGB three grayscale curves, and extract a clearer pulse wave curves through independent component analysis, and then we get the heart rate under the motion state. At last, by means of compare our system with Fingertip Pulse Oximeter, result show the system can realize a more accurate measurement, the error is less than 3 pats per minute.

  8. Circuit techniques for low-voltage and high-speed A/D converters

    OpenAIRE

    Waltari, Mikko

    2002-01-01

    The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brin...

  9. Integrated High-Speed Digital Optical True-Time-Delay Modules for Synthetic Aperture Radars Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Crystal Research, Inc. proposes an integrated high-speed digital optical true-time-delay module for advanced synthetic aperture radars. The unique feature of this...

  10. Few-layer molybdenum disulfide transistors and circuits for high-speed flexible electronics.

    Science.gov (United States)

    Cheng, Rui; Jiang, Shan; Chen, Yu; Liu, Yuan; Weiss, Nathan; Cheng, Hung-Chieh; Wu, Hao; Huang, Yu; Duan, Xiangfeng

    2014-10-08

    Two-dimensional layered materials, such as molybdenum disulfide, are emerging as an exciting material system for future electronics due to their unique electronic properties and atomically thin geometry. Here we report a systematic investigation of MoS2 transistors with optimized contact and device geometry, to achieve self-aligned devices with performance including an intrinsic gain over 30, an intrinsic cut-off frequency fT up to 42 GHz and a maximum oscillation frequency fMAX up to 50 GHz, exceeding the reported values for MoS2 transistors to date (fT~0.9 GHz, fMAX~1 GHz). Our results show that logic inverters or radio frequency amplifiers can be formed by integrating multiple MoS2 transistors on quartz or flexible substrates with voltage gain in the gigahertz regime. This study demonstrates the potential of two-dimensional layered semiconductors for high-speed flexible electronics.

  11. Research on the modeling of the impedance match bond at station track circuit in Chinese high-speed railway

    Directory of Open Access Journals (Sweden)

    Shiwu Yang

    2015-11-01

    Full Text Available Frequency-shift keying audio jointless track circuit is used in high-speed railway in China. However, within the station, track circuit with mechanical insulation is applied. In complex circuit network of electrified railway station, impedance match bond is designed to ensure the normal operation of the track circuit and the protection of strong traction current interference. As a combination of strong and weak electricity components of track circuit, impedance match bond is both the part of the loop of the traction current and the part of the transmission line of track circuit, playing a very critical role in the electrified railway. The structure of impedance match bond is more complex than traditional impedance transformer, including the transformer with larger air-gap, LC resonance circuit for power frequency filtering, and components to enhance the signal frequency. Modeling on impedance match bond and study about the four-terminal network parameters of impedance match bond are in favor of the following two aspects: modeling of the overall traction current and calculation of track circuit working condition. By applying the transformer equivalent circuit model and combination of testing and calculation, the accurate model of impedance match bond is constructed and verified. Finally, for ease of track circuit calculation, four-terminal network model of impedance match bond under different signal carrier frequencies is presented.

  12. Life Cycle Cost Model for Very High Speed Integrated Circuits.

    Science.gov (United States)

    1984-09-01

    8217. . % .** .** % * * * * .... * ... *..* * * *........ . . . - .. - . . . . . ."" r -7 TOCI / EQ 1. 12. 13. Pt1R2 I 357585. 84200. 441786.SBITm L (m) 357588. 84901. 442489. IOML CST 357638. 85040. 442678. COST

  13. Very High Speed Integrated Circuits - VHSIC - Final Program Repoort

    Science.gov (United States)

    1990-09-30

    contracts. The descriptions delivered by IBM contained non-standard, VI-DL ANSI/iEEE- 1076 code; therefore, simulations were not run. 76 CHAPI E~R 3 1 I...advanced systerrs d-,ign when VHDL came about. Design tools applied to problems above the gate (implementation) level require hardware 215 CHAPi ,.R / I

  14. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  15. High speed bending of 2nd level interconnects on printed circuit boards for automotive electronics

    NARCIS (Netherlands)

    Kouters, M.H.M.; Ubachs, R.; Wiel, H.J. van de; Waal, A. van der; Veer, J. van der

    2011-01-01

    Standard drop tests for portable electronics are not representative for the qualification of automotive electronics. High-frequency vibrations are more dominant than abrupt shocks during normal operation. In this work a high speed board bending (HSB) method is developed to mimic the constant cyclic

  16. Design of a Low-Voltage High-Speed Switched-Capacitor Filters Using Improved Auto Zeroed Integrator

    Science.gov (United States)

    Rashtian, M.; Hashemipour, O.; Navi, K.

    The low-voltage high-speed auto zeroed integrator characteristics is improved by applying current steering mechanism in the opamp structure of the integrators and utilizing the non-linear properties of switches. The proposed design results in considerable reduction of power dissipation. Based on this improvement a band-pass filter with centre frequency of 1 MHz and clock frequency of 6 MHz is designed. Furthermore a new circuit for implementation of an auto-zero low-pass filter is presented. Based on this configuration a fourth order low-pass switched capacitor filter with cut off frequency of 600 KHz and clock frequency of 6 MHz is presented. The proposed circuits are simulated using HSPICE and 0.25 μm CMOS technology at 1.5 V supply voltage.

  17. An On-Chip Memory for Testing of High-Speed Mixed-Signal Circuits

    OpenAIRE

    Omar, Omar Jaber

    2013-01-01

    Mixed-signal processing systems especially data converters can be reliably tested at high frequencies using on-chip testing schemes based on memory. In this thesis, an on-chip testing strategy based on shift registers/memory (2 k bits) has been proposed for digital-to-analog converters (DACs) operating at 5 GHz. The proposed design uses word length of 8 bits in order to test DAC at high speed of 5 GHz. The proposed testing strategy has been designed in standard 65 nm CMOS technology with addi...

  18. Performance Analysis of Modified Drain Gating Techniques for Low Power and High Speed Arithmetic Circuits

    Directory of Open Access Journals (Sweden)

    Shikha Panwar

    2014-01-01

    Full Text Available This paper presents several high performance and low power techniques for CMOS circuits. In these design methodologies, drain gating technique and its variations are modified by adding an additional NMOS sleep transistor at the output node which helps in faster discharge and thereby providing higher speed. In order to achieve high performance, the proposed design techniques trade power for performance in the delay critical sections of the circuit. Intensive simulations are performed using Cadence Virtuoso in a 45 nm standard CMOS technology at room temperature with supply voltage of 1.2 V. Comparative analysis of the present circuits with standard CMOS circuits shows smaller propagation delay and lesser power consumption.

  19. Wireless and photonic high-speed communication technologies, circuits and design tools

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Jiang, Chenhui

    2009-01-01

    were reported. These communication systems present new challenges for circuit designers. The presentation will be devoted to technologies and various aspects of circuit design for 100 G applications. We will present overview on wired and wireless systems demonstrating the challenges of this research...... are fundamental to emerging consumer and professional applications. These systems start to emerge as near future applications and are subject of ongoing research activities in Europe, for example within the EU FP6 GIBON project. Wireless systems with over 100 GHz carriers as well as first over 100-G fibre systems...... including design challenges, relevant trade-offs and the present bottlenecks. Different system architectures will be presented with their impact on component requirements. Similarities and differences of wired and wireless applications will be pointed out. Design methodologies, necessary tools and circuit...

  20. Liquid-Si Technology for High-Speed Circuits on Flexible Substrates

    NARCIS (Netherlands)

    Zhang, J.

    2015-01-01

    Recently, flexible, wearable and disposable electronics have attracted a lot of attention. Printing enables low-cost fabrication of circuits on flexible substrates. Printed organic and metal oxide thin-film transistors (TFTs) have been researched intensively due to the ease of solution-processing.

  1. Proposal for the award of a contract for the provision of a high-speed data circuit to the USA

    CERN Document Server

    2001-01-01

    This document concerns the award of a contract for a high-speed data circuit for Wide Area Network (WAN) connectivity between CERN and the STARLIGHT Internet exchange in Chicago, USA. The contract will be negotiated on behalf of CERN and its partners, CNRS/IN2P3 (FR), the US Department of Energy (DoE) through the California Institute of Technology (Caltech), the US National Science Foundation (NSF), the Canadian high-energy physics community through Carleton University and the World Health Organisation in Geneva. Following a market survey carried out among 26 firms in nine Member States and three firms in the USA, a call for tenders (IT-2983/IT) was sent on 7 September 2001 to 17 firms in eight Member States. By the closing date, CERN had received 13 tenders from eight Member States. The Finance Committee is invited to agree to the negotiation, on behalf of CERN and its partners, of a contract for the provision of a high-speed data circuit to the USA, with KPNQWEST (NL), the lowest bidder (after realignment),...

  2. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  3. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  4. Control method of high-speed switched reluctance motor with an asymmetric rotor magnetic circuit

    Directory of Open Access Journals (Sweden)

    Bogusz Piotr

    2016-12-01

    Full Text Available In the paper, the modified (compared to the classical asymmetric half-bridge converter for a switched reluctance machine with an asymmetric rotor magnetic circuit was analysed. An analysis for two various structures of switched reluctance motors was conducted. The rotor shaping was used to obtain required start-up torque or/and to obtain less electromagnetic torque ripple. The discussed converter gives a possibility to turn a phase off much later while reduced time of a current flows in a negative slope of inductance. The results of the research in the form of waveforms of currents, voltages and electromagnetic torque were presented. Conclusions were formulated concerning the comparison of the characteristics of SRM supplied by the classic converter and by the one supplied by the analysed converter.

  5. Design and implementation of interface units for high speed fiber optics local area networks and broadband integrated services digital networks

    Science.gov (United States)

    Tobagi, Fouad A.; Dalgic, Ismail; Pang, Joseph

    1990-01-01

    The design and implementation of interface units for high speed Fiber Optic Local Area Networks and Broadband Integrated Services Digital Networks are discussed. During the last years, a number of network adapters that are designed to support high speed communications have emerged. This approach to the design of a high speed network interface unit was to implement package processing functions in hardware, using VLSI technology. The VLSI hardware implementation of a buffer management unit, which is required in such architectures, is described.

  6. High-Speed Burst-Mode Clock and Data Recovery Circuits for Multiaccess Networks

    Science.gov (United States)

    Shastri, Bhavin J.

    Optical multiaccess networks, and specifically passive optical networks (PONs) are considered to be the most promising technologies for the deployment of fiber-to-the-premises/home/user (FTTx) to solve the problem of limited bandwidth in local area networks with a low-cost solution and a guaranteed quality of service. In a PON, multiple users share the fiber infrastructure in a point-to-multipoint (P2MP) network. This topology introduce optical path delays which inherently cause the data packets to undergo amplitude variations up to 20 dB and phase variations from --2pi to +2pi rad--burst-mode traffic. Consequently, this creates new challenges for the design and test of optical receivers front-ends and clock and data recovery circuits (CDRs), in particular, burst-mode CDRs (BM-CDRs). The research presented in this thesis investigates BM-CDRs, both theoretically and experimentally. We demonstrate two novel BM-CDR architectures. These BM-CDRs achieve error-free operation [bit error rate (BER) <10e--10] while providing instantaneous (0 preamble bit) clock phase acquisition for any phase step (+/-2pi rad) between successive bursts. Instantaneous phase acquisition improves the physical efficiency of upstream PON traffic, and increases the effective throughput of the system by raising the information rate. Our eloquent, scalable BM-CDR architectures leverage the design of low complexity commercial electronics providing a cost-effective solution for PONs. The first BM-CDR (rated at 5 Gb/s) is based on phase-tracking time domain oversampling (semiblind) CDR operated at 2x the bit rate and a clock phase aligner (CPA) that makes use of a phase picking algorithm. The second BM-CDR (rate at 10 Gb/s) is based on semiblind space domain oversampling and employs a phase-tracking CDR with multiphase clocks at the bit rate and a CPA with a novel phase picking algorithm. We experimentally demonstrate these BM-CDRs in optical test beds and study the effect of channel-impairments in

  7. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  8. High-speed pulse techniques

    CERN Document Server

    Coekin, J A

    1975-01-01

    High-Speed Pulse Techniques covers the many aspects of technique in digital electronics and encompass some of the more fundamental factors that apply to all digital systems. The book describes the nature of pulse signals and their deliberate or inadvertent processing in networks, transmission lines and transformers, and then examines the characteristics and transient performance of semiconductor devices and integrated circuits. Some of the problems associated with the assembly of these into viable systems operating at ultra high speed are also looked at. The book examines the transients and w

  9. High Speed Propulsion: Engine Design - Integration and Thermal Management (Propulsion a vitesse elevee : Conception du moteur - integration et gestion thermique)

    Science.gov (United States)

    2010-09-01

    Sep 2010 High Speed Propulsion: Engine Design - Integration and Thermal Management (Propulsion à vitesse élevée : Conception du moteur - intégration... moteur - intégration et gestion thermique) the von Karman Institute, Rhode St. Genèse, Belgium, 13-16 September 2010. High Speed Propulsion: Engine...Conception du moteur – Intégration et gestion thermique (RTO-EN-AVT-185) Synthèse Les systèmes hypersoniques vont provoquer une révolution dans

  10. High-speed measurement of single-electron circuits at low temperatures with bolometric and calorimetric applications

    Science.gov (United States)

    Swenson, Loren

    2007-12-01

    This thesis consists primarily of the description of two single-electron circuits that I fabricated and measured utilizing radio-frequency techniques. A short summary of the background material necessary for understanding this area of condensed matter experiment is included as well as a discussion of the utility of these devices as charge-sensing or energy-sensing circuit elements. In the first measurement, by configuring a radio-frequency single-electron transistor as a mixer, we demonstrate a unique implementation of this device, that achieves good charge sensitivity with large bandwidth about a tunable center frequency. In our implementation we achieve a measurement bandwidth of 16 MHz, with a tunable center frequency from 0 to 1.2 GHz, demonstrated with the transistor operating at 300 mK. Ultimately this device is limited in center frequency by the RC time of the transistor's center island, which for our device is ˜1.6 GHz, close to the measured value. The measurement bandwidth is determined by the quality factor of the readout tank circuit. In the second measurement, we detect the energy-selective diffusion of electrons through a tunnel junction to perform a new type of passive, low-power dissipation thermometry. The thermometer is based on a novel, three-junction single electron transistor, which is made with a superconducting nanoscale metal island, coupled to two tunnel junctions and a capacitive gate in the standard single-electron transistor configuration, and in addition a third tunnel junction couples the transistor island to a normal metal thin-film volume, which serves as a calorimeter. Passive diffusion of electrons from the calorimeter through the third junction changes the transistor conductance, providing a thermometric signal. This device dissipates minimal power in the calorimeter, removing a stringent limit on the minimum temperatures and energy sensitivities achievable in nanoscale calorimeters and bolometers. High speed measurements were

  11. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  12. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  13. High power CO2 laser development with AOM integration for ultra high-speed pulses

    Science.gov (United States)

    Bohrer, Markus; Vaupel, Matthias; Nirnberger, Robert; Weinberger, Bernhard; Jamalieh, Murad

    2017-01-01

    There is a 500 billion USD world market for packaging expected to grow to a trillion in 2030. Austria plays an important role world wide for high speed laser engraving applications — especially when it comes to high end solutions. Such high end solutions are fundamental for the production of print forms for the packaging and decorating industry (e. g. cans). They are additionally used for security applications (e. g. for printing banknotes), for the textile printing industry and for creating embossing forms (e. g. for the production of dashboards in the automotive industry). High speed, high precision laser engraving needs laser resonators with very stable laser beams (400 - 800W) especially in combination with AOMs. Based upon a unique carbon fiber structure - stable within the sub-micrometer range - a new resonator has been developed, accompanied by most recent thermo-mechanical FEM calculations. The resulting beam is evaluated on an automated optical bench using hexapods, allowing to optimize the complete beam path with collimators and AOM. The major steps related to laser engraving of dry offset printing plates during the full workflow from the artists design to the printed result on an aluminum can is presented in this paper as well as laser characteristics, AOM integration and correlative CLSM and SEM investigation of the results.

  14. Fast nanotopography imaging using a high speed cantilever with integrated heater-thermometer.

    Science.gov (United States)

    Lee, Byeonghee; Somnath, Suhas; King, William P

    2013-04-05

    This paper presents a high speed tapping cantilever with an integrated heater-thermometer for fast nanotopography imaging. The cantilever is much smaller and faster than previous heated cantilevers, with a length of 35 μm and a resonant frequency of 1.4 MHz. The mechanical response time is characterized by scanning over a backward-facing step of height 20 nm. The mechanical response time is 77 μs in air and 448 μs in water, which compares favorably to the fastest commercial cantilevers that do not have integrated heaters. The doped silicon cantilever is designed with an integrated heater that can heat and cool in about 10 μs and can operate in both air and water. We demonstrate standard laser-based topography imaging along with thermal topography imaging, when the cantilever is actuated via the piezoelectric shaker in an atomic force microscope system and when it is actuated by Lorentz forces. The cantilever can perform thermal topography imaging in tapping mode with an imaging resolution of 7 nm at a scan speed of 1.46 mm s(-1).

  15. High speed heterostructure devices

    CERN Document Server

    Beer, Albert C; Willardson, R K; Kiehl, Richard A; Sollner, T C L Gerhard

    1994-01-01

    Volume 41 includes an in-depth review of the most important, high-speed switches made with heterojunction technology. This volume is aimed at the graduate student or working researcher who needs a broad overview andan introduction to current literature. Key Features * The first complete review of InP-based HFETs and complementary HFETs, which promise very low power and high speed * Offers a complete, three-chapter review of resonant tunneling * Provides an emphasis on circuits as well as devices.

  16. Thrust Augmentation by Airframe-Integrated Linear-Spike Nozzle Concept for High-Speed Aircraft

    Directory of Open Access Journals (Sweden)

    Hidemi Takahashi

    2018-02-01

    Full Text Available The airframe-integrated linear-spike nozzle concept applied to an external nozzle for high-speed aircraft was evaluated with regard to the thrust augmentation capability and the trim balance. The main focus was on the vehicle aftbody. The baseline airframe geometry was first premised to be a hypersonic waverider design. The baseline aftbody case had an external nozzle comprised of a simple divergent nozzle and was hypothetically replaced with linear-spike external nozzle configurations. Performance evaluation was mainly conducted by considering the nozzle thrust generated by the pressure distribution on the external nozzle surface at the aftbody portion calculated by computer simulation at a given cruise condition with zero angle of attack. The thrust performance showed that the proposed linear-spike external nozzle concept was beneficial in thrust enhancement compared to the baseline geometry because the design of the proposed concept had a compression wall for the exhaust flow, which resulted in increasing the wall pressure. The configuration with the boattail and the angled inner nozzle exhibited further improvement in thrust performance. The trim balance evaluation showed that the aerodynamic center location appeared as acceptable. Thus, benefits were obtained by employing the airframe-integrated linear-spike external nozzle concept.

  17. High speed gain coupled DFB laser diode integrated with MQW electroabsorption modulator

    CERN Document Server

    Kim, M G; Park, S S; Oh, D K; Lee, H T; Kim, H M; Pyun, K E

    1998-01-01

    We have demonstrated stable modulation characteristics of the gain coupled distributed feedback(GC-DFB) laser diode integrated with butt-coupled InGaAsP/InGaAsP strain compensated MQW(multiple-Quantum-well) modulator for high speed optical transmission. For this purpose, we have adopted the InGaAsP/InGaAsP strain compensated MQW structure for the EA modulator and n-doped InGaAs absorptive grating for DFB laser. The typical threshold current and slope efficiency were about 15 mA and 0.1 mW/mA, respectively. The extinction ratio of fabricated integrated device was about 15 dB at -2 V, and the small signal bandwidth was shown to be around 17GHz. We also found that the alpha parameter becomes negative at below a -0.6 V bias voltage. We transmitted 10 Gbps NRZ electrical signal over 90 km of standard single mode optical fiber (SMF). A clearly opened eye diagram was observed in the modulated output.

  18. Inlet Unstart Propulsion Integration Wind Tunnel Test Program Completed for High-Speed Civil Transport

    Science.gov (United States)

    Porro, A. Robert

    2000-01-01

    One of the propulsion system concepts to be considered for the High-Speed Civil Transport (HSCT) is an underwing, dual-propulsion, pod-per-wing installation. Adverse transient phenomena such as engine compressor stall and inlet unstart could severely degrade the performance of one of these propulsion pods. The subsequent loss of thrust and increased drag could cause aircraft stability and control problems that could lead to a catastrophic accident if countermeasures are not in place to anticipate and control these detrimental transient events. Aircraft system engineers must understand what happens during an engine compressor stall and inlet unstart so that they can design effective control systems to avoid and/or alleviate the effects of a propulsion pod engine compressor stall and inlet unstart. The objective of the Inlet Unstart Propulsion Airframe Integration test program was to assess the underwing flow field of a High-Speed Civil Transport propulsion system during an engine compressor stall and subsequent inlet unstart. Experimental research testing was conducted in the 10- by 10-Foot Supersonic Wind Tunnel at the NASA Glenn Research Center at Lewis Field. The representative propulsion pod consisted of a two-dimensional, bifurcated inlet mated to a live turbojet engine. The propulsion pod was mounted below a large flat plate that acted as a wing simulator. Because of the plate s long length (nominally 10-ft wide by 18-ft long), realistic boundary layers could form at the inlet cowl plane. Transient instrumentation was used to document the aerodynamic flow-field conditions during an unstart sequence. Acquiring these data was a significant technical challenge because a typical unstart sequence disrupts the local flow field for about only 50 msec. Flow surface information was acquired via static pressure taps installed in the wing simulator, and intrusive pressure probes were used to acquire flow-field information. These data were extensively analyzed to

  19. Synthetic biology: integrated gene circuits.

    Science.gov (United States)

    Nandagopal, Nagarajan; Elowitz, Michael B

    2011-09-02

    A major goal of synthetic biology is to develop a deeper understanding of biological design principles from the bottom up, by building circuits and studying their behavior in cells. Investigators initially sought to design circuits "from scratch" that functioned as independently as possible from the underlying cellular system. More recently, researchers have begun to develop a new generation of synthetic circuits that integrate more closely with endogenous cellular processes. These approaches are providing fundamental insights into the regulatory architecture, dynamics, and evolution of genetic circuits and enabling new levels of control across diverse biological systems.

  20. Prediction Of Limit Rotational Speeds In A High-Speed Tool Bason FE Computed J-Integral Intensitiesed

    DEFF Research Database (Denmark)

    Hvejsel, Bjørn; Langmack, Lasse; Kristensen, Anders

    2002-01-01

    In order to obtain an estimate of the critical number of rotations for a high speed milling tool crack growth analysis has been performed. The crack growth is determined from stress intensities computed by J-integrals. The problem is solved in 3D using ANSYS. Boundary conditions arising from a co...

  1. Contributions to understanding the high speed machining effects on aeronautic part surface integrity

    Science.gov (United States)

    Jomaa, Walid

    To remain competitive, the aeronautic industry has increasing requirements for mechanical components and parts with high functional performance and longer in-service life. The improvement of the in-service life of components can be achieved by mastering and optimizing the surface integrity of the manufactured parts. Thus, the present study attempted to investigate, experimentally and theoretically, the tool/work material interactions on part surface integrity during the machining of aluminium alloys and hardened materials (low alloy steels) using orthogonal machining tests data. The studied materials are two aluminum alloys (6061-T6 and 7075-T651) and AISI 4340 steel. The AISI 4340 steel was machined after been induction heat treated to 58-60 HRC. These materials were selected in an attempt to provide a comprehensive study for the machining of metals with different behaviours (ductile and hard material). The proposed approach is built on three steps. First, we proposed a design of experiment (DOE) to analyse, experimentally, the chip formation and the resulting surface integrity during the high speed machining under dry condition. The orthogonal cutting mode, adopted in these experiments, allowed to explore, theoretically, the effects of technological (cutting speed and feed) and physical (cutting forces, temperature, shear angle, friction angle, and length Contact tool/chip) parameters on the chip formation mechanisms and the machined surface characteristics (residual stress, plastic deformation, phase transformation, etc.). The cutting conditions were chosen while maintaining a central composite design (CCD) with two factors (cutting speed and feed per revolution). For the aluminum 7075-T651, the results showed that the formation of BUE and the interaction between the tool edge and the iron-rich intermetallic particles are the main causes of the machined surface damage. The BUE formation increases with the cutting feed while the increase of the cutting speed

  2. Integrated circuit cooled turbine blade

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  3. High speed and leakage-tolerant domino circuits for high fan-in applications in 70nm CMOS technology

    DEFF Research Database (Denmark)

    Moradi, Farshad; Wisland, Dag; Mahmoodi, Hamid

    with latter proposed circuit. According to simulations in a predictive 70 nm process, the proposed circuit increases noise immunity by more than 26X for wide OR gates and shows performance improvement of up to 20% compared to conventional domino logic circuits. The proposed circuit reduces the contention......This paper presents two proposed circuits that employ a footer transistor that is initially OFF in the evaluation phase to reduce leakage and then turned ON to complete the evaluation. Also a new circuit is added using a NAND gate that improves the performance more than 10% -15% compared...... between keeper transistor and NMOS evaluation transistors at the beginning of evaluation phase. High fan-in comparators and multiplexers demonstrate high noise immunity compared with previous proposed works....

  4. Inventory-transportation integrated optimization for maintenance spare parts of high-speed trains.

    Directory of Open Access Journals (Sweden)

    Boliang Lin

    Full Text Available This paper presents a 0-1 programming model aimed at obtaining the optimal inventory policy and transportation mode for maintenance spare parts of high-speed trains. To obtain the model parameters for occasionally-replaced spare parts, a demand estimation method based on the maintenance strategies of China's high-speed railway system is proposed. In addition, we analyse the shortage time using PERT, and then calculate the unit time shortage cost from the viewpoint of train operation revenue. Finally, a real-world case study from Shanghai Depot is conducted to demonstrate our method. Computational results offer an effective and efficient decision support for inventory managers.

  5. Inventory-transportation integrated optimization for maintenance spare parts of high-speed trains

    Science.gov (United States)

    Wang, Jiaxi; Wang, Huasheng; Wang, Zhongkai; Li, Jian; Lin, Ruixi; Xiao, Jie; Wu, Jianping

    2017-01-01

    This paper presents a 0–1 programming model aimed at obtaining the optimal inventory policy and transportation mode for maintenance spare parts of high-speed trains. To obtain the model parameters for occasionally-replaced spare parts, a demand estimation method based on the maintenance strategies of China’s high-speed railway system is proposed. In addition, we analyse the shortage time using PERT, and then calculate the unit time shortage cost from the viewpoint of train operation revenue. Finally, a real-world case study from Shanghai Depot is conducted to demonstrate our method. Computational results offer an effective and efficient decision support for inventory managers. PMID:28472097

  6. Inventory-transportation integrated optimization for maintenance spare parts of high-speed trains.

    Science.gov (United States)

    Lin, Boliang; Wang, Jiaxi; Wang, Huasheng; Wang, Zhongkai; Li, Jian; Lin, Ruixi; Xiao, Jie; Wu, Jianping

    2017-01-01

    This paper presents a 0-1 programming model aimed at obtaining the optimal inventory policy and transportation mode for maintenance spare parts of high-speed trains. To obtain the model parameters for occasionally-replaced spare parts, a demand estimation method based on the maintenance strategies of China's high-speed railway system is proposed. In addition, we analyse the shortage time using PERT, and then calculate the unit time shortage cost from the viewpoint of train operation revenue. Finally, a real-world case study from Shanghai Depot is conducted to demonstrate our method. Computational results offer an effective and efficient decision support for inventory managers.

  7. Variational integrators for electric circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ober-Blöbaum, Sina, E-mail: sinaob@math.upb.de [Computational Dynamics and Optimal Control, University of Paderborn (Germany); Tao, Molei [Courant Institute of Mathematical Sciences, New York University (United States); Cheng, Mulin [Applied and Computational Mathematics, California Institute of Technology (United States); Owhadi, Houman; Marsden, Jerrold E. [Control and Dynamical Systems, California Institute of Technology (United States); Applied and Computational Mathematics, California Institute of Technology (United States)

    2013-06-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator.

  8. Gallium arsenide integrated optical devices for high-speed diagnostic systems

    Energy Technology Data Exchange (ETDEWEB)

    McWright, G.; Lowry, M.; Takeuchi, E.; Murphy, G.; Tindall, W.; Koo, J.; Roeske, F.

    1987-01-01

    The design, fabrication, and evaluation of waveguide electro-optic modulators in gallium arsenide for application to high-speed diagnostic systems are discussed specifically. This paper is focused on high bandwidth, single event analog modulation, and radiation susceptibility of these devices.

  9. Integrated Seismic Survey for Detecting Landslide Effects on High Speed Rail Line at Istanbul–Turkey

    Directory of Open Access Journals (Sweden)

    Grit Mert

    2016-02-01

    Full Text Available In this study, Multichannel Analysis of Surface Waves Method (MASW, seismic refraction tomography and seismic reflection methods are used together at Silivri district in Istanbul – a district with a landslide problem because of the high speed rail line project crossing through the area. The landslide structure, border and depth of the slip plane are investigated and correlated within the local geology. According to the obtained 2D seismic sections, the landslide occurs through the East-West direction in the study area and the landslide slip plane with its border are clearly obtained under the subsurface. The results prove that the study area is suitable enough for the landslide development and this evolution also affects the high speed rail line project.

  10. Proposal to increase the amount of an existing contract for the provision of a high-speed data circuit to the USA

    CERN Document Server

    2003-01-01

    This document concerns the proposal to increase the authorized amount of an existing contract for the provision of a high-speed data circuit for Wide Area Network (WAN) connectivity between CERN and the STARLIGHT Internet Exchange in Chicago, USA. The extension will be negotiated by CERN on behalf of its partners, CNRS/IN2P3 (FR), the US Department of Energy (DoE) through the California Institute of Technology (Caltech), the US National Science Foundation (NSF), the Canadian high-energy physics community through the University of Victoria (Canada), the World Health Organization (WHO) in Geneva and the European Union funded DataTAG project. The Finance Committee is invited to approve the increase of the authorized amount of the existing contract with T-SYSTEMS INTERNATIONAL (DE) for the provision of a high-speed data circuit for an additional amount of 1 731 106 euros (2 596 660 Swiss francs), bringing the total authorized limit to 5 821 000 Swiss francs, not subject to revision. The amount in Swiss francs has...

  11. Invention of the Integrated Circuit

    Indian Academy of Sciences (India)

    Home; Journals; Resonance – Journal of Science Education; Volume 17; Issue 11. Invention of the Integrated Circuit. Jack S Kilby. Classics Volume 17 Issue 11 November 2012 pp 1100-1115. Fulltext. Click here to view fulltext PDF. Permanent link: http://www.ias.ac.in/article/fulltext/reso/017/11/1100-1115 ...

  12. Development of CMOS integrated circuits

    Science.gov (United States)

    Bertino, F.; Feller, A.; Greenhouse, J.; Lombardi, T.; Merriam, A.; Noto, R.; Ozga, S.; Pryor, R.; Ramondetta, P.; Smith, A.

    1979-01-01

    Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

  13. Bioluminescent bioreporter integrated circuits (BBICs)

    Science.gov (United States)

    Simpson, Michael L.; Sayler, Gary S.; Nivens, David; Ripp, Steve; Paulus, Michael J.; Jellison, Gerald E.

    1998-07-01

    As the workhorse of the integrated circuit (IC) industry, the capabilities of CMOS have been expanded well beyond the original applications. The full spectrum of analog circuits from switched-capacitor filters to microwave circuit blocks, and from general-purpose operational amplifiers to sub- nanosecond analog timing circuits for nuclear physics experiments have been implemented in CMOS. This technology has also made in-roads into the growing area of monolithic sensors with devices such as active-pixel sensors and other electro-optical detection devices. While many of the processes used for MEMS fabrication are not compatible with the CMOS IC process, depositing a sensor material onto a previously fabricated CMOS circuit can create a very useful category of sensors. In this work we report a chemical sensor composed of bioluminescent bioreporters (genetically engineered bacteria) deposited onto a micro-luminometer fabricated in a standard CMOS IC process. The bioreporter used for this work emitted 490-nm light when exposed to toluene. This luminescence was detected by the micro- luminometer giving an indication of the concentration of toluene. Other bioluminescent bioreporters sensitive to explosives, mercury, and other organic chemicals and heavy metals have been reported. These could be incorporated (individually or in combination) with the micro-luminometer reported here to form a variety of chemical sensors.

  14. A Close Loop Low-Power and High Speed 130 nm CMOS Sample and Hold Circuit Based on Switched Capacitor for ADC Module

    Science.gov (United States)

    Nasir, Z.; Ruslan, S. H.

    2017-08-01

    A sample and hold (S/H) block is typically used as an analogue to digital interface in the analogue to digital converter (ADC) system. Since ADC is widely used in processing signals, the power consumption of the ADC must be lowered to conserve energy. Therefore the S/H circuit must be of a low powered too. Sampling phase and hold phase are the two phases of the operation cycle of the S/H circuit. Switched capacitor (SC) techniques have been developed in order to allow the integration on a single silicon chip of both digital and analogue functions. By controlling switches around the SC, the SC circuit works by passing charge into and out of a capacitor. SC circuits are suitable for on chip implementations because they replace a resistor with switches and capacitors. In this research, a closed-loop sample and hold circuit based on SC is designed and simulated with Cadence EDA tools. The schematic, layout, and simulation of the circuit is done using generic Silterra 130 nm technology file. All the analysis is done using Virtuoso Analog Design Environment. Layout and schematic are drawn using Virtuoso Schematic Editor and Virtuoso Layout Editor, Calibre is used for post layout simulation. The closed loop S/H circuit based on SC is successfully designed and able to sample and hold the analogue input waveform. The power consumption of the circuit is 0.919 mW and the propagation delay is 64.96 ps.

  15. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt......This work presents several key aspects in the design of RF integrated circuits for portable multimedia devices. One chapter is dedicated to the application of negative-feedback topologies to receiver frontends. A novel feedback technique suitable for common multiplier-based mixers is described......-series feedback), showing a difference in compression point in the order of 10dBm for the same power consumption. The same principle is also applied to a more conventional narrow-band stage in which a single loop is employed in order to enhance noise performances. Noise analysis shows sensible improvements...

  16. Study of surface integrity AISI 4140 as result of hard, dry and high speed machining using CBN

    Science.gov (United States)

    Ginting, B.; Sembiring, R. W.; Manurung, N.

    2017-09-01

    The concept of hard, dry and high speed machining can be combined, to produce high productivity, with lower production costs in manufacturing industry. Hard lathe process can be a solution to reduce production time. In lathe hard alloy steels reported problems relating to the integrity of such surface roughness, residual stress, the white layer and the surface integrity. AISI 4140 material is used for high reliable hydraulic system components. This material includes in cold work tool steel. Consideration election is because this material is able to be hardened up to 55 HRC. In this research, the experimental design using CCD model fit with three factors, each factor is composed of two levels, and six central point, experiments were conducted with 1 replications. The experimental design research using CCD model fit.

  17. Maglev vehicles and superconductor technology: Integration of high-speed ground transportation into the air travel system

    Energy Technology Data Exchange (ETDEWEB)

    Johnson, L.R.; Rote, D.M.; Hull, J.R.; Coffey, H.T.; Daley, J.G.; Giese, R.F.

    1989-04-01

    This study was undertaken to (1) evaluate the potential contribution of high-temperature superconductors (HTSCs) to the technical and economic feasibility of magnetically levitated (maglev) vehicles, (2) determine the status of maglev transportation research in the United States and abroad, (3) identify the likelihood of a significant transportation market for high-speed maglev vehicles, and (4) provide a preliminary assessment of the potential energy and economic benefits of maglev systems. HTSCs should be considered as an enhancing, rather than an enabling, development for maglev transportation because they should improve reliability and reduce energy and maintenance costs. Superconducting maglev transportation technologies were developed in the United States in the late 1960s and early 1970s. Federal support was withdrawn in 1975, but major maglev transportation programs were continued in Japan and West Germany, where full-scale prototypes now carry passengers at speeds of 250 mi/h in demonstration runs. Maglev systems are generally viewed as very-high-speed train systems, but this study shows that the potential market for maglev technology as a train system, e.g., from one downtown to another, is limited. Rather, aircraft and maglev vehicles should be seen as complementing rather than competing transportation systems. If maglev systems were integrated into major hub airport operations, they could become economical in many relatively high-density US corridors. Air traffic congestion and associated noise and pollutant emissions around airports would also be reduced. 68 refs., 26 figs., 16 tabs.

  18. Design and Analysis of a High Speed Carry Select Adder

    OpenAIRE

    Simarpreet Singh Chawla; Swapnil Aggarwal; Anshika; Nidhi Goel

    2015-01-01

    An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design. High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devi...

  19. Design and Analysis of a High Speed Carry Select Adder

    OpenAIRE

    Simarpreet Singh Chawla; Swapnil Aggarwal; Anshika; Nidhi Goel

    2015-01-01

    An optimal high-speed and low-power VLSI architecture requires an efficient arithmetic processing unit that is optimized for speed and power consumption. Adders are one of the widely used in digital integrated circuit and system design.High speed adder is the necessary component in a data path, e.g. Microprocessors and a Digital signal processor. The present paper proposes a novel high-speed adder by combining the advantages of Carry Look Ahead Adder (CLAA) and Carry Select Adder (CSA), devis...

  20. Boom Softening and Nacelle Integration on an Arrow-Wing High-Speed Civil Transport Concept

    Science.gov (United States)

    Mack, Robert J.

    1999-01-01

    During the last cycle of concept design and wind-tunnel testing, the goal of the low-boom- shaped HSCT concepts (the B-935, the LB-16, and the LB- 1 8) was to meet mission requirements and generate shaped, ground-level pressure signatures with nose shock strengths of 1.0 psf or less. The wind-tunnel tests of these concepts produced results that were partially successful and encouraging although not fully up to expectations. In spite of this, however, these conceptual designs were overly optimistic and not acceptable because: the wing planforms had excessive area; the wing structural aspect ratio was too high; one concept had aft-fuselage rather than under-the-wing engines; and the gross takeoff weights were unrealistically low because of engines that were early, high-tech versions of later, revised, more-realistic engines. The need for reducing the ground-level overpressure shock strengths still existed; a need to be met within more restrictive guidelines of mission performance and gross takeoff weight limitations. Therefore, it was decided that the next conceptual design cycle would focus on decreased nose shock strengths, "boom softening," in the signatures of the Boeing and the McDonnell Douglas baseline concepts rather than low-boom concepts with shaped-signature designs. Overly-optimistic results were not the only problem with these low-sonic-boom concepts. Papers given at the 1994 Sonic-Boom Workshop had demonstrated that the problem of successful nacelle integration on HSCT concepts had only been partially solved. Wind-tunnel pressure signature data, from the HSCT-11B (a.k.a. the LB-18) wind-tunnel model, showed that the Langley HSCT design and analysis method had been successful in reducing the nacelle-volume disturbances in the flow field. This was due.to the engine nacelles mounted behind the wing trailing-edge on the aft fuselage so that no nacelle-wing interference-lift flow-field disturbances were generated. While acceptable from a sonic-boom research

  1. Velo and REXAN - Integrated Data Management and High Speed Analysis for Experimental Facilities

    Energy Technology Data Exchange (ETDEWEB)

    Kleese van Dam, Kerstin; Carson, James P.; Corrigan, Abigail L.; Einstein, Daniel R.; Guillen, Zoe C.; Heath, Brandi S.; Kuprat, Andrew P.; Lanekoff, Ingela T.; Lansing, Carina S.; Laskin, Julia; Li, Dongsheng; Liu, Yan; Marshall, Matthew J.; Miller, Erin A.; Orr, Galya; Pinheiro da Silva, Paulo; Ryu, Seun; Szymanski, Craig J.; Thomas, Mathew

    2013-01-10

    The Chemical Imaging Initiative at the Pacific Northwest National Laboratory (PNNL) is creating a ‘Rapid Experimental Analysis’ (REXAN) Framework, based on the concept of reusable component libraries. REXAN allows developers to quickly compose and customize high throughput analysis pipelines for a range of experiments, as well as supporting the creation of multi-modal analysis pipelines. In addition, PNNL has coupled REXAN with its collaborative data management and analysis environment Velo to create an easy to use data management and analysis environments for experimental facilities. This paper will discuss the benefits of Velo and REXAN in the context of three examples: PNNL High Resolution Mass Spectrometry - reducing analysis times from hours to seconds, and enabling the analysis of much larger data samples (100KB to 40GB) at the same time · ALS X-Ray tomography - reducing analysis times of combined STXM and EM data collected at the ALS from weeks to minutes, decreasing manual work and increasing data volumes that can be analysed in a single step ·Multi-modal nano-scale analysis of STXM and TEM data - providing a semi automated process for particle detection The creation of REXAN has significantly shortened the development time for these analysis pipelines. The integration of Velo and REXAN has significantly increased the scientific productivity of the instruments and their users by creating easy to use data management and analysis environments with greatly reduced analysis times and improved analysis capabilities.

  2. Robust Diagnosis Method Based on Parameter Estimation for an Interturn Short-Circuit Fault in Multipole PMSM under High-Speed Operation

    Directory of Open Access Journals (Sweden)

    Jewon Lee

    2015-11-01

    Full Text Available This paper proposes a diagnosis method for a multipole permanent magnet synchronous motor (PMSM under an interturn short circuit fault. Previous works in this area have suffered from the uncertainties of the PMSM parameters, which can lead to misdiagnosis. The proposed method estimates the q-axis inductance (Lq of the faulty PMSM to solve this problem. The proposed method also estimates the faulty phase and the value of G, which serves as an index of the severity of the fault. The q-axis current is used to estimate the faulty phase, the values of G and Lq. For this reason, two open-loop observers and an optimization method based on a particle-swarm are implemented. The q-axis current of a healthy PMSM is estimated by the open-loop observer with the parameters of a healthy PMSM. The Lq estimation significantly compensates for the estimation errors in high-speed operation. The experimental results demonstrate that the proposed method can estimate the faulty phase, G, and Lq besides exhibiting robustness against parameter uncertainties.

  3. Robust Diagnosis Method Based on Parameter Estimation for an Interturn Short-Circuit Fault in Multipole PMSM under High-Speed Operation.

    Science.gov (United States)

    Lee, Jewon; Moon, Seokbae; Jeong, Hyeyun; Kim, Sang Woo

    2015-11-20

    This paper proposes a diagnosis method for a multipole permanent magnet synchronous motor (PMSM) under an interturn short circuit fault. Previous works in this area have suffered from the uncertainties of the PMSM parameters, which can lead to misdiagnosis. The proposed method estimates the q-axis inductance (Lq) of the faulty PMSM to solve this problem. The proposed method also estimates the faulty phase and the value of G, which serves as an index of the severity of the fault. The q-axis current is used to estimate the faulty phase, the values of G and Lq. For this reason, two open-loop observers and an optimization method based on a particle-swarm are implemented. The q-axis current of a healthy PMSM is estimated by the open-loop observer with the parameters of a healthy PMSM. The Lq estimation significantly compensates for the estimation errors in high-speed operation. The experimental results demonstrate that the proposed method can estimate the faulty phase, G, and Lq besides exhibiting robustness against parameter uncertainties.

  4. High-Speed Large-Alphabet Quantum Key Distribution Using Photonic Integrated Circuits

    Science.gov (United States)

    2014-01-28

    Part I: Channel Model and Propagation Statistics, J. OPT. COMMUN. NETW. (07 2013) Cheng- Chia Tsai, Jacob Mower, Dirk Englund. Directional free...Member Dirk Robert Englund 0.06 Jeffrey H. Shapiro 0.03 No Chee Wei Wong 0.03 Karl Berggren 0.03 Gregory Wornell 0.05 0.20 5 PERCENT_SUPPORTEDNAME FTE

  5. Long Range Logistics Planning for VHSIC (Very High Speed Integrated Circuit) Components.

    Science.gov (United States)

    1981-12-01

    essentially all other major air- frames, trading electronics for fuel and hard weapons. The tangible benefits notwithstanding, however, perhaps the most...would have taken place--probably not soon enough to keep a competitive edge on foreig competition from Japan or the Soviet Union. C. CURRENT EMPHASIS...terized by high throughput rates in relation to size, power comsumption , etc. They also require low failure rate at the board and assembly level

  6. Scaling of graphene integrated circuits.

    Science.gov (United States)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  7. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  8. High speed data converters

    CERN Document Server

    Ali, Ahmed MA

    2016-01-01

    This book covers high speed data converters from the perspective of a leading high speed ADC designer and architect, with a strong emphasis on high speed Nyquist A/D converters. For our purposes, the term 'high speed' is defined as sampling rates that are greater than 10 MS/s.

  9. Recent advances in silicon photonic integrated circuits

    Science.gov (United States)

    Bowers, John E.; Komljenovic, Tin; Davenport, Michael; Hulme, Jared; Liu, Alan Y.; Santis, Christos T.; Spott, Alexander; Srinivasan, Sudharsanan; Stanton, Eric J.; Zhang, Chong

    2016-02-01

    We review recent breakthroughs in silicon photonics technology and components and describe progress in silicon photonic integrated circuits. Heterogeneous silicon photonics has recently demonstrated performance that significantly outperforms native III-V components. The impact active silicon photonic integrated circuits could have on interconnects, telecommunications, sensors and silicon electronics is reviewed.

  10. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  11. Integrated design and manufacturing for the high speed civil transport (a combined aerodynamics/propulsion optimization study)

    Science.gov (United States)

    Baecher, Juergen; Bandte, Oliver; DeLaurentis, Dan; Lewis, Kemper; Sicilia, Jose; Soboleski, Craig

    1995-01-01

    This report documents the efforts of a Georgia Tech High Speed Civil Transport (HSCT) aerospace student design team in completing a design methodology demonstration under NASA's Advanced Design Program (ADP). Aerodynamic and propulsion analyses are integrated into the synthesis code FLOPS in order to improve its prediction accuracy. Executing the integrated product and process development (IPPD) methodology proposed at the Aerospace Systems Design Laboratory (ASDL), an improved sizing process is described followed by a combined aero-propulsion optimization, where the objective function, average yield per revenue passenger mile ($/RPM), is constrained by flight stability, noise, approach speed, and field length restrictions. Primary goals include successful demonstration of the application of the response surface methodolgy (RSM) to parameter design, introduction to higher fidelity disciplinary analysis than normally feasible at the conceptual and early preliminary level, and investigations of relationships between aerodynamic and propulsion design parameters and their effect on the objective function, $/RPM. A unique approach to aircraft synthesis is developed in which statistical methods, specifically design of experiments and the RSM, are used to more efficiently search the design space for optimum configurations. In particular, two uses of these techniques are demonstrated. First, response model equations are formed which represent complex analysis in the form of a regression polynomial. Next, a second regression equation is constructed, not for modeling purposes, but instead for the purpose of optimization at the system level. Such an optimization problem with the given tools normally would be difficult due to the need for hard connections between the various complex codes involved. The statistical methodology presents an alternative and is demonstrated via an example of aerodynamic modeling and planform optimization for a HSCT.

  12. Analog MOS integrated circuits for signal processing

    Science.gov (United States)

    Gregorian, R.; Temes, G. C.

    Theoretical and practical aspects of analog MOS integrated circuits are discussed. The basic properties of these circuits are described, providing necessary background material in mathematics and semiconductor device physics and technology. The operation and design of such important circuits as switched-capacitor filters, analog-to-digital and digital-to-analog converters, amplifiers, modulators, and oscillators. Practical problems encountered in design are discussed, solutions are provided, and some examples of actual system applications are given.

  13. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  14. Cascaded all-optical operations in a hybrid integrated 80-Gb/s logic circuit.

    Science.gov (United States)

    LeGrange, J D; Dinu, M; Sochor, T; Bollond, P; Kasper, A; Cabot, S; Johnson, G S; Kang, I; Grant, A; Kay, J; Jaques, J

    2014-06-02

    We demonstrate logic functionalities in a high-speed all-optical logic circuit based on differential Mach-Zehnder interferometers with semiconductor optical amplifiers as the nonlinear optical elements. The circuit, implemented by hybrid integration of the semiconductor optical amplifiers on a planar lightwave circuit platform fabricated in silica glass, can be flexibly configured to realize a variety of Boolean logic gates. We present both simulations and experimental demonstrations of cascaded all-optical operations for 80-Gb/s on-off keyed data.

  15. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  16. High-Speed Near Infrared Optical Receivers Based on Ge Waveguide Photodetectors Integrated in a CMOS Process

    Directory of Open Access Journals (Sweden)

    Gianlorenzo Masini

    2008-01-01

    Full Text Available We discuss our approach to monolithic intergration of Ge photodectors with CMOS electronics for high-speed optical transceivers. Receivers based on Ge waveguide photodetectors achieve a sensitivity of −14.2 dBm (10−12 bit error rate (BER at 10 Gbps and 1550 nm.

  17. Integrated Circuit Stellar Magnitude Simulator

    Science.gov (United States)

    Blackburn, James A.

    1978-01-01

    Describes an electronic circuit which can be used to demonstrate the stellar magnitude scale. Six rectangular light-emitting diodes with independently adjustable duty cycles represent stars of magnitudes 1 through 6. Experimentally verifies the logarithmic response of the eye. (Author/GA)

  18. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  19. A 1 GHz integrated circuit with carbon nanotube interconnects and silicon transistors.

    Science.gov (United States)

    Close, Gael F; Yasuda, Shinichi; Paul, Bipul; Fujita, Shinobu; Wong, H-S Philip

    2008-02-01

    Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.

  20. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  1. Progress in organic integrated circuit manufacture

    Science.gov (United States)

    Taylor, D. Martin

    2016-02-01

    This review article focuses on the development of processes for the manufacture of organic electronic circuits. Beginning with the first report of an organic transistor it highlights the key developments leading to the successful manufacture of microprocessors and other complex circuits incorporating organic transistors. Both batch processing (based on silicon integrated circuit technology) as well as mass-printing, roll-to-roll (R2R) approaches are discussed. Currently, the best circuit performances are achieved using batch processing. It is suggested that an emerging, large mass-market for electronic tags may dictate that R2R manufacture will likely be required to meet the high throughput rates needed. However, significant improvements in resolution and registration are necessary to achieve increased circuit operating speeds.

  2. Displacement Damage in Bipolar Linear Integrated Circuits

    Science.gov (United States)

    Rax, B. G.; Johnston, A. H.; Miyahira, T.

    2000-01-01

    Although many different processes can be used to manufacture linear integrated circuits, the process that is used for most circuits is optimized for high voltage -- a total power supply voltage of about 40 V -- and low cost. This process, which has changed little during the last twenty years, uses lateral and substrate p-n-p transistors. These p-n-p transistors have very wide base regions, increasing their sensitivity to displacement damage from electrons and protons. Although displacement damage effects can be easily treated for individual transistors, the net effect on linear circuits can be far more complex because circuit operation often depends on the interaction of several internal transistors. Note also that some circuits are made with more advanced processes with much narrower base widths. Devices fabricated with these newer processes are not expected to be significantly affected by displacement damage for proton fluences below 1 x 10(exp 12) p/sq cm. This paper discusses displacement damage in linear integrated circuits with more complex failure modes than those exhibited by simpler devices, such as the LM111 comparator, where the dominant response mode is gain degradation of the input transistor. Some circuits fail catastrophically at much lower equivalent total dose levels compared to tests with gamma rays. The device works satisfactorily up to nearly 1 Mrad(Si) when it is irradiated with gamma rays, but fails catastrophically between 50 and 70 krad(Si) when it is irradiated with protons.

  3. Pulsed-Power Burnout of Integrated Circuits

    Science.gov (United States)

    Results of pulsed-power burnout testing the Fairchild 9046 quad dual-input nand gate and the Amelco 6041 three-input nand gate showed the circuits to...be vulnerable to junction burnout for pulses of less than 100 V and pulse widths on the order of 100 nsec. Calculations based on Wunsch-Bell junction... burnout theory showed good agreement with the experimental results. Sample calculations applying Wunsch-Bell theory to integrated circuits are given.

  4. Phase-controlled integrated photonic quantum circuits.

    Science.gov (United States)

    Smith, Brian J; Kundys, Dmytro; Thomas-Peter, Nicholas; Smith, P G R; Walmsley, I A

    2009-08-03

    Scalable photonic quantum technologies are based on multiple nested interferometers. To realize this architecture, integrated optical structures are needed to ensure stable, controllable, and repeatable operation. Here we show a key proof-of-principle demonstration of an externallycontrolled photonic quantum circuit based upon UV-written waveguide technology. In particular, we present non-classical interference of photon pairs in a Mach-Zehnder interferometer constructed with X couplers in an integrated optical circuit with a thermo-optic phase shifter in one of the interferometer arms.

  5. The effectiveness of detection of splashed particles using a system of three integrated high-speed cameras

    Science.gov (United States)

    Ryżak, Magdalena; Beczek, Michał; Mazur, Rafał; Sochan, Agata; Bieganowski, Andrzej

    2017-04-01

    The phenomenon of splash, which is one of the factors causing erosion of the soil surface, is the subject of research of various scientific teams. One of efficient methods of observation and analysis of this phenomenon are high-speed cameras to measure particles at 2000 frames per second or higher. Analysis of the phenomenon of splash with the use of high-speed cameras and specialized software can reveal, among other things, the number of broken particles, their speeds, trajectories, and the distances over which they were transferred. The paper presents an attempt at evaluation of the efficiency of detection of splashed particles with the use of a set of 3 cameras (Vision Research MIRO 310) and software Dantec Dynamics Studio, using a 3D module (Volumetric PTV). In order to assess the effectiveness of estimating the number of particles, the experiment was performed on glass beads with a diameter of 0.5 mm (corresponding to the sand fraction). Water droplets with a diameter of 4.2 mm fell on a sample from a height of 1.5 m. Two types of splashed particles were observed: particle having a low range (up to 18 mm) splashed at larger angles and particles of a high range (up to 118 mm) splashed at smaller angles. The detection efficiency the number of splashed particles estimated by the software was 45 - 65% for particles with a large range. The effectiveness of the detection of particles by the software has been calculated on the basis of comparison with the number of beads that fell on the adhesive surface around the sample. This work was partly financed from the National Science Centre, Poland; project no. 2014/14/E/ST10/00851.

  6. Integrated Circuits in the Introductory Electronics Laboratory

    Science.gov (United States)

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  7. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully exc...

  8. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...... method enables significantly reduced noise and power consumption....

  9. Accurate Electromagnetic Modeling Methods for Integrated Circuits

    NARCIS (Netherlands)

    Sheng, Z.

    2010-01-01

    The present development of modern integrated circuits (IC’s) is characterized by a number of critical factors that make their design and verification considerably more difficult than before. This dissertation addresses the important questions of modeling all electromagnetic behavior of features on

  10. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  11. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  12. High-speed analog CMOS pipeline system

    Science.gov (United States)

    Möschen, J.; Caldwell, A.; Hervas, L.; Hosticka, B.; Kötz, U.; Sippach, B.

    1990-03-01

    We present a switched-capacitor readout system for high speed analog signals. It consists of a 10 MHz four-channel delay-line chip with 58 samples per channel and a 12 channel buffer chip with a sampling rate of 1 MHz and a depth of nine samples. In addition the buffer chip includes an analog multiplexer with 25 inputs for the buffer channels and for 13 additional unbuffered signals. Both chips have been fabricated in CMOS-technology and will be used for the readout of the ZEUS high resolution calorimeter. The circuit and chip concept will be presented and some design optimizations will be discussed. Measurements from integrated prototypes will be given including some experimental data from irradiated chips.

  13. Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

    Energy Technology Data Exchange (ETDEWEB)

    Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-04-12

    In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

  14. The RD53A Integrated Circuit

    CERN Document Server

    Garcia-Sciveres, Maurice

    2017-01-01

    Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

  15. Efficient Integrated Circuits for Wideband Wireless Transceivers

    OpenAIRE

    Duong, Quoc-Tai

    2016-01-01

    The proliferation of portable communication devices combined with the relentless demand for higher data rates has spurred the development of wireless communication standards which can support wide signal bandwidths. Benefits of the complementary metal oxide semiconductor (CMOS) process such as high device speeds and low manufacturing cost have rendered it the technology of choice for implementing wideband wireless transceiver integrated circuits (ICs). This dissertation addresses the key chal...

  16. High-frequency analog integrated circuit design

    CERN Document Server

    1995-01-01

    To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

  17. Progress in radiation immune thermionic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Lynn, D.K.; McCormick, J.B. (comps.)

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  18. Power system with an integrated lubrication circuit

    Science.gov (United States)

    Hoff, Brian D [East Peoria, IL; Akasam, Sivaprasad [Peoria, IL; Algrain, Marcelo C [Peoria, IL; Johnson, Kris W [Washington, IL; Lane, William H [Chillicothe, IL

    2009-11-10

    A power system includes an engine having a first lubrication circuit and at least one auxiliary power unit having a second lubrication circuit. The first lubrication circuit is in fluid communication with the second lubrication circuit.

  19. High-Speed Imaging Reveals Opposing Effects of Chronic Stress and Antidepressants on Neuronal Activity Propagation through the Hippocampal Trisynaptic Circuit

    Directory of Open Access Journals (Sweden)

    Jens eStepan

    2015-11-01

    Full Text Available Antidepressants (ADs are used as first-line treatment for most stress-related psychiatric disorders. The alterations in brain circuit dynamics that can arise from stress exposure and underlie therapeutic actions of ADs remain, however, poorly understood. Here, enabled by a recently developed voltage-sensitive dye imaging assay in mouse brain slices, we examined the impact of chronic stress and concentration-dependent effects of eight clinically used ADs (belonging to different chemical/functional classes on evoked neuronal activity propagations through the hippocampal trisynaptic circuitry (HTC: perforant path - dentate gyrus - area CA3 - area CA1. Exposure of mice to chronic social defeat stress led to markedly weakened activity propagations (HTC-Waves. In contrast, at concentrations in the low micromolar range, all ADs, which were bath applied to slices, caused an amplification of HTC-Waves in CA regions (invariably in area CA1. The fast-acting antidepressant ketamine, the mood stabilizer lithium, and brain-derived neurotrophic factor (BDNF exerted comparable enhancing effects, whereas the antipsychotic haloperidol and the anxiolytic diazepam attenuated HTC-Waves. Collectively, we provide direct experimental evidence that chronic stress can depress neuronal signal flow through the HTC and demonstrate shared opposing effects of ADs. Thus, our study points to a circuit-level mechanism of ADs to counteract stress-induced impairment of hippocampal network function. However, the observed effects of ADs are impossible to depend on enhanced neurogenesis.

  20. Mouldable all-carbon integrated circuits.

    Science.gov (United States)

    Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

    2013-01-01

    A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

  1. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  2. Microtelemetry--the use of integrated circuits in biotelemetry.

    Science.gov (United States)

    Gill, R W

    1976-02-01

    Integrated circuits are now in widespread use in such equipment as computers and consumer electronics, where their low cost, high reliability and small size are their principal advantages. In biotelemetry, small size is of particular importance. Here the use of integrated circuits allows systems of considerable complexity to be produced with high reliability in small packages. Commercial integrated circuits with the low power consumption and low voltage operation needed for biotelemetry are now becoming available; some such applications are briefly reviewed. In addition, examples of the use of custom integrated circuits in biotelemetry, and of the use of integrated circuit technology to build unique transducers and assemblies, are described.

  3. An integrator circuit in cerebellar cortex.

    Science.gov (United States)

    Maex, Reinoud; Steuber, Volker

    2013-09-01

    The brain builds dynamic models of the body and the outside world to predict the consequences of actions and stimuli. A well-known example is the oculomotor integrator, which anticipates the position-dependent elasticity forces acting on the eye ball by mathematically integrating over time oculomotor velocity commands. Many models of neural integration have been proposed, based on feedback excitation, lateral inhibition or intrinsic neuronal nonlinearities. We report here that a computational model of the cerebellar cortex, a structure thought to implement dynamic models, reveals a hitherto unrecognized integrator circuit. In this model, comprising Purkinje cells, molecular layer interneurons and parallel fibres, Purkinje cells were able to generate responses lasting more than 10 s, to which both neuronal and network mechanisms contributed. Activation of the somatic fast sodium current by subthreshold voltage fluctuations was able to maintain pulse-evoked graded persistent activity, whereas lateral inhibition among Purkinje cells via recurrent axon collaterals further prolonged the responses to step and sine wave stimulation. The responses of Purkinje cells decayed with a time-constant whose value depended on their baseline spike rate, with integration vanishing at low ( 30 per s). The model predicts that the apparently fast circuit of the cerebellar cortex may control the timing of slow processes without having to rely on sensory feedback. Thus, the cerebellar cortex may contain an adaptive temporal integrator, with the sensitivity of integration to the baseline spike rate offering a potential mechanism of plasticity of the response time-constant. © 2013 Federation of European Neuroscience Societies and John Wiley & Sons Ltd.

  4. Low-voltage, high-speed and compact electro-absorption modulator laterally integrated with 980-nm VCSEL.

    Science.gov (United States)

    Dalir, Hamed; Takahashi, Yuta; Koyama, Fumio

    2014-10-20

    We present a compact electro-absorption slow-light modulator laterally-integrated with a 980-nm VCSEL. We figured out the small signal modulation response for different modulator lengths. While the 3-dB small-signal modulation bandwidth of conventional directly modulated VCSELs on the same epi-wafer structure was limited below 10 GHz, we obtained a modulation bandwidth over 21 GHz for a 30 µm long modulator. We also demonstrated large signal modulation up to 25 Gbps with a low driving voltage below 600 mV(pp) and an extinction ratio of 4 dB for the modulator length of 50 µm. Prospects of much higher speed (> 40 Gbps) were examined with reducing the size of the modulator. Also, the tapered waveguide coupling structure enables "quasi-unidirectional coupling", which reduces the optical feedback in a VCSEL from the integrated modulator.

  5. GaAs integrated circuits and heterojunction devices

    Science.gov (United States)

    Fowlis, Colin

    1986-06-01

    The state of the art of GaAs technology in the U.S. as it applies to digital and analog integrated circuits is examined. In a market projection, it is noted that whereas analog ICs now largely dominate the market, in 1994 they will amount to only 39 percent vs. 57 percent for digital ICs. The military segment of the market will remain the largest (42 percent in 1994 vs. 70 percent today). ICs using depletion-mode-only FETs can be constructed in various forms, the closest to production being BFL or buffered FET logic. Schottky diode FET logic - a lower power approach - can reach higher complexities and strong efforts are being made in this direction. Enhancement type devices appear essential to reach LSI and VLSI complexity, but process control is still very difficult; strong efforts are under way, both in the U.S. and in Japan. Heterojunction devices appear very promising, although structures are fairly complex, and special fabrication techniques, such as molecular beam epitaxy and MOCVD, are necessary. High-electron-mobility-transistor (HEMT) devices show significant performance advantages over MESFETs at low temperatures. Initial results of heterojunction bipolar transistor devices show promise for high speed A/D converter applications.

  6. Thermoelectricity from wasted heat of integrated circuits

    KAUST Repository

    Fahad, Hossain M.

    2012-05-22

    We demonstrate that waste heat from integrated circuits especially computer microprocessors can be recycled as valuable electricity to power up a portion of the circuitry or other important accessories such as on-chip cooling modules, etc. This gives a positive spin to a negative effect of ever increasing heat dissipation associated with increased power consumption aligned with shrinking down trend of transistor dimension. This concept can also be used as an important vehicle for self-powered systemson- chip. We provide theoretical analysis supported by simulation data followed by experimental verification of on-chip thermoelectricity generation from dissipated (otherwise wasted) heat of a microprocessor.

  7. 3D packaging for integrated circuit systems

    Energy Technology Data Exchange (ETDEWEB)

    Chu, D.; Palmer, D.W. [eds.

    1996-11-01

    A goal was set for high density, high performance microelectronics pursued through a dense 3D packing of integrated circuits. A {open_quotes}tool set{close_quotes} of assembly processes have been developed that enable 3D system designs: 3D thermal analysis, silicon electrical through vias, IC thinning, mounting wells in silicon, adhesives for silicon stacking, pretesting of IC chips before commitment to stacks, and bond pad bumping. Validation of these process developments occurred through both Sandia prototypes and subsequent commercial examples.

  8. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...... are designed based on the monolithic membrane supported Schottky diodes, which is under development at Chalmers University of Technology, Sweden. To simplify the baseband circuitry, the received IF signal from the subharmonic mixer is further amplified and downconverted to the DC range with a low noise...

  9. HIGH SPEED CAMERA

    Science.gov (United States)

    Rogers, B.T. Jr.; Davis, W.C.

    1957-12-17

    This patent relates to high speed cameras having resolution times of less than one-tenth microseconds suitable for filming distinct sequences of a very fast event such as an explosion. This camera consists of a rotating mirror with reflecting surfaces on both sides, a narrow mirror acting as a slit in a focal plane shutter, various other mirror and lens systems as well as an innage recording surface. The combination of the rotating mirrors and the slit mirror causes discrete, narrow, separate pictures to fall upon the film plane, thereby forming a moving image increment of the photographed event. Placing a reflecting surface on each side of the rotating mirror cancels the image velocity that one side of the rotating mirror would impart, so as a camera having this short a resolution time is thereby possible.

  10. Parallel Jacobi EVD Methods on Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Chi-Chia Sun

    2014-01-01

    Full Text Available Design strategies for parallel iterative algorithms are presented. In order to further study different tradeoff strategies in design criteria for integrated circuits, A 10 × 10 Jacobi Brent-Luk-EVD array with the simplified μ-CORDIC processor is used as an example. The experimental results show that using the μ-CORDIC processor is beneficial for the design criteria as it yields a smaller area, faster overall computation time, and less energy consumption than the regular CORDIC processor. It is worth to notice that the proposed parallel EVD method can be applied to real-time and low-power array signal processing algorithms performing beamforming or DOA estimation.

  11. Post irradiation effects (PIE) in integrated circuits

    Science.gov (United States)

    Shaw, D. C.; Lowry, L.; Barnes, C.; Zakharia, M.; Agarwal, S.; Rax, B.

    1991-01-01

    Post-irradiation effects (PIE) ranging from normal recovery to catastrophic failure have been observed in integrated circuits during the PIE period. Data presented show failure due to rebound after a 10 krad(Si) dose. In particular, five device types are investigated with varying PIE response. Special attention has been given to the HI1-507A analog multiplexer because its PIE response is extreme. X-ray diffraction has been uniquely employed to measure physical stress in the HI1-507A metallization. An attempt has been made to show a relationship between stress relaxation and radiation effects. All data presented support the current MIL-STD Method 1019.4 but demonstrate the importance of performing PIE measurements, even when mission doses are as low as 10 krad(Si).

  12. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  13. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  14. High speed, high current pulsed driver circuit

    Science.gov (United States)

    Carlen, Christopher R.

    2017-03-21

    Various technologies presented herein relate to driving a LED such that the LED emits short duration pulses of light. This is accomplished by driving the LED with short duration, high amplitude current pulses. When the LED is driven by short duration, high amplitude current pulses, the LED emits light at a greater amplitude compared to when the LED is driven by continuous wave current.

  15. CMOS digital integrated circuits a first course

    CERN Document Server

    Hawkins, Charles; Zarkesh-Ha, Payman

    2016-01-01

    This book teaches the fundamentals of modern CMOS technology and covers equal treatment to both types of MOSFET transistors that make up computer circuits; power properties of logic circuits; physical and electrical properties of metals; introduction of timing circuit electronics and introduction of layout; real-world examples and problem sets.

  16. Energy-efficient neuron, synapse and STDP integrated circuits.

    Science.gov (United States)

    Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

    2012-06-01

    Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

  17. High Speed Ice Friction

    Science.gov (United States)

    Seymour-Pierce, Alexandra; Sammonds, Peter; Lishman, Ben

    2014-05-01

    Many different tribological experiments have been run to determine the frictional behaviour of ice at high speeds, ostensibly with the intention of applying results to everyday fields such as winter tyres and sports. However, experiments have only been conducted up to linear speeds of several metres a second, with few additional subject specific studies reaching speeds comparable to these applications. Experiments were conducted in the cold rooms of the Rock and Ice Physics Laboratory, UCL, on a custom built rotational tribometer based on previous literature designs. Preliminary results from experiments run at 2m/s for ice temperatures of 271 and 263K indicate that colder ice has a higher coefficient of friction, in accordance with the literature. These results will be presented, along with data from further experiments conducted at temperatures between 259-273K (in order to cover a wide range of the temperature dependent behaviour of ice) and speeds of 2-15m/s to produce a temperature-velocity-friction map for ice. The effect of temperature, speed and slider geometry on the deformation of ice will also be investigated. These speeds are approaching those exhibited by sports such as the luge (where athletes slide downhill on an icy track), placing the tribological work in context.

  18. Integrated devices in digital circuit design

    Science.gov (United States)

    Hope, G. S.

    Aspects of combinational design are examined, taking into account logical operations, truth tables, Karnaugh maps as input output expressions, minimum forms, maximum forms, minterm forms, symbols, fundamental relationships, Karnaugh maps as design tools, the implementation of logic functions, logic and implementation, logic nor implementation, implementation examples, the exclusive or function, symmetrical forms, reduction, and practical circuits. Multiplexers and demultiplexers in combinational circuits are considered along with fundamental mode circuits, event-driven sequential circuits, event-driven circuit implementation using multiplexers, clock-driven sequential circuits, counters and multiplexers in clock-driven sequential circuits, state diagram construction, registers in logic design, a digital system, programming and programming aids, input and output techniques, operation and configuration of independent systems, and a definition of a Boolean algebra. Attention is also given to Intel's and Motorola's executable instructions.

  19. Aluminum alloy metallization for integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Ghate, P.B.

    1981-09-11

    Aluminum metallization is most widely used for contacts and interconnections in both bipolar and MOS integrated circuits. Aluminum alloy films, such as Al-Si and Al-Cu films, were introduced to minimize the erosion of silicon from contact windows and to improve the electromigration resistance of interconnections. Recently, magnetron sputter-deposited aluminum, Al-2wt.%Cu and Al-2wt.%Cu-1wt.%Si films were employed to study the stability and contact resistance of Si-(Al alloy film) contacts on devices with shallow junction depths of the order of 0.35 ..mu..m. Test structures were used to determine the leakage currents of 100n/sup +//p/sup +/ diodes as a function of the storage time (up to 1000 h) at 150 C, and the physical nature of the Si-(Al alloy) contacts was examined using scanning electron microscopy. The compatibility of the Al-Cu-Si metallization with the very large scale integrated requirements of interconnection and Si-metal contacts for shallow junction devices is discussed.

  20. Wide-band polarization controller for Si photonic integrated circuits.

    Science.gov (United States)

    Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

    2016-12-15

    A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

  1. Rounding Technique for High-Speed Digital Signal Processing

    Science.gov (United States)

    Wechsler, E. R.

    1983-01-01

    Arithmetic technique facilitates high-speed rounding of 2's complement binary data. Conventional rounding of 2's complement numbers presents problems in high-speed digital circuits. Proposed technique consists of truncating K + 1 bits then attaching bit in least significant position. Mean output error is zero, eliminating introducing voltage offset at input.

  2. Securing Health Sensing Using Integrated Circuit Metric

    Directory of Open Access Journals (Sweden)

    Ruhma Tahir

    2015-10-01

    Full Text Available Convergence of technologies from several domains of computing and healthcare have aided in the creation of devices that can help health professionals in monitoring their patients remotely. An increase in networked healthcare devices has resulted in incidents related to data theft, medical identity theft and insurance fraud. In this paper, we discuss the design and implementation of a secure lightweight wearable health sensing system. The proposed system is based on an emerging security technology called Integrated Circuit Metric (ICMetric that extracts the inherent features of a device to generate a unique device identification. In this paper, we provide details of how the physical characteristics of a health sensor can be used for the generation of hardware “fingerprints”. The obtained fingerprints are used to deliver security services like authentication, confidentiality, secure admission and symmetric key generation. The generated symmetric key is used to securely communicate the health records and data of the patient. Based on experimental results and the security analysis of the proposed scheme, it is apparent that the proposed system enables high levels of security for health monitoring in resource optimized manner.

  3. Counterfeit integrated circuits detection and avoidance

    CERN Document Server

    Tehranipoor, Mark (Mohammad); Forte, Domenic

    2015-01-01

    This timely and exhaustive study offers a much-needed examination of the scope and consequences of the electronic counterfeit trade.  The authors describe a variety of shortcomings and vulnerabilities in the electronic component supply chain, which can result in counterfeit integrated circuits (ICs).  Not only does this book provide an assessment of the current counterfeiting problems facing both the public and private sectors, it also offers practical, real-world solutions for combatting this substantial threat.   ·      Helps beginners and practitioners in the field by providing a comprehensive background on the counterfeiting problem; ·      Presents innovative taxonomies for counterfeit types, test methods, and counterfeit defects, which allows for a detailed analysis of counterfeiting and its mitigation; ·      Provides step-by-step solutions for detecting different types of counterfeit ICs; ·      Offers pragmatic and practice-oriented, realistic solutions to counterfeit IC d...

  4. Designing TSVs for 3D Integrated Circuits

    CERN Document Server

    Khan, Nauman

    2013-01-01

    This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available....

  5. CLASSICS Invention of the Integrated Circuit

    Indian Academy of Sciences (India)

    IAS Admin

    electrical functions being connected directly by cutting out areas of the various layers.” This remarkable ... In 1947 I graduated from the University of Illinois with a degree in electrical engineering. I was hired by A. S. .... first circuit attempted was a phase-shift oscillator, a favorite demonstration vehicle for linear circuits at that ...

  6. F-Paris: integrated electronic circuits [Tender

    CERN Multimedia

    2003-01-01

    "Fourniture, montage et tests des circuits imprimes et modules multi composants pour le trajectographe central de CMS. Maximum de 12 000 circuits imprimes et modules multi-composants necessaires au trajectographe central de l'experience CMS aupres du Large Hadron Collider" (1 page).

  7. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  8. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  9. Parallel sparse direct solver for integrated circuit simulation

    CERN Document Server

    Chen, Xiaoming; Yang, Huazhong

    2017-01-01

    This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

  10. CERNET High Speed Data Link

    CERN Multimedia

    1975-01-01

    This card, based on a "4 slot DEC module", arbitrated the access priority of 15 datalinks of a CERNET node. Each datalinks could transfer data full duplex at 2.5 Mbit/sec over 1 Km of twisted pair (POD) cable. This was the frontier technology in 1980. The modest amount of integrated circuits was compensated by printing on the board photographs of the hardware designers, whose Belgian, Dutch and French nationality was underlined by the the short poem.

  11. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    Science.gov (United States)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-07-07

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  12. Present and future trends in integrated analog signal processing circuits

    Science.gov (United States)

    Nakayama, Kenji; Iwata, Atsushi; Yanagisawa, Takeshi

    1988-12-01

    An overview is presented of the recent and future trends in the design and applications of integrated analog signal processing circuits. Design techniques are reviewed for operational amplifiers, monolithic bipolar active RC circuits, switched-capacitor (SC) circuits, continuous-time MOS circuits, and analog-to-digital converters (ADCs). High-frequency filter realization, up to 100 MHz, has been attempted by bipolar active RC circuits and GaAs circuits. Improved design techniques for SC circuits are proposed. A multistage noise shaping ADC is very useful to integrate an accurate ADC. A high SNR (more than 91 dB) is obtained by the three-stage ADC, which can be applied to digital audio systems. An overview is presented of silicon compilers for SC circuits. A mixed analog/digital master slice LSI is proposed to simplify an LSI customizing process. A voice-band modem LSI has been developed, resulting in good filter responses and SNR. Finally, promising applications of integrated analog circuits are briefly reviewed.

  13. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    -division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

  14. 76 FR 76434 - Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions...

    Science.gov (United States)

    2011-12-07

    ... COMMISSION Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Receipt... Commission has received a complaint entitled In Re Certain Integrated Circuits, Chipsets, And Products... importation of certain integrated circuits, chipsets, and products containing same including televisions. The...

  15. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Science.gov (United States)

    2012-06-13

    ... COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of... within the United States after importation of certain radio frequency integrated circuits and devices... after importation of certain radio frequency integrated circuits and devices containing same that...

  16. High-speed optical transmission technology using all-optical signal processing

    Science.gov (United States)

    Kawanishi, Satoki

    2006-09-01

    This paper reviews recent progress on high-speed technologies for optical transmission systems in the IP and FTTH era. First, we describe our latest research results of 160 Gbit/s optical time-division multiplexing and demultiplexing experiments. The all-optical time-division multiplexer is realized as a hybrid integrated device consisting of planar lightwave circuits (PLC's) and highly-nonlinear periodically-poled lithium niobate (PPLN) waveguides while the demultiplexer is realized as a hybrid integrated device consisting of PLC's and semiconductor optical amplifiers. A new type of all-optical switch that uses a photonic crystal nanocavity and an all-optical flip-flop circuit that is composed of two-port resonant-tunneling filters based on a two dimensional photonic crystal slab with triangular air-hole lattice are shown. Finally, the possibility of over 100 Gbit/s all-optical signal processing is discussed for high-speed optical transmission systems.

  17. Radiation-hardened transistor and integrated circuit

    Science.gov (United States)

    Ma, Kwok K.

    2007-11-20

    A composite transistor is disclosed for use in radiation hardening a CMOS IC formed on an SOI or bulk semiconductor substrate. The composite transistor has a circuit transistor and a blocking transistor connected in series with a common gate connection. A body terminal of the blocking transistor is connected only to a source terminal thereof, and to no other connection point. The blocking transistor acts to prevent a single-event transient (SET) occurring in the circuit transistor from being coupled outside the composite transistor. Similarly, when a SET occurs in the blocking transistor, the circuit transistor prevents the SET from being coupled outside the composite transistor. N-type and P-type composite transistors can be used for each and every transistor in the CMOS IC to radiation harden the IC, and can be used to form inverters and transmission gates which are the building blocks of CMOS ICs.

  18. Integrated Circuit Chip Improves Network Efficiency

    Science.gov (United States)

    2008-01-01

    Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating

  19. Logistic Regression Modeling of Diminishing Manufacturing Sources for Integrated Circuits

    National Research Council Canada - National Science Library

    Gravier, Michael

    1999-01-01

    .... This thesis draws on available data from the electronics integrated circuit industry to attempt to assess whether statistical modeling offers a viable method for predicting the presence of DMSMS...

  20. Analog integrated circuits design for processing physiological signals.

    Science.gov (United States)

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  1. Integrating integrated circuit chips on paper substrates using inkjet printed electronics

    CSIR Research Space (South Africa)

    Bezuidenhout, Petrone H

    2016-11-01

    Full Text Available connect various integrated circuit(IC) chip packages to a paper substrate using a commercially-available conductive silver ink. The verification process included contact resistance compared to line resistance, percentage effective connections, geometry...

  2. Large Scale Integrated Circuits for Military Applications.

    Science.gov (United States)

    1977-05-01

    film formation, etching of numerous openings in the oxide film at locations precisely defined by photolitho - graphy, chemical treatment of the...circuit speed inversely with the linear dimensions. The practical implication is that improvements in photolitho - graphy, or the use of electron beam

  3. High speed nanofluidic protein accumulator.

    Science.gov (United States)

    Wu, Dapeng; Steckl, Andrew J

    2009-07-07

    Highly efficient preconcentration is a crucial prerequisite to the identification of important protein biomarkers with extremely low abundance in target biofluids. In this work, poly(dimethylsiloxane) microchips integrated with 10 nm polycarbonate nanopore membranes were utilized as high-speed protein accumulators. Double-sided injection control of electrokinetic fluid flow in the sample channel resulted in highly localized protein accumulation at a very sharp point in the channel cross point. This greatly enhanced the ability to detect very low levels of initial protein concentration. Fluorescein labeled human serum albumin solutions of 30 and 300 pM accumulated to 3 and 30 microM in only 100 s. Initial solutions as low as 0.3 and 3 pM could be concentrated within 200 s to 0.3 and 3 microM, respectively. This demonstrates a approximately 10(5)-10(6) accumulation factor, and an accumulation rate as high as 5000/sec, yielding a >10x improvement over most results reported to date.

  4. High speed rail distribution study.

    Science.gov (United States)

    2016-08-01

    The Texas Central Partners are in the process of developing a high speed rail line connecting : Houston and Dallas, Texas. Ultimately, plans are for 8 car trains that accommodate 200 people per : vehicle scheduled every 30 minutes. In addition, Texas...

  5. Electrothermal simulation of SOI CMOS analog integrated circuits

    Science.gov (United States)

    Yu, Feixia; Cheng, Ming-C.

    2007-05-01

    An analytical approach, combining a heat flow device model for SOI devices and a thermal model for interconnects, is presented for electrothermal simulation of SOI analog integrated circuits. The proposed approach is able to account for large temperature gradients in device, heat exchanges between devices, heat losses from the silicon islands and interconnects to the substrate through oxide, and temperature influences on electronic characteristics. Electrothermal simulations of SOI analog integrated circuits in SPICE coupled with the proposed approach are performed and compared with the isothermal model using the BSIMSOI thermal circuit. Heat flow, thermal coupling and self-heating effects in some SOI analog integrated circuits influenced by non-isothermal effects are examined. Limitations of the BSIMSOI isothermal is discussed.

  6. Integrated Circuit For Simulation Of Neural Network

    Science.gov (United States)

    Thakoor, Anilkumar P.; Moopenn, Alexander W.; Khanna, Satish K.

    1988-01-01

    Ballast resistors deposited on top of circuit structure. Cascadable, programmable binary connection matrix fabricated in VLSI form as basic building block for assembly of like units into content-addressable electronic memory matrices operating somewhat like networks of neurons. Connections formed during storage of data, and data recalled from memory by prompting matrix with approximate or partly erroneous signals. Redundancy in pattern of connections causes matrix to respond with correct stored data.

  7. Integrating Neural Circuits Controlling Female Sexual Behavior

    Directory of Open Access Journals (Sweden)

    Paul E. Micevych

    2017-06-01

    Full Text Available The hypothalamus is most often associated with innate behaviors such as is hunger, thirst and sex. While the expression of these behaviors important for survival of the individual or the species is nested within the hypothalamus, the desire (i.e., motivation for them is centered within the mesolimbic reward circuitry. In this review, we will use female sexual behavior as a model to examine the interaction of these circuits. We will examine the evidence for a hypothalamic circuit that regulates consummatory aspects of reproductive behavior, i.e., lordosis behavior, a measure of sexual receptivity that involves estradiol membrane-initiated signaling in the arcuate nucleus (ARH, activating β-endorphin projections to the medial preoptic nucleus (MPN, which in turn modulate ventromedial hypothalamic nucleus (VMH activity—the common output from the hypothalamus. Estradiol modulates not only a series of neuropeptides, transmitters and receptors but induces dendritic spines that are for estrogenic induction of lordosis behavior. Simultaneously, in the nucleus accumbens of the mesolimbic system, the mating experience produces long term changes in dopamine signaling and structure. Sexual experience sensitizes the response of nucleus accumbens neurons to dopamine signaling through the induction of a long lasting early immediate gene. While estrogen alone increases spines in the ARH, sexual experience increases dendritic spine density in the nucleus accumbens. These two circuits appear to converge onto the medial preoptic area where there is a reciprocal influence of motivational circuits on consummatory behavior and vice versa. While it has not been formally demonstrated in the human, such circuitry is generally highly conserved and thus, understanding the anatomy, neurochemistry and physiology can provide useful insight into the motivation for sexual behavior and other innate behaviors in humans.

  8. Rapidly reconfigurable high-fidelity optical arbitrary waveform generation in heterogeneous photonic integrated circuits.

    Science.gov (United States)

    Feng, Shaoqi; Qin, Chuan; Shang, Kuanping; Pathak, Shibnath; Lai, Weicheng; Guan, Binbin; Clements, Matthew; Su, Tiehui; Liu, Guangyao; Lu, Hongbo; Scott, Ryan P; Ben Yoo, S J

    2017-04-17

    This paper demonstrates rapidly reconfigurable, high-fidelity optical arbitrary waveform generation (OAWG) in a heterogeneous photonic integrated circuit (PIC). The heterogeneous PIC combines advantages of high-speed indium phosphide (InP) modulators and low-loss, high-contrast silicon nitride (Si3N4) arrayed waveguide gratings (AWGs) so that high-fidelity optical waveform syntheses with rapid waveform updates are possible. The generated optical waveforms spanned a 160 GHz spectral bandwidth starting from an optical frequency comb consisting of eight comb lines separated by 20 GHz channel spacing. The Error Vector Magnitude (EVM) values of the generated waveforms were approximately 16.4%. The OAWG module can rapidly and arbitrarily reconfigure waveforms upon every pulse arriving at 2 ns repetition time. The result of this work indicates the feasibility of truly dynamic optical arbitrary waveform generation where the reconfiguration rate or the modulator bandwidth must exceed the channel spacing of the AWG and the optical frequency comb.

  9. Vertical chip-to-chip coupling between silicon photonic integrated circuits using cantilever couplers.

    Science.gov (United States)

    Sun, Peng; Reano, Ronald M

    2011-02-28

    We demonstrate vertical chip-to-chip light coupling using silicon strip waveguide cantilever couplers. The guided-wave couplers consist of silicon strip waveguides embedded within silicon dioxide cantilevers. The cantilevers deflect 90° out-of-plane via residual stress, allowing vertical light coupling between separate chips. A chip-to-chip coupling loss of 2.5 dB per connection is measured for TE polarization and 1.1 dB for TM polarization at 1550 nm wavelength. The coupling loss varies by less than±0.8 dB within the wavelength range from 1500 nm to 1565 nm for both polarizations. The couplers enable broadband and compact system architectures involving high speed vertical data transport between photonic integrated circuits.

  10. High-Speed Edge-Detecting Line Scan Smart Camera

    Science.gov (United States)

    Prokop, Norman F.

    2012-01-01

    A high-speed edge-detecting line scan smart camera was developed. The camera is designed to operate as a component in a NASA Glenn Research Center developed inlet shock detection system. The inlet shock is detected by projecting a laser sheet through the airflow. The shock within the airflow is the densest part and refracts the laser sheet the most in its vicinity, leaving a dark spot or shadowgraph. These spots show up as a dip or negative peak within the pixel intensity profile of an image of the projected laser sheet. The smart camera acquires and processes in real-time the linear image containing the shock shadowgraph and outputting the shock location. Previously a high-speed camera and personal computer would perform the image capture and processing to determine the shock location. This innovation consists of a linear image sensor, analog signal processing circuit, and a digital circuit that provides a numerical digital output of the shock or negative edge location. The smart camera is capable of capturing and processing linear images at over 1,000 frames per second. The edges are identified as numeric pixel values within the linear array of pixels, and the edge location information can be sent out from the circuit in a variety of ways, such as by using a microcontroller and onboard or external digital interface to include serial data such as RS-232/485, USB, Ethernet, or CAN BUS; parallel digital data; or an analog signal. The smart camera system can be integrated into a small package with a relatively small number of parts, reducing size and increasing reliability over the previous imaging system..

  11. A low-power high-speed ultra-wideband pulse radio transmission system.

    Science.gov (United States)

    Wei Tang; Culurciello, E

    2009-10-01

    We present a low-power high-speed ultra-wideband (UWB) transmitter with a wireless transmission test platform. The system is specifically designed for low-power high-speed wireless implantable biosensors. The integrated transmitter consists of a compact pulse generator and a modulator. The circuit is fabricated in the 0.5-mum silicon-on-sapphire process and occupies 420 mum times 420 mum silicon area. The transmitter is capable of generating pulses with 1-ns width and the pulse rate can be controlled between 90 MHz and 270 MHz. We built a demonstration/testing system for the transmitter. The transmitter achieves a 14-Mb/s data rate. With 50% duty cycle data, the power consumption of the chip is between 10 mW and 21 mW when the transmission distance is from 3.2 to 4 m. The core circuit size is 70 mum times 130 mum.

  12. Investigation for connecting waveguide in off-planar integrated circuits.

    Science.gov (United States)

    Lin, Jie; Feng, Zhifang

    2017-09-01

    The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

  13. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  14. Novel paradigm for integrated photonics circuits: transient interconnection network

    Science.gov (United States)

    Fazio, Eugenio; Belardini, Alessandro; Bastiani, Lorenzo; Alonzo, Massimo; Chauvet, Mathieu; Zheludev, Nikolay I.; Soci, Cesare

    2017-01-01

    Self-confined beams and spatial solitons were always investigated for a purely academic point of view, describing their formation and cross-interaction. We propose a novel paradigm for integrated photonics circuits based on self-confined interconnections. We consider that circuits are not designed since beginning; a network of writing lasers provide the circuit configuration inside which information at a different wavelength travels. we propose new designs for interconnections and both digital and analog switching gates somehow inspired by Nature, following analog decision routes used in biological networks like brain synapsis or animal path finding.

  15. Advances in Thick Film Conductors for Microwave Integrated Circuits

    OpenAIRE

    Wilson, Larry K.; Rich, Debbie D.; Rich, Phil W.; R. Wayne Johnson

    1980-01-01

    New conductor pastes have made possible great improvements in the loss characteristics of thick film microwave integrated circuits. This paper presents data on the microwave characteristics of transmission structures made from newly developed copper, silver and gold conductor pastes on alumina and garnet substrates. The resistivity and microstructure for each conductor material was examined for correlation with microwave properties. These data show that thick film circuits can give excellent ...

  16. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  17. Single Event Transients in Linear Integrated Circuits

    Science.gov (United States)

    Buchner, Stephen; McMorrow, Dale

    2005-01-01

    On November 5, 2001, a processor reset occurred on board the Microwave Anisotropy Probe (MAP), a NASA mission to measure the anisotropy of the microwave radiation left over from the Big Bang. The reset caused the spacecraft to enter a safehold mode from which it took several days to recover. Were that to happen regularly, the entire mission would be compromised, so it was important to find the cause of the reset and, if possible, to mitigate it. NASA assembled a team of engineers that included experts in radiation effects to tackle the problem. The first clue was the observation that the processor reset occurred during a solar event characterized by large increases in the proton and heavy ion fluxes emitted by the sun. To the radiation effects engineers on the team, this strongly suggested that particle radiation might be the culprit, particularly when it was discovered that the reset circuit contained three voltage comparators (LM139). Previous testing revealed that large voltage transients, or glitches appeared at the output of the LM139 when it was exposed to a beam of heavy ions [NI96]. The function of the reset circuit was to monitor the supply voltage and to issue a reset command to the processor should the voltage fall below a reference of 2.5 V [PO02]. Eventually, the team of engineers concluded that ionizing particle radiation from the solar event produced a negative voltage transient on the output of one of the LM139s sufficiently large to reset the processor on MAP. Fortunately, as of the end of 2004, only two such resets have occurred. The reset on MAP was not the first malfunction on a spacecraft attributed to a transient. That occurred shortly after the launch of NASA s TOPEX/Poseidon satellite in 1992. It was suspected, and later confirmed, that an anomaly in the Earth Sensor was caused by a transient in an operational amplifier (OP-15) [KO93]. Over the next few years, problems on TDRS, CASSINI, [PR02] SOHO [HA99,HA01] and TERRA were also attributed

  18. High-Speed Electrochemical Imaging.

    Science.gov (United States)

    Momotenko, Dmitry; Byers, Joshua C; McKelvey, Kim; Kang, Minkyung; Unwin, Patrick R

    2015-09-22

    The design, development, and application of high-speed scanning electrochemical probe microscopy is reported. The approach allows the acquisition of a series of high-resolution images (typically 1000 pixels μm(-2)) at rates approaching 4 seconds per frame, while collecting up to 8000 image pixels per second, about 1000 times faster than typical imaging speeds used up to now. The focus is on scanning electrochemical cell microscopy (SECCM), but the principles and practicalities are applicable to many electrochemical imaging methods. The versatility of the high-speed scan concept is demonstrated at a variety of substrates, including imaging the electroactivity of a patterned self-assembled monolayer on gold, visualization of chemical reactions occurring at single wall carbon nanotubes, and probing nanoscale electrocatalysts for water splitting. These studies provide movies of spatial variations of electrochemical fluxes as a function of potential and a platform for the further development of high speed scanning with other electrochemical imaging techniques.

  19. Process Variations and Probabilistic Integrated Circuit Design

    CERN Document Server

    Haase, Joachim

    2012-01-01

    Uncertainty in key parameters within a chip and between different chips in the deep sub micron era plays a more and more important role. As a result, manufacturing process spreads need to be considered during the design process.  Quantitative methodology is needed to ensure faultless functionality, despite existing process variations within given bounds, during product development.   This book presents the technological, physical, and mathematical fundamentals for a design paradigm shift, from a deterministic process to a probability-orientated design process for microelectronic circuits.  Readers will learn to evaluate the different sources of variations in the design flow in order to establish different design variants, while applying appropriate methods and tools to evaluate and optimize their design.  Trains IC designers to recognize problems caused by parameter variations during manufacturing and to choose the best methods available to mitigate these issues during the design process; Offers both qual...

  20. High-speed photonics interconnects

    CERN Document Server

    Chrostowski, Lukas

    2013-01-01

    Dramatic increases in processing power have rapidly scaled on-chip aggregate bandwidths into the Tb/s range. This necessitates a corresponding increase in the amount of data communicated between chips, so as not to limit overall system performance. To meet the increasing demand for interchip communication bandwidth, researchers are investigating the use of high-speed optical interconnect architectures. Unlike their electrical counterparts, optical interconnects offer high bandwidth and negligible frequency-dependent loss, making possible per-channel data rates of more than 10 Gb/s. High-Speed

  1. Silica Integrated Optical Circuits Based on Glass Photosensitivity

    Science.gov (United States)

    Abushagur, Mustafa A. G.

    1999-01-01

    Integrated optical circuits play a major rule in the new photonics technology both in communication and sensing due to their small size and compatibility with integrated circuits. Currently integrated optical circuits (IOCs) are fabricated using similar manufacturing to those used in the semiconductor industry. In this study we are considering a new technique to fabricate IOCs which does not require layers of photolithography, depositing and etching. This method is based on the photosensitivity of germanosilicate glasses. Waveguides and other IOC devises can be patterned in these glasses by exposing them using UV lasers. This exposure by UV light changes the index of refraction of the germanosilicate glass. This technique enjoys both the simplicity and flexibility of design and fabrication with also the potential of being fast and low cost.

  2. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  3. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  4. Integrated circuits for particle physics experiments

    CERN Document Server

    Snoeys, W; Campbell, M; Cantatore, E; Faccio, F; Heijne, Erik H M; Jarron, Pierre; Kloukinas, Kostas C; Marchioro, A; Moreira, P; Toifl, Thomas H; Wyllie, Ken H

    2000-01-01

    High energy particle physics experiments investigate the nature of matter through the identification of subatomic particles produced in collisions of protons, electrons, or heavy ions which have been accelerated to very high energies. Future experiments will have hundreds of millions of detector channels to observe the interaction region where collisions take place at a 40 MHz rate. This paper gives an overview of the electronics requirements for such experiments and explains how data reduction, timing distribution, and radiation tolerance in commercial CMOS circuits are achieved for these big systems. As a detailed example, the electronics for the innermost layers of the future tracking detector, the pixel vertex detector, is discussed with special attention to system aspects. A small-scale prototype (130 channels) implemented in standard 0.25 mu m CMOS remains fully functional after a 30 Mrad(SiO/sub 2/) irradiation. A full-scale pixel readout chip containing 8000 readout channels in a 14 by 16 mm/sup 2/ ar...

  5. High-speed OTDM switching

    DEFF Research Database (Denmark)

    Jepsen, Kim Stokholm; Mikkelsen, Benny; Clausen, Anders

    1998-01-01

    Optical TDM (OTDM) continues to be of interest both for point-point transmission and as a networking technology for both LANs and long-distance fibre transmission. Recent research has demonstrated enabling techniques for OTDM networks at high speeds. In conclusion, OTDM is emerging as an attracti...

  6. Electro-optic properties of GaInAsSb/GaAs quantum well for high-speed integrated optoelectronic devices

    Science.gov (United States)

    Thoma, Jiri; Liang, Baolai; Reyner, Charles; Ochalski, Tomasz; Williams, David; Hegarty, Stephen P.; Huffaker, Diana; Huyet, Guillaume

    2013-01-01

    The electro-optic properties of strained GaInAsSb/GaAs quantum wells (QWs) are investigated. A single QW p-i-n sample was grown by molecular beam epitaxy with antimony (Sb) pre-deposition technique. We numerically predict and experimentally verify a strong quantum confined Stark shift of 40 nm. We also predict a fast absorption recovery times crucial of high-speed optoelectronic devices mainly due to strong electron tunneling and thermionic emission. Predicted recovery times are corroborated by bias and temperature dependent time-resolved photoluminescence measurements indicating (≤30 ps) recovery times. This makes GaInAsSb QW an attractive material particularly for electroabsorption modulators and saturable absorbers.

  7. Biochips: The Integrated Circuit of Biology

    DEFF Research Database (Denmark)

    Madsen, Jan

    2012-01-01

    Microfluidic biochips integrate different biochemical analysis functionalities (e.g., dispensers, filters, mixers, separators, detectors) on-chip, miniaturizing the macroscopic chemical and biological processes often processed by lab-robots, to a sub-millimeter scale. These microsystems offer sev...

  8. Photonic integrated circuits for NG-EPON

    Science.gov (United States)

    Rodrigues, Carla; Rodrigues, Francisco; Lima, Mário; Teixeira, António

    2017-08-01

    This paper intends to propose a monolithic photonic integrated InP transceiver for Next Generation of Ethernet Passive Optical Network (NG-EPON). The presented architecture was designed as an Optical Network Unit (ONU). The concept behind the suggested transceiver architecture is here presented together with the steps necessary to deploy the proposed solution.

  9. 75 FR 75694 - Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing...

    Science.gov (United States)

    2010-12-06

    ... United States after importation of certain semiconductor integrated circuits using tungsten metallization... COMMISSION Certain Semiconductor Integration Circuits Using Tungsten Metallization and Products Containing... Manufacturing Corporation of China; Integrated Device Technology, Inc. of San Jose, California; and Nanya...

  10. Bioluminescent bioreporter integrated circuit devices and methods for detecting ammonia

    Energy Technology Data Exchange (ETDEWEB)

    Simpson, Michael L [Knoxville, TN; Paulus, Michael J [Knoxville, TN; Sayler, Gary S [Blaine, TN; Applegate, Bruce M [West Lafayette, IN; Ripp, Steven A [Knoxville, TN

    2007-04-24

    Monolithic bioelectronic devices for the detection of ammonia includes a microorganism that metabolizes ammonia and which harbors a lux gene fused with a heterologous promoter gene stably incorporated into the chromosome of the microorganism and an Optical Application Specific Integrated Circuit (OASIC). The microorganism is generally a bacterium.

  11. Classical Conditioning with Pulsed Integrated Neural Networks: Circuits and System

    DEFF Research Database (Denmark)

    Lehmann, Torsten

    1998-01-01

    In this paper we investigate on-chip learning for pulsed, integrated neural networks. We discuss the implementational problems the technology imposes on learning systems and we find that abiologically inspired approach using simple circuit structures is most likely to bring success. We develop a ...... chip to solve simple classical conditioning tasks, thus verifying the design methodologies put forward in the paper....

  12. Reliability of lithium niobate Annealed Proton Exchanged integrated optical circuits

    Science.gov (United States)

    Kissa, Karl M.; Eng, Hogan; Lewis, David K.; Rodino, Vincent D.; Suchoski, Paul G., Jr.; Koziarz, Nancy A.

    1995-06-01

    Several studies have been performed recently that demonstrate the reliability of lithium niobate Annealed Proton Exchanged (APE) Integrated Optical Circuits (IOCs). Studies have been performed on APE IOC die as well as pigtailed and packaged devices. The tests indicate that the reliability of APE IOCs meet or surpass the needs of most military and commercial applications.

  13. Three-dimensional integrated circuit design

    CERN Document Server

    Xie, Yuan; Sapatnekar, Sachin S

    2009-01-01

    This book presents an overview of the field of 3D IC design, with an emphasis on electronic design automation (EDA) tools and algorithms that can enable the adoption of 3D ICs, and the architectural implementation and potential for future 3D system design. The aim of this book is to provide the reader with a complete understanding of: the promise of 3D ICs in building novel systems that enable the chip industry to continue along the path of performance scaling, the state of the art in fabrication technologies for 3D integration, the most prominent 3D-specific EDA challenges, along with solutio

  14. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  15. Automated Cell Synthesis of Analog Integrated Circuit Layout Anasyn.

    Science.gov (United States)

    Stanojevich, Bob Srbislav

    This thesis describes a novel model to automate cell generation for the design of analog integrated circuits and the conclusions about important features that such automation should include. This research represents the first attempt to address this problem by analyzing relevant issues of what constitutes an analog cell and how a technique can be implemented to generate these cells automatically. Our motivation for doing this is the critical limitations to circuit performance which arise from cell design. This thesis defines unique construction properties for the layout of some commonly used analog circuit topologies or cells. This thesis defines the physical layout of analog circuit cells beyond simple geometrical description. Each cell is an independent object that can be interfaced and communicated with. This thesis has extended the concept of an analog cell even further by incorporating synthesis rules into the cell definition. These rules are used to dynamically construct the optimized layout that will satisfy many of the options encountered in actual analog circuit design such as area, matching, tolerance, element rationing and parasitic components. This model can construct complex geometric shapes such as common-centroids, waffles, interdigitated, cascode etc. that are optimized at device level with the precise models for parasitic components. Furthermore, Object-Oriented implementation used in this thesis allow for easy integration of this work into other CAD tools. To demonstrate the feasibility and correctness of the ideas described in this thesis, a CAD tool ANASYN has been written. To test and demonstrate the utility and the performance developed, a variety of test cells have been generated. Data presented clearly demonstrate the uniqueness, flexibility, and precision of the analog circuit layout cells implemented in this research thesis. In addition, one test chip and one design chip have been laid out using cells generated by ANASYN and fabricated at

  16. Flexible circuits with integrated switches for robotic shape sensing

    Science.gov (United States)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  17. High speed cryogenic monodisperse targets

    Science.gov (United States)

    Boukharov, A.; Vishnevkii, E.

    2017-11-01

    The basic possibility of creation of high speed cryogenic monodisperse targets is shown. According to calculations at input of thin liquid cryogenic jets with a velocity of bigger 100 m/s in vacuum the jets don’t manage to freeze at distance to 1 mm and can be broken into monodisperse drops. Drops due to evaporation are cooled and become granules. High speed cryogenic monodisperse targets have the following advantages: direct input in vacuum (there is no need for a chamber of a triple point chamber and sluices), it is possible to use the equipment of a cluster target, it is possible to receive targets with a diameter of D 100m/s), exact synchronization of the target hitting moment in a beam with the moment of sensors turning on.

  18. High-speed AC motors

    Energy Technology Data Exchange (ETDEWEB)

    Jokinen, T.; Arkkio, A. [Helsinki University of Technology Laboratory of Electromechanics, Otaniemi (Finland)

    1997-12-31

    The paper deals with various types of highspeed electric motors, and their limiting powers. Standard machines with laminated rotors can be utilised if the speed is moderate. The solid rotor construction makes it possible to reach higher power and speed levels than those of laminated rotors. The development work on high-speed motors done at Helsinki University of Technology is presented, too. (orig.) 12 refs.

  19. GaAs Photonic Integrated Circuit (PIC) development for high performance communications

    Energy Technology Data Exchange (ETDEWEB)

    Sullivan, C.T.

    1998-03-01

    Sandia has established a foundational technology in photonic integrated circuits (PICs) based on the (Al,Ga,In)As material system for optical communication, radar control and testing, and network switching applications at the important 1.3{mu}m/1.55{mu}m wavelengths. We investigated the optical, electrooptical, and microwave performance characteristics of the fundamental building-block PIC elements designed to be as simple and process-tolerant as possible, with particular emphasis placed on reducing optical insertion loss. Relatively conventional device array and circuit designs were built using these PIC elements: (1) to establish a baseline performance standard; (2) to assess the impact of epitaxial growth accuracy and uniformity, and of fabrication uniformity and yield; (3) to validate our theoretical and numerical models; and (4) to resolve the optical and microwave packaging issues associated with building fully packaged prototypes. Novel and more complex PIC designs and fabrication processes, viewed as higher payoff but higher risk, were explored in a parallel effort with the intention of meshing those advances into our baseline higher-yield capability as they mature. The application focus targeted the design and fabrication of packaged solitary modulators meeting the requirements of future wideband and high-speed analog and digital data links. Successfully prototyped devices are expected to feed into more complex PICs solving specific problems in high-performance communications, such as optical beamforming networks for phased array antennas.

  20. Integration issues of a photonic layer on top of a CMOS circuit

    Science.gov (United States)

    Fedeli, J. M.; Orobtchouk, R.; Seassal, C.; Vivien, L.

    2006-02-01

    Photonics on CMOS is the integration of CMOS technology and optics components to enable either improved functionality of the electronic circuit (e.g. optical clock distribution) or as a means to miniaturize optical functions (e.g. miniaturised transceiver). The Near Infra Red (NIR) wavelength range (1.3 or 1.55μm) was chosen for this to minimise the impact the light on the behaviour of the microelectronic components. The integration of a photonic layer on a CMOS circuit can be seen in different ways: A combined fabrication at the front end level, the wafer bonding of an SOI photonic circuit at the back-end level, or the insertion of an embedded photonic layer between metallization schemes. For combined fabrication, a silicon on insulator rib technology has been developed with low (0.4dB/cm) propagation loss, ultra-high speed Ge-on-Si photodetector and SiGe/Si modulators.. In the metal-semiconductor-metal (MSM) configuration, bandwith of 35 GHz at 1.3 μm and 1.55μm has been measured. In the second approach, a wafer bonding of silicon rib and stripe technologies was achieved above the metallization layers of a CMOS wafer. For the third method, direct fabrication of a photonic layer at the back-end level was achieved using low temperature processes. Waveguide technologies such as SiNx (loss 2dB/cm) or amorphous silicon (loss 5dB/cm) were developed and were followed by the molecular bonding of InP die, these were needed to create the optoelectronic components (sources and detectors). Using an InP microdisk, 50% coupling was achieved to a stripe silicon waveguide.

  1. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  2. Automated tuning, control and stabilization of photonic integrated circuits

    Science.gov (United States)

    O. De Aguiar, Douglas; Annoni, Andrea; Peserico, Nicola; Guglielmi, Emanuele; Carminati, Marco; Ferrari, Giorgio; Morichetti, Francesco

    2017-05-01

    The complexity scaling of silicon photonics circuits is raising novel needs related to control. Reconfigurable architectures need fast, accurate and robust procedures for the tuning and stabilization of their working point, counteracting temperature drifts originated by environmental fluctuations and mutual thermal crosstalk from surrounding integrated devices. In this contribution, we report on our recent achievements on the automated tuning, control and stabilization of silicon photonics architectures. The proposed control strategy exploits transparent integrated detectors to monitor non-invasively the light propagating in the silicon waveguides in key spots of the circuit. Local monitoring enables the partitioning of complex architectures in small photonic cells that can be easily tuned and controlled, with need for neither preliminary circuit calibration nor global optimization algorithms. The ability to monitor the Quality Of of Transmission (QoT) of the optical paths in Photonic Integrated Circuits (PICs) is also demonstrated with the use of channel labelling and non-invasive light monitoring. Several examples of applications are presented that include the automatic reconfiguration and feedback controlled stabilization of an 8×8 switch fabric based on Mach-Zehnder interferometers (MZIs) and the realization of a wavelength locking platform enabling feedback-control of silicon microring resonators (MRRs) for the realization of a 4×10 Gbit/s wavelength-division-multiplexing transmitter. The effectiveness and the robustness of the proposed approach for tuning and stabilization of the presented architectures is demonstrated by showing that no significant performance degradation is observed under uncooled operation for the silicon chip.

  3. Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

    CERN Document Server

    A Papa, David

    2013-01-01

    This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

  4. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2018-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  5. Integrated circuit electrometer and sweep circuitry for an atmospheric probe

    Science.gov (United States)

    Zimmerman, L. E.

    1971-01-01

    The design of electrometer circuitry using an integrated circuit operational amplifier with a MOSFET input is described. Input protection against static voltages is provided by a dual ultra low leakage diode or a neon lamp. Factors affecting frequency response leakage resistance, and current stability are discussed, and methods are suggested for increasing response speed and for eliminating leakage resistance and current instabilities. Based on the above, two practical circuits, one having a linear response and the other a logarithmic response, were designed and evaluated experimentally. The design of a sweep circuit to implement mobility measurements using atmospheric probes is presented. A triangular voltage waveform is generated and shaped to contain a step in voltage from zero volts in both positive and negative directions.

  6. Power-Integrated Circuit Active Leakage Current Detector

    Directory of Open Access Journals (Sweden)

    M. F. Bulacio

    2012-01-01

    Full Text Available Most of the failures of induction motors become insulation faults, causing a permanent damage. Using differential current transformers, a system capable of insulation fault detection was developed, based on the differential relay protection scheme. Both signal injection and fault detection circuitry were integrated in a single chip. The proposed scheme is faster than other existing protection and not restricted to protect induction motors, but several other devices (such as IGBTs and systems. This paper explains the principle of operation of fault protection scheme and analyzes an integrated implementation through simulations and experimental results. A power-integrated circuit (PIC implementation is presented.

  7. Ultra high-speed sorting.

    Science.gov (United States)

    Leary, James F

    2005-10-01

    Cell sorting has a history dating back approximately 40 years. The main limitation has been that, although flow cytometry is a science, cell sorting has been an art during most of this time. Recent advances in assisting technologies have helped to decrease the amount of expertise necessary to perform sorting. Droplet-based sorting is based on a controlled disturbance of a jet stream dependent on surface tension. Sorting yield and purity are highly dependent on stable jet break-off position. System pressures and orifice diameters dictate the number of droplets per second, which is the sort rate limiting step because modern electronics can more than handle the higher cell signal processing rates. Cell sorting still requires considerable expertise. Complex multicolor sorting also requires new and more sophisticated sort decisions, especially when cell subpopulations are rare and need to be extracted from background. High-speed sorting continues to pose major problems in terms of biosafety due to the aerosols generated. Cell sorting has become more stable and predictable and requires less expertise to operate. However, the problems of aerosol containment continue to make droplet-based cell sorting problematical. Fluid physics and cell viability restraints pose practical limits for high-speed sorting that have almost been reached. Over the next 5 years there may be advances in fluidic switching sorting in lab-on-a-chip microfluidic systems that could not only solve the aerosol and viability problems but also make ultra high-speed sorting possible and practical through massively parallel and exponential staging microfluidic architectures.

  8. Micromachined Integrated Quantum Circuit Containing a Superconducting Qubit

    Science.gov (United States)

    Brecht, T.; Chu, Y.; Axline, C.; Pfaff, W.; Blumoff, J. Z.; Chou, K.; Krayzman, L.; Frunzio, L.; Schoelkopf, R. J.

    2017-04-01

    We present a device demonstrating a lithographically patterned transmon integrated with a micromachined cavity resonator. Our two-cavity, one-qubit device is a multilayer microwave-integrated quantum circuit (MMIQC), comprising a basic unit capable of performing circuit-QED operations. We describe the qubit-cavity coupling mechanism of a specialized geometry using an electric-field picture and a circuit model, and obtain specific system parameters using simulations. Fabrication of the MMIQC includes lithography, etching, and metallic bonding of silicon wafers. Superconducting wafer bonding is a critical capability that is demonstrated by a micromachined storage-cavity lifetime of 34.3 μ s , corresponding to a quality factor of 2 ×106 at single-photon energies. The transmon coherence times are T1=6.4 μ s , and T2echo=11.7 μ s . We measure qubit-cavity dispersive coupling with a rate χq μ/2 π =-1.17 MHz , constituting a Jaynes-Cummings system with an interaction strength g /2 π =49 MHz . With these parameters we are able to demonstrate circuit-QED operations in the strong dispersive regime with ease. Finally, we highlight several improvements and anticipated extensions of the technology to complex MMIQCs.

  9. Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

    Science.gov (United States)

    Liu, Yuanda; Ang, Kah-Wee

    2017-07-25

    Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10(3). Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

  10. Organic printed photonics: From microring lasers to integrated circuits.

    Science.gov (United States)

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  11. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Science.gov (United States)

    2011-09-19

    ... COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice... certain digital televisions containing integrated circuit devices and components thereof by reason of... the sale within the United States after importation of certain digital televisions containing...

  12. 77 FR 74027 - Certain Integrated Circuit Packages Provided with Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-12-12

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuit Packages Provided with Multiple Heat- Conducting Paths and Products... integrated circuit packages provided with multiple heat-conducting paths and products containing same by...

  13. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2011-06-10

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including... integrated circuits, chipsets, and products containing same including televisions, media players, and cameras...

  14. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-07-20

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice of... limited exclusion order against certain integrated circuits, chipsets, and products containing the same...

  15. 77 FR 39510 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not...

    Science.gov (United States)

    2012-07-03

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Determination Not... the sale within the United States after importation of certain semiconductor integrated circuit...

  16. Design techniques for low-voltage analog integrated circuits

    Science.gov (United States)

    Rakús, Matej; Stopjaková, Viera; Arbet, Daniel

    2017-08-01

    In this paper, a review and analysis of different design techniques for (ultra) low-voltage integrated circuits (IC) are performed. This analysis shows that the most suitable design methods for low-voltage analog IC design in a standard CMOS process include techniques using bulk-driven MOS transistors, dynamic threshold MOS transistors and MOS transistors operating in weak or moderate inversion regions. The main advantage of such techniques is that there is no need for any modification of standard CMOS structure or process. Basic circuit building blocks like differential amplifiers or current mirrors designed using these approaches are able to operate with the power supply voltage of 600 mV (or even lower), which is the key feature towards integrated systems for modern portable applications.

  17. Broadband opto-mechanical phase shifter for photonic integrated circuits

    Science.gov (United States)

    Guo, Xiang; Zou, Chang-Ling; Ren, Xi-Feng; Sun, Fang-Wen; Guo, Guang-Can

    2012-08-01

    A broadband opto-mechanical phase shifter for photonic integrated circuits is proposed and numerically investigated. The structure consists of a mode-carrying waveguide and a deformable non-mode-carrying nanostring, which are parallel with each other. Since the nanostring can be deflected by the optical gradient force between the waveguide and the nanostring, the effective refractive indices of the waveguide will be changed and a phase shift will be generated. The phase shift under different geometry sizes, launched powers and boundary conditions are calculated and the dynamical properties as well as the thermal noise's effect are also discussed. It is demonstrated that a π phase shift can be realized with only about 0.64 mW launched power and 50 μm long nanostring. The proposed phase shifter may find potential usage in future investigation of photonic integrated circuits.

  18. On-chip enzymatic microbiofuel cell-powered integrated circuits.

    Science.gov (United States)

    Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

    2017-05-16

    A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

  19. Gigahertz flexible graphene transistors for microwave integrated circuits.

    Science.gov (United States)

    Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

    2014-08-26

    Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

  20. Millimeter-wave and optoelectronic applications of heterostructure integrated circuits

    Science.gov (United States)

    Pavlidis, Dimitris

    1991-01-01

    The properties are reviewed of heterostructure devices for microwave-monolithic-integrated circuits (MMICs) and optoelectronic integrated circuits (OICs). Specific devices examined include lattice-matched and pseudomorphic InAlAs/InGaAs high-electron mobility transistors (HEMTs), mixer/multiplier diodes, and heterojunction bipolar transistors (HBTs) developed with a number of materials. MMICs are reviewed that can be employed for amplification, mixing, and signal generation, and receiver/transmitter applications are set forth for OICs based on GaAs and InP heterostructure designs. HEMTs, HBTs, and junction-FETs can be utilized in combination with PIN, MSM, and laser diodes to develop novel communication systems based on technologies that combine microwave and photonic capabilities.

  1. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  2. Radiation Testing and Evaluation Issues for Modern Integrated Circuits

    Science.gov (United States)

    LaBel, Kenneth A.; Cohn, Lew M.

    2005-01-01

    Abstract. Changes in modern integrated circuit (IC) technologies have modified the way we approach and conduct radiation tolerance and testing of electronics. These changes include scaling of geometries, new materials, new packaging technologies, and overall speed and device complexity challenges. In this short course section, we will identify and discuss these issues as they impact radiation testing, modeling, and effects mitigation of modern integrated circuits. The focus will be on CMOS-based technologies, however, other high performance technologies will be discussed where appropriate. The effects of concern will be: Single-Event Effects (SEE) and steady state total ionizing dose (TID) IC response. However, due to the growing use of opto-electronics in space systems issues concerning displacement damage testing will also be considered. This short course section is not intended to provide detailed "how-to-test" information, but simply provide a snapshot of current challenges and some of the approaches being considered.

  3. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  4. ELECTRON AND OPTICAL BEAM TESTING OF INTEGRATED CIRCUITS

    OpenAIRE

    Collin, J.-P.

    1989-01-01

    The evolution of Integrated Circuits technology and architecture is pushing today the associated test and characterization technology to even higher levels. The test must not only present even higher parametric performances like voltage, temporal and spatial resolutions and a good fault coverage but also high level functionalities like a CAD link and automation capabilities. Each and all of these characteristics, when they are identified as measurement and functional performances, need more a...

  5. Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

    Science.gov (United States)

    2017-03-01

    H- field; Probe Array; Counterfeit Detection; IC Trust . Introduction Counterfeiting is a huge flail that still continues to serve in the...Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits   contains the RF-switch matrix and broad-band (BB) low noise amplifiers (LNAs...fabricated, tested and used for IC’s TRUST . Measurement setup has been proposed for system validation and of IC scanning surface. Validation test of the

  6. Integrated Circuit Readout for the Silicon Sensor Test Station

    OpenAIRE

    Atkin, E; Kluev, A.; Silaev, A.; Fedenko, A.; Karmanov, D.; Merkin, M.(Moscow State University, Moscow, Russia); Voronin, A.

    2009-01-01

    Various chips for the silicon sensors measurements are described. These chips are based on 0.35 um and 0.18um CMOS technology. Several analog chips together with self-trigger /derandomizer one allow to measure silicon sensors designed for different purposes. Tracking systems, calorimeters, particle charge measurement system and other application sensors can be investigated by the integrated circuit readout with laser or radioactive sources. Also electrical parameters of silicon sensors can be...

  7. Mathematical model of an integrated circuit cooling through cylindrical rods

    OpenAIRE

    Beltrán-Prieto, Luis Antonio; Beltrán-Prieto, Juan Carlos; Komínková Oplatková, Zuzana

    2017-01-01

    One of the main challenges in integrated circuits development is to propose alternatives to handle the extreme heat generated by high frequency of electrons moving in a reduced space that cause overheating and reduce the lifespan of the device. The use of cooling fins offers an alternative to enhance the heat transfer using combined a conduction-convection systems. Mathematical model of such process is important for parametric design and also to gain information about temperature distribution...

  8. Short circuit analysis of distribution system with integration of DG

    DEFF Research Database (Denmark)

    Su, Chi; Liu, Zhou; Chen, Zhe

    2014-01-01

    Integration of distributed generation (DG) such as wind turbines into distribution system is increasing all around the world, because of the flexible and environmentally friendly characteristics. However, DG integration may change the pattern of the fault currents in the distribution system...... during both balanced and unbalanced faults. Major factors such as external grid short circuit power capacity, WT integration location, connection type of WT integration transformer are taken into account. In turn, the challenges brought to the protection system in the distribution network are presented...... and as a result bring challenges to the network protection system. This problem has been frequently discussed in the literature, but mostly considering only the balanced fault situation. This paper presents an investigation on the influence of full converter based wind turbine (WT) integration on fault currents...

  9. 77 FR 39735 - Certain Integrated Circuit Packages Provided With Multiple Heat-Conducting Paths and Products...

    Science.gov (United States)

    2012-07-05

    ... Integrated Circuit Packages Provided With Multiple Heat- Conducting Paths and Products Containing Same... within the United States after importation of certain integrated circuit packages provided with multiple... importation, or the sale within the United States after importation of certain integrated circuit packages...

  10. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Science.gov (United States)

    2010-02-04

    ... COMMISSION In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice... importation, and sale within the United States after importation of certain semiconductor integrated circuits... infringement certain LSI integrated circuits, as well as certain Seagate hard disk drives that contain the...

  11. 77 FR 64826 - Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation...

    Science.gov (United States)

    2012-10-23

    ... COMMISSION Certain Integrated Circuit Chips and Products Containing the Same; Institution of Investigation... integrated circuit chips and products containing the same by reason of infringement of certain claims of U.S... importation of certain integrated circuit chips and products containing the same that infringe one or more of...

  12. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  13. Pneumatic oscillator circuits for timing and control of integrated microfluidics

    Science.gov (United States)

    Duncan, Philip N.; Nguyen, Transon V.; Hui, Elliot E.

    2013-01-01

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices. PMID:24145429

  14. Pneumatic oscillator circuits for timing and control of integrated microfluidics.

    Science.gov (United States)

    Duncan, Philip N; Nguyen, Transon V; Hui, Elliot E

    2013-11-05

    Frequency references are fundamental to most digital systems, providing the basis for process synchronization, timing of outputs, and waveform synthesis. Recently, there has been growing interest in digital logic systems that are constructed out of microfluidics rather than electronics, as a possible means toward fully integrated laboratory-on-a-chip systems that do not require any external control apparatus. However, the full realization of this goal has not been possible due to the lack of on-chip frequency references, thus requiring timing signals to be provided from off-chip. Although microfluidic oscillators have been demonstrated, there have been no reported efforts to characterize, model, or optimize timing accuracy, which is the fundamental metric of a clock. Here, we report pneumatic ring oscillator circuits built from microfluidic valves and channels. Further, we present a compressible-flow analysis that differs fundamentally from conventional circuit theory, and we show the utility of this physically based model for the optimization of oscillator stability. Finally, we leverage microfluidic clocks to demonstrate circuits for the generation of phase-shifted waveforms, self-driving peristaltic pumps, and frequency division. Thus, pneumatic oscillators can serve as on-chip frequency references for microfluidic digital logic circuits. On-chip clocks and pumps both constitute critical building blocks on the path toward achieving autonomous laboratory-on-a-chip devices.

  15. FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

    Directory of Open Access Journals (Sweden)

    Zhengwei Hao

    2012-01-01

    Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

  16. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = ‑1.

  17. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  18. Integrated diode circuits for greater than 1 THz

    Science.gov (United States)

    Schoenthal, Gerhard Siegbert

    The terahertz frequency band, spanning from roughly 100 GHz to 10 THz, forms the transition from electronics to photonics. This band is often referred to as the "terahertz technology gap" because it lacks typical microwave and optical components. The deficit of terahertz devices makes it difficult to conduct important scientific measurements that are exclusive to this band in fields such as radio astronomy and chemical spectroscopy. In addition, a number of scientific, military and commercial applications will become more practical when a suitable terahertz technology is developed. UVa's Applied Electrophysics Laboratory has extended non-linear microwave diode technology into the terahertz region. Initial success was achieved with whisker-contacted diodes and then discrete planar Schottky diodes soldered onto quartz circuits. Work at UVa and the Jet Propulsion Laboratory succeeded in integrating this diode technology onto low dielectric substrates, thereby producing more practical components with greater yield and improved performance. However, the development of circuit integration technologies for greater than 1 THz and the development of broadly tunable sources of terahertz power remain as major research goals. Meeting these critical needs is the primary motivation for this research. To achieve this goal and demonstrate a useful prototype for one of our sponsors, this research project has focused on the development of a Sideband Generator at 1.6 THz. This component allows use of a fixed narrow band source as a tunable power source for terahertz spectroscopy and compact range radar. To prove the new fabrication and circuit technologies, initial devices were fabricated and tested at 200 and 600 GHz. These circuits included non-ohmic cathodes, air-bridged fingers, oxideless anode formation, and improved quartz integration processes. The excellent performance of these components validated these new concepts. The prototype process was then further optimized to

  19. Development of Integrated Single Flux Quantum - Superconducting Qubit Circuits

    Science.gov (United States)

    Leonard, Edward, Jr.; Thorbeck, Ted; Zhu, Shaojiang; Howington, Caleb; Hutchings, Matthew; Nelson, Jj; Plourde, Britton; McDermott, Robert

    Significant theoretical and experimental progress has been made in recent years towards a scalable superconducting quantum circuit architecture. Here we present a first attempt to integrate classical control elements from the single flux quantum (SFQ) digital logic family with a superconducting transom qubit on a single chip. The SFQ driving circuit is fabricated in a six-layer high-Jc Nb/Al-AlOx/Nb junction process while the transmon qubit is subsequently formed using submicron Al-AlOx-Al junctions grown by double-angle evaporation. We investigate sources of decoherence associated with the more complex fabrication process and describe first attempts to perform coherent qubit manipulations using resonant trains of SFQ pulses.

  20. A novel readout integrated circuit for ferroelectric FPA detector

    Science.gov (United States)

    Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

    2017-11-01

    Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

  1. Method of making thermally-isolated silicon-based integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.; Bauer, Todd

    2017-11-21

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  2. Thermally-isolated silicon-based integrated circuits and related methods

    Energy Technology Data Exchange (ETDEWEB)

    Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

    2017-05-09

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  3. Lithography for enabling advances in integrated circuits and devices.

    Science.gov (United States)

    Garner, C Michael

    2012-08-28

    Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

  4. Advances in integrated photonic circuits for packet-switched interconnection

    Science.gov (United States)

    Williams, Kevin A.; Stabile, Ripalta

    2014-03-01

    Sustained increases in capacity and connectivity are needed to overcome congestion in a range of broadband communication network nodes. Packet routing and switching in the electronic domain are leading to unsustainable energy- and bandwidth-densities, motivating research into hybrid solutions: optical switching engines are introduced for massive-bandwidth data transport while the electronic domain is clocked at more modest GHz rates to manage routing. Commercially-deployed optical switching engines using MEMS technologies are unwieldy and too slow to reconfigure for future packet-based networking. Optoelectronic packet-compliant switch technologies have been demonstrated as laboratory prototypes, but they have so far mostly used discretely pigtailed components, which are impractical for control plane development and product assembly. Integrated photonics has long held the promise of reduced hardware complexity and may be the critical step towards packet-compliant optical switching engines. Recently a number of laboratories world-wide have prototyped optical switching circuits using monolithic integration technology with up to several hundreds of integrated optical components per chip. Our own work has focused on multi-input to multi-output switching matrices. Recently we have demonstrated 8×8×8λ space and wavelength selective switches using gated cyclic routers and 16×16 broadband switching chips using monolithic multi-stage networks. We now operate these advanced circuits with custom control planes implemented with FPGAs to explore real time packet routing in multi-wavelength, multi-port test-beds. We review our contributions in the context of state of the art photonic integrated circuit technology and packet optical switching hardware demonstrations.

  5. Towards high-speed scanning tunneling microscopy

    NARCIS (Netherlands)

    Tabak, Femke Chantal

    2013-01-01

    In this thesis, two routes towards high-speed scanning tunneling microscopy (STM) are described. The first possibility for high-speed scanning that is discussed is the use of MEMS (Micro-Electro Mechanical Systems) devices as high-speed add-ons in STM microscopes. The functionality of these devices

  6. High-speed imaging at high x-ray energy: CdTe sensors coupled to charge-integrating pixel array detectors

    Energy Technology Data Exchange (ETDEWEB)

    Becker, Julian; Tate, Mark W.; Shanks, Katherine S.; Philipp, Hugh T.; Weiss, Joel T.; Purohit, Prafull [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Chamberlain, Darol [Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States); Gruner, Sol M., E-mail: smg26@cornell.edu [Laboratory of Atomic and Solid State Physics, Cornell University, Ithaca, NY 14853 (United States); Cornell High Energy Synchrotron Source (CHESS), Cornell University, Ithaca, NY 14853 (United States)

    2016-07-27

    Pixel Array Detectors (PADs) consist of an x-ray sensor layer bonded pixel-by-pixel to an underlying readout chip. This approach allows both the sensor and the custom pixel electronics to be tailored independently to best match the x-ray imaging requirements. Here we describe the hybridization of CdTe sensors to two different charge-integrating readout chips, the Keck PAD and the Mixed-Mode PAD (MM-PAD), both developed previously in our laboratory. The charge-integrating architecture of each of these PADs extends the instantaneous counting rate by many orders of magnitude beyond that obtainable with photon counting architectures. The Keck PAD chip consists of rapid, 8-frame, in-pixel storage elements with framing periods <150 ns. The second detector, the MM-PAD, has an extended dynamic range by utilizing an in-pixel overflow counter coupled with charge removal circuitry activated at each overflow. This allows the recording of signals from the single-photon level to tens of millions of x-rays/pixel/frame while framing at 1 kHz. Both detector chips consist of a 128×128 pixel array with (150 µm){sup 2} pixels.

  7. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  8. An analog memory integrated circuit for waveform acquisition up to 900 MHz

    Science.gov (United States)

    Haller, G. M.; Wooley, B. A.

    1993-12-01

    The design and implementation of a switched-capacitor memory suitable for capturing high-speed analog waveforms is described. Highlights of the presented circuit are a 900 MHz sampling frequency (generated on chip), input signal independent cell pedestals and sampling instances, and cell gains that are insensitive to component sizes. A two-channel version of the memory with 32 cells for each channel has been integrated in a 2-micron complementary metal oxide semiconductor (CMOS) process with poly-to-poly capacitors. The measured rms cel pedestal variation in a channel after baseline subtraction is less than 0.3 mV across the full input signal range. The cell-to-cell gain matching is better than 0.01% rms, and the nonlinearity is less than 0.03% for a 2.5-V input range. The dynamic range of the memory exceeds 13 bits, and the peak signal-to-(noise+distortion) ratio for a 21.4 MHz sine wave sampled at 900 MHz is 59 dB.

  9. Integrated circuits: Resistless processing simplifies production and cuts costs

    Science.gov (United States)

    Weiner, K.

    1993-03-01

    Reducing the complexity and cost of producing deep-submicrometer integrated circuits (IC's) will soon be possible using a revolutionary approach being developed at the Lawrence Livermore National Laboratory (LLNL). Resistless Projection Doping (RPD) will eliminate the need for photoresist processing during the impurity doping step. This single innovation will reduce the doping sequence from 13 steps to 1 and eliminate the need for five pieces of capital equipment costing more than $5 million. The overall cost of high-volume wafer fabrication will be reduced by more than 10 percent. In addition, the LLNL RPD machine is compact and modular, minimizing facilities costs when compared to today's industry-standard doping equipment. These physical characteristics of the machine also allow the RPD process to be easily incorporated into single-wafer, 'cluster' processing tools. When integrated with existing deposition, etching, and annealing steps and developing lithography techniques, the LLNL doping process completes the technology set required to produce a flexible fabrication facility of the future. At one-fifth the cost of current mega-fabrication facilities, the availability of these compact, low-volume, smart factories will give US manufacturers a substantial competitive advantage in the world-wide marketplace for high-value custom and semi-custom integrated circuits.

  10. Photonic Packaging: Transforming Silicon Photonic Integrated Circuits into Photonic Devices

    Directory of Open Access Journals (Sweden)

    Lee Carroll

    2016-12-01

    Full Text Available Dedicated multi-project wafer (MPW runs for photonic integrated circuits (PICs from Si foundries mean that researchers and small-to-medium enterprises (SMEs can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

  11. Numerical counting ratemeter with variable time constant and integrated circuits; Ictometre numerique a constante de temps variable a circuits integres

    Energy Technology Data Exchange (ETDEWEB)

    Kaiser, J.; Fuan, J. [Commissariat a l' Energie Atomique, Saclay (France). Centre d' Etudes Nucleaires

    1967-07-01

    We present here the prototype of a numerical counting ratemeter which is a special version of variable time-constant frequency meter (1). The originality of this work lies in the fact that the change in the time constant is carried out automatically. Since the criterion for this change is the accuracy in the annunciated result, the integration time is varied as a function of the frequency. For the prototype described in this report, the time constant varies from 1 sec to 1 millisec. for frequencies in the range 10 Hz to 10 MHz. This prototype is built entirely of MECL-type integrated circuits from Motorola and is thus contained in two relatively small boxes. (authors) [French] Nous presentons ici le prototype d'un ictometre numerique, celui-ci etant une version speciale d'un frequencemetre a constante de temps variable (1). Le nouvel interet de cette etude est le fait que le changement de la constante de temps se fait automatiquement. Le critere de ce changement etant la precision du resultat a afficher on change alors le temps d'integration en fonction de la frequence. Pour le prototype decrit dans ce rapport la constante de temps varie entre 1 s et 1 ms pour des frequences allant de 10 Hz a 10 MHz. Ce prototype est entierement realise en circuit integre type MECL de Motorola et se presente en consequence dans deux boitiers d'une taille relativement petite. (auteurs)

  12. Extremely flexible nanoscale ultrathin body silicon integrated circuits on plastic.

    Science.gov (United States)

    Shahrjerdi, Davood; Bedell, Stephen W

    2013-01-09

    In recent years, flexible devices based on nanoscale materials and structures have begun to emerge, exploiting semiconductor nanowires, graphene, and carbon nanotubes. This is primarily to circumvent the existing shortcomings of the conventional flexible electronics based on organic and amorphous semiconductors. The aim of this new class of flexible nanoelectronics is to attain high-performance devices with increased packing density. However, highly integrated flexible circuits with nanoscale transistors have not yet been demonstrated. Here, we show nanoscale flexible circuits on 60 Å thick silicon, including functional ring oscillators and memory cells. The 100-stage ring oscillators exhibit the stage delay of ~16 ps at a power supply voltage of 0.9 V, the best reported for any flexible circuits to date. The mechanical flexibility is achieved by employing the controlled spalling technology, enabling the large-area transfer of the ultrathin body silicon devices to a plastic substrate at room temperature. These results provide a simple and cost-effective pathway to enable ultralight flexible nanoelectronics with unprecedented level of system complexity based on mainstream silicon technology.

  13. Integrated biocircuits: engineering functional multicellular circuits and devices.

    Science.gov (United States)

    Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

    2018-01-19

    Novel in vitro platforms are currently revolutionizing the study and reconstruction of cellular circuitry to bypass the pertaining obstacles of data retrieval in vivo. While earlier approaches have provided great insights into culturing circuits in planar dissociated cell culture systems, the lack of full control over network activity and formation limits our understanding of their functionality. Thus, integrating various controllable parameters are required in creating a suitable microenvironment including cell patterning, highly-specified electrical and chemical stimuli, and rational circuit formation via logic functions. Recent advancements in organoid and 3D culture systems account for another major microenvironment factor of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain and other neural structures and compare them to disease models to identify the underlying principles of pathology. This perspective focuses on exploring the current state of the art of living multicellular device technologies to provide knowledge of the advancements of the fabrication processes and identify the current biological principles that are applied in designing these devices. It then provides perspectives and proposes new insights into the future of these devices within the scope of living cellular devices that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics. © 2018 IOP Publishing Ltd.

  14. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  15. Custom Integrated Circuit Design for Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere

    ) are contained in the probe. Due to the nature of ultrasonic transducers, the transmitting circuitry needs to generate high-voltage pulses to drive them. Furthermore, the low-voltage receiving circuitry has to provide high enough signal to noise ratio (SNR) in order to generate usable imaging. For the purpose...... of evaluating the feasibility of the transmitting and receiving circuitry of a handheld probe for portable ultrasound scanners, three integrated circuit prototypes have been fabricated. Measurements have been performed on all of them with satisfactory results. The first part of this project is focused...

  16. High-Speed, Integrated Ablation Cell and Dual Concentric Injector Plasma Torch for Laser Ablation-Inductively Coupled Plasma Mass Spectrometry.

    Science.gov (United States)

    Douglas, David N; Managh, Amy J; Reid, Helen J; Sharp, Barry L

    2015-11-17

    In recent years, laser ablation-inductively coupled plasma mass spectrometry (LA-ICPMS) has gained increasing importance for biological analysis, where ultratrace imaging at micrometer resolution is required. However, while undoubtedly a valuable research tool, the washout times and sensitivity of current technology have restricted its routine and clinical application. Long periods between sampling points are required to maintain adequate spatial resolution. Additionally, temporal signal dispersion reduces the signal-to-noise ratio, which is a particular concern when analyzing discrete samples, such as individual particles or cells. This paper describes a novel, two-volume laser ablation cell and integrated ICP torch designed to minimize aerosol dispersion for fast, efficient sample transport. The holistic design utilizes a short, continuous diameter fused silica conduit, which extends from the point of ablation, through the ICP torch, and into the base of the plasma. This arrangement removes the requirement for a dispersive component for argon addition, and helps to keep the sample on axis with the ICP cone orifice. Hence, deposition of sample on the cones is theoretically reduced with a resulting improvement in the absolute sensitivity (counts per unit mole). The system described here achieved washouts of 1.5, 3.2, and 4.9 ms for NIST 612 glass, at full width half, 10%, and 1% maximum, respectively, with an 8-14-fold improvement in absolute sensitivity, compared to a single volume ablation cell. To illustrate the benefits of this performance, the system was applied to a contemporary bioanalytical challenge, specifically the analysis of individual biological cells, demonstrating similar improvements in performance.

  17. High-efficiency grid-connected photovoltaic module integrated converter system with high-speed communication interfaces for small-scale distribution power generation

    Energy Technology Data Exchange (ETDEWEB)

    Choi, Woo-Young; Lai, Jih-Sheng (Jason) [Future Energy Electronics Center, Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, VA (United States)

    2010-04-15

    This paper presents a high-efficiency grid-connected photovoltaic (PV) module integrated converter (MIC) system with reduced PV current variation. The proposed PV MIC system consists of a high-efficiency step-up DC-DC converter and a single-phase full-bridge DC-AC inverter. An active-clamping flyback converter with a voltage-doubler rectifier is proposed for the step-up DC-DC converter. The proposed step-up DC-DC converter reduces the switching losses by eliminating the reverse-recovery current of the output rectifying diodes. To reduce the PV current variation introduced by the grid-connected inverter, a PV current variation reduction method is also suggested. The suggested PV current variation reduction method reduces the PV current variation without any additional components. Moreover, for centralized power control of distributed PV MIC systems, a PV power control scheme with both a central control level and a local control level is presented. The central PV power control level controls the whole power production by sending out reference power signals to each individual PV MIC system. The proposed step-up DC-DC converter achieves a high-efficiency of 97.5% at 260 W output power to generate the DC-link voltage of 350 V from the PV voltage of 36.1 V. The PV MIC system including the DC-DC converter and the DC-AC inverter achieves a high-efficiency of 95% with the PV current ripple less than 3% variation of the rated PV current. (author)

  18. Inspection of the integrity of surface mounted integrated circuits on a printed circuit board using vision

    OpenAIRE

    Yakoub, Imad

    1991-01-01

    Machine vision technology has permeated many areas of industry, and automated inspection systems are playing increasingly important roles in many production processes. Electronic manufacturing is a good example of the integration of vision based feedback in manufacturing and the assembly of surface mount PCBs is typical of the technology involved. There are opportunities to use machine vision during different stages of the surface mount process. The problem in the inspection of solder joints ...

  19. Integrated circuits based on bilayer MoS₂ transistors.

    Science.gov (United States)

    Wang, Han; Yu, Lili; Lee, Yi-Hsien; Shi, Yumeng; Hsu, Allen; Chin, Matthew L; Li, Lain-Jong; Dubey, Madan; Kong, Jing; Palacios, Tomas

    2012-09-12

    Two-dimensional (2D) materials, such as molybdenum disulfide (MoS(2)), have been shown to exhibit excellent electrical and optical properties. The semiconducting nature of MoS(2) allows it to overcome the shortcomings of zero-bandgap graphene, while still sharing many of graphene's advantages for electronic and optoelectronic applications. Discrete electronic and optoelectronic components, such as field-effect transistors, sensors, and photodetectors made from few-layer MoS(2) show promising performance as potential substitute of Si in conventional electronics and of organic and amorphous Si semiconductors in ubiquitous systems and display applications. An important next step is the fabrication of fully integrated multistage circuits and logic building blocks on MoS(2) to demonstrate its capability for complex digital logic and high-frequency ac applications. This paper demonstrates an inverter, a NAND gate, a static random access memory, and a five-stage ring oscillator based on a direct-coupled transistor logic technology. The circuits comprise between 2 to 12 transistors seamlessly integrated side-by-side on a single sheet of bilayer MoS(2). Both enhancement-mode and depletion-mode transistors were fabricated thanks to the use of gate metals with different work functions.

  20. Integrated circuit amplifiers for multi-electrode intracortical recording.

    Science.gov (United States)

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  1. Mixed signal custom integrated circuit development for physics instrumentation

    Energy Technology Data Exchange (ETDEWEB)

    Britton, C.L. Jr.; Bryan, W.L.; Emery, M.S. [and others

    1998-10-01

    The Monolithic Systems Development Group at the Oak Ridge National Laboratory has been greatly involved in custom mixed-mode integrated circuit development for the PHENIX detector at the Relativistic Heavy Ion collider (RHIC) at Brookhaven National Laboratory and position-sensitive germanium spectrometer front-ends for the Naval Research Laboratory (NRL). This paper will outline the work done for both PHENIX and the Naval Research Laboratory in the area of full-custom, mixed-signal CMOS integrated electronics. This paper presents the architectures chosen for the various PHENIX detectors which include position-sensitive silicon, capacitive pixel, and phototube detectors, and performance results for the subsystems as well as a system description of the NRL germanium strip system and its performance. The performance of the custom preamplifiers, discriminators, analog memories, analog-digital converters, and control circuitry for all systems will be presented.

  2. ON EFFICIENT OPERATIONAL CONCEPT OF FUTURE HIGH-SPEED RAILWAY IN THE CZECH REPUBLIC

    Directory of Open Access Journals (Sweden)

    Michal Drábek

    2016-09-01

    Full Text Available The aim of this paper is to elaborate a layout of the first operational concept of Rapid Services with 1 hour system travel time between Praha and Brno. Two basic methods are used – Integrated Periodic Timetable (periodic rendezvous of all services in IPT-nodes and Operational Concept Economy Approach, as defined below by the author. In this paper, three recent high-speed railway concepts for the future so-called Rapid Services network of the Czech Republic are followed-up. The first one is an operational traffic planning study by Kalcík, Janoš et al. on behalf of Czech Ministry of Transport from 2010. The second one is the high-speed railway promoting book High Speed Rail Even in the Czech Republic by Šlegr et al. from 2012, with likely the most detailed concept of Rapid Services network. The third one is a paper on progress of the official spatial-technical studies for some future Czech high-speed lines by Šulc from 2014. The importance of achievement of 1 hour travel time between the largest agglomerations is briefly presented. The presented methodological approach, although soft and manager-oriented, comprises some firm principles: segmentation of high-speed train offer, so that more expensive rolling stock is not wasted by operation on long conventional line sections, consideration of system travel times for efficient rolling stock circuit, restriction of need for links from high-speed to conventional lines, and utilization of high-speed lines as a "rail highway". This approach is intended to be particularized iteratively, with every application. So, in this paper, first version of Operational Concept Economy Approach is introduced. The key idea is that passengers should be offered such travel times and service intervals (headways and such number of direct services, which are adequate to their potential demand, but as much synergistic effect as possible should be strived to be achieved for every proposed construction (new or

  3. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  4. High speed imaging - An important industrial tool

    Science.gov (United States)

    Moore, Alton; Pinelli, Thomas E.

    1986-01-01

    High-speed photography, which is a rapid sequence of photographs that allow an event to be analyzed through the stoppage of motion or the production of slow-motion effects, is examined. In high-speed photography 16, 35, and 70 mm film and framing rates between 64-12,000 frames per second are utilized to measure such factors as angles, velocities, failure points, and deflections. The use of dual timing lamps in high-speed photography and the difficulties encountered with exposure and programming the camera and event are discussed. The application of video cameras to the recording of high-speed events is described.

  5. Integrated Circuit Design in US High-Energy Physics

    Energy Technology Data Exchange (ETDEWEB)

    Geronimo, G. D. [Brookhaven National Lab. (BNL), Upton, NY (United States); Christian, D. [Fermi National Accelerator Lab. (FNAL), Batavia, IL (United States); Bebek, C. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Garcia-Sciveres, M. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Lippe, H. V. D. [Lawrence Berkeley National Lab. (LBNL), Berkeley, CA (United States); Haller, G. [SLAC National Accelerator Lab., Menlo Park, CA (United States); Grillo, AA [Univ. of California, Santa Cruz, CA (United States); Newcomer, M [Univ. of Pennsylvania, Philadelphia, PA (United States)

    2013-07-10

    This whitepaper summarizes the status, plans, and challenges in the area of integrated circuit design in the United States for future High Energy Physics (HEP) experiments. It has been submitted to CPAD (Coordinating Panel for Advanced Detectors) and the HEP Community Summer Study 2013(Snowmass on the Mississippi) held in Minnesota July 29 to August 6, 2013. A workshop titled: US Workshop on IC Design for High Energy Physics, HEPIC2013 was held May 30 to June 1, 2013 at Lawrence Berkeley National Laboratory (LBNL). A draft of the whitepaper was distributed to the attendees before the workshop, the content was discussed at the meeting, and this document is the resulting final product. The scope of the whitepaper includes the following topics: Needs for IC technologies to enable future experiments in the three HEP frontiers Energy, Cosmic and Intensity Frontiers; Challenges in the different technology and circuit design areas and the related R&D needs; Motivation for using different fabrication technologies; Outlook of future technologies including 2.5D and 3D; Survey of ICs used in current experiments and ICs targeted for approved or proposed experiments; IC design at US institutes and recommendations for collaboration in the future.

  6. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    Science.gov (United States)

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-06

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

  7. Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

    OpenAIRE

    Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

    2017-01-01

    Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate int...

  8. 77 FR 19032 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same Notice of Receipt...

    Science.gov (United States)

    2012-03-29

    ... Certain Semiconductor Integrated Circuit Devices and Products Containing Same, DN 2888; the Commission is... importation of certain semiconductor integrated circuit devices and products containing same. The complaint...] [FR Doc No: 2012-7567] INTERNATIONAL TRADE COMMISSION [DN 2888] Certain Semiconductor Integrated...

  9. Infrared transparent graphene heater for silicon photonic integrated circuits.

    Science.gov (United States)

    Schall, Daniel; Mohsin, Muhammad; Sagade, Abhay A; Otto, Martin; Chmielak, Bartos; Suckow, Stephan; Giesecke, Anna Lena; Neumaier, Daniel; Kurz, Heinrich

    2016-04-18

    Thermo-optical tuning of the refractive index is one of the pivotal operations performed in integrated silicon photonic circuits for thermal stabilization, compensation of fabrication tolerances, and implementation of photonic operations. Currently, heaters based on metal wires provide the temperature control in the silicon waveguide. The strong interaction of metal and light, however, necessitates a certain gap between the heater and the photonic structure to avoid significant transmission loss. Here we present a graphene heater that overcomes this constraint and enables an energy efficient tuning of the refractive index. We achieve a tuning power as low as 22 mW per free spectral range and fast response time of 3 µs, outperforming metal based waveguide heaters. Simulations support the experimental results and suggest that for graphene heaters the spacing to the silicon can be further reduced yielding the best possible energy efficiency and operation speed.

  10. Photonic integrated circuits unveil crisis-induced intermittency.

    Science.gov (United States)

    Karsaklian Dal Bosco, Andreas; Akizawa, Yasuhiro; Kanno, Kazutaka; Uchida, Atsushi; Harayama, Takahisa; Yoshimura, Kazuyuki

    2016-09-19

    We experimentally investigate an intermittent route to chaos in a photonic integrated circuit consisting of a semiconductor laser with time-delayed optical feedback from a short external cavity. The transition from a period-doubling dynamics to a fully-developed chaos reveals a stage intermittently exhibiting these two dynamics. We unveil the bifurcation mechanism underlying this route to chaos by using the Lang-Kobayashi model and demonstrate that the process is based on a phenomenon of attractor expansion initiated by a particular distribution of the local Lyapunov exponents. We emphasize on the crucial importance of the distribution of the steady-state solutions introduced by the time-delayed feedback on the existence of this intermittent dynamics.

  11. Uncertain behaviours of integrated circuits improve computational performance.

    Science.gov (United States)

    Yoshimura, Chihiro; Yamaoka, Masanao; Hayashi, Masato; Okuyama, Takuya; Aoki, Hidetaka; Kawarabayashi, Ken-ichi; Mizuno, Hiroyuki

    2015-11-20

    Improvements to the performance of conventional computers have mainly been achieved through semiconductor scaling; however, scaling is reaching its limitations. Natural phenomena, such as quantum superposition and stochastic resonance, have been introduced into new computing paradigms to improve performance beyond these limitations. Here, we explain that the uncertain behaviours of devices due to semiconductor scaling can improve the performance of computers. We prototyped an integrated circuit by performing a ground-state search of the Ising model. The bit errors of memory cell devices holding the current state of search occur probabilistically by inserting fluctuations into dynamic device characteristics, which will be actualised in the future to the chip. As a result, we observed more improvements in solution accuracy than that without fluctuations. Although the uncertain behaviours of devices had been intended to be eliminated in conventional devices, we demonstrate that uncertain behaviours has become the key to improving computational performance.

  12. Two multichannel integrated circuits for neural recording and signal processing.

    Science.gov (United States)

    Obeid, Iyad; Morizio, James C; Moxon, Karen A; Nicolelis, Miguel A L; Wolf, Patrick D

    2003-02-01

    We have developed, manufactured, and tested two analog CMOS integrated circuit "neurochips" for recording from arrays of densely packed neural electrodes. Device A is a 16-channel buffer consisting of parallel noninverting amplifiers with a gain of 2 V/V. Device B is a 16-channel two-stage analog signal processor with differential amplification and high-pass filtering. It features selectable gains of 250 and 500 V/V as well as reference channel selection. The resulting amplifiers on Device A had a mean gain of 1.99 V/V with an equivalent input noise of 10 microV(rms). Those on Device B had mean gains of 53.4 and 47.4 dB with a high-pass filter pole at 211 Hz and an equivalent input noise of 4.4 microV(rms). Both devices were tested in vivo with electrode arrays implanted in the somatosensory cortex.

  13. Further on integrator circuit analogy for natural convection

    Energy Technology Data Exchange (ETDEWEB)

    Khane, Vaibhav [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States); Usman, Shoaib, E-mail: usmans@mst.ed [Nuclear Engineering, Missouri University of Science and Technology, 225 Fulton Hall, 300W. 13th St., Rolla, MO-65409 (United States)

    2010-03-15

    This research is an extension of the previous work on the development of an integrator (RC) circuit analogy for natural convection. This analogy has been proven experimentally as well as by numerical simulations. Additional Rayleigh-Benard convection numerical simulations were performed to investigate DELTAT (temperature difference between source and sink) dependence of the thermal resistance of a natural convection system. Our results suggest that analogous to voltage dependent resistor (VDR) in electrical engineering, DELTAT dependent thermal resistance is observed in natural convection system. This DELTAT dependent thermal resistance leads to a variable time constant. Moreover, this research also suggests that for a natural convection system, in addition to the thermal capacitance a kinetic energy capacitance also exists. The relative contribution of kinetic energy capacitance depends on Rayleigh number. These results provide significant step forward towards development of a new inexpensive modeling and transient analysis tool for a natural convection system.

  14. Enabling the Internet of Things from integrated circuits to integrated systems

    CERN Document Server

    2017-01-01

    This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardwar...

  15. High-speed imaging in fluids

    NARCIS (Netherlands)

    Versluis, Michel

    2013-01-01

    High-speed imaging is in popular demand for a broad range of experiments in fluids. It allows for a detailed visualization of the event under study by acquiring a series of image frames captured at high temporal and spatial resolution. This review covers high-speed imaging basics, by defining

  16. Holistic design in high-speed optical interconnects

    Science.gov (United States)

    Saeedi, Saman

    Integrated circuit scaling has enabled a huge growth in processing capability, which necessitates a corresponding increase in inter-chip communication bandwidth. As bandwidth requirements for chip-to-chip interconnection scale, deficiencies of electrical channels become more apparent. Optical links present a viable alternative due to their low frequency-dependent loss and higher bandwidth density in the form of wavelength division multiplexing. As integrated photonics and bonding technologies are maturing, commercialization of hybrid-integrated optical links are becoming a reality. Increasing silicon integration leads to better performance in optical links but necessitates a corresponding co-design strategy in both electronics and photonics. In this light, holistic design of high-speed optical links with an in-depth understanding of photonics and state-of-the-art electronics brings their performance to unprecedented levels. This thesis presents developments in high-speed optical links by co-designing and co-integrating the primary elements of an optical link: receiver, transmitter, and clocking. In the first part of this thesis a 3D-integrated CMOS/Silicon-photonic receiver will be presented. The electronic chip features a novel design that employs a low-bandwidth TIA front-end, double-sampling and equalization through dynamic offset modulation. Measured results show -14.9dBm of sensitivity and energy eciency of 170fJ/b at 25Gb/s. The same receiver front-end is also used to implement source-synchronous 4-channel WDM-based parallel optical receiver. Quadrature ILO-based clocking is employed for synchronization and a novel frequency-tracking method that exploits the dynamics of IL in a quadrature ring oscillator to increase the effective locking range. An adaptive body-biasing circuit is designed to maintain the per-bit-energy consumption constant across wide data-rates. The prototype measurements indicate a record-low power consumption of 153fJ/b at 32Gb/s. The

  17. A global standardization trend for high-speed client and line side transceivers

    Science.gov (United States)

    Isono, Hideki

    2015-03-01

    Seeing the recent vast data increase in information industry, IT society will move into the new era of Zettabyte in a few years. Under these circumstances, high-speed and high-capacity optical communication systems have been deployed in the industry. Especially high speed optical transceivers are key devices to realize high-speed systems, and the practical development is accelerated. In order to develop these leading edge products timely, the global standard criteria are strongly required in the industry. Based on these backgrounds, the forum standardization bodies such as OIF PLLWG/ IEEE802.3 are energetically creating the de-fact standards. With regard to 100G/400G standardization activities, IEEE802.3 leads the client side, and OIF PLL-WG leads the line side, and both of them play important roles in the industry. In the previous Photonics West conferences, the activities of these standardization bodies till 2013 were reported. In 2014, the discussions of 400G client side transceiver projects have made some progress in IEEE802.3, whose baseline technologies are about to be fixed. Also 100G transceiver projects for metro applications in the line side, whose target profile is CFP2 form factor, have been discussed in OIF PLL-WG. In this paper, these high-end standardization topics are introduced and the future products direction is also discussed from the technical point of view. In order to realize these small form factor and cost effective transceivers, the device integration technologies, the low power device/electrical circuit technologies, and the development of high speed electrical interface such as 25G/50G are key factors.

  18. High-speed photodiodes in standard CMOS technology

    NARCIS (Netherlands)

    Radovanovic, S.

    2004-01-01

    This thesis describes high-speed photodiodes in standard CMOS technology which allow monolithic integration of optical receivers for short-haul communication. The electronics for (multiple users) long-haul communication is very expensive (InP, GaAs), but the usage is justified by the large number of

  19. SDN architecture for optical packet and circuit integrated networks

    Science.gov (United States)

    Furukawa, Hideaki; Miyazawa, Takaya

    2016-02-01

    We have been developing an optical packet and circuit integrated (OPCI) network, which realizes dynamic optical path, high-density packet multiplexing, and flexible wavelength resource allocation. In the OPCI networks, a best-effort service and a QoS-guaranteed service are provided by employing optical packet switching (OPS) and optical circuit switching (OCS) respectively, and users can select these services. Different wavelength resources are assigned for OPS and OCS links, and the amount of their wavelength resources are dynamically changed in accordance with the service usage conditions. To apply OPCI networks into wide-area (core/metro) networks, we have developed an OPCI node with a distributed control mechanism. Moreover, our OPCI node works with a centralized control mechanism as well as a distributed one. It is therefore possible to realize SDN-based OPCI networks, where resource requests and a centralized configuration are carried out. In this paper, we show our SDN architecture for an OPS system that configures mapping tables between IP addresses and optical packet addresses and switching tables according to the requests from multiple users via a web interface. While OpenFlow-based centralized control protocol is coming into widespread use especially for single-administrative, small-area (LAN/data-center) networks. Here, we also show an interworking mechanism between OpenFlow-based networks (OFNs) and the OPCI network for constructing a wide-area network, and a control method of wavelength resource selection to automatically transfer diversified flows from OFNs to the OPCI network.

  20. 77 FR 60721 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of...

    Science.gov (United States)

    2012-10-04

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Notice of... importation, and the sale within the United States after importation of certain semiconductor integrated circuit devices and products containing same by reason of infringement of certain claims of U.S. Patent...

  1. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  2. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Science.gov (United States)

    2012-05-01

    ... COMMISSION Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of... devices and products containing same by reason of infringement of certain claims of U.S. Patent No. 7,225... semiconductor integrated circuit devices and products containing same that infringe one or more of claims 1, 2...

  3. Millimeter-Wave Integrated Circuit Design for Wireless and Radar Applications

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Krozer, Viktor; Vidkjær, Jens

    2006-01-01

    This paper describes a quadrature voltage-controlled oscillator (QVCO), frequency doubler, and sub-harmonic mixer (SHM) for a millimeter-wave (mm-wave) front-end implemented in a high-speed InP DHBT technology. The QVCO exhibits large tuning range from 38 to 47.8 GHz with an output power around -15...... from 40-50 GHz. To the authors knowledge the QVCO, frequency doubler, and SHM presents the first mm-wave implementations of these circuits in InP DHBT technology....

  4. Design structure for in-system redundant array repair in integrated circuits

    Science.gov (United States)

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  5. CMOS Image Sensors for High Speed Applications.

    Science.gov (United States)

    El-Desouki, Munir; Deen, M Jamal; Fang, Qiyin; Liu, Louis; Tse, Frances; Armstrong, David

    2009-01-01

    Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD) imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4∼5 μm) due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps).

  6. CMOS Image Sensors for High Speed Applications

    Directory of Open Access Journals (Sweden)

    M. Jamal Deen

    2009-01-01

    Full Text Available Recent advances in deep submicron CMOS technologies and improved pixel designs have enabled CMOS-based imagers to surpass charge-coupled devices (CCD imaging technology for mainstream applications. The parallel outputs that CMOS imagers can offer, in addition to complete camera-on-a-chip solutions due to being fabricated in standard CMOS technologies, result in compelling advantages in speed and system throughput. Since there is a practical limit on the minimum pixel size (4~5 μm due to limitations in the optics, CMOS technology scaling can allow for an increased number of transistors to be integrated into the pixel to improve both detection and signal processing. Such smart pixels truly show the potential of CMOS technology for imaging applications allowing CMOS imagers to achieve the image quality and global shuttering performance necessary to meet the demands of ultrahigh-speed applications. In this paper, a review of CMOS-based high-speed imager design is presented and the various implementations that target ultrahigh-speed imaging are described. This work also discusses the design, layout and simulation results of an ultrahigh acquisition rate CMOS active-pixel sensor imager that can take 8 frames at a rate of more than a billion frames per second (fps.

  7. Pulse Propagation in High-Speed Digital Circuits

    Science.gov (United States)

    1989-05-08

    tk) 2V2 (d,tk) + V2h(d,tk) I(d,tk) 2Vn +(dtk) + Vnh(d,tk) x b Figure 3.3 Element stamp associated with the Thevenin companion model of Figure 3.2. This...3.7) to Eq. (3.8) yields the means of com- puting e-r(w)d: e-r(o)d = E(o)e-A(w)dE(o))-t Since C (W) Td = [e-r(w)d]T , it need not be considered further

  8. High speed curving performance of rail vehicles

    Science.gov (United States)

    2015-03-23

    On March 13, 2013, the Federal Railroad Administration (FRA) published a final rule titled Vehicle/Track Interaction Safety Standards; High-Speed and High Cant Deficiency Operations which amended the Track Safety Standards (49 CFR Part213) and ...

  9. Jane's high-speed marine transportation

    National Research Council Canada - National Science Library

    Phillips, S.J

    1998-01-01

    The purpose of this book is to provide a comprehensive reference yearbook covering the design, build and operation of high-speed marine transportation, worldwide, an annually updated reference book...

  10. Mathematical model of an integrated circuit cooling through cylindrical rods

    Directory of Open Access Journals (Sweden)

    Beltrán-Prieto Luis Antonio

    2017-01-01

    Full Text Available One of the main challenges in integrated circuits development is to propose alternatives to handle the extreme heat generated by high frequency of electrons moving in a reduced space that cause overheating and reduce the lifespan of the device. The use of cooling fins offers an alternative to enhance the heat transfer using combined a conduction-convection systems. Mathematical model of such process is important for parametric design and also to gain information about temperature distribution along the surface of the transistor. In this paper, we aim to obtain the equations for heat transfer along the chip and the fin by performing energy balance and heat transfer by conduction from the chip to the rod, followed by dissipation to the surrounding by convection. Newton's law of cooling and Fourier law were used to obtain the equations that describe the profile temperature in the rod and the surface of the chip. Ordinary differential equations were obtained and the respective analytical solutions were derived after consideration of boundary conditions. The temperature along the rod decreased considerably from the initial temperature (in contatct with the chip surface. This indicates the benefit of using a cilindrical rod to distribute the heat generated in the chip.

  11. Microcoil Spring Interconnects for Ceramic Grid Array Integrated Circuits

    Science.gov (United States)

    Strickland, S. M.; Hester, J. D.; Gowan, A. K.; Montgomery, R. K.; Geist, D. L.; Blanche, J. F.; McGuire, G. D.; Nash, T. S.

    2011-01-01

    As integrated circuit miniaturization trends continue, they drive the need for smaller higher input/output (I/O) packages. Hermetically sealed ceramic area array parts are the package of choice by the space community for high reliability space flight electronic hardware. Unfortunately, the coefficient of thermal expansion mismatch between the ceramic area array package and the epoxy glass printed wiring board limits the life of the interconnecting solder joint. This work presents the results of an investigation by Marshall Space Flight Center into a method to increase the life of this second level interconnection by the use of compliant microcoil springs. The design of the spring and its attachment process are presented along with thermal cycling results of microcoil springs (MCS) compared with state-of-the-art ball and column interconnections. Vibration testing has been conducted on MCS and high lead column parts. Radio frequency simulation and measurements have been made and the MCS has been modeled and a stress analysis performed. Thermal cycling and vibration testing have shown MCS interconnects to be significantly more reliable than solder columns. Also, MCS interconnects are less prone to handling damage than solder columns. Future work that includes shock testing, incorporation into a digital signal processor board, and process evaluation of expansion from a 400 I/O device to a device with over 1,100 I/O is identified.

  12. Graphene-on-silicon hybrid plasmonic-photonic integrated circuits.

    Science.gov (United States)

    Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

    2017-06-16

    Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

  13. An integrated modelling framework for neural circuits with multiple neuromodulators.

    Science.gov (United States)

    Joshi, Alok; Youssofzadeh, Vahab; Vemana, Vinith; McGinnity, T M; Prasad, Girijesh; Wong-Lin, KongFatt

    2017-01-01

    Neuromodulators are endogenous neurochemicals that regulate biophysical and biochemical processes, which control brain function and behaviour, and are often the targets of neuropharmacological drugs. Neuromodulator effects are generally complex partly owing to the involvement of broad innervation, co-release of neuromodulators, complex intra- and extrasynaptic mechanism, existence of multiple receptor subtypes and high interconnectivity within the brain. In this work, we propose an efficient yet sufficiently realistic computational neural modelling framework to study some of these complex behaviours. Specifically, we propose a novel dynamical neural circuit model that integrates the effective neuromodulator-induced currents based on various experimental data (e.g. electrophysiology, neuropharmacology and voltammetry). The model can incorporate multiple interacting brain regions, including neuromodulator sources, simulate efficiently and easily extendable to large-scale brain models, e.g. for neuroimaging purposes. As an example, we model a network of mutually interacting neural populations in the lateral hypothalamus, dorsal raphe nucleus and locus coeruleus, which are major sources of neuromodulator orexin/hypocretin, serotonin and norepinephrine/noradrenaline, respectively, and which play significant roles in regulating many physiological functions. We demonstrate that such a model can provide predictions of systemic drug effects of the popular antidepressants (e.g. reuptake inhibitors), neuromodulator antagonists or their combinations. Finally, we developed user-friendly graphical user interface software for model simulation and visualization for both fundamental sciences and pharmacological studies. © 2017 The Authors.

  14. Experimental demonstration of interferometric imaging using photonic integrated circuits.

    Science.gov (United States)

    Su, Tiehui; Scott, Ryan P; Ogden, Chad; Thurman, Samuel T; Kendrick, Richard L; Duncan, Alan; Yu, Runxiang; Yoo, S J B

    2017-05-29

    This paper reports design, fabrication, and demonstration of a silica photonic integrated circuit (PIC) capable of conducting interferometric imaging with multiple baselines around λ = 1550 nm. The PIC consists of four sets of five waveguides (total of twenty waveguides), each leading to a three-band spectrometer (total of sixty waveguides), after which a tunable Mach-Zehnder interferometer (MZI) constructs interferograms from each pair of the waveguides. A total of thirty sets of interferograms (ten pairs of three spectral bands) is collected by the detector array at the output of the PIC. The optical path difference (OPD) of each interferometer baseline is kept to within 1 µm to maximize the visibility of the interference measurement. We constructed an experiment to utilize the two baselines for complex visibility measurement on a point source and a variable width slit. We used the point source to demonstrate near unity value of the PIC instrumental visibility, and used the variable slit to demonstrate visibility measurement for a simple extended object. The experimental result demonstrates the visibility of baseline 5 and 20 mm for a slit width of 0 to 500 µm in good agreement with theoretical predictions.

  15. Modularized construction of general integrated circuits on individual carbon nanotubes.

    Science.gov (United States)

    Pei, Tian; Zhang, Panpan; Zhang, Zhiyong; Qiu, Chenguang; Liang, Shibo; Yang, Yingjun; Wang, Sheng; Peng, Lian-Mao

    2014-06-11

    While constructing general integrated circuits (ICs) with field-effect transistors (FETs) built on individual CNTs is among few viable ways to build ICs with small dimension and high performance that can be compared with that of state-of-the-art Si based ICs, this has not been demonstrated owing to the absence of valid and well-tolerant fabrication method. Here we demonstrate a modularized method for constructing general ICs on individual CNTs with different electric properties. A pass-transistor-logic style 8-transistor (8-T) unit is built, demonstrated as a multifunctional function generator with good tolerance to inhomogeneity in the CNTs used and used as a building block for constructing general ICs. As an example, an 8-bits BUS system that is widely used to transfer data between different systems in a computer is constructed. This is the most complicated IC fabricated on individual CNTs to date, containing 46 FETs built on six individual semiconducting CNTs. The 8-T unit provides a good basis for constructing complex ICs to explore the potential and limits of CNT ICs given the current imperfection in available CNT materials and may also be developed into a universal and efficient way for constructing general ICs on ideal CNT materials in the future.

  16. Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

    Science.gov (United States)

    Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

    2014-05-01

    This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

  17. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  18. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    Science.gov (United States)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  19. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...

  20. High-speed analog-to-digital conversion

    CERN Document Server

    Demler, Michael J

    1991-01-01

    This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, ""

  1. Silicon-based photonic integrated circuit for label-free biosensing

    OpenAIRE

    Samusenko, Alina

    2016-01-01

    Silicon-based Photonic Integrated Circuit (PIC) is a device that integrates several optical components using the mature semiconductor technology platform, developed through years for the needs of electronic integrated circuits. In recent years, silicon PICs have been demonstrated as a powerful platform for biosensing systems - devices which play an omnipresent role in such essential life aspects as health care, environmental monitoring, food safety, etc. The growing importance of silicon phot...

  2. Study of sensitivity and noise in the piezoelectric self-sensing and self-actuating cantilever with an integrated Wheatstone bridge circuit.

    Science.gov (United States)

    Shin, ChaeHo; Jeon, InSu; Khim, Zheong G; Hong, J W; Nam, HyoJin

    2010-03-01

    A detection method using a self-sensing cantilever is more desirable than other detection methods (optical fiber and laser beam bounce detection) that are bulky and require alignment. The advantage of the self-sensing cantilever is its simplicity, particularly its simple structure. It can be used for the construction of an atomic force microscopy system with a vacuum, fluids, and a low temperature chamber. Additionally, the self-actuating cantilever can be used for a high speed scanning system because the bandwidth is larger than the bulk scanner. Frequently, ZnO film has been used as an actuator in a self-actuating cantilever. In this paper, we studied the characteristics of the self-sensing and self-actuating cantilever with an integrated Wheatstone bridge circuit substituting the ZnO film with a lead zirconate titanate (PZT) film as the actuator. We can reduce the leakage current (to less than 10(-4) A/cm(2)) in the PZT cantilever and improve sensor sensitivity through a reduction of noise level from the external sensor circuit using the Wheatstone bridge circuit embedded into the cantilever. The self-sensing and actuating cantilever with an integrated Wheatstone bridge circuit was compared with a commercial self-sensing cantilever or self-sensing and actuating cantilever without an integrated Wheatstone bridge circuit. The measurement results have shown that sensing the signal to noise level and the minimum detectable deflection improved to 4.78 mV and 1.18 nm, respectively. We believe that this cantilever allows for easier system integration and miniaturization, provides better controllability and higher scan speeds, and offers the potential for full automation.

  3. Laser Integration on Silicon Photonic Circuits Through Transfer Printing

    Science.gov (United States)

    2017-03-10

    for small- and medium-sized enterprises (SMEs) and universities , through multiproject wafer services such as Europractice and IME. The AIM...photonic circuits through transfer printing Grant number: FA9550-15-1-0460 PI: Gunther Roelkens Photonics Research Group, Ghent University -imec Period of...Circuit CMOS Complementary Metal Oxide Semiconductor SME small- and medium-sized enterprises DFB distributed feedback laser DISTRIBUTION A. Approved for public release: distribution unlimited.

  4. High speed rail : challenges for the high speed rail project in Norway

    OpenAIRE

    Ringstad, Vidar

    2012-01-01

    This Master Thesis has focus on parts of the public transport system in Norway. The main topic in this thesis is: What variables must be calculated for the decision concerning the construction and implementation of the Norwegian High Speed Rail project, and how are the variables calculated? High Speed Rail does not have a single standard definition. High Speed Rail definition, given in the European Union definition, Directive 96/48 is suitable for many different systems of rolling stock...

  5. Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

    Science.gov (United States)

    Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  6. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Science.gov (United States)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  7. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Directory of Open Access Journals (Sweden)

    Heck Martijn J.R.

    2016-06-01

    Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  8. Scientific Visualization in High Speed Network Environments

    Science.gov (United States)

    Vaziri, Arsi; Kutler, Paul (Technical Monitor)

    1997-01-01

    In several cases, new visualization techniques have vastly increased the researcher's ability to analyze and comprehend data. Similarly, the role of networks in providing an efficient supercomputing environment have become more critical and continue to grow at a faster rate than the increase in the processing capabilities of supercomputers. A close relationship between scientific visualization and high-speed networks in providing an important link to support efficient supercomputing is identified. The two technologies are driven by the increasing complexities and volume of supercomputer data. The interaction of scientific visualization and high-speed networks in a Computational Fluid Dynamics simulation/visualization environment are given. Current capabilities supported by high speed networks, supercomputers, and high-performance graphics workstations at the Numerical Aerodynamic Simulation Facility (NAS) at NASA Ames Research Center are described. Applied research in providing a supercomputer visualization environment to support future computational requirements are summarized.

  9. High Speed Digital Camera Technology Review

    Science.gov (United States)

    Clements, Sandra D.

    2009-01-01

    A High Speed Digital Camera Technology Review (HSD Review) is being conducted to evaluate the state-of-the-shelf in this rapidly progressing industry. Five HSD cameras supplied by four camera manufacturers participated in a Field Test during the Space Shuttle Discovery STS-128 launch. Each camera was also subjected to Bench Tests in the ASRC Imaging Development Laboratory. Evaluation of the data from the Field and Bench Tests is underway. Representatives from the imaging communities at NASA / KSC and the Optical Systems Group are participating as reviewers. A High Speed Digital Video Camera Draft Specification was updated to address Shuttle engineering imagery requirements based on findings from this HSD Review. This draft specification will serve as the template for a High Speed Digital Video Camera Specification to be developed for the wider OSG imaging community under OSG Task OS-33.

  10. Aluminum heat sink enables power transistors to be mounted integrally with printed circuit board

    Science.gov (United States)

    Seaward, R. C.

    1967-01-01

    Power transistor is provided with an integral flat plate aluminum heat sink which mounts directly on a printed circuit board containing associated circuitry. Standoff spacers are used to attach the heat sink to the printed circuit board containing the remainder of the circuitry.

  11. A new monolithic integrated circuit for multiwire proportional chamber (MWPC) read-out system

    CERN Document Server

    Bareyre, P; Borel, J; Borgeaud, P; Brisson, J C; Merckel, G; Meunier, P; Ollivier, B; Poinsignon, J; Prunier, J

    1976-01-01

    A new monolithic 8-channel PMOS integrated circuit has been developed for an experiment to be carried out on the CERN 300 GeV accelerator. The circuit, read-out electronics and tests performed on 12 large MWPC (total of 48000 channels) are described and the results are presented. (3 refs).

  12. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  13. A Novel Analog Integrated Circuit Design Course Covering Design, Layout, and Resulting Chip Measurement

    Science.gov (United States)

    Lin, Wei-Liang; Cheng, Wang-Chuan; Wu, Chen-Hao; Wu, Hai-Ming; Wu, Chang-Yu; Ho, Kuan-Hsuan; Chan, Chueh-An

    2010-01-01

    This work describes a novel, first-year graduate-level analog integrated circuit (IC) design course. The course teaches students analog circuit design; an external manufacturer then produces their designs in three different silicon chips. The students, working in pairs, then test these chips to verify their success. All work is completed within…

  14. High Speed Wireless Signal Generation and Demodulation

    DEFF Research Database (Denmark)

    Caballero Jambrina, Antonio; Sambaraju, Rakesh; Zibar, Darko

    We present the experimental demonstration of high speed wireless generation, up to 40 Gb/s, in the 75-110 GHz wireless band. All-optical OFDM and photonic up-conversion are used for generation and single side-band modulation with digital coherent detection for demodulation.......We present the experimental demonstration of high speed wireless generation, up to 40 Gb/s, in the 75-110 GHz wireless band. All-optical OFDM and photonic up-conversion are used for generation and single side-band modulation with digital coherent detection for demodulation....

  15. Reflection Reduction on DDR3 High-Speed Bus by Improved PSO

    Science.gov (United States)

    Li, Huiyong; Jiang, Hongxu; Li, Bo; Duan, Miyi

    2014-01-01

    The signal integrity of the circuit, as one of the important design issues in high-speed digital system, is usually seriously affected by the signal reflection due to impedance mismatch in the DDR3 bus. In this paper, a novel optimization method is proposed to optimize impedance mismatch and reduce the signal refection. Specifically, by applying the via parasitic, an equivalent model of DDR3 high-speed signal transmission, which bases on the match between the on-die-termination (ODT) value of DDR3 and the characteristic impedance of the transmission line, is established. Additionally, an improved particle swarm optimization algorithm with adaptive perturbation is presented to solve the impedance mismatch problem (IPSO-IMp) based on the above model. The algorithm dynamically judges particles' state and introduces perturbation strategy for local aggregation, from which the local optimum is avoided and the ability of optimization-searching is activated. IPSO-IMp achieves higher accuracy than the standard algorithm, and the speed increases nearly 33% as well. Finally, the simulation results verify that the solution obviously decreases the signal reflection, with the signal transmission quality increasing by 1.3 dB compared with the existing method. PMID:24778582

  16. High Speed Link Radiated Emission Reduction

    Science.gov (United States)

    Bisognin, P.; Pelissou, P.; Cissou, R.; Giniaux, M.; Vargas, O.

    2016-05-01

    To control the radiated emission of high-speed link and associated unit, the current approach is to implement overall harness shielding on cables bundles. This method is very efficient in the HF/ VHF (high frequency/ very high frequency) and UHF (ultra-high frequency) ranges when the overall harness shielding is properly bonded on EMC back-shell. Unfortunately, with the increasing frequency, the associated half wavelength matches with the size of Sub-D connector that is the case for the L band. Therefore, the unit connectors become the main source of interference emission. For the L-band and S-band, the current technology of EMC back-shell leaves thin aperture matched with the L band half wavelength and therefore, the shielding effectiveness is drastically reduced. In addition, overall harness shielding means significant increases of the harness mass.Airbus D&S Toulouse and Elancourt investigated a new solution to avoid the need of overall harness shielding. The objective is to procure EM (Electro-Magnetic) clean unit connected to cables bundles free of any overall harness shielding. The proposed solution is to implement EMC common mode filtering on signal interfaces directly on unit PCB as close as possible the unit connector.Airbus D&S Elancourt designed and manufactured eight mock-ups of LVDS (Low Voltage Differential Signaling) interface PCBs' with different solutions of filtering. After verification of the signal integrity, three mock-ups were retained (RC filter and two common mode choke coil) in addition to the reference one (without EMC filter).Airbus D&S Toulouse manufactured associated LVDS cable bundles and integrated the RX (Receiver) and TX (Transmitter) LVDS boards in shielded boxes.Then Airbus D&S performed radiated emission measurement of the LVDS links subassemblies (e.g. RX and TX boxes linked by LVDS cables) according to the standard test method. This paper presents the different tested solutions and main conclusions on the feasibility of such

  17. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  18. An Integrated-Circuit Temperature Sensor for Calorimetry and Differential Temperature Measurement.

    Science.gov (United States)

    Muyskens, Mark A.

    1997-01-01

    Describes the application of an integrated-circuit (IC) chip which provides an easy-to-use, inexpensive, rugged, computer-interfaceable temperature sensor for calorimetry and differential temperature measurement. Discusses its design and advantages. (JRH)

  19. Waveguide Phase Modulator for Integrated Planar Lightwave Circuits in KTP Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This SBIR Phase II effort proposes the development and integration of a Planar Lightwave Circuit (PLC) into an all fiber-based seed laser system used in high...

  20. Aerodynamic design on high-speed trains

    Science.gov (United States)

    Ding, San-San; Li, Qiang; Tian, Ai-Qin; Du, Jian; Liu, Jia-Li

    2016-04-01

    Compared with the traditional train, the operational speed of the high-speed train has largely improved, and the dynamic environment of the train has changed from one of mechanical domination to one of aerodynamic domination. The aerodynamic problem has become the key technological challenge of high-speed trains and significantly affects the economy, environment, safety, and comfort. In this paper, the relationships among the aerodynamic design principle, aerodynamic performance indexes, and design variables are first studied, and the research methods of train aerodynamics are proposed, including numerical simulation, a reduced-scale test, and a full-scale test. Technological schemes of train aerodynamics involve the optimization design of the streamlined head and the smooth design of the body surface. Optimization design of the streamlined head includes conception design, project design, numerical simulation, and a reduced-scale test. Smooth design of the body surface is mainly used for the key parts, such as electric-current collecting system, wheel truck compartment, and windshield. The aerodynamic design method established in this paper has been successfully applied to various high-speed trains (CRH380A, CRH380AM, CRH6, CRH2G, and the Standard electric multiple unit (EMU)) that have met expected design objectives. The research results can provide an effective guideline for the aerodynamic design of high-speed trains.

  1. High-Speed Rail & Air Transport Competition

    NARCIS (Netherlands)

    Adler, Nicole; Nash, Chris; Pels, Eric

    2008-01-01

    This paper develops a methodology to assess transport infrastructure investments and their effects on a Nash equilibria taking into account competition between multiple privatized transport operator types. The operators, including high-speed rail, hub and spoke legacy airlines and low cost carriers,

  2. High-speed Rail & air transport competition

    NARCIS (Netherlands)

    Adler, N; Nash, C.; Pels, E.

    2010-01-01

    This research develops a methodology to assess infrastructure investments and their effects on transport equilibria taking into account competition between multiple privatized transport operator types. The operators, including high-speed rail, hub-and-spoke legacy airlines and regional low-cost

  3. Brandaris ultra high-speed imaging facility

    NARCIS (Netherlands)

    Lajoinie, Guillaume; de Jong, Nico; Versluis, Michel; Tsuji, K.

    2017-01-01

    High-speed imaging is in popular demand for a broad range of scientific applications, including fluid physics, and bubble and droplet dynamics. It allows for a detailed visualization of the event under study by acquiring a series of images captured at high temporal and spatial resolution. The

  4. Crew Rostering for the High Speed Train

    NARCIS (Netherlands)

    R.M. Lentink (Ramon); M.A. Odijk; E. van Rijn

    2002-01-01

    textabstractAt the time of writing we entered the final stage of implementing the crew rostering system Harmony CDR to facilitate the planning of catering crews on board of the Thalys, the High Speed Train connecting Paris, Cologne, Brussels, Amsterdam, and Geneva. Harmony CDR optimally supports the

  5. Localized In Situ Cladding Annealing for Post Fabrication Trimming of Silicon Photonic Integrated Circuits

    Science.gov (United States)

    2016-03-21

    In-Situ Cladding Annealing for Post-Fabrication Trimming of Silicon Photonic Integrated Circuits Steven Spector1, Jeffrey M. Knecht, and Paul W...calibration process rather than adjusting it continuously by applying power to a heater during operation of the circuit . When compared to other methods...is especially well suited to the low-cost integration of large numbers of optical components. One great challenge to fully realizing this potential

  6. Integrated-Circuit Controller For Brushless dc Motor

    Science.gov (United States)

    Le, Dong Tuan

    1994-01-01

    Generic circuit performs commutation-logic and power-switching functions for control of brushless dc motor. Controller includes commutation-logic and associated control circuitry, power supply, and inverters containing power transistors. Major advantages of controller are size, weight, and power consumption can be made less than other brushless-dc-motor controllers.

  7. Development of a high-speed digital signal process system for bunch-by-bunch feedback systems

    Directory of Open Access Journals (Sweden)

    Makoto Tobiyama

    2000-01-01

    Full Text Available High-speed digital filter systems for bunch-by-bunch feedback systems have been developed at KEK. A two-tap finite impulse response filter with simple hardware realizes the functions of a 90° phase shift, suppression of the static component and digital delay of up to a few hundred turns for the KEKB rings. Difficulties in the circuit board, such as the trimming of the timing skews or the problem of long-term reliability, have been solved using custom GaAs large-scale integrated circuits which demultiplex and multiplex fast parallel-digital data coming from the analog-to-digital converter and going to the digital-to-analog converter. Two major applications of the filter board, the bunch current monitor and the bunch oscillation recorder with 20 MB memories for transient-domain analysis of the instabilities, are also described.

  8. Note: An improved low-frequency correction technique for piezoelectric force sensors in high-speed nanopositioning systems

    Science.gov (United States)

    Yong, Yuen K.; Fleming, Andrew J.

    2017-04-01

    Piezoelectric force and position sensors provide high sensitivity but are limited at low frequencies due to their high-pass response which complicates the direct application of integral control. To overcome this issue, an additional sensor or low-frequency correction method is typically employed. However, these approaches introduce an additional first-order response that must be higher than the high-pass response of the piezo and interface electronics. This article describes a simplified method for low-frequency correction that uses the piezoelectric sensor as an electrical component in a filter circuit. The resulting response is first-order, rather than second-order, with a cut-off frequency equal to that of a buffer circuit with the same input resistance. The proposed method is demonstrated to allow simultaneous damping and tracking control of a high-speed vertical nanopositioning stage.

  9. V-band low-noise integrated circuit receiver. [for space communication systems

    Science.gov (United States)

    Chang, K.; Louie, K.; Grote, A. J.; Tahim, R. S.; Mlinar, M. J.; Hayashibara, G. M.; Sun, C.

    1983-01-01

    A compact low-noise V-band integrated circuit receiver has been developed for space communication systems. The receiver accepts an RF input of 60-63 GHz and generates an IF output of 3-6 GHz. A Gunn oscillator at 57 GHz is phaselocked to a low-frequency reference source to achieve high stability and low FM noise. The receiver has an overall single sideband noise figure of less than 10.5 dB and an RF to IF gain of 40 dB over a 3-GHz RF bandwidth. All RF circuits are fabricated in integrated circuits on a Duroid substrate.

  10. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

    Directory of Open Access Journals (Sweden)

    Yuharu Shinki

    2017-08-01

    Full Text Available This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

  11. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Lun Li

    2006-04-01

    Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

  12. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  13. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Science.gov (United States)

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  14. Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

    Science.gov (United States)

    Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

    2017-01-01

    According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

  15. High-speed velocity measurements on an EFI-system

    Science.gov (United States)

    Prinse, W. C.; van't Hof, P. G.; Cheng, L. K.; Scholtes, J. H. G.

    2007-01-01

    For the development of an Exploding Foil Initiator for Insensitive Munitions applications the following topics are of interest: the electrical circuit, the exploding foil, the velocity of the flyer, the driver explosive, the secondary flyer and the acceptor explosive. Several parameters of the EFI have influences on the velocity of the flyer. To investigate these parameters a Fabry-Perot Velocity Interferometer System (F-PVIS) has been used. The light to and from the flyer is transported by a multimode fibre terminated with a GRIN-lens. By this method the velocity of very tiny objects (0.1 mm), can be measured. The velocity of flyer can be recorded with nanosecond resolution, depending on the Fabry-Perot etalon and the streak camera. With this equipment the influence of the dimensions of the exploding foil and the flyer on the velocity and the acceleration of the flyer are investigated. Also the integrity of the flyer during flight can be analyzed. To characterize the explosive material, to be used as driver explosive in EFI's, the initiation behaviour of the explosive has been investigated by taking pictures of the explosion with a high speed framing and streak camera. From these pictures the initiation distance and the detonation behaviour of the explosive has been analyzed. Normally, the driver explosive initiates the acceptor explosive (booster) by direct contact. This booster explosive is embedded in the main charge of the munitions. The combination of initiator, booster explosive and main charge explosive is called the detonation train. In this research the possibility of initiation of the booster by an intermediate flyer is investigated. This secondary flyer can be made of different materials, like aluminium, steel and polyester with different sizes. With the aid of the F-PVIS the acceleration of the secondary flyer is investigated. This reveals the influence of the thickness and density of the flyer on the acceleration and final velocity. Under certain

  16. Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

    Science.gov (United States)

    Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    2017-09-04

    We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

  17. Gas turbine for high speed trains

    Energy Technology Data Exchange (ETDEWEB)

    Chenard, J.-L. [Turbomeca (France)

    1994-12-31

    This presentation will show how the gas turbine engines can be the right compromise to face the challenges raised by the demand for high speed trains through out the world. From the steam locomotive still in use in China to the TGV or ICE in Europe and Shinkensen in Japan able to run at more than 300 kms/hour, the modes of traction for trains have been greatly improved during the last fifty years. Even more faster trains are under studies for the future with the magnetic levitation system. Three main propulsion system, diesel, electric and gas turbines are actually competing in the high speed train market. They will have to comply with the new environmental regulations, better efficiency and customers` requirements for the developed countries, and with the necessity to use the existing tracks for most of the applications

  18. High-Speed Rail & Air Transport Competition

    OpenAIRE

    Nicole Adler; Chris Nash; Eric Pels

    2008-01-01

    This paper develops a methodology to assess transport infrastructure investments and their effects on a Nash equilibria taking into account competition between multiple privatized transport operator types. The operators, including high-speed rail, hub and spoke legacy airlines and low cost carriers, maximize profit functions via prices, frequency and train/plane sizes, given infrastructure provision and costs and environmental charges. The methodology is subsequently applied to all 27 Europea...

  19. High-speed inline holographic Stokesmeter imaging.

    Science.gov (United States)

    Liu, Xue; Heifetz, Alexander; Tseng, Shih C; Shahriar, M S

    2009-07-01

    We demonstrate a high-speed inline holographic Stokesmeter that consists of two liquid crystal retarders and a spectrally selective holographic grating. Explicit choices of angles of orientation for the components in the inline architecture are identified to yield higher measurement accuracy than the classical architecture. We show polarimetric images of an artificial scene produced by such a Stokesmeter, demonstrating the ability to identify an object not recognized by intensity-only imaging systems.

  20. Radiation-Tolerant High-Speed Camera

    Science.gov (United States)

    2017-03-01

    Radiation -Tolerant High-Speed Camera Esko Mikkola, Andrew Levy, Matt Engelman Alphacore, Inc. Tempe, AZ 85281 Abstract: As part of an... radiation -hardened CMOS image sensor and camera system. Radiation -hardened cameras with frame rates as high as 10 kfps and resolution of 1Mpixel are not...camera solution that is under development with a similar architecture. It also includes a brief description of the radiation -hardened camera that

  1. Stochastic Simulation of Integrated Circuits with Nonlinear Black-Box Components via Augmented Deterministic Equivalents

    Directory of Open Access Journals (Sweden)

    MANFREDI, P.

    2014-11-01

    Full Text Available This paper extends recent literature results concerning the statistical simulation of circuits affected by random electrical parameters by means of the polynomial chaos framework. With respect to previous implementations, based on the generation and simulation of augmented and deterministic circuit equivalents, the modeling is extended to generic and ?black-box? multi-terminal nonlinear subcircuits describing complex devices, like those found in integrated circuits. Moreover, based on recently-published works in this field, a more effective approach to generate the deterministic circuit equivalents is implemented, thus yielding more compact and efficient models for nonlinear components. The approach is fully compatible with commercial (e.g., SPICE-type circuit simulators and is thoroughly validated through the statistical analysis of a realistic interconnect structure with a 16-bit memory chip. The accuracy and the comparison against previous approaches are also carefully established.

  2. Integrated circuits and logic operations based on single-layer MoS2.

    Science.gov (United States)

    Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

    2011-12-27

    Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

  3. Recent high-speed rail vehicles; Kosoku tetsudo sharyo

    Energy Technology Data Exchange (ETDEWEB)

    Sone, S. [The University of Tokyo, Tokyo (Japan); Ishizu, K. [Central Japan Railway Company, Nagoya (Japan); Yoshie, N. [Nishi-Nippon Railroad Co. Ltd., Fukuoka (Japan); Hata, T. [East Japan Railway Co., Tokyo (Japan); Watanabe, T.; Hata, H. [Railway Technical Research Institute, Tokyo (Japan); Brun, D.

    1997-05-01

    This paper describes the latest progress in high speed rail vehicles. It was in 1981 when TGV has inaugurated commercial operation with a speed of 260 km/h. Japan is trying to recover from a setback by putting forward the 300-line vehicle of discrete motive force system, and the 500-line vehicle of complete discrete motive force system featured by reduced weight and a unique power collection system. Central Japan Railway is moving forward a 700-line train aimed at improving comfortability and reducing noise. The 500-line vehicle has vehicular features such as the sharpened head shape, weight reduction and adoption of vibration control, and also such features in electric circuits as centralized main circuit devices and improved monitoring devices. The vehicle`s running test verified stable run at 300 km/h. The Shinkansen vehicle designed by East Japan Railway adopted collective control on the main circuit system, and transferred to a system in which large capacity GTOs are used to drive three-phase induction motors. The Inter City Express has been put into practical use in Germany, with traction vehicles arranged on both ends of a train. Technological characteristics in TGV may be pointed out as avoidance of curves and high gradient. Exchange of electric train technologies is in progress between Japan and Europe. 19 refs., 27 figs., 6 tabs.

  4. Developing course lecture notes on high-speed rail.

    Science.gov (United States)

    2017-07-15

    1. Introduction a. World-wide Development of High-Speed Rail (Japan, Europe, China) b. High-speed Rail in the U.S. 2. High-Speed Rail Infrastructure a. Geometric Design of High Speed Rail i. Horizontal Curve ii. Vertical Curve iii. Grade and Turnout ...

  5. Rapid mapping of digital integrated circuit logic gates via multi-spectral backside imaging

    CERN Document Server

    Adato, Ronen; Zangeneh, Mahmoud; Zhou, Boyou; Joshi, Ajay; Goldberg, Bennett; Unlu, M Selim

    2016-01-01

    Modern semiconductor integrated circuits are increasingly fabricated at untrusted third party foundries. There now exist myriad security threats of malicious tampering at the hardware level and hence a clear and pressing need for new tools that enable rapid, robust and low-cost validation of circuit layouts. Optical backside imaging offers an attractive platform, but its limited resolution and throughput cannot cope with the nanoscale sizes of modern circuitry and the need to image over a large area. We propose and demonstrate a multi-spectral imaging approach to overcome these obstacles by identifying key circuit elements on the basis of their spectral response. This obviates the need to directly image the nanoscale components that define them, thereby relaxing resolution and spatial sampling requirements by 1 and 2 - 4 orders of magnitude respectively. Our results directly address critical security needs in the integrated circuit supply chain and highlight the potential of spectroscopic techniques to addres...

  6. Design of high-speed optical transmission module with an integrated Ti:Er:LiNbO3 waveguide laser/ LiNbO3 electro-optic modulator

    Science.gov (United States)

    Bai, Yang; Chen, Shufen; Fu, Li; Fang, Wei; Lu, Junjun

    2005-01-01

    A high bit rate more than 10Gbit/s optical pulse generation device is the key to achieving high-speed and broadband optical fiber communication network system .Now, we propose a novel high-speed optical transmission module(TM) consisting of a Ti:Er:LiNbO3 waveguide laser and a Mach-Zehnder-type encoding modulator on the same Er-doped substrate. According to the standard of ITU-T, we design the 10Gbit/ s transmission module at 1.53μm on the Z cut Y propagation LiNbO3 slice. A dynamic model and the corresponding numerical code are used to analyze the waveguide laser while the electrooptic effect to design the modulator. Meanwhile, the working principle, key technology, typical characteristic parameters of the module are given. The transmission module has a high extinction ratio and a low driving voltage, which supplies the efficient, miniaturized light source for wavelength division multiplexing(WDM) system. In additional, the relation of the laser gain with the cavity parameter, as well as the relation of the bandwidth of the electrooptic modulator with some key factors are discussed .The designed module structure is simulated by BPM software and HFSS software.

  7. HBT and Schottky diode table-based nonlinear models for microwave integrated circuits design

    OpenAIRE

    Rodriguez Testera, Alejandro

    2012-01-01

    Accurate active device nonlinear models are key elements in the design of Microwave Integrated Circuits (MICs) with Circuit Aided Design (CAD) tools. There is a large diversity of nonlinear models proposals, each one with their own formulation and characteristics. The most popular ones are empirical, in the sense that model parameters are extracted from electrical measurements, and they could be classified in analytical/compact and black-box (both, table-based and behavioral). Analytical ...

  8. Analog parallel processor hardware for high speed pattern recognition

    Science.gov (United States)

    Daud, T.; Tawel, R.; Langenbacher, H.; Eberhardt, S. P.; Thakoor, A. P.

    1990-01-01

    A VLSI-based analog processor for fully parallel, associative, high-speed pattern matching is reported. The processor consists of two main components: an analog memory matrix for storage of a library of patterns, and a winner-take-all (WTA) circuit for selection of the stored pattern that best matches an input pattern. An inner product is generated between the input vector and each of the stored memories. The resulting values are applied to a WTA network for determination of the closest match. Patterns with up to 22 percent overlap are successfully classified with a WTA settling time of less than 10 microsec. Applications such as star pattern recognition and mineral classification with bounded overlap patterns have been successfully demonstrated. This architecture has a potential for an overall pattern matching speed in excess of 10 exp 9 bits per second for a large memory.

  9. High-Speed, Three Dimensional Object Composition Mapping Technology

    Energy Technology Data Exchange (ETDEWEB)

    Ishikawa, M Y

    2001-02-14

    This document overviews an entirely new approach to determining the composition--the chemical-elemental, isotopic and molecular make-up--of complex, highly structured objects, moreover with microscopic spatial resolution in all 3 dimensions. The front cover depicts the new type of pulsed laser system at the heart of this novel technology under adjustment by Alexis Wynne, and schematically indicates two of its early uses: swiftly analyzing the 3-D composition governed structure of a transistor circuit with both optical and mass-spectrometric detectors, and of fossilized dinosaur and turtle bones high-speed probed by optical detection means. Studying the composition-cued 3-D micro-structures of advanced composite materials and the microscopic scale composition-texture of biological tissues are two near-term examples of the rich spectrum of novel applications enabled by this field-opening analytic tool-set.

  10. Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

    Science.gov (United States)

    Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

    2012-01-01

    Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

  11. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  12. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

    Science.gov (United States)

    Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

    2008-07-24

    The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

  13. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  14. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  15. High-speed X-ray imaging pixel array detector for synchrotron bunch isolation

    Energy Technology Data Exchange (ETDEWEB)

    Philipp, Hugh T., E-mail: htp2@cornell.edu; Tate, Mark W.; Purohit, Prafull; Shanks, Katherine S.; Weiss, Joel T. [Cornell University, Ithaca, NY 14853 (United States); Gruner, Sol M. [Cornell University, Ithaca, NY 14853 (United States); Cornell University, Ithaca, NY 14853 (United States)

    2016-01-28

    A high-speed pixel array detector for time-resolved X-ray imaging at synchrotrons has been developed. The ability to isolate single synchrotron bunches makes it ideal for time-resolved dynamical studies. A wide-dynamic-range imaging X-ray detector designed for recording successive frames at rates up to 10 MHz is described. X-ray imaging with frame rates of up to 6.5 MHz have been experimentally verified. The pixel design allows for up to 8–12 frames to be stored internally at high speed before readout, which occurs at a 1 kHz frame rate. An additional mode of operation allows the integration capacitors to be re-addressed repeatedly before readout which can enhance the signal-to-noise ratio of cyclical processes. This detector, along with modern storage ring sources which provide short (10–100 ps) and intense X-ray pulses at megahertz rates, opens new avenues for the study of rapid structural changes in materials. The detector consists of hybridized modules, each of which is comprised of a 500 µm-thick silicon X-ray sensor solder bump-bonded, pixel by pixel, to an application-specific integrated circuit. The format of each module is 128 × 128 pixels with a pixel pitch of 150 µm. In the prototype detector described here, the three-side buttable modules are tiled in a 3 × 2 array with a full format of 256 × 384 pixels. The characteristics, operation, testing and application of the detector are detailed.

  16. All aboard for high-speed rail

    Energy Technology Data Exchange (ETDEWEB)

    Herman, D.

    1996-09-01

    A sleek, bullet-nosed train whizzing across the countryside is a fairly common sight in many nations. Since the Train a Grande Vitesse (TGV)--the record-setting ``train with great speed``--was introduced in France in 1981, Germany, Japan, and other countries have joined the high-speed club. In addition, the Eurostar passenger train, which travels between Great Britain and France through the Channel Tunnel, can move at 186 miles per hour once it reaches French tracks. Despite the technology`s growth elsewhere, rapid rail travel has not been seen on US shores beyond a few test runs by various manufacturers. Before the end of the century, however, American train spotters will finally be able to see some very fast trains here too. In March, Washington, DC-based Amtrak announced the purchase of 18 American Flyer high-speed train sets for the Northeast Corridor, which stretches from Boston through new York to the nation`s capital. Furthermore, Florida will get its own system by 2004, and other states are now taking a look at the technology. The American Flyer--designed by Montreal-based Bombardier and TGV manufacturer GEC Alsthom Transport in Paris--should venture onto US rails by 1999. Traveling at up to 150 miles per hour, the American Flyer will cut the New York-Boston run from 4 1/2 hours to 3 hours and reduce New York-Washington trip time from 3 hours to less than 2 3/4. Amtrak hopes the new trains and better times will earn it a greater share of travelers from air shuttles and perhaps from Interstate 95. This article describes how technologies that tilt railcars and propel the world`s fastest trains will be merged into one train set for the American Flyer, Amtrak`s first trip along high-speed rails.

  17. Controllable High-Speed Rotation of Nanowires

    Science.gov (United States)

    Fan, D. L.; Zhu, F. Q.; Cammarata, R. C.; Chien, C. L.

    2005-06-01

    We report a versatile method for executing controllable high-speed rotation of nanowires by ac voltages applied to multiple electrodes. The rotation of the nanowires can be instantly switched on or off with precisely controlled rotation speed (to at least 1800 rpm), definite chirality, and total angle of rotation. We have determined the torque due to the fluidic drag force on nanowire of different lengths. We also demonstrate a micromotor using a rotating nanowire driving a dust particle into circular motion. This method has been used to rotate magnetic and nonmagnetic nanowires as well as carbon nanotubes.

  18. High-speed multispectral confocal biomedical imaging.

    Science.gov (United States)

    Carver, Gary E; Locknar, Sarah A; Morrison, William A; Ramanujan, V Krishnan; Farkas, Daniel L

    2014-03-01

    A new approach for generating high-speed multispectral confocal images has been developed. The central concept is that spectra can be acquired for each pixel in a confocal spatial scan by using a fast spectrometer based on optical fiber delay lines. This approach merges fast spectroscopy with standard spatial scanning to create datacubes in real time. The spectrometer is based on a serial array of reflecting spectral elements, delay lines between these elements, and a single element detector. The spatial, spectral, and temporal resolution of the instrument is described and illustrated by multispectral images of laser-induced autofluorescence in biological tissues.

  19. Theory Of High-Speed Stereophotogrammetry

    Science.gov (United States)

    Hongxun, Song; Junren, Chen

    1989-06-01

    The general equations of direct linear transformation (DLT) are derived according to the actual process of high-speed stereophotogrammetry. The equations are not only applicable to the ordinary photographic system, but also to the photographic system with reflectors or stereo-reflectors. The equations are also suitable to the enlarged, copied and projected measurements of photographic film. The linear and non-linear errors in photogrammetric process can be corrected. Finally, the equations of right angle intersection photogrammetry are given and the merits and demerits of this method are discussed.

  20. High Speed SPM of Functional Materials

    Energy Technology Data Exchange (ETDEWEB)

    Huey, Bryan D. [Univ. of Connecticut, Storrs, CT (United States)

    2015-08-14

    The development and optimization of applications comprising functional materials necessitates a thorough understanding of their static and dynamic properties and performance at the nanoscale. Leveraging High Speed SPM and concepts enabled by it, efficient measurements and maps with nanoscale and nanosecond temporal resolution are uniquely feasible. This includes recent enhancements for topographic, conductivity, ferroelectric, and piezoelectric properties as originally proposed, as well as newly developed methods or improvements to AFM-based mechanical, friction, thermal, and photoconductivity measurements. The results of this work reveal fundamental mechanisms of operation, and suggest new approaches for improving the ultimate speed and/or efficiency, of data storage systems, magnetic-electric sensors, and solar cells.

  1. Sensory integration in mouse insular cortex reflects GABA circuit maturation

    National Research Council Canada - National Science Library

    Gogolla, Nadine; Takesian, Anne E; Feng, Guoping; Fagiolini, Michela; Hensch, Takao K

    2014-01-01

    Insular cortex (IC) contributes to a variety of complex brain functions, such as communication, social behavior, and self-awareness through the integration of sensory, emotional, and cognitive content...

  2. Miniature high speed compressor having embedded permanent magnet motor

    Science.gov (United States)

    Zhou, Lei (Inventor); Zheng, Liping (Inventor); Chow, Louis (Inventor); Kapat, Jayanta S. (Inventor); Wu, Thomas X. (Inventor); Kota, Krishna M. (Inventor); Li, Xiaoyi (Inventor); Acharya, Dipjyoti (Inventor)

    2011-01-01

    A high speed centrifugal compressor for compressing fluids includes a permanent magnet synchronous motor (PMSM) having a hollow shaft, the being supported on its ends by ball bearing supports. A permanent magnet core is embedded inside the shaft. A stator with a winding is located radially outward of the shaft. The PMSM includes a rotor including at least one impeller secured to the shaft or integrated with the shaft as a single piece. The rotor is a high rigidity rotor providing a bending mode speed of at least 100,000 RPM which advantageously permits implementation of relatively low-cost ball bearing supports.

  3. High-speed optical links for UAV applications

    Science.gov (United States)

    Chen, C.; Grier, A.; Malfa, M.; Booen, E.; Harding, H.; Xia, C.; Hunwardsen, M.; Demers, J.; Kudinov, K.; Mak, G.; Smith, B.; Sahasrabudhe, A.; Patawaran, F.; Wang, T.; Wang, A.; Zhao, C.; Leang, D.; Gin, J.; Lewis, M.; Nguyen, D.; Quirk, K.

    2017-02-01

    High speed optical backbone links between a fleet of UAVs is an integral part of the Facebook connectivity architecture. To support the architecture, the optical terminals need to provide high throughput rates (in excess of tens of Gbps) while achieving low weight and power consumption. The initial effort is to develop and demonstrate an optical terminal capable of meeting the data rate requirements and demonstrate its functions for both air-air and air-ground engagements. This paper is a summary of the effort to date.

  4. ACTS High-Speed VSAT Demonstrated

    Science.gov (United States)

    Tran, Quang K.

    1999-01-01

    The Advanced Communication Technology Satellite (ACTS) developed by NASA has demonstrated the breakthrough technologies of Ka-band transmission, spot-beam antennas, and onboard processing. These technologies have enabled the development of very small and ultrasmall aperture terminals (VSAT s and USAT's), which have capabilities greater than have been possible with conventional satellite technologies. The ACTS High Speed VSAT (HS VSAT) is an effort at the NASA Glenn Research Center at Lewis Field to experimentally demonstrate the maximum user throughput data rate that can be achieved using the technologies developed and implemented on ACTS. This was done by operating the system uplinks as frequency division multiple access (FDMA), essentially assigning all available time division multiple access (TDMA) time slots to a single user on each of two uplink frequencies. Preliminary results show that, using a 1.2-m antenna in this mode, the High Speed VSAT can achieve between 22 and 24 Mbps of the 27.5 Mbps burst rate, for a throughput efficiency of 80 to 88 percent.

  5. Study of high-speed civil transports

    Science.gov (United States)

    1989-01-01

    A systems study to identify the economic potential for a high-speed commercial transport (HSCT) has considered technology, market characteristics, airport infrastructure, and environmental issues. Market forecasts indicate a need for HSCT service in the 2000/2010 time frame conditioned on economic viability and environmental acceptability. Design requirements focused on a 300 passenger, 3 class service, and 6500 nautical mile range based on the accelerated growth of the Pacific region. Compatibility with existing airports was an assumed requirement. Mach numbers between 2 and 25 were examined in conjunction with the appropriate propulsion systems, fuels, structural materials, and thermal management systems. Aircraft productivity was a key parameter with aircraft worth, in comparison to aircraft price, being the airline-oriented figure of merit. Aircraft screening led to determination that Mach 3.2 (TSJF) would have superior characteristics to Mach 5.0 (LNG) and the recommendation that the next generation high-speed commercial transport aircraft use a kerosene fuel. The sensitivity of aircraft performance and economics to environmental constraints (e.g., sonic boom, engine emissions, and airport/community noise) was identified together with key technologies. In all, current technology is not adequate to produce viable HSCTs for the world marketplace. Technology advancements must be accomplished to meet environmental requirements (these requirements are as yet undetermined for sonic boom and engine emissions). High priority is assigned to aircraft gross weight reduction which benefits both economics and environmental aspects. Specific technology requirements are identified and national economic benefits are projected.

  6. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  7. Magnetic force microscopy method and apparatus to detect and image currents in integrated circuits

    Science.gov (United States)

    Campbell, Ann. N.; Anderson, Richard E.; Cole, Jr., Edward I.

    1995-01-01

    A magnetic force microscopy method and improved magnetic tip for detecting and quantifying internal magnetic fields resulting from current of integrated circuits. Detection of the current is used for failure analysis, design verification, and model validation. The interaction of the current on the integrated chip with a magnetic field can be detected using a cantilevered magnetic tip. Enhanced sensitivity for both ac and dc current and voltage detection is achieved with voltage by an ac coupling or a heterodyne technique. The techniques can be used to extract information from analog circuits.

  8. Reflectively coupled waveguide photodetector for high speed optical interconnection.

    Science.gov (United States)

    Hsu, Shih-Hsiang

    2010-01-01

    To fully utilize GaAs high drift mobility, techniques to monolithically integrate In0.53Ga0.47As p-i-n photodetectors with GaAs based optical waveguides using total internal reflection coupling are reviewed. Metal coplanar waveguides, deposited on top of the polyimide layer for the photodetector's planarization and passivation, were then uniquely connected as a bridge between the photonics and electronics to illustrate the high-speed monitoring function. The photodetectors were efficiently implemented and imposed on the echelle grating circle for wavelength division multiplexing monitoring. In optical filtering performance, the monolithically integrated photodetector channel spacing was 2 nm over the 1,520-1,550 nm wavelength range and the pass band was 1 nm at the -1 dB level. For high-speed applications the full-width half-maximum of the temporal response and 3-dB bandwidth for the reflectively coupled waveguide photodetectors were demonstrated to be 30 ps and 11 GHz, respectively. The bit error rate performance of this integrated photodetector at 10 Gbit/s with 2(7)-1 long pseudo-random bit sequence non-return to zero input data also showed error-free operation.

  9. An integrated energy-efficient capacitive sensor digital interface circuit

    KAUST Repository

    Omran, Hesham

    2014-06-19

    In this paper, we propose an energy-efficient 13-bit capacitive sensor interface circuit. The proposed design fully relies on successive approximation algorithm, which eliminates the need for oversampling and digital decimation filtering, and thus low-power consumption is achieved. The proposed architecture employs a charge amplifier stage to acheive parasitic insensitive operation and fine absolute resolution. Moreover, the output code is not affected by offset voltages or charge injection. The successive approximation algorithm is implemented in the capacitance-domain using a coarse-fine programmable capacitor array, which allows digitizing wide capacitance range in compact area. Analysis for the maximum achievable resolution due to mismatch is provided. The proposed design is insensitive to any reference voltage or current which translates to low temperature sensitivity. The operation of a prototype fabricated in a standard CMOS technology is experimentally verified using both on-chip and off-chip capacitive sensors. Compared to similar prior work, the fabricated prototype achieves and excellent energy efficiency of 34 pJ/step.

  10. Quantum dash based single section mode locked lasers for photonic integrated circuits.

    Science.gov (United States)

    Joshi, Siddharth; Calò, Cosimo; Chimot, Nicolas; Radziunas, Mindaugas; Arkhipov, Rostislav; Barbet, Sophie; Accard, Alain; Ramdane, Abderrahim; Lelarge, Francois

    2014-05-05

    We present the first demonstration of an InAs/InP Quantum Dash based single-section frequency comb generator designed for use in photonic integrated circuits (PICs). The laser cavity is closed using a specifically designed Bragg reflector without compromising the mode-locking performance of the self pulsating laser. This enables the integration of single-section mode-locked laser in photonic integrated circuits as on-chip frequency comb generators. We also investigate the relations between cavity modes in such a device and demonstrate how the dispersion of the complex mode frequencies induced by the Bragg grating implies a violation of the equi-distance between the adjacent mode frequencies and, therefore, forbids the locking of the modes in a classical Bragg Device. Finally we integrate such a Bragg Mirror based laser with Semiconductor Optical Amplifier (SOA) to demonstrate the monolithic integration of QDash based low phase noise sources in PICs.

  11. Integrative Strategy for Effective Teaching of Alternating Circuits in ...

    African Journals Online (AJOL)

    One of the reasons advanced for the low enrolment and achievement of students in Physics at both secondary and post-secondary schools is poor teaching strategies used by teachers of Physics particularly in teaching Physics concepts classified by students as being difficult. In this paper, integrative strategy for effective ...

  12. Laser beam welding by high-speed beam deflection; Laserstrahlschweissen durch High-Speed-Strahlbewegung

    Energy Technology Data Exchange (ETDEWEB)

    Klotzbach, A.; Morgenthal, L.; Beyer, E. [Fraunhofer-Institut fuer Werkstoff- und Strahltechnik, Dresden (Germany)

    1999-04-01

    The beam deflection system developed at Fraunhofer IWS can be used for rapid moving of a high power laser beam over the workpiece surface. Therefore it is possible to scan even rather small paths with high speed. The system contents two galvanometer scanner with specially designed lightweight mirrors in combination with a beam focusing unit. (Fig. 1). The high-speed welding of contours with small diameter is favorably done with both focusing optics and workpiece fixed (Fig. 2,3). Thus all notorius problems of conventional handling systems, as limited velocity and accuracy resulting from the inertia of the moved focusing head or workpiece, vanish. (orig.)

  13. W-band Phased Array Systems using Silicon Integrated Circuits

    Science.gov (United States)

    Kim, Sang Young

    This thesis presents the silicon-based on-chip W-band phased array systems. An improved quadrature all-pass filter (QAF) and its implementation in 60--80 GHz active phase shifter using 0.13 microm SiGe BiCMOS technology is presented. It is demonstrated that with the inclusion of an Rs/R in the high Q branches of C and L, the sensitivity to the loading capacitance, therefore the I/Q phase and amplitude errors are minimized. This technique is especially suited for wideband millimeter-wave circuits where the loading capacitance (CL) is comparable to the filter capacitance (C). A prototype 60--80 GHz active phased shifter using the improved QAF is demonstrated. The overall chip size is 1.15 x 0.92 mm2 with the power consumption of 108 mW. The measured S11 and S22 are pass pi-network. The chip size is 0.45 x 0.3 mm2 without pads and consumes virtually no power. The measured S11 and S22 is 8 dBm and the simulated IIP3 is > 22 dBm. A low-power 76--84 GHz 4-element phased array receiver using the designed passive phase shifter is presented. The power consumption is minimized by using a single-ended design and alternating the amplifiers and phase shifter cells to result in a low noise figure at a low power consumption. A variable gain amplifier and the 11° phase shifter are used to correct for the rms gain and phase errors at different operating frequencies. The overall chip size is 2.0 x 2.7 mm2 with the current consumption of 18 mA/channel with 1.8 V supply voltage. The measured S11 and S 22 is circuits are designed differentially to result in less sensitivity to packaging effect and high channel-to-channel isolation. The overall chip size is 5.0 x 5.8 mm 2 with the power consumption of 500--600 mA from 2 V supply voltage. The measured S11 and S22 for all 16 phase states is 10 dB for 76.4--90 GHz with the rms gain error of -45 dB. The measured NF is 11.2--13 dB at 77--87 GHz at the maximum gain state. And the measured input P1dB is 20 dBm at 77 GHz and -25.8 dBm at the

  14. Restoring heart function and electrical integrity: closing the circuit

    Science.gov (United States)

    Monteiro, Luís Miguel; Vasques-Nóvoa, Francisco; Ferreira, Lino; Pinto-do-Ó, Perpétua; Nascimento, Diana Santos

    2017-04-01

    Cardiovascular diseases are the main cause of death in the world and are often associated with the occurrence of arrhythmias due to disruption of myocardial electrical integrity. Pathologies involving dysfunction of the specialized cardiac excitatory/conductive tissue are also common and constitute an added source of morbidity and mortality since current standard therapies withstand a great number of limitations. As electrical integrity is essential for a well-functioning heart, innovative strategies have been bioengineered to improve heart conduction and/or promote myocardial repair, based on: (1) gene and/or cell delivery; or (2) conductive biomaterials as tools for cardiac tissue engineering. Herein we aim to review the state-of-art in the area, while briefly describing the biological principles underlying the heart electrical/conduction system and how this system can be disrupted in heart disease. Suggestions regarding targets for future studies are also presented.

  15. Application of optimized parallel processing digital computers and numerical approximation methods to the ultra high-speed three-dimensional reconstruction of the intact thorax.

    Science.gov (United States)

    Gilbert, B K; Krueger, L M; Chu, A; Ritman, E L; Swartzlander, E E; Atkins, D E

    1979-08-01

    In order to achieve the computational capability to carry out many thousands of cross-sectional reconstructions, necessary to support a prototype high temporal and spatial resolution cylindrical scanning multiaxial tomographic unit, a series of design, software simulation, and fabrication studies is underway to develop a special-purpose high-speed reconstruction computer. This processor will rely upon integrated circuit arithmetic components of advanced design, and highly parallel architecture to execute X-ray based transaxial reconstruction algorithms at the rate of hundreds of cross sections/sec.

  16. High-speed dynamic-clamp interface

    Science.gov (United States)

    Yang, Yang; Adowski, Timothy; Ramamurthy, Bina; Neef, Andreas

    2015-01-01

    The dynamic-clamp technique is highly useful for mimicking synaptic or voltage-gated conductances. However, its use remains rare in part because there are few systems, and they can be expensive and difficult for less-experienced programmers to implement. Furthermore, some conductances (such as sodium channels) can be quite rapid or may have complex voltage sensitivity, so high speeds are necessary. To address these issues, we have developed a new interface that uses a common personal computer platform with National Instruments data acquisition and WaveMetrics IGOR to provide a simple user interface. This dynamic clamp implements leak and linear synaptic conductances as well as a voltage-dependent synaptic conductance and kinetic channel conductances based on Hodgkin-Huxley or Markov models. The speed of the system can be assayed using a testing mode, and currently speeds of >100 kHz (10 μs per cycle) are achievable with short latency and little jitter. PMID:25632075

  17. High-speed electrical motor evaluation

    Energy Technology Data Exchange (ETDEWEB)

    1989-02-03

    Under this task, MTI conducted a general review of state-of-the-art high-speed motors. The purpose of this review was to assess the operating parameters, limitations and performance of existing motor designs, and to establish commercial sources for a motor compatible with the requirements of the Brayton-cycle system. After the motor requirements were established, a list of motor types, manufacturers and designs capable of achieving the requisite performance was compiled. This list was based on an in-house evaluation of designs. Following the establishment of these options, a technical evaluation of the designs selected was conducted. In parallel with their evaluations, MTI focused on the establishment of commercial sources.

  18. HIGH SPEED KERR CELL FRAMING CAMERA

    Science.gov (United States)

    Goss, W.C.; Gilley, L.F.

    1964-01-01

    The present invention relates to a high speed camera utilizing a Kerr cell shutter and a novel optical delay system having no moving parts. The camera can selectively photograph at least 6 frames within 9 x 10/sup -8/ seconds during any such time interval of an occurring event. The invention utilizes particularly an optical system which views and transmits 6 images of an event to a multi-channeled optical delay relay system. The delay relay system has optical paths of successively increased length in whole multiples of the first channel optical path length, into which optical paths the 6 images are transmitted. The successively delayed images are accepted from the exit of the delay relay system by an optical image focusing means, which in turn directs the images into a Kerr cell shutter disposed to intercept the image paths. A camera is disposed to simultaneously view and record the 6 images during a single exposure of the Kerr cell shutter. (AEC)

  19. Network Based High Speed Product Innovation

    DEFF Research Database (Denmark)

    Lindgren, Peter

    In the first decade of the 21st century, New Product Development has undergone major changes in the way NPD is managed and organised. This is due to changes in technology, market demands, and in the competencies of companies. As a result NPD organised in different forms of networks is predicted...... to be of ever-increasing importance to many different kinds of companies. This happens at the same times as the share of new products of total turnover and earnings is increasing at unprecedented speed in many firms and industries. The latter results in the need for very fast innovation and product development...... - a need that can almost only be resolved by organising NPD in some form of network configuration. The work of Peter Lindgren is on several aspects of network based high speed product innovation and contributes to a descriptive understanding of this phenomenon as well as with normative theory on how NPD...

  20. High speed optical filtering using active resonant subwavelength gratings

    Science.gov (United States)

    Gin, A. V.; Kemme, S. A.; Boye, R. R.; Peters, D. W.; Ihlefeld, J. F.; Briggs, R. D.; Wendt, J. R.; Ellis, A. R.; Marshall, L. H.; Carter, T. R.; Hunker, J. D.; Samora, S.

    2010-02-01

    In this work, we describe the most recent progress towards the device modeling, fabrication, testing and system integration of active resonant subwavelength grating (RSG) devices. Passive RSG devices have been a subject of interest in subwavelength-structured surfaces (SWS) in recent years due to their narrow spectral response and high quality filtering performance. Modulating the bias voltage of interdigitated metal electrodes over an electrooptic thin film material enables the RSG components to act as actively tunable high-speed optical filters. The filter characteristics of the device can be engineered using the geometry of the device grating and underlying materials. Using electron beam lithography and specialized etch techniques, we have fabricated interdigitated metal electrodes on an insulating layer and BaTiO3 thin film on sapphire substrate. With bias voltages of up to 100V, spectral red shifts of several nanometers are measured, as well as significant changes in the reflected and transmitted signal intensities around the 1.55um wavelength. Due to their small size and lack of moving parts, these devices are attractive for high speed spectral sensing applications. We will discuss the most recent device testing results as well as comment on the system integration aspects of this project.

  1. High-speed ground transportation noise and vibration impact assessment.

    Science.gov (United States)

    2012-09-01

    This report is the second edition of a guidance manual originally issued in 2005, which presents procedures for predicting and assessing noise and vibration impacts of high-speed ground transportation projects. Projects involving high-speed trains us...

  2. High Speed Magnetostrictive MEMS Actuated Mirror Deflectors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The main goal of this proposal is to develop high speed magnetostrictive and MEMS actuators for rapidly deflecting or deforming mirrors. High speed, light-weight,...

  3. Potential scenarios of concern for high speed rail operations

    Science.gov (United States)

    2011-03-16

    Currently, multiple operating authorities are proposing the : introduction of high-speed rail service in the United States. : While high-speed rail service shares a number of basic : principles with conventional-speed rail service, the operational : ...

  4. South Carolina southeast high speed rail corridor improvement study

    Science.gov (United States)

    2001-02-01

    The Southeast Rail Corridor was originally designated as a high-speed corridor in Section 1010 of the Intermodal Surface Transportation Efficiency Act (ISTEA) of 1991. More specifically, it involved the high-speed grade-crossing improvement program o...

  5. High-speed and intercity passenger rail testing strategy.

    Science.gov (United States)

    2013-05-01

    This high-speed and intercity passenger rail (HSIPR) testing strategy addresses the requirements for testing of high-speed train sets and technology before introduction to the North American railroad system. The report documents the results of a surv...

  6. High Speed Magnetostrictive MEMS Actuated Mirror Deflectors Project

    Data.gov (United States)

    National Aeronautics and Space Administration — We propose to develop high speed magnetostrictive and MEMS actuators for rapidly deflecting or deforming mirrors. High speed, light-weight, low voltage beam...

  7. The Hybrid Integrated Circuit of the ALICE Inner Tracking System upgrade

    CERN Document Server

    Fiorenza, G; Pastore, C; Valentino, V

    2016-01-01

    The upgrade of the Inner Tracking System scheduled during the second long shutdown is an important milestone of the ALICE upgrade and it will provide a high improvement of its performances. In this contribution the smallest operator unit of the detector, the Hybrid Integrated Circuits, is presented.

  8. The impact of very high performance integrated circuits on avionics system readiness

    Science.gov (United States)

    Strull, G.

    1985-08-01

    Very high performance integrated circuits (VHPIC) represent more than an integrated circuit technology advance- VHPIC really represents a new systems/technology culture. With a philosophy of top-down design and bottom-up build, a vehicle is provided to avoid rapid obsolescence so prevalent in the fast moving integrated circuit industry. However, to successfully and effectively design advanced systems in this manner, a design methodology is required that adequately addresses the challenge. Since everything from chip definition through application analysis is interactive with everything else, the challenge is to adequately keep track of all the perimeters and their relationship. The methodology by which design and analysis are accomplished is discussed. The starting point is the systems architecture and its application software. From the architecture and application software the partitioning of the system into appropriate modules can be derived. From this an idea of the integrated circuits needed can be determined. The elements of system readiness are described. They are design, implementation, insertion, maintenance, and (Preplanned Product Improvement).

  9. Effective Teaching of the Physical Design of Integrated Circuits Using Educational Tools

    Science.gov (United States)

    Aziz, Syed Mahfuzul; Sicard, Etienne; Ben Dhia, Sonia

    2010-01-01

    This paper presents the strategies used for effective teaching and skill development in integrated circuit (IC) design using project-based learning (PBL) methodologies. It presents the contexts in which these strategies are applied to IC design courses at the University of South Australia, Adelaide, Australia, and the National Institute of Applied…

  10. InP HEMT Integrated Circuits for Submillimeter Wave Radiometers in Earth Remote Sensing

    Science.gov (United States)

    Deal, William R.; Chattopadhyay, Goutam

    2012-01-01

    The operating frequency of InP integrated circuits has pushed well into the Submillimeter Wave frequency band, with amplification reported as high as 670 GHz. This paper provides an overview of current performance and potential application of InP HEMT to Submillimeter Wave radiometers for earth remote sensing.

  11. 77 FR 67833 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission...

    Science.gov (United States)

    2012-11-14

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Radio Frequency Integrated Circuits and Devices Containing Same; Notice of Commission Determination Not To Review an Initial Determination Terminating the Investigation in its Entirety AGENCY: U.S...

  12. Wideband Monolithic Microwave Integrated Circuit Frequency Converters with GaAs mHEMT Technology

    DEFF Research Database (Denmark)

    Krozer, Viktor; Johansen, Tom Keinicke; Djurhuus, Torsten

    2005-01-01

    We present monolithic microwave integrated circuit (MMIC) frequency converter, which can be used for up and down conversion, due to the large RF and IF port bandwidth. The MMIC converters are based on commercially available GaAs mHEMT technology and are comprised of a Gilbert mixer cell core...

  13. 77 FR 40381 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice...

    Science.gov (United States)

    2012-07-09

    ... From the Federal Register Online via the Government Publishing Office INTERNATIONAL TRADE COMMISSION Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof, Notice... conditions in the U.S. economy or U.S. consumers. No petitions for review were received.The Commission has...

  14. SPICE Modeling of Body Bias Effect in 4H-SiC Integrated Circuit Resistors

    Science.gov (United States)

    Neudeck, Philip G.

    2017-01-01

    The DC electrical behavior of n-type 4H-SiC resistors used for realizing 500C durable integrated circuits (ICs) is studied as a function of substrate bias and temperature. Improved fidelity electrical simulation is described using SPICE NMOS model to simulate resistor substrate body bias effect that is absent from the SPICE semiconductor resistor model.

  15. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

    NARCIS (Netherlands)

    Roozeboom, F.; Narayanan, V.; Kakushima, K.; Timans, P.J.; Gusev, E.P.; Karim, Z.; Gendt, S. De

    2016-01-01

    The topics of this annual symposium continue to describe the evolution of traditional scaling in CMOS integrated circuit manufacturing (More Moore for short), combined with the opportunities from growing diversification and embedded functionality (More than Moore). Once again, the main objective was

  16. A METHOD AND AN APPARATUS FOR PROVIDING TIMING SIGNALS TO A NUMBER OF CIRCUITS, AN INTEGRATED CIRCUIT AND A NODE

    DEFF Research Database (Denmark)

    2006-01-01

    A method of providing or transporting a timing signal between a number of circuits, electrical or optical, where each circuit is fed by a node. The nodes forward timing signals between each other, and at least one node is adapted to not transmit a timing signal before having received a timing...... signal from at least two nodes. In this manner, the direction of the timing skew between nodes and circuits is known and data transport between the circuits made easier....

  17. Performance prediction for silicon photonics integrated circuits with layout-dependent correlated manufacturing variability.

    Science.gov (United States)

    Lu, Zeqin; Jhoja, Jaspreet; Klein, Jackson; Wang, Xu; Liu, Amy; Flueckiger, Jonas; Pond, James; Chrostowski, Lukas

    2017-05-01

    This work develops an enhanced Monte Carlo (MC) simulation methodology to predict the impacts of layout-dependent correlated manufacturing variations on the performance of photonics integrated circuits (PICs). First, to enable such performance prediction, we demonstrate a simple method with sub-nanometer accuracy to characterize photonics manufacturing variations, where the width and height for a fabricated waveguide can be extracted from the spectral response of a racetrack resonator. By measuring the spectral responses for a large number of identical resonators spread over a wafer, statistical results for the variations of waveguide width and height can be obtained. Second, we develop models for the layout-dependent enhanced MC simulation. Our models use netlist extraction to transfer physical layouts into circuit simulators. Spatially correlated physical variations across the PICs are simulated on a discrete grid and are mapped to each circuit component, so that the performance for each component can be updated according to its obtained variations, and therefore, circuit simulations take the correlated variations between components into account. The simulation flow and theoretical models for our layout-dependent enhanced MC simulation are detailed in this paper. As examples, several ring-resonator filter circuits are studied using the developed enhanced MC simulation, and statistical results from the simulations can predict both common-mode and differential-mode variations of the circuit performance.

  18. On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

    Science.gov (United States)

    He, Li; Li, Mo

    2014-05-01

    The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

  19. New high-speed line Nuremberg - Ingolstadt - Electrical engineering equipment; Neubaustrecke (NBS) Nuernberg - Ingolstadt - Technische Ausruestung

    Energy Technology Data Exchange (ETDEWEB)

    Krems, S. [Balfour Beatty Rail GmbH, Berlin (Germany); Matthes, U. [DB Projektbau GmbH, Nuernberg (Germany)

    2007-07-01

    The Bavarian fast railway line Nuremberg - Ingolstadt is equipped with most recent railway infrastructure for a 300 km/h fast high-speed traffic. The electrical engineering installations were implemented within a seven years period. Since December 2006 the line has been integrated into scheduled services and operated with high-speed trains. So far, the installations complied fully with all the requirements. (orig.)

  20. High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

    Science.gov (United States)

    Sridhar, Ranjana; Pandey, Neeta; Bhattacharyya, Asok; Bhatia, Veepsa

    2016-06-01

    This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, -0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

  1. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  2. Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

    Science.gov (United States)

    2018-01-01

    ORGANIZATION NAME(S) AND ADDRESS(ES) University of Kansas Center for Research, Inc. 2385 Irving Hill Rd Lawrence KS 66045-7552 8. PERFORMING... ORGANIZATION REPORT NUMBER 9. SPONSORING/MONITORING AGENCY NAME(S) AND ADDRESS(ES) Air Force Research Laboratory/RITB 525 Brooks Road Rome NY 13441-4505 10...multidisciplinary effort encompassed high-performance computing, nanotechnology, integrated circuits, and integrated systems. The project’s architecture was

  3. Fusion: ultra-high-speed and IR image sensors

    Science.gov (United States)

    Etoh, T. Goji; Dao, V. T. S.; Nguyen, Quang A.; Kimata, M.

    2015-08-01

    Most targets of ultra-high-speed video cameras operating at more than 1 Mfps, such as combustion, crack propagation, collision, plasma, spark discharge, an air bag at a car accident and a tire under a sudden brake, generate sudden heat. Researchers in these fields require tools to measure the high-speed motion and heat simultaneously. Ultra-high frame rate imaging is achieved by an in-situ storage image sensor. Each pixel of the sensor is equipped with multiple memory elements to record a series of image signals simultaneously at all pixels. Image signals stored in each pixel are read out after an image capturing operation. In 2002, we developed an in-situ storage image sensor operating at 1 Mfps 1). However, the fill factor of the sensor was only 15% due to a light shield covering the wide in-situ storage area. Therefore, in 2011, we developed a backside illuminated (BSI) in-situ storage image sensor to increase the sensitivity with 100% fill factor and a very high quantum efficiency 2). The sensor also achieved a much higher frame rate,16.7 Mfps, thanks to the wiring on the front side with more freedom 3). The BSI structure has another advantage that it has less difficulties in attaching an additional layer on the backside, such as scintillators. This paper proposes development of an ultra-high-speed IR image sensor in combination of advanced nano-technologies for IR imaging and the in-situ storage technology for ultra-highspeed imaging with discussion on issues in the integration.

  4. Power Management Integrated Circuit for Indoor Photovoltaic Energy Harvesting System

    Science.gov (United States)

    Jain, Vipul

    In today's world, power dissipation is a main concern for battery operated mobile devices. Key design decisions are being governed by power rather than area/delay because power requirements are growing more stringent every year. Hence, a hybrid power management system is proposed, which uses both a solar panel to harvest energy from indoor lighting and a battery to power the load. The system tracks the maximum power point of the solar panel and regulates the battery and microcontroller output load voltages through the use of an on-chip switched-capacitor DC-DC converter. System performance is verified through simulation at the 180nm technology node and is made to be integrated on-chip with 0.25 second startup time, 79% efficiency, --8/+14% ripple on the load, an average 1micro A of quiescent current (3.7micro W of power) and total on-chip area of 1.8mm2 .

  5. High-Speed Low-Jitter Frequency Multiplication in CMOS

    NARCIS (Netherlands)

    van de Beek, R.C.H.

    2004-01-01

    This thesis deals with high-speed Clock and Frequency Multiplication. The term `high-speedù applies to both the output and the reference frequency of the multiplier. Much emphasis is placed on analysis and optimization of the total timing inaccuracies, and on implementing a high-speed feedback

  6. Videokymography : High-speed line scanning of vocal fold vibration

    NARCIS (Netherlands)

    Svec, JG; Schutte, HK

    A digital technique for high-speed visualization of vibration, called videokymography, was developed and applied to the vocal folds. The system uses a modified video camera able to work in two modes: high-speed (nearly 8,000 images/s) and standard (50 images/s in CCIR norm). In the high-speed mode,

  7. 4H-SiC JFET Multilayer Integrated Circuit Technologies Tested Up to 1000 K

    Science.gov (United States)

    Spry, D. J.; Neudeck, P. G.; Chen, L.; Chang, C. W.; Lukco, D.; Beheim, G. M.

    2015-01-01

    Testing of semiconductor electronics at temperatures above their designed operating envelope is recognized as vital to qualification and lifetime prediction of circuits. This work describes the high temperature electrical testing of prototype 4H silicon carbide (SiC) junction field effect transistor (JFET) integrated circuits (ICs) technology implemented with multilayer interconnects; these ICs are intended for prolonged operation at temperatures up to 773K (500 C). A 50 mm diameter sapphire wafer was used in place of the standard NASA packaging for this experiment. Testing was carried out between 300K (27 C) and 1150K (877 C) with successful electrical operation of all devices observed up to 1000K (727 C).

  8. SEMICONDUCTOR DEVICES: A novel high voltage start up circuit for an integrated switched mode power supply

    Science.gov (United States)

    Hao, Hu; Xingbi, Chen

    2010-09-01

    A novel high voltage start up circuit for providing an initial bias voltage to an integrated switched mode power supply (SMPS) is presented. An enhanced mode VDMOS transistor, the gate of which is biased by a floating p-island, is used to provide start up current and sustain high voltage. An NMOS transistor having a high source to ground breakdown voltage is included to extend the bias voltage range to the SMPS. Simulation results indicate that the high voltage start up circuit can start and restart as designed. The proposed structure is believed to be more energy saving and cost-effective compared with other solutions.

  9. Verification and Quantification of Single Event Effects on High Speed SRAM in Terrestrial Environments

    Science.gov (United States)

    Huff, H.; You, Z.; Williams, T.; Nichols, T.; Attia, J.; Fogarty, T. N.; Kirby, K.; Wilkins, R.; Lawton, R.

    1998-01-01

    As integrated circuits become more sensitive to charged particles and neutrons, anomalous performance due to single event effects (SEE) is a concern and requires experimental verification and quantification. The Center for Applied Radiation Research (CARR) at Prairie View A&M University has developed experiments as a participant in the NASA ER-2 Flight Program, the APEX balloon flight program and the Student Launch Program. Other high altitude and ground level experiments of interest to DoD and commercial applications are being developed. The experiment characterizes the SEE behavior of high speed and high density SRAM's. The system includes a PC-104 computer unit, an optical drive for storage, a test board with the components under test, and a latchup detection and reset unit. The test program will continuously monitor the stored checkerboard data pattern in the SW and record errors. Since both the computer and the optical drive contain integrated circuits, they are also vulnerable to radiation effects. A latchup detection unit with discrete components will monitor the test program and reset the system when necessary. The first results will be obtained from the NASA ER-2 flights, which are now planned to take place in early 1998 from Dryden Research Center in California. The series of flights, at altitudes up to 70,000 feet, and a variety of flight profiles should yield a distribution of conditions for correlating SEES. SEE measurements will be performed from the time of aircraft power-up on the ground throughout the flight regime until systems power-off after landing.

  10. SELF-ALIGNED SINGLE CRYSTAL CONTACTED HIGH-SPEED SILICON BIPOLAR TRANSISTOR UTILIZING SELECTIVE (SEG) AND CONFINED SELECTIVE EPITAXIAL GROWTH (CLSEG)

    OpenAIRE

    Siekkinen, James W.; Neudeck, Gerold W.

    1992-01-01

    A new high-speed bipolar transistor structure, the ELOBJT-3, is proposed as a novel application of selective epitaxy technology. The new structure is greatly suited to high-speed ECL circuits, where Ccb, C,, and Rbx are of prime importance. The reduction of these parasitics to their nearly theoretical minimums is accomplished through the use of dielectric isolation and concentric contacting. For extremely high speed operation, dimensions can be scaled to sub-micron size due to the completely ...

  11. A thermal protection module for automotive integrated circuits

    Science.gov (United States)

    Han, Yifeng; Zhai, Mingjing; Zhou, Junfeng

    2017-07-01

    Automotive ICs work in wide ambient temperature range up to 150∘C. It is important to design an over temperature protection mechanism for the reliability of ICs and systems. A thermal protection module for the automotive ICs is reported in this paper. Dual channel detection and decision scheme was designed based on band gap voltage reference. Precision thermal protection point was set by serial resistors and the variations of power supply, temperature and the process were removed by the resistor ratio. The thermal protection module was implemented in CSMC 0.5 μm 60 V BCD process, incorporated in a CAN transceiver chip. The area of the module was about 0.02 mm2 and thus it was very compact and low cost to integrate in chips. The performance of the thermal protection parameters was measured in incubators. The thermal shutdown temperature was about 164.4∘C and the thermal recovery temperature was about 153∘C with hysteresis temperature of 10 K. Additionally, the thermal protection module showed good consistency with different chips.

  12. Active resonant subwavelength grating devices for high speed spectroscopic sensing

    Science.gov (United States)

    Gin, A. V.; Kemme, S. A.; Boye, R. R.; Peters, D. W.; Ihlefeld, J. F.; Briggs, R. D.; Wendt, J. R.; Marshall, L. H.; Carter, T. R.; Samora, S.

    2009-02-01

    In this paper, we describe progress towards a multi-color spectrometer and radiometer based upon an active resonant subwavelength grating (RSG). This active RSG component acts as a tunable high-speed optical filter that allows device miniaturization and ruggedization not realizable using current sensors with conventional bulk optics. Furthermore, the geometrical characteristics of the device allow for inherently high speed operation. Because of the small critical dimensions of the RSG devices, the fabrication of these sensors can prove challenging. However, we utilize the state-of-the-art capabilities at Sandia National Laboratories to realize these subwavelength grating devices. This work also leverages previous work on passive RSG devices with greater than 98% efficiency and ~1nm FWHM. Rigorous coupled wave analysis has been utilized to design RSG devices with PLZT, PMN-PT and BaTiO3 electrooptic thin films on sapphire substrates. The simulated interdigitated electrode configuration achieves field strengths around 3×107 V/m. This translates to an increase in the refractive index of 0.05 with a 40V bias potential resulting in a 90% contrast of the modulated optical signal. We have fabricated several active RSG devices on selected electro-optic materials and we discuss the latest experimental results on these devices with variable electrostatic bias and a tunable wavelength source around 1.5μm. Finally, we present the proposed data acquisition hardware and system integration plans.

  13. High-speed stimulated Brillouin scattering spectroscopy at 780 nm

    Directory of Open Access Journals (Sweden)

    Itay Remer

    2016-09-01

    Full Text Available We demonstrate a high-speed stimulated Brillouin scattering (SBS spectroscopy system that is able to acquire stimulated Brillouin gain point-spectra in water samples and Intralipid tissue phantoms over 2 GHz within 10 ms and 100 ms, respectively, showing a 10-100 fold increase in acquisition rates over current frequency-domain SBS spectrometers. This improvement was accomplished by integrating an ultra-narrowband hot rubidium-85 vapor notch filter in a simplified frequency-domain SBS spectrometer comprising nearly counter-propagating continuous-wave pump-probe light at 780 nm and conventional single-modulation lock-in detection. The optical notch filter significantly suppressed stray pump light, enabling detection of stimulated Brillouin gain spectra with substantially improved acquisition times at adequate signal-to-noise ratios (∼25 dB in water samples and ∼15 dB in tissue phantoms. These results represent an important step towards the use of SBS spectroscopy for high-speed measurements of Brillouin gain resonances in scattering and non-scattering samples.

  14. High speed and wide bandwidth delta-sigma ADCs

    CERN Document Server

    Bolatkale, Muhammed; Makinwa, Kofi A A

    2014-01-01

    This book describes techniques for realizing wide bandwidth (125MHz) over-sampled analog-to-digital converters (ADCs) in nanometer-CMOS processes.  The authors offer a clear and complete picture of system level challenges and practical design solutions in high-speed Delta-Sigma modulators.  Readers will be enabled to implement ADCs as continuous-time delta-sigma (CT∆Σ) modulators, offering simple resistive inputs, which do not require the use of power-hungry input buffers, as well as offering inherent anti-aliasing, which simplifies system integration. The authors focus on the design of high speed and wide-bandwidth ΔΣMs that make a step in bandwidth range which was previously only possible with Nyquist converters. More specifically, this book describes the stability, power efficiency, and linearity limits of ΔΣMs, aiming at a GHz sampling frequency.   • Provides overview of trends in Wide Bandwidth and High Dynamic Range analog-to-digital converters (ADCs); • Enables the design of a wide band...

  15. Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

    Science.gov (United States)

    Abraham, Billion; Widodo, Arif; Chen, Poki

    2016-06-01

    In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

  16. Deterministic Integration of Single Photon Sources in Silicon Based Photonic Circuits.

    Science.gov (United States)

    Zadeh, Iman Esmaeil; Elshaari, Ali W; Jöns, Klaus D; Fognini, Andreas; Dalacu, Dan; Poole, Philip J; Reimer, Michael E; Zwiller, Val

    2016-04-13

    A major step toward fully integrated quantum optics is the deterministic incorporation of high quality single photon sources in on-chip optical circuits. We show a novel hybrid approach in which preselected III-V single quantum dots in nanowires are transferred and integrated in silicon based photonic circuits. The quantum emitters maintain their high optical quality after integration as verified by measuring a low multiphoton probability of 0.07 ± 0.07 and emission line width as narrow as 3.45 ± 0.48 GHz. Our approach allows for optimum alignment of the quantum dot light emission to the fundamental waveguide mode resulting in very high coupling efficiencies. We estimate a coupling efficiency of 24.3 ± 1.7% from the studied single-photon source to the photonic channel and further show by finite-difference time-domain simulations that for an optimized choice of material and design the efficiency can exceed 90%.

  17. High-Speed Interferometry Under Impacting Drops

    KAUST Repository

    Langley, Kenneth R.

    2017-08-31

    Over the last decade the rapid advances in high-speed video technology, have opened up to study many multi-phase fluid phenomena, which tend to occur most rapidly on the smallest length-scales. One of these is the entrapment of a small bubble under a drop impacting onto a solid surface. Here we have gone from simply observing the presence of the bubble to detailed imaging of the formation of a lubricating air-disc under the drop center and its subsequent contraction into the bubble. Imaging the full shape-evolution of the air-disc has required μm and sub-μs space and time resolutions. Time-resolved 200 ns interferometry with monochromatic light, has allowed us to follow individual fringes to obtain absolute air-layer thicknesses, based on the eventual contact with the solid. We can follow the evolution of the dimple shape as well as the compression of the gas. The improved imaging has also revealed new levels of detail, like the nature of the first contact which produces a ring of micro-bubbles, highlighting the influence of nanometric surface roughness. Finally, for impacts of ultra-viscous drops we see gliding on ~100 nm thick rarified gas layers, followed by extreme wetting at numerous random spots.

  18. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication.

    Science.gov (United States)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  19. CMOS Integrated Lock-in Readout Circuit for FET Terahertz Detectors

    Science.gov (United States)

    Domingues, Suzana; Perenzoni, Daniele; Perenzoni, Matteo; Stoppa, David

    2017-06-01

    In this paper, a switched-capacitor readout circuit topology integrated with a THz antenna and field-effect transistor detector is analyzed, designed, and fabricated in a 0.13-μm standard CMOS technology. The main objective is to perform amplification and filtering of the signal, as well as subtraction of background in case of modulated source, in order to avoid the need for an external lock-in amplifier, in a compact implementation. A maximum responsivity of 139.7 kV/W, and a corresponding minimum NEP of 2.2 nW/√Hz, was obtained with a two-stage readout circuit at 1 kHz modulation frequency. The presented switched-capacitor circuit is suitable for implementation in pixel arrays due to its compact size and power consumption (0.014 mm2 and 36 μW).

  20. Wafer scale millimeter-wave integrated circuits based on epitaxial graphene in high data rate communication

    Science.gov (United States)

    Habibpour, Omid; He, Zhongxia Simon; Strupinski, Wlodek; Rorsman, Niklas; Zirath, Herbert

    2017-02-01

    In recent years, the demand for high data rate wireless communications has increased dramatically, which requires larger bandwidth to sustain multi-user accessibility and quality of services. This can be achieved at millimeter wave frequencies. Graphene is a promising material for the development of millimeter-wave electronics because of its outstanding electron transport properties. Up to now, due to the lack of high quality material and process technology, the operating frequency of demonstrated circuits has been far below the potential of graphene. Here, we present monolithic integrated circuits based on epitaxial graphene operating at unprecedented high frequencies (80-100 GHz). The demonstrated circuits are capable of encoding/decoding of multi-gigabit-per-second information into/from the amplitude or phase of the carrier signal. The developed fabrication process is scalable to large wafer sizes.

  1. High-Speed Data Recorder for Space, Geodesy, and Other High-Speed Recording Applications

    Science.gov (United States)

    Taveniku, Mikael

    2013-01-01

    A high-speed data recorder and replay equipment has been developed for reliable high-data-rate recording to disk media. It solves problems with slow or faulty disks, multiple disk insertions, high-altitude operation, reliable performance using COTS hardware, and long-term maintenance and upgrade path challenges. The current generation data recor - ders used within the VLBI community are aging, special-purpose machines that are both slow (do not meet today's requirements) and are very expensive to maintain and operate. Furthermore, they are not easily upgraded to take advantage of commercial technology development, and are not scalable to multiple 10s of Gbit/s data rates required by new applications. The innovation provides a softwaredefined, high-speed data recorder that is scalable with technology advances in the commercial space. It maximally utilizes current technologies without being locked to a particular hardware platform. The innovation also provides a cost-effective way of streaming large amounts of data from sensors to disk, enabling many applications to store raw sensor data and perform post and signal processing offline. This recording system will be applicable to many applications needing realworld, high-speed data collection, including electronic warfare, softwaredefined radar, signal history storage of multispectral sensors, development of autonomous vehicles, and more.

  2. Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering.

    Science.gov (United States)

    Mars, Kamel; Lioe, De Xing; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2017-11-09

    Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS) have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS) image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM) employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system.

  3. Label-Free Biomedical Imaging Using High-Speed Lock-In Pixel Sensor for Stimulated Raman Scattering

    Directory of Open Access Journals (Sweden)

    Kamel Mars

    2017-11-01

    Full Text Available Raman imaging eliminates the need for staining procedures, providing label-free imaging to study biological samples. Recent developments in stimulated Raman scattering (SRS have achieved fast acquisition speed and hyperspectral imaging. However, there has been a problem of lack of detectors suitable for MHz modulation rate parallel detection, detecting multiple small SRS signals while eliminating extremely strong offset due to direct laser light. In this paper, we present a complementary metal-oxide semiconductor (CMOS image sensor using high-speed lock-in pixels for stimulated Raman scattering that is capable of obtaining the difference of Stokes-on and Stokes-off signal at modulation frequency of 20 MHz in the pixel before reading out. The generated small SRS signal is extracted and amplified in a pixel using a high-speed and large area lateral electric field charge modulator (LEFM employing two-step ion implantation and an in-pixel pair of low-pass filter, a sample and hold circuit and a switched capacitor integrator using a fully differential amplifier. A prototype chip is fabricated using 0.11 μm CMOS image sensor technology process. SRS spectra and images of stearic acid and 3T3-L1 samples are successfully obtained. The outcomes suggest that hyperspectral and multi-focus SRS imaging at video rate is viable after slight modifications to the pixel architecture and the acquisition system.

  4. A Dynamic Range Enhanced Readout Technique with a Two-Step TDC for High Speed Linear CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Zhiyuan Gao

    2015-11-01

    Full Text Available This paper presents a dynamic range (DR enhanced readout technique with a two-step time-to-digital converter (TDC for high speed linear CMOS image sensors. A multi-capacitor and self-regulated capacitive trans-impedance amplifier (CTIA structure is employed to extend the dynamic range. The gain of the CTIA is auto adjusted by switching different capacitors to the integration node asynchronously according to the output voltage. A column-parallel ADC based on a two-step TDC is utilized to improve the conversion rate. The conversion is divided into coarse phase and fine phase. An error calibration scheme is also proposed to correct quantization errors caused by propagation delay skew within −Tclk~+Tclk. A linear CMOS image sensor pixel array is designed in the 0.13 μm CMOS process to verify this DR-enhanced high speed readout technique. The post simulation results indicate that the dynamic range of readout circuit is 99.02 dB and the ADC achieves 60.22 dB SNDR and 9.71 bit ENOB at a conversion rate of 2 MS/s after calibration, with 14.04 dB and 2.4 bit improvement, compared with SNDR and ENOB of that without calibration.

  5. Optimized Signaling Method for High-Speed Transmission Channels with Higher Order Transfer Function

    Science.gov (United States)

    Ševčík, Břetislav; Brančík, Lubomír; Kubíček, Michal

    2017-08-01

    In this paper, the selected results from testing of optimized CMOS friendly signaling method for high-speed communications over cables and printed circuit boards (PCBs) are presented and discussed. The proposed signaling scheme uses modified concept of pulse width modulated (PWM) signal which enables to better equalize significant channel losses during data high-speed transmission. Thus, the very effective signaling method to overcome losses in transmission channels with higher order transfer function, typical for long cables and multilayer PCBs, is clearly analyzed in the time and frequency domain. Experimental results of the measurements include the performance comparison of conventional PWM scheme and clearly show the great potential of the modified signaling method for use in low power CMOS friendly equalization circuits, commonly considered in modern communication standards as PCI-Express, SATA or in Multi-gigabit SerDes interconnects.

  6. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

    Science.gov (United States)

    Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

    2016-08-10

    Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

  7. Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

    Science.gov (United States)

    McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

    2017-03-28

    Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

  8. Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

    Science.gov (United States)

    Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

    2017-01-01

    Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate integrated waveguides, where the waves propagate through air, thus reducing the associated losses. This is the case of the empty substrate integrated waveguide (ESIW) or the air-filled substrate integrated waveguide (air-filled SIW). However, all these SIC are H plane structures, so classical H plane solutions in rectangular waveguides have already been mapped to most of these new SIC. In this paper a novel E plane empty substrate integrated waveguide (ESIW-E) is presented. This structure allows to easily map classical E plane solutions in rectangular waveguide to this new substrate integrated solution. It is similar to the ESIW, although more layers are needed to build the structure. A wideband transition (covering the frequency range between 33 GHz and 50 GHz) from microstrip to ESIW-E is designed and manufactured. Measurements are successfully compared with simulation, proving the validity of this new SIC. A broadband high-frequency phase shifter (for operation from 35 GHz to 47 GHz) is successfully implemented in ESIW-E, thus proving the good performance of this new SIC in a practical application.

  9. High Speed/ Low Effluent Process for Ethanol

    Energy Technology Data Exchange (ETDEWEB)

    M. Clark Dale

    2006-10-30

    n this project, BPI demonstrated a new ethanol fermentation technology, termed the High Speed/ Low Effluent (HS/LE) process on both lab and large pilot scale as it would apply to wet mill and/or dry mill corn ethanol production. The HS/LE process allows very rapid fermentations, with 18 to 22% sugar syrups converted to 9 to 11% ethanol ‘beers’ in 6 to 12 hours using either a ‘consecutive batch’ or ‘continuous cascade’ implementation. This represents a 5 to 8X increase in fermentation speeds over conventional 72 hour batch fermentations which are the norm in the fuel ethanol industry today. The ‘consecutive batch’ technology was demonstrated on a large pilot scale (4,800 L) in a dry mill corn ethanol plant near Cedar Rapids, IA (Xethanol Biofuels). The pilot demonstrated that 12 hour fermentations can be accomplished on an industrial scale in a non-sterile industrial environment. Other objectives met in this project included development of a Low Energy (LE) Distillation process which reduces the energy requirements for distillation from about 14,000 BTU/gal steam ($0.126/gal with natural gas @ $9.00 MCF) to as low as 0.40 KW/gal electrical requirements ($0.022/gal with electricity @ $0.055/KWH). BPI also worked on the development of processes that would allow application of the HS/LE fermentation process to dry mill ethanol plants. A High-Value Corn ethanol plant concept was developed to produce 1) corn germ/oil, 2) corn bran, 3) ethanol, 4) zein protein, and 5) nutritional protein, giving multiple higher value products from the incoming corn stream.

  10. A MoTe2 based light emitting diode and photodetector for silicon photonic integrated circuits

    Science.gov (United States)

    Bie, Ya-Qing; Heuck, M.; Grosso, G.; Furchi, M.; Cao, Y.; Zheng, J.; Navarro-Moratalla, E.; Zhou, L.; Taniguchi, T.; Watanabe, K.; Kong, J.; Englund, D.; Jarillo-Herrero, P.

    A key challenge in photonics today is to address the interconnects bottleneck in high-speed computing systems. Silicon photonics has emerged as a leading architecture, partly because many components such as waveguides, interferometers and modulators, could be integrated on silicon-based processors. However, light sources and photodetectors present continued challenges. Common approaches for light source include off-chip or wafer-bonded lasers based on III-V materials, but studies show advantages for directly modulated light sources. The most advanced photodetectors in silicon photonics are based on germanium growth which increases system cost. The emerging two dimensional transition metal dichalcogenides (TMDs) offer a path for optical interconnects components that can be integrated with the CMOS processing by back-end-of-the-line processing steps. Here we demonstrate a silicon waveguide-integrated light source and photodetector based on a p-n junction of bilayer MoTe2, a TMD semiconductor with infrared band gap. The state-of-the-art fabrication technology provides new opportunities for integrated optoelectronic systems.

  11. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  12. VCSEL-based optical transceiver module for high-speed short-reach interconnect

    Science.gov (United States)

    Yagisawa, Takatoshi; Oku, Hideki; Mori, Tatsuhiro; Tsudome, Rie; Tanaka, Kazuhiro; Daikuhara, Osamu; Komiyama, Takeshi; Ide, Satoshi

    2017-02-01

    Interconnects have been more important in high-performance computing systems and high-end servers beside its improvements in computing capability. Recently, active optical cables (AOCs) have started being used for this purpose instead of conventionally used copper cables. The AOC enables to extend the transmission distance of the high-speed signals dramatically by its broadband characteristics, however, it tend to increase the cost. In this paper, we report our developed quad small form-factor pluggable (QSFP) AOC utilizing cost-effective optical-module technologies. These are a unique structure using generally used flexible printed circuit (FPC) in combination with an optical waveguide that enables low-cost high-precision assembly with passive alignment, a lens-integrated ferrule that improves productivity by eliminating a polishing process for physical contact of standard PMT connector for the optical waveguide, and an overdrive technology that enables 100 Gb/s (25 Gb/s × 4-channel) operation with low-cost 14 Gb/s vertical-cavity surfaceemitting laser (VCSEL) array. The QSFP AOC demonstrated clear eye opening and error-free operation at 100 Gb/s with high yield rate even though the 14 Gb/s VCSEL was used thanks to the low-coupling loss resulting from the highprecision alignment of optical devices and the over-drive technology.

  13. Quiet High Speed Fan II (QHSF II): Final Report

    Science.gov (United States)

    Kontos, Karen; Weir, Don; Ross, Dave

    2012-01-01

    This report details the aerodynamic, mechanical, structural design and fabrication of a Honey Engines Quiet High Speed Fan II (lower hub/tip ratio and higher specific flow than the Baseline I fan). This fan/nacelle system incorporates features such as advanced forward sweep and an advanced integrated fan/fan exit guide vane design that provides for the following characteristics: (1) Reduced noise at supersonic tip speeds, in comparison to current state-of-the-art fan technology; (2) Improved aeroelastic stability within the anticipated operating envelope; and (3) Aerodynamic performance consistent with current state-of-the-art fan technology. This fan was fabricated by Honeywell and tested in the NASA Glenn 9- by 15-Ft Low Speed Wind Tunnel for aerodynamic, aeromechanical, and acoustic performance.

  14. Common-signal-induced synchronization in photonic integrated circuits and its application to secure key distribution.

    Science.gov (United States)

    Sasaki, Takuma; Kakesu, Izumi; Mitsui, Yusuke; Rontani, Damien; Uchida, Atsushi; Sunada, Satoshi; Yoshimura, Kazuyuki; Inubushi, Masanobu

    2017-10-16

    We experimentally achieve common-signal-induced synchronization in two photonic integrated circuits with short external cavities driven by a constant-amplitude random-phase light. The degree of synchronization can be controlled by changing the optical feedback phase of the two photonic integrated circuits. The change in the optical feedback phase leads to a significant redistribution of the spectral energy of optical and RF spectra, which is a unique characteristic of PICs with the short external cavity. The matching of the RF and optical spectra is necessary to achieve synchronization between the two PICs, and stable synchronization can be obtained over an hour in the presence of optical feedback. We succeed in generating information-theoretic secure keys and achieving the final key generation rate of 184 kb/s using the PICs.

  15. Fully Printed Stretchable Thin-Film Transistors and Integrated Logic Circuits.

    Science.gov (United States)

    Cai, Le; Zhang, Suoming; Miao, Jinshui; Yu, Zhibin; Wang, Chuan

    2016-12-27

    This paper reports intrinsically stretchable thin-film transistors (TFTs) and integrated logic circuits directly printed on elastomeric polydimethylsiloxane (PDMS) substrates. The printed devices utilize carbon nanotubes and a type of hybrid gate dielectric comprising PDMS and barium titanate (BaTiO3) nanoparticles. The BaTiO3/PDMS composite simultaneously provides high dielectric constant, superior stretchability, low leakage, as well as good printability and compatibility with the elastomeric substrate. Both TFTs and logic circuits can be stretched beyond 50% strain along either channel length or channel width directions for thousands of cycles while showing no significant degradation in electrical performance. This work may offer an entry into more sophisticated stretchable electronic systems with monolithically integrated sensors, actuators, and displays, fabricated by scalable and low-cost methods for real life applications.

  16. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  17. Experimental and theoretical analysis of integrated circuit (IC) chips on flexible substrates subjected to bending

    Science.gov (United States)

    Chen, Ying; Yuan, Jianghong; Zhang, Yingchao; Huang, Yonggang; Feng, Xue

    2017-10-01

    The interfacial failure of integrated circuit (IC) chips integrated on flexible substrates under bending deformation has been studied theoretically and experimentally. A compressive buckling test is used to impose the bending deformation onto the interface between the IC chip and the flexible substrate quantitatively, after which the failed interface is investigated using scanning electron microscopy. A theoretical model is established based on the beam theory and a bi-layer interface model, from which an analytical expression of the critical curvature in relation to the interfacial failure is obtained. The relationships between the critical curvature, the material, and the geometric parameters of the device are discussed in detail, providing guidance for future optimization flexible circuits based on IC chips.

  18. High-dimensional quantum key distribution based on multicore fiber using silicon photonic integrated circuits

    DEFF Research Database (Denmark)

    Ding, Yunhong; Bacco, Davide; Dalgaard, Kjeld

    2017-01-01

    -dimensional quantum states, and enables breaking the information efficiency limit of traditional quantum key distribution protocols. In addition, the silicon photonic circuits used in our work integrate variable optical attenuators, highly efficient multicore fiber couplers, and Mach-Zehnder interferometers, enabling......Quantum key distribution provides an efficient means to exchange information in an unconditionally secure way. Historically, quantum key distribution protocols have been based on binary signal formats, such as two polarization states, and the transmitted information efficiency of the quantum key...... is intrinsically limited to 1 bit/photon. Here we propose and experimentally demonstrate, for the first time, a high-dimensional quantum key distribution protocol based on space division multiplexing in multicore fiber using silicon photonic integrated lightwave circuits. We successfully realized three mutually...

  19. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  20. Design and characterization of integrated components for SiN photonic quantum circuits.

    Science.gov (United States)

    Poot, Menno; Schuck, Carsten; Ma, Xiao-Song; Guo, Xiang; Tang, Hong X

    2016-04-04

    The design, fabrication, and detailed calibration of essential building blocks towards fully integrated linear-optics quantum computation are discussed. Photonic devices are made from silicon nitride rib waveguides, where measurements on ring resonators show small propagation losses. Directional couplers are designed to be insensitive to fabrication variations. Their offset and coupling lengths are measured, as well as the phase difference between the transmitted and reflected light. With careful calibrations, the insertion loss of the directional couplers is found to be small. Finally, an integrated controlled-NOT circuit is characterized by measuring the transmission through different combinations of inputs and outputs. The gate fidelity for the CNOT operation with this circuit is estimated to be 99.81% after post selection. This high fidelity is due to our robust design, good fabrication reproducibility, and extensive characterizations.

  1. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  2. Single Molecule Detection Using a Silicon Nanopore-Nanotransistor Integrated Circuit

    Science.gov (United States)

    2006-01-01

    CONTRACT NUMBER Single Molecule Detection Using a Silicon Nanopore-Nanotransistor Integrated Circuit 5b.GRANTNUMBER FA9550-04-1-0214 5c. PROGRAMWELEMENT...electrolyte, and the small pore volume (-20nm 3), D (200mV) we suppose that each of these electrical (i) signatures is indicative of a single molecule 60...polynucleotide. Most of the experimental work using a nanopore W - as a transducer for single molecule detection uses electronics D - K borrowed from

  3. High figure-of-merit SOI power LDMOS for power integrated circuits

    OpenAIRE

    Singh, Yashvir; Rawat, Rahul Singh

    2015-01-01

    The structural modifications in the conventional power laterally diffused metal-oxide-semiconductor field-effect transistor (LDMOS) are carried out to improve the breakdown voltage, on-resistance, gate-charge and figure-of-merits of the device with reduced cell pitch. The modified device has planer structure implemented on silicon-on-insulator which is suitable for low to medium voltage power integrated circuits. The proposed LDMOS consists of two gate electrodes placed vertically in two sepa...

  4. Proposal for combined conducted and radiated emission modelling for Integrated Circuit

    OpenAIRE

    Serpaud, Sébastien; Ghfiri, C.; Boyer, Alexandre; Durier, A

    2017-01-01

    International audience; This paper describes a methodology to build a combined conducted and radiated emission model for integrated circuits. The development of emission models of a FPGA extracted from two different approaches is presented and discussed. The first approach allows to build a predictable model from FPGA implementation and some passive measurement on FPGA device. The second approach allows to build a model from only the near field measurement. In conclusion, the accuracy of both...

  5. Towards synthetic gene circuits with enhancers: biology's multi-input integrators.

    Science.gov (United States)

    Amit, Roee

    2012-01-01

    One of the greatest challenges facing synthetic biology is to develop a technology that allows gene regulatory circuits in microbes to integrate multiple inputs or stimuli using a small DNA sequence "foot-print", and which will generate precise and reproducible outcomes. Achieving this goal is hindered by the routine utilization of the commonplace σ(70) promoters in gene-regulatory circuits. These promoters typically are not capable of integrating binding of more than two or three transcription factors in natural examples, which has limited the field to developing integrated circuits made of two-input biological "logic" gates. In natural examples the regulatory elements, which integrate multiple inputs are called enhancers. These regulatory elements are ubiquitous in all organisms in the tree of life, and interestingly metazoan and bacterial enhancers are significantly more similar in terms of both Transcription Factor binding site arrangement and biological function than previously thought. These similarities imply that there may be underlying enhancer design principles or grammar rules by which one can engineer novel gene regulatory circuits. However, at present our current understanding of enhancer structure-function relationship in all organisms is limited, thus preventing us from using these objects routinely in synthetic biology application. In order to alleviate this problem, in this book chapter, I will review our current view of bacterial enhancers, allowing us to first highlight the potential of enhancers to be a game-changing tool in synthetic biology application, and subsequently to draw a road-map for developing the necessary quantitative understanding to reach this goal.

  6. Integrated genomic and gene expression profiling identifies two major genomic circuits in urothelial carcinoma.

    Directory of Open Access Journals (Sweden)

    David Lindgren

    Full Text Available Similar to other malignancies, urothelial carcinoma (UC is characterized by specific recurrent chromosomal aberrations and gene mutations. However, the interconnection between specific genomic alterations, and how patterns of chromosomal alterations adhere to different molecular subgroups of UC, is less clear. We applied tiling resolution array CGH to 146 cases of UC and identified a number of regions harboring recurrent focal genomic amplifications and deletions. Several potential oncogenes were included in the amplified regions, including known oncogenes like E2F3, CCND1, and CCNE1, as well as new candidate genes, such as SETDB1 (1q21, and BCL2L1 (20q11. We next combined genome profiling with global gene expression, gene mutation, and protein expression data and identified two major genomic circuits operating in urothelial carcinoma. The first circuit was characterized by FGFR3 alterations, overexpression of CCND1, and 9q and CDKN2A deletions. The second circuit was defined by E3F3 amplifications and RB1 deletions, as well as gains of 5p, deletions at PTEN and 2q36, 16q, 20q, and elevated CDKN2A levels. TP53/MDM2 alterations were common for advanced tumors within the two circuits. Our data also suggest a possible RAS/RAF circuit. The tumors with worst prognosis showed a gene expression profile that indicated a keratinized phenotype. Taken together, our integrative approach revealed at least two separate networks of genomic alterations linked to the molecular diversity seen in UC, and that these circuits may reflect distinct pathways of tumor development.

  7. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier

    Directory of Open Access Journals (Sweden)

    De Xing Lioe

    2016-04-01

    Full Text Available A complementary metal-oxide semiconductor (CMOS lock-in pixel to observe stimulated Raman scattering (SRS using a high speed lateral electric field modulator (LEFM for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF and switched-capacitor (SC integrator with a fully CMOS differential amplifier. AC (modulated components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10−5 is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  8. A Stimulated Raman Scattering CMOS Pixel Using a High-Speed Charge Modulator and Lock-in Amplifier.

    Science.gov (United States)

    Lioe, De Xing; Mars, Kamel; Kawahito, Shoji; Yasutomi, Keita; Kagawa, Keiichiro; Yamada, Takahiro; Hashimoto, Mamoru

    2016-04-13

    A complementary metal-oxide semiconductor (CMOS) lock-in pixel to observe stimulated Raman scattering (SRS) using a high speed lateral electric field modulator (LEFM) for photo-generated charges and in-pixel readout circuits is presented. An effective SRS signal generated after the SRS process is very small and needs to be extracted from an extremely large offset due to a probing laser signal. In order to suppress the offset components while amplifying high-frequency modulated small SRS signal components, the lock-in pixel uses a high-speed LEFM for demodulating the SRS signal, resistor-capacitor low-pass filter (RC-LPF) and switched-capacitor (SC) integrator with a fully CMOS differential amplifier. AC (modulated) components remained in the RC-LPF outputs are eliminated by the phase-adjusted sampling with the SC integrator and the demodulated DC (unmodulated) components due to the SRS signal are integrated over many samples in the SC integrator. In order to suppress further the residual offset and the low frequency noise (1/f noise) components, a double modulation technique is introduced in the SRS signal measurements, where the phase of high-frequency modulated laser beam before irradiation of a specimen is modulated at an intermediate frequency and the demodulation is done at the lock-in pixel output. A prototype chip for characterizing the SRS lock-in pixel is implemented and a successful operation is demonstrated. The reduction effects of residual offset and 1/f noise components are confirmed by the measurements. A ratio of the detected small SRS to offset a signal of less than 10(-)⁵ is experimentally demonstrated, and the SRS spectrum of a Benzonitrile sample is successfully observed.

  9. Research on high-speed railway's vibration analysis checking based on intelligent mobile terminal

    Science.gov (United States)

    Li, Peigang; Xie, Shulin; Zhao, Xuefeng

    2017-04-01

    Recently, the development of high-speed railway meets the requirement of society booming and it has gradually become the first choice for long-length journey. Since ensuring the safety and stable operation are of great importance to high-speed trains owing to its unique features, vibration analysis checking is one of main means to be adopted. Due to the popularization of Smartphone, in this research, a novel public-participating method to achieve high-speed railway's vibration analysis checking based on smartphone and an inspection application of high-speed railway line built in the intelligent mobile terminal were proposed. Utilizing the accelerometer, gyroscope, GPS and other high-performance sensors which were integrated in smartphone, the application can obtain multiple parameters like acceleration, angle, etc and pinpoint the location. Therefore, through analyzing the acceleration data in time domain and frequency domain using fast Fourier transform, the research compared much of data from monitoring tests under different measure conditions and measuring points. Furthermore, an idea of establishing a system about analysis checking was outlined in paper. It has been validated that the smartphone-based high-speed railway line inspection system is reliable and feasible on the high-speed railway lines. And it has more advantages, such as convenience, low cost and being widely used. Obviously, the research has important practical significance and broad application prospects.

  10. Water Containment Systems for Testing High-Speed Flywheels

    Science.gov (United States)

    Trase, Larry; Thompson, Dennis

    2006-01-01

    Water-filled containers are used as building blocks in a new generation of containment systems for testing high-speed flywheels. Such containment systems are needed to ensure safety by trapping high-speed debris in the event of centrifugal breakup or bearing failure. Traditional containment systems for testing flywheels consist mainly of thick steel rings. The effectiveness of this approach to shielding against high-speed debris was demonstrated in a series of tests.

  11. Chicago-St. Louis high speed rail plan

    Energy Technology Data Exchange (ETDEWEB)

    Stead, M.E.

    1994-12-31

    The Illinois Department of Transportation (IDOT), in cooperation with Amtrak, undertook the Chicago-St. Louis High Speed Rail Financial and Implementation Plan study in order to develop a realistic and achievable blueprint for implementation of high speed rail in the Chicago-St. Louis corridor. This report presents a summary of the Price Waterhouse Project Team`s analysis and the Financial and Implementation Plan for implementing high speed rail service in the Chicago-St. Louis corridor.

  12. Integrated cascade of photovoltaic cells as a power supply for integrated circuits

    NARCIS (Netherlands)

    Mouthaan, A.J.

    1984-01-01

    ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard

  13. Peak holding circuit for extremely narrow pulses

    Science.gov (United States)

    Oneill, R. W. (Inventor)

    1975-01-01

    An improved pulse stretching circuit comprising: a high speed wide-band amplifier connected in a fast charge integrator configuration; a holding circuit including a capacitor connected in parallel with a discharging network which employs a resistor and an FET; and an output buffer amplifier. Input pulses of very short duration are applied to the integrator charging the capacitor to a value proportional to the input pulse amplitude. After a predetermined period of time, conventional circuitry generates a dump pulse which is applied to the gate of the FET making a low resistance path to ground which discharges the capacitor. When the dump pulse terminates, the circuit is ready to accept another pulse to be stretched. The very short input pulses are thus stretched in width so that they may be analyzed by conventional pulse height analyzers.

  14. Dielectric Spectroscopic Detection of Early Failures in 3-D Integrated Circuits.

    Science.gov (United States)

    Obeng, Yaw; Okoro, C A; Ahn, Jung-Joon; You, Lin; Kopanski, Joseph J

    The commercial introduction of three dimensional integrated circuits (3D-ICs) has been hindered by reliability challenges, such as stress related failures, resistivity changes, and unexplained early failures. In this paper, we discuss a new RF-based metrology, based on dielectric spectroscopy, for detecting and characterizing electrically active defects in fully integrated 3D devices. These defects are traceable to the chemistry of the insolation dielectrics used in the through silicon via (TSV) construction. We show that these defects may be responsible for some of the unexplained early reliability failures observed in TSV enabled 3D devices.

  15. System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation.

    Science.gov (United States)

    Kwon, Hyukjin J; Seok, Seyeong; Lim, Geunbae

    2017-11-18

    Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS) technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

  16. System Modeling of a MEMS Vibratory Gyroscope and Integration to Circuit Simulation

    Directory of Open Access Journals (Sweden)

    Hyukjin J. Kwon

    2017-11-01

    Full Text Available Recently, consumer applications have dramatically created the demand for low-cost and compact gyroscopes. Therefore, on the basis of microelectromechanical systems (MEMS technology, many gyroscopes have been developed and successfully commercialized. A MEMS gyroscope consists of a MEMS device and an electrical circuit for self-oscillation and angular-rate detection. Since the MEMS device and circuit are interactively related, the entire system should be analyzed together to design or test the gyroscope. In this study, a MEMS vibratory gyroscope is analyzed based on the system dynamic modeling; thus, it can be mathematically expressed and integrated into a circuit simulator. A behavioral simulation of the entire system was conducted to prove the self-oscillation and angular-rate detection and to determine the circuit parameters to be optimized. From the simulation, the operating characteristic according to the vacuum pressure and scale factor was obtained, which indicated similar trends compared with those of the experimental results. The simulation method presented in this paper can be generalized to a wide range of MEMS devices.

  17. High-speed rail-coming to America?

    Science.gov (United States)

    Cameron, David Ossian

    2009-01-01

    The United States lags many parts of the world when it comes to high-speed rail. But investing in high-speed rail could help us through current problems. Funds- $8 billion-in the economic stimulus package passed by Congress are designated for high-speed rail. Other funds in the pipeline total approximately $15.5 billion. High-speed rail can relieve congestion, free up national airspace, provide reliable transportation and positive economic development, create jobs, and is more energy efficient than other modes of travel.

  18. The high-speed train and its spatial effects

    OpenAIRE

    Javier Gutiérrez Puebla

    2004-01-01

    This paper analyses the high-speed train from a spatial point of view. The basic characteristics of this transportation mode,the evolution of high-speed networks in several countries and the building of a trans-European high-speed railway network are studied.The paper analyses also the process of space-time convergence and its consequences on competitivity and cohesion;the tunel effect;the impact of the high speed-train on transportation demand;and the impacts on the city.

  19. Comparison of a new integrated current source with the modified Howland circuit for EIT applications.

    Science.gov (United States)

    Hong, Hongwei; Rahal, Mohamad; Demosthenous, Andreas; Bayford, Richard H

    2009-10-01

    Multi-frequency electrical impedance tomography (MF-EIT) systems require current sources that are accurate over a wide frequency range (1 MHz) and with large load impedance variations. The most commonly employed current source design in EIT systems is the modified Howland circuit (MHC). The MHC requires tight matching of resistors to achieve high output impedance and may suffer from instability over a wide frequency range in an integrated solution. In this paper, we introduce a new integrated current source design in CMOS technology and compare its performance with the MHC. The new integrated design has advantages over the MHC in terms of power consumption and area. The output current and the output impedance of both circuits were determined through simulations and measurements over the frequency range of 10 kHz to 1 MHz. For frequencies up to 1 MHz, the measured maximum variation of the output current for the integrated current source is 0.8% whereas for the MHC the corresponding value is 1.5%. Although the integrated current source has an output impedance greater than 1 MOmega up to 1 MHz in simulations, in practice, the impedance is greater than 160 kOmega up to 1 MHz due to the presence of stray capacitance.

  20. Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

    Science.gov (United States)

    Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

    2010-02-21

    Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

  1. Nanocomposites for high-speed optical modulators and plasmonic thermal mid-infrared emitters

    Science.gov (United States)

    Demir, Veysi

    Demand for high-speed optical modulators and narrow-bandwidth infrared thermal emitters for numerous applications continues to rise and new optical devices are needed to deal with massive data flows, processing powers, and fabrication costs. Conventional techniques are usually hindered by material limitations or electronic interconnects and advances in organic nanocomposite materials and their integration into photonic integrated circuits (PICs) have been acknowledged as a promising alternative to single crystal techniques. The work presented in this thesis uses plasmonic and magneto-optic effects towards the development of novel optical devices for harnessing light and generating high bandwidth signals (>40GHz) at room and cryogenic temperatures (4.2°K). Several publications have resulted from these efforts and are listed at the end of the abstract. In our first published research we developed a narrow-bandwidth mid-infrared thermal emitter using an Ag/dielectric/Ag thin film structure arranged in hexagonal planar lattice structures. PECVD produced nanoamorphous carbon (NAC) is used as a dielectric layer. Spectrally tunable (>2 mum) and narrow bandwidth (resistivity of NAC from 1012 and 109 O.cm with an MoSi2 dopant and increasing the emitter lattice constant from 4 to 7 mum. This technique offers excellent flexibility for developing cost-effective mid-IR sources as compared to costly fiber and quantum cascade lasers (QCLs). Next, the effect of temperature on the Verdet constant for cobalt-ferrite polymer nanocomposites was measured for a series of temperatures ranging from 40 to 200°K with a Faraday rotation polarimeter. No visual change was observed in the films during thermal cycling, and ˜4x improvement was achieved at 40°K. The results are promising and further analysis is merited at 4.2°K to assess the performance of this material for cryogenic magneto-optic modulators for supercomputers. Finally, the dielectric constant and loss tangent of MAPTMS sol

  2. Giga bit per second Differential Scheme for High Speed Interconnect

    OpenAIRE

    Mandeep Singh Narula; Pankaj Rakheja; Charu Rana

    2012-01-01

    The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth ...

  3. Ultrafast, high precision gated integrator

    Energy Technology Data Exchange (ETDEWEB)

    Wang, X.

    1995-01-01

    An ultrafast, high precision gated integrator has been developed by introducing new design approaches that overcome the problems associated with earlier gated integrator circuits. The very high speed is evidenced by the output settling time of less than 50 ns and 20 MHz input pulse rate. The very high precision is demonstrated by the total output offset error of less than 0.2mV and the output droop rate of less than 10{mu}V/{mu}s. This paper describes the theory of this new gated integrator circuit operation. The completed circuit test results are presented.

  4. SEMICONDUCTOR INTEGRATED CIRCUITS: Design and research of an LED driving circuit with accurate proportional current sampling mode

    Science.gov (United States)

    Wei, Guo; Xing, Yang; Dazhong, Zhu

    2010-04-01

    An LED driving circuit in accurate proportional current sampling mode is designed and fabricated based on CSMC 0.5 μm standard CMOS technology. It realizes accurate sensing of sampling current variation with output driving current. A better constant output current characteristic is achieved by using an amplifier to clamp the drain voltage of both the sampling MOSFET and power MOSFET to the same value with feedback control. Small signal equivalent circuit analysis shows that the small signal output resistance in the accurate proportional current sampling mode circuit is much larger than that in a traditional proportional current sampling mode circuit, and circuit stability could be assured. Circuit simulation and chip testing results show that when the LED driving current is 350 mA and the power supply is 6 V with ±10% variation, the stability of the output constant current of the accurate proportional current sampling mode LED driving IC will show 41% improvement over that of a traditional proportional current sampling mode LED driving IC.

  5. The functional significance of newly born neurons integrated into olfactory bulb circuits

    Directory of Open Access Journals (Sweden)

    Masayuki eSakamoto

    2014-05-01

    Full Text Available The olfactory bulb (OB is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  6. 6H-SiC Transistor Integrated Circuits Demonstrating Prolonged Operation at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith, Roger; Ferrier, Terry; Krasowski, Michael J.; hide

    2008-01-01

    The NASA Glenn Research Center is developing very high temperature semiconductor integrated circuits (ICs) for use in the hot sections of aircraft engines and for Venus exploration where ambient temperatures are well above the approximately 300 degrees Centigrade effective limit of silicon-on-insulator IC technology. In order for beneficial technology insertion to occur, such transistor ICs must be capable of prolonged operation in such harsh environments. This paper reports on the fabrication and long-term 500 degrees Centigrade operation of 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). Simple analog amplifier and digital logic gate ICs have now demonstrated thousands of hours of continuous 500 degrees Centigrade operation in oxidizing air atmosphere with minimal changes in relevant electrical parameters. Electrical characterization and modeling of transistors and circuits at temperatures from 24 degrees Centigrade to 500 degrees Centigrade is also described. Desired analog and digital IC functionality spanning this temperature range was demonstrated without changing the input signals or power supply voltages.

  7. A contact lens with integrated telecommunication circuit and sensors for wireless and continuous tear glucose monitoring

    Science.gov (United States)

    Yao, H.; Liao, Y.; Lingley, A. R.; Afanasiev, A.; Lähdesmäki, I.; Otis, B. P.; Parviz, B. A.

    2012-07-01

    We present an integrated functional contact lens, composed of a differential glucose sensor module, metal interconnects, sensor read-out circuit, antenna and telecommunication circuit, to monitor tear glucose levels wirelessly, continuously and non-invasively. The electrochemical differential sensor module is based on immobilization of activated and de-activated glucose oxidase. We characterized the sensor on a model polymer eye and determined that it showed good repeatability, molecular interference rejection and linearity in the range of 0-2 mM glucose, covering normal tear glucose concentrations (0.1-0.6 mM). We also report the temperature, ageing and protein-fouling sensitivity of the sensor. We report the design and implementation of a low-power (3 µW) sensor read-out and telecommunication circuit to deliver wireless power and transmit data for the sensor module. Using this small chip (0.36 mm2), we produced an integrated contact lens with sensors and demonstrated wireless operation of the system and glucose read-out over the distance of several centimeters.

  8. The functional significance of newly born neurons integrated into olfactory bulb circuits.

    Science.gov (United States)

    Sakamoto, Masayuki; Kageyama, Ryoichiro; Imayoshi, Itaru

    2014-01-01

    The olfactory bulb (OB) is the first central processing center for olfactory information connecting with higher areas in the brain, and this neuronal circuitry mediates a variety of odor-evoked behavioral responses. In the adult mammalian brain, continuous neurogenesis occurs in two restricted regions, the subventricular zone (SVZ) of the lateral ventricle and the hippocampal dentate gyrus. New neurons born in the SVZ migrate through the rostral migratory stream and are integrated into the neuronal circuits of the OB throughout life. The significance of this continuous supply of new neurons in the OB has been implicated in plasticity and memory regulation. Two decades of huge investigation in adult neurogenesis revealed the biological importance of integration of new neurons into the olfactory circuits. In this review, we highlight the recent findings about the physiological functions of newly generated neurons in rodent OB circuits and then discuss the contribution of neurogenesis in the brain function. Finally, we introduce cutting edge technologies to monitor and manipulate the activity of new neurons.

  9. Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

    Science.gov (United States)

    Penchovsky, Robert

    2012-10-19

    Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

  10. PCSIM: A Parallel Simulation Environment for Neural Circuits Fully Integrated with Python

    Science.gov (United States)

    Pecevski, Dejan; Natschläger, Thomas; Schuch, Klaus

    2008-01-01

    The Parallel Circuit SIMulator (PCSIM) is a software package for simulation of neural circuits. It is primarily designed for distributed simulation of large scale networks of spiking point neurons. Although its computational core is written in C++, PCSIM's primary interface is implemented in the Python programming language, which is a powerful programming environment and allows the user to easily integrate the neural circuit simulator with data analysis and visualization tools to manage the full neural modeling life cycle. The main focus of this paper is to describe PCSIM's full integration into Python and the benefits thereof. In particular we will investigate how the automatically generated bidirectional interface and PCSIM's object-oriented modular framework enable the user to adopt a hybrid modeling approach: using and extending PCSIM's functionality either employing pure Python or C++ and thus combining the advantages of both worlds. Furthermore, we describe several supplementary PCSIM packages written in pure Python and tailored towards setting up and analyzing neural simulations. PMID:19543450

  11. Structure of the EGF receptor transactivation circuit integrates multiple signals with cell context

    Energy Technology Data Exchange (ETDEWEB)

    Joslin, Elizabeth J.; Shankaran, Harish; Opresko, Lee K.; Bollinger, Nikki; Lauffenburger, Douglas A.; Wiley, H. S.

    2010-05-10

    Transactivation of the epidermal growth factor receptor (EGFR) has been proposed to be a mechanism by which a variety of cellular inputs can be integrated into a single signaling pathway, but the regulatory topology of this important system is unclear. To understand the transactivation circuit, we first created a “non-binding” reporter for ligand shedding. We then quantitatively defined how signals from multiple agonists were integrated both upstream and downstream of the EGFR into the extracellular signal regulated kinase (ERK) cascade in human mammary epithelial cells. We found that transactivation is mediated by a recursive autocrine circuit where ligand shedding drives EGFR-stimulated ERK that in turn drives further ligand shedding. The time from shedding to ERK activation is fast (<5 min) whereas the recursive feedback is slow (>15 min). Simulations showed that this delay in positive feedback greatly enhanced system stability and robustness. Our results indicate that the transactivation circuit is constructed so that the magnitude of ERK signaling is governed by the sum of multiple direct inputs, while recursive, autocrine ligand shedding controls signal duration.

  12. Integrated cascade of photovoltaic cells as a power supply for integrated circuits

    OpenAIRE

    Mouthaan, A.J.

    1984-01-01

    ICs can be powered directly when a supply voltage source capable of generating a multiple of the open circuit voltage of one pn-junction is available on a chip. Two schemes have been investigated for cascading photovoltaic cells on the chip. The structures can be made compatible with standard bipolar processes. Deep ion implantations have been used here to realize the multiple-junction structure. Power losses due to photocurrents originating from insulation junctions in the cascade can be kep...

  13. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  14. MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

    Science.gov (United States)

    Jang, Munseon; Yun, Kwang-Seok

    2017-12-01

    In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

  15. A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

    Directory of Open Access Journals (Sweden)

    Chyan-Chyi Wu

    2011-11-01

    Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

  16. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  17. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-01

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits. PMID:24463956

  18. Long-Term Characterization of 6H-SiC Transistor Integrated Circuit Technology Operating at 500 C

    Science.gov (United States)

    Neudeck, Philip G.; Spry, David J.; Chen, Liang-Yu; Chang, Carl W.; Beheim, Glenn M.; Okojie, Robert S.; Evans, Laura J.; Meredith Roger D.; Ferrier, Terry L.; Krasowski, Michael J.; hide

    2008-01-01

    NASA has been developing very high temperature semiconductor integrated circuits for use in the hot sections of aircraft engines and for Venus exploration. This paper reports on long-term 500 C electrical operation of prototype 6H-SiC integrated circuits based on epitaxial 6H-SiC junction field effect transistors (JFETs). As of this writing, some devices have surpassed 4000 hours of continuous 500 C electrical operation in oxidizing air atmosphere with minimal change in relevant electrical parameters.

  19. SPICE Simulations of single event transients in bipolar analog integrated circuits using public information and free open source tools

    OpenAIRE

    Franco Peláez, Francisco Javier; Palomar Trives, Carlos; González Izquierdo, Jesús; Agapito Serrano, Juan Andrés

    2015-01-01

    This paper proposes a technique to build SPICE micromodels of integrated circuits in bipolar technology appropriate to simulate single event transients. First of all, we will show how to obtain SPICE models of the internal transistors from texts in the scientific and academic literature. Next, several strategies to figure out the internal structure of the integrated circuits and bias point will be shown. Finally, simulation results will be compared to data issue from experiments, either perfo...

  20. Design and implementation of Gm-APD array readout integrated circuit for infrared 3D imaging

    Science.gov (United States)

    Zheng, Li-xia; Yang, Jun-hao; Liu, Zhao; Dong, Huai-peng; Wu, Jin; Sun, Wei-feng

    2013-09-01

    A single-photon detecting array of readout integrated circuit (ROIC) capable of infrared 3D imaging by photon detection and time-of-flight measurement is presented in this paper. The InGaAs avalanche photon diodes (APD) dynamic biased under Geiger operation mode by gate controlled active quenching circuit (AQC) are used here. The time-of-flight is accurately measured by a high accurate time-to-digital converter (TDC) integrated in the ROIC. For 3D imaging, frame rate controlling technique is utilized to the pixel's detection, so that the APD related to each pixel should be controlled by individual AQC to sense and quench the avalanche current, providing a digital CMOS-compatible voltage pulse. After each first sense, the detector is reset to wait for next frame operation. We employ counters of a two-segmental coarse-fine architecture, where the coarse conversion is achieved by a 10-bit pseudo-random linear feedback shift register (LFSR) in each pixel and a 3-bit fine conversion is realized by a ring delay line shared by all pixels. The reference clock driving the LFSR counter can be generated within the ring delay line Oscillator or provided by an external clock source. The circuit is designed and implemented by CSMC 0.5μm standard CMOS technology and the total chip area is around 2mm×2mm for 8×8 format ROIC with 150μm pixel pitch. The simulation results indicate that the relative time resolution of the proposed ROIC can achieve less than 1ns, and the preliminary test results show that the circuit function is correct.

  1. Cleveland-Columbus-Cincinnati high-speed rail study

    Science.gov (United States)

    2001-07-01

    In the past five years, the evaluation of different high-speed rail (HSR) studies in the Midwest has resulted in a realization that high speed rail, with speeds greater than 110 miles per hour, is too expensive in the short term to be implemented in ...

  2. Florida High Speed Rail Authority - 2003 report to the legislature

    Science.gov (United States)

    2003-01-01

    Since its last full report to the Legislature in January 2002, the Florida High Speed Rail Authority (FHSRA) has continued to fulfill the duties defined in the Florida High Speed Rail Authority Act, Section 341.8201 to 341.842, Florida Statutes. The ...

  3. Advancing high-speed rail policy in the United States.

    Science.gov (United States)

    2012-06-01

    This report builds on a review of international experience with high-speed rail projects to develop recommendations for a High-speed rail policy framework for the United States. The international review looked at the experience of Korea, Taiwan, Chin...

  4. Optical Systems for Ultra-High-Speed TDM Networking

    DEFF Research Database (Denmark)

    Galili, Michael; Hu, Hao; Mulvad, Hans Christian Hansen

    2014-01-01

    This paper discusses key results in the field of high speed optical networking with particular focus on packet-based systems. Schemes for optical packet labeling, packet switching and packet synchronization will be discussed, along with schemes for optical clock recovery, channel identification...... and detection of ultra-high-speed optical signals....

  5. Optical Systems for Ultra-High-Speed TDM Networking

    Directory of Open Access Journals (Sweden)

    Michael Galili

    2014-04-01

    Full Text Available This paper discusses key results in the field of high speed optical networking with particular focus on packet-based systems. Schemes for optical packet labeling, packet switching and packet synchronization will be discussed, along with schemes for optical clock recovery, channel identification and detection of ultra-high-speed optical signals.

  6. 14 CFR 23.253 - High speed characteristics.

    Science.gov (United States)

    2010-01-01

    ... 14 Aeronautics and Space 1 2010-01-01 2010-01-01 false High speed characteristics. 23.253 Section... Requirements § 23.253 High speed characteristics. If a maximum operating speed VMO/MMO is established under § 23.1505(c), the following speed increase and recovery characteristics must be met: (a) Operating...

  7. High-Speed, High-Resolution Time-to-Digital Conversion

    Science.gov (United States)

    Katz, Richard; Kleyner, Igor; Garcia, Rafael

    2013-01-01

    This innovation is a series of time-tag pulses from a photomultiplier tube, featuring short time interval between pulses (e.g., 2.5 ns). Using the previous art, dead time between pulses is too long, or too much hardware is required, including a very-high-speed demultiplexer. A faster method is needed. The goal of this work is to provide circuits to time-tag pulses that arrive at a high rate using the hardwired logic in an FPGA - specifically the carry chain - to create what is (in effect) an analog delay line. High-speed pulses travel down the chain in a "wave." For instance, a pulse train has been demonstrated from a 1- GHz source reliably traveling down the carry chain. The size of the carry chain is over 10 ns in the time domain. Thus, multiple pulses will travel down the carry chain in a wave simultaneously. A register clocked by a low-skew clock takes a "snapshot" of the wave. Relatively simple logic can extract the pulses from the snapshot picture by detecting the transitions between logic states. The propagation delay of CMOS (complementary metal oxide semiconductor) logic circuits will differ and/or change as a result of temperature, voltage, age, radiation, and manufacturing variances. The time-to-digital conversion circuits can be calibrated with test signals, or the changes can be nulled by a separate on-die calibration channel, in a closed loop circuit.

  8. High-Speed Automated Tester for Vacuum Chamber Feedthrough Connectors and Cables

    Science.gov (United States)

    Swope, Robert H.; Powers, Edward I. (Technical Monitor)

    2000-01-01

    The Goddard Space Flight Center's thermal vacuum laboratory has developed a high-speed automated system for testing the integrity of 37-pin MIL-C-5015 cylindrical electrical feedthrough connectors used on penetration plates of thermal vacuum chambers. The system consists of a desktop PC driving a data acquisition front end. The latter measures the resistance through each pin of the connector and the resistance from each pin to all other pins and the connector shell. In addition to identifying unacceptable feedthroughs, the system is also used for testing cables. In the special case of Type T thermocouples (used almost exclusively at the lab), the difference in resistance between the copper and constantan wires provides positive proof of accidentally reversed connector wiring. Data acquisition time to completely test a cable or feedthrough connector is less than thirty seconds. The system provides a hardcopy printout of the resistance readings. Connectors or cables with fewer wires are tested using simple adapter cables. Initial tests indicate that the performance of a given feedthrough connector can be predicted on the basis of measured resistance readings, reducing ongoing cost of connector replacement. The opportunity to positively certify the integrity of cables, cable connectors and feedthroughs before the start of a thermal vacuum test minimizes the likelihood of a circuit problem that would require returning the chamber to ambient conditions for repair. This system has two principal advantages for the Goddard thermal vacuum laboratory. Its only significant cost was the labor to fabricate the test cable and shorting cable -- about 40 man-hours total. The system was built around a computer and data acquisition unit that were already on hand. The second advantage is that it very quickly tests both of the parameters that are essential.

  9. An Integrated Circuit for Signal Processing of the AMS RICH Photmultipliers Tubes

    CERN Document Server

    Barrau, A; Pouxe, J; Rossetto, O

    1998-01-01

    An analog integrated circuit has been designed, in a BiCMOS 0.8 micron technology, for the feasability study of the signal processing of the AMS RICH photomultiplier tubes. This low power, three channel gated integrator includes its own gate and no external analog delay is requiered. It processes PMT pulses over a dynamic range of more than 100. A logic output that indicates whether the analog charge has to be considered is provided. This gated integrator is used with a compact DSP based acquisition system in a 132 channels RICH prototype. The charge calibration of each channel is carried out using a LED. The pedestal measurement is performed on activation of a dedicated input. The noise contribution study of the input RC network and amplifiers is presented.

  10. Optical interconnects for in-plane high-speed signal distribution at 10 Gb/s: Analysis and demonstration

    Science.gov (United States)

    Chang, Yin-Jung

    With decreasing transistor size, increasing chip speed, and larger numbers of processors in a system, the performance of a module/system is being limited by the off-chip and off-module bandwidth-distance products. Optical links have moved from fiber-based long distance communications to the cabinet level of 1m--100m, and recently to the backplane-level (10cm--1m). Board-level inter-chip parallel optical interconnects have been demonstrated recently by researchers from Intel, IBM, Fujitsu, NTT and a few research groups in universities. However, the board-level signal/clock distribution function using optical interconnects, the lightwave circuits, the system design, a practically convenient integration scheme committed to the implementation of a system prototype have not been explored or carefully investigated. In this dissertation, the development of a board-level 1 x 4 optical-to-electrical signal distribution at 10Gb/s is presented. In contrast to other prototypes demonstrating board-level parallel optical interconnects that have been drawing much attention for the past decade, the optical link design for the high-speed signal broadcasting is even more complicated and the pitch between receivers could be varying as opposed to fixed-pitch design that has been widely-used in the parallel optical interconnects. New challenges for the board-level high-speed signal broadcasting include, but are not limited to, a new optical link design, a lightwave circuit as a distribution network, and a novel integration scheme that can be a complete radical departure from the traditional assembly method. One of the key building blocks in the lightwave circuit is the distribution network in which a 1 x 4 multimode interference (MMI) splitter is employed. MMI devices operating at high data rates are important in board-level optical interconnects and need to be characterized in the application of board-level signal broadcasting. To determine the speed limitations of MMI devices, the

  11. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  12. Impact of a high-speed train of microdrops on a liquid pool

    NARCIS (Netherlands)

    Bouwhuis, W.; Huang, X; Chan, C.U.; Frommhold, P.E.; Ohl, C.D.; Lohse, Detlef; Snoeijer, Jacobus Hendrikus; van der Meer, Roger M.

    2016-01-01

    A train of high-speed microdrops impacting on a liquid pool can create a very deep and narrow cavity, reaching depths more than 1000 times the size of the individual drops. The impact of such a droplet train is studied numerically using boundary integral simulations. In these simulations, we solve

  13. High-speed Internet Use and Academic Gratifications in the College Residence.

    Science.gov (United States)

    Matthews, Denise; Schrum, Lynne

    2003-01-01

    A multimethod exploration of undergraduates' high-speed Internet use in residence halls took a uses-and-gratifications approach and revealed Internet use as integral to students' lives. Students' negative comments about Internet distractions from academic work led to identification of an individual difference variable, internal locus of control of…

  14. Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

    Science.gov (United States)

    Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

    2017-10-13

    Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

  15. Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits

    Science.gov (United States)

    Ker, Ming-Dou; Hsiao, Yuan-Wen

    An impedance-isolation technique is proposed for on-chip ESD protection design for radio-frequency (RF) integrated circuits (ICs), which has been successfully verified in a 0.25-µm CMOS process with thick top-layer metal. With the resonance of LC-tank at the operating frequency of the RF circuit, the impedance (especially, the parasitic capacitance) of the ESD protection devices can be isolated from the RF input node of low-noise amplifier (LNA). Therefore, the LNA can be co-designed with the proposed impedance-isolation technique to simultaneously achieve excellent RF performance and high ESD robustness. The power gain (S21-parameter) and noise figure of the ESD protection circuits with the proposed impedance-isolation technique have been experimentally measured and compared to those with the conventional double-diodes ESD protection scheme. The proposed impedance-isolation technique had been demonstrated to be suitable for on-chip ESD protection design for RF ICs.

  16. Modeling for infrared readout integrated circuit based on Verilog-A

    Science.gov (United States)

    Wang, Xiao; Shi, Zelin

    2015-04-01

    Infrared detectors are the core of infrared imaging systems, while readout integrated circuits are the key components of detectors. In order to grasp the performance of circuits quickly and accurately, a method of circuit modeling using Verilog-A language is proposed, which present a behavioral simulation model for the ROIC. At first, a typical capacitor trans-impedance amplifier(CTIA) ROIC unit is showed, then the two essential parts of it,operational amplifier and switch are modeled on behavioral level. The op amp model concludes these non-ideal factors, such as finite gain-bandwidth product, input and output offset, output resistance and so on. Non-deal factors that affect switches are considered in the switch behavioral model, such as rise and fall time, on-resistance and so on. At last time-domain modeling method for noise is presented, which is compared with the classical frequency domain method for difference. The analysis results shows that in the situation that noise interested bandwidth(NIBW) is more than 5MHz, the difference between the two methods leads to less than 1% if the sample rate of noise is larger 4 times of the NIBW

  17. Microfluidic pneumatic logic circuits and digital pneumatic microprocessors for integrated microfluidic systems.

    Science.gov (United States)

    Rhee, Minsoung; Burns, Mark A

    2009-11-07

    We have developed pneumatic logic circuits and microprocessors built with microfluidic channels and valves in polydimethylsiloxane (PDMS). The pneumatic logic circuits perform various combinational and sequential logic calculations with binary pneumatic signals (atmosphere and vacuum), producing cascadable outputs based on Boolean operations. A complex microprocessor is constructed from combinations of various logic circuits and receives pneumatically encoded serial commands at a single input line. The device then decodes the temporal command sequence by spatial parallelization, computes necessary logic calculations between parallelized command bits, stores command information for signal transportation and maintenance, and finally executes the command for the target devices. Thus, such pneumatic microprocessors will function as a universal on-chip control platform to perform complex parallel operations for large-scale integrated microfluidic devices. To demonstrate the working principles, we have built 2-bit, 3-bit, 4-bit, and 8-bit microprocessors to control various target devices for applications such as four color dye mixing, and multiplexed channel fluidic control. By significantly reducing the need for external controllers, the digital pneumatic microprocessor can be used as a universal on-chip platform to autonomously manipulate microfluids in a high throughput manner.

  18. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Science.gov (United States)

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  19. Multifunctional and multi-output plasmonic meta-elements for integrated optical circuits.

    Science.gov (United States)

    Wang, Jiayuan; Hu, Chuang; Zhang, Jiasen

    2014-09-22

    Based on a novel phase-sieve method by in-plane interference processes, a well-designed nonperiodic nanogroove array on gold surface is proposed as a multifunctional and multi-output plasmonic meta-element (MPM) for surface plasmon polariton waves. An MPM functions as a plasmonic lens (PL) as well as a plasmonic array illuminator (PAI), and another MPM acts as two PLs with an intersection angle of π/4 are fabricated and validated by leakage radiation microscopy measurements. Our proposed scheme with implemented functionalities could promote potential applications in high density integrated optical circuits.

  20. Laser attacks on integrated circuits: from CMOS to FD-SOI

    OpenAIRE

    Dutertre, Jean-Max; De Castro, Stephan; Sarafianos, Alexandre; Boher, Noémie; Rouzeyre, Bruno; Lisart, Mathieu; Damiens, Joel; Candelier, Philippe; Flottes, Marie-Lise; Di Natale, Giorgio

    2014-01-01

    International audience; The use of a laser as a means to inject errors during the computations of a secure integrated circuit (IC) for the purpose of retrieving secret data was first reported in 2002. Since then, a lot of research work, mainly experimental, has been carried out to study this threat. This paper reports research conducted, in the framework of the french national project LIESSE, to obtain an electrical model of the laser effects on CMOS ICs. Based on simulation, a first model pe...