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Sample records for high-k gate stacks

  1. Low-power DRAM-compatible Replacement Gate High-k/Metal Gate Stacks

    Science.gov (United States)

    Ritzenthaler, R.; Schram, T.; Bury, E.; Spessot, A.; Caillat, C.; Srividya, V.; Sebaai, F.; Mitard, J.; Ragnarsson, L.-Å.; Groeseneken, G.; Horiguchi, N.; Fazan, P.; Thean, A.

    2013-06-01

    In this work, the possibility of integration of High-k/Metal Gate (HKMG), Replacement Metal Gate (RMG) gate stacks for low power DRAM compatible transistors is studied. First, it is shown that RMG gate stacks used for Logic applications need to be seriously reconsidered, because of the additional anneal(s) needed in a DRAM process. New solutions are therefore developed. A PMOS stack HfO2/TiN with TiN deposited in three times combined with Work Function metal oxidations is demonstrated, featuring a very good Work Function of 4.95 eV. On the other hand, the NMOS side is shown to be a thornier problem to solve: a new solution based on the use of oxidized Ta as a diffusion barrier is proposed, and a HfO2/TiN/TaOX/TiAl/TiN/TiN gate stack featuring an aggressive Work Function of 4.35 eV (allowing a Work Function separation of 600 mV between NMOS and PMOS) is demonstrated. This work paves the way toward the integration of gate-last options for DRAM periphery transistors.

  2. Electronic States of High-k Oxides in Gate Stack Structures

    Science.gov (United States)

    Zhu, Chiyu

    In this dissertation, in-situ X-ray and ultraviolet photoemission spectroscopy have been employed to study the interface chemistry and electronic structure of potential high-k gate stack materials. In these gate stack materials, HfO2 and La2O3 are selected as high-k dielectrics, VO2 and ZnO serve as potential channel layer materials. The gate stack structures have been prepared using a reactive electron beam system and a plasma enhanced atomic layer deposition system. Three interrelated issues represent the central themes of the research: 1) the interface band alignment, 2) candidate high-k materials, and 3) band bending, internal electric fields, and charge transfer. 1) The most highlighted issue is the band alignment of specific high-k structures. Band alignment relationships were deduced by analysis of XPS and UPS spectra for three different structures: a) HfO2/VO2/SiO2/Si, b) HfO 2-La2O3/ZnO/SiO2/Si, and c) HfO 2/VO2/ HfO2/SiO2/Si. The valence band offset of HfO2/VO2, ZnO/SiO2 and HfO 2/SiO2 are determined to be 3.4 +/- 0.1, 1.5 +/- 0.1, and 0.7 +/- 0.1 eV. The valence band offset between HfO2-La2O3 and ZnO was almost negligible. Two band alignment models, the electron affinity model and the charge neutrality level model, are discussed. The results show the charge neutrality model is preferred to describe these structures. 2) High-k candidate materials were studied through comparison of pure Hf oxide, pure La oxide, and alloyed Hf-La oxide films. An issue with the application of pure HfO2 is crystallization which may increase the leakage current in gate stack structures. An issue with the application of pure La2O3 is the presence of carbon contamination in the film. Our study shows that the alloyed Hf-La oxide films exhibit an amorphous structure along with reduced carbon contamination. 3) Band bending and internal electric fields in the gate stack structure were observed by XPS and UPS and indicate the charge transfer during the growth and process. The oxygen

  3. Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

    2015-08-15

    Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

  4. Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

    International Nuclear Information System (INIS)

    Zhang ShuXiang; Yang Hong; Tang Bo; Tang Zhaoyun; Xu Yefeng; Xu Jing; Yan Jiang

    2014-01-01

    ALD HfO 2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D and A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D and A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme. (semiconductor technology)

  5. 2-D modeling and analysis of short-channel behavior of a front high- K gate stack triple-material gate SB SON MOSFET

    Science.gov (United States)

    Banerjee, Pritha; Kumari, Tripty; Sarkar, Subir Kumar

    2018-02-01

    This paper presents the 2-D analytical modeling of a front high- K gate stack triple-material gate Schottky Barrier Silicon-On-Nothing MOSFET. Using the two-dimensional Poisson's equation and considering the popular parabolic potential approximation, expression for surface potential as well as the electric field has been considered. In addition, the response of the proposed device towards aggressive downscaling, that is, its extent of immunity towards the different short-channel effects, has also been considered in this work. The analytical results obtained have been validated using the simulated results obtained using ATLAS, a two-dimensional device simulator from SILVACO.

  6. Comprehensive study and design of scaled metal/high-k/Ge gate stacks with ultrathin aluminum oxide interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Asahara, Ryohei; Hideshima, Iori; Oka, Hiroshi; Minoura, Yuya; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi; Watanabe, Heiji [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Ogawa, Shingo [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Toray Research Center Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan); Yoshigoe, Akitaka; Teraoka, Yuden [Japan Atomic Energy Agency, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan)

    2015-06-08

    Advanced metal/high-k/Ge gate stacks with a sub-nm equivalent oxide thickness (EOT) and improved interface properties were demonstrated by controlling interface reactions using ultrathin aluminum oxide (AlO{sub x}) interlayers. A step-by-step in situ procedure by deposition of AlO{sub x} and hafnium oxide (HfO{sub x}) layers on Ge and subsequent plasma oxidation was conducted to fabricate Pt/HfO{sub 2}/AlO{sub x}/GeO{sub x}/Ge stacked structures. Comprehensive study by means of physical and electrical characterizations revealed distinct impacts of AlO{sub x} interlayers, plasma oxidation, and metal electrodes serving as capping layers on EOT scaling, improved interface quality, and thermal stability of the stacks. Aggressive EOT scaling down to 0.56 nm and very low interface state density of 2.4 × 10{sup 11 }cm{sup −2}eV{sup −1} with a sub-nm EOT and sufficient thermal stability were achieved by systematic process optimization.

  7. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    Science.gov (United States)

    Chaowen, Liu; Jingping, Xu; Lu, Liu; Hanhan, Lu; Yuan, Huang

    2016-02-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. Project supported by the National Natural Science Foundation of China (No. 61176100).

  8. A threshold-voltage model for small-scaled GaAs nMOSFET with stacked high-k gate dielectric

    International Nuclear Information System (INIS)

    Liu Chaowen; Xu Jingping; Liu Lu; Lu Hanhan; Huang Yuan

    2016-01-01

    A threshold-voltage model for a stacked high-k gate dielectric GaAs MOSFET is established by solving a two-dimensional Poisson's equation in channel and considering the short-channel, DIBL and quantum effects. The simulated results are in good agreement with the Silvaco TCAD data, confirming the correctness and validity of the model. Using the model, impacts of structural and physical parameters of the stack high-k gate dielectric on the threshold-voltage shift and the temperature characteristics of the threshold voltage are investigated. The results show that the stacked gate dielectric structure can effectively suppress the fringing-field and DIBL effects and improve the threshold and temperature characteristics, and on the other hand, the influence of temperature on the threshold voltage is overestimated if the quantum effect is ignored. (paper)

  9. High-performance III-V MOSFET with nano-stacked high-k gate dielectric and 3D fin-shaped structure.

    Science.gov (United States)

    Chen, Szu-Hung; Liao, Wen-Shiang; Yang, Hsin-Chia; Wang, Shea-Jue; Liaw, Yue-Gie; Wang, Hao; Gu, Haoshuang; Wang, Mu-Chun

    2012-08-01

    A three-dimensional (3D) fin-shaped field-effect transistor structure based on III-V metal-oxide-semiconductor field-effect transistor (MOSFET) fabrication has been demonstrated using a submicron GaAs fin as the high-mobility channel. The fin-shaped channel has a thickness-to-width ratio (TFin/WFin) equal to 1. The nano-stacked high-k Al2O3 dielectric was adopted as a gate insulator in forming a metal-oxide-semiconductor structure to suppress gate leakage. The 3D III-V MOSFET exhibits outstanding gate controllability and shows a high Ion/Ioff ratio > 105 and a low subthreshold swing of 80 mV/decade. Compared to a conventional Schottky gate metal-semiconductor field-effect transistor or planar III-V MOSFETs, the III-V MOSFET in this work exhibits a significant performance improvement and is promising for future development of high-performance n-channel devices based on III-V materials.

  10. Effects of Gate Stack Structural and Process Defectivity on High-k Dielectric Dependence of NBTI Reliability in 32 nm Technology Node PMOSFETs

    Directory of Open Access Journals (Sweden)

    H. Hussin

    2014-01-01

    Full Text Available We present a simulation study on negative bias temperature instability (NBTI induced hole trapping in E′ center defects, which leads to depassivation of interface trap precursor in different geometrical structures of high-k PMOSFET gate stacks using the two-stage NBTI model. The resulting degradation is characterized based on the time evolution of the interface and hole trap densities, as well as the resulting threshold voltage shift. By varying the physical thicknesses of the interface silicon dioxide (SiO2 and hafnium oxide (HfO2 layers, we investigate how the variation in thickness affects hole trapping/detrapping at different stress temperatures. The results suggest that the degradations are highly dependent on the physical gate stack parameters for a given stress voltage and temperature. The degradation is more pronounced by 5% when the thicknesses of HfO2 are increased but is reduced by 11% when the SiO2 interface layer thickness is increased during lower stress voltage. However, at higher stress voltage, greater degradation is observed for a thicker SiO2 interface layer. In addition, the existence of different stress temperatures at which the degradation behavior differs implies that the hole trapping/detrapping event is thermally activated.

  11. Electron-electron scattering-induced channel hot electron injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors with high-k/metal gate stacks

    International Nuclear Information System (INIS)

    Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Liu, Xi-Wen; Chang, Ting-Chang; Chen, Ching-En; Ho, Szu-Han; Tseng, Tseung-Yuen; Cheng, Osbert; Huang, Cheng-Tung; Lu, Ching-Sen

    2014-01-01

    This work investigates electron-electron scattering (EES)-induced channel hot electron (CHE) injection in nanoscale n-channel metal-oxide-semiconductor field-effect-transistors (n-MOSFETs) with high-k/metal gate stacks. Many groups have proposed new models (i.e., single-particle and multiple-particle process) to well explain the hot carrier degradation in nanoscale devices and all mechanisms focused on Si-H bond dissociation at the Si/SiO 2 interface. However, for high-k dielectric devices, experiment results show that the channel hot carrier trapping in the pre-existing high-k bulk defects is the main degradation mechanism. Therefore, we propose a model of EES-induced CHE injection to illustrate the trapping-dominant mechanism in nanoscale n-MOSFETs with high-k/metal gate stacks.

  12. Electrical and materials properties of AlN/ HfO{sub 2} high-k stack with a metal gate

    Energy Technology Data Exchange (ETDEWEB)

    Reid, Kimberly G. [Tokyo Electron U.S., 14338 FM 1826, Austin, TX 78737 (United States)], E-mail: kim@ireid.com; Dip, Anthony [Tokyo Electron U.S., 2400 Grove Blvd., Austin, TX 78747 (United States)], E-mail: anthony.dip@us.tel.com; Sasaki, Sadao [Tokyo Electron U.S. (United States)], E-mail: Sadao.sasaki@us.tel.com; Triyoso, Dina [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Dina.Triyoso@freescale.com; Samavedam, Sri [Freescale Semiconductor Inc., 3501 Ed Bluestein Blvd, Austin, TX 78721 (United States)], E-mail: Sri.Samavedam@freescale.com; Gilmer, David [SEMATECH 2706 Montopolis Drive, Austin, TX 78741 (United States)], E-mail: David.Gilmer@sematech.org; Gondran, Carolyn F.H. [Process Characterization Laboratory, ATDF/SEMATECH, 2706 Montopolis Drive, Austin, Texas 78741 (United States)], E-mail: Carolyn.Gondran@atdf.com

    2009-02-27

    In this study, aluminum nitride (AlN) was grown by molecular layer deposition on HfO{sub 2} that had been deposited on 200 mm Si (100) substrates. The AlN was grown on HfO{sub 2} using sequential exposures of trimethyl-aluminum and ammonia (NH{sub 3}) in a batch vertical furnace. Excellent thickness uniformity on test wafers from the top of the furnace to the bottom of the furnace (across the furnace load) was obtained. The equivalent oxide thickness was 16.5-18.8 A for the AlN/HfO{sub 2} stack on patterned device wafers with a molybdenum oxynitride metal gate with leakage current densities from low 10{sup -5} to mid 10{sup -6} A/cm{sup 2} at threshold voltage minus one volt. There was no change in the work function with the AlN cap on HfO{sub 2} with the MoN metal gate, even with a 1000 deg. C anneal.

  13. Effect of atomic-arrangement matching on La{sub 2}O{sub 3}/Ge heterostructures for epitaxial high-k-gate-stacks

    Energy Technology Data Exchange (ETDEWEB)

    Kanashima, T., E-mail: kanashima@ee.es.osaka-u.ac.jp; Zenitaka, M.; Kajihara, Y.; Yamada, S.; Hamaya, K. [Graduate School of Engineering Science, Osaka University, Machkaneyama 1-3, Toyonaka, Osaka 560-8531 (Japan); Nohira, H. [Tokyo City University, 1-28-1 Tamazutumi, Setagaya-ku, Tokyo 158-8557 (Japan)

    2015-12-14

    We demonstrate a high-quality La{sub 2}O{sub 3} layer on germanium (Ge) as an epitaxial high-k-gate-insulator, where there is an atomic-arrangement matching condition between La{sub 2}O{sub 3}(001) and Ge(111). Structural analyses reveal that (001)-oriented La{sub 2}O{sub 3} layers were grown epitaxially only when we used Ge(111) despite low growth temperatures less than 300 °C. The permittivity (k) of the La{sub 2}O{sub 3} layer is roughly estimated to be ∼19 from capacitance-voltage (C-V) analyses in Au/La{sub 2}O{sub 3}/Ge structures after post-metallization-annealing treatments, although the C-V curve indicates the presence of carrier traps near the interface. By using X-ray photoelectron spectroscopy analyses, we find that only Ge–O–La bonds are formed at the interface, and the thickness of the equivalent interfacial Ge oxide layer is much smaller than that of GeO{sub 2} monolayer. We discuss a model of the interfacial structure between La{sub 2}O{sub 3} and Ge(111) and comment on the C-V characteristics.

  14. CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

    Science.gov (United States)

    Dentoni Litta, Eugenio; Ritzenthaler, Romain; Schram, Tom; Spessot, Alessio; O’Sullivan, Barry; Machkaoutsan, Vladimir; Fazan, Pierre; Ji, Yunhyuck; Mannaert, Geert; Lorant, Christophe; Sebaai, Farid; Thiam, Arame; Ercken, Monique; Demuynck, Steven; Horiguchi, Naoto

    2018-04-01

    Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

  15. Integration issues of high-k and metal gate into conventional CMOS technology

    International Nuclear Information System (INIS)

    Song, S.C.; Zhang, Z.; Huffman, C.; Bae, S.H.; Sim, J.H.; Kirsch, P.; Majhi, P.; Moumen, N.; Lee, B.H.

    2006-01-01

    Issues surrounding the integration of Hf-based high-k dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate stack process as well as optimization of other CMOS process steps enables robust CMOSFETs with a wide process latitude. HfO 2 of a 2 nm physical thickness shows complete suppression of transient charge trapping resulting from a significant reduction in film volume as well as kinetically suppressed crystallization. Metal thickness is also critical when optimizing physical stress effects and minimizing dopant diffusion. A high temperature anneal after source and drain implantation in a conventional CMOSFET process reduces the interface state density and improves electron mobility

  16. Optimum source/drain overlap design for 16 nm high-k/metal gate MOSFETs

    International Nuclear Information System (INIS)

    Jang, Junyong; Lim, Towoo; Kim, Youngmin

    2009-01-01

    We explore a source/drain (S/D) design for a 16 nm MOSFET utilizing a replacement process for a high-k gate dielectric and metal gate electrode integration. Using TCAD simulation, a trade-off study between series resistance and overlap capacitance is carried out for a high-k dielectric surrounding gate structure, which results from the replacement process. An optimum S/D overlap to gate for the high-k surrounding gate structure is found to be different from the conventional gate structure, i.e. 0∼1 nm underlap is preferred for the surround high-k gate structure while 1∼2 nm overlap for the conventional gate one

  17. Investigation of High-k Dielectrics and Metal Gate Electrodes for Non-volatile Memory Applications

    Science.gov (United States)

    Jayanti, Srikant

    Due to the increasing demand of non-volatile flash memories in the portable electronics, the device structures need to be scaled down drastically. However, the scalability of traditional floating gate structures beyond 20 nm NAND flash technology node is uncertain. In this regard, the use of metal gates and high-k dielectrics as the gate and interpoly dielectrics respectively, seem to be promising substitutes in order to continue the flash scaling beyond 20nm. Furthermore, research of novel memory structures to overcome the scaling challenges need to be explored. Through this work, the use of high-k dielectrics as IPDs in a memory structure has been studied. For this purpose, IPD process optimization and barrier engineering were explored to determine and improve the memory performance. Specifically, the concept of high-k / low-k barrier engineering was studied in corroboration with simulations. In addition, a novel memory structure comprising a continuous metal floating gate was investigated in combination with high-k blocking oxides. Integration of thin metal FGs and high-k dielectrics into a dual floating gate memory structure to result in both volatile and non-volatile modes of operation has been demonstrated, for plausible application in future unified memory architectures. The electrical characterization was performed on simple MIS/MIM and memory capacitors, fabricated through CMOS compatible processes. Various analytical characterization techniques were done to gain more insight into the material behavior of the layers in the device structure. In the first part of this study, interfacial engineering was investigated by exploring La2O3 as SiO2 scavenging layer. Through the silicate formation, the consumption of low-k SiO2 was controlled and resulted in a significant improvement in dielectric leakage. The performance improvement was also gauged through memory capacitors. In the second part of the study, a novel memory structure consisting of continuous metal FG

  18. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-01-07

    Can we build a flexible and transparent truly high performance computer? High-k/metal gate stack based metal-oxide-semiconductor capacitor devices are monolithically fabricated on industry\\'s most widely used low-cost bulk single-crystalline silicon (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree of freedom to fabricate nanoelectronics devices using state-of-the-art CMOS compatible processes and then to utilize them in an unprecedented way for wide deployment over nearly any kind of shape and architecture surfaces. Electrical characterization shows uncompromising performance of post release devices. Mechanical characterization shows extra-ordinary flexibility (minimum bending radius of 1 cm) making this generic process attractive to extend the horizon of flexible electronics for truly high performance computers. Schematic and photograph of flexible high-k/metal gate MOSCAPs showing high flexibility and C-V plot showing uncompromised performance. Copyright © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  19. Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor

    International Nuclear Information System (INIS)

    Afifah Maheran A H; Menon P S; Shaari, S; Elgomati, H A; Salehuddin, F; Ahmad, I

    2013-01-01

    In this paper, we invented the optimization experiment design of a 22 nm gate length NMOS device which uses a combination of high-k material and metal as the gate which was numerically developed using an industrial-based simulator. The high-k material is Titanium dioxide (TiO 2 ), while the metal gate is Tungsten Silicide (WSi x ). The design is optimized using the L9 Taguchi method to get the optimum parameter design. There are four process parameters and two noise parameters which were varied for analyzing the effect on the threshold voltage (V th ). The objective of this experiment is to minimize the variance of V th where Taguchi's nominal-the-best signal-to-noise ratio (S/N Ratio) was used. The best settings of the process parameters were determined using Analysis of Mean (ANOM) and analysis of variance (ANOVA) to reduce the variability of V th . The results show that the V th values have least variance and the mean value can be adjusted to 0.306V ±0.027 for the NMOS device which is in line with projections by the ITRS specifications.

  20. Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs

    Science.gov (United States)

    Dentoni Litta, E.; Hellström, P.-E.; Östling, M.

    2015-06-01

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  1. Channel mobility degradation and charge trapping in high-k/metal gate NMOSFETs

    International Nuclear Information System (INIS)

    Mathew, Shajan; Bera, L.K.; Balasubramanian, N.; Joo, M.S.; Cho, B.J.

    2004-01-01

    NMOSFETs with Metalo-Organic Chemical Vapor Deposited (MOCVD) HfAlO gate dielectric and TiN metal gate have been fabricated. Channel electron mobility was measured using the split-CV method and compared with SiO 2 devices. All high-k devices showed lower mobility compared with SiO 2 reference devices. High-k MOSFETs exhibited significant charge trapping and threshold instability. Threshold voltage recovery with time was studied on devices with oxide/nitride interfacial layer between high-k film and silicon substrate

  2. Yttrium scandate thin film as alternative high-permittivity dielectric for germanium gate stack formation

    Energy Technology Data Exchange (ETDEWEB)

    Lu, Cimang, E-mail: cimang@adam.t.u-tokyo.ac.jp; Lee, Choong Hyun; Nishimura, Tomonori; Toriumi, Akira [Department of Materials Engineering, The University of Tokyo, 7-3-1 Hongo, Tokyo 113-8656 (Japan); JST, CREST, 7-3-1 Hongo, Tokyo 113-8656 (Japan)

    2015-08-17

    We investigated yttrium scandate (YScO{sub 3}) as an alternative high-permittivity (k) dielectric thin film for Ge gate stack formation. Significant enhancement of k-value is reported in YScO{sub 3} comparing to both of its binary compounds, Y{sub 2}O{sub 3} and Sc{sub 2}O{sub 3}, without any cost of interface properties. It suggests a feasible approach to a design of promising high-k dielectrics for Ge gate stack, namely, the formation of high-k ternary oxide out of two medium-k binary oxides. Aggressive scaling of equivalent oxide thickness (EOT) with promising interface properties is presented by using YScO{sub 3} as high-k dielectric and yttrium-doped GeO{sub 2} (Y-GeO{sub 2}) as interfacial layer, for a demonstration of high-k gate stack on Ge. In addition, we demonstrate Ge n-MOSFET performance showing the peak electron mobility over 1000 cm{sup 2}/V s in sub-nm EOT region by YScO{sub 3}/Y-GeO{sub 2}/Ge gate stack.

  3. Intermodulation Linearity in High-k/Metal Gate 28 nm RF CMOS Transistors

    Directory of Open Access Journals (Sweden)

    Zhen Li

    2015-09-01

    Full Text Available This paper presents experimental characterization, simulation, and Volterra series based analysis of intermodulation linearity on a high-k/metal gate 28 nm RF CMOS technology. A figure-of-merit is proposed to account for both VGS and VDS nonlinearity, and extracted from frequency dependence of measured IIP3. Implications to biasing current and voltage optimization for linearity are discussed.

  4. Study of high-k gate dielectrics by means of positron annihilation

    International Nuclear Information System (INIS)

    Uedono, A.; Naito, T.; Otsuka, T.; Ito, K.; Shiraishi, K.; Yamabe, K.; Miyazaki, S.; Watanabe, H.; Umezawa, N.; Hamid, A.; Chikyow, T.; Ohdaira, T.; Suzuki, R.; Ishibashi, S.; Inumiya, S.; Kamiyama, S.; Akasaka, Y.; Nara, Y.; Yamada, K.

    2007-01-01

    High-dielectric constant (high-k) gate materials, such as HfSiO x and HfAlO x , fabricated by atomic-layer-deposition techniques were characterized using monoenergetic positron beams. Measurements of the Doppler broadening spectra of annihilation radiation and the lifetime spectra of positrons indicated that positrons annihilated from the trapped state by open volumes that exist intrinsically in amorphous structures of the films. The size distributions of the open volumes and the local atomic configurations around such volumes can be discussed using positron annihilation parameters, and they were found to correlate with the electrical properties of the films. We confirmed that the positron annihilation is useful technique to characterize the matrix structure of amorphous high-k materials, and can be used to determine process parameters for the fabrication of high-k gate dielectrics. (copyright 2007 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  5. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa

    2010-03-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  6. Gate-first integration of tunable work function metal gates of different thicknesses into high-k metal gates CMOS FinFETs for multi- VTh engineering

    KAUST Repository

    Hussain, Muhammad Mustafa; Smith, Casey Eben; Harris, Harlan Rusty; Young, Chadwin; Tseng, Hsinghuang; Jammy, Rajarao

    2010-01-01

    Gate-first integration of tunable work function metal gates of different thicknesses (320 nm) into high-k/metal gates CMOS FinFETs was demonstrated to achieve multiple threshold voltages (VTh) for 32-nm technology and beyond logic, memory, input/output, and system-on-a-chip applications. The fabricated devices showed excellent short-channel effect immunity (drain-induced barrier lowering ∼ 40 mV/V), nearly symmetric VTh, low T inv(∼ 1.4 nm), and high Ion(∼780μAμm) for N/PMOS without any intentional strain enhancement. © 2006 IEEE.

  7. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    Directory of Open Access Journals (Sweden)

    Yu-Hsien Lin

    2015-01-01

    Full Text Available We investigated amorphous indium gallium zinc oxide (a-IGZO thin film transistors (TFTs using different high-k gate dielectric materials such as silicon nitride (Si3N4 and aluminum oxide (Al2O3 at low temperature process (<300°C and compared them with low temperature silicon dioxide (SiO2. The IGZO device with high-k gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, postannealing treatment is an essential process for completing the process. The chemical reaction of the high-k/IGZO interface due to heat formation in high-k/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-k gate dielectric materials and explained the interface effect by charge band diagram.

  8. Investigation of high- k yttrium copper titanate thin films as alternative gate dielectrics

    International Nuclear Information System (INIS)

    Monteduro, Anna Grazia; Ameer, Zoobia; Rizzato, Silvia; Martino, Maurizio; Caricato, Anna Paola; Maruccio, Giuseppe; Tasco, Vittorianna; Lekshmi, Indira Chaitanya; Hazarika, Abhijit; Choudhury, Debraj; Sarma, D D

    2016-01-01

    Nearly amorphous high- k yttrium copper titanate thin films deposited by laser ablation were investigated in both metal–oxide–semiconductor (MOS) and metal–insulator–metal (MIM) junctions in order to assess the potentialities of this material as a gate oxide. The trend of dielectric parameters with film deposition shows a wide tunability for the dielectric constant and AC conductivity, with a remarkably high dielectric constant value of up to 95 for the thick films and conductivity as low as 6  ×  10 −10 S cm −1 for the thin films deposited at high oxygen pressure. The AC conductivity analysis points out a decrease in the conductivity, indicating the formation of a blocking interface layer, probably due to partial oxidation of the thin films during cool-down in an oxygen atmosphere. Topography and surface potential characterizations highlight differences in the thin film microstructure as a function of the deposition conditions; these differences seem to affect their electrical properties. (paper)

  9. Pentacene based thin film transistors with high-k dielectric Nd2O3 as a gate insulator

    International Nuclear Information System (INIS)

    Sarma, R.; Saikia, D.

    2010-01-01

    We have investigated the pentacene based Organic Thin Film Transistors (OTFTs) with high-k dielectric Nd 2 O 3 . Use of high dielectric constant (high-k) gate insulator Nd 2 O 3 reduces the threshold voltage and sub threshold swing of the OTFTs. The calculated threshold voltage -2.2V and sub-threshold swing 1V/decade, current ON-OFF ratio is 1.7 X 10 4 and mobility is 0.13cm 2 /V.s. Pentacene film is deposited on Nd 2 O 3 surface using two step deposition method. Deposited pentacene film is found poly crystalline in nature. (author)

  10. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto

    2013-02-12

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry\\'s most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  11. Structural and electrical characteristics of high-k/metal gate metal oxide semiconductor capacitors fabricated on flexible, semi-transparent silicon (100) fabric

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa; Sevilla, Galo T.

    2013-01-01

    In pursuit of flexible computers with high performance devices, we demonstrate a generic process to fabricate 10 000 metal-oxide-semiconductor capacitors (MOSCAPs) with semiconductor industry's most advanced high-k/metal gate stacks on widely used, inexpensive bulk silicon (100) wafers and then using a combination of iso-/anisotropic etching to release the top portion of the silicon with the already fabricated devices as a mechanically flexible (bending curvature of 133 m−1), optically semi-transparent silicon fabric (1.5 cm × 3 cm × 25 μm). The electrical characteristics show 3.7 nm effective oxide thickness, −0.2 V flat band voltage, and no hysteresis from the fabricated MOSCAPs.

  12. Influence of ultra-thin TiN thickness (1.4 nm and 2.4 nm) on positive bias temperature instability (PBTI) of high-k/metal gate nMOSFETs with gate-last process

    International Nuclear Information System (INIS)

    Qi Lu-Wei; Yang Hong; Ren Shang-Qing; Xu Ye-Feng; Luo Wei-Chun; Xu Hao; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    The positive bias temperature instability (PBTI) degradations of high-k/metal gate (HK/MG) nMOSFETs with thin TiN capping layers (1.4 nm and 2.4 nm) are systemically investigated. In this paper, the trap energy distribution in gate stack during PBTI stress is extracted by using ramped recovery stress, and the temperature dependences of PBTI (90 °C, 125 °C, 160 °C) are studied and activation energy (E a ) values (0.13 eV and 0.15 eV) are extracted. Although the equivalent oxide thickness (EOT) values of two TiN thickness values are almost similar (0.85 nm and 0.87 nm), the 2.4-nm TiN one (thicker TiN capping layer) shows better PBTI reliability (13.41% at 0.9 V, 90 °C, 1000 s). This is due to the better interfacial layer/high-k (IL/HK) interface, and HK bulk states exhibited through extracting activation energy and trap energy distribution in the high-k layer. (paper)

  13. High permittivity materials for oxide gate stack in Ge-based metal oxide semiconductor capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Molle, Alessandro, E-mail: alessandro.molle@mdm.infm.i [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Baldovino, Silvia [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy); Spiga, Sabina [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Fanciulli, Marco [Laboratorio Nazionale MDM, CNR-INFM, via C. Olivetti 2, 20041 Agrate Brianza, Milano (Italy); Dipartimento di Scienza dei Materiali, Universita degli Studi di Milano Bicocca, Milano (Italy)

    2010-01-01

    In the effort to ultimately shrink the size of logic devices towards a post-Si era, the integration of Ge as alternative channel material for high-speed p-MOSFET devices and the concomitant coupling with high permittivity dielectrics (high-k) as gate oxides is currently a key-challenge in microelectronics. However, the Ge option still suffers from a number of unresolved drawbacks and open issues mainly related to the thermodynamic and electrical compatibility of Ge substrates with high-k gate stack. Strictly speaking, two main concerns can be emphasized. On one side is the dilemma on which chemical/physical passivation is more suitable to minimize the unavoidable presence of electrically active defects at the oxide/semiconductor interface. On the other side, overcoming the SiO{sub 2} gate stack opens the route to a number of potentially outperforming high-k oxides. Two deposition approaches were here separately adopted to investigate the high-k oxide growth on Ge substrates, the molecular beam deposition (MBD) of Gd{sub 2}O{sub 3} and the atomic layer deposition (ALD) of HfO{sub 2}. In the MBD framework epitaxial and amorphous Gd{sub 2}O{sub 3} films were grown onto GeO{sub 2}-passivated Ge substrates. In this case, Ge passivation was achieved by exploiting the Ge{sup 4+} bonding state in GeO{sub 2} ultra-thin interface layers intentionally deposited in between Ge and the high-k oxide by means of atomic oxygen exposure to Ge. The composition of the interface layer has been characterized as a function of the oxidation temperature and evidence of Ge dangling bonds at the GeO{sub 2}/Ge interface has been reported. Finally, the electrical response of MOS capacitors incorporating Gd{sub 2}O{sub 3} and GeO{sub 2}-passivated Ge substrates has been checked by capacitance-voltage measurements. On the other hand, the structural and electrical properties of HfO{sub 2} films grown by ALD on Ge by using different oxygen precursors, i.e. H{sub 2}O, Hf(O{sup t}Bu){sub 2}(mmp

  14. Plasma-Induced Damage on the Reliability of Hf-Based High-k/Dual Metal-Gates Complementary Metal Oxide Semiconductor Technology

    International Nuclear Information System (INIS)

    Weng, W.T.; Lin, H.C.; Huang, T.Y.; Lee, Y.J.; Lin, H.C.

    2009-01-01

    This study examines the effects of plasma-induced damage (PID) on Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates that thinning the gate dielectric reduces the impact of damage on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (NMOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO 2 /poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for high-k/metal-gate CMOS technology.

  15. Mechanisms for plasma etching of HfO{sub 2} gate stacks with Si selectivity and photoresist trimming

    Energy Technology Data Exchange (ETDEWEB)

    Shoeb, Juline; Kushner, Mark J. [Department of Electrical and Computer Engineering, Iowa State University, Ames, Iowa 50011 (United States); Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109-2122 (United States)

    2009-11-15

    To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO{sub 2} in particular, are being implemented as a replacement for SiO{sub 2}. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl{sub 3}/Cl{sub 2} mixtures effectively etches HfO{sub 2} while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl{sub 3}/Cl{sub 2} plasmas, preceded by photoresist trimming in Ar/O{sub 2} plasmas, are discussed. It was found that BCl{sub n} species react with HfO{sub 2}, which under ion impact, form volatile etch products such as B{sub m}OCl{sub n} and HfCl{sub n}. Selectivity to Si is achieved by creating Si-B bonding as a precursor to the deposition of a BCl{sub n} polymer which slows the etch rate relative to HfO{sub 2}. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile are discussed.

  16. Al2O3 nanocrystals embedded in amorphous Lu2O3 high-k gate dielectric for floating gate memory application

    International Nuclear Information System (INIS)

    Yuan, C L; Chan, M Y; Lee, P S; Darmawan, P; Setiawan, Y

    2007-01-01

    The integration of nanoparticles has high potential in technological applications and opens up possibilities of the development of new devices. Compared to the conventional floating gate memory, a structure containing nanocrystals embedded in dielectrics shows high potential to produce a memory with high endurance, low operating voltage, fast write-erase speeds and better immunity to soft errors [S. Tiwari, F. Rana, H. Hanafi et al. 1996 Appl.Phys. Lett. 68, 1377]. A significant improvement on data retention [J. J. Lee, X. Wang et al. 2003 Proceedings of the VLSI Technol. Symposium, p33] can be observed when discrete nanodots are used instead of continuous floating gate as charge storage nodes because local defect related leakage can be reduced efficiently. Furthermore, using a high-k dielectric in place of the conventional SiO2 based dielectric, nanodots flash memory is able to achieve significantly improved programming efficiency and data retention [A. Thean and J. -P. Leburton, 2002 IEEE Potentials 21, 35; D. W. Kim, T. Kim and S. K. Banerjee, 2003 IEEE Trans. Electron Devices 50, 1823]. We have recently successfully developed a method to produce nanodots embedded in high-k gate dielectrics [C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Electrochemical and Solid-State Letters 9, F53; C. L. Yuan, P. Darmawan, Y. Setiawan and P. S. Lee, 2006 Europhys. Lett. 74, 177]. In this paper, we fabricated the memory structure of Al 2 O 3 nanocrystals embedded in amorphous Lu 2 O 3 high k dielectric using pulsed laser ablation. The mean size and density of the Al 2 O 3 nanocrystals are estimated to be about 5 nm and 7x1011 cm -2 , respectively. Good electrical performances in terms of large memory window and good data retention were observed. Our preparation method is simple, fast and economical

  17. Understanding the Structure of High-K Gate Oxides - Oral Presentation

    Energy Technology Data Exchange (ETDEWEB)

    Miranda, Andre [SLAC National Accelerator Lab., Menlo Park, CA (United States)

    2015-08-25

    Hafnium Oxide (HfO2) amorphous thin films are being used as gate oxides in transistors because of their high dielectric constant (κ) over Silicon Dioxide. The present study looks to find the atomic structure of HfO2 thin films which hasn’t been done with the technique of this study. In this study, two HfO2 samples were studied. One sample was made with thermal atomic layer deposition (ALD) on top of a Chromium and Gold layer on a silicon wafer. The second sample was made with plasma ALD on top of a Chromium and Gold layer on a Silicon wafer. Both films were deposited at a thickness of 50nm. To obtain atomic structure information, Grazing Incidence X-ray diffraction (GIXRD) was carried out on the HfO2 samples. Because of this, absorption, footprint, polarization, and dead time corrections were applied to the scattering intensity data collected. The scattering curves displayed a difference in structure between the ALD processes. The plasma ALD sample showed the broad peak characteristic of an amorphous structure whereas the thermal ALD sample showed an amorphous structure with characteristics of crystalline materials. This appears to suggest that the thermal process results in a mostly amorphous material with crystallites within. Further, the scattering intensity data was used to calculate a pair distribution function (PDF) to show more atomic structure. The PDF showed atom distances in the plasma ALD sample had structure up to 10 Å, while the thermal ALD sample showed the same structure below 10 Å. This structure that shows up below 10 Å matches the bond distances of HfO2 published in literature. The PDF for the thermal ALD sample also showed peaks up to 20 Å, suggesting repeating atomic spacing outside the HfO2 molecule in the sample. This appears to suggest that there is some crystalline structure within the thermal ALD sample.

  18. Analytical V TH and S models for (DMG-GC-stack) surrounding-gate MOSFET

    Science.gov (United States)

    Aouaj, Abdellah; Bouziane, Ahmed; Nouaçry, Ahmed

    2012-01-01

    This article presents an analytical model of surface potential, threshold voltage and subthreshold swing for a new structure of surrounding-gate MOSFET by combining dual-material gate, graded channel and gate stack. By comparison with published results, it is shown that the new MOSFET structure can improve the immunity of CMOS-based devices in the nanoscale regime against short-channel effects.

  19. Effect of Thermal Budget on the Electrical Characterization of Atomic Layer Deposited HfSiO/TiN Gate Stack MOSCAP Structure.

    Directory of Open Access Journals (Sweden)

    Z N Khan

    Full Text Available Metal Oxide Semiconductor (MOS capacitors (MOSCAP have been instrumental in making CMOS nano-electronics realized for back-to-back technology nodes. High-k gate stacks including the desirable metal gate processing and its integration into CMOS technology remain an active research area projecting the solution to address the requirements of technology roadmaps. Screening, selection and deposition of high-k gate dielectrics, post-deposition thermal processing, choice of metal gate structure and its post-metal deposition annealing are important parameters to optimize the process and possibly address the energy efficiency of CMOS electronics at nano scales. Atomic layer deposition technique is used throughout this work because of its known deposition kinetics resulting in excellent electrical properties and conformal structure of the device. The dynamics of annealing greatly influence the electrical properties of the gate stack and consequently the reliability of the process as well as manufacturable device. Again, the choice of the annealing technique (migration of thermal flux into the layer, time-temperature cycle and sequence are key parameters influencing the device's output characteristics. This work presents a careful selection of annealing process parameters to provide sufficient thermal budget to Si MOSCAP with atomic layer deposited HfSiO high-k gate dielectric and TiN gate metal. The post-process annealing temperatures in the range of 600°C -1000°C with rapid dwell time provide a better trade-off between the desirable performance of Capacitance-Voltage hysteresis and the leakage current. The defect dynamics is thought to be responsible for the evolution of electrical characteristics in this Si MOSCAP structure specifically designed to tune the trade-off at low frequency for device application.

  20. Active gate driver for dv/dt control and active voltage clamping in an IGBT stack

    DEFF Research Database (Denmark)

    Rasmussen, Tonny Wederberg

    2005-01-01

    For high voltages converters stacks of IGBTs can be used if the static and dynamic voltage sharing among the IGBTs can be applied. dVCE/dt should also be controlled in order not to damage insulation material. This paper describes theory and measurements of an active gate driver for stacking IGBTs....... For the measurements two series connected standard IGBTs made for hard switching applications are used. Problems are shown and proposals for improvements are given....

  1. Comparative studies of AlGaN/GaN MOS-HEMTs with stacked gate dielectrics by the mixed thin film growth method

    International Nuclear Information System (INIS)

    Chou, Bo-Yi; Hsu, Wei-Chou; Liu, Han-Yin; Ho, Chiu-Sheng; Lee, Ching-Sung

    2013-01-01

    This paper reports Al 0.27 Ga 0.73 N/GaN metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) with stacked Al 2 O 3 /HfO 2 gate dielectrics by using hydrogen peroxideoxidation/sputtering techniques. The Al 2 O 3 employed as a gate dielectric and surface passivation layer effectively suppresses the gate leakage current, improves RF drain current collapse and exhibits good thermal stability. Moreover, by stacking the good insulating high-k HfO 2 dielectric further suppresses the gate leakage, enhances the dielectric breakdown field and power-added efficiency, and decreases the equivalent oxide thickness. The present MOS-HEMT design has demonstrated superior improvements of 10.1% (16.4%) in the maximum drain–source current (I DS,max ), 11.4% (22.5%) in the gate voltage swing and 12.5%/14.4% (21.9%/22.3%) in the two-terminal gate–drain breakdown/turn-on voltages (BV GD /V ON ), and the present design also demonstrates the lowest gate leakage current and best thermal stability characteristics as compared to two reference MOS-HEMTs with a single Al 2 O 3 /(HfO 2 ) dielectric layer of the same physical thickness. (invited paper)

  2. Interfacial microstructure of NiSi x/HfO2/SiO x/Si gate stacks

    International Nuclear Information System (INIS)

    Gribelyuk, M.A.; Cabral, C.; Gusev, E.P.; Narayanan, V.

    2007-01-01

    Integration of NiSi x based fully silicided metal gates with HfO 2 high-k gate dielectrics offers promise for further scaling of complementary metal-oxide- semiconductor devices. A combination of high resolution transmission electron microscopy and small probe electron energy loss spectroscopy (EELS) and energy dispersive X-ray analysis has been applied to study interfacial reactions in the undoped gate stack. NiSi was found to be polycrystalline with the grain size decreasing from top to bottom of NiSi x film. Ni content varies near the NiSi/HfO x interface whereby both Ni-rich and monosilicide phases were observed. Spatially non-uniform distribution of oxygen along NiSi x /HfO 2 interface was observed by dark field Scanning Transmission Electron Microscopy and EELS. Interfacial roughness of NiSi x /HfO x was found higher than that of poly-Si/HfO 2 , likely due to compositional non-uniformity of NiSi x . No intermixing between Hf, Ni and Si beyond interfacial roughness was observed

  3. A gate drive circuit for gate-turn-off (GTO) devices in series stack

    International Nuclear Information System (INIS)

    Despe, O.

    1999-01-01

    A gate-turn-off (GTO) switch is under development at the Advanced Photon Source as a replacement for a thyratron switch in high power pulsed application. The high voltage in the application requires multiple GTOs connected in series. One component that is critical to the success of GTO operation is the gate drive circuit. The gate drive circuit has to provide fast high-current pulses to the GTO gate for fast turn-on and turn-off. It also has to be able to operate while floating at high voltage. This paper describes a gate drive circuit that meets these requirements

  4. Self-aligned top-gate InGaZnO thin film transistors using SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Rongsheng; Zhou, Wei; Zhang, Meng; Wong, Man; Kwok, Hoi Sing

    2013-12-02

    Self-aligned top-gate amorphous indium–gallium–zinc oxide (a-IGZO) thin film transistors (TFTs) utilizing SiO{sub 2}/Al{sub 2}O{sub 3} stack thin films as gate dielectric are developed in this paper. Due to high quality of the high-k Al{sub 2}O{sub 3} and good interface between active layer and gate dielectric, the resulting a-IGZO TFT exhibits good electrical performance including field-effect mobility of 9 cm{sup 2}/Vs, threshold voltage of 2.2 V, subthreshold swing of 0.2 V/decade, and on/off current ratio of 1 × 10{sup 7}. With scaling down of the channel length, good characteristics are also obtained with a small shift of the threshold voltage and no degradation of subthreshold swing. - Highlights: • Self-aligned top-gate indium–gallium–zinc oxide thin-film transistor is proposed. • SiO{sub 2}/Al{sub 2}O{sub 3} stack gate dielectric is proposed. • The source/drain areas are hydrogen-doped by CHF{sub 3} plasma. • The devices show good electrical performance and scaling down behavior.

  5. First-principles simulations of the leakage current in metal-oxide-semiconductor structures caused by oxygen vacancies in HfO2 high-K gate dielectric

    International Nuclear Information System (INIS)

    Mao, L.F.; Wang, Z.O.

    2008-01-01

    HfO 2 high-K gate dielectric has been used as a new gate dielectric in metal-oxide-semiconductor structures. First-principles simulations are used to study the effects of oxygen vacancies on the tunneling current through the oxide. A level which is nearly 1.25 eV from the bottom of the conduction band is introduced into the bandgap due to the oxygen vacancies. The tunneling current calculations show that the tunneling currents through the gate oxide with different defect density possess the typical characteristic of stress-induced leakage current. Further analysis shows that the location of oxygen vacancies will have a marked effect on the tunneling current. The largest increase in the tunneling current caused by oxygen vacancies comes about at the middle oxide field when defects are located at the middle of the oxide. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  6. Development of III-V p-MOSFETs with high-kappa gate stack for future CMOS applications

    Science.gov (United States)

    Nagaiah, Padmaja

    on strained surface and buried channel In0.36 Ga0.64Sb QW MOSFETs with thin top barrier and in-situ deposited a-Si IPL and high-k HfO2 as well as combination Al 2O3+HfO2 gate stacks and ex-situ atomic layer deposited (ALD) combination gate oxide and with thin 2 nm InAs surface passivation layer is presented. Finally, summary of the salient results from the different chapters is provided with recommendations for future research.

  7. Interface Study on Amorphous Indium Gallium Zinc Oxide Thin Film Transistors Using High-k Gate Dielectric Materials

    International Nuclear Information System (INIS)

    Lin, Y. H.; Chou, J. C.

    2015-01-01

    We investigated amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT_s) using different high-Κ gate dielectric materials such as silicon nitride (Si_3N_4) and aluminum oxide (Al_2O_3) at low temperature process (<300 degree) and compared them with low temperature silicon dioxide (SiO_2). The IGZO device with high-Κ gate dielectric material will expect to get high gate capacitance density to induce large amount of channel carrier and generate the higher drive current. In addition, for the integrating process of integrating IGZO device, post annealing treatment is an essential process for completing the process. The chemical reaction of the high-κ/IGZO interface due to heat formation in high-Κ/IGZO materials results in reliability issue. We also used the voltage stress for testing the reliability for the device with different high-Κ gate dielectric materials and explained the interface effect by charge band diagram.

  8. High-frequency self-aligned graphene transistors with transferred gate stacks

    Science.gov (United States)

    Cheng, Rui; Bai, Jingwei; Liao, Lei; Zhou, Hailong; Chen, Yu; Liu, Lixin; Lin, Yung-Chen; Jiang, Shan; Huang, Yu; Duan, Xiangfeng

    2012-01-01

    Graphene has attracted enormous attention for radio-frequency transistor applications because of its exceptional high carrier mobility, high carrier saturation velocity, and large critical current density. Herein we report a new approach for the scalable fabrication of high-performance graphene transistors with transferred gate stacks. Specifically, arrays of gate stacks are first patterned on a sacrificial substrate, and then transferred onto arbitrary substrates with graphene on top. A self-aligned process, enabled by the unique structure of the transferred gate stacks, is then used to position precisely the source and drain electrodes with minimized access resistance or parasitic capacitance. This process has therefore enabled scalable fabrication of self-aligned graphene transistors with unprecedented performance including a record-high cutoff frequency up to 427 GHz. Our study defines a unique pathway to large-scale fabrication of high-performance graphene transistors, and holds significant potential for future application of graphene-based devices in ultra–high-frequency circuits. PMID:22753503

  9. Performance of organic field effect transistors with high-k gate oxide after application of consecutive bias stress

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Sunwoo; Choi, Changhwan; Lee, Kilbock [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of); Cho, Joong Hwee [Department of Embedded Systems Engineering,University of Incheon, Incheon 406-722 (Korea, Republic of); Ko, Ki-Young [Korea Institute of Patent Information, Seoul, 146-8 (Korea, Republic of); Ahn, Jinho, E-mail: jhahn@hanyang.ac.kr [Department of Materials Science and Engineering, Hanyang University, Seoul, 133-791 (Korea, Republic of)

    2012-10-30

    We report the effect of consecutive electrical stress on the performance of organic field effect transistors (OFETs). Sputtered aluminum oxide (Al{sub 2}O{sub 3}) and hafnium oxide (HfO{sub 2}) were used as gate oxide layers. After the electrical stress, the threshold voltage, which strongly depends on bulk defects, was remarkably shifted to the negative direction, while the other performance characteristics of OFETs such as on-current, transconductance and mobility, which are sensitive to interface defects, were slightly decreased. This result implies that the defects in the bulk layer are significantly affected compared to the defects in the interface layer. Thus, it is important to control the defects in the pentacene bulk layer in order to maintain the good reliabilities of pentacene devices. Those defects in HfO{sub 2} gate oxide devices were larger compared to those in Al{sub 2}O{sub 3} gate oxide devices.

  10. Vacancy-fluorine complexes and their impact on the properties of metal-oxide transistors with high-k gate dielectrics studied using monoenergetic positron beams

    Science.gov (United States)

    Uedono, A.; Inumiya, S.; Matsuki, T.; Aoyama, T.; Nara, Y.; Ishibashi, S.; Ohdaira, T.; Suzuki, R.; Miyazaki, S.; Yamada, K.

    2007-09-01

    Vacancy-fluorine complexes in metal-oxide semiconductors (MOS) with high-k gate dielectrics were studied using a positron annihilation technique. F+ ions were implanted into Si substrates before the deposition of gate dielectrics (HfSiON). The shift of threshold voltage (Vth) in MOS capacitors and an increase in Fermi level position below the HfSiON/Si interface were observed after F+ implantation. Doppler broadening spectra of the annihilation radiation and positron lifetimes were measured before and after HfSiON fabrication processes. From a comparison between Doppler broadening spectra and those obtained by first-principles calculation, the major defect species in Si substrates after annealing treatment (1050 °C, 5 s) was identified as vacancy-fluorine complexes (V3F2). The origin of the Vth shift in the MOS capacitors was attributed to V3F2 located in channel regions.

  11. Influence of multi-deposition multi-annealing on time-dependent dielectric breakdown characteristics of PMOS with high-k/metal gate last process

    International Nuclear Information System (INIS)

    Wang Yan-Rong; Yang Hong; Xu Hao; Wang Xiao-Lei; Luo Wei-Chun; Qi Lu-Wei; Zhang Shu-Xiang; Wang Wen-Wu; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2015-01-01

    A multi-deposition multi-annealing technique (MDMA) is introduced into the process of high-k/metal gate MOSFET for the gate last process to effectively reduce the gate leakage and improve the device’s performance. In this paper, we systematically investigate the electrical parameters and the time-dependent dielectric breakdown (TDDB) characteristics of positive channel metal oxide semiconductor (PMOS) under different MDMA process conditions, including the deposition/annealing (D and A) cycles, the D and A time, and the total annealing time. The results show that the increases of the number of D and A cycles (from 1 to 2) and D and A time (from 15 s to 30 s) can contribute to the results that the gate leakage current decreases by about one order of magnitude and that the time to fail (TTF) at 63.2% increases by about several times. However, too many D and A cycles (such as 4 cycles) make the equivalent oxide thickness (EOT) increase by about 1 Å and the TTF of PMOS worsen. Moreover, different D and A times and numbers of D and A cycles induce different breakdown mechanisms. (paper)

  12. The influence of carbon doping on the performance of Gd2O3 as high-k gate dielectric

    International Nuclear Information System (INIS)

    Shekhter, P.; Yehezkel, S.; Shriki, A.; Eizenberg, M.; Chaudhuri, A. R.; Osten, H. J.; Laha, A.

    2014-01-01

    One of the approaches for overcoming the issue of leakage current in modern metal-oxide-semiconductor devices is utilizing the high dielectric constants of lanthanide based oxides. We investigated the effect of carbon doping directly into Gd 2 O 3 layers on the performance of such devices. It was found that the amount of carbon introduced into the dielectric is above the solubility limit; carbon atoms enrich the oxide-semiconductor interface and cause a significant shift in the flat band voltage of the stack. Although the carbon atoms slightly degrade this interface, this method has a potential for tuning the flat band voltage of such structures

  13. Quantum Hall Effect and Semimetallic Behavior of Dual-Gated ABA-Stacked Trilayer Graphene

    Directory of Open Access Journals (Sweden)

    E. A. Henriksen

    2012-01-01

    Full Text Available The electronic structure of multilayer graphenes depends strongly on the number of layers as well as the stacking order. Here we explore the electronic transport of purely ABA-stacked trilayer graphenes in a dual-gated field-effect device configuration. We find both that the zero-magnetic-field transport and the quantum Hall effect at high magnetic fields are distinctly different from the monolayer and bilayer graphenes, and that they show electron-hole asymmetries that are strongly suggestive of a semimetallic band overlap. When the ABA trilayers are subjected to an electric field perpendicular to the sheet, Landau-level splittings due to a lifting of the valley degeneracy are clearly observed.

  14. Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.

    2012-03-09

    It is shown that the well-known negative flatband voltage (VFB) shift, induced by rare-earth oxide capping in metal gate stacks, can be completely reversed in the absence of the silicon overlayer. Using TaN metal gates and Gd2O3-doped dielectric, we measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which originates from an interfacial dipole. The dipole is created by the replacement of interfacial oxygen atoms in the HfO2 lattice with nitrogen atoms from TaN.

  15. Growth Related Carrier Mobility Enhancement of Pentacene Thin-Film Transistors with High-k Oxide Gate Dielectric

    International Nuclear Information System (INIS)

    Ai-Fang, Yu; Qiong, Qi; Peng, Jiang; Chao, Jiang

    2009-01-01

    Carrier mobility enhancement from 0.09 to 0.59 cm 2 /Vs is achieved for pentacene-based thin-film transistors (TFTs) by modifying the HfO 2 gate dielectric with a polystyrene (PS) thin film. The improvement of the transistor's performance is found to be strongly related to the initial film morphologies of pentacene on the dielectrics. In contrast to the three-dimensional island-like growth mode on the HfO 2 surface, the Stranski-Krastanov growth mode on the smooth and nonpolar PS/HfO 2 surface is believed to be the origin of the excellent carrier mobility of the TFTs. A large well-connected first monolayer with fewer boundaries is formed via the Stranski–Krastanov growth mode, which facilitates a charge transport parallel to the substrate and promotes higher carrier mobility. (cross-disciplinary physics and related areas of science and technology)

  16. Change in carrier type in high-k gate carbon nanotube field-effect transistors by interface fixed charges

    International Nuclear Information System (INIS)

    Moriyama, N; Ohno, Y; Kitamura, T; Kishimoto, S; Mizutani, T

    2010-01-01

    We study the phenomenon of change in carrier type in carbon nanotube field-effect transistors (CNFETs) caused by the atomic layer deposition (ALD) of a HfO 2 gate insulator. When a HfO 2 layer is deposited on a CNFET, the type of carrier changes from p-type to n-type. The so-obtained n-type device has good performance and stability in air. The conductivity of such a device with a channel length of 0.7 μm is 11% of the quantum conductance 4e 2 /h. The contact resistance for electron current is estimated to be 14 kΩ. The n-type conduction of this CNFET is maintained for more than 100 days. The change in carrier type is attributed to positive fixed charges introduced at the interface between the HfO 2 and SiO 2 layers. We also propose a novel technique to control the type of conduction by utilizing interface fixed charges; this technique is compatible with Si CMOS process technology.

  17. GaN-Based High-k Praseodymium Oxide Gate MISFETs with P2S5/(NH42SX + UV Interface Treatment Technology

    Directory of Open Access Journals (Sweden)

    Chao-Wei Lin

    2012-01-01

    Full Text Available This study examines the praseodymium-oxide- (Pr2O3- passivated AlGaN/GaN metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs with high dielectric constant in which the AlGaN Schottky layers are treated with P2S5/(NH42SX + ultraviolet (UV illumination. An electron-beam evaporated Pr2O3 insulator is used instead of traditional plasma-assisted chemical vapor deposition (PECVD, in order to prevent plasma-induced damage to the AlGaN. In this work, the HEMTs are pretreated with P2S5/(NH42SX solution and UV illumination before the gate insulator (Pr2O3 is deposited. Since stable sulfur that is bound to the Ga species can be obtained easily and surface oxygen atoms are reduced by the P2S5/(NH42SX pretreatment, the lowest leakage current is observed in MIS-HEMT. Additionally, a low flicker noise and a low surface roughness (0.38 nm are also obtained using this novel process, which demonstrates its ability to reduce the surface states. Low gate leakage current Pr2O3 and high-k AlGaN/GaN MIS-HEMTs, with P2S5/(NH42SX + UV illumination treatment, are suited to low-noise applications, because of the electron-beam-evaporated insulator and the new chemical pretreatment.

  18. Low-temperature fabrication of sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors

    Science.gov (United States)

    Yao, Rihui; Zheng, Zeke; Xiong, Mei; Zhang, Xiaochen; Li, Xiaoqing; Ning, Honglong; Fang, Zhiqiang; Xie, Weiguang; Lu, Xubing; Peng, Junbiao

    2018-03-01

    In this work, low temperature fabrication of a sputtered high-k HfO2 gate dielectric for flexible a-IGZO thin film transistors (TFTs) on polyimide substrates was investigated. The effects of Ar-pressure during the sputtering process and then especially the post-annealing treatments at low temperature (≤200 °C) for HfO2 on reducing the density of defects in the bulk and on the surface were systematically studied. X-ray reflectivity, UV-vis and X-ray photoelectron spectroscopy, and micro-wave photoconductivity decay measurements were carried out and indicated that the high quality of optimized HfO2 film and its high dielectric properties contributed to the low concentration of structural defects and shallow localized defects such as oxygen vacancies. As a result, the well-structured HfO2 gate dielectric exhibited a high density of 9.7 g/cm3, a high dielectric constant of 28.5, a wide optical bandgap of 4.75 eV, and relatively low leakage current. The corresponding flexible a-IGZO TFT on polyimide exhibited an optimal device performance with a saturation mobility of 10.3 cm2 V-1 s-1, an Ion/Ioff ratio of 4.3 × 107, a SS value of 0.28 V dec-1, and a threshold voltage (Vth) of 1.1 V, as well as favorable stability under NBS/PBS gate bias and bending stress.

  19. Study of interfaces and band offsets in TiN/amorphous LaLuO3 gate stacks

    KAUST Repository

    Mitrovic, Ivona Z.; Simutis, G.; Davey, W. M.; Sedghi, Naser; Hall, Stephen D.; Dhanak, Vinod R.; Alexandrou, Ioannis; Wang, Qingxiao; Lopes, Joao Marcelo J.; Schubert, Jü rgen M.

    2011-01-01

    sub-peak which relates to Ti bond to interstitial oxygen have been identified for an ultra-thin 1.7 nm TiN/3 nm LLO gate stack. The angle-dependent XPS analysis of Si2s spectra as well as shifts of La4d, La3d and Lu4d core levels suggests a silicate-type

  20. In situ atomic layer nitridation on the top and down regions of the amorphous and crystalline high-K gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Tsai, Meng-Chen [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Lee, Min-Hung [Institute of Electro-Optical Science and Technology, National Taiwan Normal University, Taipei 11677, Taiwan (China); Kuo, Chin-Lung; Lin, Hsin-Chih [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China); Chen, Miin-Jang, E-mail: mjchen@ntu.edu.tw [Department of Materials Science and Engineering, National Taiwan University, Taipei 10617, Taiwan (China)

    2016-11-30

    Highlights: • The structural and electrical characteristics of the ZrO{sub 2} high-K dielectrics, treated with the in situ atomic layer doping of nitrogen into the top and down regions (top and down nitridation, TN and DN, respectively), were investigated. • The amorphous DN sample has a lower leakage current density (J{sub g}) than the amorphous TN sample, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). • The crystalline TN sample exhibited a lower CET and a similar J{sub g} as compared with the crystalline DN sample, which can be ascribed to the suppression of IL regrowth. • The crystalline ZrO{sub 2} with in situ atomic layer doping of nitrogen into the top region exhibited superior scaling limit, electrical characteristics, and reliability. - Abstract: Amorphous and crystalline ZrO{sub 2} gate dielectrics treated with in situ atomic layer nitridation on the top and down regions (top and down nitridation, abbreviated as TN and DN) were investigated. In a comparison between the as-deposited amorphous DN and TN samples, the DN sample has a lower leakage current density (J{sub g}) of ∼7 × 10{sup −4} A/cm{sup 2} with a similar capacitance equivalent thickness (CET) of ∼1.53 nm, attributed to the formation of SiO{sub x}N{sub y} in the interfacial layer (IL). The post-metallization annealing (PMA) leads to the transformation of ZrO{sub 2} from the amorphous to the crystalline tetragonal/cubic phase, resulting in an increment of the dielectric constant. The PMA-treated TN sample exhibits a lower CET of 1.22 nm along with a similar J{sub g} of ∼1.4 × 10{sup −5} A/cm{sup 2} as compared with the PMA-treated DN sample, which can be ascribed to the suppression of IL regrowth. The result reveals that the nitrogen engineering in the top and down regions has a significant impact on the electrical characteristics of amorphous and crystalline ZrO{sub 2} gate dielectrics, and the nitrogen incorporation at the top of crystalline

  1. Study of interfaces and band offsets in TiN/amorphous LaLuO3 gate stacks

    KAUST Repository

    Mitrovic, Ivona Z.

    2011-07-01

    TiN/LaLuO3 (LLO) gate stacks formed by molecular beam deposition have been investigated by X-ray photoelectron spectroscopy, medium energy ion scattering, spectroscopic ellipsometry, scanning transmission electron microscopy, electron energy loss spectroscopy and atomic force microscopy. The results indicate an amorphous structure for deposited LLO films. The band offset between the Fermi level of TiN and valence band of LLO is estimated to be 2.65 ± 0.05 eV. A weaker La-O-Lu bond and a prominent Ti2p sub-peak which relates to Ti bond to interstitial oxygen have been identified for an ultra-thin 1.7 nm TiN/3 nm LLO gate stack. The angle-dependent XPS analysis of Si2s spectra as well as shifts of La4d, La3d and Lu4d core levels suggests a silicate-type with Si-rich SiOx LLO/Si interface. Symmetrical valence and conduction band offsets for LLO to Si of 2.2 eV and the bandgap of 5.5 ± 0.1 eV have been derived from the measurements. The band alignment for ultra-thin TiN/LLO gate stack is affected by structural changes. Copyright © 2011 Published by Elsevier B.V. All rights reserved.

  2. Interfacial Cation-Defect Charge Dipoles in Stacked TiO2/Al2O3 Gate Dielectrics.

    Science.gov (United States)

    Zhang, Liangliang; Janotti, Anderson; Meng, Andrew C; Tang, Kechao; Van de Walle, Chris G; McIntyre, Paul C

    2018-02-14

    Layered atomic-layer-deposited and forming-gas-annealed TiO 2 /Al 2 O 3 dielectric stacks, with the Al 2 O 3 layer interposed between the TiO 2 and a p-type germanium substrate, are found to exhibit a significant interface charge dipole that causes a ∼-0.2 V shift of the flat-band voltage and suppresses the leakage current density for gate injection of electrons. These effects can be eliminated by the formation of a trilayer dielectric stack, consistent with the cancellation of one TiO 2 /Al 2 O 3 interface dipole by the addition of another dipole of opposite sign. Density functional theory calculations indicate that the observed interface-dependent properties of TiO 2 /Al 2 O 3 dielectric stacks are consistent in sign and magnitude with the predicted behavior of Al Ti and Ti Al point-defect dipoles produced by local intermixing of the Al 2 O 3 /TiO 2 layers across the interface. Evidence for such intermixing is found in both electrical and physical characterization of the gate stacks.

  3. Improvements in the reliability of a-InGaZnO thin-film transistors with triple stacked gate insulator in flexible electronics applications

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Hua-Mao [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang3708@gmail.com [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Taiwan (China); Tai, Ya-Hsiang [Department of Photonics & Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Chen, Kuan-Fu [Department of Physics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Chiang, Hsiao-Cheng [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Liu, Kuan-Hsien [Department of Electrophysics, National Chiao Tung University, Hsinchu, Taiwan (China); Lee, Chao-Kuei [Department of Photonics, National Sun Yat-Sen University, Kaohsiung, Taiwan (China); Lin, Wei-Ting; Cheng, Chun-Cheng; Tu, Chun-Hao; Liu, Chu-Yu [Advanced Technology Research Center, AU Optronics Corp, Hsinchu, Taiwan (China)

    2015-11-30

    This study examined the impact of the low-temperature stacking gate insulator on the gate bias instability of a-InGaZnO thin film transistors in flexible electronics applications. Although the quality of SiN{sub x} at low process/deposition temperature is better than that of SiO{sub x} at similarly low process/deposition temperature, there is still a very large positive threshold voltage (V{sub th}) shift of 9.4 V for devices with a single low-temperature SiN{sub x} gate insulator under positive gate bias stress. However, a suitable oxide–nitride–oxide-stacked gate insulator exhibits a V{sub th} shift of only 0.23 V. This improvement results from the larger band offset and suitable gate insulator thickness that can effectively suppress carrier trapping behavior. - Highlights: • The cause of the bias instability for a low-temperature gate insulator is verified. • A triple-stacked gate insulator was fabricated. • A suitable triple stacked gate insulator shows only 0.23 V threshold voltage shift.

  4. TiN/Al2O3/ZnO gate stack engineering for top-gate thin film transistors by combination of post oxidation and annealing

    Science.gov (United States)

    Kato, Kimihiko; Matsui, Hiroaki; Tabata, Hitoshi; Takenaka, Mitsuru; Takagi, Shinichi

    2018-04-01

    Control of fabrication processes for a gate stack structure with a ZnO thin channel layer and an Al2O3 gate insulator has been examined for enhancing the performance of a top-gate ZnO thin film transistor (TFT). The Al2O3/ZnO interface and the ZnO layer are defective just after the Al2O3 layer formation by atomic layer deposition. Post treatments such as plasma oxidation, annealing after the Al2O3 deposition, and gate metal formation (PMA) are promising to improve the interfacial and channel layer qualities drastically. Post-plasma oxidation effectively reduces the interfacial defect density and eliminates Fermi level pinning at the Al2O3/ZnO interface, which is essential for improving the cut-off of the drain current of TFTs. A thermal effect of post-Al2O3 deposition annealing at 350 °C can improve the crystalline quality of the ZnO layer, enhancing the mobility. On the other hand, impacts of post-Al2O3 deposition annealing and PMA need to be optimized because the annealing can also accompany the increase in the shallow-level defect density and the resulting electron concentration, in addition to the reduction in the deep-level defect density. The development of the interfacial control technique has realized the excellent TFT performance with a large ON/OFF ratio, steep subthreshold characteristics, and high field-effect mobility.

  5. Trap state passivation improved hot-carrier instability by zirconium-doping in hafnium oxide in a nanoscale n-metal-oxide semiconductor-field effect transistors with high-k/metal gate

    International Nuclear Information System (INIS)

    Liu, Hsi-Wen; Tsai, Jyun-Yu; Liu, Kuan-Ju; Lu, Ying-Hsin; Chang, Ting-Chang; Chen, Ching-En; Tseng, Tseung-Yuen; Lin, Chien-Yu; Cheng, Osbert; Huang, Cheng-Tung; Ye, Yi-Han

    2016-01-01

    This work investigates the effect on hot carrier degradation (HCD) of doping zirconium into the hafnium oxide high-k layer in the nanoscale high-k/metal gate n-channel metal-oxide-semiconductor field-effect-transistors. Previous n-metal-oxide semiconductor-field effect transistor studies demonstrated that zirconium-doped hafnium oxide reduces charge trapping and improves positive bias temperature instability. In this work, a clear reduction in HCD is observed with zirconium-doped hafnium oxide because channel hot electron (CHE) trapping in pre-existing high-k bulk defects is the main degradation mechanism. However, this reduced HCD became ineffective at ultra-low temperature, since CHE traps in the deeper bulk defects at ultra-low temperature, while zirconium-doping only passivates shallow bulk defects.

  6. Study of the La-related dipole in TiN/LaO{sub x}/HfSiON/SiON/Si gate stacks using hard X-ray photoelectron spectroscopy and backside medium energy ion scattering

    Energy Technology Data Exchange (ETDEWEB)

    Boujamaa, R. [STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles (France); CEA-LETI, MINATEC Campus, F38054 Grenoble (France); Laboratoire des Matériaux et du Génie Physique, CNRS, Grenoble INP, 3 parvis L. Néel, BP 257, 38016 Grenoble (France); Martinez, E.; Pierre, F.; Renault, O. [CEA-LETI, MINATEC Campus, F38054 Grenoble (France); Detlefs, B.; Zegenhagen, J. [European Synchrotron Radiation Facility, 6 rue Jules Horowitz, F-38000 Grenoble (France); Baudot, S. [STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles (France); Gros-Jean, M., E-mail: Mickael.Gros-Jean@st.com [STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles (France); Bertin, F. [STMicroelectronics, 850, rue Jean Monnet, 38926 Crolles (France); Dubourdieu, C., E-mail: Catherine.Dubourdieu@ec-lyon.fr [Institut des Nanotechnologies de Lyon, CNRS, Ecole Centrale de Lyon, 36 avenue Guy de Collongue, 69134 Ecully (France)

    2015-04-30

    Highlights: • Precise La depth distribution in gate stacks before and after annealing by MEIS. • Analysis by HAXPES of the buried high K/SiO{sub 2} interface without removing TiN gate. • Formation of La-silicate at the HfSiON/SiON interface. • Internal electrical field induced at the HfSiON/SiON interface by the La diffusion. • Increase of electric field strength with initial LaO{sub x} thickness. - Abstract: In this paper, we report the effect of high temperature annealing on the chemical and electronic structure of technologically relevant TiN/LaO{sub x}/HfSiON/SiON/Si gate stacks. Using medium energy ion scattering from the backside of the samples, a non-destructive compositional depth profile of La has been obtained, revealing the lanthanum diffusion in the SiON interface layer upon annealing. To complement this analysis, hard X-ray photoelectron spectroscopy with synchrotron radiation has been performed to investigate the chemical and electronic structure of the gate stacks. The results show clear changes in the Hf and Ti core level energy positions with respect to Si bulk, with changes in the thickness of the LaO{sub x} capping layer. We infer that La diffusion generates an internal electrical field at the La-silicate interface between HfSiON and SiON, and that its strength increases with the increase of LaO{sub x} thickness. These findings support the band alignment model based on a La-induced interfacial dipole.

  7. High-Performance Flexible Single-Crystalline Silicon Nanomembrane Thin-Film Transistors with High- k Nb2O5-Bi2O3-MgO Ceramics as Gate Dielectric on a Plastic Substrate.

    Science.gov (United States)

    Qin, Guoxuan; Zhang, Yibo; Lan, Kuibo; Li, Lingxia; Ma, Jianguo; Yu, Shihui

    2018-04-18

    A novel method of fabricating flexible thin-film transistor based on single-crystalline Si nanomembrane (SiNM) with high- k Nb 2 O 5 -Bi 2 O 3 -MgO (BMN) ceramic gate dielectric on a plastic substrate is demonstrated in this paper. SiNMs are successfully transferred to a flexible polyethylene terephthalate substrate, which has been plated with indium-tin-oxide (ITO) conductive layer and high- k BMN ceramic gate dielectric layer by room-temperature magnetron sputtering. The BMN ceramic gate dielectric layer demonstrates as high as ∼109 dielectric constant, with only dozens of pA current leakage. The Si-BMN-ITO heterostructure has only ∼nA leakage current at the applied voltage of 3 V. The transistor is shown to work at a high current on/off ratio of above 10 4 , and the threshold voltage is ∼1.3 V, with over 200 cm 2 /(V s) effective channel electron mobility. Bending tests have been conducted and show that the flexible transistors have good tolerance on mechanical bending strains. These characteristics indicate that the flexible single-crystalline SiNM transistors with BMN ceramics as gate dielectric have great potential for applications in high-performance integrated flexible circuit.

  8. Physical and electrical properties of bilayer CeO{sub 2}/TiO{sub 2} gate dielectric stack

    Energy Technology Data Exchange (ETDEWEB)

    Chong, M.M.V. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); GlobalFoundries Singapore Private Limited, 60 Woodlands Industrial Park D Street 2, Singapore 738406 (Singapore); Lee, P.S. [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore); Tok, A.I.Y., E-mail: MIYTOK@ntu.edu.sg [School of Materials Science and Engineering, Nanyang Technological University of Singapore, Block N 4.1Nanyang Avenue, Singapore 639798 (Singapore)

    2016-08-15

    Highlights: • A bilayer gate dielectric stack of CeO{sub 2}/TiO{sub 2} to study the dependency of film growth with varying annealing temperatures is proposed. • The study demonstrates CeO{sub 2}/TiO{sub 2} bilayer stack with comparable κ-value as that of HfO{sub 2} but with reduced leakage current density of 4 orders of magnitude. • Schottky emission is the dominant leakage conduction mechanism of annealed CeO{sub 2}/TiO{sub 2} stack due to thermionic effect of interface properties. - Abstract: This study demonstrates a bilayer gate oxide structure of cerium oxide deposited via pulsed laser deposition and titanium oxide using conventional atomic layer deposition. Samples were deposited on p-type Si (100) substrate and exhibit interesting physical and electrical properties such that 600 °C annealed CeO{sub 2}/TiO{sub 2} samples having κ-value of 18 whereas pure CeO{sub 2} deposited samples have dielectric constant of 17.1 with leakage current density of 8.94 × 10{sup −6} A/cm{sup 2} at 1 V applied voltage. The result shows promising usage of the synthesized rare earth oxides as gate dielectric where ideal κ-value and significant reduction of the leakage current by 5 orders of magnitude is achieved. Leakage current conduction mechanism for as-deposited sample is found to be dominated by Poole–Frenkel (PF) emission; the trap level is found to be at 1.29 eV whereas annealed samples (600 °C and 800 °C) exhibited Schottky emission with trap levels at 1.45 eV and 0.81 eV, respectively.

  9. Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

    Science.gov (United States)

    Consiglio, Steven P.

    To continue the rapid progress of the semiconductor industry as described by Moore's Law, the feasibility of new material systems for front end of the line (FEOL) process technologies needs to be investigated, since the currently employed polysilicon/SiO2-based transistor system is reaching its fundamental scaling limits. Revolutionary breakthroughs in complementary-metal-oxide-semiconductor (CMOS) technology were recently announced by Intel Corporation and International Business Machines Corporation (IBM), with both organizations revealing significant progress in the implementation of hafnium-based high-k dielectrics along with metal gates. This announcement was heralded by Gordon Moore as "...the biggest change in transistor technology since the introduction of polysilicon gate MOS transistors in the late 1960s." Accordingly, the study described herein focuses on the growth of Hf-based dielectrics and Hf-based metal gates using chemical vapor-based deposition methods, specifically metallorganic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). A family of Hf source complexes that has received much attention recently due to their desirable properties for implementation in wafer scale manufacturing is the Hf dialkylamide precursors. These precursors are room temperature liquids and possess sufficient volatility and desirable decomposition characteristics for both MOCVD and ALD processing. Another benefit of using these sources is the existence of chemically compatible Si dialkylamide sources as co-precursors for use in Hf silicate growth. The first part of this study investigates properties of MOCVD-deposited HfO2 and HfSixOy using dimethylamido Hf and Si precursor sources using a customized MOCVD reactor. The second part of this study involves a study of wet and dry surface pre-treatments for ALD growth of HfO2 using tetrakis(ethylmethylamido)hafnium in a wafer scale manufacturing environment. The third part of this study is an investigation of

  10. A comparative study on top-gated and bottom-gated multilayer MoS2 transistors with gate stacked dielectric of Al2O3/HfO2.

    Science.gov (United States)

    Zou, Xiao; Xu, Jingping; Huang, Hao; Zhu, Ziqang; Wang, Hongjiu; Li, Borui; Liao, Lei; Fang, Guojia

    2018-06-15

    Top-gated and bottom-gated transistors with multilayer MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 (9 nm/6 nm) were fabricated and comparatively studied. Excellent electrical properties are demonstrated for the TG transistors with high on-off current ratio of 10 8 , high field-effect mobility of 10 2 cm 2 V -1 s -1 , and low subthreshold swing of 93 mV dec -1 . Also, enhanced reliability has been achieved for the TG transistors with threshold voltage shift of 10 -3 -10 -2 V MV -1 cm -1 after 6 MV cm -1 gate-biased stressing. All improvement for the TG device can be ascribed to the formed device structure and dielectric environment. Degradation of the performance for the BG transistors should be attributed to reduced gate capacitance density and deteriorated interface properties related to vdW gap with a thickness about 0.4 nm. So, the TG transistor with MoS 2 channel fully encapsulated by stacked Al 2 O 3 /HfO 2 is a promising way to fabricate high-performance ML MoS 2 field-effect transistors for practical electron device applications.

  11. Thermal stability and chemical bonding states of AlOxNy/Si gate stacks revealed by synchrotron radiation photoemission spectroscopy

    International Nuclear Information System (INIS)

    He, G.; Toyoda, S.; Shimogaki, Y.; Oshima, M.

    2010-01-01

    Annealing-temperature dependence of the thermal stability and chemical bonding states of AlO x N y /SiO 2 /Si gate stacks grown by metalorganic chemical vapor deposition (MOCVD) using new chemistry was investigated by synchrotron radiation photoemission spectroscopy (SRPES). Results have confirmed the formation of the AlN and AlNO compounds in the as-deposited samples. Annealing the AlO x N y samples in N 2 ambient in 600-800 deg. C promotes the formation of SiO 2 component. Meanwhile, there is no formation of Al-O-Si and Al-Si binding states, suggesting no interdiffusion of Al with the Si substrate. A thermally induced reaction between Si and AlO x N y to form volatile SiO and Al 2 O is suggested to be responsible for the full disappearance of the Al component that accompanies annealing at annealing temperature of 1000 deg. C. The released N due to the breakage of the Al-N bonding will react with the SiO 2 interfacial layer and lead to the formation of the Si 3 -N-O/Si 2 -N-O components at the top of Si substrate. These results indicate high temperature processing induced evolution of the interfacial chemistry and application range of AlO x N y /Si gate stacks in future CMOS devices.

  12. AlN and Al oxy-nitride gate dielectrics for reliable gate stacks on Ge and InGaAs channels

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Y.; Li, H.; Robertson, J. [Engineering Department, Cambridge University, Cambridge CB2 1PZ (United Kingdom)

    2016-05-28

    AlN and Al oxy-nitride dielectric layers are proposed instead of Al{sub 2}O{sub 3} as a component of the gate dielectric stacks on higher mobility channels in metal oxide field effect transistors to improve their positive bias stress instability reliability. It is calculated that the gap states of nitrogen vacancies in AlN lie further away in energy from the semiconductor band gap than those of oxygen vacancies in Al{sub 2}O{sub 3}, and thus AlN might be less susceptible to charge trapping and have a better reliability performance. The unfavourable defect energy level distribution in amorphous Al{sub 2}O{sub 3} is attributed to its larger coordination disorder compared to the more symmetrically bonded AlN. Al oxy-nitride is also predicted to have less tendency for charge trapping.

  13. The electrical performance and gate bias stability of an amorphous InGaZnO thin-film transistor with HfO2 high-k dielectrics

    Science.gov (United States)

    Wang, Ruo Zheng; Wu, Sheng Li; Li, Xin Yu; Zhang, Jin Tao

    2017-07-01

    In this study, we set out to fabricate an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) with SiNx/HfO2/SiNx (SHS) sandwiched dielectrics. The J-V and C-V of this SHS film were extracted by the Au/p-Si/SHS/Ti structure. At room temperature the a-IGZO with SHS dielectrics showed the following electrical properties: a threshold voltage of 2.9 V, a subthreshold slope of 0.35 V/decade, an on/off current ratio of 3.5 × 107, and a mobility of 12.8 cm2 V-1 s-1. Finally, we tested the influence of gate bias stress on the TFT, and the result showed that the threshold voltage shifted to a positive voltage when applying a positive gate voltage to the TFT.

  14. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium–gallium–zinc oxide gate stack

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-01

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium–gallium–zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>104). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  15. Synaptic behaviors of thin-film transistor with a Pt/HfO x /n-type indium-gallium-zinc oxide gate stack.

    Science.gov (United States)

    Yang, Paul; Park, Daehoon; Beom, Keonwon; Kim, Hyung Jun; Kang, Chi Jung; Yoon, Tae-Sik

    2018-07-20

    We report a variety of synaptic behaviors in a thin-film transistor (TFT) with a metal-oxide-semiconductor gate stack that has a Pt/HfO x /n-type indium-gallium-zinc oxide (n-IGZO) structure. The three-terminal synaptic TFT exhibits a tunable synaptic weight with a drain current modulation upon repeated application of gate and drain voltages. The synaptic weight modulation is analog, voltage-polarity dependent reversible, and strong with a dynamic range of multiple orders of magnitude (>10 4 ). This modulation process emulates biological synaptic potentiation, depression, excitatory-postsynaptic current, paired-pulse facilitation, and short-term to long-term memory transition behaviors as a result of repeated pulsing with respect to the pulse amplitude, width, repetition number, and the interval between pulses. These synaptic behaviors are interpreted based on the changes in the capacitance of the Pt/HfO x /n-IGZO gate stack, the channel mobility, and the threshold voltage that result from the redistribution of oxygen ions by the applied gate voltage. These results demonstrate the potential of this structure for three-terminal synaptic transistor using the gate stack composed of the HfO x gate insulator and the IGZO channel layer.

  16. Temperature dependence of trapping effects in metal gates/Al2O3/InGaAs stacks

    Science.gov (United States)

    Palumbo, F.; Pazos, S.; Aguirre, F.; Winter, R.; Krylov, I.; Eizenberg, M.

    2017-06-01

    The influence of the temperature on Metal Gate/Al2O3/n-InGaAs stacks has been studied by means of capacitance-voltage (C-V) hysteresis and flat band voltage as function of both negative and positive stress fields. It was found that the de-trapping effect decreases at low-temperature, indicating that the de-trapping of trapped electrons from oxide traps may be performed via Al2O3/InGaAs interface defects. The dependence of the C-V hysteresis on the stress field at different temperatures in our InGaAs stacks can be explained in terms of the defect spatial distribution. An oxide defect distribution can be found very close to the metal gate/Al2O3 interface. On the other side, the Al2O3/InGaAs interface presents defects distributed from the interface into the bulk of the oxide, showing the influence of InGaAs on Al2O3 in terms of the spatial defect distribution. At the present, he is a research staff of the National Council of Science and Technology (CONICET), working in the National Commission of Atomic Energy (CNEA) in Buenos Aires, Argentina, well embedded within international research collaboration. Since 2008, he is Professor at the National Technological University (UTN) in Buenos Aires, Argentina. Dr. Palumbo has received research fellowships from: Marie Curie Fellowship within the 7th European Community Framework Programme, Abdus Salam International Centre for Theoretical Physics (ICTP) Italy, National Council of Science and Technology (CONICET) Argentina, and Consiglio Nazionale delle Ricerche (CNR) Italy. He is also a frequent scientific visitor of academic institutions as IMM-CNR-Italy, Minatec Grenoble-France, the Autonomous University of Barcelona-Spain, and the Israel Institute of Technology-Technion. He has authored and co-authored more than 50 papers in international conferences and journals.

  17. Gate-stack engineering for self-organized Ge-dot/SiO2/SiGe-shell MOS capacitors

    Directory of Open Access Journals (Sweden)

    Wei-Ting eLai

    2016-02-01

    Full Text Available We report the first-of-its-kind, self-organized gate-stack heterostructure of Ge-dot/SiO2/SiGe-shell on Si fabricated in a single step through the selective oxidation of a SiGe nano-patterned pillar over a Si3N4 buffer layer on a Si substrate. Process-controlled tunability of the Ge-dot size (7.5−90 nm, the SiO2 thickness (3−4 nm, and as well the SiGe-shell thickness (2−15 nm has been demonstrated, enabling a practically-achievable core building block for Ge-based metal-oxide-semiconductor (MOS devices. Detailed morphologies, structural, and electrical interfacial properties of the SiO2/Ge-dot and SiO2/SiGe interfaces were assessed using transmission electron microscopy, energy dispersive x-ray spectroscopy, and temperature-dependent high/low-frequency capacitance-voltage measurements. Notably, NiGe/SiO2/SiGe and Al/SiO2/Ge-dot/SiO2/SiGe MOS capacitors exhibit low interface trap densities of as low as 3-5x10^11 cm^-2·eV^-1 and fixed charge densities of 1-5x10^11 cm^-2, suggesting good-quality SiO2/SiGe-shell and SiO2/Ge-dot interfaces. In addition, the advantage of having single-crystalline Si1-xGex shell (x > 0.5 in a compressive stress state in our self-aligned gate-stack heterostructure has great promise for possible SiGe (or Ge MOS nanoelectronic and nanophotonic applications.

  18. Analysis of chemical bond states and electrical properties of stacked AlON/HfO{sub 2} gate oxides formed by using a layer-by-layer technique

    Energy Technology Data Exchange (ETDEWEB)

    Choi, Wonjoon; Lee, Jonghyun; Yang, Jungyup; Kim, Chaeok; Hong, Jinpyo; Nahm, Tschanguh; Byun, Byungsub; Kim, Moseok [Hanyang University, Seoul (Korea, Republic of)

    2006-06-15

    Stacked AlON/HfO{sub 2} thin films for gate oxides in metal-oxide-semiconductor devices are successfully prepared on Si substrates by utilizing a layer-by-layer technique integrated with an off-axis RF remote plasma sputtering process at room temperature. This off-axis structure is designed to improve the uniformity and the quality of gate oxide films. Also, a layer-by-layer technique is used to control the interface layer between the gate oxide and the Si substrate. The electrical properties of our stacked films are characterized by using capacitance versus voltage and leakage current versus voltage measurements. The stacked AlON/HfO{sub 2} gate oxide exhibits a low leakage current of about 10{sup -6} A/cm{sup 2} and a high dielectric constant value of 14.26 by effectively suppressing the interface layer between gate oxide and Si substrate. In addition, the chemical bond states and the optimum thickness of each AlON and HfO{sub 2} thin film are analyzed using X-ray photoemission spectroscopy and transmission electron microscopy measurement.

  19. SiO2/AlON stacked gate dielectrics for AlGaN/GaN MOS heterojunction field-effect transistors

    Science.gov (United States)

    Watanabe, Kenta; Terashima, Daiki; Nozaki, Mikito; Yamada, Takahiro; Nakazawa, Satoshi; Ishida, Masahiro; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    Stacked gate dielectrics consisting of wide bandgap SiO2 insulators and thin aluminum oxynitride (AlON) interlayers were systematically investigated in order to improve the performance and reliability of AlGaN/GaN metal–oxide–semiconductor (MOS) devices. A significantly reduced gate leakage current compared with that in a single AlON layer was achieved with these structures, while maintaining the superior thermal stability and electrical properties of the oxynitride/AlGaN interface. Consequently, distinct advantages in terms of the reliability of the gate dielectrics, such as an improved immunity against electron injection and an increased dielectric breakdown field, were demonstrated for AlGaN/GaN MOS capacitors with optimized stacked structures having a 3.3-nm-thick AlON interlayer.

  20. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.

    2011-10-12

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  1. Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits

    KAUST Repository

    Fahad, Hossain M.; Smith, Casey; Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2011-01-01

    We introduce the concept of a silicon nanotube field effect transistor whose unique core-shell gate stacks help achieve full volume inversion by giving a surge in minority carrier concentration in the near vicinity of the ultrathin channel and at the same time rapid roll-off at the source and drain junctions constituting velocity saturation-induced higher drive current-enhanced high performance per device with efficient real estate consumption. The core-shell gate stacks also provide superior short channel effects control than classical planar metal oxide semiconductor field effect transistor (MOSFET) and gate-all-around nanowire FET. The proposed device offers the true potential to be an ideal blend for quantum ballistic transport study of device property control by bottom-up approach and high-density integration compatibility using top-down state-of-the-art complementary metal oxide semiconductor flow. © 2011 American Chemical Society.

  2. Characterization, integration and reliability of HfO2 and LaLuO3 high-κ/metal gate stacks for CMOS applications

    International Nuclear Information System (INIS)

    Nichau, Alexander

    2013-01-01

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO 3 and HfO 2 are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO 3 and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO 3 is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO 3 on germanium, germanate formation is shown. LaLuO 3 is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO 3 in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO 3 and HfO 2 . Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO 2 gate stacks is scalable below 1 nm by the use of thinned interfacial SiO 2 . The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the gate electrode to decrease the EOT of HfO 2 gate stacks

  3. Characterization, integration and reliability of HfO{sub 2} and LaLuO{sub 3} high-κ/metal gate stacks for CMOS applications

    Energy Technology Data Exchange (ETDEWEB)

    Nichau, Alexander

    2013-07-15

    The continued downscaling of MOSFET dimensions requires an equivalent oxide thickness (EOT) of the gate stack below 1 nm. An EOT below 1.4 nm is hereby enabled by the use of high-κ/metal gate stacks. LaLuO{sub 3} and HfO{sub 2} are investigated as two different high-κ oxides on silicon in conjunction with TiN as the metal electrode. LaLuO{sub 3} and its temperature-dependent silicate formation are characterized by hard X-ray photoemission spectroscopy (HAXPES). The effective attenuation length of LaLuO{sub 3} is determined between 7 and 13 keV to enable future interface and diffusion studies. In a first investigation of LaLuO{sub 3} on germanium, germanate formation is shown. LaLuO{sub 3} is further integrated in a high-temperature MOSFET process flow with varying thermal treatment. The devices feature drive currents up to 70μA/μm at 1μm gate length. Several optimization steps are presented. The effective device mobility is related to silicate formation and thermal budget. At high temperature the silicate formation leads to mobility degradation due to La-rich silicate formation. The integration of LaLuO{sub 3} in high-T processes delicately connects with the optimization of the TiN metal electrode. Hereby, stoichiometric TiN yields the best results in terms of thermal stability with respect to Si-capping and high-κ oxide. Different approaches are presented for a further EOT reduction with LaLuO{sub 3} and HfO{sub 2}. Thereby the thermodynamic and kinetic predictions are employed to estimate the behavior on the nanoscale. Based on thermodynamics, excess oxygen in the gate stack, especially in oxidized metal electrodes, is identified to prevent EOT scaling below 1.2 nm. The equivalent oxide thickness of HfO{sub 2} gate stacks is scalable below 1 nm by the use of thinned interfacial SiO{sub 2}. The prevention of oxygen incorporation into the metal electrode by Si-capping maintains the EOT after high temperature annealing. Redox systems are employed within the

  4. Thermal response of Ru electrodes in contact with SiO2 and Hf-based high-k gate dielectrics

    International Nuclear Information System (INIS)

    Wen, H.-C.; Lysaght, P.; Alshareef, H.N.; Huffman, C.; Harris, H.R.; Choi, K.; Senzaki, Y.; Luan, H.; Majhi, P.; Lee, B.H.; Campin, M. J.; Foran, B.; Lian, G.D.; Kwong, D.-L.

    2005-01-01

    A systematic experimental evaluation of the thermal stability of Ru metal gate electrodes in direct contact with SiO 2 and Hf-based dielectric layers was performed and correlated with electrical device measurements. The distinctly different interfacial reactions in the Ru/SiO 2 , Ru/HfO 2 , and Ru/HfSiO x film systems were observed through cross-sectional high-resolution transmission electron microscopy, high angle annular dark field scanning transmission electron microscopy with electron-energy-loss spectra, and energy dispersive x-ray spectra analysis. Ru interacted with SiO 2 , but remained stable on HfO 2 at 1000 deg. C. The onset of Ru/SiO 2 interfacial interactions is identified via silicon substrate pitting possibly from Ru diffusion into the dielectric in samples exposed to a 900 deg. C/10-s anneal. The dependence of capacitor device degradation with decreasing SiO 2 thickness suggests Ru diffuses through SiO 2 , followed by an abrupt, rapid, nonuniform interaction of ruthenium silicide as Ru contacts the Si substrate. Local interdiffusion detected on Ru/HfSiO x samples may be due to phase separation of HfSiO x into HfO 2 grains within a SiO 2 matrix, suggesting that SiO 2 provides a diffusion pathway for Ru. Detailed evidence consistent with a dual reaction mechanism for the Ru/SiO 2 system at 1000 deg. C is presented

  5. Study on influences of TiN capping layer on time-dependent dielectric breakdown characteristic of ultra-thin EOT high- k metal gate NMOSFET with kMC TDDB simulations

    International Nuclear Information System (INIS)

    Xu Hao; Yang Hong; Luo Wei-Chun; Xu Ye-Feng; Wang Yan-Rong; Tang Bo; Wang Wen-Wu; Qi Lu-Wei; Li Jun-Feng; Yan Jiang; Zhu Hui-Long; Zhao Chao; Chen Da-Peng; Ye Tian-Chun

    2016-01-01

    The thickness effect of the TiN capping layer on the time dependent dielectric breakdown (TDDB) characteristic of ultra-thin EOT high- k metal gate NMOSFET is investigated in this paper. Based on experimental results, it is found that the device with a thicker TiN layer has a more promising reliability characteristic than that with a thinner TiN layer. From the charge pumping measurement and secondary ion mass spectroscopy (SIMS) analysis, it is indicated that the sample with the thicker TiN layer introduces more Cl passivation at the IL/Si interface and exhibits a lower interface trap density. In addition, the influences of interface and bulk trap density ratio N it / N ot are studied by TDDB simulations through combining percolation theory and the kinetic Monte Carlo (kMC) method. The lifetime reduction and Weibull slope lowering are explained by interface trap effects for TiN capping layers with different thicknesses. (paper)

  6. A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

    Science.gov (United States)

    Ishii, Yuichiro; Tanaka, Miki; Yabuuchi, Makoto; Sawada, Yohei; Tanaka, Shinji; Nii, Koji; Lu, Tien Yu; Huang, Chun Hsien; Sian Chen, Shou; Tse Kuo, Yu; Lung, Ching Cheng; Cheng, Osbert

    2018-04-01

    We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (I read) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (V min) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

  7. Lowering the environmental impact of high-kappa/ metal gate stack surface preparation processes

    Science.gov (United States)

    Zamani, Davoud

    ABSTRACT Hafnium based oxides and silicates are promising high-κ dielectrics to replace SiO2 as gate material for state-of-the-art semiconductor devices. However, integrating these new high-κ materials into the existing complementary metal-oxide semiconductor (CMOS) process remains a challenge. One particular area of concern is the use of large amounts of HF during wet etching of hafnium based oxides and silicates. The patterning of thin films of these materials is accomplished by wet etching in HF solutions. The use of HF allows dissolution of hafnium as an anionic fluoride complex. Etch selectivity with respect to SiO2 is achieved by appropriately diluting the solutions and using slightly elevated temperatures. From an ESH point of view, it would be beneficial to develop methods which would lower the use of HF. The first objective of this study is to find new chemistries and developments of new wet etch methods to reduce fluoride consumption during wet etching of hafnium based high-κ materials. Another related issue with major environmental impact is the usage of large amounts of rinsing water for removal of HF in post-etch cleaning step. Both of these require a better understanding of the HF interaction with the high-κ surface during the etching, cleaning, and rinsing processes. During the rinse, the cleaning chemical is removed from the wafers. Ensuring optimal resource usage and cycle time during the rinse requires a sound understanding and quantitative description of the transport effects that dominate the removal rate of the cleaning chemicals from the surfaces. Multiple processes, such as desorption and re-adsorption, diffusion, migration and convection, all factor into the removal rate of the cleaning chemical during the rinse. Any of these processes can be the removal rate limiting process, the bottleneck of the rinse. In fact, the process limiting the removal rate generally changes as the rinse progresses, offering the opportunity to save resources

  8. Effect of the post-deposition annealing on electrical characteristics of MIS structures with HfO{sub 2}/SiO{sub 2} gate dielectric stacks

    Energy Technology Data Exchange (ETDEWEB)

    Taube, Andrzej [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Mroczynski, Robert, E-mail: rmroczyn@elka.pw.edu.pl [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Korwin-Mikke, Katarzyna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Gieraltowska, Sylwia [Institute of Physics, Polish Academy of Sciences, Al. Lotnikow 32/46, 02-668 Warsaw (Poland); Szmidt, Jan [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology, Koszykowa 75, 00-662 Warsaw (Poland); Piotrowska, Anna [Institute of Electron Technology, Al. Lotnikow 32/46, 02-668 Warsaw (Poland)

    2012-09-01

    In this work, we report on effects of post-deposition annealing on electrical characteristics of metal-insulator-semiconductor (MIS) structures with HfO{sub 2}/SiO{sub 2} double gate dielectric stacks. Obtained results have shown the deterioration of electro-physical properties of MIS structures, e.g. higher interface traps density in the middle of silicon forbidden band (D{sub itmb}), as well as non-uniform distribution and decrease of breakdown voltage (U{sub br}) values, after annealing above 400 Degree-Sign C. Two potential hypothesis of such behavior were proposed: the formation of interfacial layer between hafnia and silicon dioxide and the increase of crystallinity of HfO{sub 2} due to the high temperature treatment. Furthermore, the analysis of conduction mechanisms in investigated stacks revealed Poole-Frenkel (P-F) tunneling at broad range of electric field intensity.

  9. I2 basal stacking fault as a degradation mechanism in reverse gate-biased AlGaN/GaN HEMTs

    Science.gov (United States)

    Lang, A. C.; Hart, J. L.; Wen, J. G.; Miller, D. J.; Meyer, D. J.; Taheri, M. L.

    2016-09-01

    Here, we present the observation of a bias-induced, degradation-enhancing defect process in plasma-assisted molecular beam epitaxy grown reverse gate-biased AlGaN/GaN high electron mobility transistors (HEMTs), which is compatible with the current theoretical framework of HEMT degradation. Specifically, we utilize both conventional transmission electron microscopy and aberration-corrected transmission electron microscopy to analyze microstructural changes in not only high strained regions in degraded AlGaN/GaN HEMTs but also the extended gate-drain access region. We find a complex defect structure containing an I2 basal stacking fault and offer a potential mechanism for device degradation based on this defect structure. This work supports the reality of multiple failure mechanisms during device operation and identifies a defect potentially involved with device degradation.

  10. Fermi level pinning in metal/Al{sub 2}O{sub 3}/InGaAs gate stack after post metallization annealing

    Energy Technology Data Exchange (ETDEWEB)

    Winter, R.; Krylov, I.; Cytermann, C.; Eizenberg, M. [Department of Materials Science and Engineering, Technion—Israel Institute of Technology, Haifa 32000 (Israel); Tang, K.; Ahn, J.; McIntyre, P. C. [Department of Materials Science and Engineering, Stanford University, Stanford, California 94305 (United States)

    2015-08-07

    The effect of post metal deposition annealing on the effective work function in metal/Al{sub 2}O{sub 3}/InGaAs gate stacks was investigated. The effective work functions of different metal gates (Al, Au, and Pt) were measured. Flat band voltage shifts for these and other metals studied suggest that their Fermi levels become pinned after the post-metallization vacuum annealing. Moreover, there is a difference between the measured effective work functions of Al and Pt, and the reported vacuum work function of these metals after annealing. We propose that this phenomenon is caused by charging of indium and gallium induced traps at the annealed metal/Al{sub 2}O{sub 3} interface.

  11. An EELS sub-nanometer investigation of the dielectric gate stack for the realization of InGaAs based MOSFET devices

    International Nuclear Information System (INIS)

    Longo, P; Paterson, G W; Craven, A J; Holland, M C; Thayne, I G

    2010-01-01

    In this paper, a subnanometer investigation of the Ga 2 O 3 /GdGaO dielectric gate stack deposited onto InGaAs is presented. Results regarding the influence of the growth conditions on the interface region from a chemical and morphological point of view are presented. The chemical information reported in this paper has been obtained using electron energy loss spectroscopy (EELS) that was carried out in a scanning transmission electron microscope ((S)TEM) showing both spatial and depth resolution.

  12. High-k shallow traps observed by charge pumping with varying discharging times

    International Nuclear Information System (INIS)

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen; Chang, Ting-Chang; Lu, Ying-Hsin; Lo, Wen-Hung; Tsai, Jyun-Yu; Liu, Kuan-Ju; Wang, Bin-Wei; Cao, Xi-Xin; Chen, Hua-Mao; Cheng, Osbert; Huang, Cheng-Tung; Chen, Tsai-Fu

    2013-01-01

    In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO 2 /metal gate stacks. N T -V high level characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N T for extra contribution of I cp traps. N T is the number of traps, and I cp is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I cp traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different Ti x N 1−x metal gate concentrations. Next, N T -V high level characteristic curves with different falling times (t falling time ) and base level times (t base level ) show that extra contribution of I cp traps decrease with an increase in t falling time . By fitting discharge formula for different t falling time , the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t falling time . This current cannot be measured by the charge pumping technique. Subsequent measurements of N T by charge pumping technique at t base level reveal a remainder of electrons trapped in high-k bulk shallow traps

  13. Physical and electrical characterizations of AlGaN/GaN MOS gate stacks with AlGaN surface oxidation treatment

    Science.gov (United States)

    Yamada, Takahiro; Watanabe, Kenta; Nozaki, Mikito; Shih, Hong-An; Nakazawa, Satoshi; Anda, Yoshiharu; Ueda, Tetsuzo; Yoshigoe, Akitaka; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji

    2018-06-01

    The impacts of inserting ultrathin oxides into insulator/AlGaN interfaces on their electrical properties were investigated to develop advanced AlGaN/GaN metal–oxide–semiconductor (MOS) gate stacks. For this purpose, the initial thermal oxidation of AlGaN surfaces in oxygen ambient was systematically studied by synchrotron radiation X-ray photoelectron spectroscopy (SR-XPS) and atomic force microscopy (AFM). Our physical characterizations revealed that, when compared with GaN surfaces, aluminum addition promotes the initial oxidation of AlGaN surfaces at temperatures of around 400 °C, followed by smaller grain growth above 850 °C. Electrical measurements of AlGaN/GaN MOS capacitors also showed that, although excessive oxidation treatment of AlGaN surfaces over around 700 °C has an adverse effect, interface passivation with the initial oxidation of the AlGaN surfaces at temperatures ranging from 400 to 500 °C was proven to be beneficial for fabricating high-quality AlGaN/GaN MOS gate stacks.

  14. High-k shallow traps observed by charge pumping with varying discharging times

    Energy Technology Data Exchange (ETDEWEB)

    Ho, Szu-Han; Chen, Ching-En; Tseng, Tseung-Yuen [Department of Electronics Engineering, National Chiao Tung University, Hsinchu 300, Taiwan (China); Chang, Ting-Chang, E-mail: tcchang@mail.phys.nsysu.edu.tw [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Advanced Optoelectronics Technology Center, National Cheng Kung University, Tainan, Taiwan (China); Lu, Ying-Hsin; Lo, Wen-Hung; Tsai, Jyun-Yu; Liu, Kuan-Ju [Department of Physics, National Sun Yat-Sen University, Kaohsiung 804, Taiwan (China); Wang, Bin-Wei; Cao, Xi-Xin [Department of Embedded System Engineering, Peking University, Beijing, P.R.China (China); Chen, Hua-Mao [Department of Photonics and Institute of Electro-Optical Engineering, National Chiao Tung University, Hsinchu, Taiwan (China); Cheng, Osbert; Huang, Cheng-Tung; Chen, Tsai-Fu [Device Department, United Microelectronics Corporation, Tainan Science Park, Taiwan (China)

    2013-11-07

    In this paper, we investigate the influence of falling time and base level time on high-k bulk shallow traps measured by charge pumping technique in n-channel metal-oxide-semiconductor field-effect transistors with HfO{sub 2}/metal gate stacks. N{sub T}-V{sub high} {sub level} characteristic curves with different duty ratios indicate that the electron detrapping time dominates the value of N{sub T} for extra contribution of I{sub cp} traps. N{sub T} is the number of traps, and I{sub cp} is charge pumping current. By fitting discharge formula at different temperatures, the results show that extra contribution of I{sub cp} traps at high voltage are in fact high-k bulk shallow traps. This is also verified through a comparison of different interlayer thicknesses and different Ti{sub x}N{sub 1−x} metal gate concentrations. Next, N{sub T}-V{sub high} {sub level} characteristic curves with different falling times (t{sub falling} {sub time}) and base level times (t{sub base} {sub level}) show that extra contribution of I{sub cp} traps decrease with an increase in t{sub falling} {sub time}. By fitting discharge formula for different t{sub falling} {sub time}, the results show that electrons trapped in high-k bulk shallow traps first discharge to the channel and then to source and drain during t{sub falling} {sub time}. This current cannot be measured by the charge pumping technique. Subsequent measurements of N{sub T} by charge pumping technique at t{sub base} {sub level} reveal a remainder of electrons trapped in high-k bulk shallow traps.

  15. Oxygen vacancy defect engineering using atomic layer deposited HfAlOx in multi-layered gate stack

    Science.gov (United States)

    Bhuyian, M. N.; Sengupta, R.; Vurikiti, P.; Misra, D.

    2016-05-01

    This work evaluates the defects in high quality atomic layer deposited (ALD) HfAlOx with extremely low Al (estimated by the high temperature current voltage measurement shows that the charged oxygen vacancies, V+/V2+, are the primary source of defects in these dielectrics. When Al is added in HfO2, the V+ type defects with a defect activation energy of Ea ˜ 0.2 eV modify to V2+ type to Ea ˜ 0.1 eV with reference to the Si conduction band. When devices were stressed in the gate injection mode for 1000 s, more V+ type defects are generated and Ea reverts back to ˜0.2 eV. Since Al has a less number of valence electrons than do Hf, the change in the co-ordination number due to Al incorporation seems to contribute to the defect level modifications. Additionally, the stress induced leakage current behavior observed at 20 °C and at 125 °C demonstrates that the addition of Al in HfO2 contributed to suppressed trap generation process. This further supports the defect engineering model as reduced flat-band voltage shifts were observed at 20 °C and at 125 °C.

  16. Evolution of interfacial Fermi level in In{sub 0.53}Ga{sub 0.47}As/high-κ/TiN gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Carr, Adra; Rozen, John; Frank, Martin M.; Ando, Takashi; Cartier, Eduard A.; Kerber, Pranita; Narayanan, Vijay; Haight, Richard [IBM T. J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598 (United States)

    2015-07-06

    The net charge state was probed of metal-oxide-semiconductor gate stacks consisting of In{sub 0.53}Ga{sub 0.47}As /high-κ dielectric/5 nm TiN, for both Al{sub 2}O{sub 3} and HfO{sub 2} dielectrics, via investigation of band bending at the InGaAs/high-κ interface. Using pump-probe photoelectron spectroscopy, changes to band bending were studied for each sequential layer deposited onto the InGaAs substrate and subsequent annealing up to 600 °C. Two behavioral regions were observed in annealing studies: (1) a lower temperature (<350 °C) region, attributed to changes at the high-κ/TiN interface, and (2) a higher temperature region (> 350 °C), associated with a net positive charge increase within the oxide. These band bending measurements delineate the impact of processing steps inherently inaccessible via capacitance-voltage electrical characterization.

  17. Modeling small-signal response of GaN-based metal-insulator-semiconductor high electron mobility transistor gate stack in spill-over regime: Effect of barrier resistance and interface states

    International Nuclear Information System (INIS)

    Capriotti, M.; Fleury, C.; Oposich, M.; Bethge, O.; Strasser, G.; Pogany, D.; Lagger, P.; Ostermaier, C.

    2015-01-01

    We provide theoretical and simulation analysis of the small signal response of SiO 2 /AlGaN/GaN metal insulator semiconductor (MIS) capacitors from depletion to spill over region, where the AlGaN/SiO 2 interface is accumulated with free electrons. A lumped element model of the gate stack, including the response of traps at the III-N/dielectric interface, is proposed and represented in terms of equivalent parallel capacitance, C p , and conductance, G p . C p -voltage and G p -voltage dependences are modelled taking into account bias dependent AlGaN barrier dynamic resistance R br and the effective channel resistance. In particular, in the spill-over region, the drop of C p with the frequency increase can be explained even without taking into account the response of interface traps, solely by considering the intrinsic response of the gate stack (i.e., no trap effects) and the decrease of R br with the applied forward bias. Furthermore, we show the limitations of the conductance method for the evaluation of the density of interface traps, D it , from the G p /ω vs. angular frequency ω curves. A peak in G p /ω vs. ω occurs even without traps, merely due to the intrinsic frequency response of gate stack. Moreover, the amplitude of the G p /ω vs. ω peak saturates at high D it , which can lead to underestimation of D it . Understanding the complex interplay between the intrinsic gate stack response and the effect of interface traps is relevant for the development of normally on and normally off MIS high electron mobility transistors with stable threshold voltage

  18. Microstructure and chemical analysis of Hf-based high-k dielectric layers in metal-insulator-metal capacitors

    Energy Technology Data Exchange (ETDEWEB)

    Thangadurai, P. [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Mikhelashvili, V.; Eisenstein, G. [Department of Electrical Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel); Kaplan, W.D., E-mail: kaplan@tx.technion.ac.i [Department of Materials Engineering, Technion - Israel Institute of Technology, Haifa 32000 (Israel)

    2010-05-31

    The microstructure and chemistry of the high-k gate dielectric significantly influences the performance of metal-insulator-metal (MIM) and metal-oxide-semiconductor devices. In particular, the local structure, chemistry, and inter-layer mixing are important phenomena to be understood. In the present study, high resolution and analytical transmission electron microscopy are combined to study the local structure, morphology, and chemistry in MIM capacitors containing a Hf-based high-k dielectric. The gate dielectric, bottom and gate electrodes were deposited on p-type Si(100) wafers by electron beam evaporation. Four chemically distinguishable sub-layers were identified within the dielectric stack. One is an unintentionally formed 4.0 nm thick interfacial layer of Ta{sub 2}O{sub 5} at the interface between the Ta electrode and the dielectric. The other three layers are based on HfN{sub x}O{sub y} and HfTiO{sub y}, and intermixing between the nearby sub-layers including deposited SiO{sub 2}. Hf-rich clusters were found in the HfN{sub x}O{sub y} layer adjacent to the Ta{sub 2}O{sub 5} layer.

  19. Fabrication and electrical properties of metal-oxide semiconductor capacitors based on polycrystalline p-Cu{sub x}O and HfO{sub 2}/SiO{sub 2} high-{kappa} stack gate dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Zou Xiao [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Department of Electromachine Engineering, Jianghan University, Wuhan, 430056 (China); Fang Guojia, E-mail: gjfang@whu.edu.c [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China); Yuan Longyan; Liu Nishuang; Long Hao; Zhao Xingzhong [Department of Electronic Science and Technology, School of Physical Science and Technology, Wuhan University, Wuhan, 430074 (China)

    2010-05-31

    Polycrystalline p-type Cu{sub x}O films were deposited after the growth of HfO{sub 2} dielectric on Si substrate by pulsed laser deposition, and Cu{sub x}O metal-oxide-semiconductor (MOS) capacitors with HfO{sub 2}/SiO{sub 2} stack gate dielectric were primarily fabricated and investigated. X-ray diffraction and X-ray photoelectron spectroscopy were applied to analyze crystalline structure and Cu{sup +}/Cu{sup 2+} ratios of Cu{sub x}O films respectively. SiO{sub 2} interlayer formed between the high-{kappa} dielectric and substrate was estimated by the transmission electron microscope. Results of electrical characteristic measurement indicate that the permittivity of HfO{sub 2} is about 22, and the gate leakage current density of MOS capacitor with 11.3 nm HfO{sub 2}/SiO{sub 2} stack dielectrics is {approx} 10{sup -4} A/cm{sup 2}. Results also show that the annealing in N{sub 2} can improve the quality of Cu{sub x}O/HfO{sub 2} interface and thus reduce the gate leakage density.

  20. Insights into thermal diffusion of germanium and oxygen atoms in HfO2/GeO2/Ge gate stacks and their suppressed reaction with atomically thin AlOx interlayers

    International Nuclear Information System (INIS)

    Ogawa, Shingo; Asahara, Ryohei; Minoura, Yuya; Hosoi, Takuji; Shimura, Takayoshi; Watanabe, Heiji; Sako, Hideki; Kawasaki, Naohiko; Yamada, Ichiko; Miyamoto, Takashi

    2015-01-01

    The thermal diffusion of germanium and oxygen atoms in HfO 2 /GeO 2 /Ge gate stacks was comprehensively evaluated by x-ray photoelectron spectroscopy and secondary ion mass spectrometry combined with an isotopic labeling technique. It was found that 18 O-tracers composing the GeO 2 underlayers diffuse within the HfO 2 overlayers based on Fick's law with the low activation energy of about 0.5 eV. Although out-diffusion of the germanium atoms through HfO 2 also proceeded at the low temperatures of around 200 °C, the diffusing germanium atoms preferentially segregated on the HfO 2 surfaces, and the reaction was further enhanced at high temperatures with the assistance of GeO desorption. A technique to insert atomically thin AlO x interlayers between the HfO 2 and GeO 2 layers was proven to effectively suppress both of these independent germanium and oxygen intermixing reactions in the gate stacks

  1. Insights into thermal diffusion of germanium and oxygen atoms in HfO{sub 2}/GeO{sub 2}/Ge gate stacks and their suppressed reaction with atomically thin AlO{sub x} interlayers

    Energy Technology Data Exchange (ETDEWEB)

    Ogawa, Shingo, E-mail: Shingo-Ogawa@trc.toray.co.jp [Toray Research Center, Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan); Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Asahara, Ryohei; Minoura, Yuya; Hosoi, Takuji, E-mail: hosoi@mls.eng.osaka-u.ac.jp; Shimura, Takayoshi; Watanabe, Heiji [Graduate School of Engineering, Osaka University, 2-1 Yamadaoka, Suita, Osaka 565-0871 (Japan); Sako, Hideki; Kawasaki, Naohiko; Yamada, Ichiko; Miyamoto, Takashi [Toray Research Center, Inc., 3-3-7 Sonoyama, Otsu, Shiga 520-8567 (Japan)

    2015-12-21

    The thermal diffusion of germanium and oxygen atoms in HfO{sub 2}/GeO{sub 2}/Ge gate stacks was comprehensively evaluated by x-ray photoelectron spectroscopy and secondary ion mass spectrometry combined with an isotopic labeling technique. It was found that {sup 18}O-tracers composing the GeO{sub 2} underlayers diffuse within the HfO{sub 2} overlayers based on Fick's law with the low activation energy of about 0.5 eV. Although out-diffusion of the germanium atoms through HfO{sub 2} also proceeded at the low temperatures of around 200 °C, the diffusing germanium atoms preferentially segregated on the HfO{sub 2} surfaces, and the reaction was further enhanced at high temperatures with the assistance of GeO desorption. A technique to insert atomically thin AlO{sub x} interlayers between the HfO{sub 2} and GeO{sub 2} layers was proven to effectively suppress both of these independent germanium and oxygen intermixing reactions in the gate stacks.

  2. USPIO-enhanced 3D-cine self-gated cardiac MRI based on a stack-of-stars golden angle short echo time sequence: Application on mice with acute myocardial infarction.

    Science.gov (United States)

    Trotier, Aurélien J; Castets, Charles R; Lefrançois, William; Ribot, Emeline J; Franconi, Jean-Michel; Thiaudière, Eric; Miraux, Sylvain

    2016-08-01

    To develop and assess a 3D-cine self-gated method for cardiac imaging of murine models. A 3D stack-of-stars (SOS) short echo time (STE) sequence with a navigator echo was performed at 7T on healthy mice (n = 4) and mice with acute myocardial infarction (MI) (n = 4) injected with ultrasmall superparamagnetic iron oxide (USPIO) nanoparticles. In all, 402 spokes were acquired per stack with the incremental or the golden angle method using an angle increment of (360/402)° or 222.48°, respectively. A cylindrical k-space was filled and repeated with a maximum number of repetitions (NR) of 10. 3D cine cardiac images at 156 μm resolution were reconstructed retrospectively and compared for the two methods in terms of contrast-to-noise ratio (CNR). The golden angle images were also reconstructed with NR = 10, 6, and 3, to assess cardiac functional parameters (ejection fraction, EF) on both animal models. The combination of 3D SOS-STE and USPIO injection allowed us to optimize the identification of cardiac peaks on navigator signal and generate high CNR between blood and myocardium (15.3 ± 1.0). The golden angle method resulted in a more homogeneous distribution of the spokes inside a stack (P cine images could be obtained without electrocardiogram or respiratory gating in mice. It allows precise measurement of cardiac functional parameters even on MI mice. J. Magn. Reson. Imaging 2016;44:355-365. © 2016 Wiley Periodicals, Inc.

  3. Stacking with stochastic cooling

    Energy Technology Data Exchange (ETDEWEB)

    Caspers, Fritz E-mail: Fritz.Caspers@cern.ch; Moehl, Dieter

    2004-10-11

    Accumulation of large stacks of antiprotons or ions with the aid of stochastic cooling is more delicate than cooling a constant intensity beam. Basically the difficulty stems from the fact that the optimized gain and the cooling rate are inversely proportional to the number of particles 'seen' by the cooling system. Therefore, to maintain fast stacking, the newly injected batch has to be strongly 'protected' from the Schottky noise of the stack. Vice versa the stack has to be efficiently 'shielded' against the high gain cooling system for the injected beam. In the antiproton accumulators with stacking ratios up to 10{sup 5} the problem is solved by radial separation of the injection and the stack orbits in a region of large dispersion. An array of several tapered cooling systems with a matched gain profile provides a continuous particle flux towards the high-density stack core. Shielding of the different systems from each other is obtained both through the spatial separation and via the revolution frequencies (filters). In the 'old AA', where the antiproton collection and stacking was done in one single ring, the injected beam was further shielded during cooling by means of a movable shutter. The complexity of these systems is very high. For more modest stacking ratios, one might use azimuthal rather than radial separation of stack and injected beam. Schematically half of the circumference would be used to accept and cool new beam and the remainder to house the stack. Fast gating is then required between the high gain cooling of the injected beam and the low gain stack cooling. RF-gymnastics are used to merge the pre-cooled batch with the stack, to re-create free space for the next injection, and to capture the new batch. This scheme is less demanding for the storage ring lattice, but at the expense of some reduction in stacking rate. The talk reviews the 'radial' separation schemes and also gives some

  4. Low-voltage high-speed programming gate-all-around floating gate memory cell with tunnel barrier engineering

    Science.gov (United States)

    Hamzah, Afiq; Ezaila Alias, N.; Ismail, Razali

    2018-06-01

    The aim of this study is to investigate the memory performances of gate-all-around floating gate (GAA-FG) memory cell implementing engineered tunnel barrier concept of variable oxide thickness (VARIOT) of low-k/high-k for several high-k (i.e., Si3N4, Al2O3, HfO2, and ZrO2) with low-k SiO2 using three-dimensional (3D) simulator Silvaco ATLAS. The simulation work is conducted by initially determining the optimized thickness of low-k/high-k barrier-stacked and extracting their Fowler–Nordheim (FN) coefficients. Based on the optimized parameters the device performances of GAA-FG for fast program operation and data retention are assessed using benchmark set by 6 and 8 nm SiO2 tunnel layer respectively. The programming speed has been improved and wide memory window with 30% increment from conventional SiO2 has been obtained using SiO2/Al2O3 tunnel layer due to its thin low-k dielectric thickness. Furthermore, given its high band edges only 1% of charge-loss is expected after 10 years of ‑3.6/3.6 V gate stress.

  5. Multi-gated field emitters for a micro-column

    International Nuclear Information System (INIS)

    Mimura, Hidenori; Kioke, Akifumi; Aoki, Toru; Neo, Yoichiro; Yoshida, Tomoya; Nagao, Masayoshi

    2011-01-01

    We have developed a multi-gated field emitter (FE) such as a quadruple-gated FE with a three-stacked electrode lens and a quintuple-gated FE with a four-stacked electrode lens. Both the FEs can focus the electron beam. However, the quintuple-gated FE has a stronger electron convergence than the quadruple-gated FE, and a beam crossover is clearly observed for the quintuple-gated FE.

  6. Algebraic stacks

    Indian Academy of Sciences (India)

    Deligne, Mumford and Artin [DM, Ar2]) and consider algebraic stacks, then we can cons- truct the 'moduli ... the moduli scheme and the moduli stack of vector bundles. First I will give ... 1–31. © Printed in India. 1 ...... Cultura, Spain. References.

  7. Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack

    Directory of Open Access Journals (Sweden)

    Shi-Bing Qian

    2015-12-01

    Full Text Available Amorphous indium-gallium-zinc oxide (a-IGZO thin-film transistor (TFT memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al2O3/Pt nanocrystals/Al2O3 gate stack under a maximal processing temperature of 300 oC. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 103 P/E cycles, and a memory window of 1.1 V was retained after 105 s retention time.

  8. Electrically programmable-erasable In-Ga-Zn-O thin-film transistor memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack

    Energy Technology Data Exchange (ETDEWEB)

    Qian, Shi-Bing; Zhang, Wen-Peng; Liu, Wen-Jun; Ding, Shi-Jin, E-mail: sjding@fudan.edu.cn [State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University, Shanghai 200433 (China)

    2015-12-15

    Amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) memory is very promising for transparent and flexible system-on-panel displays; however, electrical erasability has always been a severe challenge for this memory. In this article, we demonstrated successfully an electrically programmable-erasable memory with atomic-layer-deposited Al{sub 2}O{sub 3}/Pt nanocrystals/Al{sub 2}O{sub 3} gate stack under a maximal processing temperature of 300 {sup o}C. As the programming voltage was enhanced from 14 to 19 V for a constant pulse of 0.2 ms, the threshold voltage shift increased significantly from 0.89 to 4.67 V. When the programmed device was subjected to an appropriate pulse under negative gate bias, it could return to the original state with a superior erasing efficiency. The above phenomena could be attributed to Fowler-Nordheim tunnelling of electrons from the IGZO channel to the Pt nanocrystals during programming, and inverse tunnelling of the trapped electrons during erasing. In terms of 0.2-ms programming at 16 V and 350-ms erasing at −17 V, a large memory window of 3.03 V was achieved successfully. Furthermore, the memory exhibited stable repeated programming/erasing (P/E) characteristics and good data retention, i.e., for 2-ms programming at 14 V and 250-ms erasing at −14 V, a memory window of 2.08 V was still maintained after 10{sup 3} P/E cycles, and a memory window of 1.1 V was retained after 10{sup 5} s retention time.

  9. Fixed interface charges between AlGaN barrier and gate stack composed of in situ grown SiN and Al2O3 in AlGaN/GaN high electron mobility transistors with normally off capability

    International Nuclear Information System (INIS)

    Capriotti, M.; Alexewicz, A.; Fleury, C.; Gavagnin, M.; Bethge, O.; Wanzenböck, H. D.; Bertagnolli, E.; Pogany, D.; Strasser, G.; Visalli, D.; Derluyn, J.

    2014-01-01

    Using a generalized extraction method, the fixed charge density N int at the interface between in situ deposited SiN and 5 nm thick AlGaN barrier is evaluated by measurements of threshold voltage V th of an AlGaN/GaN metal insulator semiconductor high electron mobility transistor as a function of SiN thickness. The thickness of the originally deposited 50 nm thick SiN layer is reduced by dry etching. The extracted N int is in the order of the AlGaN polarization charge density. The total removal of the in situ SiN cap leads to a complete depletion of the channel region resulting in V th  = +1 V. Fabrication of a gate stack with Al 2 O 3 as a second cap layer, deposited on top of the in situ SiN, is not introducing additional fixed charges at the SiN/Al 2 O 3 interface

  10. Fabrication of Nonvolatile Memory Effects in High-k Dielectric Thin Films Using Electron Irradiation

    International Nuclear Information System (INIS)

    Park, Chanrock; Cho, Daehee; Kim, Jeongeun; Hwang, Jinha

    2010-01-01

    Electron Irradiation can be applied towards nano-floating gate memories which are recognized as one of the next-generation nonvolatile memory semiconductors. NFGMs can overcome the preexisting limitations encountered in Dynamic Random Access Memories and Flash memories with the excellent advantages, i. e. high-density information storage, high response speed, high compactness, etc. The traditional nano-floating gate memories are fabricated through multi-layered nano structures of the dissimilar materials where the charge-trapping portions are sandwiched into the high-k dielectrics. However, this work reports the unique nonvolatile responses in single-layered high-k dielectric thin films if irradiated with highly accelerated electron beams. The implications of the electron irradiation will be discussed towards high-performance nano-floating gate memories

  11. Suppression of subthreshold characteristics variation for junctionless multigate transistors using high-k spacers

    International Nuclear Information System (INIS)

    Lou, Haijun; Zhang, Baili; Li, Dan; Lin, Xinnan; He, Jin; Chan, Mansun

    2015-01-01

    In this work, the high-k spacer is proposed to suppress the subthreshold characteristics variation of junctionless multigate transistor (JMT) with non-ideal sidewall angle for the first time. It is demonstrated that the variation of subthreshold characteristics induced by the changing sidewall angle is efficiently suppressed by high-k spacers due to the enhanced corner effect through the fringe capacitance, and the electrostatic integrity of JMTs is also improved at sub-22 nm gate length. Two key parameters of high-k spacer, the thickness and length, have been optimized in terms of the suppression of subthreshold characteristics variation. Then their optimal values are proposed. The benefit of high-k spacer makes JMTs more scalable. (paper)

  12. High-K Strategy Scale: A Measure of the High-K Independent Criterion of Fitness

    Directory of Open Access Journals (Sweden)

    Cezar Giosan

    2006-01-01

    Full Text Available The present study aimed at testing whether factors documented in the literature as being indicators of a high-K reproductive strategy have effects on fitness in extant humans. A 26-item High-K Strategy Scale comprising these factors was developed and tested on 250 respondents. Items tapping into health and attractiveness, upward mobility, social capital and risks consideration, were included in the scale. As expected, the scale showed a significant correlation with perceived offspring quality and a weak, but significant association with actual number of children. The scale had a high reliability coefficient (Cronbach's Alpha = .92. Expected correlations were found between the scale and number of medical diagnoses, education, perceived social support, and number of previous marriages, strengthening the scale's construct validity. Implications of the results are discussed.

  13. Transparently wrap-gated semiconductor nanowire arrays for studies of gate-controlled photoluminescence

    Energy Technology Data Exchange (ETDEWEB)

    Nylund, Gustav; Storm, Kristian; Torstensson, Henrik; Wallentin, Jesper; Borgström, Magnus T.; Hessman, Dan; Samuelson, Lars [Solid State Physics, Nanometer Structure Consortium, Lund University, Box 118, S-221 00 Lund (Sweden)

    2013-12-04

    We present a technique to measure gate-controlled photoluminescence (PL) on arrays of semiconductor nanowire (NW) capacitors using a transparent film of Indium-Tin-Oxide (ITO) wrapping around the nanowires as the gate electrode. By tuning the wrap-gate voltage, it is possible to increase the PL peak intensity of an array of undoped InP NWs by more than an order of magnitude. The fine structure of the PL spectrum reveals three subpeaks whose relative peak intensities change with gate voltage. We interpret this as gate-controlled state-filling of luminescing quantum dot segments formed by zincblende stacking faults in the mainly wurtzite NW crystal structure.

  14. New theory of effective work functions at metal/high-k dielectric interfaces : application to metal/high-k HfO2 and la2O 3 dielectric interfaces

    OpenAIRE

    Shiraishi, Kenji; Nakayama, Takashi; Akasaka, Yasushi; Miyazaki, Seiichi; Nakaoka, Takashi; Ohmori, Kenji; Ahmet, Parhat; Torii, Kazuyoshi; Watanabe, Heiji; Chikyow, Toyohiro; Nara, Yasuo; Iwai, Hiroshi; Yamada, Keisaku

    2006-01-01

    We have constructed a universal theory of the work functions at metal/high-k HfO2 and La2O3 dielectric interfaces by introducing a new concept of generalized charge neutrality levels. Our theory systematically reproduces the experimentally observed work functions of various gate metals on Hf-based high-k dielectrics, including the hitherto unpredictable behaviors of the work functions of p-metals. Our new concept provides effective guiding principles to achieving near-bandedge work functions ...

  15. Linear gate

    International Nuclear Information System (INIS)

    Suwono.

    1978-01-01

    A linear gate providing a variable gate duration from 0,40μsec to 4μsec was developed. The electronic circuity consists of a linear circuit and an enable circuit. The input signal can be either unipolar or bipolar. If the input signal is bipolar, the negative portion will be filtered. The operation of the linear gate is controlled by the application of a positive enable pulse. (author)

  16. Using KrF ELA to Improve Gate-Stacked LaAlO₃/ZrO₂ Indium Gallium Zinc Oxide Thin-Film Transistors with Novel Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition Technique.

    Science.gov (United States)

    Wu, Chien-Hung; Chang, Kow-Ming; Chen, Yi-Ming; Huang, Bo-Wen; Zhang, Yu-Xin; Wang, Shui-Jinn

    2018-03-01

    Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) technique and KrF excimer laser annealing (ELA) were employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO-TFTs). Device with a 150 mJ/cm2 laser annealing densities demonstrated excellent electrical characteristics with improved on/off current ratio of 4.7×107, high channel mobility of 10 cm2/V-s, and low subthreshold swing of 0.15 V/dec. The improvements are attributed to the adjustment of oxygen vacancies in the IGZO channel to an appropriate range of around 28.3% and the reduction of traps at the high-k/IGZO interface.

  17. Ge{sub 0.83}Sn{sub 0.17} p-channel metal-oxide-semiconductor field-effect transistors: Impact of sulfur passivation on gate stack quality

    Energy Technology Data Exchange (ETDEWEB)

    Lei, Dian; Wang, Wei; Gong, Xiao, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org; Liang, Gengchiau; Yeo, Yee-Chia, E-mail: elegong@nus.edu.sg, E-mail: yeo@ieee.org [Department of Electrical and Computer Engineering, National University of Singapore, Singapore 117576 (Singapore); Zhang, Zheng; Pan, Jisheng [Institute of Material Research and Engineering, A*STAR (Agency for Science, Technology and Research), 3 Research Link, Singapore 117602 (Singapore); Tok, Eng-Soon [Department of Physics, National University of Singapore, Singapore 117551 (Singapore)

    2016-01-14

    The effect of room temperature sulfur passivation of the surface of Ge{sub 0.83}Sn{sub 0.17} prior to high-k dielectric (HfO{sub 2}) deposition is investigated. X-ray photoelectron spectroscopy (XPS) was used to examine the chemical bonding at the interface of HfO{sub 2} and Ge{sub 0.83}Sn{sub 0.17}. Sulfur passivation is found to be effective in suppressing the formation of both Ge oxides and Sn oxides. A comparison of XPS results for sulfur-passivated and non-passivated Ge{sub 0.83}Sn{sub 0.17} samples shows that sulfur passivation of the GeSn surface could also suppress the surface segregation of Sn atoms. In addition, sulfur passivation reduces the interface trap density D{sub it} at the high-k dielectric/Ge{sub 0.83}Sn{sub 0.17} interface from the valence band edge to the midgap of Ge{sub 0.83}Sn{sub 0.17}, as compared with a non-passivated control. The impact of the improved D{sub it} is demonstrated in Ge{sub 0.83}Sn{sub 0.17} p-channel metal-oxide-semiconductor field-effect transistors (p-MOSFETs). Ge{sub 0.83}Sn{sub 0.17} p-MOSFETs with sulfur passivation show improved subthreshold swing S, intrinsic transconductance G{sub m,int}, and effective hole mobility μ{sub eff} as compared with the non-passivated control. At a high inversion carrier density N{sub inv} of 1 × 10{sup 13 }cm{sup −2}, sulfur passivation increases μ{sub eff} by 25% in Ge{sub 0.83}Sn{sub 0.17} p-MOSFETs.

  18. Structural and optical properties of germanium nanostructures on Si(100 and embedded in high-k oxides

    Directory of Open Access Journals (Sweden)

    Ray Samit

    2011-01-01

    Full Text Available Abstract The structural and optical properties of Ge quantum dots (QDs grown on Si(001 for mid-infrared photodetector and Ge nanocrystals embedded in oxide matrices for floating gate memory devices are presented. The infrared photoluminescence (PL signal from Ge islands has been studied at a low temperature. The temperature- and bias-dependent photocurrent spectra of a capped Si/SiGe/Si(001 QDs infrared photodetector device are presented. The properties of Ge nanocrystals of different size and density embedded in high-k matrices grown using radio frequency magnetron sputtering have been studied. Transmission electron micrographs have revealed the formation of isolated spherical Ge nanocrystals in high-k oxide matrix of sizes ranging from 4 to 18 nm. Embedded nanocrystals in high band gap oxides have been found to act as discrete trapping sites for exchanging charge carriers with the conduction channel by direct tunneling that is desired for applications in floating gate memory devices.

  19. Flexible semi-transparent silicon (100) fabric with high-k/metal gate devices

    KAUST Repository

    Rojas, Jhonathan Prieto; Hussain, Muhammad Mustafa

    2013-01-01

    (100) wafers and then released as continuous, mechanically flexible, optically semi-transparent and high thermal budget compatible silicon fabric with devices. This is the first ever demonstration with this set of materials which allows full degree

  20. High-k dielectrics as bioelectronic interface for field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Borstlap, D

    2007-03-15

    Ion-sensitive field-effect transistors (ISFETs) are employed as bioelectronic sensors for the cell-transistor coupling and for the detection of DNA sequences. For these applications, thermally grown SiO{sub 2} films are used as standard gate dielectric. In the first part of this dissertation, the suitability of high-k dielectrics was studied to increase the gate capacitance and hence the signal-to-noise ratio of bioelectronic ISFETs: Upon culturing primary rat neurons on the corresponding high-k dielectrics, Al{sub 2}O{sub 3}, yttria stabilised zirkonia (YSZ), DyScO{sub 3}, CeO{sub 2}, LaAlO{sub 3}, GdScO{sub 3} and LaScO{sub 3} proved to be biocompatible substrates. Comprehensive electrical and electrochemical current-voltage measurements and capacitance-voltage measurements were performed for the determination of the dielectric properties of the high-k dielectrics. In the second part of the dissertation, standard SiO{sub 2} ISFETs with lower input capacitance and high-k dielectric Al{sub 2}O{sub 3}, YSZ und DyScO{sub 3} ISFETs were comprehensively characterised and compared with each other regarding their signal-to-noise ratio, their ion sensitivity and their drift behaviour. The ion sensitivity measurements showed that the YSZ ISFETs were considerably more sensitive to K{sup +} and Na{sup +} ions than the SiO{sub 2}, Al{sub 2}O{sub 3} und DyScO{sub 3} ISFETs. In the final third part of the dissertation, bioelectronic experiments were performed with the high-k ISFETs. The shape of the signals, which were measured from HL-1 cells with YSZ ISFETs, differed considerably from the corresponding measurements with SiO{sub 2} and DyScO{sub 3} ISFETs: After the onset of the K{sup +} current, the action potentials measured with YSZ ISFETs showed a strong drift in the direction opposite to the K{sup +} current signal. First coupling experiments between HEK 293 cells, which were transfected with a K{sup +} ion channel, and YSZ ISFETs affirmed the assumption from the HL-1

  1. Characterization of epitaxial GaAs MOS capacitors using atomic layer-deposited TiO2/Al2O3 gate stack: study of Ge auto-doping and p-type Zn doping.

    Science.gov (United States)

    Dalapati, Goutam Kumar; Shun Wong, Terence Kin; Li, Yang; Chia, Ching Kean; Das, Anindita; Mahata, Chandreswar; Gao, Han; Chattopadhyay, Sanatan; Kumar, Manippady Krishna; Seng, Hwee Leng; Maiti, Chinmay Kumar; Chi, Dong Zhi

    2012-02-02

    Electrical and physical properties of a metal-oxide-semiconductor [MOS] structure using atomic layer-deposited high-k dielectrics (TiO2/Al2O3) and epitaxial GaAs [epi-GaAs] grown on Ge(100) substrates have been investigated. The epi-GaAs, either undoped or Zn-doped, was grown using metal-organic chemical vapor deposition method at 620°C to 650°C. The diffusion of Ge atoms into epi-GaAs resulted in auto-doping, and therefore, an n-MOS behavior was observed for undoped and Zn-doped epi-GaAs with the doping concentration up to approximately 1017 cm-3. This is attributed to the diffusion of a significant amount of Ge atoms from the Ge substrate as confirmed by the simulation using SILVACO software and also from the secondary ion mass spectrometry analyses. The Zn-doped epi-GaAs with a doping concentration of approximately 1018 cm-3 converts the epi-GaAs layer into p-type since the Zn doping is relatively higher than the out-diffused Ge concentration. The capacitance-voltage characteristics show similar frequency dispersion and leakage current for n-type and p-type epi-GaAs layers with very low hysteresis voltage (approximately 10 mV).PACS: 81.15.Gh.

  2. From surface to volume plasmons in hyperbolic metamaterials: General existence conditions for bulk high-k waves in metal-dielectric and graphene-dielectric multilayers

    DEFF Research Database (Denmark)

    Zhukovsky, Sergei; Andryieuski, Andrei; Sipe, John E.

    2014-01-01

    -dielectric and recently introduced graphene-dielectric stacks. We confirm that short-range surface plasmons in thin metal layers can give rise to hyperbolic metamaterial properties and demonstrate that long-range surface plasmons cannot. We also show that graphene-dielectric multilayers tend to support high- k waves...

  3. Investigation of capacitance characteristics in metal/high-k ...

    Indian Academy of Sciences (India)

    MS received 4 May 2016; accepted 10 January 2017; published online 21 August 2017. Abstract. Capacitance vs. ... with high-k materials is the prime technological challenge. [2]. ... reliability of MOS devices are strongly dependent on the for-.

  4. High-Density Stacked Ru Nanocrystals for Nonvolatile Memory Application

    International Nuclear Information System (INIS)

    Ping, Mao; Zhi-Gang, Zhang; Li-Yang, Pan; Jun, Xu; Pei-Yi, Chen

    2009-01-01

    Stacked ruthenium (Ru) nanocrystals (NCs) are formed by rapid thermal annealing for the whole gate stacks and embedded in memory structure, which is compatible with conventional CMOS technology. Ru NCs with high density (3 × 10 12 cm −2 ), small size (2–4 nm) and good uniformity both in aerial distribution and morphology are formed. Attributed to the higher surface trap density, a memory window of 5.2 V is obtained with stacked Ru NCs in comparison to that of 3.5 V with single-layer samples. The stacked Ru NCs device also exhibits much better retention performance because of Coulomb blockade and vertical uniformity between stacked Ru NCs

  5. OpenStack essentials

    CERN Document Server

    Radez, Dan

    2015-01-01

    If you need to get started with OpenStack or want to learn more, then this book is your perfect companion. If you're comfortable with the Linux command line, you'll gain confidence in using OpenStack.

  6. Stack gas treatment

    Science.gov (United States)

    Reeves, Adam A.

    1977-04-12

    Hot stack gases transfer contained heat to a gravity flow of pebbles treated with a catalyst, cooled stacked gases and a sulfuric acid mist is withdrawn from the unit, and heat picked up by the pebbles is transferred to air for combustion or other process. The sulfuric acid (or sulfur, depending on the catalyst) is withdrawn in a recovery unit.

  7. Mastering OpenStack

    CERN Document Server

    Khedher, Omar

    2015-01-01

    This book is intended for system administrators, cloud engineers, and system architects who want to deploy a cloud based on OpenStack in a mid- to large-sized IT infrastructure. If you have a fundamental understanding of cloud computing and OpenStack and want to expand your knowledge, then this book is an excellent checkpoint to move forward.

  8. Emerging Applications for High K Materials in VLSI Technology

    Science.gov (United States)

    Clark, Robert D.

    2014-01-01

    The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI) manufacturing for leading edge Dynamic Random Access Memory (DRAM) and Complementary Metal Oxide Semiconductor (CMOS) applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM) diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD) is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing. PMID:28788599

  9. Emerging Applications for High K Materials in VLSI Technology

    Directory of Open Access Journals (Sweden)

    Robert D. Clark

    2014-04-01

    Full Text Available The current status of High K dielectrics in Very Large Scale Integrated circuit (VLSI manufacturing for leading edge Dynamic Random Access Memory (DRAM and Complementary Metal Oxide Semiconductor (CMOS applications is summarized along with the deposition methods and general equipment types employed. Emerging applications for High K dielectrics in future CMOS are described as well for implementations in 10 nm and beyond nodes. Additional emerging applications for High K dielectrics include Resistive RAM memories, Metal-Insulator-Metal (MIM diodes, Ferroelectric logic and memory devices, and as mask layers for patterning. Atomic Layer Deposition (ALD is a common and proven deposition method for all of the applications discussed for use in future VLSI manufacturing.

  10. Radiation-Tolerant Intelligent Memory Stack - RTIMS

    Science.gov (United States)

    Ng, Tak-kwong; Herath, Jeffrey A.

    2011-01-01

    This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

  11. Stacking the Equiangular Spiral

    OpenAIRE

    Agrawal, A.; Azabi, Y. O.; Rahman, B. M.

    2013-01-01

    We present an algorithm that adapts the mature Stack and Draw (SaD) methodology for fabricating the exotic Equiangular Spiral Photonic Crystal Fiber. (ES-PCF) The principle of Steiner chains and circle packing is exploited to obtain a non-hexagonal design using a stacking procedure based on Hexagonal Close Packing. The optical properties of the proposed structure are promising for SuperContinuum Generation. This approach could make accessible not only the equiangular spiral but also other qua...

  12. Investigation of 6T SRAM memory circuit using high-k dielectrics based nano scale junctionless transistor

    Science.gov (United States)

    Charles Pravin, J.; Nirmal, D.; Prajoon, P.; Mohan Kumar, N.; Ajayan, J.

    2017-04-01

    In this paper the Dual Metal Surround Gate Junctionless Transistor (DMSGJLT) has been implemented with various high-k dielectric. The leakage current in the device is analysed in detail by obtaining the band structure for different high-k dielectric material. It is noticed that with increasing dielectric constant the device provides more resistance for the direct tunnelling of electron in off state. The gate oxide capacitance also shows 0.1 μF improvement with Hafnium Oxide (HfO2) than Silicon Oxide (SiO2). This paved the way for a better memory application when high-k dielectric is used. The Six Transistor (6T) Static Random Access Memory (SRAM) circuit implemented shows 41.4% improvement in read noise margin for HfO2 than SiO2. It also shows 37.49% improvement in write noise margin and 30.16% improvement in hold noise margin for HfO2 than SiO2.

  13. Investigation of capacitance characteristics in metal/high-k

    Indian Academy of Sciences (India)

    Keywords. C − V characteristic; high-k dielectric; interface state density; MIS structure; nanotechnology; TCAD simulation. Abstract. Capacitance vs. voltage ( C − V ) curves at AC high frequency of a metal–insulator–semiconductor (MIS) capacitorare investigated in this paper. Bi-dimensional simulations with Silvaco TCAD ...

  14. Towards stacked zone plates

    International Nuclear Information System (INIS)

    Werner, S; Rehbein, S; Guttman, P; Heim, S; Schneider, G

    2009-01-01

    Fresnel zone plates are the key optical elements for soft and hard x-ray microscopy. For short exposure times and minimum radiation load of the specimen the diffraction efficiency of the zone plate objectives has to be maximized. As the efficiency strongly depends on the height of the diffracting zone structures the achievable aspect ratio of the nanostructures determines these limits. To reach aspect ratios ≥ 20:1 for high efficient optics we propose to superimpose zone plates on top of each other. With this multiplication approach the final aspect ratio is only limited by the number of stacked zone plate layers. For the stack process several nanostructuring process steps have to be developed and/or improved. Our results show for the first time two layers of zone plates stacked on top of each other.

  15. Stochastic stacking without filters

    International Nuclear Information System (INIS)

    Johnson, R.P.; Marriner, J.

    1982-12-01

    The rate of accumulation of antiprotons is a critical factor in the design of p anti p colliders. A design of a system to accumulate higher anti p fluxes is presented here which is an alternative to the schemes used at the CERN AA and in the Fermilab Tevatron I design. Contrary to these stacking schemes, which use a system of notch filters to protect the dense core of antiprotons from the high power of the stack tail stochastic cooling, an eddy current shutter is used to protect the core in the region of the stack tail cooling kicker. Without filters one can have larger cooling bandwidths, better mixing for stochastic cooling, and easier operational criteria for the power amplifiers. In the case considered here a flux of 1.4 x 10 8 per sec is achieved with a 4 to 8 GHz bandwidth

  16. Stack filter classifiers

    Energy Technology Data Exchange (ETDEWEB)

    Porter, Reid B [Los Alamos National Laboratory; Hush, Don [Los Alamos National Laboratory

    2009-01-01

    Just as linear models generalize the sample mean and weighted average, weighted order statistic models generalize the sample median and weighted median. This analogy can be continued informally to generalized additive modeels in the case of the mean, and Stack Filters in the case of the median. Both of these model classes have been extensively studied for signal and image processing but it is surprising to find that for pattern classification, their treatment has been significantly one sided. Generalized additive models are now a major tool in pattern classification and many different learning algorithms have been developed to fit model parameters to finite data. However Stack Filters remain largely confined to signal and image processing and learning algorithms for classification are yet to be seen. This paper is a step towards Stack Filter Classifiers and it shows that the approach is interesting from both a theoretical and a practical perspective.

  17. Laser pulse stacking method

    Science.gov (United States)

    Moses, E.I.

    1992-12-01

    A laser pulse stacking method is disclosed. A problem with the prior art has been the generation of a series of laser beam pulses where the outer and inner regions of the beams are generated so as to form radially non-synchronous pulses. Such pulses thus have a non-uniform cross-sectional area with respect to the outer and inner edges of the pulses. The present invention provides a solution by combining the temporally non-uniform pulses in a stacking effect to thus provide a more uniform temporal synchronism over the beam diameter. 2 figs.

  18. Learning SaltStack

    CERN Document Server

    Myers, Colton

    2015-01-01

    If you are a system administrator who manages multiple servers, then you know how difficult it is to keep your infrastructure in line. If you've been searching for an easier way, this book is for you. No prior experience with SaltStack is required.

  19. Stress-induced leakage current characteristics of PMOS fabricated by a new multi-deposition multi-annealing technique with full gate last process

    International Nuclear Information System (INIS)

    Wang Yanrong; Yang Hong; Xu Hao; Luo Weichun; Qi Luwei; Zhang Shuxiang; Wang Wenwu; Zhu Huilong; Zhao Chao; Chen Dapeng; Ye Tianchun; Yan Jiang

    2017-01-01

    In the process of high- k films fabrication, a novel multi deposition multi annealing (MDMA) technique is introduced to replace simple post deposition annealing. The leakage current decreases with the increase of the post deposition annealing (PDA) times. The equivalent oxide thickness (EOT) decreases when the annealing time(s) change from 1 to 2. Furthermore, the characteristics of SILC (stress-induced leakage current) for an ultra-thin SiO 2 /HfO 2 gate dielectric stack are studied systematically. The increase of the PDA time(s) from 1 to 2 can decrease the defect and defect generation rate in the HK layer. However, increasing the PDA times to 4 and 7 may introduce too much oxygen, therefore the type of oxygen vacancy changes. (paper)

  20. Atomic layer deposition of crystalline SrHfO3 directly on Ge (001) for high-k dielectric applications

    International Nuclear Information System (INIS)

    McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G.; Hu, Chengqing; Jiang, Aiting; Yu, Edward T.; Lu, Sirong; Smith, David J.; Posadas, Agham; Demkov, Alexander A.

    2015-01-01

    The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO 3 (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10 −5 A/cm 2 at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D it ) is estimated to be as low as ∼2 × 10 12  cm −2  eV −1 under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D it value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications

  1. OpenStack cloud security

    CERN Document Server

    Locati, Fabio Alessandro

    2015-01-01

    If you are an OpenStack administrator or developer, or wish to build solutions to protect your OpenStack environment, then this book is for you. Experience of Linux administration and familiarity with different OpenStack components is assumed.

  2. Stacked magnet superconducting bearing

    International Nuclear Information System (INIS)

    Rigney, T.K. II; Saville, M.P.

    1993-01-01

    A superconducting bearing is described, comprising: a plurality of permanent magnets magnetized end-to-end and stacked side-by-side in alternating polarity, such that flux lines flow between ends of adjacent magnets; isolating means, disposed between said adjacent magnets, for reducing flux leakage between opposing sides of said adjacent magnets; and a member made of superconducting material having at least one surface in communication with said flux lines

  3. Iridium Interfacial Stack (IRIS)

    Science.gov (United States)

    Spry, David James (Inventor)

    2015-01-01

    An iridium interfacial stack ("IrIS") and a method for producing the same are provided. The IrIS may include ordered layers of TaSi.sub.2, platinum, iridium, and platinum, and may be placed on top of a titanium layer and a silicon carbide layer. The IrIS may prevent, reduce, or mitigate against diffusion of elements such as oxygen, platinum, and gold through at least some of its layers.

  4. Integration of atomic layer deposited high-k dielectrics on GaSb via hydrogen plasma exposure

    Directory of Open Access Journals (Sweden)

    Laura B. Ruppalt

    2014-12-01

    Full Text Available In this letter we report the efficacy of a hydrogen plasma pretreatment for integrating atomic layer deposited (ALD high-k dielectric stacks with device-quality p-type GaSb(001 epitaxial layers. Molecular beam eptiaxy-grown GaSb surfaces were subjected to a 30 minute H2/Ar plasma treatment and subsequently removed to air. High-k HfO2 and Al2O3/HfO2 bilayer insulating films were then deposited via ALD and samples were processed into standard metal-oxide-semiconductor (MOS capacitors. The quality of the semiconductor/dielectric interface was probed by current-voltage and variable-frequency admittance measurements. Measurement results indicate that the H2-plamsa pretreatment leads to a low density of interface states nearly independent of the deposited dielectric material, suggesting that pre-deposition H2-plasma exposure, coupled with ALD of high-k dielectrics, may provide an effective means for achieving high-quality GaSb MOS structures for advanced Sb-based digital and analog electronics.

  5. Interfacial, Electrical, and Band Alignment Characteristics of HfO2/Ge Stacks with In Situ-Formed SiO2 Interlayer by Plasma-Enhanced Atomic Layer Deposition

    Science.gov (United States)

    Cao, Yan-Qiang; Wu, Bing; Wu, Di; Li, Ai-Dong

    2017-05-01

    In situ-formed SiO2 was introduced into HfO2 gate dielectrics on Ge substrate as interlayer by plasma-enhanced atomic layer deposition (PEALD). The interfacial, electrical, and band alignment characteristics of the HfO2/SiO2 high-k gate dielectric stacks on Ge have been well investigated. It has been demonstrated that Si-O-Ge interlayer is formed on Ge surface during the in situ PEALD SiO2 deposition process. This interlayer shows fantastic thermal stability during annealing without obvious Hf-silicates formation. In addition, it can also suppress the GeO2 degradation. The electrical measurements show that capacitance equivalent thickness of 1.53 nm and a leakage current density of 2.1 × 10-3 A/cm2 at gate bias of Vfb + 1 V was obtained for the annealed sample. The conduction (valence) band offsets at the HfO2/SiO2/Ge interface with and without PDA are found to be 2.24 (2.69) and 2.48 (2.45) eV, respectively. These results indicate that in situ PEALD SiO2 may be a promising interfacial control layer for the realization of high-quality Ge-based transistor devices. Moreover, it can be demonstrated that PEALD is a much more powerful technology for ultrathin interfacial control layer deposition than MOCVD.

  6. Multibands tunneling in AAA-stacked trilayer graphene

    Science.gov (United States)

    Redouani, Ilham; Jellal, Ahmed; Bahaoui, Abdelhadi; Bahlouli, Hocine

    2018-04-01

    We study the electronic transport through np and npn junctions for AAA-stacked trilayer graphene. Two kinds of gates are considered where the first is a single gate and the second is a double gate. After obtaining the solutions for the energy spectrum, we use the transfer matrix method to determine the three transmission probabilities for each individual cone τ = 0 , ± 1 . We show that the quasiparticles in AAA-stacked trilayer graphene are not only chiral but also labeled by an additional cone index τ. The obtained bands are composed of three Dirac cones that depend on the chirality indexes. We show that there is perfect transmission for normal or near normal incidence, which is a manifestation of the Klein tunneling effect. We analyze also the corresponding total conductance, which is defined as the sum of the conductance channels in each individual cone. Our results are numerically discussed and compared with those obtained for ABA- and ABC-stacked trilayer graphene.

  7. Evolutionary search for new high-k dielectric materials: methodology and applications to hafnia-based oxides.

    Science.gov (United States)

    Zeng, Qingfeng; Oganov, Artem R; Lyakhov, Andriy O; Xie, Congwei; Zhang, Xiaodong; Zhang, Jin; Zhu, Qiang; Wei, Bingqing; Grigorenko, Ilya; Zhang, Litong; Cheng, Laifei

    2014-02-01

    High-k dielectric materials are important as gate oxides in microelectronics and as potential dielectrics for capacitors. In order to enable computational discovery of novel high-k dielectric materials, we propose a fitness model (energy storage density) that includes the dielectric constant, bandgap, and intrinsic breakdown field. This model, used as a fitness function in conjunction with first-principles calculations and the global optimization evolutionary algorithm USPEX, efficiently leads to practically important results. We found a number of high-fitness structures of SiO2 and HfO2, some of which correspond to known phases and some of which are new. The results allow us to propose characteristics (genes) common to high-fitness structures--these are the coordination polyhedra and their degree of distortion. Our variable-composition searches in the HfO2-SiO2 system uncovered several high-fitness states. This hybrid algorithm opens up a new avenue for discovering novel high-k dielectrics with both fixed and variable compositions, and will speed up the process of materials discovery.

  8. Mechanical Design of the NSTX High-k Scattering Diagnostic

    International Nuclear Information System (INIS)

    Feder, R.; Mazzucato, E.; Munsat, T.; Park, H.; Smith, D.R.; Ellis, R.; Labik, G.; Priniski, C.

    2005-01-01

    The NSTX High-k Scattering Diagnostic measures small-scale density fluctuations by the heterodyne detection of waves scattered from a millimeter wave probe beam at 280 GHz and λ = 1.07 mm. To enable this measurement, major alterations were made to the NSTX vacuum vessel and Neutral Beam armor. Close collaboration between the PPPL physics and engineering staff resulted in a flexible system with steerable launch and detection optics that can position the scattering volume either near the magnetic axis (ρ ∼ .1) or near the edge (ρ ∼ .8). 150 feet of carefully aligned corrugated waveguide was installed for injection of the probe beam and collection of the scattered signal in to the detection electronics

  9. Identical high- K three-quasiparticle rotational bands

    Energy Technology Data Exchange (ETDEWEB)

    Kaur, Harjeet; Singh, Pardeep [Guru Nanak Dev University, Department of Physics, Amritsar (India)

    2016-12-15

    A comprehensive study of high-K three-quasiparticle rotational bands in odd-A nuclei indicates the similarity in γ-ray energies and dynamic moment of inertia I{sup (2)}. The extent of the identicality between the rotational bands is evaluated by using the energy factor method. For nuclei pairs exhibiting identical bands, the average relative change in the dynamic moment of inertia I{sup (2)} is also determined. The identical behaviour shown by these bands is attributed to the interplay of nuclear structure parameters: deformation and the pairing correlations. Also, experimental trend of the I(ℎ) vs. ℎω (MeV) plot for these nuclei pairs is shown to be in agreement with Tilted-Axis Cranking (TAC) model calculations. (orig.)

  10. Mechanical Design of the NSTX High-k Scattering Diagnostic

    Energy Technology Data Exchange (ETDEWEB)

    Feder, R.; Mazzucato, E.; Munsat, T.; Park, H,; Smith, D. R.; Ellis, R.; Labik, G.; Priniski, C.

    2005-09-26

    The NSTX High-k Scattering Diagnostic measures small-scale density fluctuations by the heterodyne detection of waves scattered from a millimeter wave probe beam at 280 GHz and {lambda}=1.07 mm. To enable this measurement, major alterations were made to the NSTX vacuum vessel and Neutral Beam armor. Close collaboration between the PPPL physics and engineering staff resulted in a flexible system with steerable launch and detection optics that can position the scattering volume either near the magnetic axis ({rho} {approx} .1) or near the edge ({rho} {approx} .8). 150 feet of carefully aligned corrugated waveguide was installed for injection of the probe beam and collection of the scattered signal in to the detection electronics.

  11. Nanostructure characterization of high k materials by spectroscopic ellipsometry

    International Nuclear Information System (INIS)

    Pereira, L.; Aguas, H.; Fortunato, E.; Martins, R.

    2006-01-01

    In this work, the optical and structural properties of high k materials such as tantalum oxide and titanium oxide were studied by spectroscopic ellipsometry, where a Tauc-Lorentz dispersion model based in one (amorphous films) or two oscillators (microcrystalline films) was used. The samples were deposited at room temperature by radio frequency magnetron sputtering and then annealed at temperatures from 100 to 500 deg. C. Concerning the tantalum oxide films, the increase of the annealing temperature, up to 500 deg. C does not change the amorphous nature of the films, increasing, however, their density. The same does not happen with the titanium oxide films that are microcrystalline, even when deposited at room temperature. Data concerning the use of a four-layer model based on one and two Tauc-Lorentz dispersions is also discussed, emphasizing its use for the detection of an amorphous incubation layer, normally present on microcrystalline films grown by sputtering

  12. Improved integration of ultra-thin high-k dielectrics in few-layer MoS2 FET by remote forming gas plasma pretreatment

    Science.gov (United States)

    Wang, Xiao; Zhang, Tian-Bao; Yang, Wen; Zhu, Hao; Chen, Lin; Sun, Qing-Qing; Zhang, David Wei

    2017-01-01

    The effective and high-quality integration of high-k dielectrics on two-dimensional (2D) crystals is essential to the device structure engineering and performance improvement of field-effect transistor (FET) based on the 2D semiconductors. We report a 2D MoS2 transistor with ultra-thin Al2O3 top-gate dielectric (6.1 nm) and extremely low leakage current. Remote forming gas plasma pretreatment was carried out prior to the atomic layer deposition, providing nucleation sites with the physically adsorbed ions on the MoS2 surface. The top gate MoS2 FET exhibited excellent electrical performance, including high on/off current ratio over 109, subthreshold swing of 85 mV/decade and field-effect mobility of 45.03 cm2/V s. Top gate leakage current less than 0.08 pA/μm2 at 4 MV/cm has been obtained, which is the smallest compared with the reported top-gated MoS2 transistors. Such an optimized integration of high-k dielectric in 2D semiconductor FET with enhanced performance is very attractive, and it paves the way towards the realization of more advanced 2D nanoelectronic devices and integrated circuits.

  13. MEAN STACK WEB DEVELOPMENT

    OpenAIRE

    Le Thanh, Nghi

    2017-01-01

    The aim of the thesis is to provide a universal website using JavaScript as the main programming language. It also shows the basic parts anyone need to create a web application. The thesis creates a simple CMS using MEAN stack. MEAN is a collection of JavaScript based technologies used to develop web application. It is an acronym for MongoDB, Express, AngularJS and Node.js. It also allows non-technical users to easily update and manage a website’s content. But the application also lets o...

  14. Die-stacking architecture

    CERN Document Server

    Xie, Yuan

    2015-01-01

    The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the ""memory wall"" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to design

  15. Asymmetric Flexible Supercapacitor Stack

    Directory of Open Access Journals (Sweden)

    Leela Mohana Reddy A

    2008-01-01

    Full Text Available AbstractElectrical double layer supercapacitor is very significant in the field of electrical energy storage which can be the solution for the current revolution in the electronic devices like mobile phones, camera flashes which needs flexible and miniaturized energy storage device with all non-aqueous components. The multiwalled carbon nanotubes (MWNTs have been synthesized by catalytic chemical vapor deposition technique over hydrogen decrepitated Mischmetal (Mm based AB3alloy hydride. The polymer dispersed MWNTs have been obtained by insitu polymerization and the metal oxide/MWNTs were synthesized by sol-gel method. Morphological characterizations of polymer dispersed MWNTs have been carried out using scanning electron microscopy (SEM, transmission electron microscopy (TEM and HRTEM. An assymetric double supercapacitor stack has been fabricated using polymer/MWNTs and metal oxide/MWNTs coated over flexible carbon fabric as electrodes and nafion®membrane as a solid electrolyte. Electrochemical performance of the supercapacitor stack has been investigated using cyclic voltammetry, galvanostatic charge-discharge, and electrochemical impedance spectroscopy.

  16. Modeling of leakage currents in high-k dielectrics

    International Nuclear Information System (INIS)

    Jegert, Gunther Christian

    2012-01-01

    Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO 2 material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO 2 /TiN capacitor structures were suggested and problem areas that may

  17. Modeling of leakage currents in high-k dielectrics

    Energy Technology Data Exchange (ETDEWEB)

    Jegert, Gunther Christian

    2012-03-15

    Leakage currents are one of the major bottlenecks impeding the downscaling efforts of the semiconductor industry. Two core devices of integrated circuits, the transistor and, especially, the DRAM storage capacitor, suffer from the increasing loss currents. In this perspective a fundamental understanding of the physical origin of these leakage currents is highly desirable. However, the complexity of the involved transport phenomena so far has prevented the development of microscopic models. Instead, the analysis of transport through the ultra-thin layers of high-permittivity (high-k) dielectrics, which are employed as insulating layers, was carried out at an empirical level using simple compact models. Unfortunately, these offer only limited insight into the physics involved on the microscale. In this context the present work was initialized in order to establish a framework of microscopic physical models that allow a fundamental description of the transport processes relevant in high-k thin films. A simulation tool that makes use of kinetic Monte Carlo techniques was developed for this purpose embedding the above models in an environment that allows qualitative and quantitative analyses of the electronic transport in such films. Existing continuum approaches, which tend to conceal the important physics behind phenomenological fitting parameters, were replaced by three-dimensional transport simulations at the level of single charge carriers. Spatially localized phenomena, such as percolation of charge carriers across pointlike defects, being subject to structural relaxation processes, or electrode roughness effects, could be investigated in this simulation scheme. Stepwise a self-consistent, closed transport model for the TiN/ZrO{sub 2} material system, which is of outmost importance for the semiconductor industry, was developed. Based on this model viable strategies for the optimization of TiN/ZrO{sub 2}/TiN capacitor structures were suggested and problem areas

  18. On the Evaluation of Gate Dielectrics for 4H-SiC Based Power MOSFETs

    Directory of Open Access Journals (Sweden)

    Muhammad Nawaz

    2015-01-01

    Full Text Available This work deals with the assessment of gate dielectric for 4H-SiC MOSFETs using technology based two-dimensional numerical computer simulations. Results are studied for variety of gate dielectric candidates with varying thicknesses using well-known Fowler-Nordheim tunneling model. Compared to conventional SiO2 as a gate dielectric for 4H-SiC MOSFETs, high-k gate dielectric such as HfO2 reduces significantly the amount of electric field in the gate dielectric with equal gate dielectric thickness and hence the overall gate current density. High-k gate dielectric further reduces the shift in the threshold voltage with varying dielectric thicknesses, thus leading to better process margin and stable device operating behavior. For fixed dielectric thickness, a total shift in the threshold voltage of about 2.5 V has been observed with increasing dielectric constant from SiO2 (k=3.9 to HfO2 (k=25. This further results in higher transconductance of the device with the increase of the dielectric constant from SiO2 to HfO2. Furthermore, 4H-SiC MOSFETs are found to be more sensitive to the shift in the threshold voltage with conventional SiO2 as gate dielectric than high-k dielectric with the presence of interface state charge density that is typically observed at the interface of dielectric and 4H-SiC MOS surface.

  19. Analytical drain current formulation for gate dielectric engineered dual material gate-gate all around-tunneling field effect transistor

    Science.gov (United States)

    Madan, Jaya; Gupta, R. S.; Chaujar, Rishu

    2015-09-01

    In this work, an analytical drain current model for gate dielectric engineered (hetero dielectric)-dual material gate-gate all around tunnel field effect transistor (HD-DMG-GAA-TFET) has been developed. Parabolic approximation has been used to solve the two-dimensional (2D) Poisson equation with appropriate boundary conditions and continuity equations to evaluate analytical expressions for surface potential, electric field, tunneling barrier width and drain current. Further, the analog performance of the device is studied for three high-k dielectrics (Si3N4, HfO2, and ZrO2), and it has been investigated that the problem of lower ION, can be overcome by using the hetero-gate architecture. Moreover, the impact of scaling the gate oxide thickness and bias variations has also been studied. The HD-DMG-GAA-TFET shows an enhanced ION of the order of 10-4 A. The effectiveness of the proposed model is validated by comparing it with ATLAS device simulations.

  20. Materials Fundamentals of Gate Dielectrics

    CERN Document Server

    Demkov, Alexander A

    2006-01-01

    This book presents materials fundamentals of novel gate dielectrics that are being introduced into semiconductor manufacturing to ensure the continuous scalling of the CMOS devices. This is a very fast evolving field of research so we choose to focus on the basic understanding of the structure, thermodunamics, and electronic properties of these materials that determine their performance in device applications. Most of these materials are transition metal oxides. Ironically, the d-orbitals responsible for the high dielectric constant cause sever integration difficulties thus intrinsically limiting high-k dielectrics. Though new in the electronics industry many of these materials are wel known in the field of ceramics, and we describe this unique connection. The complexity of the structure-property relations in TM oxides makes the use of the state of the art first-principles calculations necessary. Several chapters give a detailed description of the modern theory of polarization, and heterojunction band discont...

  1. Instant BlueStacks

    CERN Document Server

    Judge, Gary

    2013-01-01

    Get to grips with a new technology, understand what it is and what it can do for you, and then get to work with the most important features and tasks. A fast-paced, example-based approach guide for learning BlueStacks.This book is for anyone with a Mac or PC who wants to run Android apps on their computer. Whether you want to play games that are freely available for Android but not your computer, or you want to try apps before you install them on a physical device or use it as a development tool, this book will show you how. No previous experience is needed as this is written in plain English

  2. Scaling the Serialization of MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    More than twenty years of thorough research on the serialization of power semiconductor switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), have resulted into several different stacking concepts; all aiming towards...... the establishment of a high-efficient, high-voltage, fast-switching device. Among the prevailing stacking approaches lies the gate balancing core technique, which, in its initial form, demonstrated very good performance in strings of high-power IGBT modules, by magnetically coupling their gate electrodes. Recently...

  3. New gate opening hours

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  4. Work Function Tuning in Sub-20nm Titanium Nitride (TiN) Metal Gate: Mechanism and Engineering

    KAUST Repository

    Hasan, Mehdi

    2011-07-01

    Scaling of transistors (the building blocks of modern information age) provides faster computation at the expense of excessive power dissipation. Thus to address these challenges, high-k/metal gate stack has been introduced in commercially available microprocessors from 2007. Since then titanium nitride (TiN) metal gate’s work function (Wf) tunability with its thickness (thickness increases, work function increases) is a well known phenomenon. Many hypotheses have been made over the years which include but not limited to: trap charge and metal gate nucleation, nitrogen concentration, microstructure agglomeration and global stress, metal oxide formation, and interfacial oxide thickness. However, clear contradictions exist in these assumptions. Also, nearly all these reports skipped a comprehensive approach to explain this complex paradigm. Therefore, in this work we first show a comprehensive physical investigation using transmission electron microcopy/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) to show replacement of oxygen by nitrogen in the metal/dielectric interface, formation of TiONx, reduction of Ti/N concentration and grain size increment happen with TiN thickness increment and thus may increase the work function. Then, using these finding, we experimentally show 100meV of work function modulation in 10nm TiN Metal-oxide-semiconductor capacitor by using low temperature oxygen annealing. A low thermal budget flow (replicating gate-last) shows similar work function boost up. Also, a work function modulation of 250meV has been possible using oxygen annealing and applying no thermal budget. On the other hand, etch-back of TiN layer can decrease the work function. Thus this study quantifies role of various factors in TiN work function tuning; it also reproduces the thickness varied TiN work function modulation in single thickness TiN thus reducing the

  5. Assessing Elementary Algebra with STACK

    Science.gov (United States)

    Sangwin, Christopher J.

    2007-01-01

    This paper concerns computer aided assessment (CAA) of mathematics in which a computer algebra system (CAS) is used to help assess students' responses to elementary algebra questions. Using a methodology of documentary analysis, we examine what is taught in elementary algebra. The STACK CAA system, http://www.stack.bham.ac.uk/, which uses the CAS…

  6. Spherical Torus Center Stack Design

    International Nuclear Information System (INIS)

    C. Neumeyer; P. Heitzenroeder; C. Kessel; M. Ono; M. Peng; J. Schmidt; R. Woolley; I. Zatz

    2002-01-01

    The low aspect ratio spherical torus (ST) configuration requires that the center stack design be optimized within a limited available space, using materials within their established allowables. This paper presents center stack design methods developed by the National Spherical Torus Experiment (NSTX) Project Team during the initial design of NSTX, and more recently for studies of a possible next-step ST (NSST) device

  7. Improved Gate Dielectric Deposition and Enhanced Electrical Stability for Single-Layer MoS2 MOSFET with an AlN Interfacial Layer.

    Science.gov (United States)

    Qian, Qingkai; Li, Baikui; Hua, Mengyuan; Zhang, Zhaofu; Lan, Feifei; Xu, Yongkuan; Yan, Ruyue; Chen, Kevin J

    2016-06-09

    Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.

  8. Towards low-voltage organic thin film transistors (OTFTs with solution-processed high-k dielectric and interface engineering

    Directory of Open Access Journals (Sweden)

    Yaorong Su

    2015-11-01

    Full Text Available Although impressive progress has been made in improving the performance of organic thin film transistors (OTFTs, the high operation voltage resulting from the low gate capacitance density of traditional SiO2 remains a severe limitation that hinders OTFTs'development in practical applications. In this regard, developing new materials with high-k characteristics at low cost is of great scientific and technological importance in the area of both academia and industry. Here, we introduce a simple solution-based technique to fabricate high-k metal oxide dielectric system (ATO at low-temperature, which can be used effectively to realize low-voltage operation of OTFTs. On the other hand, it is well known that the properties of the dielectric/semiconductor and electrode/semiconductor interfaces are crucial in controlling the electrical properties of OTFTs. By optimizing the above two interfaces with octadecylphosphonic acid (ODPA self-assembled monolayer (SAM and properly modified low-cost Cu, obviously improved device performance is attained in our low-voltage OTFTs. Further more, organic electronic devices on flexible substrates have attracted much attention due to their low-cost, rollability, large-area processability, and so on. Basing on the above results, outstanding electrical performance is achieved in flexible devices. Our studies demonstrate an effective way to realize low-voltage, high-performance OTFTs at low-cost.

  9. Modeling fuel cell stack systems

    Energy Technology Data Exchange (ETDEWEB)

    Lee, J H [Los Alamos National Lab., Los Alamos, NM (United States); Lalk, T R [Dept. of Mech. Eng., Texas A and M Univ., College Station, TX (United States)

    1998-06-15

    A technique for modeling fuel cell stacks is presented along with the results from an investigation designed to test the validity of the technique. The technique was specifically designed so that models developed using it can be used to determine the fundamental thermal-physical behavior of a fuel cell stack for any operating and design configuration. Such models would be useful tools for investigating fuel cell power system parameters. The modeling technique can be applied to any type of fuel cell stack for which performance data is available for a laboratory scale single cell. Use of the technique is demonstrated by generating sample results for a model of a Proton Exchange Membrane Fuel Cell (PEMFC) stack consisting of 125 cells each with an active area of 150 cm{sup 2}. A PEMFC stack was also used in the verification investigation. This stack consisted of four cells, each with an active area of 50 cm{sup 2}. Results from the verification investigation indicate that models developed using the technique are capable of accurately predicting fuel cell stack performance. (orig.)

  10. Features of carrier tunneling between the silicon valence band and metal in devices based on the Al/high-K oxide/SiO_2/Si structure

    International Nuclear Information System (INIS)

    Vexler, M. I.; Grekhov, I. V.

    2016-01-01

    The features of electron tunneling from or into the silicon valence band in a metal–insulator–semiconductor system with the HfO_2(ZrO_2)/SiO_2 double-layer insulator are theoretically analyzed for different modes. It is demonstrated that the valence-band current plays a less important role in structures with HfO_2(ZrO_2)/SiO_2 than in structures containing only silicon dioxide. In the case of a very wide-gap high-K oxide ZrO_2, nonmonotonic behavior related to tunneling through the upper barrier is predicted for the valence-band–metal current component. The use of an insulator stack can offer certain advantages for some devices, including diodes, bipolar tunnel-emitter transistors, and resonant-tunneling diodes, along with the traditional use of high-K insulators in a field-effect transistor.

  11. Environmental assessment of phosphogypsum stacks

    International Nuclear Information System (INIS)

    Odat, M.; Al-Attar, L.; Raja, G.; Abdul Ghany, B.

    2009-01-01

    Phosphogypsum is one of the most important by-products of phosphate fertilizer industry. It is kept in large stacks to the west of Homs city. Storing Phosphogypsum as open stacks exposed to various environmental effects, wind and rain, may cause pollution of the surrounding ecosystem (soil, plant, water and air). This study was carried out in order to assess the environmental impact of Phosphogypsum stacks on the surrounding ecosystem. The obtained results show that Phosphogypsum stacks did not increase the concentration of radionuclides, i.e. Radon-222 and Radium-226, the external exposed dose of gamma rays, as well as the concentration of heavy metals in the components of the ecosystem, soil, plant, water and air, as their concentrations did not exceed the permissible limits. However, the concentration of fluorine in the upper layer of soil, located to the east of the Phosphogypsum stacks, increased sufficiently, especially in the dry period of the year. Also, the concentration of fluoride in plants growing up near-by the Phosphogypsum stacks was too high, exceeded the permissible levels. This was reflected in poising plants and animals, feeding on the plants. Consequently, increasing the concentration of fluoride in soil and plants is the main impact of Phosphogypsum stacks on the surrounding ecosystem. Minimising this effect could be achieved by establishing a 50 meter wide protection zone surrounding the Phosphogypsum stacks, which has to be planted with non palatable trees, such as pine and cypress, forming wind barriers. Increasing the concentrations of heavy metals and fluoride in infiltrated water around the stacks was high; hence cautions must be taken to prevent its usage in any application or disposal in adjacent rivers and leaks.(author)

  12. Environmental assessment of phosphogypsum stacks

    International Nuclear Information System (INIS)

    Odat, M.; Al-Attar, L.; Raja, G.; Abdul Ghany, B.

    2008-03-01

    Phosphogypsum is one of the most important by-products of phosphate fertilizer industry. It is kept in large stacks to the west of Homs city. Storing Phosphogypsum as open stacks exposed to various environmental effects, wind and rain, may cause pollution of the surrounding ecosystem (soil, plant, water and air). This study was carried out in order to assess the environmental impact of Phosphogypsum stacks on the surrounding ecosystem. The obtained results show that Phosphogypsum stacks did not increase the concentration of radionuclides, i.e. Radon-222 and Radium-226, the external exposed dose of gamma rays, as well as the concentration of heavy metals in the components of the ecosystem, soil, plant, water and air, as their concentrations did not exceed the permissible limits. However, the concentration of fluorine in the upper layer of soil, located to the east of the Phosphogypsum stacks, increased sufficiently, especially in the dry period of the year. Also, the concentration of fluoride in plants growing up near-by the Phosphogypsum stacks was too high, exceeded the permissible levels. This was reflected in poising plants and animals, feeding on the plants. Consequently, increasing the concentration of fluoride in soil and plants is the main impact of Phosphogypsum stacks on the surrounding ecosystem. Minimising this effect could be achieved by establishing a 50 meter wide protection zone surrounding the Phosphogypsum stacks, which has to be planted with non palatable trees, such as pine and cypress, forming wind barriers. Increasing the concentrations of heavy metals and fluoride in infiltrated water around the stacks was high; hence cautions must be taken to prevent its usage in any application or disposal in adjacent rivers and leaks.(author)

  13. Nano-CMOS gate dielectric engineering

    CERN Document Server

    Wong, Hei

    2011-01-01

    According to Moore's Law, not only does the number of transistors in an integrated circuit double every two years, but transistor size also decreases at a predictable rate. At the rate we are going, the downsizing of CMOS transistors will reach the deca-nanometer scale by 2020. Accordingly, the gate dielectric thickness will be shrunk to less than half-nanometer oxide equivalent thickness (EOT) to maintain proper operation of the transistors, leaving high-k materials as the only viable solution for such small-scale EOT. This comprehensive, up-to-date text covering the physics, materials, devic

  14. Cell characteristics of FePt nano-dot memories with a high-k Al2O3 blocking oxide

    International Nuclear Information System (INIS)

    Lee, Gae Hun; Lee, Jung Min; Yang, Hyung Jun; Song, Yun Heub; Bea, Ji Cheol; Tanaka, Testsu

    2012-01-01

    The cell characteristics of an alloy FePt nano-dot (ND) charge trapping memory with a high-k dielectric as a blocking oxide was investigated. Adoption of a high-k Al 2 O 3 material as a blocking oxide for the metal nano-dot memory provided a superior scaling of the operation voltage compared to silicon oxide under a similar gate leakage level. For the 40-nm-thick high-k (Al 2 O 3 ) blocking oxide, we confirmed an operation voltage reduction of ∼7 V under the same memory window on for silicon dioxide. Also, this device showed a large memory window of 7.8 V and a low leakage current under 10 -10 A in an area of Φ 0.25 mm. From these results, the use of a dielectric (Al 2 O 3 ) as a blocking oxide for a metal nano-dot device is essential, and a metal nano-dot memory with a high-k dielectric will be one of the candidates for a high-density non-volatile memory device.

  15. Reduction of skin effect losses in double-level-T-gate structure

    Energy Technology Data Exchange (ETDEWEB)

    Mikulics, M., E-mail: m.mikulics@fz-juelich.de; Hardtdegen, H.; Arango, Y. C.; Adam, R.; Fox, A.; Grützmacher, D. [Peter Grünberg Institute (PGI-9), Forschungszentrum Jülich, D-52425 Jülich (Germany); Jülich-Aachen Research Alliance, JARA, Fundamentals of Future Information Technology, D-52425 Jülich (Germany); Gregušová, D.; Novák, J. [Institute of Electrical Engineering, Slovak Academy of Sciences, SK-84104 Bratislava (Slovakia); Stanček, S. [Department of Nuclear Physic and Technique, Slovak University of Technology, SK-81219 Bratislava (Slovakia); Kordoš, P. [Institute of Electronics and Photonics, Slovak University of Technology, SK-81219 Bratislava (Slovakia); Sofer, Z. [Department of Inorganic Chemistry, Institute of Chemical Technology, Technická 5, Prague 6 (Czech Republic); Juul, L.; Marso, M. [Faculté des Sciences, de la Technologie et de la Communication, Université du Luxembourg, L-1359 Luxembourg (Luxembourg)

    2014-12-08

    We developed a T-gate technology based on selective wet etching yielding 200 nm wide T-gate structures used for fabrication of High Electron Mobility Transistors (HEMT). Major advantages of our process are the use of only standard photolithographic process and the ability to generate T-gate stacks. A HEMT fabricated on AlGaN/GaN/sapphire with gate length L{sub g} = 200 nm and double-stacked T-gates exhibits 60 GHz cutoff frequency showing ten-fold improvement compared to 6 GHz for the same device with 2 μm gate length. HEMTs with a double-level-T-gate (DLTG) structure exhibit up to 35% improvement of f{sub max} value compared to a single T-gate device. This indicates a significant reduction of skin effect losses in DLTG structure compared to its standard T-gate counterpart. These results agree with the theoretical predictions.

  16. Single-electron-occupation metal-oxide-semiconductor quantum dots formed from efficient poly-silicon gate layout

    Energy Technology Data Exchange (ETDEWEB)

    Carroll, Malcolm S.; rochette, sophie; Rudolph, Martin; Roy, A. -M.; Curry, Matthew Jon; Ten Eyck, Gregory A.; Manginell, Ronald P.; Wendt, Joel R.; Pluym, Tammy; Carr, Stephen M; Ward, Daniel Robert; Lilly, Michael; pioro-ladriere, michel

    2017-07-01

    We introduce a silicon metal-oxide-semiconductor quantum dot structure that achieves dot-reservoir tunnel coupling control without a dedicated barrier gate. The elementary structure consists of two accumulation gates separated spatially by a gap, one gate accumulating a reservoir and the other a quantum dot. Control of the tunnel rate between the dot and the reservoir across the gap is demonstrated in the single electron regime by varying the reservoir accumulation gate voltage while compensating with the dot accumulation gate voltage. The method is then applied to a quantum dot connected in series to source and drain reservoirs, enabling transport down to the single electron regime. Finally, tuning of the valley splitting with the dot accumulation gate voltage is observed. This split accumulation gate structure creates silicon quantum dots of similar characteristics to other realizations but with less electrodes, in a single gate stack subtractive fabrication process that is fully compatible with silicon foundry manufacturing.

  17. Quantum gate decomposition algorithms.

    Energy Technology Data Exchange (ETDEWEB)

    Slepoy, Alexander

    2006-07-01

    Quantum computing algorithms can be conveniently expressed in a format of a quantum logical circuits. Such circuits consist of sequential coupled operations, termed ''quantum gates'', or quantum analogs of bits called qubits. We review a recently proposed method [1] for constructing general ''quantum gates'' operating on an qubits, as composed of a sequence of generic elementary ''gates''.

  18. Novel Quantum Dot Gate FETs and Nonvolatile Memories Using Lattice-Matched II-VI Gate Insulators

    Science.gov (United States)

    Jain, F. C.; Suarez, E.; Gogna, M.; Alamoody, F.; Butkiewicus, D.; Hohner, R.; Liaskas, T.; Karmakar, S.; Chan, P.-Y.; Miller, B.; Chandy, J.; Heller, E.

    2009-08-01

    This paper presents the successful use of ZnS/ZnMgS and other II-VI layers (lattice-matched or pseudomorphic) as high- k gate dielectrics in the fabrication of quantum dot (QD) gate Si field-effect transistors (FETs) and nonvolatile memory structures. Quantum dot gate FETs and nonvolatile memories have been fabricated in two basic configurations: (1) monodispersed cladded Ge nanocrystals (e.g., GeO x -cladded-Ge quantum dots) site-specifically self-assembled over the lattice-matched ZnMgS gate insulator in the channel region, and (2) ZnTe-ZnMgTe quantum dots formed by self-organization, using metalorganic chemical vapor-phase deposition (MOCVD), on ZnS-ZnMgS gate insulator layers grown epitaxially on Si substrates. Self-assembled GeO x -cladded Ge QD gate FETs, exhibiting three-state behavior, are also described. Preliminary results on InGaAs-on-InP FETs, using ZnMgSeTe/ZnSe gate insulator layers, are presented.

  19. Glassy carbon based supercapacitor stacks

    Energy Technology Data Exchange (ETDEWEB)

    Baertsch, M; Braun, A; Koetz, R; Haas, O [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1997-06-01

    Considerable effort is being made to develop electrochemical double layer capacitors (EDLC) that store relatively large quantities of electrical energy and possess at the same time a high power density. Our previous work has shown that glassy carbon is suitable as a material for capacitor electrodes concerning low resistance and high capacity requirements. We present the development of bipolar electrochemical glassy carbon capacitor stacks of up to 3 V. Bipolar stacks are an efficient way to meet the high voltage and high power density requirements for traction applications. Impedance and cyclic voltammogram measurements are reported here and show the frequency response of a 1, 2, and 3 V stack. (author) 3 figs., 1 ref..

  20. Time-predictable Stack Caching

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar

    completely. Thus, in systems with hard deadlines the worst-case execution time (WCET) of the real-time software running on them needs to be bounded. Modern architectures use features such as pipelining and caches for improving the average performance. These features, however, make the WCET analysis more...... addresses, provides an opportunity to predict and tighten the WCET of accesses to data in caches. In this thesis, we introduce the time-predictable stack cache design and implementation within a time-predictable processor. We introduce several optimizations to our design for tightening the WCET while...... keeping the timepredictability of the design intact. Moreover, we provide a solution for reducing the cost of context switching in a system using the stack cache. In design of these caches, we use custom hardware and compiler support for delivering time-predictable stack data accesses. Furthermore...

  1. Signatures of Mechanosensitive Gating.

    Science.gov (United States)

    Morris, Richard G

    2017-01-10

    The question of how mechanically gated membrane channels open and close is notoriously difficult to address, especially if the protein structure is not available. This perspective highlights the relevance of micropipette-aspirated single-particle tracking-used to obtain a channel's diffusion coefficient, D, as a function of applied membrane tension, σ-as an indirect assay for determining functional behavior in mechanosensitive channels. While ensuring that the protein remains integral to the membrane, such methods can be used to identify not only the gating mechanism of a protein, but also associated physical moduli, such as torsional and dilational rigidity, which correspond to the protein's effective shape change. As an example, three distinct D-versus-σ "signatures" are calculated, corresponding to gating by dilation, gating by tilt, and gating by a combination of both dilation and tilt. Both advantages and disadvantages of the approach are discussed. Copyright © 2017 Biophysical Society. Published by Elsevier Inc. All rights reserved.

  2. Stack semantics of type theory

    DEFF Research Database (Denmark)

    Coquand, Thierry; Mannaa, Bassel; Ruch, Fabian

    2017-01-01

    We give a model of dependent type theory with one univalent universe and propositional truncation interpreting a type as a stack, generalizing the groupoid model of type theory. As an application, we show that countable choice cannot be proved in dependent type theory with one univalent universe...

  3. Multilayer Piezoelectric Stack Actuator Characterization

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher M.; Aldrich, Jack B.; Blodget, Chad; Bao, Xioaqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to use actuators for precision positioning to accuracies of the order of fractions of a nanometer. For this purpose, multilayer piezoelectric stacks are being considered as actuators for driving these precision mechanisms. In this study, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and extreme temperatures and voltages. AC signal testing included impedance, capacitance and dielectric loss factor of each actuator as a function of the small-signal driving sinusoidal frequency, and the ambient temperature. DC signal testing includes leakage current and displacement as a function of the applied DC voltage. The applied DC voltage was increased to over eight times the manufacturers' specifications to investigate the correlation between leakage current and breakdown voltage. Resonance characterization as a function of temperature was done over a temperature range of -180C to +200C which generally exceeded the manufacturers' specifications. In order to study the lifetime performance of these stacks, five actuators from one manufacturer were driven by a 60volt, 2 kHz sine-wave for ten billion cycles. The tests were performed using a Lab-View controlled automated data acquisition system that monitored the waveform of the stack electrical current and voltage. The measurements included the displacement, impedance, capacitance and leakage current and the analysis of the experimental results will be presented.

  4. V-stack piezoelectric actuator

    Science.gov (United States)

    Ardelean, Emil V.; Clark, Robert L.

    2001-07-01

    Aeroelastic control of wings by means of a distributed, trailing-edge control surface is of interest with regards to maneuvers, gust alleviation, and flutter suppression. The use of high energy density, piezoelectric materials as motors provides an appealing solution to this problem. A comparative analysis of the state of the art actuators is currently being conducted. A new piezoelectric actuator design is presented. This actuator meets the requirements for trailing edge flap actuation in both stroke and force. It is compact, simple, sturdy, and leverages stroke geometrically with minimum force penalties while displaying linearity over a wide range of stroke. The V-Stack Piezoelectric Actuator, consists of a base, a lever, two piezoelectric stacks, and a pre-tensioning element. The work is performed alternately by the two stacks, placed on both sides of the lever. Pre-tensioning can be readily applied using a torque wrench, obviating the need for elastic elements and this is for the benefit of the stiffness of the actuator. The characteristics of the actuator are easily modified by changing the base or the stacks. A prototype was constructed and tested experimentally to validate the theoretical model.

  5. Open stack thermal battery tests

    Energy Technology Data Exchange (ETDEWEB)

    Long, Kevin N. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Roberts, Christine C. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Grillet, Anne M. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Headley, Alexander J. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Fenton, Kyle [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Wong, Dennis [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Ingersoll, David [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2017-04-17

    We present selected results from a series of Open Stack thermal battery tests performed in FY14 and FY15 and discuss our findings. These tests were meant to provide validation data for the comprehensive thermal battery simulation tools currently under development in Sierra/Aria under known conditions compared with as-manufactured batteries. We are able to satisfy this original objective in the present study for some test conditions. Measurements from each test include: nominal stack pressure (axial stress) vs. time in the cold state and during battery ignition, battery voltage vs. time against a prescribed current draw with periodic pulses, and images transverse to the battery axis from which cell displacements are computed. Six battery configurations were evaluated: 3, 5, and 10 cell stacks sandwiched between 4 layers of the materials used for axial thermal insulation, either Fiberfrax Board or MinK. In addition to the results from 3, 5, and 10 cell stacks with either in-line Fiberfrax Board or MinK insulation, a series of cell-free “control” tests were performed that show the inherent settling and stress relaxation based on the interaction between the insulation and heat pellets alone.

  6. Adding large EM stack support

    KAUST Repository

    Holst, Glendon

    2016-12-01

    Serial section electron microscopy (SSEM) image stacks generated using high throughput microscopy techniques are an integral tool for investigating brain connectivity and cell morphology. FIB or 3View scanning electron microscopes easily generate gigabytes of data. In order to produce analyzable 3D dataset from the imaged volumes, efficient and reliable image segmentation is crucial. Classical manual approaches to segmentation are time consuming and labour intensive. Semiautomatic seeded watershed segmentation algorithms, such as those implemented by ilastik image processing software, are a very powerful alternative, substantially speeding up segmentation times. We have used ilastik effectively for small EM stacks – on a laptop, no less; however, ilastik was unable to carve the large EM stacks we needed to segment because its memory requirements grew too large – even for the biggest workstations we had available. For this reason, we refactored the carving module of ilastik to scale it up to large EM stacks on large workstations, and tested its efficiency. We modified the carving module, building on existing blockwise processing functionality to process data in manageable chunks that can fit within RAM (main memory). We review this refactoring work, highlighting the software architecture, design choices, modifications, and issues encountered.

  7. Evaluation of the effects of thermal annealing temperature and high-k dielectrics on amorphous InGaZnO thin films by using pseudo-MOS transistors

    International Nuclear Information System (INIS)

    Lee, Se-Won; Cho, Won-Ju

    2012-01-01

    The effects of annealing temperatures and high-k gate dielectric materials on the amorphous In-Ga-Zn-O thin-film transistors (a-IGZO TFTs) were investigated using pseudo-metal-oxide semiconductor transistors (Ψ-MOSFETs), a method without conventional source/drain (S/D) layer deposition. Annealing of the a-IGZO film was carried out at 150 - 900 .deg. C in a N 2 ambient for 30 min. As the annealing temperature was increased, the electrical characteristics of Ψ-MOSFETs on a-IGZO were drastically improved. However, when the annealing temperature exceeded 700 .deg. C, a deterioration of the MOS parameters was observed, including a shift of the threshold voltage (V th ) in a negative direction, an increase in the subthreshold slope (SS) and hysteresis, a decrease in the field effect mobility (μ FE ), an increase in the trap density (N t ), and a decrease in the on/off ratio. Meanwhile, the high-k gate dielectrics enhanced the performance of a-IGZO Ψ-MOSFETs. The ZrO 2 gate dielectrics particularly exhibited excellent characteristics in terms of SS (128 mV/dec), μ FE (10.2 cm -2 /V·s), N t (1.1 x 10 12 cm -2 ), and on/off ratio (5.3 x 10 6 ). Accordingly, the Ψ-MOSFET structure is a useful method for rapid evaluation of the effects of the process and the material on a-IGZO TFTs without a conventional S/D layer deposition.

  8. Optical XOR gate

    Science.gov (United States)

    Vawter, G. Allen

    2013-11-12

    An optical XOR gate is formed as a photonic integrated circuit (PIC) from two sets of optical waveguide devices on a substrate, with each set of the optical waveguide devices including an electroabsorption modulator electrically connected in series with a waveguide photodetector. The optical XOR gate utilizes two digital optical inputs to generate an XOR function digital optical output. The optical XOR gate can be formed from III-V compound semiconductor layers which are epitaxially deposited on a III-V compound semiconductor substrate, and operates at a wavelength in the range of 0.8-2.0 .mu.m.

  9. Vertical melting of a stack of membranes

    Science.gov (United States)

    Borelli, M. E. S.; Kleinert, H.; Schakel, A. M. J.

    2001-02-01

    A stack of tensionless membranes with nonlinear curvature energy and vertical harmonic interaction is studied. At low temperatures, the system forms a lamellar phase. At a critical temperature, the stack disorders vertically in a melting-like transition.

  10. Observation of band bending of metal/high-k Si capacitor with high energy x-ray photoemission spectroscopy and its application to interface dipole measurement

    Science.gov (United States)

    Kakushima, K.; Okamoto, K.; Tachi, K.; Song, J.; Sato, S.; Kawanago, T.; Tsutsui, K.; Sugii, N.; Ahmet, P.; Hattori, T.; Iwai, H.

    2008-11-01

    Band bendings of Si substrates have been observed using hard x-ray photoemission spectroscopy. With a capability of collecting photoelectrons generated as deep as 40 nm, the binding energy shift in a core level caused by the potential profile at the surface of the substrate results in a spectrum broadening. The broadening is found to be significant when heavily doped substrates are used owing to its steep potential profile. The surface potential of the substrate can be obtained by deconvolution of the spectrum. This method has been applied to observe the band bending profile of metal-oxide-semiconductor capacitors with high-k gate dielectrics. By comparing the band bending profiles of heavily-doped n+- and p+-Si substrates, the interface dipoles presented at interfaces can be estimated. In the case of W gated La2O3/La-silicate capacitor, an interface dipole to shift the potential of -0.45 V has been estimated at La-silicate/Si interface, which effectively reduces the apparent work function of W. On the other hand, an interface dipole of 0.03-0.07 V has been found to exist at Hf-silicate/SiO2 interface for W gated HfO2/Hf-silicate/SiO2 capacitor.

  11. A split accumulation gate architecture for silicon MOS quantum dots

    Science.gov (United States)

    Rochette, Sophie; Rudolph, Martin; Roy, Anne-Marie; Curry, Matthew; Ten Eyck, Gregory; Dominguez, Jason; Manginell, Ronald; Pluym, Tammy; King Gamble, John; Lilly, Michael; Bureau-Oxton, Chloé; Carroll, Malcolm S.; Pioro-Ladrière, Michel

    We investigate tunnel barrier modulation without barrier electrodes in a split accumulation gate architecture for silicon metal-oxide-semiconductor quantum dots (QD). The layout consists of two independent accumulation gates, one gate forming a reservoir and the other the QD. The devices are fabricated with a foundry-compatible, etched, poly-silicon gate stack. We demonstrate 4 orders of magnitude of tunnel-rate control between the QD and the reservoir by modulating the reservoir gate voltage. Last electron charging energies of app. 10 meV and tuning of the ST splitting in the range 100-200 ueV are observed in two different split gate layouts and labs. This work was performed, in part, at the Center for Integrated Nanotechnologies, an Office of Science User Facility operated for the U.S. Department of Energy (DOE) Office of Science. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation, a Lockheed-Martin Company, for the U. S. Department of Energy under Contract No. DE-AC04-94AL85000.

  12. Helping Students Design HyperCard Stacks.

    Science.gov (United States)

    Dunham, Ken

    1995-01-01

    Discusses how to teach students to design HyperCard stacks. Highlights include introducing HyperCard, developing storyboards, introducing design concepts and scripts, presenting stacks, evaluating storyboards, and continuing projects. A sidebar presents a HyperCard stack evaluation form. (AEF)

  13. PRECISION COSMOGRAPHY WITH STACKED VOIDS

    International Nuclear Information System (INIS)

    Lavaux, Guilhem; Wandelt, Benjamin D.

    2012-01-01

    We present a purely geometrical method for probing the expansion history of the universe from the observation of the shape of stacked voids in spectroscopic redshift surveys. Our method is an Alcock-Paczyński (AP) test based on the average sphericity of voids posited on the local isotropy of the universe. It works by comparing the temporal extent of cosmic voids along the line of sight with their angular, spatial extent. We describe the algorithm that we use to detect and stack voids in redshift shells on the light cone and test it on mock light cones produced from N-body simulations. We establish a robust statistical model for estimating the average stretching of voids in redshift space and quantify the contamination by peculiar velocities. Finally, assuming that the void statistics that we derive from N-body simulations is preserved when considering galaxy surveys, we assess the capability of this approach to constrain dark energy parameters. We report this assessment in terms of the figure of merit (FoM) of the dark energy task force and in particular of the proposed Euclid mission which is particularly suited for this technique since it is a spectroscopic survey. The FoM due to stacked voids from the Euclid wide survey may double that of all other dark energy probes derived from Euclid data alone (combined with Planck priors). In particular, voids seem to outperform baryon acoustic oscillations by an order of magnitude. This result is consistent with simple estimates based on mode counting. The AP test based on stacked voids may be a significant addition to the portfolio of major dark energy probes and its potentialities must be studied in detail.

  14. Docker on OpenStack

    OpenAIRE

    Agarwal, Nitin; Moreira, Belmiro

    2014-01-01

    Project Specification CERN is establishing a large scale private cloud based on OpenStack as part of the expansion of the computing infrastructure for storing the data coming out of the Large Hadron Collider (LHC) experiments. As the data coming out of the detectors is increasing continuously that needs to be stored in the data center, we need more physical resources (more money) and since Virtual machines takes lot of CPU and memory overhead and minutes for creating the images, booting u...

  15. Silicate formation at the interface of Pr-oxide as a high-K dielectric and Si(001) surfaces

    International Nuclear Information System (INIS)

    Schmeisser, D.; Zheng, F.; Perez-Dieste, V.; Himpsel, F.J.; LoNigro, R.; Toro, R.G.; Malandrino, G.; Fragala, I.L.

    2006-01-01

    The composition and chemical bonding of the first atoms across the interface between Si(001) and the dielectric determine the quality of dielectric gate stacks. An analysis of that hidden interface is a challenge as it requires both, high sensitivity and elemental and chemical state information. We used X-ray absorption spectroscopy in total electron yield and total fluorescence yield at the Si2p and the O1s edges to address that issue. We report on results of Pr 2 O 3 /Si(001) as prepared by both, epitaxial growth and metal organic chemical vapor deposition (MOCVD), and compare to the SiO 2 /Si(001) system as a reference. We find evidence for the silicate formation at the interface as derived from the characteristic features at the Si2p and the O1s edges. The results are in line with model experiments in which films of increasing film thickness are deposited in situ on bare Si(001) surfaces

  16. Stack Monitor Operating Experience Review

    International Nuclear Information System (INIS)

    Cadwallader, L.C.; Bruyere, S.A.

    2009-01-01

    Stack monitors are used to sense radioactive particulates and gases in effluent air being vented from rooms of nuclear facilities. These monitors record the levels and types of effluents to the environment. This paper presents the results of a stack monitor operating experience review of the U.S. Department of Energy (DOE) Occurrence Reporting and Processing System (ORPS) database records from the past 18 years. Regulations regarding these monitors are briefly described. Operating experiences reported by the U.S. DOE and in engineering literature sources were reviewed to determine the strengths and weaknesses of these monitors. Electrical faults, radiation instrumentation faults, and human errors are the three leading causes of failures. A representative 'all modes' failure rate is 1E-04/hr. Repair time estimates vary from an average repair time of 17.5 hours (with spare parts on hand) to 160 hours (without spare parts on hand). These data should support the use of stack monitors in any nuclear facility, including the National Ignition Facility and the international ITER project.

  17. Simulation of dual-gate SOI MOSFET with different dielectric layers

    Science.gov (United States)

    Yadav, Jyoti; Chaudhary, R.; Mukhiya, R.; Sharma, R.; Khanna, V. K.

    2016-04-01

    The paper presents the process design and simulation of silicon-on-insulator (SOI)-based dual-gate metal oxide field-effect transistor (DG-MOSFET) stacked with different dielectric layers on the top of gate oxide. A detailed 2D process simulation of SOI-MOSFETs and its electrical characterization has been done using SILVACO® TCAD tool. A variation in transconductance was observed with different dielectric layers, AlN-gate MOSFET having the highest tranconductance value as compared to other three dielectric layers (SiO2, Si3N4 and Al2O3).

  18. Study of strained-Si p-channel MOSFETs with HfO2 gate dielectric

    Science.gov (United States)

    Pradhan, Diana; Das, Sanghamitra; Dash, Tara Prasanna

    2016-10-01

    In this work, the transconductance of strained-Si p-MOSFETs with high-K dielectric (HfO2) as gate oxide, has been presented through simulation using the TCAD tool Silvaco-ATLAS. The results have been compared with a SiO2/strained-Si p-MOSFET device. Peak transconductance enhancement factors of 2.97 and 2.73 has been obtained for strained-Si p-MOSFETs in comparison to bulk Si channel p-MOSFETs with SiO2 and high-K dielectric respectively. This behavior is in good agreement with the reported experimental results. The transconductance of the strained-Si device at low temperatures has also been simulated. As expected, the mobility and hence the transconductance increases at lower temperatures due to reduced phonon scattering. However, the enhancements with high-K gate dielectric is less as compared to that with SiO2.

  19. Lightweight Stacks of Direct Methanol Fuel Cells

    Science.gov (United States)

    Narayanan, Sekharipuram; Valdez, Thomas

    2004-01-01

    An improved design concept for direct methanol fuel cells makes it possible to construct fuel-cell stacks that can weigh as little as one-third as much as do conventional bipolar fuel-cell stacks of equal power. The structural-support components of the improved cells and stacks can be made of relatively inexpensive plastics. Moreover, in comparison with conventional bipolar fuel-cell stacks, the improved fuel-cell stacks can be assembled, disassembled, and diagnosed for malfunctions more easily. These improvements are expected to bring portable direct methanol fuel cells and stacks closer to commercialization. In a conventional bipolar fuel-cell stack, the cells are interspersed with bipolar plates (also called biplates), which are structural components that serve to interconnect the cells and distribute the reactants (methanol and air). The cells and biplates are sandwiched between metal end plates. Usually, the stack is held together under pressure by tie rods that clamp the end plates. The bipolar stack configuration offers the advantage of very low internal electrical resistance. However, when the power output of a stack is only a few watts, the very low internal resistance of a bipolar stack is not absolutely necessary for keeping the internal power loss acceptably low.

  20. Fringing field effects in negative capacitance field-effect transistors with a ferroelectric gate insulator

    Science.gov (United States)

    Hattori, Junichi; Fukuda, Koichi; Ikegami, Tsutomu; Ota, Hiroyuki; Migita, Shinji; Asai, Hidehiro; Toriumi, Akira

    2018-04-01

    We study the effects of fringing electric fields on the behavior of negative-capacitance (NC) field-effect transistors (FETs) with a silicon-on-insulator body and a gate stack consisting of an oxide film, an internal metal film, a ferroelectric film, and a gate electrode using our own device simulator that can properly handle the complicated relationship between the polarization and the electric field in ferroelectric materials. The behaviors of such NC FETs and the corresponding metal-oxide-semiconductor (MOS) FETs are simulated and compared with each other to evaluate the effects of the NC of the ferroelectric film. Then, the fringing field effects are evaluated by comparing the NC effects in NC FETs with and without gate spacers. The fringing field between the gate stack, especially the internal metal film, and the source/drain region induces more charges at the interface of the film with the ferroelectric film. Accordingly, the function of the NC to modulate the gate voltage and the resulting function to improve the subthreshold swing are enhanced. We also investigate the relationships of these fringing field effects to the drain voltage and four design parameters of NC FETs, i.e., gate length, gate spacer permittivity, internal metal film thickness, and oxide film thickness.

  1. Solid Oxide Fuel Cell Stack Diagnostics

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Barfod, Rasmus Gottrup

    As SOFC technology is moving closer to a commercial break through, methods to measure the “state-of-health” of operating stacks are becoming of increasing interest. This requires application of advanced methods for detailed electrical and electrochemical characterization during operation....... An operating stack is subject to compositional gradients in the gaseous reactant streams, and temperature gradients across each cell and across the stack, which complicates detailed analysis. Several experimental stacks from Topsoe Fuel Cell A/S were characterized using Electrochemical Impedance Spectroscopy...... in the hydrogen fuel gas supplied to the stack. EIS was used to examine the long-term behavior and monitor the evolution of the impedance of each of the repeating units and the whole stack. The observed impedance was analyzed in detail for one of the repeating units and the whole stack and the losses reported...

  2. Volatile and Nonvolatile Characteristics of Asymmetric Dual-Gate Thyristor RAM with Vertical Structure.

    Science.gov (United States)

    Kim, Hyun-Min; Kwon, Dae Woong; Kim, Sihyun; Lee, Kitae; Lee, Junil; Park, Euyhwan; Lee, Ryoongbin; Kim, Hyungjin; Kim, Sangwan; Park, Byung-Gook

    2018-09-01

    In this paper, the volatile and nonvolatile characteristics of asymmetric dual-gate thyristor random access memory (TRAM) are investigated using the technology of a computer-aided design (TCAD) simulation. Owing to the use of two independent gates having different gate dielectric layers, volatile and nonvolatile memory functions can be realized in a single device. The first gate with a silicon oxide layer controls the one-transistor dynamic random access memory (1T-DRAM) characteristics of the device. From the simulation results, a rapid write speed (107) can be achieved. The second gate, whose dielectric material is composed of oxide/nitride/oxide (O/N/O) layers, is used to implement the nonvolatile property by trapping charges in the nitride layer. In addition, this offers an advantage when processing the 3D-stack memory application, as the device has a vertical channel structure with polycrystalline silicon.

  3. Continuous adjustment of threshold voltage in carbon nanotube field-effect transistors through gate engineering

    Science.gov (United States)

    Zhong, Donglai; Zhao, Chenyi; Liu, Lijun; Zhang, Zhiyong; Peng, Lian-Mao

    2018-04-01

    In this letter, we report a gate engineering method to adjust threshold voltage of carbon nanotube (CNT) based field-effect transistors (FETs) continuously in a wide range, which makes the application of CNT FETs especially in digital integrated circuits (ICs) easier. Top-gated FETs are fabricated using solution-processed CNT network films with stacking Pd and Sc films as gate electrodes. By decreasing the thickness of the lower layer metal (Pd) from 20 nm to zero, the effective work function of the gate decreases, thus tuning the threshold voltage (Vt) of CNT FETs from -1.0 V to 0.2 V. The continuous adjustment of threshold voltage through gate engineering lays a solid foundation for multi-threshold technology in CNT based ICs, which then can simultaneously provide high performance and low power circuit modules on one chip.

  4. Barrier inhomogeneities at vertically stacked graphene-based heterostructures.

    Science.gov (United States)

    Lin, Yen-Fu; Li, Wenwu; Li, Song-Lin; Xu, Yong; Aparecido-Ferreira, Alex; Komatsu, Katsuyoshi; Sun, Huabin; Nakaharai, Shu; Tsukagoshi, Kazuhito

    2014-01-21

    The integration of graphene and other atomically flat, two-dimensional materials has attracted much interest and been materialized very recently. An in-depth understanding of transport mechanisms in such heterostructures is essential. In this study, vertically stacked graphene-based heterostructure transistors were manufactured to elucidate the mechanism of electron injection at the interface. The temperature dependence of the electrical characteristics was investigated from 300 to 90 K. In a careful analysis of current-voltage characteristics, an unusual decrease in the effective Schottky barrier height and increase in the ideality factor were observed with decreasing temperature. A model of thermionic emission with a Gaussian distribution of barriers was able to precisely interpret the conduction mechanism. Furthermore, mapping of the effective Schottky barrier height is unmasked as a function of temperature and gate voltage. The results offer significant insight for the development of future layer-integration technology based on graphene-based heterostructures.

  5. Multi-quasiparticle high-K isomeric states in deformed nuclei

    Directory of Open Access Journals (Sweden)

    Xu F. R.

    2016-01-01

    Full Text Available In the past years, we have made many theoretical investigations on multi-quasiparticle high-K isomeric states. A deformation-pairing-configuration self-consistent calculation has been developed by calculating a configuration-constrained multi-quasiparticle potential energy surface (PES. The specific single-particle orbits that define the high-K configuration are identified and tracked (adiabatically blocked by calculating the average Nilsson numbers. The deformed Woods-Saxon potential was taken to give single-particle orbits. The configuration-constrained PES takes into account the shape polarization effect. Such calculations give good results on excitation energies, deformations and other structure information about multi-quasiparticle high-K isomeric states. Many different mass regions have been investigated.

  6. Effects of high-order deformation on high-K isomers in superheavy nuclei

    International Nuclear Information System (INIS)

    Liu, H. L.; Bertulani, C. A.; Xu, F. R.; Walker, P. M.

    2011-01-01

    Using, for the first time, configuration-constrained potential-energy-surface calculations with the inclusion of β 6 deformation, we find remarkable effects of the high-order deformation on the high-K isomers in 254 No, the focus of recent spectroscopy experiments on superheavy nuclei. For shapes with multipolarity six, the isomers are more tightly bound and, microscopically, have enhanced deformed shell gaps at N=152 and Z=100. The inclusion of β 6 deformation significantly improves the description of the very heavy high-K isomers.

  7. Identicity in high-K three quasiparticle rotational bands: a theoretical approach

    International Nuclear Information System (INIS)

    Kaur, Harjeet; Singh, Pardeep; Malik, Sham S

    2015-01-01

    The systematics are studied for the identical band phenomenon in high-K three quasiparticle rotational bands. The identical rotational bands based on the same bandhead spin are analyzed on the basis of similarities in γ-ray energies, dynamic moment of inertia and kinematic moment of inertia in particular, which is a function of deformation degrees of freedom, pairing strengths and Nilsson orbitals in nuclei. It is established that a combined effect of all these parameters decides the identicity of the moment of inertia in high-K three quasiparticle rotational bands as the systematics are backed by the Tilted Axis Cranking model calculations. (paper)

  8. Amplifying genetic logic gates.

    Science.gov (United States)

    Bonnet, Jerome; Yin, Peter; Ortiz, Monica E; Subsoontorn, Pakpoom; Endy, Drew

    2013-05-03

    Organisms must process information encoded via developmental and environmental signals to survive and reproduce. Researchers have also engineered synthetic genetic logic to realize simpler, independent control of biological processes. We developed a three-terminal device architecture, termed the transcriptor, that uses bacteriophage serine integrases to control the flow of RNA polymerase along DNA. Integrase-mediated inversion or deletion of DNA encoding transcription terminators or a promoter modulates transcription rates. We realized permanent amplifying AND, NAND, OR, XOR, NOR, and XNOR gates actuated across common control signal ranges and sequential logic supporting autonomous cell-cell communication of DNA encoding distinct logic-gate states. The single-layer digital logic architecture developed here enables engineering of amplifying logic gates to control transcription rates within and across diverse organisms.

  9. Cardiac gated ventilation

    International Nuclear Information System (INIS)

    Hanson, C.W. III; Hoffman, E.A.

    1995-01-01

    There are several theoretic advantages to synchronizing positive pressure breaths with the cardiac cycle, including the potential for improving distribution of pulmonary and myocardial blood flow and enhancing cardiac output. The authors evaluated the effects of synchronizing respiration to the cardiac cycle using a programmable ventilator and electron beam CT (EBCT) scanning. The hearts of anesthetized dogs were imaged during cardiac gated respiration with a 50 msec scan aperture. Multi slice, short axis, dynamic image data sets spanning the apex to base of the left ventricle were evaluated to determine the volume of the left ventricular chamber at end-diastole and end-systole during apnea, systolic and diastolic cardiac gating. The authors observed an increase in cardiac output of up to 30% with inspiration gated to the systolic phase of the cardiac cycle in a non-failing model of the heart

  10. Vertically stacked nanocellulose tactile sensor.

    Science.gov (United States)

    Jung, Minhyun; Kim, Kyungkwan; Kim, Bumjin; Lee, Kwang-Jae; Kang, Jae-Wook; Jeon, Sanghun

    2017-11-16

    Paper-based electronic devices are attracting considerable attention, because the paper platform has unique attributes such as flexibility and eco-friendliness. Here we report on what is claimed to be the firstly fully integrated vertically-stacked nanocellulose-based tactile sensor, which is capable of simultaneously sensing temperature and pressure. The pressure and temperature sensors are operated using different principles and are stacked vertically, thereby minimizing the interference effect. For the pressure sensor, which utilizes the piezoresistance principle under pressure, the conducting electrode was inkjet printed on the TEMPO-oxidized-nanocellulose patterned with micro-sized pyramids, and the counter electrode was placed on the nanocellulose film. The pressure sensor has a high sensitivity over a wide range (500 Pa-3 kPa) and a high durability of 10 4 loading/unloading cycles. The temperature sensor combines various materials such as poly(3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS), silver nanoparticles (AgNPs) and carbon nanotubes (CNTs) to form a thermocouple on the upper nanocellulose layer. The thermoelectric-based temperature sensors generate a thermoelectric voltage output of 1.7 mV for a temperature difference of 125 K. Our 5 × 5 tactile sensor arrays show a fast response, negligible interference, and durable sensing performance.

  11. Atomic layer deposition of crystalline SrHfO{sub 3} directly on Ge (001) for high-k dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    McDaniel, Martin D.; Ngo, Thong Q.; Ekerdt, John G., E-mail: ekerdt@utexas.edu [Department of Chemical Engineering, The University of Texas at Austin, Austin, Texas 78712 (United States); Hu, Chengqing; Jiang, Aiting; Yu, Edward T. [Microelectronics Research Center, The University of Texas at Austin, Austin, Texas 78758 (United States); Lu, Sirong; Smith, David J. [Department of Physics, Arizona State University, Tempe, Arizona 85287 (United States); Posadas, Agham; Demkov, Alexander A. [Department of Physics, The University of Texas at Austin, Austin, Texas 78712 (United States)

    2015-02-07

    The current work explores the crystalline perovskite oxide, strontium hafnate, as a potential high-k gate dielectric for Ge-based transistors. SrHfO{sub 3} (SHO) is grown directly on Ge by atomic layer deposition and becomes crystalline with epitaxial registry after post-deposition vacuum annealing at ∼700 °C for 5 min. The 2 × 1 reconstructed, clean Ge (001) surface is a necessary template to achieve crystalline films upon annealing. The SHO films exhibit excellent crystallinity, as shown by x-ray diffraction and transmission electron microscopy. The SHO films have favorable electronic properties for consideration as a high-k gate dielectric on Ge, with satisfactory band offsets (>2 eV), low leakage current (<10{sup −5} A/cm{sup 2} at an applied field of 1 MV/cm) at an equivalent oxide thickness of 1 nm, and a reasonable dielectric constant (k ∼ 18). The interface trap density (D{sub it}) is estimated to be as low as ∼2 × 10{sup 12 }cm{sup −2 }eV{sup −1} under the current growth and anneal conditions. Some interfacial reaction is observed between SHO and Ge at temperatures above ∼650 °C, which may contribute to increased D{sub it} value. This study confirms the potential for crystalline oxides grown directly on Ge by atomic layer deposition for advanced electronic applications.

  12. The untyped stack calculus and Bohm's theorem

    Directory of Open Access Journals (Sweden)

    Alberto Carraro

    2013-03-01

    Full Text Available The stack calculus is a functional language in which is in a Curry-Howard correspondence with classical logic. It enjoys confluence but, as well as Parigot's lambda-mu, does not admit the Bohm Theorem, typical of the lambda-calculus. We present a simple extension of stack calculus which is for the stack calculus what Saurin's Lambda-mu is for lambda-mu.

  13. Flexural characteristics of a stack leg

    International Nuclear Information System (INIS)

    Cook, J.

    1979-06-01

    A 30 MV tandem Van de Graaff accelerator is at present under construction at Daresbury Laboratory. The insulating stack of the machine is of modular construction, each module being 860 mm in length. Each live section stack module contains 8 insulating legs mounted between bulkhead rings. The design, fabrication (from glass discs bonded to stainless steel discs using an epoxy film adhesive) and testing of the stack legs is described. (U.K.)

  14. Voltage tunable plasmon propagation in dual gated bilayer graphene

    Science.gov (United States)

    Farzaneh, Seyed M.; Rakheja, Shaloo

    2017-10-01

    In this paper, we theoretically investigate plasmon propagation characteristics in AB and AA stacked bilayer graphene (BLG) in the presence of energy asymmetry due to an electrostatic field oriented perpendicularly to the plane of the graphene sheet. We first derive the optical conductivity of BLG using the Kubo formalism incorporating energy asymmetry and finite electron scattering. All results are obtained for room temperature (300 K) operation. By solving Maxwell's equations in a dual gate device setup, we obtain the wavevector of propagating plasmon modes in the transverse electric (TE) and transverse magnetic (TM) directions at terahertz frequencies. The plasmon wavevector allows us to compare the compression factor, propagation length, and the mode confinement of TE and TM plasmon modes in bilayer and monolayer graphene sheets and also to study the impact of material parameters on plasmon characteristics. Our results show that the energy asymmetry can be harnessed to increase the propagation length of TM plasmons in BLG. AA stacked BLG shows a larger increase in the propagation length than AB stacked BLG; conversely, it is very insensitive to the Fermi level variations. Additionally, the dual gate structure allows independent modulation of the energy asymmetry and the Fermi level in BLG, which is advantageous for reconfiguring plasmon characteristics post device fabrication.

  15. Accelerated life testing and reliability of high K multilayer ceramic capacitors

    Science.gov (United States)

    Minford, W. J.

    1981-01-01

    The reliability of one lot of high K multilayer ceramic capacitors was evaluated using accelerated life testing. The degradation in insulation resistance was characterized as a function of voltage and temperature. The times to failure at a voltage-temperature stress conformed to a lognormal distribution with a standard deviation approximately 0.5.

  16. ooi: OpenStack OCCI interface

    Directory of Open Access Journals (Sweden)

    Álvaro López García

    2016-01-01

    Full Text Available In this document we present an implementation of the Open Grid Forum’s Open Cloud Computing Interface (OCCI for OpenStack, namely ooi (Openstack occi interface, 2015  [1]. OCCI is an open standard for management tasks over cloud resources, focused on interoperability, portability and integration. ooi aims to implement this open interface for the OpenStack cloud middleware, promoting interoperability with other OCCI-enabled cloud management frameworks and infrastructures. ooi focuses on being non-invasive with a vanilla OpenStack installation, not tied to a particular OpenStack release version.

  17. ooi: OpenStack OCCI interface

    Science.gov (United States)

    López García, Álvaro; Fernández del Castillo, Enol; Orviz Fernández, Pablo

    In this document we present an implementation of the Open Grid Forum's Open Cloud Computing Interface (OCCI) for OpenStack, namely ooi (Openstack occi interface, 2015) [1]. OCCI is an open standard for management tasks over cloud resources, focused on interoperability, portability and integration. ooi aims to implement this open interface for the OpenStack cloud middleware, promoting interoperability with other OCCI-enabled cloud management frameworks and infrastructures. ooi focuses on being non-invasive with a vanilla OpenStack installation, not tied to a particular OpenStack release version.

  18. Stacking stability of MoS2 bilayer: An ab initio study

    International Nuclear Information System (INIS)

    Tao Peng; Guo Huai-Hong; Yang Teng; Zhang Zhi-Dong

    2014-01-01

    The study of the stacking stability of bilayer MoS 2 is essential since a bilayer has exhibited advantages over single layer MoS 2 in many aspects for nanoelectronic applications. We explored the relative stability, optimal sliding path between different stacking orders of bilayer MoS 2 , and (especially) the effect of inter-layer stress, by combining first-principles density functional total energy calculations and the climbing-image nudge-elastic-band (CI-NEB) method. Among five typical stacking orders, which can be categorized into two kinds (I: AA, AB and II: AA', AB', A'B), we found that stacking orders with Mo and S superposing from both layers, such as AA' and AB, is more stable than the others. With smaller computational efforts than potential energy profile searching, we can study the effect of inter-layer stress on the stacking stability. Under isobaric condition, the sliding barrier increases by a few eV/(ucGPa) from AA' to AB', compared to 0.1 eV/(ucGPa) from AB to [AB]. Moreover, we found that interlayer compressive stress can help enhance the transport properties of AA'. This study can help understand why inter-layer stress by dielectric gating materials can be an effective means to improving MoS 2 on nanoelectronic applications. (condensed matter: structural, mechanical, and thermal properties)

  19. Gate valve performance prediction

    International Nuclear Information System (INIS)

    Harrison, D.H.; Damerell, P.S.; Wang, J.K.; Kalsi, M.S.; Wolfe, K.J.

    1994-01-01

    The Electric Power Research Institute is carrying out a program to improve the performance prediction methods for motor-operated valves. As part of this program, an analytical method to predict the stem thrust required to stroke a gate valve has been developed and has been assessed against data from gate valve tests. The method accounts for the loads applied to the disc by fluid flow and for the detailed mechanical interaction of the stem, disc, guides, and seats. To support development of the method, two separate-effects test programs were carried out. One test program determined friction coefficients for contacts between gate valve parts by using material specimens in controlled environments. The other test program investigated the interaction of the stem, disc, guides, and seat using a special fixture with full-sized gate valve parts. The method has been assessed against flow-loop and in-plant test data. These tests include valve sizes from 3 to 18 in. and cover a considerable range of flow, temperature, and differential pressure. Stem thrust predictions for the method bound measured results. In some cases, the bounding predictions are substantially higher than the stem loads required for valve operation, as a result of the bounding nature of the friction coefficients in the method

  20. Stanford, Duke, Rice,... and Gates?

    Science.gov (United States)

    Carey, Kevin

    2009-01-01

    This article presents an open letter to Bill Gates. In his letter, the author suggests that Bill Gates should build a brand-new university, a great 21st-century institution of higher learning. This university will be unlike anything the world has ever seen. He asks Bill Gates not to stop helping existing colleges create the higher-education system…

  1. Direct Interaction between the Voltage Sensors Produces Cooperative Sustained Deactivation in Voltage-gated H+ Channel Dimers*

    OpenAIRE

    Okuda, Hiroko; Yonezawa, Yasushige; Takano, Yu; Okamura, Yasushi; Fujiwara, Yuichiro

    2016-01-01

    The voltage-gated H+ channel (Hv) is a voltage sensor domain-like protein consisting of four transmembrane segments (S1?S4). The native Hv structure is a homodimer, with the two channel subunits functioning cooperatively. Here we show that the two voltage sensor S4 helices within the dimer directly cooperate via a ?-stacking interaction between Trp residues at the middle of each segment. Scanning mutagenesis showed that Trp situated around the original position provides the slow gating kineti...

  2. Stacks of SPS Dipole Magnets

    CERN Multimedia

    1974-01-01

    Stacks of SPS Dipole Magnets ready for installation in the tunnel. The SPS uses a separated function lattice with dipoles for bending and quadrupoles for focusing. The 6.2 m long normal conducting dipoles are of H-type with coils that are bent-up at the ends. There are two types, B1 (total of 360) and B2 (384). Both are for a maximum field of 1.8 Tesla and have the same outer dimensions (450x800 mm2 vxh) but with different gaps (B1: 39x129 mm2, B2: 52x92 mm2) tailored to the beam size. The yoke, made of 1.5 mm thick laminations, consists of an upper and a lower half joined together in the median plane once the coils have been inserted.

  3. California dreaming?[PEM stacks

    Energy Technology Data Exchange (ETDEWEB)

    Crosse, J.

    2002-06-01

    Hyundai's Santa Fe FCEV will be on sale by the end of 2002. Hyundai uses PEM stacks that are manufactured by International Fuel Cells (IFC), a division of United Technologies. Santa Fe is equipped with a 65 kW electric powertrain of Enova systems and Shell's new gasoline reformer called Hydrogen Source. Eugene Jang, Senior Engineer - Fuel Cell and Materials at Hyundai stated that the compressor related losses on IFC system are below 3%. The maximum speed offered by the vehicle is estimated as 123km/hr while the petrol equivalent fuel consumption is quoted between 5.6L/100 km and 4.8L/100 km. Santa Fe is a compact vehicle offering better steering response and a pleasant drive. (author)

  4. Double optical gating

    Science.gov (United States)

    Gilbertson, Steve

    The observation and control of dynamics in atomic and molecular targets requires the use of laser pulses with duration less than the characteristic timescale of the process which is to be manipulated. For electron dynamics, this time scale is on the order of attoseconds where 1 attosecond = 10 -18 seconds. In order to generate pulses on this time scale, different gating methods have been proposed. The idea is to extract or "gate" a single pulse from an attosecond pulse train and switch off all the other pulses. While previous methods have had some success, they are very difficult to implement and so far very few labs have access to these unique light sources. The purpose of this work is to introduce a new method, called double optical gating (DOG), and to demonstrate its effectiveness at generating high contrast single isolated attosecond pulses from multi-cycle lasers. First, the method is described in detail and is investigated in the spectral domain. The resulting attosecond pulses produced are then temporally characterized through attosecond streaking. A second method of gating, called generalized double optical gating (GDOG), is also introduced. This method allows attosecond pulse generation directly from a carrier-envelope phase un-stabilized laser system for the first time. Next the methods of DOG and GDOG are implemented in attosecond applications like high flux pulses and extreme broadband spectrum generation. Finally, the attosecond pulses themselves are used in experiments. First, an attosecond/femtosecond cross correlation is used for characterization of spatial and temporal properties of femtosecond pulses. Then, an attosecond pump, femtosecond probe experiment is conducted to observe and control electron dynamics in helium for the first time.

  5. Vector Fields and Flows on Differentiable Stacks

    DEFF Research Database (Denmark)

    A. Hepworth, Richard

    2009-01-01

    This paper introduces the notions of vector field and flow on a general differentiable stack. Our main theorem states that the flow of a vector field on a compact proper differentiable stack exists and is unique up to a uniquely determined 2-cell. This extends the usual result on the existence...... of vector fields....

  6. Project W-420 stack monitoring system upgrades

    International Nuclear Information System (INIS)

    CARPENTER, K.E.

    1999-01-01

    This project will execute the design, procurement, construction, startup, and turnover activities for upgrades to the stack monitoring system on selected Tank Waste Remediation System (TWRS) ventilation systems. In this plan, the technical, schedule, and cost baselines are identified, and the roles and responsibilities of project participants are defined for managing the Stack Monitoring System Upgrades, Project W-420

  7. 40 CFR 61.44 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.44 Section 61.44 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... Firing § 61.44 Stack sampling. (a) Sources subject to § 61.42(b) shall be continuously sampled, during...

  8. On the "stacking fault" in copper

    NARCIS (Netherlands)

    Fransens, J.R.; Pleiter, F

    2003-01-01

    The results of a perturbed gamma-gamma angular correlations experiment on In-111 implanted into a properly cut single crystal of copper show that the defect known in the literature as "stacking fault" is not a planar faulted loop but a stacking fault tetrahedron with a size of 10-50 Angstrom.

  9. Learning OpenStack networking (Neutron)

    CERN Document Server

    Denton, James

    2014-01-01

    If you are an OpenStack-based cloud operator with experience in OpenStack Compute and nova-network but are new to Neutron networking, then this book is for you. Some networking experience is recommended, and a physical network infrastructure is required to provide connectivity to instances and other network resources configured in the book.

  10. Status of MCFC stack technology at IHI

    Energy Technology Data Exchange (ETDEWEB)

    Hosaka, M.; Morita, T.; Matsuyama, T.; Otsubo, M. [Ishikawajima-Harima Heavy Industries Co., Ltd., Tokyo (Japan)

    1996-12-31

    The molten carbonate fuel cell (MCFC) is a promising option for highly efficient power generation possible to enlarge. IHI has been studying parallel flow MCFC stacks with internal manifolds that have a large electrode area of 1m{sup 2}. IHI will make two 250 kW stacks for MW plant, and has begun to make cell components for the plant. To improve the stability of stack, soft corrugated plate used in the separator has been developed, and a way of gathering current from stacks has been studied. The DC output potential of the plant being very high, the design of electric insulation will be very important. A 20 kW short stack test was conducted in 1995 FY to certificate some of the improvements and components of the MW plant. These activities are presented below.

  11. Modular fuel-cell stack assembly

    Science.gov (United States)

    Patel, Pinakin

    2010-07-13

    A fuel cell assembly having a plurality of fuel cells arranged in a stack. An end plate assembly abuts the fuel cell at an end of said stack. The end plate assembly has an inlet area adapted to receive an exhaust gas from the stack, an outlet area and a passage connecting the inlet area and outlet area and adapted to carry the exhaust gas received at the inlet area from the inlet area to the outlet area. A further end plate assembly abuts the fuel cell at a further opposing end of the stack. The further end plate assembly has a further inlet area adapted to receive a further exhaust gas from the stack, a further outlet area and a further passage connecting the further inlet area and further outlet area and adapted to carry the further exhaust gas received at the further inlet area from the further inlet area to the further outlet area.

  12. Interface engineering and reliability characteristics of hafnium dioxide with poly silicon gate and dual metal (ruthenium-tantalum alloy, ruthenium) gate electrode for beyond 65 nm technology

    Science.gov (United States)

    Kim, Young-Hee

    Chip density and performance improvements have been driven by aggressive scaling of semiconductor devices. In both logic and memory applications, SiO 2 gate dielectrics has reached its physical limit, direct tunneling resulting from scaling down of dielectrics thickness. Therefore high-k dielectrics have attracted a great deal of attention from industries as the replacement of conventional SiO2 gate dielectrics. So far, lots of candidate materials have been evaluated and Hf-based high-k dielectrics were chosen to the promising materials for gate dielectrics. However, lots of issues were identified and more thorough researches were carried out on Hf-based high-k dielectrics. For instances, mobility degradation, charge trapping, crystallization, Fermi level pinning, interface engineering, and reliability studies. In this research, reliability study of HfO2 were explored with poly gate and dual metal (Ru-Ta alloy, Ru) gate electrode as well as interface engineering. Hard breakdown and soft breakdown were compared and Weibull slope of soft breakdown was smaller than that of hard breakdown, which led to a potential high-k scaling issue. Dynamic reliability has been studied and the combination of trapping and detrapping contributed the enhancement of lifetime projection. Polarity dependence was shown that substrate injection might reduce lifetime projection as well as it increased soft breakdown behavior. Interface tunneling mechanism was suggested with dual metal gate technology. Soft breakdown (l st breakdown) was mainly due to one layer breakdown of bi-layer structure. Low weibull slope was in part attributed to low barrier height of HfO 2 compared to interface layer. Interface layer engineering was thoroughly studied in terms of mobility, swing, and short channel effect using deep sub-micron MOSFET devices. In fact, Hf-based high-k dielectrics could be scaled down to below EOT of ˜10A and it successfully achieved the competitive performance goals. However, it is

  13. High-K rotational bands in {sup 174}Hf and {sup 175}Hf

    Energy Technology Data Exchange (ETDEWEB)

    Gjoerup, N L; Sletten, G [The Niels Bohr Institute, Roskilbe (Denmark); Walker, P M [Surrey Univ., Guildford (United Kingdom). Dept. of Physics; Bentley, M A [Daresbury Lab. (United Kingdom); Cullen, D M; Sharpey-Schafer, J F; Fallon, P; Smith, G [Liverpool Univ. (United Kingdom). Oliver Lodge Lab.

    1992-08-01

    High sensitivity experiments with {sup 48}Ca, {sup 18}O and {sup 9}Be induced reactions using the ESSA-30, TESSA-3 and NORDBALL arrays have provided extensive new information on the high spin level structures of {sup 174}Hf and {sup 175}Hf. During the series of experiments, several new bands have been found and most known bands have been extended considerably. Spin and excitation energy ranges for {sup 174}Hf are now {approx} 35 {Dirac_h} and {approx} 13 MeV, respectively, and for {sup 175}Hf ranges are {approx} 30 {Dirac_h} and {approx} 7 MeV. respectively. Several new high-K structures have been found in {sup 174}Hf and the structure of these and the already known high-K bands in both nuclei together with the new Tilted Axis Cranking approach might explain the small K-hindrances observed for K-isomers in this region. (author). 8 refs., 2 figs.

  14. Noise Gating Solar Images

    Science.gov (United States)

    DeForest, Craig; Seaton, Daniel B.; Darnell, John A.

    2017-08-01

    I present and demonstrate a new, general purpose post-processing technique, "3D noise gating", that can reduce image noise by an order of magnitude or more without effective loss of spatial or temporal resolution in typical solar applications.Nearly all scientific images are, ultimately, limited by noise. Noise can be direct Poisson "shot noise" from photon counting effects, or introduced by other means such as detector read noise. Noise is typically represented as a random variable (perhaps with location- or image-dependent characteristics) that is sampled once per pixel or once per resolution element of an image sequence. Noise limits many aspects of image analysis, including photometry, spatiotemporal resolution, feature identification, morphology extraction, and background modeling and separation.Identifying and separating noise from image signal is difficult. The common practice of blurring in space and/or time works because most image "signal" is concentrated in the low Fourier components of an image, while noise is evenly distributed. Blurring in space and/or time attenuates the high spatial and temporal frequencies, reducing noise at the expense of also attenuating image detail. Noise-gating exploits the same property -- "coherence" -- that we use to identify features in images, to separate image features from noise.Processing image sequences through 3-D noise gating results in spectacular (more than 10x) improvements in signal-to-noise ratio, while not blurring bright, resolved features in either space or time. This improves most types of image analysis, including feature identification, time sequence extraction, absolute and relative photometry (including differential emission measure analysis), feature tracking, computer vision, correlation tracking, background modeling, cross-scale analysis, visual display/presentation, and image compression.I will introduce noise gating, describe the method, and show examples from several instruments (including SDO

  15. Probing Temperature Inside Planar SOFC Short Stack, Modules, and Stack Series

    Science.gov (United States)

    Yu, Rong; Guan, Wanbing; Zhou, Xiao-Dong

    2017-02-01

    Probing temperature inside a solid oxide fuel cell (SOFC) stack lies at the heart of the development of high-performance and stable SOFC systems. In this article, we report our recent work on the direct measurements of the temperature in three types of SOFC systems: a 5-cell short stack, a 30-cell stack module, and a stack series consisting of two 30-cell stack modules. The dependence of temperature on the gas flow rate and current density was studied under a current sweep or steady-state operation. During the current sweep, the temperature inside the 5-cell stack decreased with increasing current, while it increased significantly at the bottom and top of the 30-cell stack. During a steady-state operation, the temperature of the 5-cell stack was stable while it was increased in the 30-cell stack. In the stack series, the maximum temperature gradient reached 190°C when the gas was not preheated. If the gas was preheated and the temperature gradient was reduced to 23°C in the stack series with the presence of a preheating gas and segmented temperature control, this resulted in a low degradation rate.

  16. The impact of stack geometry and mean pressure on cold end temperature of stack in thermoacoustic refrigeration systems

    Science.gov (United States)

    Wantha, Channarong

    2018-02-01

    This paper reports on the experimental and simulation studies of the influence of stack geometries and different mean pressures on the cold end temperature of the stack in the thermoacoustic refrigeration system. The stack geometry was tested, including spiral stack, circular pore stack and pin array stack. The results of this study show that the mean pressure of the gas in the system has a significant impact on the cold end temperature of the stack. The mean pressure of the gas in the system corresponds to thermal penetration depth, which results in a better cold end temperature of the stack. The results also show that the cold end temperature of the pin array stack decreases more than that of the spiral stack and circular pore stack geometry by approximately 63% and 70%, respectively. In addition, the thermal area and viscous area of the stack are analyzed to explain the results of such temperatures of thermoacoustic stacks.

  17. Phosphorus oxide gate dielectric for black phosphorus field effect transistors

    Science.gov (United States)

    Dickerson, W.; Tayari, V.; Fakih, I.; Korinek, A.; Caporali, M.; Serrano-Ruiz, M.; Peruzzini, M.; Heun, S.; Botton, G. A.; Szkopek, T.

    2018-04-01

    The environmental stability of the layered semiconductor black phosphorus (bP) remains a challenge. Passivation of the bP surface with phosphorus oxide, POx, grown by a reactive ion etch with oxygen plasma is known to improve photoluminescence efficiency of exfoliated bP flakes. We apply phosphorus oxide passivation in the fabrication of bP field effect transistors using a gate stack consisting of a POx layer grown by reactive ion etching followed by atomic layer deposition of Al2O3. We observe room temperature top-gate mobilities of 115 cm2 V-1 s-1 in ambient conditions, which we attribute to the low defect density of the bP/POx interface.

  18. A quantum Fredkin gate

    Science.gov (United States)

    Patel, Raj B.; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C.; Pryde, Geoff J.

    2016-01-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently. PMID:27051868

  19. A quantum Fredkin gate.

    Science.gov (United States)

    Patel, Raj B; Ho, Joseph; Ferreyrol, Franck; Ralph, Timothy C; Pryde, Geoff J

    2016-03-01

    Minimizing the resources required to build logic gates into useful processing circuits is key to realizing quantum computers. Although the salient features of a quantum computer have been shown in proof-of-principle experiments, difficulties in scaling quantum systems have made more complex operations intractable. This is exemplified in the classical Fredkin (controlled-SWAP) gate for which, despite theoretical proposals, no quantum analog has been realized. By adding control to the SWAP unitary, we use photonic qubit logic to demonstrate the first quantum Fredkin gate, which promises many applications in quantum information and measurement. We implement example algorithms and generate the highest-fidelity three-photon Greenberger-Horne-Zeilinger states to date. The technique we use allows one to add a control operation to a black-box unitary, something that is impossible in the standard circuit model. Our experiment represents the first use of this technique to control a two-qubit operation and paves the way for larger controlled circuits to be realized efficiently.

  20. Controlling the layer localization of gapless states in bilayer graphene with a gate voltage

    Science.gov (United States)

    Jaskólski, W.; Pelc, M.; Bryant, Garnett W.; Chico, Leonor; Ayuela, A.

    2018-04-01

    Experiments in gated bilayer graphene with stacking domain walls present topological gapless states protected by no-valley mixing. Here we research these states under gate voltages using atomistic models, which allow us to elucidate their origin. We find that the gate potential controls the layer localization of the two states, which switches non-trivially between layers depending on the applied gate voltage magnitude. We also show how these bilayer gapless states arise from bands of single-layer graphene by analyzing the formation of carbon bonds between layers. Based on this analysis we provide a model Hamiltonian with analytical solutions, which explains the layer localization as a function of the ratio between the applied potential and interlayer hopping. Our results open a route for the manipulation of gapless states in electronic devices, analogous to the proposed writing and reading memories in topological insulators.

  1. Five stacks over the Danube

    International Nuclear Information System (INIS)

    Anon.

    1998-01-01

    Following the departure of Communism, Hungary adopted the most ambitious privatisation programme of all the eastern European countries. Within a year the state electricity company, MVM, and the oil and gas company, MOL, were prepared for sale and a consequent injection of foreign capital. Control of prices by central government inhibited investment initially but a new legal framework put in place in 1995 introduced a pricing regime more attractive to external investors. Particular interest was shown in the 2,200MW mixed heavy oil and natural gas power plant at Dunamenti on the Danube, characterised by its five stacks of varying height which reflect the changing technology employed at the plant. The bid was won by Tractabel of Belgium who have been highly successful in improving plant efficiency. However, the impact of privatisation is now being felt in uncertainty over fuel supply. Removing such uncertainty in order to maintain existing investment and provide the additional 4000MW of generating capacity needed to keep pace with demand, is a major problem which the incoming government faces. (UK)

  2. Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

    International Nuclear Information System (INIS)

    Ghosh, Bahniman; Mondal, Partha; Akram, M. W.; Bal, Punyasloka; Salimath, Akshay Kumar

    2014-01-01

    We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability. (semiconductor devices)

  3. Multiple Independent Gate FETs: How Many Gates Do We Need?

    OpenAIRE

    Amarù, Luca; Hills, Gage; Gaillardon, Pierre-Emmanuel; Mitra, Subhasish; De Micheli, Giovanni

    2015-01-01

    Multiple Independent Gate Field Effect Transistors (MIGFETs) are expected to push FET technology further into the semiconductor roadmap. In a MIGFET, supplementary gates either provide (i) enhanced conduction properties or (ii) more intelligent switching functions. In general, each additional gate also introduces a side implementation cost. To enable more efficient digital systems, MIGFETs must leverage their expressive power to realize complex logic circuits with few physical resources. Rese...

  4. Density of oxidation-induced stacking faults in damaged silicon

    NARCIS (Netherlands)

    Kuper, F.G.; Hosson, J.Th.M. De; Verwey, J.F.

    1986-01-01

    A model for the relation between density and length of oxidation-induced stacking faults on damaged silicon surfaces is proposed, based on interactions of stacking faults with dislocations and neighboring stacking faults. The model agrees with experiments.

  5. 100-nm gate lithography for double-gate transistors

    Science.gov (United States)

    Krasnoperova, Azalia A.; Zhang, Ying; Babich, Inna V.; Treichler, John; Yoon, Jung H.; Guarini, Kathryn; Solomon, Paul M.

    2001-09-01

    The double gate field effect transistor (FET) is an exploratory device that promises certain performance advantages compared to traditional CMOS FETs. It can be scaled down further than the traditional devices because of the greater electrostatic control by the gates on the channel (about twice as short a channel length for the same gate oxide thickness), has steeper sub-threshold slope and about double the current for the same width. This paper presents lithographic results for double gate FET's developed at IBM's T. J. Watson Research Center. The device is built on bonded wafers with top and bottom gates self-aligned to each other. The channel is sandwiched between the top and bottom polysilicon gates and the gate length is defined using DUV lithography. An alternating phase shift mask was used to pattern gates with critical dimensions of 75 nm, 100 nm and 125 nm in photoresist. 50 nm gates in photoresist have also been patterned by 20% over-exposure of nominal 100 nm lines. No trim mask was needed because of a specific way the device was laid out. UV110 photoresist from Shipley on AR-3 antireflective layer were used. Process windows, developed and etched patterns are presented.

  6. Dynamical stability of slip-stacking particles

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, Jeffrey; Zwaska, Robert

    2014-09-01

    We study the stability of particles in slip-stacking configuration, used to nearly double proton beam intensity at Fermilab. We introduce universal area factors to calculate the available phase space area for any set of beam parameters without individual simulation. We find perturbative solutions for stable particle trajectories. We establish Booster beam quality requirements to achieve 97% slip-stacking efficiency. We show that slip-stacking dynamics directly correspond to the driven pendulum and to the system of two standing-wave traps moving with respect to each other.

  7. Text-Filled Stacked Area Graphs

    DEFF Research Database (Denmark)

    Kraus, Martin

    2011-01-01

    -filled stacked area graphs; i.e., graphs that feature stacked areas that are filled with small-typed text. Since these graphs allow for computing the text layout automatically, it is possible to include large amounts of textual detail with very little effort. We discuss the most important challenges and some...... solutions for the design of text-filled stacked area graphs with the help of an exemplary visualization of the genres, publication years, and titles of a database of several thousand PC games....

  8. Tunable electro-optic filter stack

    Science.gov (United States)

    Fontecchio, Adam K.; Shriyan, Sameet K.; Bellingham, Alyssa

    2017-09-05

    A holographic polymer dispersed liquid crystal (HPDLC) tunable filter exhibits switching times of no more than 20 microseconds. The HPDLC tunable filter can be utilized in a variety of applications. An HPDLC tunable filter stack can be utilized in a hyperspectral imaging system capable of spectrally multiplexing hyperspectral imaging data acquired while the hyperspectral imaging system is airborne. HPDLC tunable filter stacks can be utilized in high speed switchable optical shielding systems, for example as a coating for a visor or an aircraft canopy. These HPDLC tunable filter stacks can be fabricated using a spin coating apparatus and associated fabrication methods.

  9. Enhanced intrinsic voltage gain in artificially stacked bilayer CVD graphene field effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Pandey, Himadri; Kataria, Satender [RWTH Aachen University, Chair for Electronic Devices, Aachen (Germany); University of Siegen, School of Science and Technology, Siegen (Germany); Aguirre-Morales, Jorge-Daniel; Fregonese, Sebastien; Zimmer, Thomas [IMS Laboratory, Centre National de la Recherche Scientifique, University of Bordeaux, Talence (France); Passi, Vikram [University of Siegen, School of Science and Technology, Siegen (Germany); AMO GmbH, Advanced Microelectronics Center Aachen (Germany); Iannazzo, Mario; Alarcon, Eduard [Technical University of Catalonia, Department of Electronics Engineering, UPC, Barcelona (Spain); Lemme, Max C. [RWTH Aachen University, Chair for Electronic Devices, Aachen (Germany); University of Siegen, School of Science and Technology, Siegen (Germany); AMO GmbH, Advanced Microelectronics Center Aachen (Germany)

    2017-11-15

    We report on electronic transport in dual-gate, artificially stacked bilayer graphene field effect transistors (BiGFETs) fabricated from large-area chemical vapor deposited (CVD) graphene. The devices show enhanced tendency to current saturation, which leads to reduced minimum output conductance values. This results in improved intrinsic voltage gain of the devices when compared to monolayer graphene FETs. We employ a physics based compact model originally developed for Bernal stacked bilayer graphene FETs (BSBGFETs) to explore the observed phenomenon. The improvement in current saturation may be attributed to increased charge carrier density in the channel and thus reduced saturation velocity due to carrier-carrier scattering. (copyright 2017 by WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim)

  10. Expert Oracle GoldenGate

    CERN Document Server

    Prusinski, Ben; Chung, Richard

    2011-01-01

    Expert Oracle GoldenGate is a hands-on guide to creating and managing complex data replication environments using the latest in database replication technology from Oracle. GoldenGate is the future in replication technology from Oracle, and aims to be best-of-breed. GoldenGate supports homogeneous replication between Oracle databases. It supports heterogeneous replication involving other brands such as Microsoft SQL Server and IBM DB2 Universal Server. GoldenGate is high-speed, bidirectional, highly-parallelized, and makes only a light impact on the performance of databases involved in replica

  11. Characterization of Piezoelectric Stacks for Space Applications

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher; Aldrich, Jack; Blodget, Chad; Bao, Xiaoqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to actuate mechanisms to precision levels in the nanometer range and below. Co-fired multilayer piezoelectric stacks offer the required actuation precision that is needed for such mechanisms. To obtain performance statistics and determine reliability for extended use, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and high temperatures and voltages. In order to study the lifetime performance of these stacks, five actuators were driven sinusoidally for up to ten billion cycles. An automated data acquisition system was developed and implemented to monitor each stack's electrical current and voltage waveforms over the life of the test. As part of the monitoring tests, the displacement, impedance, capacitance and leakage current were measured to assess the operation degradation. This paper presents some of the results of this effort.

  12. The stack on software and sovereignty

    CERN Document Server

    Bratton, Benjamin H

    2016-01-01

    A comprehensive political and design theory of planetary-scale computation proposing that The Stack -- an accidental megastructure -- is both a technological apparatus and a model for a new geopolitical architecture.

  13. Development of Auto-Stacking Warehouse Truck

    Directory of Open Access Journals (Sweden)

    Kuo-Hsien Hsia

    2018-03-01

    Full Text Available Warehouse automation is a very important issue for the promotion of traditional industries. For the production of larger and stackable products, it is usually necessary to operate a fork-lifter for the stacking and storage of the products by a skilled person. The general autonomous warehouse-truck does not have the ability of stacking objects. In this paper, we develop a prototype of auto-stacking warehouse-truck that can work without direct operation by a skill person. With command made by an RFID card, the stacker truck can take the packaged product to the warehouse on the prior-planned route and store it in a stacking way in the designated storage area, or deliver the product to the shipping area or into the container from the storage area. It can significantly reduce the manpower requirements of the skilled-person of forklift technician and improve the safety of the warehousing area.

  14. High-K structures in {sup 180}W and {sup 181}W

    Energy Technology Data Exchange (ETDEWEB)

    Yeung, K C; Walker, P M; Singleton, B D.D. [Surrey Univ., Guildford (United Kingdom). Dept. of Physics; Urban, W; Lisle, J C; Copnell, J; Mo, J N [Manchester Univ. (United Kingdom). Schuster Lab.; Joyce, M J [Liverpool Univ. (United Kingdom). Oliver Lodge Lab.; Gjorup, N L; Sletten, G [Risoe National Lab., Roskilde (Denmark)

    1992-08-01

    In each of the prolate-deformed isotopes {sup 180}W and {sup 181}W, a very high-K non-collective state has been found which decays directly into the corresponding collective ground-state rotational band. There is complete breakdown of the K-selection rule, in contrast to the partial breakdown observed recently in {sup 174}Hf and {sup 182}Os. Nevertheless, the non-collective states themselves retain characteristics associated with a prolate axially symmetric shape, implying that K is still a useful quantum number. (author). 17 refs., 2 figs.

  15. The effect of injection of high K+ solution into scala media.

    Science.gov (United States)

    Fukazawa, T; Ohmura, M; Yagi, N

    1987-01-01

    Thirty guinea pig ears were studied to investigate the effect of endolymphatic hydrops on the cochlea. High K+ solution was injected into the scala media, and cochlear microphonics (CM) and endocochlear potential (EP) were observed before, during and after the injection. The CM amplitude decreased rapidly after injection, ending in a depressed plateau value. By contrast, EP remained almost unchanged. By changing the composition of the solution it was suggested that the effect of the injection was mechanical one, rather than biochemical. In three ears, spontaneous recovery of CM was observed during a relatively long interval after the injection. The meaning of these findings for the hearing loss in Meniere's disease is discussed.

  16. Exploring online evolution of network stacks

    OpenAIRE

    Imai, Pierre

    2013-01-01

    Network stacks today follow a one-size-fits-all philosophy. They are mostly kept unmodified due to often prohibitive costs of engineering, deploying and administrating customisation of the networking software, with the Internet stack architecture still largely being based on designs and assumptions made for the ARPANET 40 years ago. We venture that heterogeneous and rapidly changing networks of the future require, in order to be successful, run-time self-adaptation mechanisms at different tim...

  17. A novel optical gating method for laser gated imaging

    Science.gov (United States)

    Ginat, Ran; Schneider, Ron; Zohar, Eyal; Nesher, Ofer

    2013-06-01

    For the past 15 years, Elbit Systems is developing time-resolved active laser-gated imaging (LGI) systems for various applications. Traditional LGI systems are based on high sensitive gated sensors, synchronized to pulsed laser sources. Elbit propriety multi-pulse per frame method, which is being implemented in LGI systems, improves significantly the imaging quality. A significant characteristic of the LGI is its ability to penetrate a disturbing media, such as rain, haze and some fog types. Current LGI systems are based on image intensifier (II) sensors, limiting the system in spectral response, image quality, reliability and cost. A novel propriety optical gating module was developed in Elbit, untying the dependency of LGI system on II. The optical gating module is not bounded to the radiance wavelength and positioned between the system optics and the sensor. This optical gating method supports the use of conventional solid state sensors. By selecting the appropriate solid state sensor, the new LGI systems can operate at any desired wavelength. In this paper we present the new gating method characteristics, performance and its advantages over the II gating method. The use of the gated imaging systems is described in a variety of applications, including results from latest field experiments.

  18. A Time-predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspour, Sahar; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to le...... of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures.......Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less...... precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation...

  19. StackGAN++: Realistic Image Synthesis with Stacked Generative Adversarial Networks

    OpenAIRE

    Zhang, Han; Xu, Tao; Li, Hongsheng; Zhang, Shaoting; Wang, Xiaogang; Huang, Xiaolei; Metaxas, Dimitris

    2017-01-01

    Although Generative Adversarial Networks (GANs) have shown remarkable success in various tasks, they still face challenges in generating high quality images. In this paper, we propose Stacked Generative Adversarial Networks (StackGAN) aiming at generating high-resolution photo-realistic images. First, we propose a two-stage generative adversarial network architecture, StackGAN-v1, for text-to-image synthesis. The Stage-I GAN sketches the primitive shape and colors of the object based on given...

  20. Quasi-particle and collective magnetism: Rotation, pairing and blocking in high-K isomers

    International Nuclear Information System (INIS)

    Stone, N.J.; Stone, J.R.; Walker, P.M.; Bingham, C.R.

    2013-01-01

    For the first time, a wide range of collective magnetic g-factors g R , obtained from a novel analysis of experimental data for multi-quasi-particle configurations in high-K isomers, is shown to exhibit a striking systematic variation with the relative number of proton and neutron quasi-particles, N p −N n . Using the principle of additivity, the quasi-particle contribution to magnetism in high-K isomers of Lu–Re, Z=71–75, has been estimated. Based on these estimates, band-structure branching ratio data are used to explore the behavior of the collective contribution as the number and proton/neutron nature (N p , N n ), of the quasi-particle excitations, change. Basic ideas of pairing, its quenching by quasi-particle excitation and the consequent changes to moment of inertia and collective magnetism are discussed. Existing model calculations do not reproduce the observed g R variation adequately. The paired superfluid system of nucleons in these nuclei, and their excitations, present properties of general physics interest. The new-found systematic behavior of g R in multi-quasi-particle excitations of this unique system, showing variation from close to zero for multi-neutron states to above 0.5 for multi-proton states, opens a fresh window on these effects and raises the important question of just which nucleons contribute to the ‘collective’ properties of these nuclei

  1. Penn State DOE GATE Program

    Energy Technology Data Exchange (ETDEWEB)

    Anstrom, Joel

    2012-08-31

    The Graduate Automotive Technology Education (GATE) Program at The Pennsylvania State University (Penn State) was established in October 1998 pursuant to an award from the U.S. Department of Energy (U.S. DOE). The focus area of the Penn State GATE Program is advanced energy storage systems for electric and hybrid vehicles.

  2. Piezoconductivity of gated suspended graphene

    NARCIS (Netherlands)

    Medvedyeva, M.V.; Blanter, Y.M.

    2011-01-01

    We investigate the conductivity of graphene sheet deformed over a gate. The effect of the deformation on the conductivity is twofold: The lattice distortion can be represented as pseudovector potential in the Dirac equation formalism, whereas the gate causes inhomogeneous density redistribution. We

  3. Low-frequency noise in multilayer MoS2 field-effect transistors: the effect of high-k passivation.

    Science.gov (United States)

    Na, Junhong; Joo, Min-Kyu; Shin, Minju; Huh, Junghwan; Kim, Jae-Sung; Piao, Mingxing; Jin, Jun-Eon; Jang, Ho-Kyun; Choi, Hyung Jong; Shim, Joon Hyung; Kim, Gyu-Tae

    2014-01-07

    Diagnosing of the interface quality and the interactions between insulators and semiconductors is significant to achieve the high performance of nanodevices. Herein, low-frequency noise (LFN) in mechanically exfoliated multilayer molybdenum disulfide (MoS2) (~11.3 nm-thick) field-effect transistors with back-gate control was characterized with and without an Al2O3 high-k passivation layer. The carrier number fluctuation (CNF) model associated with trapping/detrapping the charge carriers at the interface nicely described the noise behavior in the strong accumulation regime both with and without the Al2O3 passivation layer. The interface trap density at the MoS2-SiO2 interface was extracted from the LFN analysis, and estimated to be Nit ~ 10(10) eV(-1) cm(-2) without and with the passivation layer. This suggested that the accumulation channel induced by the back-gate was not significantly influenced by the passivation layer. The Hooge mobility fluctuation (HMF) model implying the bulk conduction was found to describe the drain current fluctuations in the subthreshold regime, which is rarely observed in other nanodevices, attributed to those extremely thin channel sizes. In the case of the thick-MoS2 (~40 nm-thick) without the passivation, the HMF model was clearly observed all over the operation regime, ensuring the existence of the bulk conduction in multilayer MoS2. With the Al2O3 passivation layer, the change in the noise behavior was explained from the point of formation of the additional top channel in the MoS2 because of the fixed charges in the Al2O3. The interface trap density from the additional CNF model was Nit = 1.8 × 10(12) eV(-1) cm(-2) at the MoS2-Al2O3 interface.

  4. Impact and Origin of Interface States in MOS Capacitor with Monolayer MoS2 and HfO2 High-k Dielectric.

    Science.gov (United States)

    Xia, Pengkun; Feng, Xuewei; Ng, Rui Jie; Wang, Shijie; Chi, Dongzhi; Li, Cequn; He, Zhubing; Liu, Xinke; Ang, Kah-Wee

    2017-01-13

    Two-dimensional layered semiconductors such as molybdenum disulfide (MoS 2 ) at the quantum limit are promising material for nanoelectronics and optoelectronics applications. Understanding the interface properties between the atomically thin MoS 2 channel and gate dielectric is fundamentally important for enhancing the carrier transport properties. Here, we investigate the frequency dispersion mechanism in a metal-oxide-semiconductor capacitor (MOSCAP) with a monolayer MoS 2 and an ultra-thin HfO 2 high-k gate dielectric. We show that the existence of sulfur vacancies at the MoS 2 -HfO 2 interface is responsible for the generation of interface states with a density (D it ) reaching ~7.03 × 10 11  cm -2  eV -1 . This is evidenced by a deficit S:Mo ratio of ~1.96 using X-ray photoelectron spectroscopy (XPS) analysis, which deviates from its ideal stoichiometric value. First-principles calculations within the density-functional theory framework further confirms the presence of trap states due to sulfur deficiency, which exist within the MoS 2 bandgap. This corroborates to a voltage-dependent frequency dispersion of ~11.5% at weak accumulation which decreases monotonically to ~9.0% at strong accumulation as the Fermi level moves away from the mid-gap trap states. Further reduction in D it could be achieved by thermally diffusing S atoms to the MoS 2 -HfO 2 interface to annihilate the vacancies. This work provides an insight into the interface properties for enabling the development of MoS 2 devices with carrier transport enhancement.

  5. On photonic controlled phase gates

    International Nuclear Information System (INIS)

    Kieling, K; Eisert, J; O'Brien, J L

    2010-01-01

    As primitives for entanglement generation, controlled phase gates have a central role in quantum computing. Especially in ideas realizing instances of quantum computation in linear optical gate arrays, a closer look can be rewarding. In such architectures, all effective nonlinearities are induced by measurements. Hence the probability of success is a crucial parameter of such quantum gates. In this paper, we discuss this question for controlled phase gates that implement an arbitrary phase with one and two control qubits. Within the class of post-selected gates in dual-rail encoding with vacuum ancillas, we identify the optimal success probabilities. We construct networks that allow for implementation using current experimental capabilities in detail. The methods employed here appear specifically useful with the advent of integrated linear optical circuits, providing stable interferometers on monolithic structures.

  6. GATE: Improving the computational efficiency

    International Nuclear Information System (INIS)

    Staelens, S.; De Beenhouwer, J.; Kruecker, D.; Maigne, L.; Rannou, F.; Ferrer, L.; D'Asseler, Y.; Buvat, I.; Lemahieu, I.

    2006-01-01

    GATE is a software dedicated to Monte Carlo simulations in Single Photon Emission Computed Tomography (SPECT) and Positron Emission Tomography (PET). An important disadvantage of those simulations is the fundamental burden of computation time. This manuscript describes three different techniques in order to improve the efficiency of those simulations. Firstly, the implementation of variance reduction techniques (VRTs), more specifically the incorporation of geometrical importance sampling, is discussed. After this, the newly designed cluster version of the GATE software is described. The experiments have shown that GATE simulations scale very well on a cluster of homogeneous computers. Finally, an elaboration on the deployment of GATE on the Enabling Grids for E-Science in Europe (EGEE) grid will conclude the description of efficiency enhancement efforts. The three aforementioned methods improve the efficiency of GATE to a large extent and make realistic patient-specific overnight Monte Carlo simulations achievable

  7. Start-Stop Test Procedures on the PEMFC Stack Level

    DEFF Research Database (Denmark)

    Mitzel, Jens; Nygaard, Frederik; Veltzé, Sune

    The test is addressed to investigate the influence on stack durability of a long stop followed by a restart of a stack. Long stop should be defined as a stop in which the anodic compartment is fully filled by air due to stack leakages. In systems, leakage level of the stack is low and time to fil...

  8. Principles for Instructional Stack Development in HyperCard.

    Science.gov (United States)

    McEneaney, John E.

    The purpose of this paper is to provide information about obtaining and using HyperCard stacks that introduce users to principles of stack development. The HyperCard stacks described are available for downloading free of charge from a server at Indiana University South Bend. Specific directions are given for stack use, with advice for beginners. A…

  9. Pentacene-Based Thin Film Transistor with Inkjet-Printed Nanocomposite High-K Dielectrics

    Directory of Open Access Journals (Sweden)

    Chao-Te Liu

    2012-01-01

    Full Text Available The nanocomposite gate insulating film of a pentacene-based thin film transistor was deposited by inkjet printing. In this study, utilizing the pearl miller to crumble the agglomerations and the dispersant to well stabilize the dispersion of nano-TiO2 particles in the polymer matrix of the ink increases the dose concentration for pico-jetting, which could be as the gate dielectric film made by inkjet printing without the photography process. Finally, we realized top contact pentacene-TFTs and successfully accomplished the purpose of directly patternability and increase the performance of the device based on the nanocomposite by inkjet printing. These devices exhibited p-channel TFT characteristics with a high field-effect mobility (a saturation mobility of ̃0.58 cm2 V−1 s−1, a large current ratio (>103 and a low operation voltage (<6 V. Furthermore, we accorded the deposited mechanisms which caused the interface difference between of inkjet printing and spin coating. And we used XRD, SEM, Raman spectroscopy to help us analyze the transfer characteristics of pentacene films and the performance of OTFTs.

  10. Gated equilibrium bloodpool scintigraphy

    International Nuclear Information System (INIS)

    Reinders Folmer, S.C.C.

    1981-01-01

    This thesis deals with the clinical applications of gated equilibrium bloodpool scintigraphy, performed with either a gamma camera or a portable detector system, the nuclear stethoscope. The main goal has been to define the value and limitations of noninvasive measurements of left ventricular ejection fraction as a parameter of cardiac performance in various disease states, both for diagnostic purposes as well as during follow-up after medical or surgical intervention. Secondly, it was attempted to extend the use of the equilibrium bloodpool techniques beyond the calculation of ejection fraction alone by considering the feasibility to determine ventricular volumes and by including the possibility of quantifying valvular regurgitation. In both cases, it has been tried to broaden the perspective of the observations by comparing them with results of other, invasive and non-invasive, procedures, in particular cardiac catheterization, M-mode echocardiography and myocardial perfusion scintigraphy. (Auth.)

  11. EmuStack: An OpenStack-Based DTN Network Emulation Platform (Extended Version

    Directory of Open Access Journals (Sweden)

    Haifeng Li

    2016-01-01

    Full Text Available With the advancement of computing and network virtualization technology, the networking research community shows great interest in network emulation. Compared with network simulation, network emulation can provide more relevant and comprehensive details. In this paper, EmuStack, a large-scale real-time emulation platform for Delay Tolerant Network (DTN, is proposed. EmuStack aims at empowering network emulation to become as simple as network simulation. Based on OpenStack, distributed synchronous emulation modules are developed to enable EmuStack to implement synchronous and dynamic, precise, and real-time network emulation. Meanwhile, the lightweight approach of using Docker container technology and network namespaces allows EmuStack to support a (up to hundreds of nodes large-scale topology with only several physical nodes. In addition, EmuStack integrates the Linux Traffic Control (TC tools with OpenStack for managing and emulating the virtual link characteristics which include variable bandwidth, delay, loss, jitter, reordering, and duplication. Finally, experiences with our initial implementation suggest the ability to run and debug experimental network protocol in real time. EmuStack environment would bring qualitative change in network research works.

  12. Forced Air-Breathing PEMFC Stacks

    Directory of Open Access Journals (Sweden)

    K. S. Dhathathreyan

    2012-01-01

    Full Text Available Air-breathing fuel cells have a great potential as power sources for various electronic devices. They differ from conventional fuel cells in which the cells take up oxygen from ambient air by active or passive methods. The air flow occurs through the channels due to concentration and temperature gradient between the cell and the ambient conditions. However developing a stack is very difficult as the individual cell performance may not be uniform. In order to make such a system more realistic, an open-cathode forced air-breathing stacks were developed by making appropriate channel dimensions for the air flow for uniform performance in a stack. At CFCT-ARCI (Centre for Fuel Cell Technology-ARC International we have developed forced air-breathing fuel cell stacks with varying capacity ranging from 50 watts to 1500 watts. The performance of the stack was analysed based on the air flow, humidity, stability, and so forth, The major advantage of the system is the reduced number of bipolar plates and thereby reduction in volume and weight. However, the thermal management is a challenge due to the non-availability of sufficient air flow to remove the heat from the system during continuous operation. These results will be discussed in this paper.

  13. Levitation characteristics of HTS tape stacks

    Energy Technology Data Exchange (ETDEWEB)

    Pokrovskiy, S. V.; Ermolaev, Y. S.; Rudnev, I. A. [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation)

    2015-03-15

    Due to the considerable development of the technology of second generation high-temperature superconductors and a significant improvement in their mechanical and transport properties in the last few years it is possible to use HTS tapes in the magnetic levitation systems. The advantages of tapes on a metal substrate as compared with bulk YBCO material primarily in the strength, and the possibility of optimizing the convenience of manufacturing elements of levitation systems. In the present report presents the results of the magnetic levitation force measurements between the stack of HTS tapes containing of tapes and NdFeB permanent magnet in the FC and ZFC regimes. It was found a non- linear dependence of the levitation force from the height of the array of stack in both modes: linear growth at small thickness gives way to flattening and constant at large number of tapes in the stack. Established that the levitation force of stacks comparable to that of bulk samples. The numerical calculations using finite element method showed that without the screening of the applied field the levitation force of the bulk superconductor and the layered superconductor stack with a critical current of tapes increased by the filling factor is exactly the same, and taking into account the screening force slightly different.

  14. Modelling of Leakage Current Through Double Dielectric Gate Stack in Metal Oxide Semiconductor Capacitor

    International Nuclear Information System (INIS)

    Fatimah A Noor; Mikrajuddin Abdullah; Sukirno; Khairurrijal

    2008-01-01

    In this paper, we have derived analytical expression of leakage current through double barriers in Metal Oxide Semiconductor (MOS) capacitor. Initially, electron transmittance through the MOS capacitor was derived by including the coupling between the transverse and longitudinal energies. The transmittance was then employed to obtain leakage current through the double barrier. In this model, we observed the effect of electron velocity due to the coupling effect and the oxide thickness to the leakage current. The calculated results showed that the leakage current decreases as the electron velocity increases. (author)

  15. Anomalous positive flatband voltage shifts in metal gate stacks containing rare-earth oxide capping layers

    KAUST Repository

    Caraveo-Frescas, J. A.; Hedhili, Mohamed N.; Wang, H.; Schwingenschlö gl, Udo; Alshareef, Husam N.

    2012-01-01

    measure a ∼350 mV negative shift with the Si overlayer present and a ∼110 mV positive shift with the Si overlayer removed. This effect is correlated to a positive change in the average electrostatic potential at the TaN/dielectric interface which

  16. Pairing and Blocking in High-K Isomers: Variation of the Collective Parameter gR

    Directory of Open Access Journals (Sweden)

    Stone N.J.

    2013-12-01

    Full Text Available Using the principle of additivity, the quasi-particle contribution to magnetism in high-K isomers of Lu - Re has been estimated. Based on these estimates band structure branching ratio data is used to explore the behavior of the collective contribution as the number and neutron/proton nature (Np, Nn, of the quasi-particle excitations, change. A striking systematic variation of the collective g-factor gR with the difference, Np – Nn, is revealed. Basic ideas of pairing, its quenching by quasi-particle excitation and the consequent changes to moment of inertia and collective magnetism are discussed. The new found systematic behaviour of gR opens a fresh window on these effects amenable to detailed theoretical investigation.

  17. Maintaining K+ balance on the low-Na+, high-K+ diet

    Science.gov (United States)

    Cornelius, Ryan J.; Wang, Bangchen; Wang-France, Jun

    2016-01-01

    A low-Na+, high-K+ diet (LNaHK) is considered a healthier alternative to the “Western” high-Na+ diet. Because the mechanism for K+ secretion involves Na+ reabsorptive exchange for secreted K+ in the distal nephron, it is not understood how K+ is eliminated with such low Na+ intake. Animals on a LNaHK diet produce an alkaline load, high urinary flows, and markedly elevated plasma ANG II and aldosterone levels to maintain their K+ balance. Recent studies have revealed a potential mechanism involving the actions of alkalosis, urinary flow, elevated ANG II, and aldosterone on two types of K+ channels, renal outer medullary K+ and large-conductance K+ channels, located in principal and intercalated cells. Here, we review these recent advances. PMID:26739887

  18. Elemental maps in human allantochorial placental vessels cells: 1. High K{sup +} and acetylcholine effects

    Energy Technology Data Exchange (ETDEWEB)

    Michelet-Habchi, C. E-mail: michelet@cenbg.in2p3.fr; Barberet, Ph.; Dutta, R.K.; Guiet-Bara, A.; Bara, M.; Moretto, Ph

    2003-09-01

    Regulation of vascular tone in the fetal extracorporeal circulation most likely depends on circulating hormones, local paracrine mechanisms and changes in membrane potential of vascular smooth muscle cells (VSMCs) and of vascular endothelial cells (VECs). The membrane potential is a function of the physiological activities of ionic channels (particularly, K{sup +} and Ca{sup 2+} channels in these cells). These channels regulate the ionic distribution into these cells. Micro-particle induced X-ray emission (PIXE) analysis was applied to determine the ionic composition of VSMC and of VEC in the placental human allantochorial vessels in a physiological survival medium (Hanks' solution) modified by the addition of acetylcholine (ACh: which opens the calcium-sensitive K{sup +} channels, K{sub Ca}) and of high concentration of K{sup +} (which blocks the voltage-sensitive K{sup +} channels, K{sub df}). In VSMC (media layer), the addition of ACh induced no modification of the Na, K, Cl, P, S, Mg and Ca concentrations and high K{sup +} medium increased significantly the Cl and K concentrations, the other ion concentrations remaining constant. In endothelium (VEC), ACh addition implicated a significant increase of Na and K concentration, and high K{sup +} medium, a significant increase in Cl and K concentration. These results indicated the importance of K{sub df}, K{sub Ca} and K{sub ATP} channels in the regulation of K{sup +} intracellular distribution in VSMC and VEC and the possible intervention of a Na-K-2Cl cotransport and corroborated the previous electrophysiological data.

  19. SEMICONDUCTOR DEVICES: Structural and electrical characteristics of lanthanum oxide gate dielectric film on GaAs pHEMT technology

    Science.gov (United States)

    Chia-Song, Wu; Hsing-Chung, Liu

    2009-11-01

    This paper investigates the feasibility of using a lanthanum oxide thin film (La2O3) with a high dielectric constant as a gate dielectric on GaAs pHEMTs to reduce gate leakage current and improve the gate to drain breakdown voltage relative to the conventional GaAs pHEMT. An E/D mode pHEMT in a single chip was realized by selecting the appropriate La2O3 thickness. The thin La2O3 film was characterized: its chemical composition and crystalline structure were determined by X-ray photoelectron spectroscopy and X-ray diffraction, respectively. La2O3 exhibited good thermal stability after post-deposition annealing at 200, 400 and 600 °C because of its high binding-energy (835.6 eV). Experimental results clearly demonstrated that the La2O3 thin film was thermally stable. The DC and RF characteristics of Pt/La2O3/Ti/Au gate and conventional Pt/Ti/Au gate pHEMTs were examined. The measurements indicated that the transistor with the Pt/La2O3/Ti/Au gate had a higher breakdown voltage and lower gate leakage current. Accordingly, the La2O3 thin film is a potential high-k material for use as a gate dielectric to improve electrical performance and the thermal effect in high-power applications.

  20. Demonstration of hetero-gate-dielectric tunneling field-effect transistors (HG TFETs).

    Science.gov (United States)

    Choi, Woo Young; Lee, Hyun Kook

    2016-01-01

    The steady scaling-down of semiconductor device for improving performance has been the most important issue among researchers. Recently, as low-power consumption becomes one of the most important requirements, there have been many researches about novel devices for low-power consumption. Though scaling supply voltage is the most effective way for low-power consumption, performance degradation is occurred for metal-oxide-semiconductor field-effect transistors (MOSFETs) when supply voltage is reduced because subthreshold swing (SS) of MOSFETs cannot be lower than 60 mV/dec. Thus, in this thesis, hetero-gate-dielectric tunneling field-effect transistors (HG TFETs) are investigated as one of the most promising alternatives to MOSFETs. By replacing source-side gate insulator with a high- k material, HG TFETs show higher on-current, suppressed ambipolar current and lower SS than conventional TFETs. Device design optimization through simulation was performed and fabrication based on simulation demonstrated that performance of HG TFETs were better than that of conventional TFETs. Especially, enlargement of gate insulator thickness while etching gate insulator at the source side was improved by introducing HF vapor etch process. In addition, the proposed HG TFETs showed higher performance than our previous results by changing structure of sidewall spacer by high- k etching process.

  1. Progress of MCFC stack technology at Toshiba

    Energy Technology Data Exchange (ETDEWEB)

    Hori, M.; Hayashi, T.; Shimizu, Y. [Toshiba Corp., Tokyo (Japan)

    1996-12-31

    Toshiba is working on the development of MCFC stack technology; improvement of cell characteristics, and establishment of separator technology. For the cell technology, Toshiba has concentrated on both the restraints of NiO cathode dissolution and electrolyte loss from cells, which are the critical issues to extend cell life in MCFC, and great progress has been made. On the other hand, recognizing that the separator is one of key elements in accomplishing reliable and cost-competitive MCFC stacks, Toshiba has been accelerating the technology establishment and verification of an advanced type separator. A sub-scale stack with such a separator was provided for an electric generating test, and has been operated for more than 10,000 hours. This paper presents several topics obtained through the technical activities in the MCFC field at Toshiba.

  2. Development of an Integrated Polymer Microfluidic Stack

    International Nuclear Information System (INIS)

    Datta, Proyag; Hammacher, Jens; Pease, Mark; Gurung, Sitanshu; Goettert, Jost

    2006-01-01

    Microfluidic is a field of considerable interest. While significant research has been carried out to develop microfluidic components, very little has been done to integrate the components into a complete working system. We present a flexible modular system platform that addresses the requirements of a complete microfluidic system. A microfluidic stack system is demonstrated with the layers of the stack being modular for specific functions. The stack and accompanying infrastructure provides an attractive platform for users to transition their design concepts into a working microfluidic system quickly with very little effort. The concept is demonstrated by using the system to carry out a chemilumiscence experiment. Details regarding the fabrication, assembly and experimental methods are presented

  3. Detailed Electrochemical Characterisation of Large SOFC Stacks

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, R.

    2012-01-01

    application of advanced methods for detailed electrochemical characterisation during operation. An operating stack is subject to steep compositional gradients in the gaseous reactant streams, and significant temperature gradients across each cell and across the stack, which makes it a complex system...... Fuel Cell A/S was characterised in detail using electrochemical impedance spectroscopy. An investigation of the optimal geometrical placement of the current probes and voltage probes was carried out in order to minimise measurement errors caused by stray impedances. Unwanted stray impedances...... are particularly problematic at high frequencies. Stray impedances may be caused by mutual inductance and stray capacitance in the geometrical set-up and do not describe the fuel cell. Three different stack geometries were investigated by electrochemical impedance spectroscopy. Impedance measurements were carried...

  4. High power, repetitive stacked Blumlein pulse generators

    Energy Technology Data Exchange (ETDEWEB)

    Davanloo, F; Borovina, D L; Korioth, J L; Krause, R K; Collins, C B [Univ. of Texas at Dallas, Richardson, TX (United States). Center for Quantum Electronics; Agee, F J [US Air Force Phillips Lab., Kirtland AFB, NM (United States); Kingsley, L E [US Army CECOM, Ft. Monmouth, NJ (United States)

    1997-12-31

    The repetitive stacked Blumlein pulse power generators developed at the University of Texas at Dallas consist of several triaxial Blumleins stacked in series at one end. The lines are charged in parallel and synchronously commuted with a single switch at the other end. In this way, relatively low charging voltages are multiplied to give a high discharge voltage across an arbitrary load. Extensive characterization of these novel pulsers have been performed over the past few years. Results indicate that they are capable of producing high power waveforms with rise times and repetition rates in the range of 0.5-50 ns and 1-300 Hz, respectively, using a conventional thyratron, spark gap, or photoconductive switch. The progress in the development and use of stacked Blumlein pulse generators is reviewed. The technology and the characteristics of these novel pulsers driving flash x-ray diodes are discussed. (author). 4 figs., 5 refs.

  5. Calculation of tritium release from reactor's stack

    International Nuclear Information System (INIS)

    Akhadi, M.

    1996-01-01

    Method for calculation of tritium release from nuclear to environment has been discussed. Part of gas effluent contain tritium in form of HTO vapor released from reactor's stack was sampled using silica-gel. The silica-gel was put in the water to withdraw HTO vapor absorbed by silica-gel. Tritium concentration in the water was measured by liquid scintillation counter of Aloka LSC-703. Tritium concentration in the gas effluent and total release of tritium from reactor's stack during certain interval time were calculated using simple mathematic formula. This method has examined for calculation of tritium release from JRR-3M's stack of JAERI, Japan. From the calculation it was obtained the value of tritium release as much as 4.63 x 10 11 Bq during one month. (author)

  6. Photon-gated spin transistor

    OpenAIRE

    Li, Fan; Song, Cheng; Cui, Bin; Peng, Jingjing; Gu, Youdi; Wang, Guangyue; Pan, Feng

    2017-01-01

    Spin-polarized field-effect transistor (spin-FET), where a dielectric layer is generally employed for the electrical gating as the traditional FET, stands out as a seminal spintronic device under the miniaturization trend of electronics. It would be fundamentally transformative if optical gating was used for spin-FET. We report a new type of spin-polarized field-effect transistor (spin-FET) with optical gating, which is fabricated by partial exposure of the (La,Sr)MnO3 channel to light-emitti...

  7. Electrical properties of nano-resistors made from the Zr-doped HfO2 high-k dielectric film

    Science.gov (United States)

    Zhang, Shumao; Kuo, Yue

    2018-03-01

    Electrical properties of nano-sized resistors made from the breakdown of the metal-oxide-semiconductor capacitor composed of the amorphous high-k gate dielectric have been investigated under different stress voltages and temperatures. The effective resistance of nano-resistors in the device was estimated from the I-V curve in the high voltage range. It decreased with the increase of the number of resistors. The resistance showed complicated temperature dependence, i.e. it neither behaves like a conductor nor a semiconductor. In the low voltage operation range, the charge transfer was controlled by the Schottky barrier at the nano-resistor/Si interface. The barrier height decreased with the increase of stress voltage, which was probably caused by the change of the nano-resistor composition. Separately, it was observed that the barrier height was dependent on the temperature, which was probably due to the dynamic nano-resistor formation process and the inhomogeneous barrier height distribution. The unique electrical characteristics of this new type of nano-resistors are important for many electronic and optoelectronic applications.

  8. Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

    Science.gov (United States)

    Hu, Yaoqiao; Jiang, Huaxing; Lau, Kei May; Li, Qiang

    2018-04-01

    For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec-1, and a field-effect electron mobility of 12.1 cm2 V-1 s-1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm-1 at V DS = 5 V. The gate leakage current is below 10-2 A cm-2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm-1 is obtained. Gate hysteresis and frequency-dependent capacitance-voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ˜3 × 1012 cm-2 eV-1.

  9. Nonlinearly stacked low noise turbofan stator

    Science.gov (United States)

    Schuster, William B. (Inventor); Nolcheff, Nick A. (Inventor); Gunaraj, John A. (Inventor); Kontos, Karen B. (Inventor); Weir, Donald S. (Inventor)

    2009-01-01

    A nonlinearly stacked low noise turbofan stator vane having a characteristic curve that is characterized by a nonlinear sweep and a nonlinear lean is provided. The stator is in an axial fan or compressor turbomachinery stage that is comprised of a collection of vanes whose highly three-dimensional shape is selected to reduce rotor-stator and rotor-strut interaction noise while maintaining the aerodynamic and mechanical performance of the vane. The nonlinearly stacked low noise turbofan stator vane reduces noise associated with the fan stage of turbomachinery to improve environmental compatibility.

  10. Stack Monitoring System At PUSPATI TRIGA Reactor

    International Nuclear Information System (INIS)

    Zamrul Faizad Omar; Mohd Sabri Minhat; Zareen Khan Abdul Jalil Khan; Ridzuan Abdul Mutalib; Khairulezwan Abdul Manan; Nurfarhana Ayuni Joha; Izhar Abu Hussin

    2014-01-01

    This paper describes the current Stack Monitoring System at PUSPATI TRIGA Reactor (RTP) building. A stack monitoring system is a continuous air monitor placed at the reactor top for monitoring the presence of radioactive gaseous in the effluent air from the RTP building. The system consists of four detectors that provide the reading for background, particulate, Iodine and Noble gas. There is a plan to replace the current system due to frequent fault of the system, thus thorough understanding of the current system is required. Overview of the whole system will be explained in this paper. Some current results would be displayed and moving forward brief plan would be mentioned. (author)

  11. Nitride passivation of the interface between high-k dielectrics and SiGe

    Energy Technology Data Exchange (ETDEWEB)

    Sardashti, Kasra [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Materials Science and Engineering Program, University of California, San Diego, La Jolla, California 92093-0411 (United States); Hu, Kai-Ting [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States); Department of Mechanical and Aerospace Engineering, University of California, San Diego, La Jolla, California 92093-0411 (United States); Tang, Kechao; McIntyre, Paul [Department of Materials Science and Engineering, Stanford University, Stanford, California 94305 (United States); Madisetti, Shailesh; Oktyabrsky, Serge [Colleges of Nanoscale Science and Engineering, SUNY Polytechnic Institute, Albany, New York 12222 (United States); Siddiqui, Shariq; Sahu, Bhagawan [TD Research, GLOBALFOUNDRIES US, Inc., Albany, New York 12203 (United States); Yoshida, Naomi; Kachian, Jessica; Dong, Lin [Applied Materials, Inc., Santa Clara, California 95054 (United States); Fruhberger, Bernd [California Institute for Telecommunications and Information Technology, University of California San Diego, La Jolla, California 92093-0436 (United States); Kummel, Andrew C., E-mail: akummel@ucsd.edu [Department of Chemistry and Biochemistry, University of California, San Diego, La Jolla, California 92093-0358 (United States)

    2016-01-04

    In-situ direct ammonia (NH{sub 3}) plasma nitridation has been used to passivate the Al{sub 2}O{sub 3}/SiGe interfaces with Si nitride and oxynitride. X-ray photoelectron spectroscopy of the buried Al{sub 2}O{sub 3}/SiGe interface shows that NH{sub 3} plasma pre-treatment should be performed at high temperatures (300 °C) to fully prevent Ge nitride and oxynitride formation at the interface and Ge out-diffusion into the oxide. C-V and I-V spectroscopy results show a lower density of interface traps and smaller gate leakage for samples with plasma nitridation at 300 °C.

  12. Serializing off-the-shelf MOSFETs by Magnetically Coupling Their Gate Electrodes

    DEFF Research Database (Denmark)

    Dimopoulos, Emmanouil; Munk-Nielsen, Stig

    2013-01-01

    While the semiconductor industry struggles with the inherent trade-offs of solid-state devices, serialization of power switches, like the Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) or the Insulated Gate Bipolar Transistor (IGBT), has been proven to be an advantageous alternative...... to acquire a high-efficient, high-voltage, fast-switching device. More than twenty years of research, on the serialization of solid-state devices, have resulted into several different stacking concepts. Among the prevailing ones, the gate balancing core technique, which has demonstrated very good performance...... in strings of high-power IGBT modules. In this paper, the limitations of the gate balancing core technique, when employed to serialize low or medium power off-the-shelf switches, are identified via experimental results. A new design specification for the interwinding capacitance of the employed transformer...

  13. Reversible logic gates on Physarum Polycephalum

    International Nuclear Information System (INIS)

    Schumann, Andrew

    2015-01-01

    In this paper, we consider possibilities how to implement asynchronous sequential logic gates and quantum-style reversible logic gates on Physarum polycephalum motions. We show that in asynchronous sequential logic gates we can erase information because of uncertainty in the direction of plasmodium propagation. Therefore quantum-style reversible logic gates are more preferable for designing logic circuits on Physarum polycephalum

  14. Demonstration of a Quantum Nondemolition Sum Gate

    DEFF Research Database (Denmark)

    Yoshikawa, J.; Miwa, Y.; Huck, Alexander

    2008-01-01

    The sum gate is the canonical two-mode gate for universal quantum computation based on continuous quantum variables. It represents the natural analogue to a qubit C-NOT gate. In addition, the continuous-variable gate describes a quantum nondemolition (QND) interaction between the quadrature...

  15. A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

    International Nuclear Information System (INIS)

    Rahi Shiromani Balmukund; Asthana Pranav; Ghosh Bahniman

    2014-01-01

    We propose a heterostructure junctionless tunnel field effect transistor (HJL-TFET) using AlGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates (named gate, gate1) with two different work functions (gate = 4.2 eV, gate1 = 5.2 eV respectively). The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10 −6 A/μm, the off current remains as low as 9.1 × 10 −14 A/μm. So I ON /I OFF ratio of ≃ 10 8 is achieved. Point subthreshold swing has also been reduced to a value of ≃ 41 mV/decade for TiO 2 gate material. (semiconductor devices)

  16. Deep Gate Recurrent Neural Network

    Science.gov (United States)

    2016-11-22

    and Fred Cummins. Learning to forget: Continual prediction with lstm . Neural computation, 12(10):2451–2471, 2000. Alex Graves. Generating sequences...DSGU) and Simple Gated Unit (SGU), which are structures for learning long-term dependencies. Compared to traditional Long Short-Term Memory ( LSTM ) and...Gated Recurrent Unit (GRU), both structures require fewer parameters and less computation time in sequence classification tasks. Unlike GRU and LSTM

  17. Bill Gates vil redde Folkeskolen

    DEFF Research Database (Denmark)

    Fejerskov, Adam Moe

    2014-01-01

    Det amerikanske uddannelsessystem bliver for tiden udsat for hård kritik, ledt an af Microsoft stifteren Bill Gates. Gates har indtil videre brugt 3 mia. kroner på at skabe opbakning til tiltag som præstationslønning af lærere og strømlining af pensum på tværs af alle skoler i landet...

  18. Stacked spheres and lower bound theorem

    Indian Academy of Sciences (India)

    BASUDEB DATTA

    2011-11-20

    Nov 20, 2011 ... Preliminaries. Lower bound theorem. On going work. Definitions. An n-simplex is a convex hull of n + 1 affinely independent points. (called vertices) in some Euclidean space R. N . Stacked spheres and lower bound theorem. Basudeb Datta. Indian Institute of Science. 2 / 27 ...

  19. Contemporary sample stacking in analytical electrophoresis

    Czech Academy of Sciences Publication Activity Database

    Šlampová, Andrea; Malá, Zdeňka; Pantůčková, Pavla; Gebauer, Petr; Boček, Petr

    2013-01-01

    Roč. 34, č. 1 (2013), s. 3-18 ISSN 0173-0835 R&D Projects: GA ČR GAP206/10/1219 Institutional support: RVO:68081715 Keywords : biological samples * stacking * trace analysis * zone electrophoresis Subject RIV: CB - Analytical Chemistry, Separation Impact factor: 3.161, year: 2013

  20. SRS reactor stack plume marking tests

    International Nuclear Information System (INIS)

    Petry, S.F.

    1992-03-01

    Tests performed in 105-K in 1987 and 1988 demonstrated that the stack plume can successfully be made visible (i.e., marked) by introducing smoke into the stack breech. The ultimate objective of these tests is to provide a means during an emergency evacuation so that an evacuee can readily identify the stack plume and evacuate in the opposite direction, thus minimizing the potential of severe radiation exposure. The EPA has also requested DOE to arrange for more tests to settle a technical question involving the correct calculation of stack downwash. New test canisters were received in 1988 designed to produce more smoke per unit time; however, these canisters have not been evaluated, because normal ventilation conditions have not been reestablished in K Area. Meanwhile, both the authorization and procedure to conduct the tests have expired. The tests can be performed during normal reactor operation. It is recommended that appropriate authorization and procedure approval be obtained to resume testing after K Area restart

  1. Scaling the CERN OpenStack cloud

    Science.gov (United States)

    Bell, T.; Bompastor, B.; Bukowiec, S.; Castro Leon, J.; Denis, M. K.; van Eldik, J.; Fermin Lobo, M.; Fernandez Alvarez, L.; Fernandez Rodriguez, D.; Marino, A.; Moreira, B.; Noel, B.; Oulevey, T.; Takase, W.; Wiebalck, A.; Zilli, S.

    2015-12-01

    CERN has been running a production OpenStack cloud since July 2013 to support physics computing and infrastructure services for the site. In the past year, CERN Cloud Infrastructure has seen a constant increase in nodes, virtual machines, users and projects. This paper will present what has been done in order to make the CERN cloud infrastructure scale out.

  2. Stacking non-BPS D-branes

    International Nuclear Information System (INIS)

    Alberghi, Gian Luigi; Caceres, Elena; Goldstein, Kevin; Lowe, David A. . lowe@het.brown.edu

    2001-08-01

    We present a candidate supergravity solution for a stacked configuration of stable non-BPS D-branes in Type II string theory compactified on T 4 /Z 2 . This gives a supergravity description of nonabelian tachyon condensation on the brane woldvolume. (author)

  3. Trace interpolation by slant-stack migration

    International Nuclear Information System (INIS)

    Novotny, M.

    1990-01-01

    The slant-stack migration formula based on the radon transform is studied with respect to the depth steep Δz of wavefield extrapolation. It can be viewed as a generalized trace-interpolation procedure including wave extrapolation with an arbitrary step Δz. For Δz > 0 the formula yields the familiar plane-wave decomposition, while for Δz > 0 it provides a robust tool for migration transformation of spatially under sampled wavefields. Using the stationary phase method, it is shown that the slant-stack migration formula degenerates into the Rayleigh-Sommerfeld integral in the far-field approximation. Consequently, even a narrow slant-stack gather applied before the diffraction stack can significantly improve the representation of noisy data in the wavefield extrapolation process. The theory is applied to synthetic and field data to perform trace interpolation and dip reject filtration. The data examples presented prove that the radon interpolator works well in the dip range, including waves with mutual stepouts smaller than half the dominant period

  4. Contemporary sample stacking in analytical electrophoresis

    Czech Academy of Sciences Publication Activity Database

    Malá, Zdeňka; Šlampová, Andrea; Křivánková, Ludmila; Gebauer, Petr; Boček, Petr

    2015-01-01

    Roč. 36, č. 1 (2015), s. 15-35 ISSN 0173-0835 R&D Projects: GA ČR(CZ) GA13-05762S Institutional support: RVO:68081715 Keywords : biological samples * stacking * trace analysis * zone electrophoresis Subject RIV: CB - Analytical Chemistry, Separation Impact factor: 2.482, year: 2015

  5. 40 CFR 61.53 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.53 Section 61.53 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... sampling. (a) Mercury ore processing facility. (1) Unless a waiver of emission testing is obtained under...

  6. 40 CFR 61.33 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.33 Section 61.33 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... sampling. (a) Unless a waiver of emission testing is obtained under § 61.13, each owner or operator...

  7. OpenStack cloud computing cookbook

    CERN Document Server

    Jackson, Kevin

    2013-01-01

    A Cookbook full of practical and applicable recipes that will enable you to use the full capabilities of OpenStack like never before.This book is aimed at system administrators and technical architects moving from a virtualized environment to cloud environments with familiarity of cloud computing platforms. Knowledge of virtualization and managing linux environments is expected.

  8. Toward advising SME's on stacked funding

    NARCIS (Netherlands)

    Rauwerda, Kirsten; van Teeffelen, Lex; de Graaf, Frank Jan

    2017-01-01

    This paper addresses new funding issues faced by SMEs. Over a period of nine months, the authors conducted a preliminary study into the problems surrounding stacked funding faced by SMEs and their financial advisers. The study includes a short literature review, the outcomes of three round table

  9. Photoswitchable Intramolecular H-Stacking of Perylenebisimide

    NARCIS (Netherlands)

    Wang, Jiaobing; Kulago, Artem; Browne, Wesley R.; Feringa, Ben L.

    2010-01-01

    Dynamic control over the formation of H- or J-type aggregates of chromophores is of fundamental importance for developing responsive organic optoelectronic materials. In this study, the first example of photoswitching between a nonstacked and an intramolecularly H-stacked arrangement of

  10. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  11. OpenStack Object Storage (Swift) essentials

    CERN Document Server

    Kapadia, Amar; Varma, Sreedhar

    2015-01-01

    If you are an IT administrator and you want to enter the world of cloud storage using OpenStack Swift, then this book is ideal for you. Basic knowledge of Linux and server technology is beneficial to get the most out of the book.

  12. Latest design of gate valves

    Energy Technology Data Exchange (ETDEWEB)

    Kurzhofer, U.; Stolte, J.; Weyand, M.

    1996-12-01

    Babcock Sempell, one of the most important valve manufacturers in Europe, has delivered valves for the nuclear power industry since the beginning of the peaceful application of nuclear power in the 1960s. The latest innovation by Babcock Sempell is a gate valve that meets all recent technical requirements of the nuclear power technology. At the moment in the United States, Germany, Sweden, and many other countries, motor-operated gate and globe valves are judged very critically. Besides the absolute control of the so-called {open_quotes}trip failure,{close_quotes} the integrity of all valve parts submitted to operational forces must be maintained. In case of failure of the limit and torque switches, all valve designs have been tested with respect to the quality of guidance of the gate. The guidances (i.e., guides) shall avoid a tilting of the gate during the closing procedure. The gate valve newly designed by Babcock Sempell fulfills all these characteristic criteria. In addition, the valve has cobalt-free seat hardfacing, the suitability of which has been proven by friction tests as well as full-scale blowdown tests at the GAP of Siemens in Karlstein, West Germany. Babcock Sempell was to deliver more than 30 gate valves of this type for 5 Swedish nuclear power stations by autumn 1995. In the presentation, the author will report on the testing performed, qualifications, and sizing criteria which led to the new technical design.

  13. CMOS gate array characterization procedures

    Science.gov (United States)

    Spratt, James P.

    1993-09-01

    Present procedures are inadequate for characterizing the radiation hardness of gate array product lines prior to personalization because the selection of circuits to be used, from among all those available in the manufacturer's circuit library, is usually uncontrolled. (Some circuits are fundamentally more radiation resistant than others.) In such cases, differences in hardness can result between different designs of the same logic function. Hardness also varies because many gate arrays feature large custom-designed megacells (e.g., microprocessors and random access memories-MicroP's and RAM's). As a result, different product lines cannot be compared equally. A characterization strategy is needed, along with standardized test vehicle(s), methodology, and conditions, so that users can make informed judgments on which gate arrays are best suited for their needs. The program described developed preferred procedures for the radiation characterization of gate arrays, including a gate array evaluation test vehicle, featuring a canary circuit, designed to define the speed versus hardness envelope of the gate array. A multiplier was chosen for this role, and a baseline multiplier architecture is suggested that could be incorporated into an existing standard evaluation circuit chip.

  14. A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics

    Directory of Open Access Journals (Sweden)

    D.Nirmal

    2014-07-01

    Full Text Available In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on low power and high gain in the device, the materials of the device also been taken into consideration. In the present technology, Computationally intensive devices with low power dissipation and high gain are becoming a critical application domain. Several factors have contributed to this paradigm shift. The primary driving factor being the increase in scale of integration, the chip has to accommodate smaller and faster transistors than their predecessors. During the last decade semiconductor technology has been led by conventional scaling. Scaling, has been aimed towards higher speed, lower power and higher density of the semiconductor devices. However, as scaling approached its physical limits, it has become more difficult and challenging for fabrication industry. Therefore, tremendous research has been carried out to investigate the alternatives, and this led to the introduction of new Nano materials and concepts to overcome the difficulties in the device fabrications. In order to reduce the leakage current and parasitic capacitance in devices, gate oxide high-k dielectric materials are explored. Among the different high-k materials available the nano size Zirconium dioxide material is suggested as an alternate gate oxide material for devices due to its thermal stability and small grain size of material. To meet the requirements of ITRS roadmap 2012, the Multi gate devices are considered to be one of the most promising technologies for the future microelectronics industry due to its excellent immunity to short channel effects and high value of On current. The double gate or multi gate devices provide a better scalability option due to its excellent immunity to short-channel effects. Here the different high-k materials are replaced in different

  15. Psychometrics and life history strategy: the structure and validity of the High K Strategy Scale.

    Science.gov (United States)

    Copping, Lee T; Campbell, Anne; Muncer, Steven

    2014-03-22

    In this paper, we critically review the conceptualization and implementation of psychological measures of life history strategy associated with Differential K theory. The High K Strategy Scale (HKSS: Giosan, 2006) was distributed to a large British sample (n = 809) with the aim of assessing its factor structure and construct validity in relation to theoretically relevant life history variables: age of puberty, age of first sexual encounter, and number of sexual partners. Exploratory and confirmatory factor analyses indicated that the HKSS in its current form did not show an adequate statistical fit to the data. Modifications to improve fit indicated four correlated factors (personal capital, environmental stability, environmental security, and social capital). Later puberty in women was positively associated with measures of the environment and personal capital. Among men, contrary to Differential K predictions but in line with female mate preferences, earlier sexual debut and more sexual partners were positively associated with more favorable environments and higher personal and social capital. We raise concerns about the use of psychometric indicators of lifestyle and personality as proxies for life history strategy when they have not been validated against objective measures derived from contemporary life history theory and when their status as causes, mediators, or correlates has not been investigated.

  16. High-k Scattering Receiver Mixer Performance for NSTX-U

    Science.gov (United States)

    Barchfeld, Robert; Riemenschneider, Paul; Domier, Calvin; Luhmann, Neville; Ren, Yang; Kaita, Robert

    2016-10-01

    The High-k Scattering system detects primarily electron-scale turbulence k θ spectra for studying electron thermal transport in NSTX-U. A 100 mW, 693 GHz probe beam passes through plasma, and scattered power is detected by a 4-pixel quasi optical, mixer array. Remotely controlled receiving optics allows the scattering volume to be located from core to edge with a k θ span of 7 to 40 cm-1. The receiver array features 4 RF diagonal input horns, where the electric field polarization is aligned along the diagonal of a square cross section horn, at 30 mm channel spacing. The local oscillator is provided by a 14.4 GHz source followed by a x48 multiplier chain, giving an intermediate frequency of 1 GHz. The receiver optics receive 4 discreet scattering angles simultaneously, and then focus the signals as 4 parallel signals to their respective horns. A combination of a steerable probe beam, and translating receiver, allows for upward or downward scattering which together can provide information about 2D turbulence wavenumber spectrum. IF signals are digitized and stored for later computer analysis. The performance of the receiver mixers is discussed, along with optical design features to enhance the tuning and performance of the mixers. Work supported in part by U.S. DOE Grant DE-FG02-99ER54518 and DE-AC02-09CH1146.

  17. Full Polymer Dielectric Elastomeric Actuators (DEA Functionalised with Carbon Nanotubes and High-K Ceramics

    Directory of Open Access Journals (Sweden)

    Tilo Köckritz

    2016-09-01

    Full Text Available Dielectric elastomer actuators (DEA are special devices which have a simple working and construction principle and outstanding actuation properties. The DEAs consist of a combination of different materials for the dielectric and electrode layers. The combination of these layers causes incompatibilities in their interconnections. Dramatic differences in the mechanical properties and bad adhesion of the layers are the principal causes for the reduction of the actuation displacement and strong reduction of lifetime. Common DEAs achieve actuation displacements of 2% and a durability of some million cycles. The following investigations represent a new approach to solving the problems of common systems. The investigated DEA consists of only one basic raw polymer, which was modified according to the required demands of each layer. The basic raw polymer was modified with single-walled carbon nanotubes or high-k ceramics, for example, lead magnesium niobate-lead titanate. The development of the full polymer DEA comprised the development of materials and technologies to realise a reproducible layer composition. It was proven that the full polymer actuator worked according to the theoretical rules. The investigated system achieved actuation displacements above 20% regarding thickness, outstanding interconnections at each layer without any failures, and durability above 3 million cycles without any indication of an impending malfunction.

  18. Novel technique of source and drain engineering for dual-material double-gate (DMDG) SOI MOSFETS

    Science.gov (United States)

    Yadav, Himanshu; Malviya, Abhishek Kumar; Chauhan, R. K.

    2018-04-01

    The dual-metal dual-gate (DMDG) SOI has been used with Dual Sided Source and Drain Engineered 50nm SOI MOSFET with various high-k gate oxide. It has been scrutinized in this work to enhance its electrical performance. The proposed structure is designed by creating Dual Sided Source and Drain Modification and its characteristics are evaluated on ATLAS device simulator. The consequence of this dual sided assorted doping on source and drain side of the DMDG transistor has better leakage current immunity and heightened ION current with higher ION to IOFF Ratio. Which thereby vesting the proposed device appropriate for low power digital applications.

  19. Project W-420 Stack Monitoring system upgrades conceptual design report

    International Nuclear Information System (INIS)

    TUCK, J.A.

    1998-01-01

    This document describes the scope, justification, conceptual design, and performance of Project W-420 stack monitoring system upgrades on six NESHAP-designated, Hanford Tank Farms ventilation exhaust stacks

  20. Project W-420 Stack Monitoring system upgrades conceptual design report

    Energy Technology Data Exchange (ETDEWEB)

    TUCK, J.A.

    1998-11-06

    This document describes the scope, justification, conceptual design, and performance of Project W-420 stack monitoring system upgrades on six NESHAP-designated, Hanford Tank Farms ventilation exhaust stacks.

  1. Surface and interfacial chemistry of high-k dielectric and interconnect materials on silicon

    Science.gov (United States)

    Kirsch, Paul Daniel

    Surfaces and interfaces play a critical role in the manufacture and function of silicon based integrated circuits. It is therefore reasonable to study the chemistries at these surfaces and interfaces to improve existing processes and to develop new ones. Model barium strontium titanate high-k dielectric systems have been deposited on ultrathin silicon oxynitride in ultrahigh vacuum. The resulting nanostructures are characterized with secondary ion mass spectroscopy (SIMS) and X-ray photoelectron spectroscopy (XPS). An interfacial reaction between Ba and Sr atoms and SiOxNy was found to create silicates, BaSixOy or SrSi xOy. Inclusion of N in the interfacial oxide decreased silicate formation in both Ba and Sr systems. Furthermore, inclusion of N in the interfacial oxide decreased the penetration of Ba and Sr containing species, such as silicides and silicates. Sputter deposited HfO2 was studied on nitrided and unnitrided Si(100) surfaces. XPS and SIMS were used to verify the presence of interfacial HfSixOy and estimate its relative amount on both nitrided and unnitrided samples. More HfSixOy formed without the SiNx interfacial layer. These interfacial chemistry results are then used to explain the electrical measurements obtained from metal oxide semiconductor (MOS) capacitors. MOS capacitors with interfacial SiNx exhibit reduced leakage current and increased capacitance. Lastly, surface science techniques were used to develop a processing technique for reducing thin films of copper (II) and copper (I) oxide to copper. Deuterium atoms (D*) and methyl radicals (CH3*) were shown to reduce Cu 2+ and/or Cu1+ to Cu0 within 30 min at a surface temperature of 400 K under a flux of 1 x 1015 atoms/cm2s. Temperature programmed desorption experiments suggest that oxygen leaves the surface as D2O and CO2 for the D* and CH3* treated surfaces, respectively.

  2. Modulation of the effective work function of a TiN metal gate for NMOS requisition with Al incorporation

    International Nuclear Information System (INIS)

    Han Kai; Ma Xueli; Yang Hong; Wang Wenwu

    2013-01-01

    The effect of Al incorporation on the effective work function (EWF) of TiN metal gate was systematically investigated. Metal—oxide—semiconductor (MOS) capacitors with W/TiN/Al/TiN gate stacks were used to fulfill this purpose. Different thickness ratios of Al to TiN and different post metal annealing (PMA) conditions were employed. Significant shift of work function towards to Si conduction band was observed, which was suitable for NMOS and the magnitude of shift depends on the processing conditions. (semiconductor technology)

  3. Multistage Force Amplification of Piezoelectric Stacks

    Science.gov (United States)

    Xu, Tian-Bing (Inventor); Siochi, Emilie J. (Inventor); Zuo, Lei (Inventor); Jiang, Xiaoning (Inventor); Kang, Jin Ho (Inventor)

    2015-01-01

    Embodiments of the disclosure include an apparatus and methods for using a piezoelectric device, that includes an outer flextensional casing, a first cell and a last cell serially coupled to each other and coupled to the outer flextensional casing such that each cell having a flextensional cell structure and each cell receives an input force and provides an output force that is amplified based on the input force. The apparatus further includes a piezoelectric stack coupled to each cell such that the piezoelectric stack of each cell provides piezoelectric energy based on the output force for each cell. Further, the last cell receives an input force that is the output force from the first cell and the last cell provides an output apparatus force In addition, the piezoelectric energy harvested is based on the output apparatus force. Moreover, the apparatus provides displacement based on the output apparatus force.

  4. Development of on-site PAFC stacks

    Energy Technology Data Exchange (ETDEWEB)

    Hotta, K.; Matsumoto, Y. [Kansai Electric Power Co., Amagasaki (Japan); Horiuchi, H.; Ohtani, T. [Mitsubishi Electric Corp., Kobe (Japan)

    1996-12-31

    PAFC (Phosphoric Acid Fuel Cell) has been researched for commercial use and demonstration plants have been installed in various sites. However, PAFC don`t have a enough stability yet, so more research and development must be required in the future. Especially, cell stack needs a proper state of three phases (liquid, gas and solid) interface. It is very difficult technology to keep this condition for a long time. In the small size cell with the electrode area of 100 cm{sup 2}, gas flow and temperature distributions show uniformity. But in the large size cell with the electrode area of 4000 cm{sup 2}, the temperature distributions show non-uniformity. These distributions would cause to be shorten the cell life. Because these distributions make hot-spot and gas poverty in limited parts. So we inserted thermocouples in short-stack for measuring three-dimensional temperature distributions and observed effects of current density and gas utilization on temperature.

  5. System for inspection of stacked cargo containers

    Science.gov (United States)

    Derenzo, Stephen [Pinole, CA

    2011-08-16

    The present invention relates to a system for inspection of stacked cargo containers. One embodiment of the invention generally comprises a plurality of stacked cargo containers arranged in rows or tiers, each container having a top, a bottom a first side, a second side, a front end, and a back end; a plurality of spacers arranged in rows or tiers; one or more mobile inspection devices for inspecting the cargo containers, wherein the one or more inspection devices are removeably disposed within the spacers, the inspection means configured to move through the spacers to detect radiation within the containers. The invented system can also be configured to inspect the cargo containers for a variety of other potentially hazardous materials including but not limited to explosive and chemical threats.

  6. Industrial stacks design; Diseno de chimeneas industriales

    Energy Technology Data Exchange (ETDEWEB)

    Cacheux, Luis [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1987-12-31

    The Instituto de Investigaciones Electricas (IIE) though its Civil Works Department, develops, under contract with CFE`s Gerencia de Proyectos Termoelectricos (Management of Fossil Power Plant Projects), a series of methods for the design of stacks, which pretends to solve the a present day problem: the stack design of the fossil power plants that will go into operation during the next coming years in the country. [Espanol] El Instituto de Investigaciones Electricas (IIE), a traves del Departamento de Ingenieria Civil, desarrolla, bajo contrato con la Gerencia de Proyectos Termoelectricos, de la Comision Federal de Electricidad (CFE), un conjunto de metodos para el diseno de chimeneas, con el que se pretende resolver un problema inmediato: el diseno de las chimeneas de las centrales termoelectricas que entraran en operacion durante los proximos anos, en el pais.

  7. Absorption spectra of AA-stacked graphite

    International Nuclear Information System (INIS)

    Chiu, C W; Lee, S H; Chen, S C; Lin, M F; Shyu, F L

    2010-01-01

    AA-stacked graphite shows strong anisotropy in geometric structures and velocity matrix elements. However, the absorption spectra are isotropic for the polarization vector on the graphene plane. The spectra exhibit one prominent plateau at middle energy and one shoulder structure at lower energy. These structures directly reflect the unique geometric and band structures and provide sufficient information for experimental fitting of the intralayer and interlayer atomic interactions. On the other hand, monolayer graphene shows a sharp absorption peak but no shoulder structure; AA-stacked bilayer graphene has two absorption peaks at middle energy and abruptly vanishes at lower energy. Furthermore, the isotropic features are expected to exist in other graphene-related systems. The calculated results and the predicted atomic interactions could be verified by optical measurements.

  8. Industrial stacks design; Diseno de chimeneas industriales

    Energy Technology Data Exchange (ETDEWEB)

    Cacheux, Luis [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1986-12-31

    The Instituto de Investigaciones Electricas (IIE) though its Civil Works Department, develops, under contract with CFE`s Gerencia de Proyectos Termoelectricos (Management of Fossil Power Plant Projects), a series of methods for the design of stacks, which pretends to solve the a present day problem: the stack design of the fossil power plants that will go into operation during the next coming years in the country. [Espanol] El Instituto de Investigaciones Electricas (IIE), a traves del Departamento de Ingenieria Civil, desarrolla, bajo contrato con la Gerencia de Proyectos Termoelectricos, de la Comision Federal de Electricidad (CFE), un conjunto de metodos para el diseno de chimeneas, con el que se pretende resolver un problema inmediato: el diseno de las chimeneas de las centrales termoelectricas que entraran en operacion durante los proximos anos, en el pais.

  9. 400 W High Temperature PEM Fuel Cell Stack Test

    DEFF Research Database (Denmark)

    Andreasen, Søren Juhl; Kær, Søren Knudsen

    2006-01-01

    This work demonstrates the operation of a 30 cell high temperature PEM (HTPEM) fuel cell stack. This prototype stack has been developed at the Institute of Energy Technology, Aalborg University, as a proof-of-concept for a low pressure cathode air cooled HTPEM stack. The membranes used are Celtec...

  10. New opening hours of the gates

    CERN Multimedia

    GS Department

    2009-01-01

    Please note the new opening hours of the gates as well as the intersites tunnel from the 19 May 2009: GATE A 7h - 19h GATE B 24h/24 GATE C 7h - 9h\t17h - 19h GATE D 8h - 12h\t13h - 16h GATE E 7h - 9h\t17h - 19h Prévessin 24h/24 The intersites tunnel will be opened from 7h30 to 18h non stop. GS-SEM Group Infrastructure and General Services Department

  11. Role of stacking disorder in ice nucleation.

    Science.gov (United States)

    Lupi, Laura; Hudait, Arpa; Peters, Baron; Grünwald, Michael; Gotchy Mullen, Ryan; Nguyen, Andrew H; Molinero, Valeria

    2017-11-08

    The freezing of water affects the processes that determine Earth's climate. Therefore, accurate weather and climate forecasts hinge on good predictions of ice nucleation rates. Such rate predictions are based on extrapolations using classical nucleation theory, which assumes that the structure of nanometre-sized ice crystallites corresponds to that of hexagonal ice, the thermodynamically stable form of bulk ice. However, simulations with various water models find that ice nucleated and grown under atmospheric temperatures is at all sizes stacking-disordered, consisting of random sequences of cubic and hexagonal ice layers. This implies that stacking-disordered ice crystallites either are more stable than hexagonal ice crystallites or form because of non-equilibrium dynamical effects. Both scenarios challenge central tenets of classical nucleation theory. Here we use rare-event sampling and free energy calculations with the mW water model to show that the entropy of mixing cubic and hexagonal layers makes stacking-disordered ice the stable phase for crystallites up to a size of at least 100,000 molecules. We find that stacking-disordered critical crystallites at 230 kelvin are about 14 kilojoules per mole of crystallite more stable than hexagonal crystallites, making their ice nucleation rates more than three orders of magnitude higher than predicted by classical nucleation theory. This effect on nucleation rates is temperature dependent, being the most pronounced at the warmest conditions, and should affect the modelling of cloud formation and ice particle numbers, which are very sensitive to the temperature dependence of ice nucleation rates. We conclude that classical nucleation theory needs to be corrected to include the dependence of the crystallization driving force on the size of the ice crystallite when interpreting and extrapolating ice nucleation rates from experimental laboratory conditions to the temperatures that occur in clouds.

  12. A Late Pleistocene sea level stack

    OpenAIRE

    Spratt Rachel M; Lisiecki Lorraine E

    2016-01-01

    Late Pleistocene sea level has been reconstructed from ocean sediment core data using a wide variety of proxies and models. However, the accuracy of individual reconstructions is limited by measurement error, local variations in salinity and temperature, and assumptions particular to each technique. Here we present a sea level stack (average) which increases the signal-to-noise ratio of individual reconstructions. Specifically, we perform principal componen...

  13. CAM and stack air sampler design guide

    International Nuclear Information System (INIS)

    Phillips, T.D.

    1994-01-01

    About 128 air samplers and CAMs presently in service to detect and document potential radioactive release from 'H' and 'F' area tank farm ventilation stacks are scheduled for replacement and/or upgrade by Projects S-5764, S-2081, S-3603, and S-4516. The seven CAMs scheduled to be upgraded by Project S-4516 during 1995 are expected to provide valuable experience for the three remaining projects. The attached document provides design guidance for the standardized High Level Waste air sampling system

  14. Extended Life PZT Stack Test Fixture

    Science.gov (United States)

    Badescu, Mircea; Sherrit, S.; Bao, X.; Aldrich, J.; Bar-Cohen, Y.; Jones, C.

    2009-01-01

    Piezoelectric stacks are being sought to be used as actuators for precision positioning and deployment of mechanisms in future planetary missions. Beside the requirement for very high operation reliability, these actuators are required for operation at space environments that are considered harsh compared to normal terrestrial conditions.These environmental conditions include low and high temperatures and vacuum or high pressure. Additionally, the stacks are subjected to high stress and in some applications need to operate with a very long lifetime durability.Many of these requirements are beyond the current industry design margins for nominal terrestrial applications. In order to investigate some of the properties that will indicate the durability of such actuators and their limitations we have developed a new type of test fixture that can be easily integrated in various test chambers for simulating environmental conditions, can provide access for multiple measurements while being exposed to adjustable stress levels. We designed and built two test fixtures and these fixtures were made to be adjustable for testing stacks with different dimensions and can be easily used in small or large numbers. The properties that were measured using these fixtures include impedance, capacitance, dielectric loss factor, leakage current, displacement, breakdown voltage, and lifetime performance. The fixtures characteristics and the test capabilities are presented in this paper.

  15. Electrochemical Detection in Stacked Paper Networks.

    Science.gov (United States)

    Liu, Xiyuan; Lillehoj, Peter B

    2015-08-01

    Paper-based electrochemical biosensors are a promising technology that enables rapid, quantitative measurements on an inexpensive platform. However, the control of liquids in paper networks is generally limited to a single sample delivery step. Here, we propose a simple method to automate the loading and delivery of liquid samples to sensing electrodes on paper networks by stacking multiple layers of paper. Using these stacked paper devices (SPDs), we demonstrate a unique strategy to fully immerse planar electrodes by aqueous liquids via capillary flow. Amperometric measurements of xanthine oxidase revealed that electrochemical sensors on four-layer SPDs generated detection signals up to 75% higher compared with those on single-layer paper devices. Furthermore, measurements could be performed with minimal user involvement and completed within 30 min. Due to its simplicity, enhanced automation, and capability for quantitative measurements, stacked paper electrochemical biosensors can be useful tools for point-of-care testing in resource-limited settings. © 2015 Society for Laboratory Automation and Screening.

  16. Respiratory gating in cardiac PET

    DEFF Research Database (Denmark)

    Lassen, Martin Lyngby; Rasmussen, Thomas; Christensen, Thomas E

    2017-01-01

    BACKGROUND: Respiratory motion due to breathing during cardiac positron emission tomography (PET) results in spatial blurring and erroneous tracer quantification. Respiratory gating might represent a solution by dividing the PET coincidence dataset into smaller respiratory phase subsets. The aim...... of our study was to compare the resulting imaging quality by the use of a time-based respiratory gating system in two groups administered either adenosine or dipyridamole as the pharmacological stress agent. METHODS AND RESULTS: Forty-eight patients were randomized to adenosine or dipyridamole cardiac...... stress (82)RB-PET. Respiratory rates and depths were measured by a respiratory gating system in addition to registering actual respiratory rates. Patients undergoing adenosine stress showed a decrease in measured respiratory rate from initial to later scan phase measurements [12.4 (±5.7) vs 5.6 (±4...

  17. Robustness of holonomic quantum gates

    International Nuclear Information System (INIS)

    Solinas, P.; Zanardi, P.; Zanghi, N.

    2005-01-01

    Full text: If the driving field fluctuates during the quantum evolution this produces errors in the applied operator. The holonomic (and geometrical) quantum gates are believed to be robust against some kind of noise. Because of the geometrical dependence of the holonomic operators can be robust against this kind of noise; in fact if the fluctuations are fast enough they cancel out leaving the final operator unchanged. I present the numerical studies of holonomic quantum gates subject to this parametric noise, the fidelity of the noise and ideal evolution is calculated for different noise correlation times. The holonomic quantum gates seem robust not only for fast fluctuating fields but also for slow fluctuating fields. These results can be explained as due to the geometrical feature of the holonomic operator: for fast fluctuating fields the fluctuations are canceled out, for slow fluctuating fields the fluctuations do not perturb the loop in the parameter space. (author)

  18. Electrical characterization of 4H-SiC metal-oxide-semiconductor structure with Al2O3 stacking layers as dielectric

    Science.gov (United States)

    Chang, P. K.; Hwu, J. G.

    2018-02-01

    Interface defects and oxide bulk traps conventionally play important roles in the electrical performance of SiC MOS device. Introducing the Al2O3 stack grown by repeated anodization of Al films can notably lower the leakage current in comparison to the SiO2 structure, and enhance the minority carrier response at low frequency when the number of Al2O3 layers increase. In addition, the interface quality is not deteriorated by the stacking of Al2O3 layers because the stacked Al2O3 structure grown by anodization possesses good uniformity. In this work, the capacitance equivalent thickness (CET) of stacking Al2O3 will be up to 19.5 nm and the oxidation process can be carried out at room temperature. For the Al2O3 gate stack with CET 19.5 nm on n-SiC substrate, the leakage current at 2 V is 2.76 × 10-10 A/cm2, the interface trap density at the flatband voltage is 3.01 × 1011 eV-1 cm-2, and the effective breakdown field is 11.8 MV/cm. Frequency dispersion and breakdown characteristics may thus be improved as a result of the reduction in trap density. The Al2O3 stacking layers are capable of maintaining the leakage current as low as possible even after constant voltage stress test, which will further ameliorate reliability characteristics.

  19. Guanine base stacking in G-quadruplex nucleic acids

    Science.gov (United States)

    Lech, Christopher Jacques; Heddi, Brahim; Phan, Anh Tuân

    2013-01-01

    G-quadruplexes constitute a class of nucleic acid structures defined by stacked guanine tetrads (or G-tetrads) with guanine bases from neighboring tetrads stacking with one another within the G-tetrad core. Individual G-quadruplexes can also stack with one another at their G-tetrad interface leading to higher-order structures as observed in telomeric repeat-containing DNA and RNA. In this study, we investigate how guanine base stacking influences the stability of G-quadruplexes and their stacked higher-order structures. A structural survey of the Protein Data Bank is conducted to characterize experimentally observed guanine base stacking geometries within the core of G-quadruplexes and at the interface between stacked G-quadruplex structures. We couple this survey with a systematic computational examination of stacked G-tetrad energy landscapes using quantum mechanical computations. Energy calculations of stacked G-tetrads reveal large energy differences of up to 12 kcal/mol between experimentally observed geometries at the interface of stacked G-quadruplexes. Energy landscapes are also computed using an AMBER molecular mechanics description of stacking energy and are shown to agree quite well with quantum mechanical calculated landscapes. Molecular dynamics simulations provide a structural explanation for the experimentally observed preference of parallel G-quadruplexes to stack in a 5′–5′ manner based on different accessible tetrad stacking modes at the stacking interfaces of 5′–5′ and 3′–3′ stacked G-quadruplexes. PMID:23268444

  20. Comparison of the quality of the chest film between digital radiography and conventional high kV radiography

    International Nuclear Information System (INIS)

    Zeng Qingsi; Cen Renli; Chen Ling; He Jianxun; Lin Hanfei

    2003-01-01

    Objective: To evaluate the quality and usefulness of direct digital radiography system in roentgenogram of chest in clinical practice. Methods: 1000 cases of chest roentgenograms with digital radiography and high kV conventional radiography were selected for analysis by 3 senior radiologists. Results: 1. With digital radiography system, the quality of chest film was assessed as grade A in 50.6%, grade B in 38.5%, grade C in 10.9%, and no waste film. 2. With conventional high kV radiography, the quality of chest film was assessed as grade A in 41.1%, grade B in 44.1%, grade C in 13.3%, and waste film in 1.5%. The direct digital radiography was statistically superior to the conventional high kV radiography. 3. The fine structure of the lungs could be revealed in 100.0% of chest roentgenogram with direct digital radiograph system, which was significantly higher than that acquired with the conventional high KV radiography (78.6%, P < 0.001). Conclusion: Direct digital radiography could provide the chest film with better quality than that with the conventional high kV radiography. The direct digital radiography system is easy to operate, fast in capturing imaging and could provide post-processing techniques, which will facilitate the accurate diagnosis of chest radiography

  1. Transistor memory devices with large memory windows, using multi-stacking of densely packed, hydrophobic charge trapping metal nanoparticle array

    International Nuclear Information System (INIS)

    Cho, Ikjun; Cho, Jinhan; Kim, Beom Joon; Cho, Jeong Ho; Ryu, Sook Won

    2014-01-01

    Organic field-effect transistor (OFET) memories have rapidly evolved from low-cost and flexible electronics with relatively low-memory capacities to memory devices that require high-capacity memory such as smart memory cards or solid-state hard drives. Here, we report the high-capacity OFET memories based on the multilayer stacking of densely packed hydrophobic metal NP layers in place of the traditional transistor memory systems based on a single charge trapping layer. We demonstrated that the memory performances of devices could be significantly enhanced by controlling the adsorption isotherm behavior, multilayer stacking structure and hydrophobicity of the metal NPs. For this study, tetraoctylammonium (TOA)-stabilized Au nanoparticles (TOA-Au NPs ) were consecutively layer-by-layer (LbL) assembled with an amine-functionalized poly(amidoamine) dendrimer (PAD). The formed (PAD/TOA-Au NP ) n films were used as a multilayer stacked charge trapping layer at the interface between the tunneling dielectric layer and the SiO 2 gate dielectric layer. For a single Au NP layer (i.e. PAD/TOA-Au NP ) 1 ) with a number density of 1.82 × 10 12 cm −2 , the memory window of the OFET memory device was measured to be approximately 97 V. The multilayer stacked OFET memory devices prepared with four Au NP layers exhibited excellent programmable memory properties (i.e. a large memory window (ΔV th ) exceeding 145 V, a fast switching speed (1 μs), a high program/erase (P/E) current ratio (greater than 10 6 ) and good electrical reliability) during writing and erasing over a relatively short time scale under an operation voltage of 100 V applied at the gate. (paper)

  2. Dynamic Model of High Temperature PEM Fuel Cell Stack Temperature

    DEFF Research Database (Denmark)

    Andreasen, Søren Juhl; Kær, Søren Knudsen

    2007-01-01

    cathode air cooled 30 cell HTPEM fuel cell stack developed at the Institute of Energy Technology at Aalborg University. This fuel cell stack uses PEMEAS Celtec P-1000 membranes, runs on pure hydrogen in a dead end anode configuration with a purge valve. The cooling of the stack is managed by running......The present work involves the development of a model for predicting the dynamic temperature of a high temperature PEM (HTPEM) fuel cell stack. The model is developed to test different thermal control strategies before implementing them in the actual system. The test system consists of a prototype...... the stack at a high stoichiometric air flow. This is possible because of the PBI fuel cell membranes used, and the very low pressure drop in the stack. The model consists of a discrete thermal model dividing the stack into three parts: inlet, middle and end and predicting the temperatures in these three...

  3. Ultra-low power thin film transistors with gate oxide formed by nitric acid oxidation method

    International Nuclear Information System (INIS)

    Kobayashi, H.; Kim, W. B.; Matsumoto, T.

    2011-01-01

    We have developed a low temperature fabrication method of SiO 2 /Si structure by use of nitric acid, i.e., nitric acid oxidation of Si (NAOS) method, and applied it to thin film transistors (TFT). A silicon dioxide (SiO 2 ) layer formed by the NAOS method at room temperature possesses 1.8 nm thickness, and its leakage current density is as low as that of thermally grown SiO 2 layer with the same thickness formed at ∼900 deg C. The fabricated TFTs possess an ultra-thin NAOS SiO 2 /CVD SiO 2 stack gate dielectric structure. The ultrathin NAOS SiO 2 layer effectively blocks a gate leakage current, and thus, the thickness of the gate oxide layer can be decreased from 80 to 20 nm. The thin gate oxide layer enables to decrease the operation voltage to 2 V (cf. the conventional operation voltage of TFTs with 80 nm gate oxide: 12 V) because of the low threshold voltages, i.e., -0.5 V for P-ch TFTs and 0.5 V for N-ch TFTs, and thus the consumed power decreases to 1/36 of that of the conventional TFTs. The drain current increases rapidly with the gate voltage, and the sub-threshold voltage is ∼80 mV/dec. The low sub-threshold swing is attributable to the thin gate oxide thickness and low interface state density of the NAOS SiO 2 layer. (authors)

  4. Dynamic gating window for compensation of baseline shift in respiratory-gated radiation therapy

    International Nuclear Information System (INIS)

    Pepin, Eric W.; Wu Huanmei; Shirato, Hiroki

    2011-01-01

    Purpose: To analyze and evaluate the necessity and use of dynamic gating techniques for compensation of baseline shift during respiratory-gated radiation therapy of lung tumors. Methods: Motion tracking data from 30 lung tumors over 592 treatment fractions were analyzed for baseline shift. The finite state model (FSM) was used to identify the end-of-exhale (EOE) breathing phase throughout each treatment fraction. Using duty cycle as an evaluation metric, several methods of end-of-exhale dynamic gating were compared: An a posteriori ideal gating window, a predictive trend-line-based gating window, and a predictive weighted point-based gating window. These methods were evaluated for each of several gating window types: Superior/inferior (SI) gating, anterior/posterior beam, lateral beam, and 3D gating. Results: In the absence of dynamic gating techniques, SI gating gave a 39.6% duty cycle. The ideal SI gating window yielded a 41.5% duty cycle. The weight-based method of dynamic SI gating yielded a duty cycle of 36.2%. The trend-line-based method yielded a duty cycle of 34.0%. Conclusions: Dynamic gating was not broadly beneficial due to a breakdown of the FSM's ability to identify the EOE phase. When the EOE phase was well defined, dynamic gating showed an improvement over static-window gating.

  5. Travels with Gates - July 2010

    Science.gov (United States)

    New Sanctions SEOUL, South Korea, July 21, 2010 - Secretary of State Hillary Rodham Clinton, in Seoul - Secretary of State Hillary Rodham Clinton and Defense Secretary Robert M. Gates reaffirmed the U.S zone along with Secretary of State Hillary Rodham Clinton and their South Korean counterparts to

  6. Double-disc gate valve

    International Nuclear Information System (INIS)

    Wheatley, S.J.

    1979-01-01

    The invention relates to an improvement in a conventional double-disc gate valve having a vertically movable gate assembly including a wedge, spreaders slidably engaged therewith, a valve disc carried by the spreaders. When the gate assembly is lowered to a selected point in the valve casing, the valve discs are moved transversely outward to close inlet and outlet ports in the casing. The valve includes hold-down means for guiding the disc-and-spreader assemblies as they are moved transversely outward and inward. If such valves are operated at relatively high differential pressures, they sometimes jam during opening. Such jamming has been a problem for many years in gate valves used in gaseous diffusion plants for the separation of uranium isotopes. The invention is based on the finding that the above-mentioned jamming results when the outlet disc tilts about its horizontal axis in a certain way during opening of the valve. In accordance with the invention, tilting of the outlet disc is maintained at a tolerable value by providing the disc with a rigid downwardly extending member and by providing the casing with a stop for limiting inward arcuate movement of the member to a preselected value during opening of the valve

  7. Bill Gates eyes healthcare market.

    Science.gov (United States)

    Dunbar, C

    1995-02-01

    The entrepreneurial spirit is still top in Bill Gates' mind as he look toward healthcare and other growth industries. Microsoft's CEO has not intention of going the way of other large technology companies that became obsolete before they could compete today.

  8. Dry dock gate stability modelling

    Science.gov (United States)

    Oktoberty; Widiyanto; Sasono, E. J.; Pramono, S.; Wandono, A. T.

    2018-03-01

    The development of marine transportation needs in Indonesia increasingly opens national shipyard business opportunities to provide shipbuilding services to the shipbuilding vessels. That emphasizes the stability of prime. The ship's decking door becomes an integral part of the efficient place and the specification of the use of the asset of its operational ease. This study aims to test the stability of Dry Dock gate with the length of 35.4 meters using Maxsurf and Hydromax in analyzing the calculation were in its assessment using interval per 500 mm length so that it can get detail data toward longitudinal and transverse such as studying Ship planning in general. The test result shows dry dock gate meets IMO standard with ballast construction containing 54% and 68% and using fix ballast can produce GMt 1,924 m, tide height 11,357m. The GMt value indicates dry dick gate can be stable and firmly erect at the base of the mouth dry dock. When empty ballast produces GMt 0.996 which means dry dock date is stable, but can easily be torn down. The condition can be used during dry dock gate treatment.

  9. Electrical and materials properties of ZrO2 gate dielectrics grown by atomic layer chemical vapor deposition

    Science.gov (United States)

    Perkins, Charles M.; Triplett, Baylor B.; McIntyre, Paul C.; Saraswat, Krishna C.; Haukka, Suvi; Tuominen, Marko

    2001-04-01

    Structural and electrical properties of gate stack structures containing ZrO2 dielectrics were investigated. The ZrO2 films were deposited by atomic layer chemical vapor deposition (ALCVD) after different substrate preparations. The structure, composition, and interfacial characteristics of these gate stacks were examined using cross-sectional transmission electron microscopy and x-ray photoelectron spectroscopy. The ZrO2 films were polycrystalline with either a cubic or tetragonal crystal structure. An amorphous interfacial layer with a moderate dielectric constant formed between the ZrO2 layer and the substrate during ALCVD growth on chemical oxide-terminated silicon. Gate stacks with a measured equivalent oxide thickness (EOT) of 1.3 nm showed leakage values of 10-5 A/cm2 at a bias of -1 V from flatband, which is significantly less than that seen with SiO2 dielectrics of similar EOT. A hysteresis of 8-10 mV was seen for ±2 V sweeps while a midgap interface state density (Dit) of ˜3×1011 states/cm eV was determined from comparisons of measured and ideal capacitance curves.

  10. NSF tandem stack support structure deflection characteristics

    International Nuclear Information System (INIS)

    Cook, J.

    1979-12-01

    Results are reported of load tests carried out on the glass legs of the insulating stack of the 30 MV tandem Van de Graaff accelerator now under construction at Daresbury Laboratory. The tests to investigate the vulnerability of the legs when subjected to tensile stresses were designed to; establish the angle of rotation of the pads from which the stresses in the glass legs may be calculated, proof-test the structure and at the same time reveal any asymmetry in pad rotations or deflections, and to confirm the validity of the computer design analysis. (UK)

  11. Compliant Glass Seals for SOFC Stacks

    Energy Technology Data Exchange (ETDEWEB)

    Chou, Yeong -Shyung [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Choi, Jung-Pyung [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Xu, Wei [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Stephens, Elizabeth V. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Koeppel, Brian J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Stevenson, Jeffry W. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Lara-Curzio, Edgar [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2014-04-30

    This report summarizes results from experimental and modeling studies performed by participants in the Solid-State Energy Conversion Alliance (SECA) Core Technology Program, which indicate that compliant glass-based seals offer a number of potential advantages over conventional seals based on de-vitrifying glasses, including reduced stresses during stack operation and thermal cycling, and the ability to heal micro-damage induced during thermal cycling. The properties and composition of glasses developed and/or investigated in these studies are reported, along with results from long-term (up to 5,800h) evaluations of seals based on a compliant glass containing ceramic particles or ceramic fibers.

  12. Improved Direct Methanol Fuel Cell Stack

    Science.gov (United States)

    Wilson, Mahlon S.; Ramsey, John C.

    2005-03-08

    A stack of direct methanol fuel cells exhibiting a circular footprint. A cathode and anode manifold, tie-bolt penetrations and tie-bolts are located within the circular footprint. Each fuel cell uses two graphite-based plates. One plate includes a cathode active area that is defined by serpentine channels connecting the inlet and outlet cathode manifold. The other plate includes an anode active area defined by serpentine channels connecting the inlet and outlet of the anode manifold, where the serpentine channels of the anode are orthogonal to the serpentine channels of the cathode. Located between the two plates is the fuel cell active region.

  13. Displacive phase transformations and generalized stacking faults

    Czech Academy of Sciences Publication Activity Database

    Paidar, Václav; Ostapovets, Andriy; Duparc, O. H.; Khalfallah, O.

    2012-01-01

    Roč. 122, č. 3 (2012), s. 490-492 ISSN 0587-4246. [International Symposium on Physics of Materials, ISPMA /12./. Praha, 04.09.2011-08.09.2011] R&D Projects: GA AV ČR IAA100100920 Institutional research plan: CEZ:AV0Z10100520 Keywords : ab-initio calculations * close-packed structures * generalized stacking faults * homogeneous deformation * lattice deformation * many-body potentials Subject RIV: BM - Solid Matter Physics ; Magnetism Impact factor: 0.531, year: 2012

  14. Poly(methyl methacrylate) as a self-assembled gate dielectric for graphene field-effect transistors

    Energy Technology Data Exchange (ETDEWEB)

    Sanne, A.; Movva, H. C. P.; Kang, S.; McClellan, C.; Corbet, C. M.; Banerjee, S. K. [Microelectronics Research Center, University of Texas, Austin, Texas 78758 (United States)

    2014-02-24

    We investigate poly(methyl methacrylate) (PMMA) as a low thermal budget organic gate dielectric for graphene field effect-transistors (GFETs) based on a simple process flow. We show that high temperature baking steps above the glass transition temperature (∼130 °C) can leave a self-assembled, thin PMMA film on graphene, where we get a gate dielectric almost for “free” without additional atomic layer deposition type steps. Electrical characterization of GFETs with PMMA as a gate dielectric yields a dielectric constant of k = 3.0. GFETs with thinner PMMA dielectrics have a lower dielectric constant due to decreased polarization arising from neutralization of dipoles and charged carriers as baking temperatures increase. The leakage through PMMA gate dielectric increases with decreasing dielectric thickness and increasing electric field. Unlike conventional high-k gate dielectrics, such low-k organic gate dielectrics are potentially attractive for devices such as the proposed Bilayer pseudoSpin Field-Effect Transistor or flexible high speed graphene electronics.

  15. The Study of Electrical Properties for Multilayer La2O3/Al2O3 Dielectric Stacks and LaAlO3 Dielectric Film Deposited by ALD.

    Science.gov (United States)

    Feng, Xing-Yao; Liu, Hong-Xia; Wang, Xing; Zhao, Lu; Fei, Chen-Xi; Liu, He-Lei

    2017-12-01

    The capacitance and leakage current properties of multilayer La 2 O 3 /Al 2 O 3 dielectric stacks and LaAlO 3 dielectric film are investigated in this paper. A clear promotion of capacitance properties is observed for multilayer La 2 O 3 /Al 2 O 3 stacks after post-deposition annealing (PDA) at 800 °C compared with PDA at 600 °C, which indicated the recombination of defects and dangling bonds performs better at the high-k/Si substrate interface for a higher annealing temperature. For LaAlO 3 dielectric film, compared with multilayer La 2 O 3 /Al 2 O 3 dielectric stacks, a clear promotion of trapped charges density (N ot ) and a degradation of interface trap density (D it ) can be obtained simultaneously. In addition, a significant improvement about leakage current property is observed for LaAlO 3 dielectric film compared with multilayer La 2 O 3 /Al 2 O 3 stacks at the same annealing condition. We also noticed that a better breakdown behavior for multilayer La 2 O 3 /Al 2 O 3 stack is achieved after annealing at a higher temperature for its less defects.

  16. Computerized plutonium laboratory-stack monitoring system

    International Nuclear Information System (INIS)

    Stafford, R.G.; DeVore, R.K.

    1977-01-01

    The Los Alamos Scientific Laboratory has recently designed and constructed a Plutonium Research and Development Facility to meet design criteria imposed by the United States Energy Research and Development Administration. A primary objective of the design criteria is to assure environmental protection and to reliably monitor plutonium effluent via the ventilation exhaust systems. A state-of-the-art facility exhaust air monitoring system is described which establishes near ideal conditions for evaluating plutonium activity in the stack effluent. Total and static pressure sensing manifolds are incorporated to measure average velocity and integrated total discharge air volume. These data are logged at a computer which receives instrument data through a multiplex scanning system. A multipoint isokinetic sampling assembly with associated instrumentation is described. Continuous air monitors have been designed to sample from the isokinetic sampling assembly and transmit both instantaneous and integrated stack effluent concentration data to the computer and various cathode ray tube displays. The continuous air monitors also serve as room air monitors in the plutonium facility with the primary objective of timely evacuation of personnel if an above tolerance airborne plutonium concentration is detected. Several continuous air monitors are incorporated in the ventilation system to assist in identification of release problem areas

  17. Control of heteroepitaxial stacking by substrate miscut

    International Nuclear Information System (INIS)

    Bonham, S.W.; Flynn, C.P.

    1998-01-01

    We report studies of fcc epitaxial crystals, grown on Nb(110), in which the Nb surface offers a template for selection between the two alternative stackings, ABCA hor-ellipsis and ACBA hor-ellipsis of the fcc close-packed planes. The Nb templates were grown epitaxially about 500 Angstrom thick on sapphire (11 bar 20), and the fcc material studied was Cu 3 Au. From symmetry it is not possible for the perfect bcc (110) surface to cause any such selection, which is here attributed instead to vicinal miscut: the logarithm of the stacking ratio must be even in miscut along [001] and odd in miscut along [1 bar 10]. We find that the measured selectivity is small for miscuts less than about 0.5 degree, but approaches a factor 10 3 for miscuts along [1 bar 10] greater than about 1 degree. A mechanism for the selection process is discussed in terms of fingered mesostructures that grow on Nb(110) in this regime, as observed first by Zhou, Bonham, and Flynn. copyright 1998 The American Physical Society

  18. Generalized stacking fault energies of alloys.

    Science.gov (United States)

    Li, Wei; Lu, Song; Hu, Qing-Miao; Kwon, Se Kyun; Johansson, Börje; Vitos, Levente

    2014-07-02

    The generalized stacking fault energy (γ surface) provides fundamental physics for understanding the plastic deformation mechanisms. Using the ab initio exact muffin-tin orbitals method in combination with the coherent potential approximation, we calculate the γ surface for the disordered Cu-Al, Cu-Zn, Cu-Ga, Cu-Ni, Pd-Ag and Pd-Au alloys. Studying the effect of segregation of the solute to the stacking fault planes shows that only the local chemical composition affects the γ surface. The calculated alloying trends are discussed using the electronic band structure of the base and distorted alloys.Based on our γ surface results, we demonstrate that the previous revealed 'universal scaling law' between the intrinsic energy barriers (IEBs) is well obeyed in random solid solutions. This greatly simplifies the calculations of the twinning measure parameters or the critical twinning stress. Adopting two twinnability measure parameters derived from the IEBs, we find that in binary Cu alloys, Al, Zn and Ga increase the twinnability, while Ni decreases it. Aluminum and gallium yield similar effects on the twinnability.

  19. Design of double gate vertical tunnel field effect transistor using HDB and its performance estimation

    Science.gov (United States)

    Seema; Chauhan, Sudakar Singh

    2018-05-01

    In this paper, we demonstrate the double gate vertical tunnel field-effect transistor using homo/hetero dielectric buried oxide (HDB) to obtain the optimized device characteristics. In this concern, the existence of double gate, HDB and electrode work-function engineering enhances DC performance and Analog/RF performance. The use of electrostatic doping helps to achieve higher on-current owing to occurrence of higher tunneling generation rate of charge carriers at the source/epitaxial interface. Further, lightly doped drain region and high- k dielectric below channel and drain region are responsible to suppress the ambipolar current. Simulated results clarifies that proposed device have achieved the tremendous performance in terms of driving current capability, steeper subthreshold slope (SS), drain induced barrier lowering (DIBL), hot carrier effects (HCEs) and high frequency parameters for better device reliability.

  20. High performance solution processed zirconium oxide gate dielectric appropriate for low temperature device application

    Energy Technology Data Exchange (ETDEWEB)

    Hasan, Musarrat; Nguyen, Manh-Cuong; Kim, Hyojin; You, Seung-Won; Jeon, Yoon-Seok; Tong, Duc-Tai; Lee, Dong-Hwi; Jeong, Jae Kyeong; Choi, Rino, E-mail: rino.choi@inha.ac.kr

    2015-08-31

    This paper reports a solution processed electrical device with zirconium oxide gate dielectric that was fabricated at a low enough temperature appropriate for flexible electronics. Both inorganic dielectric and channel materials were synthesized in the same organic solvent. The dielectric constant achieved was 13 at 250 °C with a reasonably low leakage current. The bottom gate transistor devices showed the highest mobility of 75 cm{sup 2}/V s. The device is operated at low voltage with high-k dielectric with excellent transconductance and low threshold voltage. Overall, the results highlight the potential of low temperature solution based deposition in fabricating more complicated circuits for a range of applications. - Highlights: • We develop a low temperature inorganic dielectric deposition process. • We fabricate oxide semiconductor channel devices using all-solution processes. • Same solvent is used for dielectric and oxide semiconductor deposition.

  1. Effect of oxygen on tuning the TiNx metal gate work function on LaLuO3

    International Nuclear Information System (INIS)

    Mitrovic, I.Z.; Przewlocki, H.M.; Piskorski, K.; Simutis, G.; Dhanak, V.R.; Sedghi, N.; Hall, S.

    2012-01-01

    This paper presents experimental evidence on effective work function tuning due to the presence of oxygen at the TiNx/LaLuO 3 interface. Two complementary techniques, internal photoemission and X-ray photoelectron spectroscopy, show good agreement on the position of the metal gate Fermi level to conduction (2.79 ± 0.25 eV) and valence (2.65 ± 0.08 eV) band edge for TiNx/bulk LaLuO 3 gate stacks. The chemical shifts of Ti2p and N1s core levels and different degree in ionicity of TiNx metal gates correlate with the observed valence band offset shifts. The results have significance for setting the band edge work function and resulting low threshold voltage for ultimately scaled LaLuO 3 -based p-metal oxide semiconductor field effect transistor devices. - Highlights: ► The conduction band offset measured by internal photoemission. ► The valence band offset (VBO) measured by X-ray photoelectron spectroscopy. ► Different degree in ionicity of TiNx correlates with the VBO shifts. ► The effective work function of the gate stacks varies from 4.6 to 5.2 eV. ► Oxygen at the TiNx/LaLuO 3 interface increases effective work function.

  2. Description of gasket failure in a 7 cell PEMFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Husar, Attila; Serra, Maria [Institut de Robotica i Informatica Industrial, Parc Tecnologic de Barcelona, Edifici U, C. Llorens i Artigas, 4-6, 2a Planta, 08028 Barcelona (Spain); Kunusch, Cristian [Laboratorio de Electronica Industrial Control e Instrumentacion, Facultad de Ingenieria, UNLP (Argentina)

    2007-06-10

    This article presents the data and the description of a fuel cell stack that failed due to gasket degradation. The fuel cell under study is a 7 cell stack. The unexpected change in several variables such as temperature, pressure and voltage indicated the possible failure of the stack. The stack was monitored over a 6 h period in which data was collected and consequently analyzed to conclude that the fuel cell stack failed due to a crossover leak on the anode inlet port located on the cathode side gasket of cell 2. This stack failure analysis revealed a series of indicators that could be used by a super visional controller in order to initiate a shutdown procedure. (author)

  3. Simple Stacking Methods for Silicon Micro Fuel Cells

    Directory of Open Access Journals (Sweden)

    Gianmario Scotti

    2014-08-01

    Full Text Available We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack. We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV of 1.6 V and a power density of 63 mW·cm−2, proving the viability of the design.

  4. Temperature behavior of electrical properties of high-k lead-magnesium-niobium titanate thin-films

    Energy Technology Data Exchange (ETDEWEB)

    Chen Wenbin, E-mail: cwb0201@163.com [Electromechanical Engineering College, Guilin University of Electronic Technology (China); McCarthy, Kevin G. [Department of Electrical and Electronic Engineering, University College Cork (Ireland); Copuroglu, Mehmet; O' Brien, Shane; Winfield, Richard; Mathewson, Alan [Tyndall National Institute, University College Cork (Ireland)

    2012-05-01

    This paper reports on the temperature dependence of the electrical properties of high-k lead-magnesium-niobium titanate thin films processed with different compositions (with and without nanoparticles) and with different annealing temperatures (450 Degree-Sign C and 750 Degree-Sign C). These characterization results support the ongoing investigation of the material's electrical properties which are necessary before the dielectric can be used in silicon-based IC applications.

  5. SEMICONDUCTOR TECHNOLOGY: TaN wet etch for application in dual-metal-gate integration technology

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2009-12-01

    Wet-etch etchants and the TaN film method for dual-metal-gate integration are investigated. Both HF/HN O3/H2O and NH4OH/H2O2 solutions can etch TaN effectively, but poor selectivity to the gate dielectric for the HF/HNO3/H2O solution due to HF being included in HF/HNO3/H2O, and the fact that TaN is difficult to etch in the NH4OH/H2O2 solution at the first stage due to the thin TaOxNy layer on the TaN surface, mean that they are difficult to individually apply to dual-metal-gate integration. A two-step wet etching strategy using the HF/HNO3/H2O solution first and the NH4OH/H2O2 solution later can fully remove thin TaN film with a photo-resist mask and has high selectivity to the HfSiON dielectric film underneath. High-k dielectric film surfaces are smooth after wet etching of the TaN metal gate and MOSCAPs show well-behaved C-V and Jg-Vg characteristics, which all prove that the wet etching of TaN has little impact on electrical performance and can be applied to dual-metal-gate integration technology for removing the first TaN metal gate in the PMOS region.

  6. Development of the electric utility dispersed use PAFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Horiuchi, Hiroshi; Kotani, Ikuo [Mitsubishi Electric Co., Kobe (Japan); Morotomi, Isamu [Kansai Electric Power Co., Hyogo (Japan)] [and others

    1996-12-31

    Kansai Electric Power Co. and Mitsubishi Electric Co. have been developing the electric utility dispersed use PAFC stack operated under the ambient pressure. The new cell design have been developed, so that the large scale cell (1 m{sup 2} size) was adopted for the stack. To confirm the performance and the stability of the 1 m{sup 2} scale cell design, the short stack study had been performed.

  7. Stacked Heterogeneous Neural Networks for Time Series Forecasting

    Directory of Open Access Journals (Sweden)

    Florin Leon

    2010-01-01

    Full Text Available A hybrid model for time series forecasting is proposed. It is a stacked neural network, containing one normal multilayer perceptron with bipolar sigmoid activation functions, and the other with an exponential activation function in the output layer. As shown by the case studies, the proposed stacked hybrid neural model performs well on a variety of benchmark time series. The combination of weights of the two stack components that leads to optimal performance is also studied.

  8. Linear gate with prescaled window

    Energy Technology Data Exchange (ETDEWEB)

    Koch, J; Bissem, H H; Krause, H; Scobel, W [Hamburg Univ. (Germany, F.R.). 1. Inst. fuer Experimentalphysik

    1978-07-15

    An electronic circuit is described that combines the features of a linear gate, a single channel analyzer and a prescaler. It allows selection of a pulse height region between two adjustable thresholds and scales the intensity of the spectrum within this window down by a factor 2sup(N) (0<=N<=9), whereas the complementary part of the spectrum is transmitted without being affected.

  9. Interface Engineering and Gate Dielectric Engineering for High Performance Ge MOSFETs

    Directory of Open Access Journals (Sweden)

    Jiabao Sun

    2015-01-01

    Full Text Available In recent years, germanium has attracted intensive interests for its promising applications in the microelectronics industry. However, to achieve high performance Ge channel devices, several critical issues still have to be addressed. Amongst them, a high quality gate stack, that is, a low defect interface layer and a dielectric layer, is of crucial importance. In this work, we first review the existing methods of interface engineering and gate dielectric engineering and then in more detail we discuss and compare three promising approaches (i.e., plasma postoxidation, high pressure oxidation, and ozone postoxidation. It has been confirmed that these approaches all can significantly improve the overall performance of the metal-oxide-semiconductor field effect transistor (MOSFET device.

  10. Nonvolatile Memories Using Quantum Dot (QD) Floating Gates Assembled on II-VI Tunnel Insulators

    Science.gov (United States)

    Suarez, E.; Gogna, M.; Al-Amoody, F.; Karmakar, S.; Ayers, J.; Heller, E.; Jain, F.

    2010-07-01

    This paper presents preliminary data on quantum dot gate nonvolatile memories using nearly lattice-matched ZnS/Zn0.95Mg0.05S/ZnS tunnel insulators. The GeO x -cladded Ge and SiO x -cladded Si quantum dots (QDs) are self-assembled site-specifically on the II-VI insulator grown epitaxially over the Si channel (formed between the source and drain region). The pseudomorphic II-VI stack serves both as a tunnel insulator and a high- κ dielectric. The effect of Mg incorporation in ZnMgS is also investigated. For the control gate insulator, we have used Si3N4 and SiO2 layers grown by plasma- enhanced chemical vapor deposition.

  11. Edge states in gated bilayer-monolayer graphene ribbons and bilayer domain walls

    Science.gov (United States)

    Mirzakhani, M.; Zarenia, M.; Peeters, F. M.

    2018-05-01

    Using the effective continuum model, the electron energy spectrum of gated bilayer graphene with a step-like region of decoupled graphene layers at the edge of the sample is studied. Different types of coupled-decoupled interfaces are considered, i.e., zigzag (ZZ) and armchair junctions, which result in significant different propagating states. Two non-valley-polarized conducting edge states are observed for ZZ type, which are mainly located around the ZZ-ended graphene layers. Additionally, we investigated both BA-BA and BA-AB domain walls in the gated bilayer graphene within the continuum approximation. Unlike the BA-BA domain wall, which exhibits gapped insulating behaviour, the domain walls surrounded by different stackings of bilayer regions feature valley-polarized edge states. Our findings are consistent with other theoretical calculations, such as from the tight-binding model and first-principles calculations, and agree with experimental observations.

  12. Turbostratic stacked CVD graphene for high-performance devices

    Science.gov (United States)

    Uemura, Kohei; Ikuta, Takashi; Maehashi, Kenzo

    2018-03-01

    We have fabricated turbostratic stacked graphene with high-transport properties by the repeated transfer of CVD monolayer graphene. The turbostratic stacked CVD graphene exhibited higher carrier mobility and conductivity than CVD monolayer graphene. The electron mobility for the three-layer turbostratic stacked CVD graphene surpassed 10,000 cm2 V-1 s-1 at room temperature, which is five times greater than that for CVD monolayer graphene. The results indicate that the high performance is derived from maintenance of the linear band dispersion, suppression of the carrier scattering, and parallel conduction. Therefore, turbostratic stacked CVD graphene is a superior material for high-performance devices.

  13. Method for monitoring stack gases for uranium activity

    International Nuclear Information System (INIS)

    Beverly, C.R.; Ernstberger, H.G.

    1988-01-01

    A method for sampling stack gases emanating from the purge cascade of a gaseous diffusion cascade system utilized to enrich uranium for determining the presence and extent of uranium in the stack gases in the form of gaseous uranium hexafluoride, is described comprising the steps of removing a side stream of gases from the stack gases, contacting the side stream of the stack gases with a stream of air sufficiently saturated with moisture for reacting with and converting any gaseous uranium hexafluroide contracted thereby in the side stream of stack gases to particulate uranyl fluoride. Thereafter contacting the side stream of stack gases containing the particulate uranyl fluoride with moving filter means for continuously intercepting and conveying the intercepted particulate uranyl fluoride away from the side stream of stack gases, and continually scanning the moving filter means with radiation monitoring means for sensing the presence and extent of particulate uranyl fluoride on the moving filter means which is indicative of the extent of particulate uranyl fluoride in the side stream of stack gases which in turn is indicative of the presence and extent of uranium hexafluoride in the stack gases

  14. Highly Efficient, Durable Regenerative Solid Oxide Stack, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Precision Combustion, Inc. (PCI) proposes to develop a highly efficient regenerative solid oxide stack design. Novel structural elements allow direct internal...

  15. Enhanced stability of thin film transistors with double-stacked amorphous IWO/IWO:N channel layer

    Science.gov (United States)

    Lin, Dong; Pi, Shubin; Yang, Jianwen; Tiwari, Nidhi; Ren, Jinhua; Zhang, Qun; Liu, Po-Tsun; Shieh, Han-Ping

    2018-06-01

    In this work, bottom-gate top-contact thin film transistors with double-stacked amorphous IWO/IWO:N channel layer were fabricated. Herein, amorphous IWO and N-doped IWO were deposited as front and back channel layers, respectively, by radio-frequency magnetron sputtering. The electrical characteristics of the bi-layer-channel thin film transistors (TFTs) were examined and compared with those of single-layer-channel (i.e., amorphous IWO or IWO:N) TFTs. It was demonstrated to exhibit a high mobility of 27.2 cm2 V‑1 s‑1 and an on/off current ratio of 107. Compared to the single peers, bi-layer a-IWO/IWO:N TFTs showed smaller hysteresis and higher stability under negative bias stress and negative bias temperature stress. The enhanced performance could be attributed to its unique double-stacked channel configuration, which successfully combined the merits of the TFTs with IWO and IWO:N channels. The underlying IWO thin film provided percolation paths for electron transport, meanwhile, the top IWO:N layer reduced the bulk trap densities. In addition, the IWO channel/gate insulator interface had reduced defects, and IWO:N back channel surface was insensitive to the ambient atmosphere. Overall, the proposed bi-layer a-IWO/IWO:N TFTs show potential for practical applications due to its possibly long-term serviceability.

  16. Durable solid oxide electrolysis cells and stacks

    Energy Technology Data Exchange (ETDEWEB)

    Ming Chen

    2010-08-15

    The purpose of this project was to make a substantial contribution to development of a cost competitive electrolysis technology based on solid oxide cells. The strategy was to address what had been identified as the key issues in previous research projects. Accordingly five lines of work were carried out in the here reported project: 1) Cell and stack element testing and post test characterization to identify major degradation mechanisms under electrolysis operation. 2) Development of interconnects and coatings to allow stable electrolysis operation at approx850 deg. C or above. 3) Development of seals with reduced Si emission. 4) Development of durable SOEC cathodes. 5) Modeling. Good progress has been made on several of the planned activities. The outcome and most important achievements of the current project are listed for the five lines of the work. (LN)

  17. ATLAS software stack on ARM64

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00529764; The ATLAS collaboration; Stewart, Graeme; Seuster, Rolf; Quadt, Arnulf

    2017-01-01

    This paper reports on the port of the ATLAS software stack onto new prototype ARM64 servers. This included building the “external” packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adjustments. A few additional modifications were needed to account for the different operating system, Ubuntu instead of Scientific Linux 6 / CentOS7. Selected results from the validation of the physics outputs on these ARM 64-bit servers will be shown. CPU, memory and IO intensive benchmarks using ATLAS specific environment and infrastructure have been performed, with a particular emphasis on the performance vs. energy consumption.

  18. ATLAS software stack on ARM64

    Science.gov (United States)

    Smith, Joshua Wyatt; Stewart, Graeme A.; Seuster, Rolf; Quadt, Arnulf; ATLAS Collaboration

    2017-10-01

    This paper reports on the port of the ATLAS software stack onto new prototype ARM64 servers. This included building the “external” packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adjustments. A few additional modifications were needed to account for the different operating system, Ubuntu instead of Scientific Linux 6 / CentOS7. Selected results from the validation of the physics outputs on these ARM 64-bit servers will be shown. CPU, memory and IO intensive benchmarks using ATLAS specific environment and infrastructure have been performed, with a particular emphasis on the performance vs. energy consumption.

  19. Stacked generalization: an introduction to super learning.

    Science.gov (United States)

    Naimi, Ashley I; Balzer, Laura B

    2018-04-10

    Stacked generalization is an ensemble method that allows researchers to combine several different prediction algorithms into one. Since its introduction in the early 1990s, the method has evolved several times into a host of methods among which is the "Super Learner". Super Learner uses V-fold cross-validation to build the optimal weighted combination of predictions from a library of candidate algorithms. Optimality is defined by a user-specified objective function, such as minimizing mean squared error or maximizing the area under the receiver operating characteristic curve. Although relatively simple in nature, use of Super Learner by epidemiologists has been hampered by limitations in understanding conceptual and technical details. We work step-by-step through two examples to illustrate concepts and address common concerns.

  20. Manifold seal structure for fuel cell stack

    Science.gov (United States)

    Collins, William P.

    1988-01-01

    The seal between the sides of a fuel cell stack and the gas manifolds is improved by adding a mechanical interlock between the adhesive sealing strip and the abutting surface of the manifolds. The adhesive is a material which can flow to some extent when under compression, and the mechanical interlock is formed providing small openings in the portion of the manifold which abuts the adhesive strip. When the manifolds are pressed against the adhesive strips, the latter will flow into and through the manifold openings to form buttons or ribs which mechanically interlock with the manifolds. These buttons or ribs increase the bond between the manifolds and adhesive, which previously relied solely on the adhesive nature of the adhesive.

  1. Actuators Using Piezoelectric Stacks and Displacement Enhancers

    Science.gov (United States)

    Bar-Cohen, Yoseph; Sherrit, Stewart; Bao, Xiaoqi; Badescu, Mircea; Lee, Hyeong Jae; Walkenmeyer, Phillip; Lih, Shyh-Shiuh

    2015-01-01

    Actuators are used to drive all active mechanisms including machines, robots, and manipulators to name a few. The actuators are responsible for moving, manipulating, displacing, pushing and executing any action that is needed by the mechanism. There are many types and principles of actuation that are responsible for these movements ranging from electromagnetic, electroactive, thermo-mechanic, piezoelectric, electrostrictive etc. Actuators are readily available from commercial producers but there is a great need for reducing their size, increasing their efficiency and reducing their weight. Studies at JPL’s Non Destructive Evaluation and Advanced Actuators (NDEAA) Laboratory have been focused on the use of piezoelectric stacks and novel designs taking advantage of piezoelectric’s potential to provide high torque/force density actuation and high electromechanical conversion efficiency. The actuators/motors that have been developed and reviewed in this paper are operated by various horn configurations as well as the use of pre-stress flexures that make them thermally stable and increases their coupling efficiency. The use of monolithic designs that pre-stress the piezoelectric stack eliminates the use of compression stress bolt. These designs enable the embedding of developed solid-state motors/actuators in any structure with the only macroscopically moving parts are the rotor or the linear translator. Finite element modeling and design tools were used to determine the requirements and operation parameters and the results were used to simulate, design and fabricate novel actuators/motors. The developed actuators and performance will be described and discussed in this paper.

  2. A high performance gate drive for large gate turn off thyristors

    Energy Technology Data Exchange (ETDEWEB)

    Szilagyi, C.P.

    1993-01-01

    Past approaches to gate turn-off (GTO) gating are application oriented, inefficient and dissipate power even when inactive. They allow the gate to avalanch, and do not reduce GTO turn-on and turn-off losses. A new approach is proposed which will allow modular construction and adaptability to large GTOs in the 50 amp to 2000 amp range. The proposed gate driver can be used in large voltage source and current source inverters and other power converters. The approach consists of a power metal-oxide-silicon field effect transistor (MOSFET) technology gating unit, with associated logic and supervisory circuits and an isolated flyback converter as the dc power source for the gating unit. The gate driver formed by the gating unit and the flyback converter is designed for 4000 V isolation. Control and supervisory signals are exchanged between the gate driver and the remote control system via fiber optics. The gating unit has programmable front-porch current amplitude and pulse-width, programmable closed-loop controlled back-porch current, and a turn-off switch capable of supplying negative gate current at demand as a function of peak controllable forward anode current. The GTO turn-on, turn-off and gate avalanch losses are reduced to a minimum. The gate driver itself has minimum operating losses. Analysis, design and practical realization are reported. 19 refs., 54 figs., 1 tab.

  3. Band alignments and improved leakage properties of (La2O3)0.5(SiO2)0.5/SiO2/GaN stacks for high-temperature metal-oxide-semiconductor field-effect transistor applications

    Science.gov (United States)

    Gao, L. G.; Xu, B.; Guo, H. X.; Xia, Y. D.; Yin, J.; Liu, Z. G.

    2009-06-01

    The band alignments of (La2O3)0.5(SiO2)0.5(LSO)/GaN and LSO/SiO2/GaN gate dielectric stacks were investigated comparatively by using x-ray photoelectron spectroscopy. The valence band offsets for LSO/GaN stack and LSO/SiO2/GaN stack are 0.88 and 1.69 eV, respectively, while the corresponding conduction band offsets are found to be 1.40 and 1.83 eV, respectively. Measurements of the leakage current density as function of temperature revealed that the LSO/SiO2/GaN stack has much lower leakage current density than that of the LSO/GaN stack, especially at high temperature. It is concluded that the presence of a SiO2 buffer layer increases band offsets and reduces the leakage current density effectively.

  4. Cognitive mechanisms associated with auditory sensory gating

    Science.gov (United States)

    Jones, L.A.; Hills, P.J.; Dick, K.M.; Jones, S.P.; Bright, P.

    2016-01-01

    Sensory gating is a neurophysiological measure of inhibition that is characterised by a reduction in the P50 event-related potential to a repeated identical stimulus. The objective of this work was to determine the cognitive mechanisms that relate to the neurological phenomenon of auditory sensory gating. Sixty participants underwent a battery of 10 cognitive tasks, including qualitatively different measures of attentional inhibition, working memory, and fluid intelligence. Participants additionally completed a paired-stimulus paradigm as a measure of auditory sensory gating. A correlational analysis revealed that several tasks correlated significantly with sensory gating. However once fluid intelligence and working memory were accounted for, only a measure of latent inhibition and accuracy scores on the continuous performance task showed significant sensitivity to sensory gating. We conclude that sensory gating reflects the identification of goal-irrelevant information at the encoding (input) stage and the subsequent ability to selectively attend to goal-relevant information based on that previous identification. PMID:26716891

  5. A bistable electromagnetically actuated rotary gate microvalve

    International Nuclear Information System (INIS)

    Luharuka, Rajesh; Hesketh, Peter J

    2008-01-01

    Two types of rotary gate microvalves are developed for flow modulation in microfluidic systems. These microvalves have been tested for an open flow rate of up to 100 sccm and operate under a differential pressure of 6 psig with flow modulation of up to 100. The microvalve consists of a suspended gate that rotates in the plane of the chip to regulate flow through the orifice. The gate is suspended by a novel fully compliant in-plane rotary bistable micromechanism (IPRBM) that advantageously constrains the gate in all degrees of freedom except for in-plane rotational motion. Multiple inlet/outlet orifices provide flexibility of operating the microvalve in three different flow configurations. The rotary gate microvalve is switched with an external electromagnetic actuator. The suspended gate is made of a soft magnetic material and its electromagnetic actuation is based on the operating principle of a variable-reluctance stepper motor

  6. Experimental superposition of orders of quantum gates

    Science.gov (United States)

    Procopio, Lorenzo M.; Moqanaki, Amir; Araújo, Mateus; Costa, Fabio; Alonso Calafell, Irati; Dowd, Emma G.; Hamel, Deny R.; Rozema, Lee A.; Brukner, Časlav; Walther, Philip

    2015-01-01

    Quantum computers achieve a speed-up by placing quantum bits (qubits) in superpositions of different states. However, it has recently been appreciated that quantum mechanics also allows one to ‘superimpose different operations'. Furthermore, it has been shown that using a qubit to coherently control the gate order allows one to accomplish a task—determining if two gates commute or anti-commute—with fewer gate uses than any known quantum algorithm. Here we experimentally demonstrate this advantage, in a photonic context, using a second qubit to control the order in which two gates are applied to a first qubit. We create the required superposition of gate orders by using additional degrees of freedom of the photons encoding our qubits. The new resource we exploit can be interpreted as a superposition of causal orders, and could allow quantum algorithms to be implemented with an efficiency unlikely to be achieved on a fixed-gate-order quantum computer. PMID:26250107

  7. High speed gated x-ray imagers

    International Nuclear Information System (INIS)

    Kilkenny, J.D.; Bell, P.; Hanks, R.; Power, G.; Turner, R.E.; Wiedwald, J.

    1988-01-01

    Single and multi-frame gated x-ray images with time-resolution as fast as 150 psec are described. These systems are based on the gating of microchannel plates in a stripline configuration. The gating voltage comes from the avalanche breakdown of reverse biased p-n junction producing high power voltage pulses as short as 70 psec. Results from single and four frame x-ray cameras used on Nova are described. 8 refs., 9 figs

  8. Seven channel gated charge to time converter

    Energy Technology Data Exchange (ETDEWEB)

    Stubbs, R J; Waddoup, W D [Durham Univ. (UK)

    1977-11-01

    By using a hybrid integrated circuit seven independent gated charge to time converters have been constructed in a single width NIM module. Gate widths from < approximately 10 ns to approximately 300 ns are possible with a resolution of 0.25 pC, linearity is better than +-1 pC over 2.5 decades of input signal height. Together with a multichannel scaling system described in the following paper one has a very powerful multichannel gated ADC system.

  9. Gating-ML: XML-based gating descriptions in flow cytometry.

    Science.gov (United States)

    Spidlen, Josef; Leif, Robert C; Moore, Wayne; Roederer, Mario; Brinkman, Ryan R

    2008-12-01

    The lack of software interoperability with respect to gating due to lack of a standardized mechanism for data exchange has traditionally been a bottleneck, preventing reproducibility of flow cytometry (FCM) data analysis and the usage of multiple analytical tools. To facilitate interoperability among FCM data analysis tools, members of the International Society for the Advancement of Cytometry (ISAC) Data Standards Task Force (DSTF) have developed an XML-based mechanism to formally describe gates (Gating-ML). Gating-ML, an open specification for encoding gating, data transformations and compensation, has been adopted by the ISAC DSTF as a Candidate Recommendation. Gating-ML can facilitate exchange of gating descriptions the same way that FCS facilitated for exchange of raw FCM data. Its adoption will open new collaborative opportunities as well as possibilities for advanced analyses and methods development. The ISAC DSTF is satisfied that the standard addresses the requirements for a gating exchange standard.

  10. A dual shared stack for FSLM in Erika Enterprise

    NARCIS (Netherlands)

    Balasubramanian, S.M.N.; Afshar, S.; Gai, P.; Behnam, M.; Bril, R.J.

    2017-01-01

    Recently, the flexible spin-lock model (FSLM) has been introduced, unifying spin-based and suspension-based resource sharing protocols for real-time multi-core platforms. Unlike the multiprocessor stack resource policy (MSRP), FSLM doesn’t allow tasks on a core to share a single stack, however. In

  11. Long Josephson Junction Stack Coupled to a Cavity

    DEFF Research Database (Denmark)

    Madsen, Søren Peder; Pedersen, Niels Falsig; Groenbech-Jensen, N.

    2007-01-01

    A stack of inductively coupled long Josephson junctions are modeled as a system of coupled sine-Gordon equations. One boundary of the stack is coupled electrically to a resonant cavity. With one fluxon in each Josephson junction, the inter-junction fluxon forces are repulsive. We look at a possible...... transition, induced by the cavity, to a bunched state....

  12. Efficient Context Switching for the Stack Cache: Implementation and Analysis

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian; Naji, Amine

    2015-01-01

    , the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved...

  13. Analysis of preemption costs for the stack cache

    DEFF Research Database (Denmark)

    Naji, Amine; Abbaspour, Sahar; Brandner, Florian

    2018-01-01

    , the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved...

  14. Simultaneous stack-gas scrubbing and waste water treatment

    Science.gov (United States)

    Poradek, J. C.; Collins, D. D.

    1980-01-01

    Simultaneous treatment of wastewater and S02-laden stack gas make both treatments more efficient and economical. According to results of preliminary tests, solution generated by stack gas scrubbing cycle reduces bacterial content of wastewater. Both processess benefit by sharing concentrations of iron.

  15. A Software Managed Stack Cache for Real-Time Systems

    DEFF Research Database (Denmark)

    Jordan, Alexander; Abbaspourseyedi, Sahar; Schoeberl, Martin

    2016-01-01

    In a real-time system, the use of a scratchpad memory can mitigate the difficulties related to analyzing data caches, whose behavior is inherently hard to predict. We propose to use a scratchpad memory for stack allocated data. While statically allocating stack frames for individual functions...

  16. Benchmarking gate-based quantum computers

    Science.gov (United States)

    Michielsen, Kristel; Nocon, Madita; Willsch, Dennis; Jin, Fengping; Lippert, Thomas; De Raedt, Hans

    2017-11-01

    With the advent of public access to small gate-based quantum processors, it becomes necessary to develop a benchmarking methodology such that independent researchers can validate the operation of these processors. We explore the usefulness of a number of simple quantum circuits as benchmarks for gate-based quantum computing devices and show that circuits performing identity operations are very simple, scalable and sensitive to gate errors and are therefore very well suited for this task. We illustrate the procedure by presenting benchmark results for the IBM Quantum Experience, a cloud-based platform for gate-based quantum computing.

  17. Electrocardiographic gating in positron emission computed tomography

    International Nuclear Information System (INIS)

    Hoffman, E.J.; Phelps, M.E.; Wisenberg, G.; Schelbert, H.R.; Kuhl, D.E.

    1979-01-01

    Electrocardiographic (ECG) synchronized multiple gated data acquisition was employed with positron emission computed tomography (ECT) to obtain images of myocardial blood pool and myocardium. The feasibility and requirements of multiple gated data acquisition in positron ECT were investigated for 13NH3, ( 18 F)-2-fluoro-2-D-deoxyglucose, and ( 11 C)-carboxyhemoglobin. Examples are shown in which image detail is enhanced and image interpretation is facilitated when ECG gating is employed in the data collection. Analysis of count rate data from a series of volunteers indicates that multiple, statistically adequate images can be obtained under a multiple gated data collection format without an increase in administered dose

  18. Direct transitions from high-K isomers to low-K bands -- {gamma} softness or coriolis coupling

    Energy Technology Data Exchange (ETDEWEB)

    Shimizu, Yoshifumi R.; Narimatsu, Kanako; Ohtsubo, Shin-Ichi [Kyushu Univ., Fukuoka (Japan)] [and others

    1996-12-31

    Recent measurements of direct transitions from high-K isomers to low-K bands reveal severe break-down of the K-selection rule and pose the problem of how to understand the mechanism of such K-violation. The authors recent systematic calculations by using a simple {gamma}-tunneling model reproduced many of the observed hindrances, indicating the importance of the {gamma} softness. However, there are some data which cannot be explained in terms of the {gamma}-degree of freedom. In this talk, the authors also discuss the results of conventional Coriolis coupling calculations, which is considered to be another important mechanism.

  19. Engineering the propagation of high-k bulk plasmonic waves in multilayer hyperbolic metamaterials by multiscale structuring

    DEFF Research Database (Denmark)

    Zhukovsky, Sergei; Lavrinenko, Andrei; Sipe, J. E.

    2013-01-01

    , wavelength scale, the propagation of bulk plasmon polaritons in the resulting multiscale HMM is subject to photonic band gap phenomena. A great degree of control over such plasmons can be exerted by varying the superstructure geometry. As an example, Bragg reflection and Fabry-Pérot resonances...... are demonstrated in multiscale HMMs with periodic superstructures. More complicated, aperiodically ordered superstructures are also considered, with fractal Cantor-like multiscale HMMs exhibiting characteristic self-similar spectral signatures in the high-k band. The multiscale HMM concept is shown...

  20. Routes to a commercially viable PEM fuel cell stack

    Energy Technology Data Exchange (ETDEWEB)

    Newton, J.; Foster, S.E.; Hodgson, D.; Marrett, A.

    2002-07-01

    This report describes the results of a project to design and build a 10 kW{sub e} proton exchange membrane fuel cell (PEMFC) stack, including membrane electrode assemblies (MEAs), bipolar plates and stack hardware. The aim was to prove the design concept and to demonstrate functionality by operating the stack at >1 kW{sub e}/L and 500 W/kg for 200 hours operation. The project was extended to include the assembly and testing of two additional 1 kW{sub e} PEMFC stacks based on coated metal components. Low equivalent weight perfluorinated ionomer ion exchange membranes were prepared and were found to give a superior electrochemical performance to commercial materials. A technique to etch various stainless steel grades and control processes was successfully developed and optimised. Coatings for stainless steel and titanium were successfully developed and met the required performance criteria. All PEMFC stack components were selected and designed to enable subsequent commercial manufacture.

  1. Voltage-Gated Calcium Channels

    Science.gov (United States)

    Zamponi, Gerald Werner

    Voltage Gated Calcium Channels is the first comprehensive book in the calcium channel field, encompassing over thirty years of progress towards our understanding of calcium channel structure, function, regulation, physiology, pharmacology, and genetics. This book balances contributions from many of the leading authorities in the calcium channel field with fresh perspectives from risings stars in the area, taking into account the most recent literature and concepts. This is the only all-encompassing calcium channel book currently available, and is an essential resource for academic researchers at all levels in the areas neuroscience, biophysics, and cardiovascular sciences, as well as to researchers in the drug discovery area.

  2. Gate current for p+-poly PMOS devices under gate injection conditions

    NARCIS (Netherlands)

    Hof, A.J.; Holleman, J.; Woerlee, P.H.

    2001-01-01

    In current CMOS processing both n+-poly and p+-poly gates are used. The I-V –relationship and reliability of n+-poly devices are widely studied and well understood. Gate currents and reliability for p+-poly PMOS devices under gate injection conditions are not well understood. In this paper, the

  3. Reflector imaging by diffraction stacking with stacking velocity analysis; Jugo sokudo kaiseki wo tomonau sanran jugoho ni yoru hanshamen imaging

    Energy Technology Data Exchange (ETDEWEB)

    Matsushima, J; Rokugawa, S; Kato, Y [The University of Tokyo, Tokyo (Japan). Faculty of Engineering; Yokota, T [Japan National Oil Corp., Tokyo (Japan); Miyazaki, T [Geological Survey of Japan, Tsukuba (Japan)

    1997-10-22

    Concerning seismic reflection survey for geometrical arrangement between pits, the scattering stacking method with stacking velocity analysis is compared with the CDP (common depth point horizontal stacking method). The advantages of the CDP supposedly include the following. Since it presumes an average velocity field, it can determine velocities having stacking effects. The method presumes stratification and, since such enables the division of huge quantities of observed data into smaller groups, more data can be calculated in a shorter time period. The method has disadvantages, attributable to its presuming an average velocity field, that accuracy in processing is lower when the velocity field contrast is higher, that accuracy in processing is low unless stratification is employed, and that velocities obtained from stacking velocity analysis are affected by dipped structures. Such shortcomings may be remedied in the scattering stacking method with stacking velocity analysis. Possibilities are that, as far as the horizontal reflection plane is concerned, it may yield stack records higher in S/N ratio than the CDP. Findings relative to dipped reflection planes will be introduced at the presentation. 6 refs., 12 figs.

  4. Boolean gates on actin filaments

    International Nuclear Information System (INIS)

    Siccardi, Stefano; Tuszynski, Jack A.; Adamatzky, Andrew

    2016-01-01

    Actin is a globular protein which forms long polar filaments in the eukaryotic cytoskeleton. Actin networks play a key role in cell mechanics and cell motility. They have also been implicated in information transmission and processing, memory and learning in neuronal cells. The actin filaments have been shown to support propagation of voltage pulses. Here we apply a coupled nonlinear transmission line model of actin filaments to study interactions between voltage pulses. To represent digital information we assign a logical TRUTH value to the presence of a voltage pulse in a given location of the actin filament, and FALSE to the pulse's absence, so that information flows along the filament with pulse transmission. When two pulses, representing Boolean values of input variables, interact, then they can facilitate or inhibit further propagation of each other. We explore this phenomenon to construct Boolean logical gates and a one-bit half-adder with interacting voltage pulses. We discuss implications of these findings on cellular process and technological applications. - Highlights: • We simulate interaction between voltage pulses using on actin filaments. • We use a coupled nonlinear transmission line model. • We design Boolean logical gates via interactions between the voltage pulses. • We construct one-bit half-adder with interacting voltage pulses.

  5. Boolean gates on actin filaments

    Energy Technology Data Exchange (ETDEWEB)

    Siccardi, Stefano, E-mail: ssiccardi@2ssas.it [The Unconventional Computing Centre, University of the West of England, Bristol (United Kingdom); Tuszynski, Jack A., E-mail: jackt@ualberta.ca [Department of Oncology, University of Alberta, Edmonton, Alberta (Canada); Adamatzky, Andrew, E-mail: andrew.adamatzky@uwe.ac.uk [The Unconventional Computing Centre, University of the West of England, Bristol (United Kingdom)

    2016-01-08

    Actin is a globular protein which forms long polar filaments in the eukaryotic cytoskeleton. Actin networks play a key role in cell mechanics and cell motility. They have also been implicated in information transmission and processing, memory and learning in neuronal cells. The actin filaments have been shown to support propagation of voltage pulses. Here we apply a coupled nonlinear transmission line model of actin filaments to study interactions between voltage pulses. To represent digital information we assign a logical TRUTH value to the presence of a voltage pulse in a given location of the actin filament, and FALSE to the pulse's absence, so that information flows along the filament with pulse transmission. When two pulses, representing Boolean values of input variables, interact, then they can facilitate or inhibit further propagation of each other. We explore this phenomenon to construct Boolean logical gates and a one-bit half-adder with interacting voltage pulses. We discuss implications of these findings on cellular process and technological applications. - Highlights: • We simulate interaction between voltage pulses using on actin filaments. • We use a coupled nonlinear transmission line model. • We design Boolean logical gates via interactions between the voltage pulses. • We construct one-bit half-adder with interacting voltage pulses.

  6. Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

    International Nuclear Information System (INIS)

    Dakhel, A.A.; Jasim, Khalil E.; Cassidy, S.; Henari, F.Z.

    2013-01-01

    Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε ′ ∞ ≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z * (ω) and modulus M * (ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices

  7. SEMICONDUCTOR TECHNOLOGY: Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

    Science.gov (United States)

    Yongliang, Li; Qiuxia, Xu

    2010-03-01

    The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 °C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case.

  8. Extraction and dielectric properties of curcuminoid films grown on Si substrate for high-k dielectric applications

    Energy Technology Data Exchange (ETDEWEB)

    Dakhel, A.A.; Jasim, Khalil E. [Department of Physics, College of Science, University of Bahrain, P.O. Box 32038 (Bahrain); Cassidy, S. [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain); Henari, F.Z., E-mail: fzhenari@rcsi-mub.com [Department of Basic Medical Sciences, Royal College of Surgeons in Ireland, Medical University of Bahrain, P.O. Box 15503 (Bahrain)

    2013-09-20

    Highlights: • The unknown insulating properties of curcuminoid extract are systematically studied. • Optical study gives a bandgap of 3.15 eV and a refractive index of 1.92 at 505 nm. • Turmeric is a high-k environmental friendly material for use in microelectronics. • Curcuminoid extract can be used as insulator of MIS devices with ε{sup ′}{sub ∞}≈54.2. -- Abstract: Curcuminoids were extracted from turmeric powder and evaporated in vacuum to prepare thin films on p-Si and glass substrates for dielectric and optical investigations. The optical absorption spectrum of the prepared amorphous film was not identical to that of the molecular one, which was identified by a strong wide absorption band in between ∼220 and 540 nm. The onset energy of the optical absorption of the film was calculated by using Hamberg et al. method. The dielectric properties of this material were systematically studied for future eco friendly applications in metal–insulator–semiconductor MIS field of applications. The complex dielectric properties were studied in the frequency range of 1–1000 kHz and was analysed in-terms of dielectric impedance Z{sup *}(ω) and modulus M{sup *}(ω). Generally, the curcuminoid complex can be considered as a high-k material and can be used in the environmental friendly production of microelectronic devices.

  9. Wet etching characteristics of a HfSiON high-k dielectric in HF-based solutions

    International Nuclear Information System (INIS)

    Li Yongliang; Xu Qiuxia

    2010-01-01

    The wet etching properties of a HfSiON high-k dielectric in HF-based solutions are investigated. HF-based solutions are the most promising wet chemistries for the removal of HfSiON, and etch selectivity of HF-based solutions can be improved by the addition of an acid and/or an alcohol to the HF solution. Due to densification during annealing, the etch rate of HfSiON annealed at 900 0 C for 30 s is significantly reduced compared with as-deposited HfSiON in HF-based solutions. After the HfSiON film has been completely removed by HF-based solutions, it is not possible to etch the interfacial layer and the etched surface does not have a hydrophobic nature, since N diffuses to the interface layer or Si substrate formation of Si-N bonds that dissolves very slowly in HF-based solutions. Existing Si-N bonds at the interface between the new high-k dielectric deposit and the Si substrate may degrade the carrier mobility due to Coulomb scattering. In addition, we show that N 2 plasma treatment before wet etching is not very effective in increasing the wet etch rate for a thin HfSiON film in our case. (semiconductor technology)

  10. Long Duration Balloon Charge Controller Stack Integration

    Science.gov (United States)

    Clifford, Kyle

    NASA and the Columbia Scientific Balloon Facility are interested in updating the design of the charge controller on their long duration balloon (LDB) in order to enable the charge controllers to be directly interfaced via RS232 serial communication by a ground testing computers and the balloon's flight computer without the need to have an external electronics stack. The design involves creating a board that will interface with the existing boards in the charge controller in order to receive telemetry from and send commands to those boards, and interface with a computer through serial communication. The inputs to the board are digital status inputs indicating things like whether the photovoltaic panels are connected or disconnected; and analog inputs with information such as the battery voltage and temperature. The outputs of the board are 100ms duration command pulses that will switch relays that do things like connect the photovoltaic panels. The main component of this design is a PIC microcontroller which translates the outputs of the existing charge controller into serial data when interrogated by a ground testing or flight computer. Other components involved in the design are an AD7888 12-bit analog to digital converter, a MAX3232 serial transceiver, various other ICs, capacitors, resistors, and connectors.

  11. Black Hole Spectroscopy with Coherent Mode Stacking.

    Science.gov (United States)

    Yang, Huan; Yagi, Kent; Blackman, Jonathan; Lehner, Luis; Paschalidis, Vasileios; Pretorius, Frans; Yunes, Nicolás

    2017-04-21

    The measurement of multiple ringdown modes in gravitational waves from binary black hole mergers will allow for testing the fundamental properties of black holes in general relativity and to constrain modified theories of gravity. To enhance the ability of Advanced LIGO/Virgo to perform such tasks, we propose a coherent mode stacking method to search for a chosen target mode within a collection of multiple merger events. We first rescale each signal so that the target mode in each of them has the same frequency and then sum the waveforms constructively. A crucial element to realize this coherent superposition is to make use of a priori information extracted from the inspiral-merger phase of each event. To illustrate the method, we perform a study with simulated events targeting the ℓ=m=3 ringdown mode of the remnant black holes. We show that this method can significantly boost the signal-to-noise ratio of the collective target mode compared to that of the single loudest event. Using current estimates of merger rates, we show that it is likely that advanced-era detectors can measure this collective ringdown mode with one year of coincident data gathered at design sensitivity.

  12. ATLAS software stack on ARM64

    CERN Document Server

    Smith, Joshua Wyatt; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment explores new hardware and software platforms that, in the future, may be more suited to its data intensive workloads. One such alternative hardware platform is the ARM architecture, which is designed to be extremely power efficient and is found in most smartphones and tablets. CERN openlab recently installed a small cluster of ARM 64-bit evaluation prototype servers. Each server is based on a single-socket ARM 64-bit system on a chip, with 32 Cortex-A57 cores. In total, each server has 128 GB RAM connected with four fast memory channels. This paper reports on the port of the ATLAS software stack onto these new prototype ARM64 servers. This included building the "external" packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adj...

  13. Testing system for a fuel cells stack

    International Nuclear Information System (INIS)

    Culcer, Mihai; Iliescu, Mariana; Stefanescu, Ioan; Raceanu, Mircea; Enache, Adrian; Lazar, Roxana Elena

    2006-01-01

    Hydrogen and electricity together represent one of the most promising ways to realize sustainable energy, whilst fuel cells provide the most efficient conversion devices for converting hydrogen and possibly other fuels into electricity. Thus, the development of fuel cell technology is currently being actively pursued worldwide. Due to its simple operation and other fair characteristics, the Proton Exchange Membrane Fuel Cell (PEMFC) is especially suitable as a replacement for the internal combustion engine. The PEMFC is also being developed for decentralized electricity and heat generation in buildings and mobile applications. Starting with 2001 the Institute of Research - Development for Cryogenics and Isotopic Technologies - ICIT - Rm. Valcea developed research activities supported by the Romanian Ministry of Education and Research within the National Research Program in order to bridge the gap to European competencies in the area of hydrogen and fuel cells. The paper deals with the testing system designed and developed in ICIT Rm. Valcea as a flexible and versatile tool allowing a large scale of parameter settings and measurements on a single cell or on a fuel cells stack onto a wind range of output power values. (authors)

  14. Weyl magnons in noncoplanar stacked kagome antiferromagnets

    Science.gov (United States)

    Owerre, S. A.

    2018-03-01

    Weyl nodes have been experimentally realized in photonic, electronic, and phononic crystals. However, magnonic Weyl nodes are yet to be seen experimentally. In this paper, we propose Weyl magnon nodes in noncoplanar stacked frustrated kagome antiferromagnets, naturally available in various real materials. Most crucially, the Weyl nodes in the current system occur at the lowest excitation and possess a topological thermal Hall effect, therefore they are experimentally accessible at low temperatures due to the population effect of bosonic quasiparticles. In stark contrast to other magnetic systems, the current Weyl nodes do not rely on time-reversal symmetry breaking by the magnetic order. Rather, they result from explicit macroscopically broken time reversal symmetry by the scalar spin chirality of noncoplanar spin textures and can be generalized to chiral spin liquid states. Moreover, the scalar spin chirality gives a real space Berry curvature which is not available in previously studied magnetic Weyl systems. We show the existence of magnon arc surface states connecting projected Weyl magnon nodes on the surface Brillouin zone. We also uncover the first realization of triply-degenerate nodal magnon point in the noncollinear regime with zero scalar spin chirality.

  15. Lithiation-induced shuffling of atomic stacks

    KAUST Repository

    Nie, Anmin

    2014-09-10

    In rechargeable lithium-ion batteries, understanding the atomic-scale mechanism of Li-induced structural evolution occurring at the host electrode materials provides essential knowledge for design of new high performance electrodes. Here, we report a new crystalline-crystalline phase transition mechanism in single-crystal Zn-Sb intermetallic nanowires upon lithiation. Using in situ transmission electron microscopy, we observed that stacks of atomic planes in an intermediate hexagonal (h-)LiZnSb phase are "shuffled" to accommodate the geometrical confinement stress arising from lamellar nanodomains intercalated by lithium ions. Such atomic rearrangement arises from the anisotropic lithium diffusion and is accompanied by appearance of partial dislocations. This transient structure mediates further phase transition from h-LiZnSb to cubic (c-)Li2ZnSb, which is associated with a nearly "zero-strain" coherent interface viewed along the [001]h/[111]c directions. This study provides new mechanistic insights into complex electrochemically driven crystalline-crystalline phase transitions in lithium-ion battery electrodes and represents a noble example of atomic-level structural and interfacial rearrangements.

  16. Captioning Transformer with Stacked Attention Modules

    Directory of Open Access Journals (Sweden)

    Xinxin Zhu

    2018-05-01

    Full Text Available Image captioning is a challenging task. Meanwhile, it is important for the machine to understand the meaning of an image better. In recent years, the image captioning usually use the long-short-term-memory (LSTM as the decoder to generate the sentence, and these models show excellent performance. Although the LSTM can memorize dependencies, the LSTM structure has complicated and inherently sequential across time problems. To address these issues, recent works have shown benefits of the Transformer for machine translation. Inspired by their success, we develop a Captioning Transformer (CT model with stacked attention modules. We attempt to introduce the Transformer to the image captioning task. The CT model contains only attention modules without the dependencies of the time. It not only can memorize dependencies between the sequence but also can be trained in parallel. Moreover, we propose the multi-level supervision to make the Transformer achieve better performance. Extensive experiments are carried out on the challenging MSCOCO dataset and the proposed Captioning Transformer achieves competitive performance compared with some state-of-the-art methods.

  17. Protected gates for topological quantum field theories

    International Nuclear Information System (INIS)

    Beverland, Michael E.; Pastawski, Fernando; Preskill, John; Buerschaper, Oliver; Koenig, Robert; Sijher, Sumit

    2016-01-01

    We study restrictions on locality-preserving unitary logical gates for topological quantum codes in two spatial dimensions. A locality-preserving operation is one which maps local operators to local operators — for example, a constant-depth quantum circuit of geometrically local gates, or evolution for a constant time governed by a geometrically local bounded-strength Hamiltonian. Locality-preserving logical gates of topological codes are intrinsically fault tolerant because spatially localized errors remain localized, and hence sufficiently dilute errors remain correctable. By invoking general properties of two-dimensional topological field theories, we find that the locality-preserving logical gates are severely limited for codes which admit non-abelian anyons, in particular, there are no locality-preserving logical gates on the torus or the sphere with M punctures if the braiding of anyons is computationally universal. Furthermore, for Ising anyons on the M-punctured sphere, locality-preserving gates must be elements of the logical Pauli group. We derive these results by relating logical gates of a topological code to automorphisms of the Verlinde algebra of the corresponding anyon model, and by requiring the logical gates to be compatible with basis changes in the logical Hilbert space arising from local F-moves and the mapping class group

  18. Gates Auto Door Car With Lights Modulated

    OpenAIRE

    Lina Carolina; Luyung Dinani, Skom, MMSi

    2002-01-01

    In scientific writing wi ll be explained about automatic gates with modulated headlights, where to find the car lights were adjusted by the relative frequency darker because of this background that the author alleviate human task in performing daily activities by using an automatic gate with the car lights modulated.

  19. Automatically closing swing gate closure assembly

    Science.gov (United States)

    Chang, Shih-Chih; Schuck, William J.; Gilmore, Richard F.

    1988-01-01

    A swing gate closure assembly for nuclear reactor tipoff assembly wherein the swing gate is cammed open by a fuel element or spacer but is reliably closed at a desired closing rate primarily by hydraulic forces in the absence of a fuel charge.

  20. Efficiency of Polymer Electrolyte Membrane Fuel Cell Stack

    Directory of Open Access Journals (Sweden)

    Hans Bosma

    2011-08-01

    Full Text Available This paper applies a feedforward control of optimal oxygen excess ratio that maximize net power (improve efficiency of a NedStack P8.0-64 PEM fuel cell stack (FCS system. Net powers profile as a function of oxygen excess ratio for some points of operation are analyzed by using FCS model. The relationships between stack current and the corresponding control input voltage that gives an optimal oxygen excess ratio are used to design a feedforward control scheme. The results of this scheme are compared to the results of a feedforward control using a constant oxygen excess ratio. Simulation results show that optimal oxygen excess ratio improves fuel cell performance compared to the results of constant oxygen excess ratio. The same procedures are performed experimentally for the FCS system. The behaviour of the net power of the fuel cell stack with respect to the variation of oxygen excess ratio is analyzed to obtain optimal values. Data of stack current and the corresponding voltage input to the compressor that gives optimal values of oxygen excess ratio are used to develop a feedforward control. Feedforward control based on constant and optimal oxygen excess ratio control, are implemented in the NedStack P8.0-64 PEM fuel cell stack system by using LabVIEW. Implementation results shows that optimal oxygen excess ratio control improves the fuel cell performance compared to the constant oxygen excess ratio control.

  1. Reliability analysis and initial requirements for FC systems and stacks

    Science.gov (United States)

    Åström, K.; Fontell, E.; Virtanen, S.

    In the year 2000 Wärtsilä Corporation started an R&D program to develop SOFC systems for CHP applications. The program aims to bring to the market highly efficient, clean and cost competitive fuel cell systems with rated power output in the range of 50-250 kW for distributed generation and marine applications. In the program Wärtsilä focuses on system integration and development. System reliability and availability are key issues determining the competitiveness of the SOFC technology. In Wärtsilä, methods have been implemented for analysing the system in respect to reliability and safety as well as for defining reliability requirements for system components. A fault tree representation is used as the basis for reliability prediction analysis. A dynamic simulation technique has been developed to allow for non-static properties in the fault tree logic modelling. Special emphasis has been placed on reliability analysis of the fuel cell stacks in the system. A method for assessing reliability and critical failure predictability requirements for fuel cell stacks in a system consisting of several stacks has been developed. The method is based on a qualitative model of the stack configuration where each stack can be in a functional, partially failed or critically failed state, each of the states having different failure rates and effects on the system behaviour. The main purpose of the method is to understand the effect of stack reliability, critical failure predictability and operating strategy on the system reliability and availability. An example configuration, consisting of 5 × 5 stacks (series of 5 sets of 5 parallel stacks) is analysed in respect to stack reliability requirements as a function of predictability of critical failures and Weibull shape factor of failure rate distributions.

  2. Dual-Gate p-GaN Gate High Electron Mobility Transistors for Steep Subthreshold Slope.

    Science.gov (United States)

    Bae, Jong-Ho; Lee, Jong-Ho

    2016-05-01

    A steep subthreshold slope characteristic is achieved through p-GaN gate HEMT with dual-gate structure. Obtained subthreshold slope is less than 120 μV/dec. Based on the measured and simulated data obtained from single-gate device, breakdown of parasitic floating-base bipolar transistor and floating gate charged with holes are responsible to increase abruptly in drain current. In the dual-gate device, on-current degrades with high temperature but subthreshold slope is not changed. To observe the switching speed of dual-gate device and transient response of drain current are measured. According to the transient responses of drain current, switching speed of the dual-gate device is about 10(-5) sec.

  3. Top-gate pentacene-based organic field-effect transistor with amorphous rubrene gate insulator

    Science.gov (United States)

    Hiroki, Mizuha; Maeda, Yasutaka; Ohmi, Shun-ichiro

    2018-02-01

    The scaling of organic field-effect transistors (OFETs) is necessary for high-density integration and for this, OFETs with a top-gate configuration are required. There have been several reports of damageless lithography processes for organic semiconductor or insulator layers. However, it is still difficult to fabricate scaled OFETs with a top-gate configuration. In this study, the lift-off process and the device characteristics of the OFETs with a top-gate configuration utilizing an amorphous (α) rubrene gate insulator were investigated. We have confirmed that α-rubrene shows an insulating property, and its extracted linear mobility was 2.5 × 10-2 cm2/(V·s). The gate length and width were 10 and 60 µm, respectively. From these results, the OFET with a top-gate configuration utilizing an α-rubrene gate insulator is promising for the high-density integration of scaled OFETs.

  4. Precise linear gating circuit on integrated microcircuits

    Energy Technology Data Exchange (ETDEWEB)

    Butskii, V.V.; Vetokhin, S.S.; Reznikov, I.V.

    Precise linear gating circuit on four microcircuits is described. A basic flowsheet of the gating circuit is given. The gating circuit consists of two input differential cascades total load of which is two current followers possessing low input and high output resistances. Follower outlets are connected to high ohmic dynamic load formed with a current source which permits to get high amplification (>1000) at one cascade. Nonlinearity amounts to <0.1% in the range of input signal amplitudes of -10-+10 V. Front duration for an output signal with 10 V amplitude amounts to 100 ns. Attenuation of input signal with a closed gating circuit is 60 db. The gating circuits described is used in the device intended for processing of scintillation sensor signals.

  5. Mixed Mechanism of Lubrication by Lipid Bilayer Stacks.

    Science.gov (United States)

    Boţan, Alexandru; Joly, Laurent; Fillot, Nicolas; Loison, Claire

    2015-11-10

    Although the key role of lipid bilayer stacks in biological lubrication is generally accepted, the mechanisms underlying their extreme efficiency remain elusive. In this article, we report molecular dynamics simulations of lipid bilayer stacks undergoing load and shear. When the hydration level is reduced, the velocity accommodation mechanism changes from viscous shear in hydration water to interlayer sliding in the bilayers. This enables stacks of hydrated lipid bilayers to act as efficient boundary lubricants for various hydration conditions, structures, and mechanical loads. We also propose an estimation for the friction coefficient; thanks to the strong hydration forces between lipid bilayers, the high local viscosity is not in contradiction with low friction coefficients.

  6. Fabrication of high gradient insulators by stack compression

    Science.gov (United States)

    Harris, John Richardson; Sanders, Dave; Hawkins, Steven Anthony; Norona, Marcelo

    2014-04-29

    Individual layers of a high gradient insulator (HGI) are first pre-cut to their final dimensions. The pre-cut layers are then stacked to form an assembly that is subsequently pressed into an HGI unit with the desired dimension. The individual layers are stacked, and alignment is maintained, using a sacrificial alignment tube that is removed after the stack is hot pressed. The HGI's are used as high voltage vacuum insulators in energy storage and transmission structures or devices, e.g. in particle accelerators and pulsed power systems.

  7. Study and Development of an OpenStack solution

    OpenAIRE

    Jorba Brosa, Maria

    2014-01-01

    Estudi i desenvolupament d'una solució de virtualització amb Openstack. Es farà un especial èmfasi en la part de seguretat. Deployment of a solution based in OpenStack for the creation of an Infrastructure service cloud. Implementación de una solución basada en OpenStack para la creación de una infrastructura de servicios cloud. Implementació d'una solució basada en OpenStack per la creació d'una infrastructura de serveis cloud.

  8. Loop Entropy Assists Tertiary Order: Loopy Stabilization of Stacking Motifs

    Directory of Open Access Journals (Sweden)

    Daniel P. Aalberts

    2011-11-01

    Full Text Available The free energy of an RNA fold is a combination of favorable base pairing and stacking interactions competing with entropic costs of forming loops. Here we show how loop entropy, surprisingly, can promote tertiary order. A general formula for the free energy of forming multibranch and other RNA loops is derived with a polymer-physics based theory. We also derive a formula for the free energy of coaxial stacking in the context of a loop. Simulations support the analytic formulas. The effects of stacking of unpaired bases are also studied with simulations.

  9. Consolidity: Stack-based systems change pathway theory elaborated

    Directory of Open Access Journals (Sweden)

    Hassen Taher Dorrah

    2014-06-01

    Full Text Available This paper presents an elaborated analysis for investigating the stack-based layering processes during the systems change pathway. The system change pathway is defined as the path resulting from the combinations of all successive changes induced on the system when subjected to varying environments, activities, events, or any excessive internal or external influences and happenings “on and above” its normal stands, situations or set-points during its course of life. The analysis is essentially based on the important overall system paradigm of “Time driven-event driven-parameters change”. Based on this paradigm, it is considered that any affected activity, event or varying environment is intelligently self-recorded inside the system through an incremental consolidity-scaled change in system parameters of the stack-based layering types. Various joint stack-based mathematical and graphical approaches supported by representable case studies are suggested for the identification, extraction, and processing of various stack-based systems changes layering of different classifications and categorizations. Moreover, some selected real life illustrative applications are provided to demonstrate the (infinite stack-based identification and recognition of the change pathway process in the areas of geology, archeology, life sciences, ecology, environmental science, engineering, materials, medicine, biology, sociology, humanities, and other important fields. These case studies and selected applications revealed that there are general similarities of the stack-based layering structures and formations among all the various research fields. Such general similarities clearly demonstrate the global concept of the “fractals-general stacking behavior” of real life systems during their change pathways. Therefore, it is recommended that concentrated efforts should be expedited toward building generic modular stack-based systems or blocks for the mathematical

  10. Static analysis of worst-case stack cache behavior

    DEFF Research Database (Denmark)

    Jordan, Alexander; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    Utilizing a stack cache in a real-time system can aid predictability by avoiding interference that heap memory traffic causes on the data cache. While loads and stores are guaranteed cache hits, explicit operations are responsible for managing the stack cache. The behavior of these operations can......-graph, the worst-case bounds can be efficiently yet precisely determined. Our evaluation using the MiBench benchmark suite shows that only 37% and 21% of potential stack cache operations actually store to and load from memory, respectively. Analysis times are modest, on average running between 0.46s and 1.30s per...

  11. Full Piezoelectric Multilayer-Stacked Hybrid Actuation/Transduction Systems

    Science.gov (United States)

    Su, Ji; Jiang, Xiaoning; Zu, Tian-Bing

    2011-01-01

    The Stacked HYBATS (Hybrid Actuation/Transduction system) demonstrates significantly enhanced electromechanical performance by using the cooperative contributions of the electromechanical responses of multilayer, stacked negative strain components and positive strain components. Both experimental and theoretical studies indicate that, for Stacked HYBATS, the displacement is over three times that of a same-sized conventional flextensional actuator/transducer. The coupled resonance mode between positive strain and negative strain components of Stacked HYBATS is much stronger than the resonance of a single element actuation only when the effective lengths of the two kinds of elements match each other. Compared with the previously invented hybrid actuation system (HYBAS), the multilayer Stacked HYBATS can be designed to provide high mechanical load capability, low voltage driving, and a highly effective piezoelectric constant. The negative strain component will contract, and the positive strain component will expand in the length directions when an electric field is applied on the device. The interaction between the two elements makes an enhanced motion along the Z direction for Stacked-HYBATS. In order to dominate the dynamic length of Stacked-HYBATS by the negative strain component, the area of the cross-section for the negative strain component will be much larger than the total cross-section areas of the two positive strain components. The transverse strain is negative and longitudinal strain positive in inorganic materials, such as ceramics/single crystals. Different piezoelectric multilayer stack configurations can make a piezoelectric ceramic/single-crystal multilayer stack exhibit negative strain or positive strain at a certain direction without increasing the applied voltage. The difference of this innovation from the HYBAS is that all the elements can be made from one-of-a-kind materials. Stacked HYBATS can provide an extremely effective piezoelectric

  12. Fuel flow distribution in SOFC stacks revealed by impedance spectroscopy

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, Rasmus

    2014-01-01

    As SOFC technology is moving closer to a commercial break through, methods to measure the “state-of-health” of operating stacks are becoming of increasing interest. This requires application of advanced methods for detailed electrical and electrochemical characterization during operation. An oper......As SOFC technology is moving closer to a commercial break through, methods to measure the “state-of-health” of operating stacks are becoming of increasing interest. This requires application of advanced methods for detailed electrical and electrochemical characterization during operation...... utilizations. The fuel flow distribution provides important information about the operating limits of the stack when high electrical efficiency is required....

  13. Stacking by electroinjection with discontinuous buffers in capillary zone electrophoresis.

    Science.gov (United States)

    Shihabi, Zak K

    2002-08-01

    The work presented here demonstrates that electroinjection can be performed using discontinuous buffers, which can result in better stacking than that obtained by hydrodynamic injection. The sample can be concentrated at the tip of the capillary leaving practically the whole capillary for sample separation. This results in several advantages, such as better sample concentration, higher plate number and shorter time of stacking. However, sample introduction by electromigration is suited for samples free or low in salt content. Samples, which are high in salt content, are better introduced by the hydrodynamic injection for stacking by the discontinuous buffers. Different simple methods to introduce the discontinuity in the buffer for electroinjection are discussed.

  14. Production and Reliability Oriented SOFC Cell and Stack Design

    DEFF Research Database (Denmark)

    Hauth, Martin; Lawlor, Vincent; Cartellieri, Peter

    2017-01-01

    The paper presents an innovative development methodology for a production and reliability oriented SOFC cell and stack design aiming at improving the stacks robustness, manufacturability, efficiency and cost. Multi-physics models allowed a probabilistic approach to consider statistical variations...... in production, material and operating parameters for the optimization phase. A methodology for 3D description of spatial distribution of material properties based on a random field models was developed and validated by experiments. Homogenized material models on multiple levels of the SOFC stack were...... and output parameters and to perform a sensitivity analysis were developed and implemented. The capabilities of the methodology is illustrated on two practical cases....

  15. Calculation of AC losses in large HTS stacks and coils

    DEFF Research Database (Denmark)

    Zermeno, Victor; Abrahamsen, Asger Bech; Mijatovic, Nenad

    2012-01-01

    In this work, we present a homogenization method to model a stack of HTS tapes under AC applied transport current or magnetic field. The idea is to find an anisotropic bulk equivalent for the stack of tapes, where the internal alternating structures of insulating, metallic, superconducting...... allowing for overcritical current densities to be considered. The method presented here allowed for a computational speedup factor of up to 2 orders of magnitude when compared to full 2-D simulations taking into account the actual structure of the stacks without compromising accuracy....

  16. Optimized stacked RADFETs for milli-rad dose measurement

    International Nuclear Information System (INIS)

    O'Connell, B.; Lane, B.; Mohammadzadeh, A.

    1999-01-01

    This paper details the improvements in the design of stacked RADFETs for increased radiation sensitivity. The issues of high read-out voltage has been shown to be a draw-back. It is the body (bulk)effect factor that is responsible for the increased overall stack Threshold voltage (V T ), which is greater than the sum of the individual devices V T . From extensive process and device simulation and resultant circuit simulation, modified stack structures have been proposed and designed. New and exciting result of lower initial (pre-irradiation) output voltage as well as increased radiation sensitivity will be presented. (author)

  17. Ablation of film stacks in solar cell fabrication processes

    Science.gov (United States)

    Harley, Gabriel; Kim, Taeseok; Cousins, Peter John

    2013-04-02

    A dielectric film stack of a solar cell is ablated using a laser. The dielectric film stack includes a layer that is absorptive in a wavelength of operation of the laser source. The laser source, which fires laser pulses at a pulse repetition rate, is configured to ablate the film stack to expose an underlying layer of material. The laser source may be configured to fire a burst of two laser pulses or a single temporally asymmetric laser pulse within a single pulse repetition to achieve complete ablation in a single step.

  18. High-K precession modes: Axially symmetric limit of wobbling motion in the cranked random-phase approximation description

    International Nuclear Information System (INIS)

    Shimizu, Yoshifumi R.; Matsuzaki, Masayuki; Matsuyanagi, Kenichi

    2005-01-01

    The rotational band built on the high-K multi-quasiparticle state can be interpreted as a multi-phonon band of the precession mode, which represents the precessional rotation about the axis perpendicular to the direction of the intrinsic angular momentum. By using the axially symmetric limit of the random-phase approximation (RPA) formalism developed for the nuclear wobbling motion, we study the properties of the precession modes in 178 W: the excitation energies, B(E2) and B(M1) values. We show that the excitations of such a specific type of rotation can be well described by the RPA formalism, which gives new insight into the wobbling motion in the triaxial superdeformed nuclei from a microscopic viewpoint

  19. Precession mode on high-K configurations: non-collective axially-symmetric limit of wobbling motion

    International Nuclear Information System (INIS)

    Shimizu, Yoshifumi R; Matsuzaki, Masayuki; Matsuyanagi, Kenichi

    2006-01-01

    The precession mode, the rotational excitation built on the high-K isomeric state, in comparison with the recently identified wobbling mode has been studied. The random-phase-approximation (RPA) formalism, which has been developed for the nuclear wobbling motion, is invoked and the precession phonon is obtained by the non-collective axially symmetric limit of the formalism. The excitation energies and the electromagnetic properties of the precession bands in 178 W are calculated, and it is found that the results of RPA calculations well correspond to those of the rotor model; the correspondence can be understood by an adiabatic approximation to the RPA phonon. As a by-product, it is also found that the problem of too small out-of-band B(E2) in our previous RPA wobbling calculations can be solved by a suitable choice of the triaxial deformation which corresponds to the one used in the rotor model

  20. Comprehensive Study of Lanthanum Aluminate High-Dielectric-Constant Gate Oxides for Advanced CMOS Devices

    Directory of Open Access Journals (Sweden)

    Masamichi Suzuki

    2012-03-01

    Full Text Available A comprehensive study of the electrical and physical characteristics of Lanthanum Aluminate (LaAlO3 high-dielectric-constant gate oxides for advanced CMOS devices was performed. The most distinctive feature of LaAlO3 as compared with Hf-based high-k materials is the thermal stability at the interface with Si, which suppresses the formation of a low-permittivity Si oxide interfacial layer. Careful selection of the film deposition conditions has enabled successful deposition of an LaAlO3 gate dielectric film with an equivalent oxide thickness (EOT of 0.31 nm. Direct contact with Si has been revealed to cause significant tensile strain to the Si in the interface region. The high stability of the effective work function with respect to the annealing conditions has been demonstrated through comparison with Hf-based dielectrics. It has also been shown that the effective work function can be tuned over a wide range by controlling the La/(La + Al atomic ratio. In addition, gate-first n-MOSFETs with ultrathin EOT that use sulfur-implanted Schottky source/drain technology have been fabricated using a low-temperature process.

  1. Stacking dependence of carrier transport properties in multilayered black phosphorous

    Science.gov (United States)

    Sengupta, A.; Audiffred, M.; Heine, T.; Niehaus, T. A.

    2016-02-01

    We present the effect of different stacking orders on carrier transport properties of multi-layer black phosphorous. We consider three different stacking orders AAA, ABA and ACA, with increasing number of layers (from 2 to 6 layers). We employ a hierarchical approach in density functional theory (DFT), with structural simulations performed with generalized gradient approximation (GGA) and the bandstructure, carrier effective masses and optical properties evaluated with the meta-generalized gradient approximation (MGGA). The carrier transmission in the various black phosphorous sheets was carried out with the non-equilibrium green’s function (NEGF) approach. The results show that ACA stacking has the highest electron and hole transmission probabilities. The results show tunability for a wide range of band-gaps, carrier effective masses and transmission with a great promise for lattice engineering (stacking order and layers) in black phosphorous.

  2. Fast principal component analysis for stacking seismic data

    Science.gov (United States)

    Wu, Juan; Bai, Min

    2018-04-01

    Stacking seismic data plays an indispensable role in many steps of the seismic data processing and imaging workflow. Optimal stacking of seismic data can help mitigate seismic noise and enhance the principal components to a great extent. Traditional average-based seismic stacking methods cannot obtain optimal performance when the ambient noise is extremely strong. We propose a principal component analysis (PCA) algorithm for stacking seismic data without being sensitive to noise level. Considering the computational bottleneck of the classic PCA algorithm in processing massive seismic data, we propose an efficient PCA algorithm to make the proposed method readily applicable for industrial applications. Two numerically designed examples and one real seismic data are used to demonstrate the performance of the presented method.

  3. Sample Stacking in capillary zone electrophoresis : Principles, advantages and limitations

    NARCIS (Netherlands)

    Beckers, J.L.; Bocek, P.

    2000-01-01

    The principles of stacking procedures are described and their properties are discussed, including the fundamentals of the behavior of zone boundaries and the consequences of the self-correcting properties of boundaries in moving boundary electrophoresis, isotachophoresis, and zone electrophoresis.

  4. DBaaS with OpenStack Trove

    CERN Document Server

    Giardini, Andrea

    2013-01-01

    The purpose of the project was to evaluate the Trove component for OpenStack, understand if it can be used with the CERN infrastructure and report the benefits and disadvantages of this software. Currently, databases for CERN projects are provided by a DbaaS software developed inside the IT-DB group. This solution works well with the actual infrastructure but it is not easy to maintain. With the migration of the CERN infrastructure to OpenStack the Database group started to evaluate the Trove component. Instead of mantaining an own DbaaS service it can be interesting to migrate everything to OpenStack and replace the actual DbaaS software with Trove. This way both virtual machines and databases will be managed by OpenStack itself.

  5. Development and preliminary experimental study on micro-stacked insulator

    International Nuclear Information System (INIS)

    Ren Chengyan; Yuan Weiqun; Zhang Dongdong; Yan Ping; Wang Jue

    2009-01-01

    High gradient insulating technology is one of the key technologies in new type dielectric wall accelerator(DWA). High gradient insulator, namely micro-stacked insulator, was developed and preliminary experimental study was done. Based on the finite element and particle simulating method, surface electric field distribution and electron movement track of micro-stacked insulator were numerated, and then the optimized design proposal was put forward. Using high temperature laminated method, we developed micro-stacked insulator samples which uses exhaustive fluorinated ethylene propylene(FEP) as dielectric layer and stainless steel as metal layer. Preliminary experiment of vacuum surface flashover in nanosecond pulse voltage was done and micro-stacked insulator exhibited favorable vacuum surface flashover performance with flashover field strength of near 180 kV/cm. (authors)

  6. Simulation of magnetization and levitation characteristics of HTS tape stacks

    Science.gov (United States)

    Anischenko, I. V.; Pokrovskii, S. V.; Mineev, N. A.

    2017-12-01

    In this work it is presented a computational model of a magnetic levitation system based on stacks of high-temperature second generation superconducting tapes (HTS) GdBa2Cu3O7-x. Calculated magnetic field and the current distributions in the system for different stacks geometries in the zero-field cooling mode are also presented. The magnetization curves of the stacks in the external field of a permanent NdFeB magnet and the levitation force dependence on the gap between the magnet and the HTS tapes stack were obtained. A model of the magnetic system, oriented to levitation application, is given. Results of modeling were compared with the experimental data.

  7. Sport stacking activities in school children's motor skill development.

    Science.gov (United States)

    Li, Yuhua; Coleman, Diane; Ransdell, Mary; Coleman, Lyndsie; Irwin, Carol

    2011-10-01

    This study examined the impact of a 12-wk. sport stacking intervention on reaction time (RT), manual dexterity, and hand-eye coordination in elementary school-aged children. 80 Grade 2 students participated in a 15-min. sport stacking practice session every school day for 12 wk., and were tested on psychomotor performance improvement. Tests for choice RT, manual dexterity, and photoelectric rotary pursuit tracking were conducted pre- and post-intervention for both experimental group (n = 36) and the controls (n = 44) who did no sport stacking. Students who had the intervention showed a greater improvement in two-choice RT. No other group difference was found. Such sport stacking activities may facilitate children's central processing and perceptual-motor integration.

  8. Stacking faults and microstructural parameters in non-mulberry silk ...

    Indian Academy of Sciences (India)

    rameters like crystal size (〈N〉), lattice strain (g) and stacking faults in polymer materials ... metal oxide compounds, but may be inadequate for describing diffraction patterns .... Further, with these model parameters for individual Bragg reflec-.

  9. Fabrication of amorphous InGaZnO thin-film transistor with solution processed SrZrO3 gate insulator

    Science.gov (United States)

    Takahashi, Takanori; Oikawa, Kento; Hoga, Takeshi; Uraoka, Yukiharu; Uchiyama, Kiyoshi

    2017-10-01

    In this paper, we describe a method of fabrication of thin film transistors (TFTs) with high dielectric constant (high-k) gate insulator by a solution deposition. We chose a solution processed SrZrO3 as a gate insulator material, which possesses a high dielectric constant of 21 with smooth surface. The IGZO-TFT with solution processed SrZrO3 showed good switching property and enough saturation features, i.e. field effect mobility of 1.7cm2/Vs, threshold voltage of 4.8V, sub-threshold swing of 147mV/decade, and on/off ratio of 2.3×107. Comparing to the TFTs with conventional SiO2 gate insulator, the sub-threshold swing was improved by smooth surface and high field effect due to the high dielectric constant of SrZrO3. These results clearly showed that use of solution processed high-k SrZrO3 gate insulator could improve sub-threshold swing. In addition, the residual carbon originated from organic precursors makes TFT performances degraded.

  10. Heuristic Solution Approaches to the Double TSP with Multiple Stacks

    DEFF Research Database (Denmark)

    Petersen, Hanne Løhmann

    This paper introduces the Double Travelling Salesman Problem with Multiple Stacks and presents a three different metaheuristic approaches to its solution. The Double Travelling Salesman Problem with Multiple Stacks is concerned with finding the shortest route performing pickups and deliveries in ...... are developed for the problem and used with each of the heuristics. Finally some computational results are given along with lower bounds on the objective value....

  11. Heuristic Solution Approaches to the Double TSP with Multiple Stacks

    DEFF Research Database (Denmark)

    Petersen, Hanne Løhmann

    2006-01-01

    This paper introduces the Double Travelling Salesman Problem with Multiple Stacks and presents a three different metaheuristic approaches to its solution. The Double Travelling Salesman Problem with Multiple Stacks is concerned with finding the shortest route performing pickups and deliveries in ...... are developed for the problem and used with each of the heuristics. Finally some computational results are given along with lower bounds on the objective value....

  12. Modeling of a Stacked Power Module for Parasitic Inductance Extraction

    Science.gov (United States)

    2017-09-15

    ARL-TR-8138 ● SEP 2017 US Army Research Laboratory Modeling of a Stacked Power Module for Parasitic Inductance Extraction by...not return it to the originator. ARL-TR-8138 ● SEP 2017 US Army Research Laboratory Modeling of a Stacked Power Module for... Power Module for Parasitic Inductance Extraction 5a. CONTRACT NUMBER 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 6. AUTHOR(S) Steven Kaplan

  13. Field-induced stacking transition of biofunctionalized trilayer graphene

    Energy Technology Data Exchange (ETDEWEB)

    Masato Nakano, C. [Flintridge Preparatory School, La Canada, California 91011 (United States); Sajib, Md Symon Jahan; Samieegohar, Mohammadreza; Wei, Tao [Dan F. Smith Department of Chemical Engineering, Lamar University, Beaumont, Texas 77710 (United States)

    2016-02-01

    Trilayer graphene (TLG) is attracting a lot of attention as their stacking structures (i.e., rhombohedral vs. Bernal) drastically affect electronic and optical properties. Based on full-atom molecular dynamics simulations, we here predict electric field-induced rhombohedral-to-Bernal transition of TLG tethered with proteins. Furthermore, our simulations show that protein's electrophoretic mobility and diffusivity are enhanced on TLG surface. This phenomenon of controllable TLG stacking transition will contribute to various applications including biosensing.

  14. Reexamination of the ISABELLE box car stacking scheme

    International Nuclear Information System (INIS)

    Chasman, R.

    1975-01-01

    Box car stacking of ISABELLE after acceleration of the fundamental frequency in the AGS is reviewed with the present ISABELLE parameters and examined with regard to longitudinal impedence requirements. The scheme results in an impedance tolerance of Z/n less than or equal to 30 Ω compared to Z/n less than or equal to 5 Ω obtained for rf stacking. However, to meet the claimed luminosity, the AGS performance demands are increased above those assumed in the ISABELLE proposal

  15. National Spherical Torus Experiment (NSTX) Center Stack Upgrade

    International Nuclear Information System (INIS)

    Neumeyer, C.; Avasarala, S.; Chrzanowski, J.; Dudek, L.; Fan, H.; Hatcher, H.; Heitzenroeder, P.; Menard, J.; Ono, M.; Ramakrishnan, S.; Titus, P.; Woolley, R.; Zhan, H.

    2009-01-01

    The purpose of the NSTX Center Stack Upgrade project is to expand the NSTX operational space and thereby the physics basis for next-step ST facilities. The plasma aspect ratio (ratio of plasma major to minor radius) of the upgrade is increased to 1.5 from the original value of 1.26, which increases the cross sectional area of the center stack by a factor of ∼ 3 and makes possible higher levels of performance and pulse duration.

  16. LOFT diesel generator ''A'' exhaust stack seismic analysis

    International Nuclear Information System (INIS)

    Blandford, R.K.

    1978-01-01

    A stress analysis of the LOFT Diesel Generator ''A'' Exhaust Stack was performed to determine its reaction to Safe-Shutdown Earthquake loads. The exhaust stack silencer and supporting foundation was found to be inadequate for the postulated seismic accelerations. Lateral support is required to prevent overturning of the silencer pedestal and reinforcement of the 4'' x 0.5'' silencer base straps is necessary. Basic requirements for this additional support are discussed

  17. Measurements of proton energy spectra using a radiochromic film stack

    Science.gov (United States)

    Filkins, T. M.; Steidle, Jessica; Ellison, D. M.; Steidle, Jeffrey; Freeman, C. G.; Padalino, S. J.; Fiksel, G.; Regan, S. P.; Sangster, T. C.

    2014-10-01

    The energy spectrum of protons accelerated from the rear-side of a thin foil illuminated with ultra-intense laser light from the OMEGA EP laser system at the University of Rochester's Laboratory for Laser Energetics (LLE) was measured using a stack of radiochromic film (RCF). The film stack consisted of four layers of Gafchromic HD-V2 film and four layers of Gafchromic MD-V2-55 film. Aluminum foils of various thicknesses were placed between each piece of RCF in the stack. This arrangement allowed protons with energies of 30 MeV to reach the back layer of RCF in the stack. The stack was placed in the detector plane of a Thomson parabola ion energy (TPIE) spectrometer. Each piece of film in the stack was scanned using a commercially available flat-bed scanner (Epson 10000XL). The resulting optical density was converted into proton fluence using an absolute calibration of the RCF obtained at the SUNY Geneseo 1.7 MV Pelletron accelerator laboratory. In these calibration measurements, the sensitivity of the radiochromic film was measured using monoenergetic protons produced by the accelerator. Details of the analysis procedure and the resulting proton energy spectra will be presented. Funded in part by a grant from the DOE through the Laboratory for Laser Energetics.

  18. New approach for dynamic flow management within the PEMFC stack

    International Nuclear Information System (INIS)

    Varlam, Mihai; Culcer, Mihai; Carcadea, Elena; Stefanescu, Ioan; Iliescu, Mariana; Enache, Adrian

    2009-01-01

    An adequate gas and water flow management is a key issue to reach and maintain a higher output power for a PEM fuel cell stack. One of the main aspects which could limit the performance of a PEM fuel cell stack is the weak capability for a non-uniform water distribution management within the fuel cell. The produced water could become a handicap to attain the best working performance by blocking the catalytic surfaces and by preventing the mass transport process. Usually, the excess water is removed in one cell, comparatively to others from the stack and taking into account that all the cells are supplied in parallel from a common air admission pipe, a limitation of gas flow rate within that cell is created. Consequently, this constraint will reduce further the water removal speed. This feedback process will generate finally a drastic decrease of the fuel cell stack performance. A new practical solution to this water and gas non-uniformity of distributions problem is to use a sequential purge procedure of several fuel cell groups inside the stack which could guarantee a right management of water. An experimental setup has been built based on four fuel cell stack. Every fuel cell was connected to a single removal pipe via a solenoid valve. A computer-controlled hardware and software system has been designed and built, in order to generate a given opening-closing sequence for the automatic valve system. (authors)

  19. Iridium Interfacial Stack - IrIS

    Science.gov (United States)

    Spry, David

    2012-01-01

    Iridium Interfacial Stack (IrIS) is the sputter deposition of high-purity tantalum silicide (TaSi2-400 nm)/platinum (Pt-200 nm)/iridium (Ir-200 nm)/platinum (Pt-200 nm) in an ultra-high vacuum system followed by a 600 C anneal in nitrogen for 30 minutes. IrIS simultaneously acts as both a bond metal and a diffusion barrier. This bondable metallization that also acts as a diffusion barrier can prevent oxygen from air and gold from the wire-bond from infiltrating silicon carbide (SiC) monolithically integrated circuits (ICs) operating above 500 C in air for over 1,000 hours. This TaSi2/Pt/Ir/Pt metallization is easily bonded for electrical connection to off-chip circuitry and does not require extra anneals or masking steps. There are two ways that IrIS can be used in SiC ICs for applications above 500 C: it can be put directly on a SiC ohmic contact metal, such as Ti, or be used as a bond metal residing on top of an interconnect metal. For simplicity, only the use as a bond metal is discussed. The layer thickness ratio of TaSi2 to the first Pt layer deposited thereon should be 2:1. This will allow Si from the TaSi2 to react with the Pt to form Pt2Si during the 600 C anneal carried out after all layers have been deposited. The Ir layer does not readily form a silicide at 600 C, and thereby prevents the Si from migrating into the top-most Pt layer during future anneals and high-temperature IC operation. The second (i.e., top-most) deposited Pt layer needs to be about 200 nm to enable easy wire bonding. The thickness of 200 nm for Ir was chosen for initial experiments; further optimization of the Ir layer thickness may be possible via further experimentation. Ir itself is not easily wire-bonded because of its hardness and much higher melting point than Pt. Below the iridium layer, the TaSi2 and Pt react and form desired Pt2Si during the post-deposition anneal while above the iridium layer remains pure Pt as desired to facilitate easy and strong wire-bonding to the Si

  20. Direct evaluation of electrical dipole moment and oxygen density ratio at high-k dielectrics/SiO2 interface by X-ray photoelectron spectroscopy analysis

    Science.gov (United States)

    Fujimura, Nobuyuki; Ohta, Akio; Ikeda, Mitsuhisa; Makihara, Katsunori; Miyazaki, Seiichi

    2018-04-01

    The electrical dipole moment at an ultrathin high-k (HfO2, Al2O3, TiO2, Y2O3, and SrO)/SiO2 interface and its correlation with the oxygen density ratio at the interface have been directly evaluated by X-ray photoelectron spectroscopy (XPS) under monochromatized Al Kα radiation. The electrical dipole moment at the high-k/SiO2 interface has been measured from the change in the cut-off energy of secondary photoelectrons. Moreover, the oxygen density ratio at the interface between high-k and SiO2 has been estimated from cation core-line signals, such as Hf 4f, Al 2p, Y 3d, Ti 2p, Sr 3d, and Si 2p. We have experimentally clarified the relationship between the measured electrical dipole moment and the oxygen density ratio at the high-k/SiO2 interface.

  1. Implementation of an IMU Aided Image Stacking Algorithm in a Digital Camera for Unmanned Aerial Vehicles.

    Science.gov (United States)

    Audi, Ahmad; Pierrot-Deseilligny, Marc; Meynard, Christophe; Thom, Christian

    2017-07-18

    Images acquired with a long exposure time using a camera embedded on UAVs (Unmanned Aerial Vehicles) exhibit motion blur due to the erratic movements of the UAV. The aim of the present work is to be able to acquire several images with a short exposure time and use an image processing algorithm to produce a stacked image with an equivalent long exposure time. Our method is based on the feature point image registration technique. The algorithm is implemented on the light-weight IGN (Institut national de l'information géographique) camera, which has an IMU (Inertial Measurement Unit) sensor and an SoC (System on Chip)/FPGA (Field-Programmable Gate Array). To obtain the correct parameters for the resampling of the images, the proposed method accurately estimates the geometrical transformation between the first and the N -th images. Feature points are detected in the first image using the FAST (Features from Accelerated Segment Test) detector, then homologous points on other images are obtained by template matching using an initial position benefiting greatly from the presence of the IMU sensor. The SoC/FPGA in the camera is used to speed up some parts of the algorithm in order to achieve real-time performance as our ultimate objective is to exclusively write the resulting image to save bandwidth on the storage device. The paper includes a detailed description of the implemented algorithm, resource usage summary, resulting processing time, resulting images and block diagrams of the described architecture. The resulting stacked image obtained for real surveys does not seem visually impaired. An interesting by-product of this algorithm is the 3D rotation estimated by a photogrammetric method between poses, which can be used to recalibrate in real time the gyrometers of the IMU. Timing results demonstrate that the image resampling part of this algorithm is the most demanding processing task and should also be accelerated in the FPGA in future work.

  2. Implementation of an IMU Aided Image Stacking Algorithm in a Digital Camera for Unmanned Aerial Vehicles

    Directory of Open Access Journals (Sweden)

    Ahmad Audi

    2017-07-01

    Full Text Available Images acquired with a long exposure time using a camera embedded on UAVs (Unmanned Aerial Vehicles exhibit motion blur due to the erratic movements of the UAV. The aim of the present work is to be able to acquire several images with a short exposure time and use an image processing algorithm to produce a stacked image with an equivalent long exposure time. Our method is based on the feature point image registration technique. The algorithm is implemented on the light-weight IGN (Institut national de l’information géographique camera, which has an IMU (Inertial Measurement Unit sensor and an SoC (System on Chip/FPGA (Field-Programmable Gate Array. To obtain the correct parameters for the resampling of the images, the proposed method accurately estimates the geometrical transformation between the first and the N-th images. Feature points are detected in the first image using the FAST (Features from Accelerated Segment Test detector, then homologous points on other images are obtained by template matching using an initial position benefiting greatly from the presence of the IMU sensor. The SoC/FPGA in the camera is used to speed up some parts of the algorithm in order to achieve real-time performance as our ultimate objective is to exclusively write the resulting image to save bandwidth on the storage device. The paper includes a detailed description of the implemented algorithm, resource usage summary, resulting processing time, resulting images and block diagrams of the described architecture. The resulting stacked image obtained for real surveys does not seem visually impaired. An interesting by-product of this algorithm is the 3D rotation estimated by a photogrammetric method between poses, which can be used to recalibrate in real time the gyrometers of the IMU. Timing results demonstrate that the image resampling part of this algorithm is the most demanding processing task and should also be accelerated in the FPGA in future work.

  3. Surface Preparation and Deposited Gate Oxides for Gallium Nitride Based Metal Oxide Semiconductor Devices

    Directory of Open Access Journals (Sweden)

    Paul C. McIntyre

    2012-07-01

    Full Text Available The literature on polar Gallium Nitride (GaN surfaces, surface treatments and gate dielectrics relevant to metal oxide semiconductor devices is reviewed. The significance of the GaN growth technique and growth parameters on the properties of GaN epilayers, the ability to modify GaN surface properties using in situ and ex situ processes and progress on the understanding and performance of GaN metal oxide semiconductor (MOS devices are presented and discussed. Although a reasonably consistent picture is emerging from focused studies on issues covered in each of these topics, future research can achieve a better understanding of the critical oxide-semiconductor interface by probing the connections between these topics. The challenges in analyzing defect concentrations and energies in GaN MOS gate stacks are discussed. Promising gate dielectric deposition techniques such as atomic layer deposition, which is already accepted by the semiconductor industry for silicon CMOS device fabrication, coupled with more advanced physical and electrical characterization methods will likely accelerate the pace of learning required to develop future GaN-based MOS technology.

  4. Getting started with FortiGate

    CERN Document Server

    Fabbri, Rosato

    2013-01-01

    This book is a step-by-step tutorial that will teach you everything you need to know about the deployment and management of FortiGate, including high availability, complex routing, various kinds of VPN working, user authentication, security rules and controls on applications, and mail and Internet access.This book is intended for network administrators, security managers, and IT pros. It is a great starting point if you have to administer or configure a FortiGate unit, especially if you have no previous experience. For people that have never managed a FortiGate unit, the book helpfully walks t

  5. Optimizing the Gating System for Steel Castings

    Directory of Open Access Journals (Sweden)

    Jan Jezierski

    2018-04-01

    Full Text Available The article presents the attempt to optimize a gating system to produce cast steel castings. It is based on John Campbell’s theory and presents the original results of computer modelling of typical and optimized gating systems for cast steel castings. The current state-of-the-art in cast steel casting foundry was compared with several proposals of optimization. The aim was to find a compromise between the best, theoretically proven gating system version, and a version that would be affordable in industrial conditions. The results show that it is possible to achieve a uniform and slow pouring process even for heavy castings to preserve their internal quality.

  6. Gate A: changes to opening hours

    CERN Multimedia

    2015-01-01

    Due to maintenance work, the opening hours of Gate A (near Reception) will be modified between Monday, 13 and Friday, 17 April 2015.   During this period, the gate will be open to vehicles between 7 a.m. and 9.30 a.m., then between 4.30 p.m. and 7 p.m. It will be completely closed to traffic between 9.30 a.m. and 4.30 p.m. Pedestrians and cyclists may continue to use the gate. We apologise for any inconvenience and thank you for your understanding.

  7. Calibration of submerged multi-sluice gates

    Directory of Open Access Journals (Sweden)

    Mohamed F. Sauida

    2014-09-01

    The main objective of this work is to study experimentally and verify empirically the different parameters affecting the discharge through submerged multiple sluice gates (i.e., the expansion ratios, gates operational management, etc.. Using multiple regression analysis of the experimental results, a general equation for discharge coefficient is developed. The results show, that the increase in the expansion ratio and the asymmetric operation of gates, give higher values for the discharge coefficient. The obtained predictions of the discharge coefficient using the developed equations are compared to the experimental data. The present developed equations showed good consistency and high accuracy.

  8. Semiconductor growth on an oxide using a metallic surfactant and interface studies for potential gate stacks from first principles

    Energy Technology Data Exchange (ETDEWEB)

    Reyes Huamantinco, Andrei

    2008-05-09

    In this work the epitaxial growth of germanium on SrHfO{sub 3}(001), and the La{sub 2}Hf{sub 2}O{sub 7}/Si(001) and SrTiO{sub 3}/GaAs(001) interfaces were studied theoretically using the Projector-Augmented Wave (PAW) method. The PAW method is based on Density Functional Theory and it is implemented in the Car-Parrinello Ab-Initio Molecular Dynamics. The goal of the germanium growth on SrHfO{sub 3}(001) is to form a germanium film with low density of defects and smooth morphology, to be used as channel in a transistor. The feasibility of using a third material to achieve germanium layer-by-layer growth was investigated. The formation of an ordered strontium film on a SrO-terminated oxide substrate, to be used as template for germanium overgrowth, was studied. Deposition of germanium on the strontium 1ML template results in wetting and thus a change of the growth mode to layer-by-layer. The germanium surface is then passivated and a germanium compound is initially formed with strontium at the surface and interface. The interfacial structure and valence band offsets of the La{sub 2}Hf{sub 2}O{sub 7}/Si(001) crystalline system were studied. The SrTiO{sub 3}/GaAs(001) crystalline interfaces with unpinned Fermi level were investigated. (orig.)

  9. Mechanosensitive gating of Kv channels.

    Directory of Open Access Journals (Sweden)

    Catherine E Morris

    Full Text Available K-selective voltage-gated channels (Kv are multi-conformation bilayer-embedded proteins whose mechanosensitive (MS Popen(V implies that at least one conformational transition requires the restructuring of the channel-bilayer interface. Unlike Morris and colleagues, who attributed MS-Kv responses to a cooperative V-dependent closed-closed expansion↔compaction transition near the open state, Mackinnon and colleagues invoke expansion during a V-independent closed↔open transition. With increasing membrane tension, they suggest, the closed↔open equilibrium constant, L, can increase >100-fold, thereby taking steady-state Popen from 0→1; "exquisite sensitivity to small…mechanical perturbations", they state, makes a Kv "as much a mechanosensitive…as…a voltage-dependent channel". Devised to explain successive gK(V curves in excised patches where tension spontaneously increased until lysis, their L-based model falters in part because of an overlooked IK feature; with recovery from slow inactivation factored in, their g(V datasets are fully explained by the earlier model (a MS V-dependent closed-closed transition, invariant L≥4. An L-based MS-Kv predicts neither known Kv time courses nor the distinctive MS responses of Kv-ILT. It predicts Kv densities (hence gating charge per V-sensor several-fold different from established values. If opening depended on elevated tension (L-based model, standard gK(V operation would be compromised by animal cells' membrane flaccidity. A MS V-dependent transition is, by contrast, unproblematic on all counts. Since these issues bear directly on recent findings that mechanically-modulated Kv channels subtly tune pain-related excitability in peripheral mechanoreceptor neurons we undertook excitability modeling (evoked action potentials. Kvs with MS V-dependent closed-closed transitions produce nuanced mechanically-modulated excitability whereas an L-based MS-Kv yields extreme, possibly excessive

  10. Respiratory gating and multi field technique radiotherapy for esophageal cancer

    International Nuclear Information System (INIS)

    Ohta, Atsushi; Kaidu, Motoki; Tanabe, Satoshi

    2017-01-01

    To investigate the effects of a respiratory gating and multi field technique on the dose-volume histogram (DVH) in radiotherapy for esophageal cancer. Twenty patients who underwent four-dimensional computed tomography for esophageal cancer were included. We retrospectively created the four treatment plans for each patient, with or without the respiratory gating and multi field technique: No gating-2-field, No gating-4-field, Gating-2-field, and Gating-4-field plans. We compared the DVH parameters of the lung and heart in the No gating-2-field plan with the other three plans.Result In the comparison of the parameters in the No gating-2-field plan, there are significant differences in the Lung V 5Gy , V 20Gy , mean dose with all three plans and the Heart V 25Gy -V 40Gy with Gating-2-field plan, V 35Gy , V 40Gy , mean dose with No Gating-4-field plan and V 30Gy -V 40Gy , and mean dose with Gating-4-field plan. The lung parameters were smaller in the Gating-2-field plan and larger in the No gating-4-field and Gating-4-field plans. The heart parameters were all larger in the No gating-2-field plan. The lung parameters were reduced by the respiratory gating technique and increased by the multi field technique. The heart parameters were reduced by both techniques. It is important to select the optimal technique according to the risk of complications. (author)

  11. 2010 ARRA Lidar: Golden Gate (CA)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — The Golden Gate LiDAR Project is a cooperative project sponsored by the US Geological Survey (USGS) and San Francisco State University (SFSU) that has resulted in...

  12. Synthesizing biomolecule-based Boolean logic gates.

    Science.gov (United States)

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2013-02-15

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, and hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications.

  13. Extending Double Optical Gating to the Midinfrared

    Science.gov (United States)

    Gorman, Timothy; Camper, Antoine; Agostini, Pierre; Dimauro, Louis

    2015-05-01

    In the past decade there has been great interest in creating broadband isolated attosecond pulses (IAPs). Primarily these IAPs have been generated using Ti:Sapphire 800nm short pulses, namely through spatiotemporal gating with the attosecond lighthouse technique, amplitude gating, polarization gating, and double optical gating (DOG). Here we present theoretical calculations and experimental investigations into extending DOG to using a 2 μm driving wavelength, the benefits of which include extended harmonic cutoff and longer input driving pulse durations. It is proposed that broadband IAPs with cutoffs extending up to 250 eV can be generated in Argon by using >30 fs pulses from the passively-CEP stabilized 2 μm idler out of an optical parametric amplifier combined with a collinear DOG experimental setup.

  14. Golden Gate and Pt. Reyes Acoustic Detections

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This dataset contains detections of acoustic tagged fish from two general locations: Golden Gate (east and west line) and Pt. Reyes. Several Vemco 69khz acoustic...

  15. Synthesizing Biomolecule-based Boolean Logic Gates

    Science.gov (United States)

    Miyamoto, Takafumi; Razavi, Shiva; DeRose, Robert; Inoue, Takanari

    2012-01-01

    One fascinating recent avenue of study in the field of synthetic biology is the creation of biomolecule-based computers. The main components of a computing device consist of an arithmetic logic unit, the control unit, memory, and the input and output devices. Boolean logic gates are at the core of the operational machinery of these parts, hence to make biocomputers a reality, biomolecular logic gates become a necessity. Indeed, with the advent of more sophisticated biological tools, both nucleic acid- and protein-based logic systems have been generated. These devices function in the context of either test tubes or living cells and yield highly specific outputs given a set of inputs. In this review, we discuss various types of biomolecular logic gates that have been synthesized, with particular emphasis on recent developments that promise increased complexity of logic gate circuitry, improved computational speed, and potential clinical applications. PMID:23526588

  16. Active gated imaging in driver assistance system

    Science.gov (United States)

    Grauer, Yoav

    2014-04-01

    In this paper, we shall present the active gated imaging system (AGIS) in relation to the automotive field. AGIS is based on a fast-gated camera and pulsed illuminator, synchronized in the time domain to record images of a certain range of interest. A dedicated gated CMOS imager sensor and near infra-red (NIR) pulsed laser illuminator, is presented in this paper to provide active gated technology. In recent years, we have developed these key components and learned the system parameters, which are most beneficial to nighttime (in all weather conditions) driving in terms of field of view, illumination profile, resolution, and processing power. We shall present our approach of a camera-based advanced driver assistance systems (ADAS) named BrightEye™, which makes use of the AGIS technology in the automotive field.

  17. Thermal stress analysis of a planar SOFC stack

    Science.gov (United States)

    Lin, Chih-Kuang; Chen, Tsung-Ting; Chyou, Yau-Pin; Chiang, Lieh-Kwang

    The aim of this study is, by using finite element analysis (FEA), to characterize the thermal stress distribution in a planar solid oxide fuel cell (SOFC) stack during various stages. The temperature profiles generated by an integrated thermo-electrochemical model were applied to calculate the thermal stress distributions in a multiple-cell SOFC stack by using a three-dimensional (3D) FEA model. The constructed 3D FEA model consists of the complete components used in a practical SOFC stack, including positive electrode-electrolyte-negative electrode (PEN) assembly, interconnect, nickel mesh, and gas-tight glass-ceramic seals. Incorporation of the glass-ceramic sealant, which was never considered in previous studies, into the 3D FEA model would produce more realistic results in thermal stress analysis and enhance the reliability of predicting potential failure locations in an SOFC stack. The effects of stack support condition, viscous behavior of the glass-ceramic sealant, temperature gradient, and thermal expansion mismatch between components were characterized. Modeling results indicated that a change in the support condition at the bottom frame of the SOFC stack would not cause significant changes in thermal stress distribution. Thermal stress distribution did not differ significantly in each unit cell of the multiple-cell stack due to a comparable in-plane temperature profile. By considering the viscous characteristics of the glass-ceramic sealant at temperatures above the glass-transition temperature, relaxation of thermal stresses in the PEN was predicted. The thermal expansion behavior of the metallic interconnect/frame had a greater influence on the thermal stress distribution in the PEN than did that of the glass-ceramic sealant due to the domination of interconnect/frame in the volume of a planar SOFC assembly.

  18. Dual-gated volumetric modulated arc therapy

    International Nuclear Information System (INIS)

    Fahimian, Benjamin; Wu, Junqing; Wu, Huanmei; Geneser, Sarah; Xing, Lei

    2014-01-01

    Gated Volumetric Modulated Arc Therapy (VMAT) is an emerging radiation therapy modality for treatment of tumors affected by respiratory motion. However, gating significantly prolongs the treatment time, as delivery is only activated during a single respiratory phase. To enhance the efficiency of gated VMAT delivery, a novel dual-gated VMAT (DG-VMAT) technique, in which delivery is executed at both exhale and inhale phases in a given arc rotation, is developed and experimentally evaluated. Arc delivery at two phases is realized by sequentially interleaving control points consisting of MUs, MLC sequences, and angles of VMAT plans generated at the exhale and inhale phases. Dual-gated delivery is initiated when a respiration gating signal enters the exhale window; when the exhale delivery concludes, the beam turns off and the gantry rolls back to the starting position for the inhale window. The process is then repeated until both inhale and exhale arcs are fully delivered. DG-VMAT plan delivery accuracy was assessed using a pinpoint chamber and diode array phantom undergoing programmed motion. DG-VMAT delivery was experimentally implemented through custom XML scripting in Varian’s TrueBeam™ STx Developer Mode. Relative to single gated delivery at exhale, the treatment time was improved by 95.5% for a sinusoidal breathing pattern. The pinpoint chamber dose measurement agreed with the calculated dose within 0.7%. For the DG-VMAT delivery, 97.5% of the diode array measurements passed the 3%/3 mm gamma criterion. The feasibility of DG-VMAT delivery scheme has been experimentally demonstrated for the first time. By leveraging the stability and natural pauses that occur at end-inspiration and end-exhalation, DG-VMAT provides a practical method for enhancing gated delivery efficiency by up to a factor of two

  19. Crystalline silicotitanate gate review analysis

    International Nuclear Information System (INIS)

    Schlahta, S.N.; Carreon, R.; Gentilucci, J.A.

    1997-11-01

    Crystalline silicotitanate (CST) is an ion-exchange method for removing radioactive cesium from tank waste to allow the separation of the waste into high- and low-level fractions. The CST, originally developed Sandia National Laboratories personnel in association with Union Oil Products Corporation, has both a high affinity and selectivity for sorbing cesium-137 from highly alkaline or acidic solutions. For several years now, the U.S. Department of Energy has funded work to investigate applying CST to large-scale removal of cesium-137 from radioactive tank wastes. In January 1997, an expert panel sponsored by the Tanks Focus Area met to review the current state of the technology and to determine whether it was ready for routine use. The review also sought to identify any technical issues that must be resolved or additional CST development that must occur before full implementation by end-users. The CST Gate Review Group concluded that sufficient work has been done to close developmental work on CST and turn the remaining site-specific tasks over to the users. This report documents the review group''s findings, issues, concerns, and recommendations as well as responses from the Tanks Focus Area expert staff to specific pretreatment and immobilization issues

  20. VKCDB: Voltage-gated potassium channel database

    Directory of Open Access Journals (Sweden)

    Gallin Warren J

    2004-01-01

    Full Text Available Abstract Background The family of voltage-gated potassium channels comprises a functionally diverse group of membrane proteins. They help maintain and regulate the potassium ion-based component of the membrane potential and are thus central to many critical physiological processes. VKCDB (Voltage-gated potassium [K] Channel DataBase is a database of structural and functional data on these channels. It is designed as a resource for research on the molecular basis of voltage-gated potassium channel function. Description Voltage-gated potassium channel sequences were identified by using BLASTP to search GENBANK and SWISSPROT. Annotations for all voltage-gated potassium channels were selectively parsed and integrated into VKCDB. Electrophysiological and pharmacological data for the channels were collected from published journal articles. Transmembrane domain predictions by TMHMM and PHD are included for each VKCDB entry. Multiple sequence alignments of conserved domains of channels of the four Kv families and the KCNQ family are also included. Currently VKCDB contains 346 channel entries. It can be browsed and searched using a set of functionally relevant categories. Protein sequences can also be searched using a local BLAST engine. Conclusions VKCDB is a resource for comparative studies of voltage-gated potassium channels. The methods used to construct VKCDB are general; they can be used to create specialized databases for other protein families. VKCDB is accessible at http://vkcdb.biology.ualberta.ca.

  1. Maturing of SOFC cell and stack production technology and preparation for demonstration of SOFC stacks. Part 2

    Energy Technology Data Exchange (ETDEWEB)

    2006-07-01

    The TOFC/Riso pilot plant production facility for the manufacture of anode-supported cells has been further up-scaled with an automated continuous spraying process and an extra sintering capacity resulting in production capacity exceeding 15,000 standard cells (12x12 cm2) in 2006 with a success rate of about 85% in the cell production. All processing steps such as tape-casting, spraying, screen-printing and atmospheric air sintering in the cell production have been selected on condition that up-scaling and cost effective, flexible, industrial mass production are feasible. The standard cell size is currently being increased to 18x18 cm2, and 150 cells of this size have been produced in 2006 for our further stack development. To improve quality and lower production cost, a new screen printing line is under establishment. TOFC's stack design is an ultra compact multilayer assembly of cells (including contact layers), metallic interconnects, spacer frames and glass seals. The compactness ensures minimized material consumption and low cost. Standard stacks with cross flow configuration contains 75 cells (12x12cm2) delivering about 1.2 kW at optimal operation conditions with pre-reformed NG as fuel. Stable performance has been demonstrated for 500-1000 hours. Significantly improved materials, especially concerning the metallic interconnect and the coatings have been introduced during the last year. Small stacks (5-10 cells) exhibit no detectable stack degradation using our latest cells and stack materials during test periods of 500-1000 hours. Larger stacks (50-75 cells) suffer from mal-distribution of gas and air inside the stacks, gas leakage, gas cross-over, pressure drop, and a certain loss of internal electrical contact during operation cycles. Measures have been taken to find solutions during the following development work. The stack production facilities have been improved and up-scaled. In 2006, 5 standard stacks have been assembled and burned in based on

  2. An experimental investigation into the deployment of 3-D, finned wing and shape memory alloy vortex generators in a forced air convection heat pipe fin stack

    International Nuclear Information System (INIS)

    Aris, M.S.; McGlen, R.; Owen, I.; Sutcliffe, C.J.

    2011-01-01

    Forced air convection heat pipe cooling systems play an essential role in the thermal management of electronic and power electronic devices such as microprocessors and IGBT's (Integrated Gate Bipolar Transistors). With increasing heat dissipation from these devices, novel methods of improving the thermal performance of fin stacks attached to the heat pipe condenser section are required. The current work investigates the use of a wing type surface protrusions in the form of 3-D delta wing tabs adhered to the fin surface, thin wings punched-out of the fin material and TiNi shape memory alloy delta wings which changed their angles of attack based on the fin surface temperature. The longitudinal vortices generated from the wing designs induce secondary mixing of the cooler free stream air entering the fin stack with the warmer fluid close to the fin surfaces. The change in angle of the attack of the active delta wings provide heat transfer enhancement while managing flow pressure losses across the fin stack. A heat transfer enhancement of 37% compared to a plain fin stack was obtained from the 3-D tabs in a staggered arrangement. The punched-out delta wings in the staggered and inline arrangements provided enhancements of 30% and 26% respectively. Enhancements from the active delta wings were lower at 16%. However, as these devices reduce the pressure drop through the fin stack by approximately 19% in the de-activate position, over the activated position, a reduction in fan operating cost may be achieved for systems operating with inlet air temperatures below the maximum inlet temperature specification for the device. CFD analysis was also carried out to provide additional detail of the local heat transfer enhancement effects. The CFD results corresponded well with previously published reports and were consistent with the experimental findings. - Highlights: → Heat transfer enhancements of heat pipe fin stacks was successfully achieved using fixed and active delta

  3. Polaron-electron assisted giant dielectric dispersion in SrZrO{sub 3} high-k dielectric

    Energy Technology Data Exchange (ETDEWEB)

    Borkar, Hitesh; Barvat, Arun; Pal, Prabir; Kumar, Ashok, E-mail: ashok553@nplindia.org [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Shukla, A. K. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Pulikkotil, J. J. [CSIR-National Physical Laboratory, Dr. K. S. Krishnan Marg, New Delhi 110012 (India); Academy of Scientific and Innovative Research (AcSIR), CSIR-National Physical Laboratory (CSIR-NPL) Campus, Dr. K S Krishnan Marg, New Delhi 110012 (India); Computation and Networking Facility, CSIR-National Physical Laboratory, New Delhi 110012 (India)

    2016-06-07

    The SrZrO{sub 3} is a well known high-k dielectric constant (∼22) and high optical bandgap (∼5.8 eV) material and one of the potential candidates for future generation nanoelectronic logic elements (8 nm node technology) beyond silicon. Its dielectric behavior is fairly robust and frequency independent till 470 K; however, it suffers a strong small-polaron based electronic phase transition (T{sub e}) linking 650 to 750 K. The impedance spectroscopy measurements revealed the presence of conducting grains and grain boundaries at elevated temperature which provide energetic mobile charge carriers with activation energy in the range of 0.7 to 1.2 eV supporting the oxygen ions and proton conduction. X-ray photoemission spectroscopy measurements suggest the presence of weak non-stoichiometric O{sup 2−} anions and hydroxyl species bound to different sites at the surface and bulk. These thermally activated charge carriers at elevated temperature significantly contribute to the polaronic based dielectric anomaly and conductivity. Our dielectric anomaly supports pseudo phase transition due to high degree of change in ZrO{sub 6} octahedral angle in the temperature range of 650–750 K, where electron density and phonon vibration affect the dielectric and conductivity properties.

  4. Transfer-Free Fabrication of Graphene Scaffolds on High-k Dielectrics from Metal-Organic Oligomers.

    Science.gov (United States)

    Pang, Qingqing; Wang, Deyan; Wang, Xiuyan; Feng, Shaoguang; Clark, Michael B; Li, Qiaowei

    2016-09-28

    In situ fabrication of graphene scaffold-ZrO2 nanofilms is achieved by thermal annealing of Zr-based metal-organic oligomers on SiO2 substrates. The structural similarities of the aromatic moieties in the ligand (phenyl-, naphthyl-, anthryl-, and pyrenyl-) compared to graphene play a major role in the ordering of the graphene scaffolds obtained. The depth profiling analysis reveals ultrathin carbon-pure or carbon-rich surfaces of the graphene scaffold-ZrO2 nanofilms. The graphene scaffolds with ∼96.0% transmittance in the visible region and 4.8 nm in thickness can be grown with this non-chemical vapor deposition method. Furthermore, the heterogeneous graphene scaffold-ZrO2 nanofilms show a low sheet resistance of 17.0 kΩ per square, corresponding to electrical conductivity of 3197 S m(-1). The strategy provides a facile method to fabricate graphene scaffolds directly on high-k dielectrics without transferring process, paving the way for its application in fabricating electronic devices.

  5. Capacitance-voltage analysis of electrical properties for WSe2 field effect transistors with high-k encapsulation layer

    Science.gov (United States)

    Ko, Seung-Pil; Shin, Jong Mok; Jang, Ho Kyun; You, Min Youl; Jin, Jun-Eon; Choi, Miri; Cho, Jiung; Kim, Gyu-Tae

    2018-02-01

    Doping effects in devices based on two-dimensional (2D) materials have been widely studied. However, detailed analysis and the mechanism of the doping effect caused by encapsulation layers has not been sufficiently explored. In this work, we present experimental studies on the n-doping effect in WSe2 field effect transistors (FETs) with a high-k encapsulation layer (Al2O3) grown by atomic layer deposition. In addition, we demonstrate the mechanism and origin of the doping effect. After encapsulation of the Al2O3 layer, the threshold voltage of the WSe2 FET negatively shifted with the increase of the on-current. The capacitance-voltage measurements of the metal insulator semiconductor (MIS) structure proved the presence of the positive fixed charges within the Al2O3 layer. The flat-band voltage of the MIS structure of Au/Al2O3/SiO2/Si was shifted toward the negative direction on account of the positive fixed charges in the Al2O3 layer. Our results clearly revealed that the fixed charges in the Al2O3 encapsulation layer modulated the Fermi energy level via the field effect. Moreover, these results possibly provide fundamental ideas and guidelines to design 2D materials FETs with high-performance and reliability.

  6. Conduction band-edge d-states in high-k dielectrics due to Jahn-Teller term splittings

    International Nuclear Information System (INIS)

    Lucovsky, G.; Fulton, C.C.; Zhang, Y.; Luning, J.; Edge, L.; Whitten, J.L.; Nemanich, R.J.; Schlom, D.G.; Afanase'v, V.V.

    2005-01-01

    X-ray absorption spectroscopy (XAS) is used to study conduction band edge electronic structure of high-k transition metal (TM) and trivalent lanthanide series rare earth (RE) oxide dielectrics. Empty TM/RE d-states are studied by intra-atomic transitions originating in core level spin-orbit split p-states, and conduction band states are studied in inter-atomic transitions which originate in the oxygen atom 1s core level state. In non-crystalline Zr and Hf silicate alloys, the local bonding symmetry, or crystal field splits these d-states into doubly and triply degenerate features. In nano-crystalline oxides, there are additional d-state splittings due to contributions of more distant neighbors that completely remove d-state degeneracies via the Jahn-Teller effect mechanism. This gives rise to highly localized band edge states that are electronically active in photoconductivity, internal photoemission, and act as bulk traps in metal oxide semiconductor (MOS) devices

  7. Respiratory gating in positron emission tomography: A quantitative comparison of different gating schemes

    International Nuclear Information System (INIS)

    Dawood, Mohammad; Buether, Florian; Lang, Norbert; Schober, Otmar; Schaefers, Klaus P

    2007-01-01

    Respiratory gating is used for reducing the effects of breathing motion in a wide range of applications from radiotherapy treatment to diagnostical imaging. Different methods are feasible for respiratory gating. In this study seven gating methods were developed and tested on positron emission tomography (PET) listmode data. The results of seven patient studies were compared quantitatively with respect to motion and noise. (1) Equal and (2) variable time-based gating methods use only the time information of the breathing cycle to define respiratory gates. (3) Equal and (4) variable amplitude-based gating approaches utilize the amplitude of the respiratory signal. (5) Cycle-based amplitude gating is a combination of time and amplitude-based techniques. A baseline correction was applied to methods (3) and (4) resulting in two new approaches: Baseline corrected (6) equal and (7) variable amplitude-based gating. Listmode PET data from seven patients were acquired together with a respiratory signal. Images were reconstructed applying the seven gating methods. Two parameters were used to quantify the results: Motion was measured as the displacement of the heart due to respiration and noise was defined as the standard deviation of pixel intensities in a background region. The amplitude-based approaches (3) and (4) were superior to the time-based methods (1) and (2). The improvement in capturing the motion was more than 30% (up to 130%) in all subjects. The variable time (2) and amplitude (4) methods had a more uniform noise distribution among all respiratory gates compared to equal time (1) and amplitude (3) methods. Baseline correction did not improve the results. Out of seven different respiratory gating approaches, the variable amplitude method (4) captures the respiratory motion best while keeping a constant noise level among all respiratory phases

  8. Validation of a HT-PEMFC stack for CHP applications

    Energy Technology Data Exchange (ETDEWEB)

    Pasupathi, S.; Ulleberg, Oe. [Western Cape Univ. (South Africa). HySA Systems, SAIAMC; Bujlo, P. [Western Cape Univ. (South Africa). HySA Systems, SAIAMC; Electrotechnical Institute Wroclaw Division (Poland); Scholta, J. [Centre for Solar Energy and Hydrogen Research (ZSW) (Germany)

    2010-07-01

    Fuel cell systems are very attractive for stationary co-generation applications as they can produce heat and electricity efficiently in a decentralized and environmentally friendly manner. PEMFC stacks operating at temperatures above 120 C, specifically in the range of 140-180 C, are ideal for co-generation purposes. In this study, preliminary results from a HTPEMFC stack designed for CHP applications is presented and discussed. A short, five-cell, HT-PEMFC stack was assembled with Celtec- P-2100 MEAs and validated in terms of electrical performance. The stack was operated with hydrogen and air at 160 C and the utilization curves for anode and cathode were recorded for a wide range of gas utilization at a current density of 0.52 A/cm{sup 2}. The current voltage characteristic was measured at optimal utilization values at 160 C. A 1kW stack is assembled and is currently being validated for its performance under various operating conditions for use in CHP applications. (orig.)

  9. Optimization of hole generation in Ti/CFRP stacks

    Science.gov (United States)

    Ivanov, Y. N.; Pashkov, A. E.; Chashhin, N. S.

    2018-03-01

    The article aims to describe methods for improving the surface quality and hole accuracy in Ti/CFRP stacks by optimizing cutting methods and drill geometry. The research is based on the fundamentals of machine building, theory of probability, mathematical statistics, and experiment planning and manufacturing process optimization theories. Statistical processing of experiment data was carried out by means of Statistica 6 and Microsoft Excel 2010. Surface geometry in Ti stacks was analyzed using a Taylor Hobson Form Talysurf i200 Series Profilometer, and in CFRP stacks - using a Bruker ContourGT-Kl Optical Microscope. Hole shapes and sizes were analyzed using a Carl Zeiss CONTURA G2 Measuring machine, temperatures in cutting zones were recorded with a FLIR SC7000 Series Infrared Camera. Models of multivariate analysis of variance were developed. They show effects of drilling modes on surface quality and accuracy of holes in Ti/CFRP stacks. The task of multicriteria drilling process optimization was solved. Optimal cutting technologies which improve performance were developed. Methods for assessing thermal tool and material expansion effects on the accuracy of holes in Ti/CFRP/Ti stacks were developed.

  10. Effect of flow parameters on flare stack generator noise

    International Nuclear Information System (INIS)

    Dinn, T.S.

    1998-01-01

    The SoundPLAN Computer Noise Model was used to determine the general effect of flare noise in a community adjacent to a petrochemical plant. Tests were conducted to determine the effect of process flow conditions and the pulsating flame on the flare stack generator noise from both a refinery flare and process flare. Flaring under normal plant operations, the flaring of fuel gas and the flaring of hydrogen were the three conditions that were tested. It was shown that the steam flow rate was the determining factor in the flare stack generated noise. Variations in the water seal level in the flare line surge tank increased or decreased the gas flowrate, which resulted in a pulsating flame. The period and amplitude of the pulsating noise from the flare stacks was determined by measuring several parameters. Flare stack noise oscillations were found to be greater for the process flare than for the refinery flare stack. It was suggested that minimizing the amount of steam fed to the flare and improving the burner design would minimize noise. 2 tabs., 6 figs

  11. Charge transfer in pi-stacked systems including DNA

    International Nuclear Information System (INIS)

    Siebbeles, L.D.A.

    2003-01-01

    Charge migration in DNA is a subject of intense current study motivated by long-range detection of DNA damage and the potential application of DNA as a molecular wire in nanoscale electronic devices. A key structural element, which makes DNA a medium for long-range charge transfer, is the array of stacked base pairs in the interior of the double helix. The overlapping pi-orbitals of the nucleobases provide a pathway for motion of charge carriers generated on the stack. This 'pi-pathway' resembles the columnarly stacked macrocyclic cores in discotic materials such as triphenylenes. The structure of these pi-stacked systems is highly disordered with dynamic fluctuations occurring on picosecond to nanosecond time scales. Theoretical calculations, concerning the effects of structural disorder and nucleobase sequence in DNA, on the dynamics of charge carriers are presented. Electronic couplings and localization energies of charge carriers were calculated using density functional theory (DFT). Results for columnarly stacked triphenylenes and DNA nucleobases are compared. The results are used to provide insight into the factors that control the mobility of charge carriers. Further, experimental results on the site-selective oxidation of guanine nucleobases in DNA (hot spots for DNA damage) are analyzed on basis of the theoretical results

  12. Generalized diffraction-stack migration and filtering of coherent noise

    KAUST Repository

    Zhan, Ge

    2014-01-27

    We reformulate the equation of reverse-time migration so that it can be interpreted as summing data along a series of hyperbola-like curves, each one representing a different type of event such as a reflection or multiple. This is a generalization of the familiar diffraction-stack migration algorithm where the migration image at a point is computed by the sum of trace amplitudes along an appropriate hyperbola-like curve. Instead of summing along the curve associated with the primary reflection, the sum is over all scattering events and so this method is named generalized diffraction-stack migration. This formulation leads to filters that can be applied to the generalized diffraction-stack migration operator to mitigate coherent migration artefacts due to, e.g., crosstalk and aliasing. Results with both synthetic and field data show that generalized diffraction-stack migration images have fewer artefacts than those computed by the standard reverse-time migration algorithm. The main drawback is that generalized diffraction-stack migration is much more memory intensive and I/O limited than the standard reverse-time migration method. © 2014 European Association of Geoscientists & Engineers.

  13. Ion bunch stacking in a Penning trap after purification in an electrostatic mirror trap

    CERN Document Server

    Rosenbusch, M; Blaum, K; Borgmann, Ch; Kreim, S; Lunney, D; Manea, V; Schweikhard, L; Wienholtz, F; Wolf, R N

    2014-01-01

    The success of many measurements in analytical mass spectrometry as well as in precision mass determinations for atomic and nuclear physics is handicapped when the ion sources deliver ``contaminations'', i.e., unwanted ions of masses similar to those of the ions of interest. In particular, in ion-trapping devices, large amounts of contaminant ions result in significant systematic errors-if the measurements are possible at all. We present a solution for such cases: The ions from a quasi-continuous source are bunched in a linear radio-frequency-quadrupole ion trap, separated by a multi-reflection time-of-flight section followed by a Bradbury-Nielsen gate, and then captured in a Penning trap. Buffer-gas cooling is used to damp the ion motion in the latter, which allows a repeated opening of the Penning trap for a stacking of mass-selected ion bunches. Proof-of-principle demonstrations have been performed with the ISOLTRAP setup at ISOLDE/CERN, both with Cs-133(+) ions from an off-line ion source and by applicati...

  14. Method for applying a thin film barrier stack to a device with microstructures, and device provided with such a thin film barrier stack

    NARCIS (Netherlands)

    2005-01-01

    A method for applying a thin film barrier stack to a device with microstructures, such as, for instance, an OLED, wherein the thin film barrier stack forms a barrier to at least moisture and oxygen, wherein the stack is built up from a combination of org. and inorg. layers, characterized in that a

  15. Thermoacoustic design using stem of goose down stack

    Science.gov (United States)

    Farikhah, Irna; Ristanto, Sigit; Idrus, Hadiyati; Kaltsum, Ummi; Faisal, Affandi; Setiawan, Ihsan; Setio Utomo, Agung Bambang

    2012-09-01

    Many refrigerators using CFC as a refrigerant are seen as the cause of the depletion of ozone. Hence, thermoacoustic was chosen as an alternative refrigerator that safe for environment. There are many variable that influenced the optimization of thermoacoustic design. One of them is thermal conductivity of material of stack. The Stack material must have a low thermal conductivity. In this research we used organic stack made of stem of goose down. It has superior thermal insulating. It means that they have the lowest thermal conductivity. The system uses no refrigerant or compressor, and the only mechanical moving part is the loudspeaker connected to a signal generator that produces the acoustic. The working fluid is air and the material of resonator is stainless steel. A series test on the laboratory found that there is a decrease of 5°C in temperature for about 2 minutes.

  16. The operation and monitoring of sewage disposal by stack injection

    Energy Technology Data Exchange (ETDEWEB)

    Jensen, D.A. [Alyeska Pipeline Service Co. (United States)

    1994-12-31

    A system that uses turbine exhaust to evaporate sewage, was described. The Alyeska Pipeline Service developed the system for isolated pump stations located in permafrost areas. The pumps moving the crude oil in the Trans Alaska Pipeline System (TAPS) were driven by simple cycle gas turbine engines which produce large amounts of waste heat. The waste heat was used to evaporate the sewage effluent, effectively destroying all pathogens in it. The process, known as `stack injection`, was recently upgraded to increase efficiency and safety. Stack injection was being used at five pump stations. Methods used to control operation of the stack injection system, and field data used to redesign the system were reviewed. 3 figs., 3 refs.

  17. Multipole Stack for the 800 MeV PS Booster

    CERN Multimedia

    1975-01-01

    The 800 MeV PS Booster had seen first beam in its 4 superposed rings in 1972, routine operation began in 1973. In the strive for ever higher beam intensities, the need for additional multipole lenses became evident. After detailed studies, the manufacture of 8 stacks of multipoles was launched in 1974. Each stack consists of 4 superposed multipoles and each multipole has 4 concentric shells. From the innermost to the outermost shell, Type A contains octupole, skew-octupole, sextupole, skew-sextupole. Type B contains skew-octupole, skew-sextupole, vertical dipole, horizontal dipole. Completion of installation in 1976 opened the way to higher beam intensities. M. Battiaz is seen here with a multipole stack and its many electrical connections.

  18. Fluxons in long and annular intrinsic Josephson junction stacks

    CERN Document Server

    Clauss, T; Moessle, M; Müller, A; Weber, A; Kölle, D; Kleiner, R

    2002-01-01

    A promising approach towards a THz oscillator based on intrinsic Josephson junctions in high-temperature superconductors is based on the collective motion of Josephson fluxons, which are predicted to form various configurations ranging from a triangular to a quadratic lattice. Not only for this reason, but certainly also for the sake of basic physics, several experimental and theoretical investigations have been done on the subject of collective fluxon dynamics in stacked intrinsic Josephson junctions. In this paper we will present some experimental results on the fluxon dynamics of long intrinsic Josephson junction stacks made of Bi sub 2 Sr sub 2 CaCu sub 2 O sub 8. The stacks were formed either in an open or in an annular geometry, and clear resonant fluxon modes were observed. Experiments discussed include measurements of current-voltage characteristics in external magnetic fields and in external microwave fields.

  19. Frictional forces in an SOFC stack with sliding seals

    Energy Technology Data Exchange (ETDEWEB)

    Yamazaki, T; Oishi, N; Namikawa, T; Yamazaki, Y [Tokyo Institute of Technology, Tokyo (Japan)

    1996-06-05

    The detrimental thermal stresses in planar SOFC stacks can be reduced using sliding seals. In the proposal planar stack the electrolyte film is sandwiched by YSZ support rings to release the thermal stresses. In order to estimate the strength of the support ring, the frictional forces between heat resistant alloy and YSZ were measured at 900{degree}C. The coefficient of friction between Hastelloy X and YSZ increased when they were measured lifter 144h heating. However, the coefficient of friction between HA-214 and YSZ did not increase. The measurement and a calculation of the stresses in the support rings led the result that a thickness of 0.6mm was necessary for 200mm diameter support rings under a stack pressure of 0.1kgcm{sup -2}. 6 refs., 9 figs., 1 tab.

  20. The Stack-Size of Combinatorial Tries Revisited

    Directory of Open Access Journals (Sweden)

    Markus E. Nebel

    2002-12-01

    Full Text Available In the present paper we consider a generalized class of extended binary trees in which leaves are distinguished in order to represent the location of a key within a trie of the same structure. We prove an exact asymptotic equivalent to the average stack-size of trees with α internal nodes and β leaves corresponding to keys; we assume that all trees with the same parameters α and β have the same probability. The assumption of that uniform model is motivated for example by the usage of tries for the compression of blockcodes. Furthermore, we will prove asymptotics for the r-th moments of the stack-size and we will show that a normalized stack-size possesses a theta distribution in the limit.